| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 | 100.00 | 100.00 | 100.00 | 100.00 |
| T251 | /workspace/coverage/default/106.prim_prince_test.35822081 | Feb 18 12:36:02 PM PST 24 | Feb 18 12:36:42 PM PST 24 | 1877889285 ps | ||
| T252 | /workspace/coverage/default/19.prim_prince_test.633651363 | Feb 18 12:35:57 PM PST 24 | Feb 18 12:37:17 PM PST 24 | 3740487406 ps | ||
| T253 | /workspace/coverage/default/483.prim_prince_test.109874800 | Feb 18 12:37:17 PM PST 24 | Feb 18 12:38:05 PM PST 24 | 2368367987 ps | ||
| T254 | /workspace/coverage/default/303.prim_prince_test.2733917892 | Feb 18 12:36:29 PM PST 24 | Feb 18 12:37:27 PM PST 24 | 2455827327 ps | ||
| T255 | /workspace/coverage/default/155.prim_prince_test.89712170 | Feb 18 12:36:27 PM PST 24 | Feb 18 12:36:52 PM PST 24 | 1023047768 ps | ||
| T256 | /workspace/coverage/default/310.prim_prince_test.2541449164 | Feb 18 12:36:33 PM PST 24 | Feb 18 12:37:30 PM PST 24 | 2560142298 ps | ||
| T257 | /workspace/coverage/default/441.prim_prince_test.327018217 | Feb 18 12:36:58 PM PST 24 | Feb 18 12:37:17 PM PST 24 | 758253144 ps | ||
| T258 | /workspace/coverage/default/317.prim_prince_test.4115396904 | Feb 18 12:36:35 PM PST 24 | Feb 18 12:37:39 PM PST 24 | 2883488417 ps | ||
| T259 | /workspace/coverage/default/411.prim_prince_test.1512659355 | Feb 18 12:36:50 PM PST 24 | Feb 18 12:37:31 PM PST 24 | 1987542996 ps | ||
| T260 | /workspace/coverage/default/383.prim_prince_test.2895981051 | Feb 18 12:36:43 PM PST 24 | Feb 18 12:37:12 PM PST 24 | 1382108302 ps | ||
| T261 | /workspace/coverage/default/177.prim_prince_test.3903149260 | Feb 18 12:36:20 PM PST 24 | Feb 18 12:37:15 PM PST 24 | 2303068537 ps | ||
| T262 | /workspace/coverage/default/259.prim_prince_test.3443828444 | Feb 18 12:36:28 PM PST 24 | Feb 18 12:36:56 PM PST 24 | 1085851918 ps | ||
| T263 | /workspace/coverage/default/208.prim_prince_test.1744336646 | Feb 18 12:36:15 PM PST 24 | Feb 18 12:36:54 PM PST 24 | 1557074563 ps | ||
| T264 | /workspace/coverage/default/477.prim_prince_test.3221844381 | Feb 18 12:37:15 PM PST 24 | Feb 18 12:37:33 PM PST 24 | 780777310 ps | ||
| T265 | /workspace/coverage/default/330.prim_prince_test.1174100565 | Feb 18 12:36:54 PM PST 24 | Feb 18 12:37:26 PM PST 24 | 1410470390 ps | ||
| T266 | /workspace/coverage/default/266.prim_prince_test.920611708 | Feb 18 12:36:34 PM PST 24 | Feb 18 12:37:33 PM PST 24 | 2736572735 ps | ||
| T267 | /workspace/coverage/default/443.prim_prince_test.2451125567 | Feb 18 12:37:13 PM PST 24 | Feb 18 12:37:40 PM PST 24 | 1216373834 ps | ||
| T268 | /workspace/coverage/default/299.prim_prince_test.3275837203 | Feb 18 12:36:38 PM PST 24 | Feb 18 12:37:51 PM PST 24 | 3656408856 ps | ||
| T269 | /workspace/coverage/default/271.prim_prince_test.1867391788 | Feb 18 12:36:31 PM PST 24 | Feb 18 12:37:37 PM PST 24 | 2849676248 ps | ||
| T270 | /workspace/coverage/default/398.prim_prince_test.4190306054 | Feb 18 12:36:57 PM PST 24 | Feb 18 12:37:27 PM PST 24 | 1296550221 ps | ||
| T271 | /workspace/coverage/default/286.prim_prince_test.576276225 | Feb 18 12:36:36 PM PST 24 | Feb 18 12:37:43 PM PST 24 | 3184876419 ps | ||
| T272 | /workspace/coverage/default/117.prim_prince_test.3301905154 | Feb 18 12:36:10 PM PST 24 | Feb 18 12:37:22 PM PST 24 | 3202455936 ps | ||
| T273 | /workspace/coverage/default/491.prim_prince_test.3292258818 | Feb 18 12:37:17 PM PST 24 | Feb 18 12:37:57 PM PST 24 | 1965190378 ps | ||
| T274 | /workspace/coverage/default/363.prim_prince_test.3473088813 | Feb 18 12:36:41 PM PST 24 | Feb 18 12:37:35 PM PST 24 | 2546973230 ps | ||
| T275 | /workspace/coverage/default/381.prim_prince_test.942732103 | Feb 18 12:36:56 PM PST 24 | Feb 18 12:37:55 PM PST 24 | 2753002999 ps | ||
| T276 | /workspace/coverage/default/28.prim_prince_test.660994375 | Feb 18 12:35:59 PM PST 24 | Feb 18 12:36:36 PM PST 24 | 1613610747 ps | ||
| T277 | /workspace/coverage/default/300.prim_prince_test.2601180068 | Feb 18 12:36:33 PM PST 24 | Feb 18 12:36:56 PM PST 24 | 863207738 ps | ||
| T278 | /workspace/coverage/default/262.prim_prince_test.3945735148 | Feb 18 12:36:34 PM PST 24 | Feb 18 12:37:49 PM PST 24 | 3351160478 ps | ||
| T279 | /workspace/coverage/default/474.prim_prince_test.485692705 | Feb 18 12:37:14 PM PST 24 | Feb 18 12:38:18 PM PST 24 | 3083560572 ps | ||
| T280 | /workspace/coverage/default/335.prim_prince_test.2481419555 | Feb 18 12:36:50 PM PST 24 | Feb 18 12:37:18 PM PST 24 | 1245971237 ps | ||
| T281 | /workspace/coverage/default/57.prim_prince_test.4292082600 | Feb 18 12:36:14 PM PST 24 | Feb 18 12:36:57 PM PST 24 | 1805481737 ps | ||
| T282 | /workspace/coverage/default/91.prim_prince_test.3941928274 | Feb 18 12:36:25 PM PST 24 | Feb 18 12:37:10 PM PST 24 | 1869107570 ps | ||
| T283 | /workspace/coverage/default/297.prim_prince_test.657163972 | Feb 18 12:36:31 PM PST 24 | Feb 18 12:37:05 PM PST 24 | 1416408044 ps | ||
| T284 | /workspace/coverage/default/408.prim_prince_test.4144683814 | Feb 18 12:36:49 PM PST 24 | Feb 18 12:37:48 PM PST 24 | 2794290344 ps | ||
| T285 | /workspace/coverage/default/59.prim_prince_test.2194804883 | Feb 18 12:36:00 PM PST 24 | Feb 18 12:36:20 PM PST 24 | 773053428 ps | ||
| T286 | /workspace/coverage/default/120.prim_prince_test.4093422067 | Feb 18 12:36:17 PM PST 24 | Feb 18 12:37:14 PM PST 24 | 2346897335 ps | ||
| T287 | /workspace/coverage/default/211.prim_prince_test.4151767272 | Feb 18 12:36:25 PM PST 24 | Feb 18 12:36:49 PM PST 24 | 909874771 ps | ||
| T288 | /workspace/coverage/default/486.prim_prince_test.4026237427 | Feb 18 12:37:19 PM PST 24 | Feb 18 12:38:31 PM PST 24 | 3563738701 ps | ||
| T289 | /workspace/coverage/default/469.prim_prince_test.1485535870 | Feb 18 12:37:10 PM PST 24 | Feb 18 12:38:00 PM PST 24 | 2297218830 ps | ||
| T290 | /workspace/coverage/default/34.prim_prince_test.2238891682 | Feb 18 12:35:55 PM PST 24 | Feb 18 12:36:41 PM PST 24 | 2100570602 ps | ||
| T291 | /workspace/coverage/default/401.prim_prince_test.647541319 | Feb 18 12:36:48 PM PST 24 | Feb 18 12:38:00 PM PST 24 | 3711817360 ps | ||
| T292 | /workspace/coverage/default/171.prim_prince_test.2239826397 | Feb 18 12:36:27 PM PST 24 | Feb 18 12:37:27 PM PST 24 | 2641709306 ps | ||
| T293 | /workspace/coverage/default/378.prim_prince_test.2004971524 | Feb 18 12:36:54 PM PST 24 | Feb 18 12:37:31 PM PST 24 | 1682020528 ps | ||
| T294 | /workspace/coverage/default/372.prim_prince_test.2795634572 | Feb 18 12:36:47 PM PST 24 | Feb 18 12:37:47 PM PST 24 | 2745408575 ps | ||
| T295 | /workspace/coverage/default/5.prim_prince_test.4279581317 | Feb 18 12:37:06 PM PST 24 | Feb 18 12:38:11 PM PST 24 | 3216946508 ps | ||
| T296 | /workspace/coverage/default/54.prim_prince_test.1910664395 | Feb 18 12:36:00 PM PST 24 | Feb 18 12:37:02 PM PST 24 | 3007156901 ps | ||
| T297 | /workspace/coverage/default/64.prim_prince_test.3346309166 | Feb 18 12:35:58 PM PST 24 | Feb 18 12:36:26 PM PST 24 | 1299364897 ps | ||
| T298 | /workspace/coverage/default/94.prim_prince_test.1080129015 | Feb 18 12:36:11 PM PST 24 | Feb 18 12:37:14 PM PST 24 | 2931804086 ps | ||
| T299 | /workspace/coverage/default/31.prim_prince_test.744786276 | Feb 18 12:36:03 PM PST 24 | Feb 18 12:36:47 PM PST 24 | 1971004661 ps | ||
| T300 | /workspace/coverage/default/254.prim_prince_test.3992058981 | Feb 18 12:36:29 PM PST 24 | Feb 18 12:37:41 PM PST 24 | 3167988039 ps | ||
| T301 | /workspace/coverage/default/87.prim_prince_test.4109874162 | Feb 18 12:36:05 PM PST 24 | Feb 18 12:37:02 PM PST 24 | 2652494872 ps | ||
| T302 | /workspace/coverage/default/436.prim_prince_test.987998508 | Feb 18 12:37:13 PM PST 24 | Feb 18 12:38:01 PM PST 24 | 2232482648 ps | ||
| T303 | /workspace/coverage/default/337.prim_prince_test.4194442259 | Feb 18 12:36:40 PM PST 24 | Feb 18 12:37:09 PM PST 24 | 1216051168 ps | ||
| T304 | /workspace/coverage/default/396.prim_prince_test.1818588704 | Feb 18 12:36:44 PM PST 24 | Feb 18 12:37:49 PM PST 24 | 2946506378 ps | ||
| T305 | /workspace/coverage/default/432.prim_prince_test.4059195498 | Feb 18 12:37:01 PM PST 24 | Feb 18 12:38:17 PM PST 24 | 3485123080 ps | ||
| T306 | /workspace/coverage/default/487.prim_prince_test.2451823615 | Feb 18 12:37:18 PM PST 24 | Feb 18 12:38:09 PM PST 24 | 2468956705 ps | ||
| T307 | /workspace/coverage/default/421.prim_prince_test.1530264533 | Feb 18 12:37:00 PM PST 24 | Feb 18 12:37:46 PM PST 24 | 2125036119 ps | ||
| T308 | /workspace/coverage/default/324.prim_prince_test.2435680480 | Feb 18 12:36:50 PM PST 24 | Feb 18 12:38:03 PM PST 24 | 3480630154 ps | ||
| T309 | /workspace/coverage/default/25.prim_prince_test.4036355446 | Feb 18 12:35:55 PM PST 24 | Feb 18 12:36:15 PM PST 24 | 903496883 ps | ||
| T310 | /workspace/coverage/default/287.prim_prince_test.3459437181 | Feb 18 12:36:31 PM PST 24 | Feb 18 12:36:56 PM PST 24 | 935582845 ps | ||
| T311 | /workspace/coverage/default/138.prim_prince_test.192902932 | Feb 18 12:36:10 PM PST 24 | Feb 18 12:37:01 PM PST 24 | 2384767257 ps | ||
| T312 | /workspace/coverage/default/359.prim_prince_test.3318885033 | Feb 18 12:36:44 PM PST 24 | Feb 18 12:37:08 PM PST 24 | 1123067605 ps | ||
| T313 | /workspace/coverage/default/39.prim_prince_test.2977640873 | Feb 18 12:35:54 PM PST 24 | Feb 18 12:36:28 PM PST 24 | 1477114500 ps | ||
| T314 | /workspace/coverage/default/269.prim_prince_test.2781357223 | Feb 18 12:36:30 PM PST 24 | Feb 18 12:37:04 PM PST 24 | 1307225146 ps | ||
| T315 | /workspace/coverage/default/419.prim_prince_test.104180402 | Feb 18 12:36:50 PM PST 24 | Feb 18 12:37:38 PM PST 24 | 2390426863 ps | ||
| T316 | /workspace/coverage/default/150.prim_prince_test.1618186614 | Feb 18 12:36:17 PM PST 24 | Feb 18 12:36:52 PM PST 24 | 1356555342 ps | ||
| T317 | /workspace/coverage/default/166.prim_prince_test.1338053820 | Feb 18 12:36:21 PM PST 24 | Feb 18 12:37:40 PM PST 24 | 3513292210 ps | ||
| T318 | /workspace/coverage/default/113.prim_prince_test.1597010407 | Feb 18 12:36:01 PM PST 24 | Feb 18 12:36:42 PM PST 24 | 1859845644 ps | ||
| T319 | /workspace/coverage/default/414.prim_prince_test.2555673660 | Feb 18 12:37:01 PM PST 24 | Feb 18 12:38:01 PM PST 24 | 2757607155 ps | ||
| T320 | /workspace/coverage/default/68.prim_prince_test.2038982592 | Feb 18 12:36:08 PM PST 24 | Feb 18 12:36:43 PM PST 24 | 1788990228 ps | ||
| T321 | /workspace/coverage/default/7.prim_prince_test.1423945509 | Feb 18 12:35:53 PM PST 24 | Feb 18 12:36:22 PM PST 24 | 1357186858 ps | ||
| T322 | /workspace/coverage/default/206.prim_prince_test.1862506007 | Feb 18 12:36:15 PM PST 24 | Feb 18 12:37:11 PM PST 24 | 2262387612 ps | ||
| T323 | /workspace/coverage/default/46.prim_prince_test.760525450 | Feb 18 12:35:58 PM PST 24 | Feb 18 12:36:44 PM PST 24 | 2055357462 ps | ||
| T324 | /workspace/coverage/default/391.prim_prince_test.2996887969 | Feb 18 12:36:48 PM PST 24 | Feb 18 12:37:26 PM PST 24 | 1737441496 ps | ||
| T325 | /workspace/coverage/default/468.prim_prince_test.1467100508 | Feb 18 12:37:11 PM PST 24 | Feb 18 12:38:03 PM PST 24 | 2465777829 ps | ||
| T326 | /workspace/coverage/default/49.prim_prince_test.3691326775 | Feb 18 12:35:59 PM PST 24 | Feb 18 12:36:27 PM PST 24 | 1189975087 ps | ||
| T327 | /workspace/coverage/default/205.prim_prince_test.2511530340 | Feb 18 12:36:26 PM PST 24 | Feb 18 12:37:29 PM PST 24 | 2676363585 ps | ||
| T328 | /workspace/coverage/default/125.prim_prince_test.3172811430 | Feb 18 12:36:06 PM PST 24 | Feb 18 12:36:40 PM PST 24 | 1573741806 ps | ||
| T329 | /workspace/coverage/default/454.prim_prince_test.1419918413 | Feb 18 12:37:08 PM PST 24 | Feb 18 12:38:21 PM PST 24 | 3540578937 ps | ||
| T330 | /workspace/coverage/default/498.prim_prince_test.1848263199 | Feb 18 12:37:18 PM PST 24 | Feb 18 12:38:14 PM PST 24 | 2568400924 ps | ||
| T331 | /workspace/coverage/default/92.prim_prince_test.487264532 | Feb 18 12:36:11 PM PST 24 | Feb 18 12:36:40 PM PST 24 | 1250996564 ps | ||
| T332 | /workspace/coverage/default/107.prim_prince_test.3066341554 | Feb 18 12:36:00 PM PST 24 | Feb 18 12:37:02 PM PST 24 | 2933615446 ps | ||
| T333 | /workspace/coverage/default/170.prim_prince_test.1053941258 | Feb 18 12:36:14 PM PST 24 | Feb 18 12:36:38 PM PST 24 | 825986056 ps | ||
| T334 | /workspace/coverage/default/2.prim_prince_test.616068329 | Feb 18 12:37:24 PM PST 24 | Feb 18 12:38:16 PM PST 24 | 2712436623 ps | ||
| T335 | /workspace/coverage/default/364.prim_prince_test.3937244390 | Feb 18 12:36:45 PM PST 24 | Feb 18 12:37:55 PM PST 24 | 3459662437 ps | ||
| T336 | /workspace/coverage/default/467.prim_prince_test.683053036 | Feb 18 12:37:14 PM PST 24 | Feb 18 12:37:57 PM PST 24 | 2062539848 ps | ||
| T337 | /workspace/coverage/default/340.prim_prince_test.143342289 | Feb 18 12:36:36 PM PST 24 | Feb 18 12:37:36 PM PST 24 | 2724782852 ps | ||
| T338 | /workspace/coverage/default/413.prim_prince_test.686563403 | Feb 18 12:36:50 PM PST 24 | Feb 18 12:38:02 PM PST 24 | 3339360796 ps | ||
| T339 | /workspace/coverage/default/409.prim_prince_test.2622511050 | Feb 18 12:36:54 PM PST 24 | Feb 18 12:37:35 PM PST 24 | 1849247129 ps | ||
| T340 | /workspace/coverage/default/132.prim_prince_test.824741289 | Feb 18 12:36:16 PM PST 24 | Feb 18 12:37:03 PM PST 24 | 1898421098 ps | ||
| T341 | /workspace/coverage/default/435.prim_prince_test.2691415188 | Feb 18 12:37:04 PM PST 24 | Feb 18 12:38:14 PM PST 24 | 3288850157 ps | ||
| T342 | /workspace/coverage/default/22.prim_prince_test.2078848298 | Feb 18 12:35:50 PM PST 24 | Feb 18 12:36:51 PM PST 24 | 2833482598 ps | ||
| T343 | /workspace/coverage/default/345.prim_prince_test.2249155327 | Feb 18 12:36:50 PM PST 24 | Feb 18 12:37:42 PM PST 24 | 2442211517 ps | ||
| T344 | /workspace/coverage/default/444.prim_prince_test.4288862992 | Feb 18 12:37:00 PM PST 24 | Feb 18 12:38:01 PM PST 24 | 3083236044 ps | ||
| T345 | /workspace/coverage/default/251.prim_prince_test.1936467291 | Feb 18 12:36:38 PM PST 24 | Feb 18 12:37:28 PM PST 24 | 2342001704 ps | ||
| T346 | /workspace/coverage/default/257.prim_prince_test.2790229965 | Feb 18 12:36:34 PM PST 24 | Feb 18 12:37:49 PM PST 24 | 3396503870 ps | ||
| T347 | /workspace/coverage/default/137.prim_prince_test.2557467868 | Feb 18 12:36:11 PM PST 24 | Feb 18 12:37:14 PM PST 24 | 2947048558 ps | ||
| T348 | /workspace/coverage/default/392.prim_prince_test.1505939690 | Feb 18 12:36:52 PM PST 24 | Feb 18 12:37:54 PM PST 24 | 2800181510 ps | ||
| T349 | /workspace/coverage/default/248.prim_prince_test.3964804114 | Feb 18 12:36:28 PM PST 24 | Feb 18 12:37:03 PM PST 24 | 1292592906 ps | ||
| T350 | /workspace/coverage/default/48.prim_prince_test.2757120239 | Feb 18 12:36:05 PM PST 24 | Feb 18 12:36:40 PM PST 24 | 1641256943 ps | ||
| T351 | /workspace/coverage/default/214.prim_prince_test.3531761131 | Feb 18 12:36:22 PM PST 24 | Feb 18 12:36:51 PM PST 24 | 1157121905 ps | ||
| T352 | /workspace/coverage/default/88.prim_prince_test.571544794 | Feb 18 12:36:00 PM PST 24 | Feb 18 12:36:40 PM PST 24 | 1857129469 ps | ||
| T353 | /workspace/coverage/default/439.prim_prince_test.2574271626 | Feb 18 12:36:59 PM PST 24 | Feb 18 12:37:34 PM PST 24 | 1563438465 ps | ||
| T354 | /workspace/coverage/default/448.prim_prince_test.1581155085 | Feb 18 12:37:05 PM PST 24 | Feb 18 12:38:02 PM PST 24 | 2608244586 ps | ||
| T355 | /workspace/coverage/default/73.prim_prince_test.756221413 | Feb 18 12:36:08 PM PST 24 | Feb 18 12:36:58 PM PST 24 | 2397634785 ps | ||
| T356 | /workspace/coverage/default/365.prim_prince_test.1183665137 | Feb 18 12:36:47 PM PST 24 | Feb 18 12:37:23 PM PST 24 | 1630864384 ps | ||
| T357 | /workspace/coverage/default/386.prim_prince_test.3898689240 | Feb 18 12:36:42 PM PST 24 | Feb 18 12:37:54 PM PST 24 | 3350874623 ps | ||
| T358 | /workspace/coverage/default/161.prim_prince_test.1033810043 | Feb 18 12:36:13 PM PST 24 | Feb 18 12:36:56 PM PST 24 | 1768083762 ps | ||
| T359 | /workspace/coverage/default/112.prim_prince_test.2546056512 | Feb 18 12:36:25 PM PST 24 | Feb 18 12:37:01 PM PST 24 | 1596667795 ps | ||
| T360 | /workspace/coverage/default/30.prim_prince_test.3967725484 | Feb 18 12:35:49 PM PST 24 | Feb 18 12:36:54 PM PST 24 | 3000480272 ps | ||
| T361 | /workspace/coverage/default/293.prim_prince_test.881499013 | Feb 18 12:36:32 PM PST 24 | Feb 18 12:37:16 PM PST 24 | 1863737205 ps | ||
| T362 | /workspace/coverage/default/246.prim_prince_test.2790923729 | Feb 18 12:36:23 PM PST 24 | Feb 18 12:36:52 PM PST 24 | 1201755182 ps | ||
| T363 | /workspace/coverage/default/56.prim_prince_test.290464029 | Feb 18 12:36:13 PM PST 24 | Feb 18 12:37:26 PM PST 24 | 3475042400 ps | ||
| T364 | /workspace/coverage/default/260.prim_prince_test.3879504890 | Feb 18 12:36:40 PM PST 24 | Feb 18 12:37:54 PM PST 24 | 3360800467 ps | ||
| T365 | /workspace/coverage/default/347.prim_prince_test.3140300618 | Feb 18 12:36:42 PM PST 24 | Feb 18 12:37:24 PM PST 24 | 1961826973 ps | ||
| T366 | /workspace/coverage/default/187.prim_prince_test.1438991786 | Feb 18 12:36:25 PM PST 24 | Feb 18 12:37:32 PM PST 24 | 3226214898 ps | ||
| T367 | /workspace/coverage/default/26.prim_prince_test.4015436842 | Feb 18 12:35:51 PM PST 24 | Feb 18 12:36:49 PM PST 24 | 2899785297 ps | ||
| T368 | /workspace/coverage/default/238.prim_prince_test.2194606519 | Feb 18 12:36:32 PM PST 24 | Feb 18 12:37:27 PM PST 24 | 2485068237 ps | ||
| T369 | /workspace/coverage/default/127.prim_prince_test.2814556187 | Feb 18 12:36:09 PM PST 24 | Feb 18 12:37:08 PM PST 24 | 2686015151 ps | ||
| T370 | /workspace/coverage/default/371.prim_prince_test.4240603409 | Feb 18 12:36:47 PM PST 24 | Feb 18 12:38:05 PM PST 24 | 3673055768 ps | ||
| T371 | /workspace/coverage/default/344.prim_prince_test.468662428 | Feb 18 12:36:48 PM PST 24 | Feb 18 12:37:13 PM PST 24 | 1138723671 ps | ||
| T372 | /workspace/coverage/default/149.prim_prince_test.2813848560 | Feb 18 12:36:21 PM PST 24 | Feb 18 12:37:41 PM PST 24 | 3668773039 ps | ||
| T373 | /workspace/coverage/default/223.prim_prince_test.243725716 | Feb 18 12:36:21 PM PST 24 | Feb 18 12:37:05 PM PST 24 | 1865655022 ps | ||
| T374 | /workspace/coverage/default/338.prim_prince_test.3401953376 | Feb 18 12:36:42 PM PST 24 | Feb 18 12:37:54 PM PST 24 | 3334326220 ps | ||
| T375 | /workspace/coverage/default/456.prim_prince_test.3346001736 | Feb 18 12:37:05 PM PST 24 | Feb 18 12:38:00 PM PST 24 | 2506941807 ps | ||
| T376 | /workspace/coverage/default/289.prim_prince_test.3039718198 | Feb 18 12:36:34 PM PST 24 | Feb 18 12:37:44 PM PST 24 | 3383988964 ps | ||
| T377 | /workspace/coverage/default/276.prim_prince_test.1930718870 | Feb 18 12:36:38 PM PST 24 | Feb 18 12:37:25 PM PST 24 | 1975591025 ps | ||
| T378 | /workspace/coverage/default/224.prim_prince_test.2889647445 | Feb 18 12:36:30 PM PST 24 | Feb 18 12:37:04 PM PST 24 | 1478620871 ps | ||
| T379 | /workspace/coverage/default/225.prim_prince_test.1502289839 | Feb 18 12:36:15 PM PST 24 | Feb 18 12:37:35 PM PST 24 | 3537628733 ps | ||
| T380 | /workspace/coverage/default/226.prim_prince_test.834800164 | Feb 18 12:36:14 PM PST 24 | Feb 18 12:37:09 PM PST 24 | 2429426836 ps | ||
| T381 | /workspace/coverage/default/178.prim_prince_test.3617544508 | Feb 18 12:36:17 PM PST 24 | Feb 18 12:36:47 PM PST 24 | 1093203870 ps | ||
| T382 | /workspace/coverage/default/380.prim_prince_test.407137149 | Feb 18 12:36:57 PM PST 24 | Feb 18 12:38:02 PM PST 24 | 3103184222 ps | ||
| T383 | /workspace/coverage/default/492.prim_prince_test.4031553830 | Feb 18 12:37:15 PM PST 24 | Feb 18 12:37:34 PM PST 24 | 831822150 ps | ||
| T384 | /workspace/coverage/default/352.prim_prince_test.2516401638 | Feb 18 12:36:42 PM PST 24 | Feb 18 12:37:41 PM PST 24 | 2873121304 ps | ||
| T385 | /workspace/coverage/default/394.prim_prince_test.3351132090 | Feb 18 12:36:47 PM PST 24 | Feb 18 12:37:53 PM PST 24 | 3124404684 ps | ||
| T386 | /workspace/coverage/default/245.prim_prince_test.2651496556 | Feb 18 12:36:43 PM PST 24 | Feb 18 12:37:20 PM PST 24 | 1696281726 ps | ||
| T387 | /workspace/coverage/default/302.prim_prince_test.3034353052 | Feb 18 12:36:29 PM PST 24 | Feb 18 12:37:32 PM PST 24 | 2717224558 ps | ||
| T388 | /workspace/coverage/default/219.prim_prince_test.2460664462 | Feb 18 12:36:27 PM PST 24 | Feb 18 12:37:04 PM PST 24 | 1578045130 ps | ||
| T389 | /workspace/coverage/default/0.prim_prince_test.1283015994 | Feb 18 12:37:23 PM PST 24 | Feb 18 12:38:25 PM PST 24 | 3228853716 ps | ||
| T390 | /workspace/coverage/default/369.prim_prince_test.2017659594 | Feb 18 12:36:45 PM PST 24 | Feb 18 12:37:15 PM PST 24 | 1434476537 ps | ||
| T391 | /workspace/coverage/default/229.prim_prince_test.982665363 | Feb 18 12:36:25 PM PST 24 | Feb 18 12:37:47 PM PST 24 | 3550950498 ps | ||
| T392 | /workspace/coverage/default/356.prim_prince_test.2137772666 | Feb 18 12:36:50 PM PST 24 | Feb 18 12:37:59 PM PST 24 | 3403315631 ps | ||
| T393 | /workspace/coverage/default/27.prim_prince_test.879700088 | Feb 18 12:36:00 PM PST 24 | Feb 18 12:37:11 PM PST 24 | 3394561968 ps | ||
| T394 | /workspace/coverage/default/78.prim_prince_test.3349936591 | Feb 18 12:36:06 PM PST 24 | Feb 18 12:36:38 PM PST 24 | 1498423418 ps | ||
| T395 | /workspace/coverage/default/140.prim_prince_test.3163537039 | Feb 18 12:36:10 PM PST 24 | Feb 18 12:37:15 PM PST 24 | 3129855803 ps | ||
| T396 | /workspace/coverage/default/265.prim_prince_test.2584918490 | Feb 18 12:36:25 PM PST 24 | Feb 18 12:37:05 PM PST 24 | 1619869273 ps | ||
| T397 | /workspace/coverage/default/42.prim_prince_test.768476335 | Feb 18 12:35:55 PM PST 24 | Feb 18 12:37:01 PM PST 24 | 3049333855 ps | ||
| T398 | /workspace/coverage/default/141.prim_prince_test.1873631775 | Feb 18 12:36:19 PM PST 24 | Feb 18 12:37:10 PM PST 24 | 2109838907 ps | ||
| T399 | /workspace/coverage/default/412.prim_prince_test.3256328632 | Feb 18 12:36:52 PM PST 24 | Feb 18 12:38:07 PM PST 24 | 3462595318 ps | ||
| T400 | /workspace/coverage/default/220.prim_prince_test.4028152441 | Feb 18 12:36:25 PM PST 24 | Feb 18 12:37:25 PM PST 24 | 2663247869 ps | ||
| T401 | /workspace/coverage/default/228.prim_prince_test.2224145294 | Feb 18 12:36:21 PM PST 24 | Feb 18 12:37:21 PM PST 24 | 2798530300 ps | ||
| T402 | /workspace/coverage/default/202.prim_prince_test.1989988830 | Feb 18 12:36:22 PM PST 24 | Feb 18 12:37:15 PM PST 24 | 2301536213 ps | ||
| T403 | /workspace/coverage/default/280.prim_prince_test.2897390330 | Feb 18 12:36:40 PM PST 24 | Feb 18 12:37:18 PM PST 24 | 1679557757 ps | ||
| T404 | /workspace/coverage/default/252.prim_prince_test.827532879 | Feb 18 12:36:26 PM PST 24 | Feb 18 12:37:13 PM PST 24 | 2081706188 ps | ||
| T405 | /workspace/coverage/default/462.prim_prince_test.1693357731 | Feb 18 12:37:07 PM PST 24 | Feb 18 12:37:31 PM PST 24 | 1106245548 ps | ||
| T406 | /workspace/coverage/default/172.prim_prince_test.4010021874 | Feb 18 12:36:14 PM PST 24 | Feb 18 12:37:27 PM PST 24 | 3161462923 ps | ||
| T407 | /workspace/coverage/default/279.prim_prince_test.3136918060 | Feb 18 12:36:44 PM PST 24 | Feb 18 12:38:02 PM PST 24 | 3507907830 ps | ||
| T408 | /workspace/coverage/default/311.prim_prince_test.1169661393 | Feb 18 12:36:38 PM PST 24 | Feb 18 12:37:33 PM PST 24 | 2558535972 ps | ||
| T409 | /workspace/coverage/default/134.prim_prince_test.445951574 | Feb 18 12:36:14 PM PST 24 | Feb 18 12:36:57 PM PST 24 | 1502866082 ps | ||
| T410 | /workspace/coverage/default/23.prim_prince_test.4036981715 | Feb 18 12:35:55 PM PST 24 | Feb 18 12:36:40 PM PST 24 | 2039922879 ps | ||
| T411 | /workspace/coverage/default/130.prim_prince_test.614915438 | Feb 18 12:36:11 PM PST 24 | Feb 18 12:36:42 PM PST 24 | 1257539887 ps | ||
| T412 | /workspace/coverage/default/241.prim_prince_test.2179770820 | Feb 18 12:36:28 PM PST 24 | Feb 18 12:37:40 PM PST 24 | 3037474046 ps | ||
| T413 | /workspace/coverage/default/243.prim_prince_test.3436473535 | Feb 18 12:36:36 PM PST 24 | Feb 18 12:37:14 PM PST 24 | 1812678652 ps | ||
| T414 | /workspace/coverage/default/282.prim_prince_test.3376821111 | Feb 18 12:36:36 PM PST 24 | Feb 18 12:37:12 PM PST 24 | 1641492594 ps | ||
| T415 | /workspace/coverage/default/242.prim_prince_test.3394787217 | Feb 18 12:36:20 PM PST 24 | Feb 18 12:37:15 PM PST 24 | 2464326346 ps | ||
| T416 | /workspace/coverage/default/428.prim_prince_test.2052827732 | Feb 18 12:36:56 PM PST 24 | Feb 18 12:37:36 PM PST 24 | 1839123366 ps | ||
| T417 | /workspace/coverage/default/307.prim_prince_test.3685555264 | Feb 18 12:36:38 PM PST 24 | Feb 18 12:37:15 PM PST 24 | 1623228729 ps | ||
| T418 | /workspace/coverage/default/142.prim_prince_test.2124744484 | Feb 18 12:36:08 PM PST 24 | Feb 18 12:36:33 PM PST 24 | 1203435987 ps | ||
| T419 | /workspace/coverage/default/385.prim_prince_test.1150034731 | Feb 18 12:36:48 PM PST 24 | Feb 18 12:37:39 PM PST 24 | 2298095459 ps | ||
| T420 | /workspace/coverage/default/121.prim_prince_test.2055502979 | Feb 18 12:36:26 PM PST 24 | Feb 18 12:37:25 PM PST 24 | 2549069896 ps | ||
| T421 | /workspace/coverage/default/480.prim_prince_test.3742910759 | Feb 18 12:37:17 PM PST 24 | Feb 18 12:37:49 PM PST 24 | 1556130713 ps | ||
| T422 | /workspace/coverage/default/173.prim_prince_test.3008719872 | Feb 18 12:36:26 PM PST 24 | Feb 18 12:37:22 PM PST 24 | 2472498075 ps | ||
| T423 | /workspace/coverage/default/153.prim_prince_test.3251609235 | Feb 18 12:36:14 PM PST 24 | Feb 18 12:37:17 PM PST 24 | 2725361802 ps | ||
| T424 | /workspace/coverage/default/390.prim_prince_test.937821004 | Feb 18 12:36:43 PM PST 24 | Feb 18 12:37:44 PM PST 24 | 2928421510 ps | ||
| T425 | /workspace/coverage/default/319.prim_prince_test.1591058897 | Feb 18 12:36:46 PM PST 24 | Feb 18 12:37:23 PM PST 24 | 1710209206 ps | ||
| T426 | /workspace/coverage/default/162.prim_prince_test.2817357644 | Feb 18 12:36:06 PM PST 24 | Feb 18 12:36:54 PM PST 24 | 2448717198 ps | ||
| T427 | /workspace/coverage/default/353.prim_prince_test.2820970387 | Feb 18 12:36:44 PM PST 24 | Feb 18 12:37:26 PM PST 24 | 1983141990 ps | ||
| T428 | /workspace/coverage/default/294.prim_prince_test.1017029308 | Feb 18 12:36:38 PM PST 24 | Feb 18 12:37:39 PM PST 24 | 2885157280 ps | ||
| T429 | /workspace/coverage/default/253.prim_prince_test.1340813582 | Feb 18 12:36:37 PM PST 24 | Feb 18 12:37:26 PM PST 24 | 2204568038 ps | ||
| T430 | /workspace/coverage/default/1.prim_prince_test.2525866204 | Feb 18 12:37:06 PM PST 24 | Feb 18 12:37:50 PM PST 24 | 2130822846 ps | ||
| T431 | /workspace/coverage/default/481.prim_prince_test.2107216196 | Feb 18 12:37:18 PM PST 24 | Feb 18 12:37:50 PM PST 24 | 1439361043 ps | ||
| T432 | /workspace/coverage/default/400.prim_prince_test.436828730 | Feb 18 12:36:54 PM PST 24 | Feb 18 12:37:26 PM PST 24 | 1357919959 ps | ||
| T433 | /workspace/coverage/default/387.prim_prince_test.3328001830 | Feb 18 12:36:55 PM PST 24 | Feb 18 12:37:51 PM PST 24 | 2523008008 ps | ||
| T434 | /workspace/coverage/default/95.prim_prince_test.1344449827 | Feb 18 12:36:15 PM PST 24 | Feb 18 12:37:23 PM PST 24 | 2883490585 ps | ||
| T435 | /workspace/coverage/default/169.prim_prince_test.4122628753 | Feb 18 12:36:23 PM PST 24 | Feb 18 12:37:29 PM PST 24 | 3016585532 ps | ||
| T436 | /workspace/coverage/default/135.prim_prince_test.2146146586 | Feb 18 12:36:22 PM PST 24 | Feb 18 12:37:06 PM PST 24 | 1840196284 ps | ||
| T437 | /workspace/coverage/default/457.prim_prince_test.320710637 | Feb 18 12:37:04 PM PST 24 | Feb 18 12:38:04 PM PST 24 | 2816152314 ps | ||
| T438 | /workspace/coverage/default/236.prim_prince_test.327854201 | Feb 18 12:36:28 PM PST 24 | Feb 18 12:37:19 PM PST 24 | 2289214731 ps | ||
| T439 | /workspace/coverage/default/13.prim_prince_test.1394111056 | Feb 18 12:35:50 PM PST 24 | Feb 18 12:36:23 PM PST 24 | 1456759221 ps | ||
| T440 | /workspace/coverage/default/218.prim_prince_test.2085759411 | Feb 18 12:36:27 PM PST 24 | Feb 18 12:37:37 PM PST 24 | 3314683199 ps | ||
| T441 | /workspace/coverage/default/230.prim_prince_test.4050977308 | Feb 18 12:36:25 PM PST 24 | Feb 18 12:37:46 PM PST 24 | 3721768269 ps | ||
| T442 | /workspace/coverage/default/237.prim_prince_test.1624013525 | Feb 18 12:36:36 PM PST 24 | Feb 18 12:37:28 PM PST 24 | 2494694353 ps | ||
| T443 | /workspace/coverage/default/295.prim_prince_test.827063223 | Feb 18 12:36:47 PM PST 24 | Feb 18 12:37:34 PM PST 24 | 2098364093 ps | ||
| T444 | /workspace/coverage/default/426.prim_prince_test.4042622027 | Feb 18 12:36:54 PM PST 24 | Feb 18 12:37:33 PM PST 24 | 1701358385 ps | ||
| T445 | /workspace/coverage/default/315.prim_prince_test.1424840781 | Feb 18 12:36:43 PM PST 24 | Feb 18 12:37:40 PM PST 24 | 2696222056 ps | ||
| T446 | /workspace/coverage/default/122.prim_prince_test.2689236966 | Feb 18 12:36:13 PM PST 24 | Feb 18 12:37:26 PM PST 24 | 3338096108 ps | ||
| T447 | /workspace/coverage/default/222.prim_prince_test.625134892 | Feb 18 12:36:29 PM PST 24 | Feb 18 12:37:12 PM PST 24 | 1740430965 ps | ||
| T448 | /workspace/coverage/default/55.prim_prince_test.95159080 | Feb 18 12:36:08 PM PST 24 | Feb 18 12:37:23 PM PST 24 | 3413937250 ps | ||
| T449 | /workspace/coverage/default/461.prim_prince_test.4075029465 | Feb 18 12:37:08 PM PST 24 | Feb 18 12:38:19 PM PST 24 | 3465817772 ps | ||
| T450 | /workspace/coverage/default/332.prim_prince_test.313219781 | Feb 18 12:36:47 PM PST 24 | Feb 18 12:37:23 PM PST 24 | 1577937546 ps | ||
| T451 | /workspace/coverage/default/466.prim_prince_test.267643207 | Feb 18 12:37:10 PM PST 24 | Feb 18 12:38:03 PM PST 24 | 2431937267 ps | ||
| T452 | /workspace/coverage/default/267.prim_prince_test.3509536583 | Feb 18 12:36:34 PM PST 24 | Feb 18 12:37:43 PM PST 24 | 3272067791 ps | ||
| T453 | /workspace/coverage/default/416.prim_prince_test.2040996439 | Feb 18 12:36:57 PM PST 24 | Feb 18 12:37:36 PM PST 24 | 1782109137 ps | ||
| T454 | /workspace/coverage/default/203.prim_prince_test.132280267 | Feb 18 12:36:23 PM PST 24 | Feb 18 12:37:07 PM PST 24 | 1785578707 ps | ||
| T455 | /workspace/coverage/default/16.prim_prince_test.2541641110 | Feb 18 12:35:51 PM PST 24 | Feb 18 12:37:01 PM PST 24 | 3475998624 ps | ||
| T456 | /workspace/coverage/default/351.prim_prince_test.3861734511 | Feb 18 12:36:51 PM PST 24 | Feb 18 12:37:35 PM PST 24 | 2169024372 ps | ||
| T457 | /workspace/coverage/default/322.prim_prince_test.3564521979 | Feb 18 12:36:35 PM PST 24 | Feb 18 12:37:40 PM PST 24 | 2969097462 ps | ||
| T458 | /workspace/coverage/default/404.prim_prince_test.393312939 | Feb 18 12:36:52 PM PST 24 | Feb 18 12:38:03 PM PST 24 | 3408264127 ps | ||
| T459 | /workspace/coverage/default/156.prim_prince_test.3199483514 | Feb 18 12:36:13 PM PST 24 | Feb 18 12:36:38 PM PST 24 | 932614902 ps | ||
| T460 | /workspace/coverage/default/452.prim_prince_test.530784463 | Feb 18 12:37:05 PM PST 24 | Feb 18 12:37:55 PM PST 24 | 2389106983 ps | ||
| T461 | /workspace/coverage/default/11.prim_prince_test.78006536 | Feb 18 12:37:14 PM PST 24 | Feb 18 12:38:17 PM PST 24 | 3259085203 ps | ||
| T462 | /workspace/coverage/default/3.prim_prince_test.2474781323 | Feb 18 12:35:53 PM PST 24 | Feb 18 12:37:08 PM PST 24 | 3503561406 ps | ||
| T463 | /workspace/coverage/default/357.prim_prince_test.3529235359 | Feb 18 12:36:42 PM PST 24 | Feb 18 12:37:55 PM PST 24 | 3447942941 ps | ||
| T464 | /workspace/coverage/default/465.prim_prince_test.3647879034 | Feb 18 12:37:13 PM PST 24 | Feb 18 12:38:19 PM PST 24 | 3326961476 ps | ||
| T465 | /workspace/coverage/default/433.prim_prince_test.1278487075 | Feb 18 12:37:01 PM PST 24 | Feb 18 12:37:53 PM PST 24 | 2411028673 ps | ||
| T466 | /workspace/coverage/default/374.prim_prince_test.1246811172 | Feb 18 12:36:55 PM PST 24 | Feb 18 12:38:11 PM PST 24 | 3501225550 ps | ||
| T467 | /workspace/coverage/default/119.prim_prince_test.402214335 | Feb 18 12:36:10 PM PST 24 | Feb 18 12:36:39 PM PST 24 | 1273562403 ps | ||
| T468 | /workspace/coverage/default/108.prim_prince_test.60577716 | Feb 18 12:36:05 PM PST 24 | Feb 18 12:36:35 PM PST 24 | 1364181275 ps | ||
| T469 | /workspace/coverage/default/336.prim_prince_test.2957365619 | Feb 18 12:36:47 PM PST 24 | Feb 18 12:37:58 PM PST 24 | 3364803051 ps | ||
| T470 | /workspace/coverage/default/66.prim_prince_test.3800388768 | Feb 18 12:36:10 PM PST 24 | Feb 18 12:36:51 PM PST 24 | 1815522884 ps | ||
| T471 | /workspace/coverage/default/388.prim_prince_test.3091465685 | Feb 18 12:36:55 PM PST 24 | Feb 18 12:37:16 PM PST 24 | 878563883 ps | ||
| T472 | /workspace/coverage/default/490.prim_prince_test.1790913996 | Feb 18 12:37:20 PM PST 24 | Feb 18 12:38:21 PM PST 24 | 3021234840 ps | ||
| T473 | /workspace/coverage/default/415.prim_prince_test.2851823618 | Feb 18 12:36:51 PM PST 24 | Feb 18 12:38:04 PM PST 24 | 3524303244 ps | ||
| T474 | /workspace/coverage/default/263.prim_prince_test.48026818 | Feb 18 12:36:30 PM PST 24 | Feb 18 12:37:22 PM PST 24 | 2221341571 ps | ||
| T475 | /workspace/coverage/default/232.prim_prince_test.885843328 | Feb 18 12:36:31 PM PST 24 | Feb 18 12:36:58 PM PST 24 | 1038308375 ps | ||
| T476 | /workspace/coverage/default/278.prim_prince_test.191758417 | Feb 18 12:36:40 PM PST 24 | Feb 18 12:37:52 PM PST 24 | 3435004950 ps | ||
| T477 | /workspace/coverage/default/136.prim_prince_test.4022370070 | Feb 18 12:36:13 PM PST 24 | Feb 18 12:37:04 PM PST 24 | 2163064104 ps | ||
| T478 | /workspace/coverage/default/33.prim_prince_test.970344796 | Feb 18 12:36:00 PM PST 24 | Feb 18 12:36:21 PM PST 24 | 817165874 ps | ||
| T479 | /workspace/coverage/default/485.prim_prince_test.4091230940 | Feb 18 12:37:18 PM PST 24 | Feb 18 12:38:22 PM PST 24 | 3063635205 ps | ||
| T480 | /workspace/coverage/default/323.prim_prince_test.2222803814 | Feb 18 12:36:40 PM PST 24 | Feb 18 12:37:45 PM PST 24 | 3221571056 ps | ||
| T481 | /workspace/coverage/default/165.prim_prince_test.4197181404 | Feb 18 12:36:07 PM PST 24 | Feb 18 12:37:08 PM PST 24 | 3119034171 ps | ||
| T482 | /workspace/coverage/default/97.prim_prince_test.304389622 | Feb 18 12:36:26 PM PST 24 | Feb 18 12:37:35 PM PST 24 | 3143551232 ps | ||
| T483 | /workspace/coverage/default/471.prim_prince_test.2803573549 | Feb 18 12:37:11 PM PST 24 | Feb 18 12:38:22 PM PST 24 | 3309555150 ps | ||
| T484 | /workspace/coverage/default/458.prim_prince_test.2984186570 | Feb 18 12:37:13 PM PST 24 | Feb 18 12:38:04 PM PST 24 | 2400305314 ps | ||
| T485 | /workspace/coverage/default/37.prim_prince_test.3301320756 | Feb 18 12:35:56 PM PST 24 | Feb 18 12:36:39 PM PST 24 | 1934937818 ps | ||
| T486 | /workspace/coverage/default/174.prim_prince_test.199848813 | Feb 18 12:36:26 PM PST 24 | Feb 18 12:37:41 PM PST 24 | 3349255566 ps | ||
| T487 | /workspace/coverage/default/247.prim_prince_test.4072635245 | Feb 18 12:36:33 PM PST 24 | Feb 18 12:37:11 PM PST 24 | 1646671470 ps | ||
| T488 | /workspace/coverage/default/65.prim_prince_test.618597519 | Feb 18 12:35:57 PM PST 24 | Feb 18 12:36:44 PM PST 24 | 2051930869 ps | ||
| T489 | /workspace/coverage/default/382.prim_prince_test.3693590154 | Feb 18 12:36:55 PM PST 24 | Feb 18 12:37:46 PM PST 24 | 2275788045 ps | ||
| T490 | /workspace/coverage/default/493.prim_prince_test.1066769916 | Feb 18 12:37:18 PM PST 24 | Feb 18 12:37:55 PM PST 24 | 1664552716 ps | ||
| T491 | /workspace/coverage/default/438.prim_prince_test.3793025965 | Feb 18 12:36:58 PM PST 24 | Feb 18 12:38:04 PM PST 24 | 3087857854 ps | ||
| T492 | /workspace/coverage/default/424.prim_prince_test.2367929594 | Feb 18 12:36:52 PM PST 24 | Feb 18 12:37:57 PM PST 24 | 3050188414 ps | ||
| T493 | /workspace/coverage/default/71.prim_prince_test.1153030698 | Feb 18 12:36:04 PM PST 24 | Feb 18 12:37:14 PM PST 24 | 3219822040 ps | ||
| T494 | /workspace/coverage/default/244.prim_prince_test.1826445756 | Feb 18 12:36:27 PM PST 24 | Feb 18 12:37:20 PM PST 24 | 2181164611 ps | ||
| T495 | /workspace/coverage/default/159.prim_prince_test.2901602059 | Feb 18 12:36:24 PM PST 24 | Feb 18 12:36:46 PM PST 24 | 859895628 ps | ||
| T496 | /workspace/coverage/default/93.prim_prince_test.3032723137 | Feb 18 12:36:05 PM PST 24 | Feb 18 12:37:06 PM PST 24 | 3098180663 ps | ||
| T497 | /workspace/coverage/default/160.prim_prince_test.3003316734 | Feb 18 12:36:18 PM PST 24 | Feb 18 12:37:24 PM PST 24 | 2790307162 ps | ||
| T498 | /workspace/coverage/default/80.prim_prince_test.4228933278 | Feb 18 12:36:15 PM PST 24 | Feb 18 12:37:20 PM PST 24 | 2794790827 ps | ||
| T499 | /workspace/coverage/default/366.prim_prince_test.2704534040 | Feb 18 12:36:49 PM PST 24 | Feb 18 12:37:36 PM PST 24 | 2326539254 ps | ||
| T500 | /workspace/coverage/default/379.prim_prince_test.3206731809 | Feb 18 12:36:39 PM PST 24 | Feb 18 12:37:56 PM PST 24 | 3732993406 ps |
| Test location | /workspace/coverage/default/114.prim_prince_test.3447333438 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 958333527 ps |
| CPU time | 15.89 seconds |
| Started | Feb 18 12:36:27 PM PST 24 |
| Finished | Feb 18 12:36:52 PM PST 24 |
| Peak memory | 146848 kb |
| Host | smart-9402ae7b-778a-44c2-85ce-e79cb7bbdcd0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3447333438 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 114.prim_prince_test.3447333438 |
| Directory | /workspace/114.prim_prince_test/latest |
| Test location | /workspace/coverage/default/0.prim_prince_test.1283015994 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 3228853716 ps |
| CPU time | 51.98 seconds |
| Started | Feb 18 12:37:23 PM PST 24 |
| Finished | Feb 18 12:38:25 PM PST 24 |
| Peak memory | 146336 kb |
| Host | smart-1b95f2b2-760f-4e3d-b853-fcd6676bf7ec |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1283015994 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_prince_test.1283015994 |
| Directory | /workspace/0.prim_prince_test/latest |
| Test location | /workspace/coverage/default/1.prim_prince_test.2525866204 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 2130822846 ps |
| CPU time | 35.02 seconds |
| Started | Feb 18 12:37:06 PM PST 24 |
| Finished | Feb 18 12:37:50 PM PST 24 |
| Peak memory | 144496 kb |
| Host | smart-a823aeea-0870-4f91-ab07-324d504bc9b2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2525866204 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_prince_test.2525866204 |
| Directory | /workspace/1.prim_prince_test/latest |
| Test location | /workspace/coverage/default/10.prim_prince_test.651724670 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 1499155897 ps |
| CPU time | 25.02 seconds |
| Started | Feb 18 12:35:42 PM PST 24 |
| Finished | Feb 18 12:36:13 PM PST 24 |
| Peak memory | 146860 kb |
| Host | smart-1af9cc3d-bfc2-4de8-b4b0-254c1ce35c89 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=651724670 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_prince_test.651724670 |
| Directory | /workspace/10.prim_prince_test/latest |
| Test location | /workspace/coverage/default/100.prim_prince_test.260161885 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 2064598368 ps |
| CPU time | 34.36 seconds |
| Started | Feb 18 12:36:02 PM PST 24 |
| Finished | Feb 18 12:36:47 PM PST 24 |
| Peak memory | 146856 kb |
| Host | smart-8c925604-815c-413d-911a-ebb975149c38 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=260161885 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 100.prim_prince_test.260161885 |
| Directory | /workspace/100.prim_prince_test/latest |
| Test location | /workspace/coverage/default/101.prim_prince_test.3253572904 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 3223170385 ps |
| CPU time | 52.8 seconds |
| Started | Feb 18 12:36:14 PM PST 24 |
| Finished | Feb 18 12:37:24 PM PST 24 |
| Peak memory | 146972 kb |
| Host | smart-34f14016-74c2-465d-9bc1-614f30bcaa94 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3253572904 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 101.prim_prince_test.3253572904 |
| Directory | /workspace/101.prim_prince_test/latest |
| Test location | /workspace/coverage/default/102.prim_prince_test.2905969276 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 2125026331 ps |
| CPU time | 35.74 seconds |
| Started | Feb 18 12:36:08 PM PST 24 |
| Finished | Feb 18 12:36:54 PM PST 24 |
| Peak memory | 146856 kb |
| Host | smart-0ee489ef-34cf-45b8-b37e-a552f4526125 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2905969276 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 102.prim_prince_test.2905969276 |
| Directory | /workspace/102.prim_prince_test/latest |
| Test location | /workspace/coverage/default/103.prim_prince_test.1963972352 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 2972155392 ps |
| CPU time | 49.58 seconds |
| Started | Feb 18 12:36:22 PM PST 24 |
| Finished | Feb 18 12:37:27 PM PST 24 |
| Peak memory | 146960 kb |
| Host | smart-371200ae-8789-4ad0-b816-24b7c9528414 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1963972352 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 103.prim_prince_test.1963972352 |
| Directory | /workspace/103.prim_prince_test/latest |
| Test location | /workspace/coverage/default/104.prim_prince_test.1635490195 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 2181965873 ps |
| CPU time | 37.06 seconds |
| Started | Feb 18 12:36:25 PM PST 24 |
| Finished | Feb 18 12:37:16 PM PST 24 |
| Peak memory | 146948 kb |
| Host | smart-98e1b9b5-303a-4e0c-a950-960bdbe1a04f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1635490195 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 104.prim_prince_test.1635490195 |
| Directory | /workspace/104.prim_prince_test/latest |
| Test location | /workspace/coverage/default/105.prim_prince_test.216336440 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 942646873 ps |
| CPU time | 15.91 seconds |
| Started | Feb 18 12:36:05 PM PST 24 |
| Finished | Feb 18 12:36:32 PM PST 24 |
| Peak memory | 146912 kb |
| Host | smart-48b78682-8aaf-4837-a525-15d4d4affc62 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=216336440 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 105.prim_prince_test.216336440 |
| Directory | /workspace/105.prim_prince_test/latest |
| Test location | /workspace/coverage/default/106.prim_prince_test.35822081 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 1877889285 ps |
| CPU time | 31.09 seconds |
| Started | Feb 18 12:36:02 PM PST 24 |
| Finished | Feb 18 12:36:42 PM PST 24 |
| Peak memory | 146884 kb |
| Host | smart-7e2c8052-7de3-474e-bac5-9df942e14578 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=35822081 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 106.prim_prince_test.35822081 |
| Directory | /workspace/106.prim_prince_test/latest |
| Test location | /workspace/coverage/default/107.prim_prince_test.3066341554 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 2933615446 ps |
| CPU time | 48.12 seconds |
| Started | Feb 18 12:36:00 PM PST 24 |
| Finished | Feb 18 12:37:02 PM PST 24 |
| Peak memory | 147088 kb |
| Host | smart-10f56715-ca71-41c7-aaaa-fe6d32c6da95 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3066341554 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 107.prim_prince_test.3066341554 |
| Directory | /workspace/107.prim_prince_test/latest |
| Test location | /workspace/coverage/default/108.prim_prince_test.60577716 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 1364181275 ps |
| CPU time | 23.22 seconds |
| Started | Feb 18 12:36:05 PM PST 24 |
| Finished | Feb 18 12:36:35 PM PST 24 |
| Peak memory | 146852 kb |
| Host | smart-a026293e-5448-44c9-843a-46f765a429e2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=60577716 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 108.prim_prince_test.60577716 |
| Directory | /workspace/108.prim_prince_test/latest |
| Test location | /workspace/coverage/default/109.prim_prince_test.1514460970 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 876152535 ps |
| CPU time | 15.07 seconds |
| Started | Feb 18 12:35:59 PM PST 24 |
| Finished | Feb 18 12:36:21 PM PST 24 |
| Peak memory | 146816 kb |
| Host | smart-6614afca-7144-4458-b85e-ef47f92c419e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1514460970 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 109.prim_prince_test.1514460970 |
| Directory | /workspace/109.prim_prince_test/latest |
| Test location | /workspace/coverage/default/11.prim_prince_test.78006536 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 3259085203 ps |
| CPU time | 52.38 seconds |
| Started | Feb 18 12:37:14 PM PST 24 |
| Finished | Feb 18 12:38:17 PM PST 24 |
| Peak memory | 145328 kb |
| Host | smart-851e590b-ae65-4215-94ba-295fc9b2b5a8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=78006536 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_prince_test.78006536 |
| Directory | /workspace/11.prim_prince_test/latest |
| Test location | /workspace/coverage/default/110.prim_prince_test.2682880625 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 1881449742 ps |
| CPU time | 30.44 seconds |
| Started | Feb 18 12:36:17 PM PST 24 |
| Finished | Feb 18 12:37:00 PM PST 24 |
| Peak memory | 146760 kb |
| Host | smart-e1b9143c-2adf-44b9-8bd1-6937e5ec396b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2682880625 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 110.prim_prince_test.2682880625 |
| Directory | /workspace/110.prim_prince_test/latest |
| Test location | /workspace/coverage/default/111.prim_prince_test.3630323487 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 1040047826 ps |
| CPU time | 17.29 seconds |
| Started | Feb 18 12:35:59 PM PST 24 |
| Finished | Feb 18 12:36:23 PM PST 24 |
| Peak memory | 146904 kb |
| Host | smart-d66d4cb0-4c5d-4cae-8c8b-24163d5bef8f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3630323487 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 111.prim_prince_test.3630323487 |
| Directory | /workspace/111.prim_prince_test/latest |
| Test location | /workspace/coverage/default/112.prim_prince_test.2546056512 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 1596667795 ps |
| CPU time | 26.04 seconds |
| Started | Feb 18 12:36:25 PM PST 24 |
| Finished | Feb 18 12:37:01 PM PST 24 |
| Peak memory | 146836 kb |
| Host | smart-a70d0112-1b14-4049-8346-bc757190f5f7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2546056512 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 112.prim_prince_test.2546056512 |
| Directory | /workspace/112.prim_prince_test/latest |
| Test location | /workspace/coverage/default/113.prim_prince_test.1597010407 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 1859845644 ps |
| CPU time | 30.71 seconds |
| Started | Feb 18 12:36:01 PM PST 24 |
| Finished | Feb 18 12:36:42 PM PST 24 |
| Peak memory | 146856 kb |
| Host | smart-1d0dfef2-00ff-4fdd-ba64-f6cfeebdd525 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1597010407 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 113.prim_prince_test.1597010407 |
| Directory | /workspace/113.prim_prince_test/latest |
| Test location | /workspace/coverage/default/115.prim_prince_test.2896008932 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 3521014424 ps |
| CPU time | 60.07 seconds |
| Started | Feb 18 12:36:03 PM PST 24 |
| Finished | Feb 18 12:37:19 PM PST 24 |
| Peak memory | 146980 kb |
| Host | smart-2bc432b9-1baf-4d7f-873a-143a0a925122 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2896008932 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 115.prim_prince_test.2896008932 |
| Directory | /workspace/115.prim_prince_test/latest |
| Test location | /workspace/coverage/default/116.prim_prince_test.304969656 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 3436643390 ps |
| CPU time | 57.03 seconds |
| Started | Feb 18 12:36:19 PM PST 24 |
| Finished | Feb 18 12:37:35 PM PST 24 |
| Peak memory | 146972 kb |
| Host | smart-87aa4021-10ac-4646-b0b5-8c828aedf905 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=304969656 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 116.prim_prince_test.304969656 |
| Directory | /workspace/116.prim_prince_test/latest |
| Test location | /workspace/coverage/default/117.prim_prince_test.3301905154 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 3202455936 ps |
| CPU time | 54.36 seconds |
| Started | Feb 18 12:36:10 PM PST 24 |
| Finished | Feb 18 12:37:22 PM PST 24 |
| Peak memory | 146956 kb |
| Host | smart-0d0e3336-f4a9-49b2-84a5-404447656aef |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3301905154 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 117.prim_prince_test.3301905154 |
| Directory | /workspace/117.prim_prince_test/latest |
| Test location | /workspace/coverage/default/118.prim_prince_test.3353393227 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 975434872 ps |
| CPU time | 16.11 seconds |
| Started | Feb 18 12:36:10 PM PST 24 |
| Finished | Feb 18 12:36:33 PM PST 24 |
| Peak memory | 146832 kb |
| Host | smart-d3ae696c-aeb8-40d0-8785-814d36580cfb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3353393227 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 118.prim_prince_test.3353393227 |
| Directory | /workspace/118.prim_prince_test/latest |
| Test location | /workspace/coverage/default/119.prim_prince_test.402214335 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 1273562403 ps |
| CPU time | 21.52 seconds |
| Started | Feb 18 12:36:10 PM PST 24 |
| Finished | Feb 18 12:36:39 PM PST 24 |
| Peak memory | 146832 kb |
| Host | smart-a44172db-5ff4-4f8f-b038-24230753b38c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=402214335 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 119.prim_prince_test.402214335 |
| Directory | /workspace/119.prim_prince_test/latest |
| Test location | /workspace/coverage/default/12.prim_prince_test.3105375828 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 1392142209 ps |
| CPU time | 22.89 seconds |
| Started | Feb 18 12:36:01 PM PST 24 |
| Finished | Feb 18 12:36:31 PM PST 24 |
| Peak memory | 146908 kb |
| Host | smart-e4836b51-09a0-45b4-b3fa-11ae51078cf1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3105375828 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_prince_test.3105375828 |
| Directory | /workspace/12.prim_prince_test/latest |
| Test location | /workspace/coverage/default/120.prim_prince_test.4093422067 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 2346897335 ps |
| CPU time | 40.24 seconds |
| Started | Feb 18 12:36:17 PM PST 24 |
| Finished | Feb 18 12:37:14 PM PST 24 |
| Peak memory | 146996 kb |
| Host | smart-eab9af34-64e4-4a42-9ec1-22609f224ee9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4093422067 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 120.prim_prince_test.4093422067 |
| Directory | /workspace/120.prim_prince_test/latest |
| Test location | /workspace/coverage/default/121.prim_prince_test.2055502979 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 2549069896 ps |
| CPU time | 43 seconds |
| Started | Feb 18 12:36:26 PM PST 24 |
| Finished | Feb 18 12:37:25 PM PST 24 |
| Peak memory | 146840 kb |
| Host | smart-196f9eba-dee1-4163-85c5-a8c77e7dda7a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2055502979 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 121.prim_prince_test.2055502979 |
| Directory | /workspace/121.prim_prince_test/latest |
| Test location | /workspace/coverage/default/122.prim_prince_test.2689236966 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 3338096108 ps |
| CPU time | 54.79 seconds |
| Started | Feb 18 12:36:13 PM PST 24 |
| Finished | Feb 18 12:37:26 PM PST 24 |
| Peak memory | 146952 kb |
| Host | smart-cfb0286e-63b1-4ea0-bc56-b1ff969c3c85 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2689236966 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 122.prim_prince_test.2689236966 |
| Directory | /workspace/122.prim_prince_test/latest |
| Test location | /workspace/coverage/default/123.prim_prince_test.251767557 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 1695617689 ps |
| CPU time | 29.04 seconds |
| Started | Feb 18 12:36:20 PM PST 24 |
| Finished | Feb 18 12:37:03 PM PST 24 |
| Peak memory | 146928 kb |
| Host | smart-ecc866e8-456d-4300-857f-a1c67e2017e6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=251767557 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 123.prim_prince_test.251767557 |
| Directory | /workspace/123.prim_prince_test/latest |
| Test location | /workspace/coverage/default/124.prim_prince_test.368131437 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 2743615391 ps |
| CPU time | 46.52 seconds |
| Started | Feb 18 12:36:13 PM PST 24 |
| Finished | Feb 18 12:37:16 PM PST 24 |
| Peak memory | 146836 kb |
| Host | smart-b0eab832-dd6e-4ab8-9249-775aafaf5510 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=368131437 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 124.prim_prince_test.368131437 |
| Directory | /workspace/124.prim_prince_test/latest |
| Test location | /workspace/coverage/default/125.prim_prince_test.3172811430 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 1573741806 ps |
| CPU time | 26.27 seconds |
| Started | Feb 18 12:36:06 PM PST 24 |
| Finished | Feb 18 12:36:40 PM PST 24 |
| Peak memory | 146824 kb |
| Host | smart-c4cf55e1-bcc9-47d7-81f6-5f2fe1aa9fec |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3172811430 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 125.prim_prince_test.3172811430 |
| Directory | /workspace/125.prim_prince_test/latest |
| Test location | /workspace/coverage/default/126.prim_prince_test.2908353190 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 1769431332 ps |
| CPU time | 29.2 seconds |
| Started | Feb 18 12:36:26 PM PST 24 |
| Finished | Feb 18 12:37:08 PM PST 24 |
| Peak memory | 146216 kb |
| Host | smart-3eddc1f4-75a5-400c-ac92-35fac00e1730 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2908353190 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 126.prim_prince_test.2908353190 |
| Directory | /workspace/126.prim_prince_test/latest |
| Test location | /workspace/coverage/default/127.prim_prince_test.2814556187 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 2686015151 ps |
| CPU time | 46.12 seconds |
| Started | Feb 18 12:36:09 PM PST 24 |
| Finished | Feb 18 12:37:08 PM PST 24 |
| Peak memory | 147028 kb |
| Host | smart-b46c6f0e-aab5-4221-9efa-bf99fcbf0aec |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2814556187 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 127.prim_prince_test.2814556187 |
| Directory | /workspace/127.prim_prince_test/latest |
| Test location | /workspace/coverage/default/128.prim_prince_test.742496636 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 897820395 ps |
| CPU time | 15.22 seconds |
| Started | Feb 18 12:36:08 PM PST 24 |
| Finished | Feb 18 12:36:28 PM PST 24 |
| Peak memory | 146828 kb |
| Host | smart-1e2412e0-5e70-4c9a-b5b2-d944efddf441 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=742496636 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 128.prim_prince_test.742496636 |
| Directory | /workspace/128.prim_prince_test/latest |
| Test location | /workspace/coverage/default/129.prim_prince_test.2175255114 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 1651829736 ps |
| CPU time | 27.82 seconds |
| Started | Feb 18 12:36:18 PM PST 24 |
| Finished | Feb 18 12:37:00 PM PST 24 |
| Peak memory | 146932 kb |
| Host | smart-1f61ff2b-70b9-42fa-85ca-227d59bf5a28 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2175255114 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 129.prim_prince_test.2175255114 |
| Directory | /workspace/129.prim_prince_test/latest |
| Test location | /workspace/coverage/default/13.prim_prince_test.1394111056 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 1456759221 ps |
| CPU time | 25.21 seconds |
| Started | Feb 18 12:35:50 PM PST 24 |
| Finished | Feb 18 12:36:23 PM PST 24 |
| Peak memory | 146864 kb |
| Host | smart-bedbb754-a8e9-40f3-9fa7-64043440fa08 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1394111056 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_prince_test.1394111056 |
| Directory | /workspace/13.prim_prince_test/latest |
| Test location | /workspace/coverage/default/130.prim_prince_test.614915438 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 1257539887 ps |
| CPU time | 22.06 seconds |
| Started | Feb 18 12:36:11 PM PST 24 |
| Finished | Feb 18 12:36:42 PM PST 24 |
| Peak memory | 146848 kb |
| Host | smart-7e8ab908-d63c-4f16-8184-c93b1e9eaeb2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=614915438 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 130.prim_prince_test.614915438 |
| Directory | /workspace/130.prim_prince_test/latest |
| Test location | /workspace/coverage/default/131.prim_prince_test.670448625 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 1413638280 ps |
| CPU time | 23.2 seconds |
| Started | Feb 18 12:36:17 PM PST 24 |
| Finished | Feb 18 12:36:52 PM PST 24 |
| Peak memory | 146848 kb |
| Host | smart-55d396de-d9eb-454f-80c1-150093cdd72e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=670448625 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 131.prim_prince_test.670448625 |
| Directory | /workspace/131.prim_prince_test/latest |
| Test location | /workspace/coverage/default/132.prim_prince_test.824741289 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 1898421098 ps |
| CPU time | 32.63 seconds |
| Started | Feb 18 12:36:16 PM PST 24 |
| Finished | Feb 18 12:37:03 PM PST 24 |
| Peak memory | 146836 kb |
| Host | smart-dbd96356-259d-4284-a9e0-15af4a3bc393 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=824741289 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 132.prim_prince_test.824741289 |
| Directory | /workspace/132.prim_prince_test/latest |
| Test location | /workspace/coverage/default/133.prim_prince_test.3383235064 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 2932142137 ps |
| CPU time | 48.65 seconds |
| Started | Feb 18 12:36:14 PM PST 24 |
| Finished | Feb 18 12:37:19 PM PST 24 |
| Peak memory | 147036 kb |
| Host | smart-111129ac-b129-400c-9342-b102bfd2f98a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3383235064 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 133.prim_prince_test.3383235064 |
| Directory | /workspace/133.prim_prince_test/latest |
| Test location | /workspace/coverage/default/134.prim_prince_test.445951574 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 1502866082 ps |
| CPU time | 25.29 seconds |
| Started | Feb 18 12:36:14 PM PST 24 |
| Finished | Feb 18 12:36:57 PM PST 24 |
| Peak memory | 146912 kb |
| Host | smart-0cb08bd7-d3bc-4891-a766-4d4ff81e24c9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=445951574 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 134.prim_prince_test.445951574 |
| Directory | /workspace/134.prim_prince_test/latest |
| Test location | /workspace/coverage/default/135.prim_prince_test.2146146586 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 1840196284 ps |
| CPU time | 30.77 seconds |
| Started | Feb 18 12:36:22 PM PST 24 |
| Finished | Feb 18 12:37:06 PM PST 24 |
| Peak memory | 146828 kb |
| Host | smart-51ed2d97-2391-4989-aaa3-73b69dff32d2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2146146586 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 135.prim_prince_test.2146146586 |
| Directory | /workspace/135.prim_prince_test/latest |
| Test location | /workspace/coverage/default/136.prim_prince_test.4022370070 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 2163064104 ps |
| CPU time | 36.83 seconds |
| Started | Feb 18 12:36:13 PM PST 24 |
| Finished | Feb 18 12:37:04 PM PST 24 |
| Peak memory | 146840 kb |
| Host | smart-5ba95021-e8a8-4b3a-afeb-1de66c18cee2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4022370070 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 136.prim_prince_test.4022370070 |
| Directory | /workspace/136.prim_prince_test/latest |
| Test location | /workspace/coverage/default/137.prim_prince_test.2557467868 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 2947048558 ps |
| CPU time | 49.26 seconds |
| Started | Feb 18 12:36:11 PM PST 24 |
| Finished | Feb 18 12:37:14 PM PST 24 |
| Peak memory | 146952 kb |
| Host | smart-10b0ae6e-cfb2-4429-b143-1ca21f8a9612 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2557467868 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 137.prim_prince_test.2557467868 |
| Directory | /workspace/137.prim_prince_test/latest |
| Test location | /workspace/coverage/default/138.prim_prince_test.192902932 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 2384767257 ps |
| CPU time | 38.94 seconds |
| Started | Feb 18 12:36:10 PM PST 24 |
| Finished | Feb 18 12:37:01 PM PST 24 |
| Peak memory | 146984 kb |
| Host | smart-d61d8c2e-3420-41dd-a149-d14025853610 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=192902932 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 138.prim_prince_test.192902932 |
| Directory | /workspace/138.prim_prince_test/latest |
| Test location | /workspace/coverage/default/139.prim_prince_test.1219237559 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 1968928954 ps |
| CPU time | 29.42 seconds |
| Started | Feb 18 12:36:29 PM PST 24 |
| Finished | Feb 18 12:37:09 PM PST 24 |
| Peak memory | 146740 kb |
| Host | smart-2f31e6ee-cfc4-4df1-8830-6a53b6776434 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1219237559 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 139.prim_prince_test.1219237559 |
| Directory | /workspace/139.prim_prince_test/latest |
| Test location | /workspace/coverage/default/14.prim_prince_test.4049064800 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 1190665854 ps |
| CPU time | 21.08 seconds |
| Started | Feb 18 12:36:15 PM PST 24 |
| Finished | Feb 18 12:36:49 PM PST 24 |
| Peak memory | 146892 kb |
| Host | smart-054b5b74-9f40-4065-b806-82c2449dab38 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4049064800 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_prince_test.4049064800 |
| Directory | /workspace/14.prim_prince_test/latest |
| Test location | /workspace/coverage/default/140.prim_prince_test.3163537039 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 3129855803 ps |
| CPU time | 50.7 seconds |
| Started | Feb 18 12:36:10 PM PST 24 |
| Finished | Feb 18 12:37:15 PM PST 24 |
| Peak memory | 146972 kb |
| Host | smart-b33f8e5d-fd16-48d1-87e9-204e48c92456 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3163537039 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 140.prim_prince_test.3163537039 |
| Directory | /workspace/140.prim_prince_test/latest |
| Test location | /workspace/coverage/default/141.prim_prince_test.1873631775 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 2109838907 ps |
| CPU time | 35.69 seconds |
| Started | Feb 18 12:36:19 PM PST 24 |
| Finished | Feb 18 12:37:10 PM PST 24 |
| Peak memory | 146836 kb |
| Host | smart-e9c82ef2-70af-42e7-b3aa-d466eec132e4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1873631775 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 141.prim_prince_test.1873631775 |
| Directory | /workspace/141.prim_prince_test/latest |
| Test location | /workspace/coverage/default/142.prim_prince_test.2124744484 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 1203435987 ps |
| CPU time | 19.75 seconds |
| Started | Feb 18 12:36:08 PM PST 24 |
| Finished | Feb 18 12:36:33 PM PST 24 |
| Peak memory | 146836 kb |
| Host | smart-f571ca08-6a24-44b9-bf87-d2c1ad58f4b4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2124744484 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 142.prim_prince_test.2124744484 |
| Directory | /workspace/142.prim_prince_test/latest |
| Test location | /workspace/coverage/default/143.prim_prince_test.2018848747 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 1528175117 ps |
| CPU time | 25.25 seconds |
| Started | Feb 18 12:36:09 PM PST 24 |
| Finished | Feb 18 12:36:41 PM PST 24 |
| Peak memory | 146920 kb |
| Host | smart-59a93897-a359-4bef-8ea6-72cac6575c2e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2018848747 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 143.prim_prince_test.2018848747 |
| Directory | /workspace/143.prim_prince_test/latest |
| Test location | /workspace/coverage/default/144.prim_prince_test.1046616677 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 992513726 ps |
| CPU time | 16.56 seconds |
| Started | Feb 18 12:36:13 PM PST 24 |
| Finished | Feb 18 12:36:39 PM PST 24 |
| Peak memory | 146832 kb |
| Host | smart-51c3a6f0-b5fe-4fc5-88a9-9f0343e54a59 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1046616677 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 144.prim_prince_test.1046616677 |
| Directory | /workspace/144.prim_prince_test/latest |
| Test location | /workspace/coverage/default/145.prim_prince_test.2591066603 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 3157316187 ps |
| CPU time | 52.07 seconds |
| Started | Feb 18 12:36:12 PM PST 24 |
| Finished | Feb 18 12:37:19 PM PST 24 |
| Peak memory | 146952 kb |
| Host | smart-3bf90cb3-7d8d-48f1-8008-495cd0957c5e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2591066603 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 145.prim_prince_test.2591066603 |
| Directory | /workspace/145.prim_prince_test/latest |
| Test location | /workspace/coverage/default/146.prim_prince_test.1440346138 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 989058548 ps |
| CPU time | 16.84 seconds |
| Started | Feb 18 12:36:08 PM PST 24 |
| Finished | Feb 18 12:36:30 PM PST 24 |
| Peak memory | 146944 kb |
| Host | smart-60d814ce-d9ac-442b-99fa-485be402b1ba |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1440346138 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 146.prim_prince_test.1440346138 |
| Directory | /workspace/146.prim_prince_test/latest |
| Test location | /workspace/coverage/default/147.prim_prince_test.4026622259 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 1828022555 ps |
| CPU time | 29.97 seconds |
| Started | Feb 18 12:36:17 PM PST 24 |
| Finished | Feb 18 12:37:01 PM PST 24 |
| Peak memory | 146760 kb |
| Host | smart-8107c7e4-1633-4970-a944-e65058491c6a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4026622259 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 147.prim_prince_test.4026622259 |
| Directory | /workspace/147.prim_prince_test/latest |
| Test location | /workspace/coverage/default/148.prim_prince_test.85020955 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 1962294432 ps |
| CPU time | 33.78 seconds |
| Started | Feb 18 12:36:11 PM PST 24 |
| Finished | Feb 18 12:36:58 PM PST 24 |
| Peak memory | 146864 kb |
| Host | smart-aa23384b-a6ef-41ef-8c37-33792615b1c6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=85020955 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 148.prim_prince_test.85020955 |
| Directory | /workspace/148.prim_prince_test/latest |
| Test location | /workspace/coverage/default/149.prim_prince_test.2813848560 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 3668773039 ps |
| CPU time | 61.07 seconds |
| Started | Feb 18 12:36:21 PM PST 24 |
| Finished | Feb 18 12:37:41 PM PST 24 |
| Peak memory | 146968 kb |
| Host | smart-6d8ae141-15b8-4ca3-aca8-401fc7bf432e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2813848560 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 149.prim_prince_test.2813848560 |
| Directory | /workspace/149.prim_prince_test/latest |
| Test location | /workspace/coverage/default/15.prim_prince_test.73693319 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 3090029963 ps |
| CPU time | 52.78 seconds |
| Started | Feb 18 12:35:58 PM PST 24 |
| Finished | Feb 18 12:37:07 PM PST 24 |
| Peak memory | 147012 kb |
| Host | smart-a346a2c2-61ac-415f-a74c-bfc0fab28b0a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=73693319 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_prince_test.73693319 |
| Directory | /workspace/15.prim_prince_test/latest |
| Test location | /workspace/coverage/default/150.prim_prince_test.1618186614 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 1356555342 ps |
| CPU time | 23.2 seconds |
| Started | Feb 18 12:36:17 PM PST 24 |
| Finished | Feb 18 12:36:52 PM PST 24 |
| Peak memory | 146824 kb |
| Host | smart-8fb8d913-aaa0-4b0c-a594-6e46c754942f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1618186614 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 150.prim_prince_test.1618186614 |
| Directory | /workspace/150.prim_prince_test/latest |
| Test location | /workspace/coverage/default/151.prim_prince_test.2036727330 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 2424089763 ps |
| CPU time | 39.51 seconds |
| Started | Feb 18 12:36:10 PM PST 24 |
| Finished | Feb 18 12:37:01 PM PST 24 |
| Peak memory | 146972 kb |
| Host | smart-f9315638-c2a9-480d-ab3b-7d14d5b52ffb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2036727330 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 151.prim_prince_test.2036727330 |
| Directory | /workspace/151.prim_prince_test/latest |
| Test location | /workspace/coverage/default/152.prim_prince_test.2937496182 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 1676574722 ps |
| CPU time | 28.31 seconds |
| Started | Feb 18 12:36:23 PM PST 24 |
| Finished | Feb 18 12:37:03 PM PST 24 |
| Peak memory | 146828 kb |
| Host | smart-9d2ba3f8-1fc3-49be-ba82-e47bbf8e9fdc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2937496182 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 152.prim_prince_test.2937496182 |
| Directory | /workspace/152.prim_prince_test/latest |
| Test location | /workspace/coverage/default/153.prim_prince_test.3251609235 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 2725361802 ps |
| CPU time | 46.23 seconds |
| Started | Feb 18 12:36:14 PM PST 24 |
| Finished | Feb 18 12:37:17 PM PST 24 |
| Peak memory | 146840 kb |
| Host | smart-d1d5d290-d2f5-4c11-ba20-085f2938323b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3251609235 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 153.prim_prince_test.3251609235 |
| Directory | /workspace/153.prim_prince_test/latest |
| Test location | /workspace/coverage/default/154.prim_prince_test.556608124 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 1189832931 ps |
| CPU time | 19.65 seconds |
| Started | Feb 18 12:36:10 PM PST 24 |
| Finished | Feb 18 12:36:37 PM PST 24 |
| Peak memory | 146756 kb |
| Host | smart-5369bf99-687f-4bb7-a724-16ddd165c4e1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=556608124 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 154.prim_prince_test.556608124 |
| Directory | /workspace/154.prim_prince_test/latest |
| Test location | /workspace/coverage/default/155.prim_prince_test.89712170 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 1023047768 ps |
| CPU time | 16.5 seconds |
| Started | Feb 18 12:36:27 PM PST 24 |
| Finished | Feb 18 12:36:52 PM PST 24 |
| Peak memory | 146864 kb |
| Host | smart-847b519f-e9f5-417a-b4b1-f1a06066b789 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=89712170 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 155.prim_prince_test.89712170 |
| Directory | /workspace/155.prim_prince_test/latest |
| Test location | /workspace/coverage/default/156.prim_prince_test.3199483514 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 932614902 ps |
| CPU time | 15.71 seconds |
| Started | Feb 18 12:36:13 PM PST 24 |
| Finished | Feb 18 12:36:38 PM PST 24 |
| Peak memory | 146832 kb |
| Host | smart-eb3b80f2-6bac-4b22-989d-569594bb47d4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3199483514 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 156.prim_prince_test.3199483514 |
| Directory | /workspace/156.prim_prince_test/latest |
| Test location | /workspace/coverage/default/157.prim_prince_test.1113222472 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 3154909779 ps |
| CPU time | 53.17 seconds |
| Started | Feb 18 12:36:22 PM PST 24 |
| Finished | Feb 18 12:37:33 PM PST 24 |
| Peak memory | 146948 kb |
| Host | smart-da1d87cb-8ec0-42a3-bde2-51053d329fa6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1113222472 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 157.prim_prince_test.1113222472 |
| Directory | /workspace/157.prim_prince_test/latest |
| Test location | /workspace/coverage/default/158.prim_prince_test.3475312678 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 1642028364 ps |
| CPU time | 26.09 seconds |
| Started | Feb 18 12:36:24 PM PST 24 |
| Finished | Feb 18 12:37:00 PM PST 24 |
| Peak memory | 146836 kb |
| Host | smart-55ab425c-f5b6-4032-ad16-0d1e28ced0c8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3475312678 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 158.prim_prince_test.3475312678 |
| Directory | /workspace/158.prim_prince_test/latest |
| Test location | /workspace/coverage/default/159.prim_prince_test.2901602059 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 859895628 ps |
| CPU time | 13.95 seconds |
| Started | Feb 18 12:36:24 PM PST 24 |
| Finished | Feb 18 12:36:46 PM PST 24 |
| Peak memory | 146836 kb |
| Host | smart-4ac56659-54a0-4db0-a9ab-af3569c37982 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2901602059 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 159.prim_prince_test.2901602059 |
| Directory | /workspace/159.prim_prince_test/latest |
| Test location | /workspace/coverage/default/16.prim_prince_test.2541641110 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 3475998624 ps |
| CPU time | 56.3 seconds |
| Started | Feb 18 12:35:51 PM PST 24 |
| Finished | Feb 18 12:37:01 PM PST 24 |
| Peak memory | 146964 kb |
| Host | smart-8093fb34-5c08-4086-b692-f3815c5dfb7d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2541641110 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_prince_test.2541641110 |
| Directory | /workspace/16.prim_prince_test/latest |
| Test location | /workspace/coverage/default/160.prim_prince_test.3003316734 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 2790307162 ps |
| CPU time | 47.34 seconds |
| Started | Feb 18 12:36:18 PM PST 24 |
| Finished | Feb 18 12:37:24 PM PST 24 |
| Peak memory | 147036 kb |
| Host | smart-73ea1c07-de87-4377-8d91-7a1fe6e53238 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3003316734 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 160.prim_prince_test.3003316734 |
| Directory | /workspace/160.prim_prince_test/latest |
| Test location | /workspace/coverage/default/161.prim_prince_test.1033810043 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 1768083762 ps |
| CPU time | 29.79 seconds |
| Started | Feb 18 12:36:13 PM PST 24 |
| Finished | Feb 18 12:36:56 PM PST 24 |
| Peak memory | 146720 kb |
| Host | smart-9e9949df-747d-4d58-b6a1-1ae05af0538a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1033810043 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 161.prim_prince_test.1033810043 |
| Directory | /workspace/161.prim_prince_test/latest |
| Test location | /workspace/coverage/default/162.prim_prince_test.2817357644 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 2448717198 ps |
| CPU time | 39.02 seconds |
| Started | Feb 18 12:36:06 PM PST 24 |
| Finished | Feb 18 12:36:54 PM PST 24 |
| Peak memory | 146956 kb |
| Host | smart-3b88f23d-00b2-4ce1-aad3-35320929bed2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2817357644 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 162.prim_prince_test.2817357644 |
| Directory | /workspace/162.prim_prince_test/latest |
| Test location | /workspace/coverage/default/163.prim_prince_test.3504278024 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 951530265 ps |
| CPU time | 16.32 seconds |
| Started | Feb 18 12:36:19 PM PST 24 |
| Finished | Feb 18 12:36:47 PM PST 24 |
| Peak memory | 146932 kb |
| Host | smart-fcc45e67-e2c8-4e69-8668-f5f420c0ff82 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3504278024 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 163.prim_prince_test.3504278024 |
| Directory | /workspace/163.prim_prince_test/latest |
| Test location | /workspace/coverage/default/164.prim_prince_test.1839312902 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 1070207535 ps |
| CPU time | 17.98 seconds |
| Started | Feb 18 12:36:13 PM PST 24 |
| Finished | Feb 18 12:36:39 PM PST 24 |
| Peak memory | 146720 kb |
| Host | smart-ce824660-7257-4ae0-a85a-92dc9159aa06 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1839312902 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 164.prim_prince_test.1839312902 |
| Directory | /workspace/164.prim_prince_test/latest |
| Test location | /workspace/coverage/default/165.prim_prince_test.4197181404 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 3119034171 ps |
| CPU time | 50.12 seconds |
| Started | Feb 18 12:36:07 PM PST 24 |
| Finished | Feb 18 12:37:08 PM PST 24 |
| Peak memory | 146956 kb |
| Host | smart-059f5af8-358b-4577-b62e-56855b420664 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4197181404 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 165.prim_prince_test.4197181404 |
| Directory | /workspace/165.prim_prince_test/latest |
| Test location | /workspace/coverage/default/166.prim_prince_test.1338053820 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 3513292210 ps |
| CPU time | 58.97 seconds |
| Started | Feb 18 12:36:21 PM PST 24 |
| Finished | Feb 18 12:37:40 PM PST 24 |
| Peak memory | 146956 kb |
| Host | smart-615cd1b6-3b24-4db7-ac2d-507531ea2954 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1338053820 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 166.prim_prince_test.1338053820 |
| Directory | /workspace/166.prim_prince_test/latest |
| Test location | /workspace/coverage/default/167.prim_prince_test.3881764694 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 2229159420 ps |
| CPU time | 36.83 seconds |
| Started | Feb 18 12:36:22 PM PST 24 |
| Finished | Feb 18 12:37:12 PM PST 24 |
| Peak memory | 146968 kb |
| Host | smart-962c0f7f-aa90-4a85-b241-a499dd702078 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3881764694 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 167.prim_prince_test.3881764694 |
| Directory | /workspace/167.prim_prince_test/latest |
| Test location | /workspace/coverage/default/168.prim_prince_test.3884819332 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 3688092299 ps |
| CPU time | 62.19 seconds |
| Started | Feb 18 12:36:14 PM PST 24 |
| Finished | Feb 18 12:37:37 PM PST 24 |
| Peak memory | 146940 kb |
| Host | smart-dd03668e-584c-4bc5-8a74-69bc88384560 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3884819332 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 168.prim_prince_test.3884819332 |
| Directory | /workspace/168.prim_prince_test/latest |
| Test location | /workspace/coverage/default/169.prim_prince_test.4122628753 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 3016585532 ps |
| CPU time | 49.68 seconds |
| Started | Feb 18 12:36:23 PM PST 24 |
| Finished | Feb 18 12:37:29 PM PST 24 |
| Peak memory | 146948 kb |
| Host | smart-c47305b4-2cad-496b-b27b-5f9e01a38390 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4122628753 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 169.prim_prince_test.4122628753 |
| Directory | /workspace/169.prim_prince_test/latest |
| Test location | /workspace/coverage/default/17.prim_prince_test.1174176230 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 2832276688 ps |
| CPU time | 47.11 seconds |
| Started | Feb 18 12:35:58 PM PST 24 |
| Finished | Feb 18 12:36:58 PM PST 24 |
| Peak memory | 146896 kb |
| Host | smart-8e43ae27-4b12-4b16-8a79-afc9e887b093 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1174176230 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_prince_test.1174176230 |
| Directory | /workspace/17.prim_prince_test/latest |
| Test location | /workspace/coverage/default/170.prim_prince_test.1053941258 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 825986056 ps |
| CPU time | 14 seconds |
| Started | Feb 18 12:36:14 PM PST 24 |
| Finished | Feb 18 12:36:38 PM PST 24 |
| Peak memory | 146856 kb |
| Host | smart-46aa565c-3f12-4fc6-845e-70ed63e69f64 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1053941258 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 170.prim_prince_test.1053941258 |
| Directory | /workspace/170.prim_prince_test/latest |
| Test location | /workspace/coverage/default/171.prim_prince_test.2239826397 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 2641709306 ps |
| CPU time | 43.91 seconds |
| Started | Feb 18 12:36:27 PM PST 24 |
| Finished | Feb 18 12:37:27 PM PST 24 |
| Peak memory | 146952 kb |
| Host | smart-a5daf5b4-dbd3-4eac-bcf9-d8e81bb15c5e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2239826397 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 171.prim_prince_test.2239826397 |
| Directory | /workspace/171.prim_prince_test/latest |
| Test location | /workspace/coverage/default/172.prim_prince_test.4010021874 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 3161462923 ps |
| CPU time | 53.79 seconds |
| Started | Feb 18 12:36:14 PM PST 24 |
| Finished | Feb 18 12:37:27 PM PST 24 |
| Peak memory | 146976 kb |
| Host | smart-cbabeb46-7c2a-4bda-b879-00c3d26c6957 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4010021874 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 172.prim_prince_test.4010021874 |
| Directory | /workspace/172.prim_prince_test/latest |
| Test location | /workspace/coverage/default/173.prim_prince_test.3008719872 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 2472498075 ps |
| CPU time | 41.16 seconds |
| Started | Feb 18 12:36:26 PM PST 24 |
| Finished | Feb 18 12:37:22 PM PST 24 |
| Peak memory | 146960 kb |
| Host | smart-963e8f26-0e4e-4287-8ec6-a3375d5b21cb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3008719872 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 173.prim_prince_test.3008719872 |
| Directory | /workspace/173.prim_prince_test/latest |
| Test location | /workspace/coverage/default/174.prim_prince_test.199848813 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 3349255566 ps |
| CPU time | 56.09 seconds |
| Started | Feb 18 12:36:26 PM PST 24 |
| Finished | Feb 18 12:37:41 PM PST 24 |
| Peak memory | 146540 kb |
| Host | smart-238a027e-8621-438f-a18a-c245f62c3004 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=199848813 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 174.prim_prince_test.199848813 |
| Directory | /workspace/174.prim_prince_test/latest |
| Test location | /workspace/coverage/default/175.prim_prince_test.3881983967 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 1155744809 ps |
| CPU time | 19.1 seconds |
| Started | Feb 18 12:36:24 PM PST 24 |
| Finished | Feb 18 12:36:53 PM PST 24 |
| Peak memory | 146824 kb |
| Host | smart-6f1d5366-7c73-4a76-a7c3-2863a2722bbc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3881983967 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 175.prim_prince_test.3881983967 |
| Directory | /workspace/175.prim_prince_test/latest |
| Test location | /workspace/coverage/default/176.prim_prince_test.1315626802 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 3501262886 ps |
| CPU time | 57.73 seconds |
| Started | Feb 18 12:36:23 PM PST 24 |
| Finished | Feb 18 12:37:39 PM PST 24 |
| Peak memory | 146880 kb |
| Host | smart-1f29685f-8f2a-455e-9c76-d75e49bbe7af |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1315626802 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 176.prim_prince_test.1315626802 |
| Directory | /workspace/176.prim_prince_test/latest |
| Test location | /workspace/coverage/default/177.prim_prince_test.3903149260 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 2303068537 ps |
| CPU time | 39.13 seconds |
| Started | Feb 18 12:36:20 PM PST 24 |
| Finished | Feb 18 12:37:15 PM PST 24 |
| Peak memory | 147032 kb |
| Host | smart-b44beae2-b15a-437a-b5ae-5872a7886af3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3903149260 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 177.prim_prince_test.3903149260 |
| Directory | /workspace/177.prim_prince_test/latest |
| Test location | /workspace/coverage/default/178.prim_prince_test.3617544508 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 1093203870 ps |
| CPU time | 18.64 seconds |
| Started | Feb 18 12:36:17 PM PST 24 |
| Finished | Feb 18 12:36:47 PM PST 24 |
| Peak memory | 146908 kb |
| Host | smart-2a6f2ed3-452e-4ab4-8715-92d4710fec1f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3617544508 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 178.prim_prince_test.3617544508 |
| Directory | /workspace/178.prim_prince_test/latest |
| Test location | /workspace/coverage/default/179.prim_prince_test.3236717289 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 3068256383 ps |
| CPU time | 52.54 seconds |
| Started | Feb 18 12:36:14 PM PST 24 |
| Finished | Feb 18 12:37:25 PM PST 24 |
| Peak memory | 146956 kb |
| Host | smart-e1206489-ccb5-4a35-8d6e-2ac532270da4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3236717289 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 179.prim_prince_test.3236717289 |
| Directory | /workspace/179.prim_prince_test/latest |
| Test location | /workspace/coverage/default/18.prim_prince_test.2432112 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 3022255214 ps |
| CPU time | 50.19 seconds |
| Started | Feb 18 12:36:06 PM PST 24 |
| Finished | Feb 18 12:37:08 PM PST 24 |
| Peak memory | 147004 kb |
| Host | smart-5d08929e-f1d9-4502-8a90-853557a091b0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2432112 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_prince_test.2432112 |
| Directory | /workspace/18.prim_prince_test/latest |
| Test location | /workspace/coverage/default/180.prim_prince_test.3926469896 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 964309344 ps |
| CPU time | 16.58 seconds |
| Started | Feb 18 12:36:15 PM PST 24 |
| Finished | Feb 18 12:36:41 PM PST 24 |
| Peak memory | 146912 kb |
| Host | smart-c9c880bd-019f-4232-b343-8cd1ede22eb9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3926469896 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 180.prim_prince_test.3926469896 |
| Directory | /workspace/180.prim_prince_test/latest |
| Test location | /workspace/coverage/default/181.prim_prince_test.4156370456 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 3584805458 ps |
| CPU time | 59.94 seconds |
| Started | Feb 18 12:36:30 PM PST 24 |
| Finished | Feb 18 12:37:49 PM PST 24 |
| Peak memory | 147036 kb |
| Host | smart-7557a3c9-2d78-4318-9913-784378b44e42 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4156370456 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 181.prim_prince_test.4156370456 |
| Directory | /workspace/181.prim_prince_test/latest |
| Test location | /workspace/coverage/default/182.prim_prince_test.2088756739 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 3436246479 ps |
| CPU time | 59.32 seconds |
| Started | Feb 18 12:36:17 PM PST 24 |
| Finished | Feb 18 12:37:37 PM PST 24 |
| Peak memory | 146968 kb |
| Host | smart-b99fa208-bbd1-43f2-ae6f-5cdfcf029ef1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2088756739 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 182.prim_prince_test.2088756739 |
| Directory | /workspace/182.prim_prince_test/latest |
| Test location | /workspace/coverage/default/183.prim_prince_test.1619155334 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 1009017573 ps |
| CPU time | 17.11 seconds |
| Started | Feb 18 12:36:13 PM PST 24 |
| Finished | Feb 18 12:36:40 PM PST 24 |
| Peak memory | 146768 kb |
| Host | smart-42fd8c52-ffca-45fe-a252-fbc07737441e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1619155334 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 183.prim_prince_test.1619155334 |
| Directory | /workspace/183.prim_prince_test/latest |
| Test location | /workspace/coverage/default/184.prim_prince_test.3872990624 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 3110386737 ps |
| CPU time | 51.57 seconds |
| Started | Feb 18 12:36:26 PM PST 24 |
| Finished | Feb 18 12:37:35 PM PST 24 |
| Peak memory | 146968 kb |
| Host | smart-5c3fa051-3697-4735-94d7-46391617e1b5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3872990624 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 184.prim_prince_test.3872990624 |
| Directory | /workspace/184.prim_prince_test/latest |
| Test location | /workspace/coverage/default/185.prim_prince_test.1342054 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 1795560596 ps |
| CPU time | 30.85 seconds |
| Started | Feb 18 12:36:27 PM PST 24 |
| Finished | Feb 18 12:37:11 PM PST 24 |
| Peak memory | 146788 kb |
| Host | smart-eb6eee5a-050c-4cdb-bee7-896ef3fcf274 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1342054 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 185.prim_prince_test.1342054 |
| Directory | /workspace/185.prim_prince_test/latest |
| Test location | /workspace/coverage/default/186.prim_prince_test.3981713566 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 1431469112 ps |
| CPU time | 25.06 seconds |
| Started | Feb 18 12:36:15 PM PST 24 |
| Finished | Feb 18 12:36:53 PM PST 24 |
| Peak memory | 146780 kb |
| Host | smart-c6cc04c6-e17f-45a7-b5a6-5cd7595b02be |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3981713566 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 186.prim_prince_test.3981713566 |
| Directory | /workspace/186.prim_prince_test/latest |
| Test location | /workspace/coverage/default/187.prim_prince_test.1438991786 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 3226214898 ps |
| CPU time | 51.65 seconds |
| Started | Feb 18 12:36:25 PM PST 24 |
| Finished | Feb 18 12:37:32 PM PST 24 |
| Peak memory | 146952 kb |
| Host | smart-9ea65165-f283-4071-9d49-73c08c3b10f0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1438991786 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 187.prim_prince_test.1438991786 |
| Directory | /workspace/187.prim_prince_test/latest |
| Test location | /workspace/coverage/default/188.prim_prince_test.3944750790 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 2297888414 ps |
| CPU time | 38.62 seconds |
| Started | Feb 18 12:36:15 PM PST 24 |
| Finished | Feb 18 12:37:09 PM PST 24 |
| Peak memory | 146956 kb |
| Host | smart-f7428c4e-b3aa-45fe-b79c-5e398b9a77d3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3944750790 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 188.prim_prince_test.3944750790 |
| Directory | /workspace/188.prim_prince_test/latest |
| Test location | /workspace/coverage/default/189.prim_prince_test.1861899926 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 3156733186 ps |
| CPU time | 52.65 seconds |
| Started | Feb 18 12:36:27 PM PST 24 |
| Finished | Feb 18 12:37:37 PM PST 24 |
| Peak memory | 146952 kb |
| Host | smart-b91e8887-afdd-4863-b339-1c03d547268f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1861899926 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 189.prim_prince_test.1861899926 |
| Directory | /workspace/189.prim_prince_test/latest |
| Test location | /workspace/coverage/default/19.prim_prince_test.633651363 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 3740487406 ps |
| CPU time | 63.14 seconds |
| Started | Feb 18 12:35:57 PM PST 24 |
| Finished | Feb 18 12:37:17 PM PST 24 |
| Peak memory | 146984 kb |
| Host | smart-3434a3e5-a5e9-4ea7-beef-eea9596201cd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=633651363 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_prince_test.633651363 |
| Directory | /workspace/19.prim_prince_test/latest |
| Test location | /workspace/coverage/default/190.prim_prince_test.3638146304 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 1010866082 ps |
| CPU time | 17.34 seconds |
| Started | Feb 18 12:36:21 PM PST 24 |
| Finished | Feb 18 12:36:48 PM PST 24 |
| Peak memory | 146892 kb |
| Host | smart-b814296b-41d0-4088-ba8c-687281ba84db |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3638146304 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 190.prim_prince_test.3638146304 |
| Directory | /workspace/190.prim_prince_test/latest |
| Test location | /workspace/coverage/default/191.prim_prince_test.1783282462 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 2453889128 ps |
| CPU time | 40.29 seconds |
| Started | Feb 18 12:36:26 PM PST 24 |
| Finished | Feb 18 12:37:21 PM PST 24 |
| Peak memory | 146912 kb |
| Host | smart-46fb49bc-ea23-4fdf-87e2-d5f580deb4a6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1783282462 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 191.prim_prince_test.1783282462 |
| Directory | /workspace/191.prim_prince_test/latest |
| Test location | /workspace/coverage/default/192.prim_prince_test.3588716648 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 2520616852 ps |
| CPU time | 42.7 seconds |
| Started | Feb 18 12:36:20 PM PST 24 |
| Finished | Feb 18 12:37:19 PM PST 24 |
| Peak memory | 147012 kb |
| Host | smart-ef9f7b5d-9f27-4b1d-abba-189a356b6a54 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3588716648 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 192.prim_prince_test.3588716648 |
| Directory | /workspace/192.prim_prince_test/latest |
| Test location | /workspace/coverage/default/193.prim_prince_test.1786531616 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 2225445933 ps |
| CPU time | 38.5 seconds |
| Started | Feb 18 12:36:27 PM PST 24 |
| Finished | Feb 18 12:37:21 PM PST 24 |
| Peak memory | 146828 kb |
| Host | smart-ba011f7c-4e78-490f-86c7-40fb2e0593da |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1786531616 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 193.prim_prince_test.1786531616 |
| Directory | /workspace/193.prim_prince_test/latest |
| Test location | /workspace/coverage/default/194.prim_prince_test.1432161629 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 1523699272 ps |
| CPU time | 25.94 seconds |
| Started | Feb 18 12:36:25 PM PST 24 |
| Finished | Feb 18 12:37:03 PM PST 24 |
| Peak memory | 146828 kb |
| Host | smart-c25983e5-9abe-455d-ac12-d5d521b34316 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1432161629 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 194.prim_prince_test.1432161629 |
| Directory | /workspace/194.prim_prince_test/latest |
| Test location | /workspace/coverage/default/195.prim_prince_test.373398426 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 2506329704 ps |
| CPU time | 41.96 seconds |
| Started | Feb 18 12:36:26 PM PST 24 |
| Finished | Feb 18 12:37:24 PM PST 24 |
| Peak memory | 146964 kb |
| Host | smart-5dbf0e5e-bd91-4adb-8de1-cd88dc79f00c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=373398426 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 195.prim_prince_test.373398426 |
| Directory | /workspace/195.prim_prince_test/latest |
| Test location | /workspace/coverage/default/196.prim_prince_test.474613017 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 1285715627 ps |
| CPU time | 21.32 seconds |
| Started | Feb 18 12:36:17 PM PST 24 |
| Finished | Feb 18 12:36:51 PM PST 24 |
| Peak memory | 146816 kb |
| Host | smart-a330310d-3f24-4527-8eaa-809da266f04b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=474613017 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 196.prim_prince_test.474613017 |
| Directory | /workspace/196.prim_prince_test/latest |
| Test location | /workspace/coverage/default/197.prim_prince_test.1339710678 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 1186368770 ps |
| CPU time | 20.3 seconds |
| Started | Feb 18 12:36:27 PM PST 24 |
| Finished | Feb 18 12:36:58 PM PST 24 |
| Peak memory | 146860 kb |
| Host | smart-2ec36333-e866-4462-a5cc-d8f51cb354fb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1339710678 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 197.prim_prince_test.1339710678 |
| Directory | /workspace/197.prim_prince_test/latest |
| Test location | /workspace/coverage/default/198.prim_prince_test.3483422223 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 1996116408 ps |
| CPU time | 33.64 seconds |
| Started | Feb 18 12:36:26 PM PST 24 |
| Finished | Feb 18 12:37:13 PM PST 24 |
| Peak memory | 146832 kb |
| Host | smart-e1c63051-057d-43f2-9f9e-dcbd4b0590a2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3483422223 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 198.prim_prince_test.3483422223 |
| Directory | /workspace/198.prim_prince_test/latest |
| Test location | /workspace/coverage/default/199.prim_prince_test.3255920551 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 1952735732 ps |
| CPU time | 33.21 seconds |
| Started | Feb 18 12:36:28 PM PST 24 |
| Finished | Feb 18 12:37:15 PM PST 24 |
| Peak memory | 146916 kb |
| Host | smart-8b46308e-3d1a-4562-ac86-3cbbe16ae2da |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3255920551 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 199.prim_prince_test.3255920551 |
| Directory | /workspace/199.prim_prince_test/latest |
| Test location | /workspace/coverage/default/2.prim_prince_test.616068329 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 2712436623 ps |
| CPU time | 43.01 seconds |
| Started | Feb 18 12:37:24 PM PST 24 |
| Finished | Feb 18 12:38:16 PM PST 24 |
| Peak memory | 146336 kb |
| Host | smart-e6ebf454-ff7f-4d83-acd1-31fcbdf65eb3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=616068329 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_prince_test.616068329 |
| Directory | /workspace/2.prim_prince_test/latest |
| Test location | /workspace/coverage/default/20.prim_prince_test.2716291512 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 1166558210 ps |
| CPU time | 20.24 seconds |
| Started | Feb 18 12:36:16 PM PST 24 |
| Finished | Feb 18 12:36:48 PM PST 24 |
| Peak memory | 146892 kb |
| Host | smart-cba74cf5-42bc-4f5a-83b2-f4bb118211f4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2716291512 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_prince_test.2716291512 |
| Directory | /workspace/20.prim_prince_test/latest |
| Test location | /workspace/coverage/default/200.prim_prince_test.485944644 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 1965867490 ps |
| CPU time | 32.33 seconds |
| Started | Feb 18 12:36:24 PM PST 24 |
| Finished | Feb 18 12:37:08 PM PST 24 |
| Peak memory | 146820 kb |
| Host | smart-41698a10-9347-471e-ab8f-bbeb6a1b7868 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=485944644 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 200.prim_prince_test.485944644 |
| Directory | /workspace/200.prim_prince_test/latest |
| Test location | /workspace/coverage/default/201.prim_prince_test.3314162352 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 1375140037 ps |
| CPU time | 23.26 seconds |
| Started | Feb 18 12:36:22 PM PST 24 |
| Finished | Feb 18 12:36:57 PM PST 24 |
| Peak memory | 146836 kb |
| Host | smart-1e9c2a15-89e4-4b86-b9a4-b9ea103f24a6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3314162352 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 201.prim_prince_test.3314162352 |
| Directory | /workspace/201.prim_prince_test/latest |
| Test location | /workspace/coverage/default/202.prim_prince_test.1989988830 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 2301536213 ps |
| CPU time | 38.28 seconds |
| Started | Feb 18 12:36:22 PM PST 24 |
| Finished | Feb 18 12:37:15 PM PST 24 |
| Peak memory | 146948 kb |
| Host | smart-52e5d937-d168-40e3-8532-8fe6ea509bc2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1989988830 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 202.prim_prince_test.1989988830 |
| Directory | /workspace/202.prim_prince_test/latest |
| Test location | /workspace/coverage/default/203.prim_prince_test.132280267 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 1785578707 ps |
| CPU time | 30.4 seconds |
| Started | Feb 18 12:36:23 PM PST 24 |
| Finished | Feb 18 12:37:07 PM PST 24 |
| Peak memory | 146928 kb |
| Host | smart-dc741d48-e40a-4def-ba80-d4ea8fc9dc0c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=132280267 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 203.prim_prince_test.132280267 |
| Directory | /workspace/203.prim_prince_test/latest |
| Test location | /workspace/coverage/default/204.prim_prince_test.993789157 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 2020908999 ps |
| CPU time | 34.31 seconds |
| Started | Feb 18 12:36:21 PM PST 24 |
| Finished | Feb 18 12:37:10 PM PST 24 |
| Peak memory | 146928 kb |
| Host | smart-819c6939-b8a8-4645-9678-11cdb92e03f8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=993789157 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 204.prim_prince_test.993789157 |
| Directory | /workspace/204.prim_prince_test/latest |
| Test location | /workspace/coverage/default/205.prim_prince_test.2511530340 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 2676363585 ps |
| CPU time | 45.72 seconds |
| Started | Feb 18 12:36:26 PM PST 24 |
| Finished | Feb 18 12:37:29 PM PST 24 |
| Peak memory | 146980 kb |
| Host | smart-5d7c07dc-78b0-4ff7-8967-55109c6c26d7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2511530340 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 205.prim_prince_test.2511530340 |
| Directory | /workspace/205.prim_prince_test/latest |
| Test location | /workspace/coverage/default/206.prim_prince_test.1862506007 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 2262387612 ps |
| CPU time | 39.33 seconds |
| Started | Feb 18 12:36:15 PM PST 24 |
| Finished | Feb 18 12:37:11 PM PST 24 |
| Peak memory | 146848 kb |
| Host | smart-268da2bf-1172-4016-8467-dae527fb90d1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1862506007 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 206.prim_prince_test.1862506007 |
| Directory | /workspace/206.prim_prince_test/latest |
| Test location | /workspace/coverage/default/207.prim_prince_test.2958692016 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 3726509356 ps |
| CPU time | 62.77 seconds |
| Started | Feb 18 12:36:32 PM PST 24 |
| Finished | Feb 18 12:37:54 PM PST 24 |
| Peak memory | 146944 kb |
| Host | smart-d4ac6a42-ff87-4ea1-8af7-c52bdf62b1e6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2958692016 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 207.prim_prince_test.2958692016 |
| Directory | /workspace/207.prim_prince_test/latest |
| Test location | /workspace/coverage/default/208.prim_prince_test.1744336646 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 1557074563 ps |
| CPU time | 26.61 seconds |
| Started | Feb 18 12:36:15 PM PST 24 |
| Finished | Feb 18 12:36:54 PM PST 24 |
| Peak memory | 146816 kb |
| Host | smart-7a78a7d6-96c8-409c-b9d9-4cc479075c2b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1744336646 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 208.prim_prince_test.1744336646 |
| Directory | /workspace/208.prim_prince_test/latest |
| Test location | /workspace/coverage/default/209.prim_prince_test.3034746322 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 2998401538 ps |
| CPU time | 49.73 seconds |
| Started | Feb 18 12:36:22 PM PST 24 |
| Finished | Feb 18 12:37:29 PM PST 24 |
| Peak memory | 146976 kb |
| Host | smart-671ed5cb-fe64-47b0-a223-287d56e7965a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3034746322 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 209.prim_prince_test.3034746322 |
| Directory | /workspace/209.prim_prince_test/latest |
| Test location | /workspace/coverage/default/21.prim_prince_test.3907205098 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 832923504 ps |
| CPU time | 14.04 seconds |
| Started | Feb 18 12:35:59 PM PST 24 |
| Finished | Feb 18 12:36:19 PM PST 24 |
| Peak memory | 146728 kb |
| Host | smart-e6f55b13-cf91-43fe-8090-77d0469ae018 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3907205098 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_prince_test.3907205098 |
| Directory | /workspace/21.prim_prince_test/latest |
| Test location | /workspace/coverage/default/210.prim_prince_test.4257855255 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 2329494646 ps |
| CPU time | 39.11 seconds |
| Started | Feb 18 12:36:15 PM PST 24 |
| Finished | Feb 18 12:37:11 PM PST 24 |
| Peak memory | 146976 kb |
| Host | smart-b6d2df13-6107-4903-a044-a83b3fd080fa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4257855255 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 210.prim_prince_test.4257855255 |
| Directory | /workspace/210.prim_prince_test/latest |
| Test location | /workspace/coverage/default/211.prim_prince_test.4151767272 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 909874771 ps |
| CPU time | 15.94 seconds |
| Started | Feb 18 12:36:25 PM PST 24 |
| Finished | Feb 18 12:36:49 PM PST 24 |
| Peak memory | 146852 kb |
| Host | smart-c73ddc73-6409-4e91-9dda-0d62d1bfc46b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4151767272 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 211.prim_prince_test.4151767272 |
| Directory | /workspace/211.prim_prince_test/latest |
| Test location | /workspace/coverage/default/212.prim_prince_test.2889277556 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 2293412379 ps |
| CPU time | 40.23 seconds |
| Started | Feb 18 12:36:24 PM PST 24 |
| Finished | Feb 18 12:37:20 PM PST 24 |
| Peak memory | 146956 kb |
| Host | smart-6dd7e47b-3f6d-459c-bff6-f00c9055e6b7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2889277556 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 212.prim_prince_test.2889277556 |
| Directory | /workspace/212.prim_prince_test/latest |
| Test location | /workspace/coverage/default/213.prim_prince_test.1957163012 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 2834862951 ps |
| CPU time | 47.63 seconds |
| Started | Feb 18 12:36:22 PM PST 24 |
| Finished | Feb 18 12:37:26 PM PST 24 |
| Peak memory | 146864 kb |
| Host | smart-26baaa80-a212-4c15-ad45-dc95f7933fde |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1957163012 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 213.prim_prince_test.1957163012 |
| Directory | /workspace/213.prim_prince_test/latest |
| Test location | /workspace/coverage/default/214.prim_prince_test.3531761131 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 1157121905 ps |
| CPU time | 19.31 seconds |
| Started | Feb 18 12:36:22 PM PST 24 |
| Finished | Feb 18 12:36:51 PM PST 24 |
| Peak memory | 146744 kb |
| Host | smart-265e2b97-d376-493b-92df-f25936f42bf6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3531761131 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 214.prim_prince_test.3531761131 |
| Directory | /workspace/214.prim_prince_test/latest |
| Test location | /workspace/coverage/default/215.prim_prince_test.4004853188 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 1843645007 ps |
| CPU time | 31.61 seconds |
| Started | Feb 18 12:36:30 PM PST 24 |
| Finished | Feb 18 12:37:15 PM PST 24 |
| Peak memory | 146744 kb |
| Host | smart-c56c52a4-2ff0-4408-bc41-9ddb5a74b9a4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4004853188 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 215.prim_prince_test.4004853188 |
| Directory | /workspace/215.prim_prince_test/latest |
| Test location | /workspace/coverage/default/216.prim_prince_test.2484308587 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 2406086806 ps |
| CPU time | 40.16 seconds |
| Started | Feb 18 12:36:25 PM PST 24 |
| Finished | Feb 18 12:37:20 PM PST 24 |
| Peak memory | 146948 kb |
| Host | smart-8c2c16fa-40ea-4d5b-8316-b21c18d6cefa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2484308587 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 216.prim_prince_test.2484308587 |
| Directory | /workspace/216.prim_prince_test/latest |
| Test location | /workspace/coverage/default/217.prim_prince_test.3028452842 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 2101249652 ps |
| CPU time | 35.63 seconds |
| Started | Feb 18 12:36:19 PM PST 24 |
| Finished | Feb 18 12:37:10 PM PST 24 |
| Peak memory | 146912 kb |
| Host | smart-917508d4-38ee-4f26-b69a-e9ca9d784597 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3028452842 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 217.prim_prince_test.3028452842 |
| Directory | /workspace/217.prim_prince_test/latest |
| Test location | /workspace/coverage/default/218.prim_prince_test.2085759411 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 3314683199 ps |
| CPU time | 54.06 seconds |
| Started | Feb 18 12:36:27 PM PST 24 |
| Finished | Feb 18 12:37:37 PM PST 24 |
| Peak memory | 146956 kb |
| Host | smart-c6bd64a5-dda7-4ed5-adac-a8b825fe5654 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2085759411 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 218.prim_prince_test.2085759411 |
| Directory | /workspace/218.prim_prince_test/latest |
| Test location | /workspace/coverage/default/219.prim_prince_test.2460664462 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 1578045130 ps |
| CPU time | 25.55 seconds |
| Started | Feb 18 12:36:27 PM PST 24 |
| Finished | Feb 18 12:37:04 PM PST 24 |
| Peak memory | 146832 kb |
| Host | smart-15989cee-b713-44c4-afc6-d0a9785c5d3b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2460664462 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 219.prim_prince_test.2460664462 |
| Directory | /workspace/219.prim_prince_test/latest |
| Test location | /workspace/coverage/default/22.prim_prince_test.2078848298 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 2833482598 ps |
| CPU time | 47.03 seconds |
| Started | Feb 18 12:35:50 PM PST 24 |
| Finished | Feb 18 12:36:51 PM PST 24 |
| Peak memory | 146976 kb |
| Host | smart-3398429c-432b-40dc-bbd0-67e0d3617ca2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2078848298 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_prince_test.2078848298 |
| Directory | /workspace/22.prim_prince_test/latest |
| Test location | /workspace/coverage/default/220.prim_prince_test.4028152441 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 2663247869 ps |
| CPU time | 44.6 seconds |
| Started | Feb 18 12:36:25 PM PST 24 |
| Finished | Feb 18 12:37:25 PM PST 24 |
| Peak memory | 147088 kb |
| Host | smart-be816c56-3720-42aa-99e8-7777f3b739df |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4028152441 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 220.prim_prince_test.4028152441 |
| Directory | /workspace/220.prim_prince_test/latest |
| Test location | /workspace/coverage/default/221.prim_prince_test.516352801 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 2548613868 ps |
| CPU time | 43.31 seconds |
| Started | Feb 18 12:36:19 PM PST 24 |
| Finished | Feb 18 12:37:19 PM PST 24 |
| Peak memory | 147036 kb |
| Host | smart-6705ae57-a5c9-4007-8632-009499670fb9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=516352801 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 221.prim_prince_test.516352801 |
| Directory | /workspace/221.prim_prince_test/latest |
| Test location | /workspace/coverage/default/222.prim_prince_test.625134892 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 1740430965 ps |
| CPU time | 29.43 seconds |
| Started | Feb 18 12:36:29 PM PST 24 |
| Finished | Feb 18 12:37:12 PM PST 24 |
| Peak memory | 146928 kb |
| Host | smart-d1fc0966-02dc-4071-a884-030eed926f06 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=625134892 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 222.prim_prince_test.625134892 |
| Directory | /workspace/222.prim_prince_test/latest |
| Test location | /workspace/coverage/default/223.prim_prince_test.243725716 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 1865655022 ps |
| CPU time | 30.73 seconds |
| Started | Feb 18 12:36:21 PM PST 24 |
| Finished | Feb 18 12:37:05 PM PST 24 |
| Peak memory | 146824 kb |
| Host | smart-ac524f4f-23bb-4001-9fe5-a27ec4a306e4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=243725716 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 223.prim_prince_test.243725716 |
| Directory | /workspace/223.prim_prince_test/latest |
| Test location | /workspace/coverage/default/224.prim_prince_test.2889647445 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 1478620871 ps |
| CPU time | 24.07 seconds |
| Started | Feb 18 12:36:30 PM PST 24 |
| Finished | Feb 18 12:37:04 PM PST 24 |
| Peak memory | 146852 kb |
| Host | smart-f05681fd-bd9f-4d84-a5a3-08755606cae5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2889647445 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 224.prim_prince_test.2889647445 |
| Directory | /workspace/224.prim_prince_test/latest |
| Test location | /workspace/coverage/default/225.prim_prince_test.1502289839 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 3537628733 ps |
| CPU time | 59.18 seconds |
| Started | Feb 18 12:36:15 PM PST 24 |
| Finished | Feb 18 12:37:35 PM PST 24 |
| Peak memory | 146940 kb |
| Host | smart-8e0100e8-ffb4-4f42-af99-e452bb322c99 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1502289839 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 225.prim_prince_test.1502289839 |
| Directory | /workspace/225.prim_prince_test/latest |
| Test location | /workspace/coverage/default/226.prim_prince_test.834800164 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 2429426836 ps |
| CPU time | 40.37 seconds |
| Started | Feb 18 12:36:14 PM PST 24 |
| Finished | Feb 18 12:37:09 PM PST 24 |
| Peak memory | 146964 kb |
| Host | smart-5e5fbf71-1bbb-4acf-b13b-88278b12259d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=834800164 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 226.prim_prince_test.834800164 |
| Directory | /workspace/226.prim_prince_test/latest |
| Test location | /workspace/coverage/default/227.prim_prince_test.2869425331 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 1032100566 ps |
| CPU time | 17.73 seconds |
| Started | Feb 18 12:36:29 PM PST 24 |
| Finished | Feb 18 12:36:57 PM PST 24 |
| Peak memory | 146932 kb |
| Host | smart-a3c45fe6-cb10-4419-a382-00fa30023c98 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2869425331 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 227.prim_prince_test.2869425331 |
| Directory | /workspace/227.prim_prince_test/latest |
| Test location | /workspace/coverage/default/228.prim_prince_test.2224145294 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 2798530300 ps |
| CPU time | 45.26 seconds |
| Started | Feb 18 12:36:21 PM PST 24 |
| Finished | Feb 18 12:37:21 PM PST 24 |
| Peak memory | 146976 kb |
| Host | smart-5b0c2795-2c27-4791-b66f-d6227957e130 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2224145294 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 228.prim_prince_test.2224145294 |
| Directory | /workspace/228.prim_prince_test/latest |
| Test location | /workspace/coverage/default/229.prim_prince_test.982665363 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 3550950498 ps |
| CPU time | 61 seconds |
| Started | Feb 18 12:36:25 PM PST 24 |
| Finished | Feb 18 12:37:47 PM PST 24 |
| Peak memory | 147060 kb |
| Host | smart-679f9690-5704-4542-a86f-efed271385ce |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=982665363 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 229.prim_prince_test.982665363 |
| Directory | /workspace/229.prim_prince_test/latest |
| Test location | /workspace/coverage/default/23.prim_prince_test.4036981715 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 2039922879 ps |
| CPU time | 34.48 seconds |
| Started | Feb 18 12:35:55 PM PST 24 |
| Finished | Feb 18 12:36:40 PM PST 24 |
| Peak memory | 146780 kb |
| Host | smart-352af175-3a85-4604-a9f4-7d9725417eb1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4036981715 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_prince_test.4036981715 |
| Directory | /workspace/23.prim_prince_test/latest |
| Test location | /workspace/coverage/default/230.prim_prince_test.4050977308 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 3721768269 ps |
| CPU time | 62.19 seconds |
| Started | Feb 18 12:36:25 PM PST 24 |
| Finished | Feb 18 12:37:46 PM PST 24 |
| Peak memory | 147088 kb |
| Host | smart-fcfcfa8f-382f-4f98-8497-fde7dfa5d534 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4050977308 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 230.prim_prince_test.4050977308 |
| Directory | /workspace/230.prim_prince_test/latest |
| Test location | /workspace/coverage/default/231.prim_prince_test.1898072903 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 3487251393 ps |
| CPU time | 59.44 seconds |
| Started | Feb 18 12:36:21 PM PST 24 |
| Finished | Feb 18 12:37:41 PM PST 24 |
| Peak memory | 146956 kb |
| Host | smart-8ed4ba89-a54a-4cb0-bfb5-46dfdc4bfc6b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1898072903 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 231.prim_prince_test.1898072903 |
| Directory | /workspace/231.prim_prince_test/latest |
| Test location | /workspace/coverage/default/232.prim_prince_test.885843328 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 1038308375 ps |
| CPU time | 17.43 seconds |
| Started | Feb 18 12:36:31 PM PST 24 |
| Finished | Feb 18 12:36:58 PM PST 24 |
| Peak memory | 146824 kb |
| Host | smart-ae11c86e-a232-460e-88bc-ed0e7ef65ba8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=885843328 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 232.prim_prince_test.885843328 |
| Directory | /workspace/232.prim_prince_test/latest |
| Test location | /workspace/coverage/default/233.prim_prince_test.1681217874 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 3339078193 ps |
| CPU time | 56.45 seconds |
| Started | Feb 18 12:36:23 PM PST 24 |
| Finished | Feb 18 12:37:39 PM PST 24 |
| Peak memory | 147032 kb |
| Host | smart-e2e400e9-1c17-41fc-a14e-7be0d8a1a76e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1681217874 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 233.prim_prince_test.1681217874 |
| Directory | /workspace/233.prim_prince_test/latest |
| Test location | /workspace/coverage/default/234.prim_prince_test.1710881066 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 2108061463 ps |
| CPU time | 35.84 seconds |
| Started | Feb 18 12:36:24 PM PST 24 |
| Finished | Feb 18 12:37:14 PM PST 24 |
| Peak memory | 146856 kb |
| Host | smart-05b118d1-dc12-401e-9c29-d1d17df302e2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1710881066 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 234.prim_prince_test.1710881066 |
| Directory | /workspace/234.prim_prince_test/latest |
| Test location | /workspace/coverage/default/235.prim_prince_test.3570961804 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 1874044287 ps |
| CPU time | 32.17 seconds |
| Started | Feb 18 12:36:25 PM PST 24 |
| Finished | Feb 18 12:37:11 PM PST 24 |
| Peak memory | 146816 kb |
| Host | smart-8807fcfa-1172-496b-93b8-b97170078baa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3570961804 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 235.prim_prince_test.3570961804 |
| Directory | /workspace/235.prim_prince_test/latest |
| Test location | /workspace/coverage/default/236.prim_prince_test.327854201 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 2289214731 ps |
| CPU time | 37.11 seconds |
| Started | Feb 18 12:36:28 PM PST 24 |
| Finished | Feb 18 12:37:19 PM PST 24 |
| Peak memory | 146948 kb |
| Host | smart-d51755f9-9c2b-440a-aeb1-44a74c362f7b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=327854201 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 236.prim_prince_test.327854201 |
| Directory | /workspace/236.prim_prince_test/latest |
| Test location | /workspace/coverage/default/237.prim_prince_test.1624013525 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 2494694353 ps |
| CPU time | 40.61 seconds |
| Started | Feb 18 12:36:36 PM PST 24 |
| Finished | Feb 18 12:37:28 PM PST 24 |
| Peak memory | 146968 kb |
| Host | smart-71931de8-92b8-4561-85e6-838ea154155d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1624013525 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 237.prim_prince_test.1624013525 |
| Directory | /workspace/237.prim_prince_test/latest |
| Test location | /workspace/coverage/default/238.prim_prince_test.2194606519 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 2485068237 ps |
| CPU time | 41.4 seconds |
| Started | Feb 18 12:36:32 PM PST 24 |
| Finished | Feb 18 12:37:27 PM PST 24 |
| Peak memory | 146972 kb |
| Host | smart-8d77fda4-a2de-4db7-a470-54ff6d7a48a4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2194606519 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 238.prim_prince_test.2194606519 |
| Directory | /workspace/238.prim_prince_test/latest |
| Test location | /workspace/coverage/default/239.prim_prince_test.195585930 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 1775409673 ps |
| CPU time | 30.67 seconds |
| Started | Feb 18 12:36:29 PM PST 24 |
| Finished | Feb 18 12:37:13 PM PST 24 |
| Peak memory | 146820 kb |
| Host | smart-7377d43a-b017-4dee-9272-bc0d91555680 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=195585930 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 239.prim_prince_test.195585930 |
| Directory | /workspace/239.prim_prince_test/latest |
| Test location | /workspace/coverage/default/24.prim_prince_test.31511566 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 2345527221 ps |
| CPU time | 37.84 seconds |
| Started | Feb 18 12:35:54 PM PST 24 |
| Finished | Feb 18 12:36:41 PM PST 24 |
| Peak memory | 146984 kb |
| Host | smart-136573a2-710e-4abc-89c0-e6f1aa472d5f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=31511566 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_prince_test.31511566 |
| Directory | /workspace/24.prim_prince_test/latest |
| Test location | /workspace/coverage/default/240.prim_prince_test.3806061503 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 2140314178 ps |
| CPU time | 36.63 seconds |
| Started | Feb 18 12:36:28 PM PST 24 |
| Finished | Feb 18 12:37:21 PM PST 24 |
| Peak memory | 146944 kb |
| Host | smart-4500a6bb-20b6-45c2-9c98-220d0236a842 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3806061503 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 240.prim_prince_test.3806061503 |
| Directory | /workspace/240.prim_prince_test/latest |
| Test location | /workspace/coverage/default/241.prim_prince_test.2179770820 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 3037474046 ps |
| CPU time | 52.81 seconds |
| Started | Feb 18 12:36:28 PM PST 24 |
| Finished | Feb 18 12:37:40 PM PST 24 |
| Peak memory | 147060 kb |
| Host | smart-be6d02b4-924a-4d20-b4cd-9622a9f3d7b4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2179770820 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 241.prim_prince_test.2179770820 |
| Directory | /workspace/241.prim_prince_test/latest |
| Test location | /workspace/coverage/default/242.prim_prince_test.3394787217 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 2464326346 ps |
| CPU time | 39.95 seconds |
| Started | Feb 18 12:36:20 PM PST 24 |
| Finished | Feb 18 12:37:15 PM PST 24 |
| Peak memory | 146944 kb |
| Host | smart-652bfab2-c7da-42b0-bafe-f26b58fb3864 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3394787217 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 242.prim_prince_test.3394787217 |
| Directory | /workspace/242.prim_prince_test/latest |
| Test location | /workspace/coverage/default/243.prim_prince_test.3436473535 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 1812678652 ps |
| CPU time | 29.66 seconds |
| Started | Feb 18 12:36:36 PM PST 24 |
| Finished | Feb 18 12:37:14 PM PST 24 |
| Peak memory | 146824 kb |
| Host | smart-bc8745f1-9281-4b59-bbff-4719e7597fe2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3436473535 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 243.prim_prince_test.3436473535 |
| Directory | /workspace/243.prim_prince_test/latest |
| Test location | /workspace/coverage/default/244.prim_prince_test.1826445756 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 2181164611 ps |
| CPU time | 37.59 seconds |
| Started | Feb 18 12:36:27 PM PST 24 |
| Finished | Feb 18 12:37:20 PM PST 24 |
| Peak memory | 146956 kb |
| Host | smart-32d60c99-4fea-497f-acfc-b95ccf58efc9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1826445756 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 244.prim_prince_test.1826445756 |
| Directory | /workspace/244.prim_prince_test/latest |
| Test location | /workspace/coverage/default/245.prim_prince_test.2651496556 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 1696281726 ps |
| CPU time | 28.74 seconds |
| Started | Feb 18 12:36:43 PM PST 24 |
| Finished | Feb 18 12:37:20 PM PST 24 |
| Peak memory | 146836 kb |
| Host | smart-4d575a57-e9be-48a9-826d-e0f2cf6c81c6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2651496556 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 245.prim_prince_test.2651496556 |
| Directory | /workspace/245.prim_prince_test/latest |
| Test location | /workspace/coverage/default/246.prim_prince_test.2790923729 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 1201755182 ps |
| CPU time | 19.62 seconds |
| Started | Feb 18 12:36:23 PM PST 24 |
| Finished | Feb 18 12:36:52 PM PST 24 |
| Peak memory | 146856 kb |
| Host | smart-fdef809c-16cf-4473-821d-6828126631b0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2790923729 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 246.prim_prince_test.2790923729 |
| Directory | /workspace/246.prim_prince_test/latest |
| Test location | /workspace/coverage/default/247.prim_prince_test.4072635245 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 1646671470 ps |
| CPU time | 27.74 seconds |
| Started | Feb 18 12:36:33 PM PST 24 |
| Finished | Feb 18 12:37:11 PM PST 24 |
| Peak memory | 146820 kb |
| Host | smart-f0648220-c655-417f-8899-354fa80d53e9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4072635245 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 247.prim_prince_test.4072635245 |
| Directory | /workspace/247.prim_prince_test/latest |
| Test location | /workspace/coverage/default/248.prim_prince_test.3964804114 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 1292592906 ps |
| CPU time | 22.67 seconds |
| Started | Feb 18 12:36:28 PM PST 24 |
| Finished | Feb 18 12:37:03 PM PST 24 |
| Peak memory | 146940 kb |
| Host | smart-0f39018e-f196-4671-bfc3-deb6ed343aed |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3964804114 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 248.prim_prince_test.3964804114 |
| Directory | /workspace/248.prim_prince_test/latest |
| Test location | /workspace/coverage/default/249.prim_prince_test.3675749944 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 3332033830 ps |
| CPU time | 57.02 seconds |
| Started | Feb 18 12:36:42 PM PST 24 |
| Finished | Feb 18 12:37:55 PM PST 24 |
| Peak memory | 147040 kb |
| Host | smart-f71ba025-f771-4ba6-a2ac-99d4bda96856 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3675749944 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 249.prim_prince_test.3675749944 |
| Directory | /workspace/249.prim_prince_test/latest |
| Test location | /workspace/coverage/default/25.prim_prince_test.4036355446 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 903496883 ps |
| CPU time | 14.97 seconds |
| Started | Feb 18 12:35:55 PM PST 24 |
| Finished | Feb 18 12:36:15 PM PST 24 |
| Peak memory | 146836 kb |
| Host | smart-c7fad9de-2f41-4580-8917-4f51e8a1460b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4036355446 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_prince_test.4036355446 |
| Directory | /workspace/25.prim_prince_test/latest |
| Test location | /workspace/coverage/default/250.prim_prince_test.1585839644 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 1734950924 ps |
| CPU time | 30.12 seconds |
| Started | Feb 18 12:36:28 PM PST 24 |
| Finished | Feb 18 12:37:12 PM PST 24 |
| Peak memory | 146944 kb |
| Host | smart-bb74d01f-7b61-4e5c-8c8a-88d23fd5b2bc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1585839644 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 250.prim_prince_test.1585839644 |
| Directory | /workspace/250.prim_prince_test/latest |
| Test location | /workspace/coverage/default/251.prim_prince_test.1936467291 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 2342001704 ps |
| CPU time | 38.43 seconds |
| Started | Feb 18 12:36:38 PM PST 24 |
| Finished | Feb 18 12:37:28 PM PST 24 |
| Peak memory | 146968 kb |
| Host | smart-78ef8457-eae9-425b-8aef-4945e7cf7f16 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1936467291 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 251.prim_prince_test.1936467291 |
| Directory | /workspace/251.prim_prince_test/latest |
| Test location | /workspace/coverage/default/252.prim_prince_test.827532879 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 2081706188 ps |
| CPU time | 33.7 seconds |
| Started | Feb 18 12:36:26 PM PST 24 |
| Finished | Feb 18 12:37:13 PM PST 24 |
| Peak memory | 146772 kb |
| Host | smart-78325aea-5438-4914-94ca-46a080fc1cc5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=827532879 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 252.prim_prince_test.827532879 |
| Directory | /workspace/252.prim_prince_test/latest |
| Test location | /workspace/coverage/default/253.prim_prince_test.1340813582 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 2204568038 ps |
| CPU time | 37.19 seconds |
| Started | Feb 18 12:36:37 PM PST 24 |
| Finished | Feb 18 12:37:26 PM PST 24 |
| Peak memory | 146976 kb |
| Host | smart-a6415ce0-8b5d-422c-ba6d-73a25329abc4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1340813582 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 253.prim_prince_test.1340813582 |
| Directory | /workspace/253.prim_prince_test/latest |
| Test location | /workspace/coverage/default/254.prim_prince_test.3992058981 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 3167988039 ps |
| CPU time | 52.8 seconds |
| Started | Feb 18 12:36:29 PM PST 24 |
| Finished | Feb 18 12:37:41 PM PST 24 |
| Peak memory | 146960 kb |
| Host | smart-b07db730-9278-42ee-bad5-41e341f733af |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3992058981 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 254.prim_prince_test.3992058981 |
| Directory | /workspace/254.prim_prince_test/latest |
| Test location | /workspace/coverage/default/255.prim_prince_test.3526139913 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 2239966396 ps |
| CPU time | 37.17 seconds |
| Started | Feb 18 12:36:41 PM PST 24 |
| Finished | Feb 18 12:37:29 PM PST 24 |
| Peak memory | 146944 kb |
| Host | smart-573f6463-8cb0-40ac-991a-477775d31036 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3526139913 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 255.prim_prince_test.3526139913 |
| Directory | /workspace/255.prim_prince_test/latest |
| Test location | /workspace/coverage/default/256.prim_prince_test.1223739683 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 900320657 ps |
| CPU time | 15.51 seconds |
| Started | Feb 18 12:36:28 PM PST 24 |
| Finished | Feb 18 12:36:53 PM PST 24 |
| Peak memory | 146860 kb |
| Host | smart-524048f9-b12d-4721-b48e-f3142b232fcd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1223739683 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 256.prim_prince_test.1223739683 |
| Directory | /workspace/256.prim_prince_test/latest |
| Test location | /workspace/coverage/default/257.prim_prince_test.2790229965 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 3396503870 ps |
| CPU time | 57.93 seconds |
| Started | Feb 18 12:36:34 PM PST 24 |
| Finished | Feb 18 12:37:49 PM PST 24 |
| Peak memory | 146936 kb |
| Host | smart-1b74acbc-d238-4def-8693-f91b48bd7759 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2790229965 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 257.prim_prince_test.2790229965 |
| Directory | /workspace/257.prim_prince_test/latest |
| Test location | /workspace/coverage/default/258.prim_prince_test.4053483912 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 1244499519 ps |
| CPU time | 20.84 seconds |
| Started | Feb 18 12:36:23 PM PST 24 |
| Finished | Feb 18 12:36:54 PM PST 24 |
| Peak memory | 146892 kb |
| Host | smart-58dcbe1b-affb-40cf-b24f-ef067f089327 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4053483912 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 258.prim_prince_test.4053483912 |
| Directory | /workspace/258.prim_prince_test/latest |
| Test location | /workspace/coverage/default/259.prim_prince_test.3443828444 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 1085851918 ps |
| CPU time | 18 seconds |
| Started | Feb 18 12:36:28 PM PST 24 |
| Finished | Feb 18 12:36:56 PM PST 24 |
| Peak memory | 146828 kb |
| Host | smart-9dd4331f-d045-4af5-b109-7efee98f6879 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3443828444 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 259.prim_prince_test.3443828444 |
| Directory | /workspace/259.prim_prince_test/latest |
| Test location | /workspace/coverage/default/26.prim_prince_test.4015436842 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 2899785297 ps |
| CPU time | 46.91 seconds |
| Started | Feb 18 12:35:51 PM PST 24 |
| Finished | Feb 18 12:36:49 PM PST 24 |
| Peak memory | 146960 kb |
| Host | smart-ef43e028-21e5-472c-adb0-e73570afa6bf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4015436842 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_prince_test.4015436842 |
| Directory | /workspace/26.prim_prince_test/latest |
| Test location | /workspace/coverage/default/260.prim_prince_test.3879504890 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 3360800467 ps |
| CPU time | 57.3 seconds |
| Started | Feb 18 12:36:40 PM PST 24 |
| Finished | Feb 18 12:37:54 PM PST 24 |
| Peak memory | 146892 kb |
| Host | smart-12d7d9c8-f460-4aa0-b1e0-de07a95a8f99 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3879504890 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 260.prim_prince_test.3879504890 |
| Directory | /workspace/260.prim_prince_test/latest |
| Test location | /workspace/coverage/default/261.prim_prince_test.198262362 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 907906357 ps |
| CPU time | 15.33 seconds |
| Started | Feb 18 12:36:31 PM PST 24 |
| Finished | Feb 18 12:36:55 PM PST 24 |
| Peak memory | 146848 kb |
| Host | smart-0757722a-2b9a-419a-a81f-efcfba107515 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=198262362 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 261.prim_prince_test.198262362 |
| Directory | /workspace/261.prim_prince_test/latest |
| Test location | /workspace/coverage/default/262.prim_prince_test.3945735148 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 3351160478 ps |
| CPU time | 57.39 seconds |
| Started | Feb 18 12:36:34 PM PST 24 |
| Finished | Feb 18 12:37:49 PM PST 24 |
| Peak memory | 146936 kb |
| Host | smart-7f16125d-8a35-437c-8b67-906acf1c7d59 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3945735148 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 262.prim_prince_test.3945735148 |
| Directory | /workspace/262.prim_prince_test/latest |
| Test location | /workspace/coverage/default/263.prim_prince_test.48026818 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 2221341571 ps |
| CPU time | 37.65 seconds |
| Started | Feb 18 12:36:30 PM PST 24 |
| Finished | Feb 18 12:37:22 PM PST 24 |
| Peak memory | 146920 kb |
| Host | smart-5f22901b-9669-41c8-82cc-8248790c96bb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=48026818 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 263.prim_prince_test.48026818 |
| Directory | /workspace/263.prim_prince_test/latest |
| Test location | /workspace/coverage/default/264.prim_prince_test.573849085 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 2566059123 ps |
| CPU time | 42.97 seconds |
| Started | Feb 18 12:36:38 PM PST 24 |
| Finished | Feb 18 12:37:33 PM PST 24 |
| Peak memory | 146972 kb |
| Host | smart-3874634b-ade3-496c-a41c-0270a48d0f28 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=573849085 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 264.prim_prince_test.573849085 |
| Directory | /workspace/264.prim_prince_test/latest |
| Test location | /workspace/coverage/default/265.prim_prince_test.2584918490 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 1619869273 ps |
| CPU time | 27.26 seconds |
| Started | Feb 18 12:36:25 PM PST 24 |
| Finished | Feb 18 12:37:05 PM PST 24 |
| Peak memory | 146760 kb |
| Host | smart-0617477f-4598-4074-a148-858baba2111c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2584918490 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 265.prim_prince_test.2584918490 |
| Directory | /workspace/265.prim_prince_test/latest |
| Test location | /workspace/coverage/default/266.prim_prince_test.920611708 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 2736572735 ps |
| CPU time | 45.38 seconds |
| Started | Feb 18 12:36:34 PM PST 24 |
| Finished | Feb 18 12:37:33 PM PST 24 |
| Peak memory | 146988 kb |
| Host | smart-ba933786-75fd-4557-ab0b-e67ec7e96d2e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=920611708 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 266.prim_prince_test.920611708 |
| Directory | /workspace/266.prim_prince_test/latest |
| Test location | /workspace/coverage/default/267.prim_prince_test.3509536583 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 3272067791 ps |
| CPU time | 53.78 seconds |
| Started | Feb 18 12:36:34 PM PST 24 |
| Finished | Feb 18 12:37:43 PM PST 24 |
| Peak memory | 146976 kb |
| Host | smart-298c3186-585e-40c4-b6d4-b347da85b6d0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3509536583 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 267.prim_prince_test.3509536583 |
| Directory | /workspace/267.prim_prince_test/latest |
| Test location | /workspace/coverage/default/268.prim_prince_test.202579649 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 3007039301 ps |
| CPU time | 50.1 seconds |
| Started | Feb 18 12:36:36 PM PST 24 |
| Finished | Feb 18 12:37:42 PM PST 24 |
| Peak memory | 146976 kb |
| Host | smart-754977cc-38ae-401b-93bb-b20861f61d32 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=202579649 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 268.prim_prince_test.202579649 |
| Directory | /workspace/268.prim_prince_test/latest |
| Test location | /workspace/coverage/default/269.prim_prince_test.2781357223 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 1307225146 ps |
| CPU time | 22.89 seconds |
| Started | Feb 18 12:36:30 PM PST 24 |
| Finished | Feb 18 12:37:04 PM PST 24 |
| Peak memory | 146836 kb |
| Host | smart-0cd2edc9-783c-4924-aea6-c3efbec4112e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2781357223 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 269.prim_prince_test.2781357223 |
| Directory | /workspace/269.prim_prince_test/latest |
| Test location | /workspace/coverage/default/27.prim_prince_test.879700088 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 3394561968 ps |
| CPU time | 55.51 seconds |
| Started | Feb 18 12:36:00 PM PST 24 |
| Finished | Feb 18 12:37:11 PM PST 24 |
| Peak memory | 146984 kb |
| Host | smart-8930623c-b517-4919-9737-076d138b0f70 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=879700088 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_prince_test.879700088 |
| Directory | /workspace/27.prim_prince_test/latest |
| Test location | /workspace/coverage/default/270.prim_prince_test.38195337 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 2030800883 ps |
| CPU time | 34.96 seconds |
| Started | Feb 18 12:36:29 PM PST 24 |
| Finished | Feb 18 12:37:18 PM PST 24 |
| Peak memory | 146940 kb |
| Host | smart-b97eae7b-37ef-4ae2-90ec-0616f6b4ad30 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=38195337 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 270.prim_prince_test.38195337 |
| Directory | /workspace/270.prim_prince_test/latest |
| Test location | /workspace/coverage/default/271.prim_prince_test.1867391788 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 2849676248 ps |
| CPU time | 48.74 seconds |
| Started | Feb 18 12:36:31 PM PST 24 |
| Finished | Feb 18 12:37:37 PM PST 24 |
| Peak memory | 146960 kb |
| Host | smart-30787f1c-e203-4edb-8b2f-b11c86753d65 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1867391788 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 271.prim_prince_test.1867391788 |
| Directory | /workspace/271.prim_prince_test/latest |
| Test location | /workspace/coverage/default/272.prim_prince_test.107964883 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 1397906602 ps |
| CPU time | 23.91 seconds |
| Started | Feb 18 12:36:31 PM PST 24 |
| Finished | Feb 18 12:37:06 PM PST 24 |
| Peak memory | 146876 kb |
| Host | smart-9ff3473d-350e-4b3c-8c7b-5b37c0d9def2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=107964883 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 272.prim_prince_test.107964883 |
| Directory | /workspace/272.prim_prince_test/latest |
| Test location | /workspace/coverage/default/273.prim_prince_test.915805478 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 1463301668 ps |
| CPU time | 25.04 seconds |
| Started | Feb 18 12:36:29 PM PST 24 |
| Finished | Feb 18 12:37:07 PM PST 24 |
| Peak memory | 146856 kb |
| Host | smart-37a282e4-e847-4540-8b7a-a1f4664695eb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=915805478 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 273.prim_prince_test.915805478 |
| Directory | /workspace/273.prim_prince_test/latest |
| Test location | /workspace/coverage/default/274.prim_prince_test.1129778427 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 1565363615 ps |
| CPU time | 25.31 seconds |
| Started | Feb 18 12:36:34 PM PST 24 |
| Finished | Feb 18 12:37:08 PM PST 24 |
| Peak memory | 146828 kb |
| Host | smart-0cc348c2-1927-45c5-8bad-96dba14917ab |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1129778427 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 274.prim_prince_test.1129778427 |
| Directory | /workspace/274.prim_prince_test/latest |
| Test location | /workspace/coverage/default/275.prim_prince_test.601922386 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 777310999 ps |
| CPU time | 13.71 seconds |
| Started | Feb 18 12:36:26 PM PST 24 |
| Finished | Feb 18 12:36:49 PM PST 24 |
| Peak memory | 146868 kb |
| Host | smart-5d7d146c-368c-4e16-a1f0-1d5b77b20fba |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=601922386 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 275.prim_prince_test.601922386 |
| Directory | /workspace/275.prim_prince_test/latest |
| Test location | /workspace/coverage/default/276.prim_prince_test.1930718870 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 1975591025 ps |
| CPU time | 34.02 seconds |
| Started | Feb 18 12:36:38 PM PST 24 |
| Finished | Feb 18 12:37:25 PM PST 24 |
| Peak memory | 146856 kb |
| Host | smart-0e3bb479-a96e-4518-9540-c83ac32aa074 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1930718870 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 276.prim_prince_test.1930718870 |
| Directory | /workspace/276.prim_prince_test/latest |
| Test location | /workspace/coverage/default/277.prim_prince_test.714057876 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 2285505133 ps |
| CPU time | 39.25 seconds |
| Started | Feb 18 12:36:37 PM PST 24 |
| Finished | Feb 18 12:37:29 PM PST 24 |
| Peak memory | 147060 kb |
| Host | smart-d8ed5c84-22fd-4572-8d9f-c302137f4852 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=714057876 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 277.prim_prince_test.714057876 |
| Directory | /workspace/277.prim_prince_test/latest |
| Test location | /workspace/coverage/default/278.prim_prince_test.191758417 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 3435004950 ps |
| CPU time | 57.16 seconds |
| Started | Feb 18 12:36:40 PM PST 24 |
| Finished | Feb 18 12:37:52 PM PST 24 |
| Peak memory | 146940 kb |
| Host | smart-55b0319d-9495-42b0-84e0-af06055dabc9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=191758417 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 278.prim_prince_test.191758417 |
| Directory | /workspace/278.prim_prince_test/latest |
| Test location | /workspace/coverage/default/279.prim_prince_test.3136918060 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 3507907830 ps |
| CPU time | 60.54 seconds |
| Started | Feb 18 12:36:44 PM PST 24 |
| Finished | Feb 18 12:38:02 PM PST 24 |
| Peak memory | 147064 kb |
| Host | smart-d9b7b4dd-32eb-4b0e-bc4c-92f6a872ab4e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3136918060 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 279.prim_prince_test.3136918060 |
| Directory | /workspace/279.prim_prince_test/latest |
| Test location | /workspace/coverage/default/28.prim_prince_test.660994375 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 1613610747 ps |
| CPU time | 27.31 seconds |
| Started | Feb 18 12:35:59 PM PST 24 |
| Finished | Feb 18 12:36:36 PM PST 24 |
| Peak memory | 146868 kb |
| Host | smart-81b75a0e-64ef-4792-8f24-8cc56aaa2bad |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=660994375 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_prince_test.660994375 |
| Directory | /workspace/28.prim_prince_test/latest |
| Test location | /workspace/coverage/default/280.prim_prince_test.2897390330 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 1679557757 ps |
| CPU time | 28.73 seconds |
| Started | Feb 18 12:36:40 PM PST 24 |
| Finished | Feb 18 12:37:18 PM PST 24 |
| Peak memory | 146920 kb |
| Host | smart-9c687399-5e3b-4129-a2d5-cf7d405cbcd2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2897390330 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 280.prim_prince_test.2897390330 |
| Directory | /workspace/280.prim_prince_test/latest |
| Test location | /workspace/coverage/default/281.prim_prince_test.912500264 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 2740789284 ps |
| CPU time | 45.72 seconds |
| Started | Feb 18 12:36:28 PM PST 24 |
| Finished | Feb 18 12:37:32 PM PST 24 |
| Peak memory | 146960 kb |
| Host | smart-fc863e2f-f04e-4481-955a-1a65bf1113f3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=912500264 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 281.prim_prince_test.912500264 |
| Directory | /workspace/281.prim_prince_test/latest |
| Test location | /workspace/coverage/default/282.prim_prince_test.3376821111 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 1641492594 ps |
| CPU time | 27.29 seconds |
| Started | Feb 18 12:36:36 PM PST 24 |
| Finished | Feb 18 12:37:12 PM PST 24 |
| Peak memory | 146828 kb |
| Host | smart-24c19048-7c0c-4098-8a6e-7b6be7d64062 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3376821111 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 282.prim_prince_test.3376821111 |
| Directory | /workspace/282.prim_prince_test/latest |
| Test location | /workspace/coverage/default/283.prim_prince_test.1906332604 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 2090076534 ps |
| CPU time | 35.44 seconds |
| Started | Feb 18 12:36:43 PM PST 24 |
| Finished | Feb 18 12:37:28 PM PST 24 |
| Peak memory | 146860 kb |
| Host | smart-d82d184d-ebe4-4029-adcd-45d9b3c03d3d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1906332604 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 283.prim_prince_test.1906332604 |
| Directory | /workspace/283.prim_prince_test/latest |
| Test location | /workspace/coverage/default/284.prim_prince_test.2935588673 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 3585666149 ps |
| CPU time | 58.89 seconds |
| Started | Feb 18 12:36:30 PM PST 24 |
| Finished | Feb 18 12:37:47 PM PST 24 |
| Peak memory | 146944 kb |
| Host | smart-bb02ee56-3fed-4a1a-9de5-8906def268f1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2935588673 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 284.prim_prince_test.2935588673 |
| Directory | /workspace/284.prim_prince_test/latest |
| Test location | /workspace/coverage/default/285.prim_prince_test.3462256605 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 954529094 ps |
| CPU time | 15.87 seconds |
| Started | Feb 18 12:36:36 PM PST 24 |
| Finished | Feb 18 12:36:58 PM PST 24 |
| Peak memory | 146852 kb |
| Host | smart-84834b2e-b56a-4e91-9df3-4504ad4d8d74 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3462256605 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 285.prim_prince_test.3462256605 |
| Directory | /workspace/285.prim_prince_test/latest |
| Test location | /workspace/coverage/default/286.prim_prince_test.576276225 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 3184876419 ps |
| CPU time | 52.42 seconds |
| Started | Feb 18 12:36:36 PM PST 24 |
| Finished | Feb 18 12:37:43 PM PST 24 |
| Peak memory | 146944 kb |
| Host | smart-ac984566-0b28-4adf-aa15-b7f935006a6d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=576276225 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 286.prim_prince_test.576276225 |
| Directory | /workspace/286.prim_prince_test/latest |
| Test location | /workspace/coverage/default/287.prim_prince_test.3459437181 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 935582845 ps |
| CPU time | 15.7 seconds |
| Started | Feb 18 12:36:31 PM PST 24 |
| Finished | Feb 18 12:36:56 PM PST 24 |
| Peak memory | 146852 kb |
| Host | smart-f0d36a58-6228-45b9-8a45-8cfcdbc430a4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3459437181 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 287.prim_prince_test.3459437181 |
| Directory | /workspace/287.prim_prince_test/latest |
| Test location | /workspace/coverage/default/288.prim_prince_test.415262116 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 3360811643 ps |
| CPU time | 56.72 seconds |
| Started | Feb 18 12:36:36 PM PST 24 |
| Finished | Feb 18 12:37:50 PM PST 24 |
| Peak memory | 146936 kb |
| Host | smart-752bd100-ec85-4f00-9fc8-1abea03f924e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=415262116 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 288.prim_prince_test.415262116 |
| Directory | /workspace/288.prim_prince_test/latest |
| Test location | /workspace/coverage/default/289.prim_prince_test.3039718198 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 3383988964 ps |
| CPU time | 55.15 seconds |
| Started | Feb 18 12:36:34 PM PST 24 |
| Finished | Feb 18 12:37:44 PM PST 24 |
| Peak memory | 146948 kb |
| Host | smart-c5be539a-0bee-421f-a407-b01f322c1edd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3039718198 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 289.prim_prince_test.3039718198 |
| Directory | /workspace/289.prim_prince_test/latest |
| Test location | /workspace/coverage/default/29.prim_prince_test.3024362607 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 3162073397 ps |
| CPU time | 51.94 seconds |
| Started | Feb 18 12:36:08 PM PST 24 |
| Finished | Feb 18 12:37:12 PM PST 24 |
| Peak memory | 146952 kb |
| Host | smart-2b16ac84-fe16-4754-806d-777c4c8464ee |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3024362607 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_prince_test.3024362607 |
| Directory | /workspace/29.prim_prince_test/latest |
| Test location | /workspace/coverage/default/290.prim_prince_test.3253172764 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 3720141263 ps |
| CPU time | 63.16 seconds |
| Started | Feb 18 12:36:26 PM PST 24 |
| Finished | Feb 18 12:37:52 PM PST 24 |
| Peak memory | 146956 kb |
| Host | smart-9f3b2cc6-7df0-4da2-b3ba-feb016448b31 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3253172764 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 290.prim_prince_test.3253172764 |
| Directory | /workspace/290.prim_prince_test/latest |
| Test location | /workspace/coverage/default/291.prim_prince_test.178073738 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 796124137 ps |
| CPU time | 13.47 seconds |
| Started | Feb 18 12:36:25 PM PST 24 |
| Finished | Feb 18 12:36:47 PM PST 24 |
| Peak memory | 146832 kb |
| Host | smart-9228214b-c4bf-4d96-92b9-aa988c248d36 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=178073738 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 291.prim_prince_test.178073738 |
| Directory | /workspace/291.prim_prince_test/latest |
| Test location | /workspace/coverage/default/292.prim_prince_test.1893582861 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 2009194695 ps |
| CPU time | 34.59 seconds |
| Started | Feb 18 12:36:30 PM PST 24 |
| Finished | Feb 18 12:37:19 PM PST 24 |
| Peak memory | 146920 kb |
| Host | smart-3022ee90-e4b1-4d7c-9e78-b15bed551a8c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1893582861 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 292.prim_prince_test.1893582861 |
| Directory | /workspace/292.prim_prince_test/latest |
| Test location | /workspace/coverage/default/293.prim_prince_test.881499013 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 1863737205 ps |
| CPU time | 32.04 seconds |
| Started | Feb 18 12:36:32 PM PST 24 |
| Finished | Feb 18 12:37:16 PM PST 24 |
| Peak memory | 146812 kb |
| Host | smart-1b97dea2-3f3a-4208-96c6-4da97fb9b712 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=881499013 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 293.prim_prince_test.881499013 |
| Directory | /workspace/293.prim_prince_test/latest |
| Test location | /workspace/coverage/default/294.prim_prince_test.1017029308 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 2885157280 ps |
| CPU time | 47.84 seconds |
| Started | Feb 18 12:36:38 PM PST 24 |
| Finished | Feb 18 12:37:39 PM PST 24 |
| Peak memory | 146976 kb |
| Host | smart-a2d34561-5ff2-448f-91de-05bed1d99d55 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1017029308 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 294.prim_prince_test.1017029308 |
| Directory | /workspace/294.prim_prince_test/latest |
| Test location | /workspace/coverage/default/295.prim_prince_test.827063223 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 2098364093 ps |
| CPU time | 36.04 seconds |
| Started | Feb 18 12:36:47 PM PST 24 |
| Finished | Feb 18 12:37:34 PM PST 24 |
| Peak memory | 146768 kb |
| Host | smart-1c923c65-642a-44fa-932b-f156ba047cdf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=827063223 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 295.prim_prince_test.827063223 |
| Directory | /workspace/295.prim_prince_test/latest |
| Test location | /workspace/coverage/default/296.prim_prince_test.500736358 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 778386344 ps |
| CPU time | 12.67 seconds |
| Started | Feb 18 12:36:44 PM PST 24 |
| Finished | Feb 18 12:37:00 PM PST 24 |
| Peak memory | 146828 kb |
| Host | smart-fa5b1847-ab42-43c9-8a80-31fac07b5399 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=500736358 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 296.prim_prince_test.500736358 |
| Directory | /workspace/296.prim_prince_test/latest |
| Test location | /workspace/coverage/default/297.prim_prince_test.657163972 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 1416408044 ps |
| CPU time | 23.68 seconds |
| Started | Feb 18 12:36:31 PM PST 24 |
| Finished | Feb 18 12:37:05 PM PST 24 |
| Peak memory | 146832 kb |
| Host | smart-907fd1c1-5606-451b-a21f-769e565ca402 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=657163972 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 297.prim_prince_test.657163972 |
| Directory | /workspace/297.prim_prince_test/latest |
| Test location | /workspace/coverage/default/298.prim_prince_test.375516415 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 1295355023 ps |
| CPU time | 21.22 seconds |
| Started | Feb 18 12:36:29 PM PST 24 |
| Finished | Feb 18 12:37:01 PM PST 24 |
| Peak memory | 146756 kb |
| Host | smart-2d6554d8-526d-4869-8446-6fb4a715572b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=375516415 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 298.prim_prince_test.375516415 |
| Directory | /workspace/298.prim_prince_test/latest |
| Test location | /workspace/coverage/default/299.prim_prince_test.3275837203 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 3656408856 ps |
| CPU time | 58.96 seconds |
| Started | Feb 18 12:36:38 PM PST 24 |
| Finished | Feb 18 12:37:51 PM PST 24 |
| Peak memory | 146952 kb |
| Host | smart-3963fbd8-2483-49e4-96a4-f7f5ef910db2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3275837203 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 299.prim_prince_test.3275837203 |
| Directory | /workspace/299.prim_prince_test/latest |
| Test location | /workspace/coverage/default/3.prim_prince_test.2474781323 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 3503561406 ps |
| CPU time | 58.82 seconds |
| Started | Feb 18 12:35:53 PM PST 24 |
| Finished | Feb 18 12:37:08 PM PST 24 |
| Peak memory | 146972 kb |
| Host | smart-bc347ac8-79d2-49c2-9e8c-bccd3549c223 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2474781323 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_prince_test.2474781323 |
| Directory | /workspace/3.prim_prince_test/latest |
| Test location | /workspace/coverage/default/30.prim_prince_test.3967725484 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 3000480272 ps |
| CPU time | 50.44 seconds |
| Started | Feb 18 12:35:49 PM PST 24 |
| Finished | Feb 18 12:36:54 PM PST 24 |
| Peak memory | 146964 kb |
| Host | smart-b2875476-3cf9-4ebb-a375-0b7321fc9ee0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3967725484 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_prince_test.3967725484 |
| Directory | /workspace/30.prim_prince_test/latest |
| Test location | /workspace/coverage/default/300.prim_prince_test.2601180068 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 863207738 ps |
| CPU time | 14.74 seconds |
| Started | Feb 18 12:36:33 PM PST 24 |
| Finished | Feb 18 12:36:56 PM PST 24 |
| Peak memory | 146824 kb |
| Host | smart-95e205e2-ff79-4a47-bb7f-3aa3790555e5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2601180068 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 300.prim_prince_test.2601180068 |
| Directory | /workspace/300.prim_prince_test/latest |
| Test location | /workspace/coverage/default/301.prim_prince_test.3945206996 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 3442300740 ps |
| CPU time | 56.23 seconds |
| Started | Feb 18 12:36:36 PM PST 24 |
| Finished | Feb 18 12:37:47 PM PST 24 |
| Peak memory | 146976 kb |
| Host | smart-84674da7-1edd-44a2-9353-99bd0cc73380 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3945206996 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 301.prim_prince_test.3945206996 |
| Directory | /workspace/301.prim_prince_test/latest |
| Test location | /workspace/coverage/default/302.prim_prince_test.3034353052 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 2717224558 ps |
| CPU time | 45.47 seconds |
| Started | Feb 18 12:36:29 PM PST 24 |
| Finished | Feb 18 12:37:32 PM PST 24 |
| Peak memory | 146948 kb |
| Host | smart-cef1c3fe-8509-47ac-b971-fbade836bf67 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3034353052 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 302.prim_prince_test.3034353052 |
| Directory | /workspace/302.prim_prince_test/latest |
| Test location | /workspace/coverage/default/303.prim_prince_test.2733917892 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 2455827327 ps |
| CPU time | 41.63 seconds |
| Started | Feb 18 12:36:29 PM PST 24 |
| Finished | Feb 18 12:37:27 PM PST 24 |
| Peak memory | 146956 kb |
| Host | smart-accf3098-835c-4fd2-a265-e29a65076210 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2733917892 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 303.prim_prince_test.2733917892 |
| Directory | /workspace/303.prim_prince_test/latest |
| Test location | /workspace/coverage/default/304.prim_prince_test.3996784762 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 2058518386 ps |
| CPU time | 33.85 seconds |
| Started | Feb 18 12:36:36 PM PST 24 |
| Finished | Feb 18 12:37:20 PM PST 24 |
| Peak memory | 146856 kb |
| Host | smart-4b743f7a-038e-4cde-b6a4-409b84bee2e8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3996784762 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 304.prim_prince_test.3996784762 |
| Directory | /workspace/304.prim_prince_test/latest |
| Test location | /workspace/coverage/default/305.prim_prince_test.1652894486 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 3404320656 ps |
| CPU time | 55.41 seconds |
| Started | Feb 18 12:36:38 PM PST 24 |
| Finished | Feb 18 12:37:48 PM PST 24 |
| Peak memory | 146952 kb |
| Host | smart-a0110856-2fb7-445e-aa0a-c38d1bef703a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1652894486 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 305.prim_prince_test.1652894486 |
| Directory | /workspace/305.prim_prince_test/latest |
| Test location | /workspace/coverage/default/306.prim_prince_test.2020717608 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 3605612733 ps |
| CPU time | 59.86 seconds |
| Started | Feb 18 12:36:44 PM PST 24 |
| Finished | Feb 18 12:37:59 PM PST 24 |
| Peak memory | 146956 kb |
| Host | smart-50be106d-ed47-4ac7-9eb8-5071bae01a16 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2020717608 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 306.prim_prince_test.2020717608 |
| Directory | /workspace/306.prim_prince_test/latest |
| Test location | /workspace/coverage/default/307.prim_prince_test.3685555264 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 1623228729 ps |
| CPU time | 27.58 seconds |
| Started | Feb 18 12:36:38 PM PST 24 |
| Finished | Feb 18 12:37:15 PM PST 24 |
| Peak memory | 146856 kb |
| Host | smart-8fe29002-4443-4719-81c8-dd8c45c3fde4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3685555264 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 307.prim_prince_test.3685555264 |
| Directory | /workspace/307.prim_prince_test/latest |
| Test location | /workspace/coverage/default/308.prim_prince_test.2344242230 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 851462660 ps |
| CPU time | 14.49 seconds |
| Started | Feb 18 12:36:38 PM PST 24 |
| Finished | Feb 18 12:36:59 PM PST 24 |
| Peak memory | 146836 kb |
| Host | smart-d7d7ad5a-8bd7-4988-ac8c-f9901b92d495 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2344242230 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 308.prim_prince_test.2344242230 |
| Directory | /workspace/308.prim_prince_test/latest |
| Test location | /workspace/coverage/default/309.prim_prince_test.2079489217 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 2077112002 ps |
| CPU time | 35.48 seconds |
| Started | Feb 18 12:36:41 PM PST 24 |
| Finished | Feb 18 12:37:27 PM PST 24 |
| Peak memory | 146908 kb |
| Host | smart-921a4ab5-ecac-4eb9-b994-88d4c8fc13c4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2079489217 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 309.prim_prince_test.2079489217 |
| Directory | /workspace/309.prim_prince_test/latest |
| Test location | /workspace/coverage/default/31.prim_prince_test.744786276 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 1971004661 ps |
| CPU time | 33.44 seconds |
| Started | Feb 18 12:36:03 PM PST 24 |
| Finished | Feb 18 12:36:47 PM PST 24 |
| Peak memory | 146896 kb |
| Host | smart-62d382ee-4925-4910-ab99-ca68506d16a1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=744786276 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_prince_test.744786276 |
| Directory | /workspace/31.prim_prince_test/latest |
| Test location | /workspace/coverage/default/310.prim_prince_test.2541449164 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 2560142298 ps |
| CPU time | 43.32 seconds |
| Started | Feb 18 12:36:33 PM PST 24 |
| Finished | Feb 18 12:37:30 PM PST 24 |
| Peak memory | 146960 kb |
| Host | smart-1ff9f9a8-cfbf-4348-a4d6-24ab7cb53662 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2541449164 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 310.prim_prince_test.2541449164 |
| Directory | /workspace/310.prim_prince_test/latest |
| Test location | /workspace/coverage/default/311.prim_prince_test.1169661393 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 2558535972 ps |
| CPU time | 42.59 seconds |
| Started | Feb 18 12:36:38 PM PST 24 |
| Finished | Feb 18 12:37:33 PM PST 24 |
| Peak memory | 146976 kb |
| Host | smart-c6af3b95-b300-4671-9c29-5c134895f0c3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1169661393 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 311.prim_prince_test.1169661393 |
| Directory | /workspace/311.prim_prince_test/latest |
| Test location | /workspace/coverage/default/312.prim_prince_test.391886060 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 1500584205 ps |
| CPU time | 25.19 seconds |
| Started | Feb 18 12:36:38 PM PST 24 |
| Finished | Feb 18 12:37:12 PM PST 24 |
| Peak memory | 146688 kb |
| Host | smart-84290559-3165-4200-8ff5-8ccc4b7b7641 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=391886060 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 312.prim_prince_test.391886060 |
| Directory | /workspace/312.prim_prince_test/latest |
| Test location | /workspace/coverage/default/313.prim_prince_test.4046505055 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 3007263621 ps |
| CPU time | 49.45 seconds |
| Started | Feb 18 12:36:40 PM PST 24 |
| Finished | Feb 18 12:37:43 PM PST 24 |
| Peak memory | 146944 kb |
| Host | smart-a4cf45d0-b5ab-41d4-90e3-c0f32f7f795d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4046505055 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 313.prim_prince_test.4046505055 |
| Directory | /workspace/313.prim_prince_test/latest |
| Test location | /workspace/coverage/default/314.prim_prince_test.559483907 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 3374206672 ps |
| CPU time | 55.9 seconds |
| Started | Feb 18 12:36:48 PM PST 24 |
| Finished | Feb 18 12:37:58 PM PST 24 |
| Peak memory | 146964 kb |
| Host | smart-97708b44-1256-48ef-8ae1-67e985368e86 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=559483907 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 314.prim_prince_test.559483907 |
| Directory | /workspace/314.prim_prince_test/latest |
| Test location | /workspace/coverage/default/315.prim_prince_test.1424840781 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 2696222056 ps |
| CPU time | 44.99 seconds |
| Started | Feb 18 12:36:43 PM PST 24 |
| Finished | Feb 18 12:37:40 PM PST 24 |
| Peak memory | 146968 kb |
| Host | smart-c108fefa-def8-42d9-8ce8-2e728e99a004 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1424840781 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 315.prim_prince_test.1424840781 |
| Directory | /workspace/315.prim_prince_test/latest |
| Test location | /workspace/coverage/default/316.prim_prince_test.1845072288 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 3441690644 ps |
| CPU time | 56.99 seconds |
| Started | Feb 18 12:36:40 PM PST 24 |
| Finished | Feb 18 12:37:52 PM PST 24 |
| Peak memory | 146956 kb |
| Host | smart-df0ecd8e-8b1d-497c-9a84-414516661f52 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1845072288 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 316.prim_prince_test.1845072288 |
| Directory | /workspace/316.prim_prince_test/latest |
| Test location | /workspace/coverage/default/317.prim_prince_test.4115396904 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 2883488417 ps |
| CPU time | 48.64 seconds |
| Started | Feb 18 12:36:35 PM PST 24 |
| Finished | Feb 18 12:37:39 PM PST 24 |
| Peak memory | 146960 kb |
| Host | smart-1cce3b92-c6a9-4b21-9dbc-150387d6e6c0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4115396904 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 317.prim_prince_test.4115396904 |
| Directory | /workspace/317.prim_prince_test/latest |
| Test location | /workspace/coverage/default/318.prim_prince_test.4024660901 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 2538703001 ps |
| CPU time | 43.19 seconds |
| Started | Feb 18 12:36:38 PM PST 24 |
| Finished | Feb 18 12:37:34 PM PST 24 |
| Peak memory | 146976 kb |
| Host | smart-e1da58ca-70cd-4f6f-9499-f352119b8ae6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4024660901 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 318.prim_prince_test.4024660901 |
| Directory | /workspace/318.prim_prince_test/latest |
| Test location | /workspace/coverage/default/319.prim_prince_test.1591058897 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 1710209206 ps |
| CPU time | 28.8 seconds |
| Started | Feb 18 12:36:46 PM PST 24 |
| Finished | Feb 18 12:37:23 PM PST 24 |
| Peak memory | 146848 kb |
| Host | smart-c572b9a0-688e-4aca-ace7-8bd10e94aeae |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1591058897 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 319.prim_prince_test.1591058897 |
| Directory | /workspace/319.prim_prince_test/latest |
| Test location | /workspace/coverage/default/32.prim_prince_test.2084340292 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 1570358702 ps |
| CPU time | 27.55 seconds |
| Started | Feb 18 12:36:16 PM PST 24 |
| Finished | Feb 18 12:36:57 PM PST 24 |
| Peak memory | 146892 kb |
| Host | smart-e1bdc11c-47bb-4b47-9eb8-f2a69cf42583 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2084340292 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_prince_test.2084340292 |
| Directory | /workspace/32.prim_prince_test/latest |
| Test location | /workspace/coverage/default/320.prim_prince_test.3112057240 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 1106864900 ps |
| CPU time | 17.95 seconds |
| Started | Feb 18 12:36:44 PM PST 24 |
| Finished | Feb 18 12:37:07 PM PST 24 |
| Peak memory | 146832 kb |
| Host | smart-c66c8f7d-b2f9-439a-8927-e4a2d5265d41 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3112057240 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 320.prim_prince_test.3112057240 |
| Directory | /workspace/320.prim_prince_test/latest |
| Test location | /workspace/coverage/default/321.prim_prince_test.2869191338 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 1682418794 ps |
| CPU time | 28.03 seconds |
| Started | Feb 18 12:36:46 PM PST 24 |
| Finished | Feb 18 12:37:22 PM PST 24 |
| Peak memory | 146820 kb |
| Host | smart-1434a9f5-880d-41a2-b9f4-03c06641429e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2869191338 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 321.prim_prince_test.2869191338 |
| Directory | /workspace/321.prim_prince_test/latest |
| Test location | /workspace/coverage/default/322.prim_prince_test.3564521979 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 2969097462 ps |
| CPU time | 49.98 seconds |
| Started | Feb 18 12:36:35 PM PST 24 |
| Finished | Feb 18 12:37:40 PM PST 24 |
| Peak memory | 146960 kb |
| Host | smart-d933b12a-0d01-4859-ac4c-22cb4a3a0090 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3564521979 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 322.prim_prince_test.3564521979 |
| Directory | /workspace/322.prim_prince_test/latest |
| Test location | /workspace/coverage/default/323.prim_prince_test.2222803814 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 3221571056 ps |
| CPU time | 51.73 seconds |
| Started | Feb 18 12:36:40 PM PST 24 |
| Finished | Feb 18 12:37:45 PM PST 24 |
| Peak memory | 146968 kb |
| Host | smart-5137f3ff-e964-4393-8d4f-bde3b9d1f2fe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2222803814 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 323.prim_prince_test.2222803814 |
| Directory | /workspace/323.prim_prince_test/latest |
| Test location | /workspace/coverage/default/324.prim_prince_test.2435680480 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 3480630154 ps |
| CPU time | 58.3 seconds |
| Started | Feb 18 12:36:50 PM PST 24 |
| Finished | Feb 18 12:38:03 PM PST 24 |
| Peak memory | 146840 kb |
| Host | smart-641f56e0-862d-4fa9-9325-2b43ae2618ca |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2435680480 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 324.prim_prince_test.2435680480 |
| Directory | /workspace/324.prim_prince_test/latest |
| Test location | /workspace/coverage/default/325.prim_prince_test.459982249 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 2054309701 ps |
| CPU time | 34.89 seconds |
| Started | Feb 18 12:36:36 PM PST 24 |
| Finished | Feb 18 12:37:23 PM PST 24 |
| Peak memory | 146844 kb |
| Host | smart-c6df436b-1e8c-425c-b8e9-bb467faada1f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=459982249 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 325.prim_prince_test.459982249 |
| Directory | /workspace/325.prim_prince_test/latest |
| Test location | /workspace/coverage/default/326.prim_prince_test.2276160600 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 2032016938 ps |
| CPU time | 33.16 seconds |
| Started | Feb 18 12:36:41 PM PST 24 |
| Finished | Feb 18 12:37:23 PM PST 24 |
| Peak memory | 146836 kb |
| Host | smart-3fae2ad4-b030-4a1b-ab67-f394f7d737d6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2276160600 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 326.prim_prince_test.2276160600 |
| Directory | /workspace/326.prim_prince_test/latest |
| Test location | /workspace/coverage/default/327.prim_prince_test.714593171 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 3184905275 ps |
| CPU time | 53.43 seconds |
| Started | Feb 18 12:36:47 PM PST 24 |
| Finished | Feb 18 12:37:55 PM PST 24 |
| Peak memory | 146944 kb |
| Host | smart-c51673f1-ae5e-4d37-940d-08e344aeb878 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=714593171 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 327.prim_prince_test.714593171 |
| Directory | /workspace/327.prim_prince_test/latest |
| Test location | /workspace/coverage/default/328.prim_prince_test.2004894448 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 2993182298 ps |
| CPU time | 50.36 seconds |
| Started | Feb 18 12:36:54 PM PST 24 |
| Finished | Feb 18 12:37:57 PM PST 24 |
| Peak memory | 146920 kb |
| Host | smart-2057c622-8578-4bd4-bc5f-a64832c7877e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2004894448 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 328.prim_prince_test.2004894448 |
| Directory | /workspace/328.prim_prince_test/latest |
| Test location | /workspace/coverage/default/329.prim_prince_test.4287414633 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 2486030069 ps |
| CPU time | 42.58 seconds |
| Started | Feb 18 12:36:54 PM PST 24 |
| Finished | Feb 18 12:37:49 PM PST 24 |
| Peak memory | 146920 kb |
| Host | smart-eae34a93-6ec3-4bcd-94d7-b9c127082bf4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4287414633 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 329.prim_prince_test.4287414633 |
| Directory | /workspace/329.prim_prince_test/latest |
| Test location | /workspace/coverage/default/33.prim_prince_test.970344796 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 817165874 ps |
| CPU time | 14.01 seconds |
| Started | Feb 18 12:36:00 PM PST 24 |
| Finished | Feb 18 12:36:21 PM PST 24 |
| Peak memory | 146868 kb |
| Host | smart-0de65ceb-cef3-4496-a6c6-3c4e397eac71 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=970344796 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_prince_test.970344796 |
| Directory | /workspace/33.prim_prince_test/latest |
| Test location | /workspace/coverage/default/330.prim_prince_test.1174100565 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 1410470390 ps |
| CPU time | 23.53 seconds |
| Started | Feb 18 12:36:54 PM PST 24 |
| Finished | Feb 18 12:37:26 PM PST 24 |
| Peak memory | 146740 kb |
| Host | smart-400aa718-dc4b-49af-a271-aafb556fbe0b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1174100565 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 330.prim_prince_test.1174100565 |
| Directory | /workspace/330.prim_prince_test/latest |
| Test location | /workspace/coverage/default/331.prim_prince_test.3821349429 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 3412985637 ps |
| CPU time | 58.46 seconds |
| Started | Feb 18 12:36:46 PM PST 24 |
| Finished | Feb 18 12:38:00 PM PST 24 |
| Peak memory | 146944 kb |
| Host | smart-997d2a02-4352-40be-85cf-c84aa0184213 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3821349429 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 331.prim_prince_test.3821349429 |
| Directory | /workspace/331.prim_prince_test/latest |
| Test location | /workspace/coverage/default/332.prim_prince_test.313219781 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 1577937546 ps |
| CPU time | 27.3 seconds |
| Started | Feb 18 12:36:47 PM PST 24 |
| Finished | Feb 18 12:37:23 PM PST 24 |
| Peak memory | 146840 kb |
| Host | smart-a3ef263b-fa79-4418-9a8b-173ca410a00b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=313219781 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 332.prim_prince_test.313219781 |
| Directory | /workspace/332.prim_prince_test/latest |
| Test location | /workspace/coverage/default/333.prim_prince_test.2313110618 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 1218964037 ps |
| CPU time | 20.66 seconds |
| Started | Feb 18 12:36:54 PM PST 24 |
| Finished | Feb 18 12:37:23 PM PST 24 |
| Peak memory | 146756 kb |
| Host | smart-2c1a41cb-20f9-4d05-9396-7e76b174a918 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2313110618 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 333.prim_prince_test.2313110618 |
| Directory | /workspace/333.prim_prince_test/latest |
| Test location | /workspace/coverage/default/334.prim_prince_test.309572474 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 1989313040 ps |
| CPU time | 33.66 seconds |
| Started | Feb 18 12:36:48 PM PST 24 |
| Finished | Feb 18 12:37:31 PM PST 24 |
| Peak memory | 146852 kb |
| Host | smart-b0bc8010-070c-4ba2-96b5-635ee25f7017 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=309572474 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 334.prim_prince_test.309572474 |
| Directory | /workspace/334.prim_prince_test/latest |
| Test location | /workspace/coverage/default/335.prim_prince_test.2481419555 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 1245971237 ps |
| CPU time | 21.82 seconds |
| Started | Feb 18 12:36:50 PM PST 24 |
| Finished | Feb 18 12:37:18 PM PST 24 |
| Peak memory | 146944 kb |
| Host | smart-11ddf71a-be04-4fa0-bf32-c53a50626527 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2481419555 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 335.prim_prince_test.2481419555 |
| Directory | /workspace/335.prim_prince_test/latest |
| Test location | /workspace/coverage/default/336.prim_prince_test.2957365619 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 3364803051 ps |
| CPU time | 56.48 seconds |
| Started | Feb 18 12:36:47 PM PST 24 |
| Finished | Feb 18 12:37:58 PM PST 24 |
| Peak memory | 146948 kb |
| Host | smart-3406c03b-5a67-41f5-b40d-8a5b5d2d2155 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2957365619 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 336.prim_prince_test.2957365619 |
| Directory | /workspace/336.prim_prince_test/latest |
| Test location | /workspace/coverage/default/337.prim_prince_test.4194442259 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 1216051168 ps |
| CPU time | 20.88 seconds |
| Started | Feb 18 12:36:40 PM PST 24 |
| Finished | Feb 18 12:37:09 PM PST 24 |
| Peak memory | 146836 kb |
| Host | smart-fa52bcf8-589a-4cb5-860b-9fd739b02c3f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4194442259 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 337.prim_prince_test.4194442259 |
| Directory | /workspace/337.prim_prince_test/latest |
| Test location | /workspace/coverage/default/338.prim_prince_test.3401953376 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 3334326220 ps |
| CPU time | 56.33 seconds |
| Started | Feb 18 12:36:42 PM PST 24 |
| Finished | Feb 18 12:37:54 PM PST 24 |
| Peak memory | 146948 kb |
| Host | smart-a44d7573-564b-4a4b-87fd-5e98534e2c65 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3401953376 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 338.prim_prince_test.3401953376 |
| Directory | /workspace/338.prim_prince_test/latest |
| Test location | /workspace/coverage/default/339.prim_prince_test.1412798486 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 1088289522 ps |
| CPU time | 18.66 seconds |
| Started | Feb 18 12:36:40 PM PST 24 |
| Finished | Feb 18 12:37:06 PM PST 24 |
| Peak memory | 146768 kb |
| Host | smart-ecc45b3d-7fe8-4513-8328-c702664628cb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1412798486 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 339.prim_prince_test.1412798486 |
| Directory | /workspace/339.prim_prince_test/latest |
| Test location | /workspace/coverage/default/34.prim_prince_test.2238891682 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 2100570602 ps |
| CPU time | 35.77 seconds |
| Started | Feb 18 12:35:55 PM PST 24 |
| Finished | Feb 18 12:36:41 PM PST 24 |
| Peak memory | 146824 kb |
| Host | smart-8df42a70-d992-4432-ae01-c7335640e9bb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2238891682 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_prince_test.2238891682 |
| Directory | /workspace/34.prim_prince_test/latest |
| Test location | /workspace/coverage/default/340.prim_prince_test.143342289 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 2724782852 ps |
| CPU time | 45.52 seconds |
| Started | Feb 18 12:36:36 PM PST 24 |
| Finished | Feb 18 12:37:36 PM PST 24 |
| Peak memory | 146956 kb |
| Host | smart-9f6bf27e-1180-4dcf-b573-61b4f6767b5e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=143342289 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 340.prim_prince_test.143342289 |
| Directory | /workspace/340.prim_prince_test/latest |
| Test location | /workspace/coverage/default/341.prim_prince_test.304924790 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 1935731645 ps |
| CPU time | 33.13 seconds |
| Started | Feb 18 12:36:54 PM PST 24 |
| Finished | Feb 18 12:37:38 PM PST 24 |
| Peak memory | 146796 kb |
| Host | smart-0de1fdf6-ef43-4d0c-98e7-9fccf82793f5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=304924790 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 341.prim_prince_test.304924790 |
| Directory | /workspace/341.prim_prince_test/latest |
| Test location | /workspace/coverage/default/342.prim_prince_test.1358582879 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 2287759138 ps |
| CPU time | 39.56 seconds |
| Started | Feb 18 12:36:50 PM PST 24 |
| Finished | Feb 18 12:37:40 PM PST 24 |
| Peak memory | 146840 kb |
| Host | smart-64f21652-0cdb-41ba-a993-82372327cea0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1358582879 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 342.prim_prince_test.1358582879 |
| Directory | /workspace/342.prim_prince_test/latest |
| Test location | /workspace/coverage/default/343.prim_prince_test.3091657137 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 2152105917 ps |
| CPU time | 35.37 seconds |
| Started | Feb 18 12:36:52 PM PST 24 |
| Finished | Feb 18 12:37:38 PM PST 24 |
| Peak memory | 146960 kb |
| Host | smart-2d20afc3-f650-4f32-ad3b-e3709b0f24a4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3091657137 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 343.prim_prince_test.3091657137 |
| Directory | /workspace/343.prim_prince_test/latest |
| Test location | /workspace/coverage/default/344.prim_prince_test.468662428 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 1138723671 ps |
| CPU time | 19.17 seconds |
| Started | Feb 18 12:36:48 PM PST 24 |
| Finished | Feb 18 12:37:13 PM PST 24 |
| Peak memory | 146820 kb |
| Host | smart-212c8ea4-0e11-4373-a75e-078d009d60c2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=468662428 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 344.prim_prince_test.468662428 |
| Directory | /workspace/344.prim_prince_test/latest |
| Test location | /workspace/coverage/default/345.prim_prince_test.2249155327 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 2442211517 ps |
| CPU time | 41.51 seconds |
| Started | Feb 18 12:36:50 PM PST 24 |
| Finished | Feb 18 12:37:42 PM PST 24 |
| Peak memory | 146888 kb |
| Host | smart-51fd9fc8-3b07-431c-8f65-8304aeeced7c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2249155327 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 345.prim_prince_test.2249155327 |
| Directory | /workspace/345.prim_prince_test/latest |
| Test location | /workspace/coverage/default/346.prim_prince_test.511643921 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 3129770956 ps |
| CPU time | 51.37 seconds |
| Started | Feb 18 12:36:43 PM PST 24 |
| Finished | Feb 18 12:37:47 PM PST 24 |
| Peak memory | 146948 kb |
| Host | smart-d1fa9c12-8241-431c-834c-6335e8272fe9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=511643921 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 346.prim_prince_test.511643921 |
| Directory | /workspace/346.prim_prince_test/latest |
| Test location | /workspace/coverage/default/347.prim_prince_test.3140300618 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 1961826973 ps |
| CPU time | 32.61 seconds |
| Started | Feb 18 12:36:42 PM PST 24 |
| Finished | Feb 18 12:37:24 PM PST 24 |
| Peak memory | 146832 kb |
| Host | smart-42ed8931-8cb6-409e-b1e5-1f0d58f6ce62 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3140300618 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 347.prim_prince_test.3140300618 |
| Directory | /workspace/347.prim_prince_test/latest |
| Test location | /workspace/coverage/default/348.prim_prince_test.3449263627 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 2363893502 ps |
| CPU time | 38.53 seconds |
| Started | Feb 18 12:36:52 PM PST 24 |
| Finished | Feb 18 12:37:42 PM PST 24 |
| Peak memory | 146960 kb |
| Host | smart-2ccc80a7-3cda-4c87-82fd-cbe7828828d1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3449263627 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 348.prim_prince_test.3449263627 |
| Directory | /workspace/348.prim_prince_test/latest |
| Test location | /workspace/coverage/default/349.prim_prince_test.3820908072 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 983966255 ps |
| CPU time | 16.57 seconds |
| Started | Feb 18 12:36:52 PM PST 24 |
| Finished | Feb 18 12:37:16 PM PST 24 |
| Peak memory | 146832 kb |
| Host | smart-4d387b5a-c124-4af4-b66f-be648d4f617c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3820908072 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 349.prim_prince_test.3820908072 |
| Directory | /workspace/349.prim_prince_test/latest |
| Test location | /workspace/coverage/default/35.prim_prince_test.1985709478 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 2831375186 ps |
| CPU time | 46.9 seconds |
| Started | Feb 18 12:35:57 PM PST 24 |
| Finished | Feb 18 12:36:57 PM PST 24 |
| Peak memory | 146988 kb |
| Host | smart-aa51e41b-c977-4071-b6fe-40c5a151bf70 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1985709478 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_prince_test.1985709478 |
| Directory | /workspace/35.prim_prince_test/latest |
| Test location | /workspace/coverage/default/350.prim_prince_test.1495020289 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 1337303557 ps |
| CPU time | 22.93 seconds |
| Started | Feb 18 12:36:48 PM PST 24 |
| Finished | Feb 18 12:37:18 PM PST 24 |
| Peak memory | 146836 kb |
| Host | smart-f1aa8ba3-b864-4587-ba1b-56933add2a44 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1495020289 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 350.prim_prince_test.1495020289 |
| Directory | /workspace/350.prim_prince_test/latest |
| Test location | /workspace/coverage/default/351.prim_prince_test.3861734511 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 2169024372 ps |
| CPU time | 35.97 seconds |
| Started | Feb 18 12:36:51 PM PST 24 |
| Finished | Feb 18 12:37:35 PM PST 24 |
| Peak memory | 147088 kb |
| Host | smart-7a0ff779-bc09-4ed3-a01a-a608a1ba939b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3861734511 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 351.prim_prince_test.3861734511 |
| Directory | /workspace/351.prim_prince_test/latest |
| Test location | /workspace/coverage/default/352.prim_prince_test.2516401638 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 2873121304 ps |
| CPU time | 46.59 seconds |
| Started | Feb 18 12:36:42 PM PST 24 |
| Finished | Feb 18 12:37:41 PM PST 24 |
| Peak memory | 146952 kb |
| Host | smart-9ed4b07d-b443-4df5-8e98-d04f65a6bcbb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2516401638 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 352.prim_prince_test.2516401638 |
| Directory | /workspace/352.prim_prince_test/latest |
| Test location | /workspace/coverage/default/353.prim_prince_test.2820970387 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 1983141990 ps |
| CPU time | 33.45 seconds |
| Started | Feb 18 12:36:44 PM PST 24 |
| Finished | Feb 18 12:37:26 PM PST 24 |
| Peak memory | 146832 kb |
| Host | smart-1c3fe63c-23eb-4dce-a7d2-4668d66f8f32 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2820970387 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 353.prim_prince_test.2820970387 |
| Directory | /workspace/353.prim_prince_test/latest |
| Test location | /workspace/coverage/default/354.prim_prince_test.2606207988 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 2725058999 ps |
| CPU time | 45.49 seconds |
| Started | Feb 18 12:36:47 PM PST 24 |
| Finished | Feb 18 12:37:44 PM PST 24 |
| Peak memory | 146944 kb |
| Host | smart-40516221-aff7-4452-b871-663b2b1513bd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2606207988 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 354.prim_prince_test.2606207988 |
| Directory | /workspace/354.prim_prince_test/latest |
| Test location | /workspace/coverage/default/355.prim_prince_test.2951009373 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 1395005187 ps |
| CPU time | 23.77 seconds |
| Started | Feb 18 12:36:50 PM PST 24 |
| Finished | Feb 18 12:37:20 PM PST 24 |
| Peak memory | 146720 kb |
| Host | smart-32ac33e1-cc17-4e68-addf-3bff61ecb2e3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2951009373 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 355.prim_prince_test.2951009373 |
| Directory | /workspace/355.prim_prince_test/latest |
| Test location | /workspace/coverage/default/356.prim_prince_test.2137772666 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 3403315631 ps |
| CPU time | 56.12 seconds |
| Started | Feb 18 12:36:50 PM PST 24 |
| Finished | Feb 18 12:37:59 PM PST 24 |
| Peak memory | 147088 kb |
| Host | smart-40f67ff7-d537-43a6-b656-9b13fa05e673 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2137772666 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 356.prim_prince_test.2137772666 |
| Directory | /workspace/356.prim_prince_test/latest |
| Test location | /workspace/coverage/default/357.prim_prince_test.3529235359 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 3447942941 ps |
| CPU time | 57.82 seconds |
| Started | Feb 18 12:36:42 PM PST 24 |
| Finished | Feb 18 12:37:55 PM PST 24 |
| Peak memory | 146888 kb |
| Host | smart-dd6aee35-059c-465c-b6a2-7b55f07892da |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3529235359 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 357.prim_prince_test.3529235359 |
| Directory | /workspace/357.prim_prince_test/latest |
| Test location | /workspace/coverage/default/358.prim_prince_test.70157169 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 3238204176 ps |
| CPU time | 54.81 seconds |
| Started | Feb 18 12:36:42 PM PST 24 |
| Finished | Feb 18 12:37:52 PM PST 24 |
| Peak memory | 146972 kb |
| Host | smart-6fa1908c-8f0e-4b76-aabf-b803cec94e45 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=70157169 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 358.prim_prince_test.70157169 |
| Directory | /workspace/358.prim_prince_test/latest |
| Test location | /workspace/coverage/default/359.prim_prince_test.3318885033 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 1123067605 ps |
| CPU time | 18.87 seconds |
| Started | Feb 18 12:36:44 PM PST 24 |
| Finished | Feb 18 12:37:08 PM PST 24 |
| Peak memory | 146832 kb |
| Host | smart-0e73ebaa-fdcb-4899-a23f-929c57d13117 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3318885033 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 359.prim_prince_test.3318885033 |
| Directory | /workspace/359.prim_prince_test/latest |
| Test location | /workspace/coverage/default/36.prim_prince_test.2883265957 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 3529984094 ps |
| CPU time | 58.34 seconds |
| Started | Feb 18 12:36:07 PM PST 24 |
| Finished | Feb 18 12:37:19 PM PST 24 |
| Peak memory | 146952 kb |
| Host | smart-b66c98c7-4442-4f02-bc77-a8a8de0bc2aa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2883265957 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_prince_test.2883265957 |
| Directory | /workspace/36.prim_prince_test/latest |
| Test location | /workspace/coverage/default/360.prim_prince_test.3898670824 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 2402358198 ps |
| CPU time | 40.08 seconds |
| Started | Feb 18 12:36:42 PM PST 24 |
| Finished | Feb 18 12:37:33 PM PST 24 |
| Peak memory | 146944 kb |
| Host | smart-33a1d35e-6d2a-41ab-bd61-da9c4d72480e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3898670824 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 360.prim_prince_test.3898670824 |
| Directory | /workspace/360.prim_prince_test/latest |
| Test location | /workspace/coverage/default/361.prim_prince_test.4160021334 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 3731172826 ps |
| CPU time | 62.7 seconds |
| Started | Feb 18 12:36:42 PM PST 24 |
| Finished | Feb 18 12:38:02 PM PST 24 |
| Peak memory | 146948 kb |
| Host | smart-33044579-fafd-4dbe-bb71-218085a01803 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4160021334 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 361.prim_prince_test.4160021334 |
| Directory | /workspace/361.prim_prince_test/latest |
| Test location | /workspace/coverage/default/362.prim_prince_test.3056835822 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 942939907 ps |
| CPU time | 16.51 seconds |
| Started | Feb 18 12:36:45 PM PST 24 |
| Finished | Feb 18 12:37:07 PM PST 24 |
| Peak memory | 146828 kb |
| Host | smart-bb25c911-668e-49e6-a56a-e9efa1c102a4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3056835822 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 362.prim_prince_test.3056835822 |
| Directory | /workspace/362.prim_prince_test/latest |
| Test location | /workspace/coverage/default/363.prim_prince_test.3473088813 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 2546973230 ps |
| CPU time | 42.36 seconds |
| Started | Feb 18 12:36:41 PM PST 24 |
| Finished | Feb 18 12:37:35 PM PST 24 |
| Peak memory | 146960 kb |
| Host | smart-92dc95c3-5491-4480-9134-16c30b60f518 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3473088813 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 363.prim_prince_test.3473088813 |
| Directory | /workspace/363.prim_prince_test/latest |
| Test location | /workspace/coverage/default/364.prim_prince_test.3937244390 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 3459662437 ps |
| CPU time | 56.93 seconds |
| Started | Feb 18 12:36:45 PM PST 24 |
| Finished | Feb 18 12:37:55 PM PST 24 |
| Peak memory | 147088 kb |
| Host | smart-ac1e5886-951c-422d-89cd-b5fafab6f32b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3937244390 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 364.prim_prince_test.3937244390 |
| Directory | /workspace/364.prim_prince_test/latest |
| Test location | /workspace/coverage/default/365.prim_prince_test.1183665137 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 1630864384 ps |
| CPU time | 27.79 seconds |
| Started | Feb 18 12:36:47 PM PST 24 |
| Finished | Feb 18 12:37:23 PM PST 24 |
| Peak memory | 146748 kb |
| Host | smart-ef1cf037-26fd-4ec3-837f-2adda84abb6f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1183665137 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 365.prim_prince_test.1183665137 |
| Directory | /workspace/365.prim_prince_test/latest |
| Test location | /workspace/coverage/default/366.prim_prince_test.2704534040 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 2326539254 ps |
| CPU time | 37.9 seconds |
| Started | Feb 18 12:36:49 PM PST 24 |
| Finished | Feb 18 12:37:36 PM PST 24 |
| Peak memory | 147088 kb |
| Host | smart-d8ee5be2-731b-4511-b570-0401d44f27bb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2704534040 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 366.prim_prince_test.2704534040 |
| Directory | /workspace/366.prim_prince_test/latest |
| Test location | /workspace/coverage/default/367.prim_prince_test.3896317610 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 2905802355 ps |
| CPU time | 48.75 seconds |
| Started | Feb 18 12:36:39 PM PST 24 |
| Finished | Feb 18 12:37:42 PM PST 24 |
| Peak memory | 146888 kb |
| Host | smart-7bf1f808-6e03-4414-9531-ede4f2e37c04 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3896317610 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 367.prim_prince_test.3896317610 |
| Directory | /workspace/367.prim_prince_test/latest |
| Test location | /workspace/coverage/default/368.prim_prince_test.3532442875 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 853922795 ps |
| CPU time | 14.72 seconds |
| Started | Feb 18 12:36:54 PM PST 24 |
| Finished | Feb 18 12:37:14 PM PST 24 |
| Peak memory | 146800 kb |
| Host | smart-9d89c630-92e1-4128-a38d-02c143584550 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3532442875 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 368.prim_prince_test.3532442875 |
| Directory | /workspace/368.prim_prince_test/latest |
| Test location | /workspace/coverage/default/369.prim_prince_test.2017659594 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 1434476537 ps |
| CPU time | 23.69 seconds |
| Started | Feb 18 12:36:45 PM PST 24 |
| Finished | Feb 18 12:37:15 PM PST 24 |
| Peak memory | 146968 kb |
| Host | smart-4b18caa1-3215-446a-8952-0205ab3f1db5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2017659594 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 369.prim_prince_test.2017659594 |
| Directory | /workspace/369.prim_prince_test/latest |
| Test location | /workspace/coverage/default/37.prim_prince_test.3301320756 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 1934937818 ps |
| CPU time | 32.81 seconds |
| Started | Feb 18 12:35:56 PM PST 24 |
| Finished | Feb 18 12:36:39 PM PST 24 |
| Peak memory | 146732 kb |
| Host | smart-1c3ac5f9-bf16-4de4-88f4-1f104f86fc78 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3301320756 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_prince_test.3301320756 |
| Directory | /workspace/37.prim_prince_test/latest |
| Test location | /workspace/coverage/default/370.prim_prince_test.153968076 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 2246164687 ps |
| CPU time | 37.67 seconds |
| Started | Feb 18 12:36:55 PM PST 24 |
| Finished | Feb 18 12:37:45 PM PST 24 |
| Peak memory | 146964 kb |
| Host | smart-1b024100-329f-4be0-b8dd-a9c09291c038 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=153968076 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 370.prim_prince_test.153968076 |
| Directory | /workspace/370.prim_prince_test/latest |
| Test location | /workspace/coverage/default/371.prim_prince_test.4240603409 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 3673055768 ps |
| CPU time | 62.07 seconds |
| Started | Feb 18 12:36:47 PM PST 24 |
| Finished | Feb 18 12:38:05 PM PST 24 |
| Peak memory | 146896 kb |
| Host | smart-21422675-0788-413c-ab1b-49927928f086 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4240603409 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 371.prim_prince_test.4240603409 |
| Directory | /workspace/371.prim_prince_test/latest |
| Test location | /workspace/coverage/default/372.prim_prince_test.2795634572 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 2745408575 ps |
| CPU time | 47 seconds |
| Started | Feb 18 12:36:47 PM PST 24 |
| Finished | Feb 18 12:37:47 PM PST 24 |
| Peak memory | 146976 kb |
| Host | smart-646feeee-07d4-4e00-9db2-6c88b5f49bab |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2795634572 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 372.prim_prince_test.2795634572 |
| Directory | /workspace/372.prim_prince_test/latest |
| Test location | /workspace/coverage/default/373.prim_prince_test.263740385 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 3379943349 ps |
| CPU time | 55.61 seconds |
| Started | Feb 18 12:36:51 PM PST 24 |
| Finished | Feb 18 12:38:00 PM PST 24 |
| Peak memory | 146944 kb |
| Host | smart-d1531a9c-2c1c-4ff9-8e40-13506890835b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=263740385 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 373.prim_prince_test.263740385 |
| Directory | /workspace/373.prim_prince_test/latest |
| Test location | /workspace/coverage/default/374.prim_prince_test.1246811172 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 3501225550 ps |
| CPU time | 58.89 seconds |
| Started | Feb 18 12:36:55 PM PST 24 |
| Finished | Feb 18 12:38:11 PM PST 24 |
| Peak memory | 146968 kb |
| Host | smart-f7406723-f7a1-4969-aaa9-9afac56f337a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1246811172 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 374.prim_prince_test.1246811172 |
| Directory | /workspace/374.prim_prince_test/latest |
| Test location | /workspace/coverage/default/375.prim_prince_test.1247665632 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 1784693874 ps |
| CPU time | 30.27 seconds |
| Started | Feb 18 12:37:00 PM PST 24 |
| Finished | Feb 18 12:37:40 PM PST 24 |
| Peak memory | 146856 kb |
| Host | smart-3a0996ac-9f61-47a3-b08a-56a684a6658d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1247665632 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 375.prim_prince_test.1247665632 |
| Directory | /workspace/375.prim_prince_test/latest |
| Test location | /workspace/coverage/default/376.prim_prince_test.2915637235 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 3617196085 ps |
| CPU time | 59.65 seconds |
| Started | Feb 18 12:36:54 PM PST 24 |
| Finished | Feb 18 12:38:10 PM PST 24 |
| Peak memory | 146956 kb |
| Host | smart-5e2a3a9f-25db-422f-8fa5-b6d3df67b547 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2915637235 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 376.prim_prince_test.2915637235 |
| Directory | /workspace/376.prim_prince_test/latest |
| Test location | /workspace/coverage/default/377.prim_prince_test.73487232 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 2054955118 ps |
| CPU time | 34.84 seconds |
| Started | Feb 18 12:36:39 PM PST 24 |
| Finished | Feb 18 12:37:27 PM PST 24 |
| Peak memory | 146884 kb |
| Host | smart-6d4c57c7-d970-4b5e-a94b-4b65004ad002 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=73487232 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 377.prim_prince_test.73487232 |
| Directory | /workspace/377.prim_prince_test/latest |
| Test location | /workspace/coverage/default/378.prim_prince_test.2004971524 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 1682020528 ps |
| CPU time | 28.17 seconds |
| Started | Feb 18 12:36:54 PM PST 24 |
| Finished | Feb 18 12:37:31 PM PST 24 |
| Peak memory | 146800 kb |
| Host | smart-224e5f2d-2b81-4d9a-b81a-8be8f4ce9de1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2004971524 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 378.prim_prince_test.2004971524 |
| Directory | /workspace/378.prim_prince_test/latest |
| Test location | /workspace/coverage/default/379.prim_prince_test.3206731809 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 3732993406 ps |
| CPU time | 61.09 seconds |
| Started | Feb 18 12:36:39 PM PST 24 |
| Finished | Feb 18 12:37:56 PM PST 24 |
| Peak memory | 146972 kb |
| Host | smart-7697ad7a-cc84-4e30-b3f8-6c2699a30383 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3206731809 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 379.prim_prince_test.3206731809 |
| Directory | /workspace/379.prim_prince_test/latest |
| Test location | /workspace/coverage/default/38.prim_prince_test.1422307062 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 2946245381 ps |
| CPU time | 47.1 seconds |
| Started | Feb 18 12:35:57 PM PST 24 |
| Finished | Feb 18 12:36:56 PM PST 24 |
| Peak memory | 146964 kb |
| Host | smart-b2116583-d0fe-4ed0-b487-f265e4020780 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1422307062 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_prince_test.1422307062 |
| Directory | /workspace/38.prim_prince_test/latest |
| Test location | /workspace/coverage/default/380.prim_prince_test.407137149 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 3103184222 ps |
| CPU time | 51.13 seconds |
| Started | Feb 18 12:36:57 PM PST 24 |
| Finished | Feb 18 12:38:02 PM PST 24 |
| Peak memory | 146952 kb |
| Host | smart-e9412b15-7b0e-43bc-952f-ca427522993d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=407137149 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 380.prim_prince_test.407137149 |
| Directory | /workspace/380.prim_prince_test/latest |
| Test location | /workspace/coverage/default/381.prim_prince_test.942732103 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 2753002999 ps |
| CPU time | 45.73 seconds |
| Started | Feb 18 12:36:56 PM PST 24 |
| Finished | Feb 18 12:37:55 PM PST 24 |
| Peak memory | 146952 kb |
| Host | smart-b49558c7-dd60-478e-8de1-e310bb0cfa3a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=942732103 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 381.prim_prince_test.942732103 |
| Directory | /workspace/381.prim_prince_test/latest |
| Test location | /workspace/coverage/default/382.prim_prince_test.3693590154 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 2275788045 ps |
| CPU time | 38.15 seconds |
| Started | Feb 18 12:36:55 PM PST 24 |
| Finished | Feb 18 12:37:46 PM PST 24 |
| Peak memory | 146968 kb |
| Host | smart-2c0d6d1a-a230-4ac1-9447-7313d1da444b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3693590154 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 382.prim_prince_test.3693590154 |
| Directory | /workspace/382.prim_prince_test/latest |
| Test location | /workspace/coverage/default/383.prim_prince_test.2895981051 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 1382108302 ps |
| CPU time | 22.83 seconds |
| Started | Feb 18 12:36:43 PM PST 24 |
| Finished | Feb 18 12:37:12 PM PST 24 |
| Peak memory | 146832 kb |
| Host | smart-e432fc53-3fef-4bf8-af21-a6de60a1320b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2895981051 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 383.prim_prince_test.2895981051 |
| Directory | /workspace/383.prim_prince_test/latest |
| Test location | /workspace/coverage/default/384.prim_prince_test.1110900758 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 3023219484 ps |
| CPU time | 50.82 seconds |
| Started | Feb 18 12:36:45 PM PST 24 |
| Finished | Feb 18 12:37:48 PM PST 24 |
| Peak memory | 146864 kb |
| Host | smart-05ba0fda-620e-4ea8-8205-d81b5196413c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1110900758 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 384.prim_prince_test.1110900758 |
| Directory | /workspace/384.prim_prince_test/latest |
| Test location | /workspace/coverage/default/385.prim_prince_test.1150034731 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 2298095459 ps |
| CPU time | 39.28 seconds |
| Started | Feb 18 12:36:48 PM PST 24 |
| Finished | Feb 18 12:37:39 PM PST 24 |
| Peak memory | 146956 kb |
| Host | smart-264b124d-7586-4c7e-a791-2f9874fa6e34 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1150034731 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 385.prim_prince_test.1150034731 |
| Directory | /workspace/385.prim_prince_test/latest |
| Test location | /workspace/coverage/default/386.prim_prince_test.3898689240 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 3350874623 ps |
| CPU time | 56.7 seconds |
| Started | Feb 18 12:36:42 PM PST 24 |
| Finished | Feb 18 12:37:54 PM PST 24 |
| Peak memory | 146980 kb |
| Host | smart-35fc4884-cf29-4f12-a5f1-8da1f96d58f3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3898689240 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 386.prim_prince_test.3898689240 |
| Directory | /workspace/386.prim_prince_test/latest |
| Test location | /workspace/coverage/default/387.prim_prince_test.3328001830 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 2523008008 ps |
| CPU time | 42.43 seconds |
| Started | Feb 18 12:36:55 PM PST 24 |
| Finished | Feb 18 12:37:51 PM PST 24 |
| Peak memory | 146628 kb |
| Host | smart-d5ee51ea-ddde-446d-96b0-02eb82adbe53 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3328001830 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 387.prim_prince_test.3328001830 |
| Directory | /workspace/387.prim_prince_test/latest |
| Test location | /workspace/coverage/default/388.prim_prince_test.3091465685 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 878563883 ps |
| CPU time | 14.32 seconds |
| Started | Feb 18 12:36:55 PM PST 24 |
| Finished | Feb 18 12:37:16 PM PST 24 |
| Peak memory | 146836 kb |
| Host | smart-309ae51b-822f-4094-ae68-468b5bcb7ba3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3091465685 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 388.prim_prince_test.3091465685 |
| Directory | /workspace/388.prim_prince_test/latest |
| Test location | /workspace/coverage/default/389.prim_prince_test.1969981141 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 3498293182 ps |
| CPU time | 59.58 seconds |
| Started | Feb 18 12:36:52 PM PST 24 |
| Finished | Feb 18 12:38:08 PM PST 24 |
| Peak memory | 146884 kb |
| Host | smart-91fa8e02-2ea0-4b6a-a774-ddf24380b5ff |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1969981141 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 389.prim_prince_test.1969981141 |
| Directory | /workspace/389.prim_prince_test/latest |
| Test location | /workspace/coverage/default/39.prim_prince_test.2977640873 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 1477114500 ps |
| CPU time | 25.09 seconds |
| Started | Feb 18 12:35:54 PM PST 24 |
| Finished | Feb 18 12:36:28 PM PST 24 |
| Peak memory | 146920 kb |
| Host | smart-14b04349-9c19-48f7-b9c7-7824c062b854 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2977640873 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_prince_test.2977640873 |
| Directory | /workspace/39.prim_prince_test/latest |
| Test location | /workspace/coverage/default/390.prim_prince_test.937821004 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 2928421510 ps |
| CPU time | 48.8 seconds |
| Started | Feb 18 12:36:43 PM PST 24 |
| Finished | Feb 18 12:37:44 PM PST 24 |
| Peak memory | 146968 kb |
| Host | smart-435e6f4f-4d9e-4d7b-8f90-ede8bf01b081 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=937821004 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 390.prim_prince_test.937821004 |
| Directory | /workspace/390.prim_prince_test/latest |
| Test location | /workspace/coverage/default/391.prim_prince_test.2996887969 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 1737441496 ps |
| CPU time | 29.83 seconds |
| Started | Feb 18 12:36:48 PM PST 24 |
| Finished | Feb 18 12:37:26 PM PST 24 |
| Peak memory | 146824 kb |
| Host | smart-08065a86-88ca-4ebd-bcc0-e699d477b63c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2996887969 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 391.prim_prince_test.2996887969 |
| Directory | /workspace/391.prim_prince_test/latest |
| Test location | /workspace/coverage/default/392.prim_prince_test.1505939690 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 2800181510 ps |
| CPU time | 47.9 seconds |
| Started | Feb 18 12:36:52 PM PST 24 |
| Finished | Feb 18 12:37:54 PM PST 24 |
| Peak memory | 146944 kb |
| Host | smart-7af77f95-193f-4892-b1af-1d01fda615f1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1505939690 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 392.prim_prince_test.1505939690 |
| Directory | /workspace/392.prim_prince_test/latest |
| Test location | /workspace/coverage/default/393.prim_prince_test.766111278 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 1404344343 ps |
| CPU time | 24.75 seconds |
| Started | Feb 18 12:36:46 PM PST 24 |
| Finished | Feb 18 12:37:19 PM PST 24 |
| Peak memory | 146820 kb |
| Host | smart-99f396b1-ffb2-466c-a75a-a412b2118187 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=766111278 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 393.prim_prince_test.766111278 |
| Directory | /workspace/393.prim_prince_test/latest |
| Test location | /workspace/coverage/default/394.prim_prince_test.3351132090 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 3124404684 ps |
| CPU time | 52.33 seconds |
| Started | Feb 18 12:36:47 PM PST 24 |
| Finished | Feb 18 12:37:53 PM PST 24 |
| Peak memory | 146976 kb |
| Host | smart-2edc84de-b6be-49de-9732-92f47a15407e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3351132090 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 394.prim_prince_test.3351132090 |
| Directory | /workspace/394.prim_prince_test/latest |
| Test location | /workspace/coverage/default/395.prim_prince_test.3091855740 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 2509294086 ps |
| CPU time | 43.58 seconds |
| Started | Feb 18 12:36:45 PM PST 24 |
| Finished | Feb 18 12:37:41 PM PST 24 |
| Peak memory | 146944 kb |
| Host | smart-281338bb-d436-4081-9fb0-754bdcaeeb00 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3091855740 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 395.prim_prince_test.3091855740 |
| Directory | /workspace/395.prim_prince_test/latest |
| Test location | /workspace/coverage/default/396.prim_prince_test.1818588704 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 2946506378 ps |
| CPU time | 50.5 seconds |
| Started | Feb 18 12:36:44 PM PST 24 |
| Finished | Feb 18 12:37:49 PM PST 24 |
| Peak memory | 146956 kb |
| Host | smart-f9c1e368-4b67-45b9-98a9-23473c255e95 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1818588704 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 396.prim_prince_test.1818588704 |
| Directory | /workspace/396.prim_prince_test/latest |
| Test location | /workspace/coverage/default/397.prim_prince_test.4014880045 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 1591652264 ps |
| CPU time | 26.73 seconds |
| Started | Feb 18 12:36:55 PM PST 24 |
| Finished | Feb 18 12:37:32 PM PST 24 |
| Peak memory | 146536 kb |
| Host | smart-91a6a1c3-e40c-4f2f-973f-359867a819f7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4014880045 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 397.prim_prince_test.4014880045 |
| Directory | /workspace/397.prim_prince_test/latest |
| Test location | /workspace/coverage/default/398.prim_prince_test.4190306054 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 1296550221 ps |
| CPU time | 21.9 seconds |
| Started | Feb 18 12:36:57 PM PST 24 |
| Finished | Feb 18 12:37:27 PM PST 24 |
| Peak memory | 146836 kb |
| Host | smart-1b78c5a6-1110-4c12-9953-084e33d20369 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4190306054 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 398.prim_prince_test.4190306054 |
| Directory | /workspace/398.prim_prince_test/latest |
| Test location | /workspace/coverage/default/399.prim_prince_test.3566828503 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 1805281376 ps |
| CPU time | 30.35 seconds |
| Started | Feb 18 12:36:55 PM PST 24 |
| Finished | Feb 18 12:37:36 PM PST 24 |
| Peak memory | 146848 kb |
| Host | smart-115b5a4e-2a1f-4a27-98a2-861e3093cc9b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3566828503 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 399.prim_prince_test.3566828503 |
| Directory | /workspace/399.prim_prince_test/latest |
| Test location | /workspace/coverage/default/4.prim_prince_test.536868732 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 2193437217 ps |
| CPU time | 37.02 seconds |
| Started | Feb 18 12:37:06 PM PST 24 |
| Finished | Feb 18 12:37:52 PM PST 24 |
| Peak memory | 144676 kb |
| Host | smart-754032cb-7214-4af0-ad27-d6aa1cc53510 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=536868732 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_prince_test.536868732 |
| Directory | /workspace/4.prim_prince_test/latest |
| Test location | /workspace/coverage/default/40.prim_prince_test.1507948602 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 943371858 ps |
| CPU time | 16.01 seconds |
| Started | Feb 18 12:36:03 PM PST 24 |
| Finished | Feb 18 12:36:25 PM PST 24 |
| Peak memory | 146892 kb |
| Host | smart-2b25a3fd-d6cc-4000-994f-aa0c035c5f40 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1507948602 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_prince_test.1507948602 |
| Directory | /workspace/40.prim_prince_test/latest |
| Test location | /workspace/coverage/default/400.prim_prince_test.436828730 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 1357919959 ps |
| CPU time | 23.07 seconds |
| Started | Feb 18 12:36:54 PM PST 24 |
| Finished | Feb 18 12:37:26 PM PST 24 |
| Peak memory | 146796 kb |
| Host | smart-3a10af81-9b33-4b1d-a7e5-c25dacf70edf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=436828730 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 400.prim_prince_test.436828730 |
| Directory | /workspace/400.prim_prince_test/latest |
| Test location | /workspace/coverage/default/401.prim_prince_test.647541319 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 3711817360 ps |
| CPU time | 59.22 seconds |
| Started | Feb 18 12:36:48 PM PST 24 |
| Finished | Feb 18 12:38:00 PM PST 24 |
| Peak memory | 146952 kb |
| Host | smart-8ab84656-ad14-46a2-87ee-6ff2b9fc906f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=647541319 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 401.prim_prince_test.647541319 |
| Directory | /workspace/401.prim_prince_test/latest |
| Test location | /workspace/coverage/default/402.prim_prince_test.1525605840 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 2470188456 ps |
| CPU time | 40.66 seconds |
| Started | Feb 18 12:36:55 PM PST 24 |
| Finished | Feb 18 12:37:48 PM PST 24 |
| Peak memory | 146956 kb |
| Host | smart-98a20219-3ce2-49f9-af6d-6476cb51c898 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1525605840 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 402.prim_prince_test.1525605840 |
| Directory | /workspace/402.prim_prince_test/latest |
| Test location | /workspace/coverage/default/403.prim_prince_test.350907814 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 2467945915 ps |
| CPU time | 41.45 seconds |
| Started | Feb 18 12:36:54 PM PST 24 |
| Finished | Feb 18 12:37:48 PM PST 24 |
| Peak memory | 146916 kb |
| Host | smart-a86b8ee4-d429-46bb-93cf-db1a8132e396 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=350907814 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 403.prim_prince_test.350907814 |
| Directory | /workspace/403.prim_prince_test/latest |
| Test location | /workspace/coverage/default/404.prim_prince_test.393312939 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 3408264127 ps |
| CPU time | 56.67 seconds |
| Started | Feb 18 12:36:52 PM PST 24 |
| Finished | Feb 18 12:38:03 PM PST 24 |
| Peak memory | 146964 kb |
| Host | smart-2d9d2685-49f5-4fbf-b710-25c4e35c9b57 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=393312939 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 404.prim_prince_test.393312939 |
| Directory | /workspace/404.prim_prince_test/latest |
| Test location | /workspace/coverage/default/405.prim_prince_test.3851221642 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 2575511529 ps |
| CPU time | 43.38 seconds |
| Started | Feb 18 12:36:47 PM PST 24 |
| Finished | Feb 18 12:37:43 PM PST 24 |
| Peak memory | 146976 kb |
| Host | smart-14307b95-6dd9-4c12-9806-d03cfd4f9038 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3851221642 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 405.prim_prince_test.3851221642 |
| Directory | /workspace/405.prim_prince_test/latest |
| Test location | /workspace/coverage/default/406.prim_prince_test.2924538064 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 1184779593 ps |
| CPU time | 20.55 seconds |
| Started | Feb 18 12:36:53 PM PST 24 |
| Finished | Feb 18 12:37:20 PM PST 24 |
| Peak memory | 146836 kb |
| Host | smart-78476fa0-d219-4afc-bceb-05c21f694893 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2924538064 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 406.prim_prince_test.2924538064 |
| Directory | /workspace/406.prim_prince_test/latest |
| Test location | /workspace/coverage/default/407.prim_prince_test.2309758022 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 1563069936 ps |
| CPU time | 27.41 seconds |
| Started | Feb 18 12:36:55 PM PST 24 |
| Finished | Feb 18 12:37:33 PM PST 24 |
| Peak memory | 146836 kb |
| Host | smart-89ad704a-991b-4a82-890b-225cb488c2ca |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2309758022 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 407.prim_prince_test.2309758022 |
| Directory | /workspace/407.prim_prince_test/latest |
| Test location | /workspace/coverage/default/408.prim_prince_test.4144683814 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 2794290344 ps |
| CPU time | 47.53 seconds |
| Started | Feb 18 12:36:49 PM PST 24 |
| Finished | Feb 18 12:37:48 PM PST 24 |
| Peak memory | 146956 kb |
| Host | smart-7fb49000-e4b1-4fda-bd70-7296c893fe5b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4144683814 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 408.prim_prince_test.4144683814 |
| Directory | /workspace/408.prim_prince_test/latest |
| Test location | /workspace/coverage/default/409.prim_prince_test.2622511050 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 1849247129 ps |
| CPU time | 30.87 seconds |
| Started | Feb 18 12:36:54 PM PST 24 |
| Finished | Feb 18 12:37:35 PM PST 24 |
| Peak memory | 146856 kb |
| Host | smart-899d8457-c1ff-456b-9c21-a1ace297deed |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2622511050 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 409.prim_prince_test.2622511050 |
| Directory | /workspace/409.prim_prince_test/latest |
| Test location | /workspace/coverage/default/41.prim_prince_test.3492346706 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 840342656 ps |
| CPU time | 14.09 seconds |
| Started | Feb 18 12:35:55 PM PST 24 |
| Finished | Feb 18 12:36:15 PM PST 24 |
| Peak memory | 146780 kb |
| Host | smart-313d3ecb-bb25-4dac-b513-beea26f120d0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3492346706 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_prince_test.3492346706 |
| Directory | /workspace/41.prim_prince_test/latest |
| Test location | /workspace/coverage/default/410.prim_prince_test.2913170284 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 1235114082 ps |
| CPU time | 20.13 seconds |
| Started | Feb 18 12:36:49 PM PST 24 |
| Finished | Feb 18 12:37:15 PM PST 24 |
| Peak memory | 146828 kb |
| Host | smart-a7c13792-3685-4f1d-88a6-9a4b6e0716ea |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2913170284 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 410.prim_prince_test.2913170284 |
| Directory | /workspace/410.prim_prince_test/latest |
| Test location | /workspace/coverage/default/411.prim_prince_test.1512659355 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 1987542996 ps |
| CPU time | 32.54 seconds |
| Started | Feb 18 12:36:50 PM PST 24 |
| Finished | Feb 18 12:37:31 PM PST 24 |
| Peak memory | 146876 kb |
| Host | smart-d27ae702-21e8-4f2c-9941-b87a8f976c8e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1512659355 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 411.prim_prince_test.1512659355 |
| Directory | /workspace/411.prim_prince_test/latest |
| Test location | /workspace/coverage/default/412.prim_prince_test.3256328632 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 3462595318 ps |
| CPU time | 58.75 seconds |
| Started | Feb 18 12:36:52 PM PST 24 |
| Finished | Feb 18 12:38:07 PM PST 24 |
| Peak memory | 146936 kb |
| Host | smart-881fff87-bec2-40d4-9f44-88f4dde66618 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3256328632 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 412.prim_prince_test.3256328632 |
| Directory | /workspace/412.prim_prince_test/latest |
| Test location | /workspace/coverage/default/413.prim_prince_test.686563403 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 3339360796 ps |
| CPU time | 56.41 seconds |
| Started | Feb 18 12:36:50 PM PST 24 |
| Finished | Feb 18 12:38:02 PM PST 24 |
| Peak memory | 146976 kb |
| Host | smart-cfa2b2e0-2825-4b6b-bf4e-0828322c0479 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=686563403 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 413.prim_prince_test.686563403 |
| Directory | /workspace/413.prim_prince_test/latest |
| Test location | /workspace/coverage/default/414.prim_prince_test.2555673660 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 2757607155 ps |
| CPU time | 47.05 seconds |
| Started | Feb 18 12:37:01 PM PST 24 |
| Finished | Feb 18 12:38:01 PM PST 24 |
| Peak memory | 146140 kb |
| Host | smart-c05b8633-68c3-438c-b76e-5e074a22e692 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2555673660 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 414.prim_prince_test.2555673660 |
| Directory | /workspace/414.prim_prince_test/latest |
| Test location | /workspace/coverage/default/415.prim_prince_test.2851823618 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 3524303244 ps |
| CPU time | 57.87 seconds |
| Started | Feb 18 12:36:51 PM PST 24 |
| Finished | Feb 18 12:38:04 PM PST 24 |
| Peak memory | 146972 kb |
| Host | smart-bda7cabb-a63a-4368-9f33-e6a309d30099 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2851823618 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 415.prim_prince_test.2851823618 |
| Directory | /workspace/415.prim_prince_test/latest |
| Test location | /workspace/coverage/default/416.prim_prince_test.2040996439 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 1782109137 ps |
| CPU time | 29.64 seconds |
| Started | Feb 18 12:36:57 PM PST 24 |
| Finished | Feb 18 12:37:36 PM PST 24 |
| Peak memory | 146828 kb |
| Host | smart-e2cdf493-8706-43db-933b-ea3a0620edf5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2040996439 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 416.prim_prince_test.2040996439 |
| Directory | /workspace/416.prim_prince_test/latest |
| Test location | /workspace/coverage/default/417.prim_prince_test.1169706187 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 1508415289 ps |
| CPU time | 25.66 seconds |
| Started | Feb 18 12:37:09 PM PST 24 |
| Finished | Feb 18 12:37:42 PM PST 24 |
| Peak memory | 146800 kb |
| Host | smart-4764be55-79fc-40ae-b8c9-efaa613a7758 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1169706187 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 417.prim_prince_test.1169706187 |
| Directory | /workspace/417.prim_prince_test/latest |
| Test location | /workspace/coverage/default/418.prim_prince_test.2798525471 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 2756436433 ps |
| CPU time | 44.72 seconds |
| Started | Feb 18 12:36:57 PM PST 24 |
| Finished | Feb 18 12:37:55 PM PST 24 |
| Peak memory | 146948 kb |
| Host | smart-bc4ba03e-518c-4eb5-8c28-46d2f1de7f51 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2798525471 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 418.prim_prince_test.2798525471 |
| Directory | /workspace/418.prim_prince_test/latest |
| Test location | /workspace/coverage/default/419.prim_prince_test.104180402 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 2390426863 ps |
| CPU time | 39.17 seconds |
| Started | Feb 18 12:36:50 PM PST 24 |
| Finished | Feb 18 12:37:38 PM PST 24 |
| Peak memory | 146968 kb |
| Host | smart-21ebfede-d724-4e98-88dc-add66cfd5c63 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=104180402 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 419.prim_prince_test.104180402 |
| Directory | /workspace/419.prim_prince_test/latest |
| Test location | /workspace/coverage/default/42.prim_prince_test.768476335 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 3049333855 ps |
| CPU time | 51.26 seconds |
| Started | Feb 18 12:35:55 PM PST 24 |
| Finished | Feb 18 12:37:01 PM PST 24 |
| Peak memory | 146984 kb |
| Host | smart-5c4bf20a-d550-4ca9-af5e-c888ab1e716a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=768476335 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_prince_test.768476335 |
| Directory | /workspace/42.prim_prince_test/latest |
| Test location | /workspace/coverage/default/420.prim_prince_test.892521958 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 2048034006 ps |
| CPU time | 35.12 seconds |
| Started | Feb 18 12:36:58 PM PST 24 |
| Finished | Feb 18 12:37:45 PM PST 24 |
| Peak memory | 146940 kb |
| Host | smart-e8721fc2-cb85-4f61-aeec-a4aa55777e12 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=892521958 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 420.prim_prince_test.892521958 |
| Directory | /workspace/420.prim_prince_test/latest |
| Test location | /workspace/coverage/default/421.prim_prince_test.1530264533 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 2125036119 ps |
| CPU time | 35.97 seconds |
| Started | Feb 18 12:37:00 PM PST 24 |
| Finished | Feb 18 12:37:46 PM PST 24 |
| Peak memory | 146856 kb |
| Host | smart-c6fb1093-ebf1-48e7-acd2-8d328629b7d2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1530264533 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 421.prim_prince_test.1530264533 |
| Directory | /workspace/421.prim_prince_test/latest |
| Test location | /workspace/coverage/default/422.prim_prince_test.2972626070 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 3109819955 ps |
| CPU time | 52.02 seconds |
| Started | Feb 18 12:37:02 PM PST 24 |
| Finished | Feb 18 12:38:07 PM PST 24 |
| Peak memory | 146948 kb |
| Host | smart-3c409333-da4e-4634-b02a-4f818955c829 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2972626070 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 422.prim_prince_test.2972626070 |
| Directory | /workspace/422.prim_prince_test/latest |
| Test location | /workspace/coverage/default/423.prim_prince_test.2890660408 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 3594849176 ps |
| CPU time | 59.45 seconds |
| Started | Feb 18 12:36:58 PM PST 24 |
| Finished | Feb 18 12:38:13 PM PST 24 |
| Peak memory | 146960 kb |
| Host | smart-0aaa9271-2fc3-432b-8540-c7252ffe9642 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2890660408 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 423.prim_prince_test.2890660408 |
| Directory | /workspace/423.prim_prince_test/latest |
| Test location | /workspace/coverage/default/424.prim_prince_test.2367929594 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 3050188414 ps |
| CPU time | 50.75 seconds |
| Started | Feb 18 12:36:52 PM PST 24 |
| Finished | Feb 18 12:37:57 PM PST 24 |
| Peak memory | 146952 kb |
| Host | smart-3ca8dae8-ee2d-4017-9c17-db144a088c64 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2367929594 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 424.prim_prince_test.2367929594 |
| Directory | /workspace/424.prim_prince_test/latest |
| Test location | /workspace/coverage/default/425.prim_prince_test.417777103 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 3444040647 ps |
| CPU time | 57.69 seconds |
| Started | Feb 18 12:36:55 PM PST 24 |
| Finished | Feb 18 12:38:10 PM PST 24 |
| Peak memory | 146952 kb |
| Host | smart-814dd0b5-d54a-4c64-ad73-6a96f635be5f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=417777103 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 425.prim_prince_test.417777103 |
| Directory | /workspace/425.prim_prince_test/latest |
| Test location | /workspace/coverage/default/426.prim_prince_test.4042622027 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 1701358385 ps |
| CPU time | 28.93 seconds |
| Started | Feb 18 12:36:54 PM PST 24 |
| Finished | Feb 18 12:37:33 PM PST 24 |
| Peak memory | 146832 kb |
| Host | smart-256f5c4d-bed5-40d8-aafc-9644246ed794 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4042622027 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 426.prim_prince_test.4042622027 |
| Directory | /workspace/426.prim_prince_test/latest |
| Test location | /workspace/coverage/default/427.prim_prince_test.4077250194 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 948359048 ps |
| CPU time | 15.5 seconds |
| Started | Feb 18 12:36:57 PM PST 24 |
| Finished | Feb 18 12:37:19 PM PST 24 |
| Peak memory | 146828 kb |
| Host | smart-2b2a3de2-9fd5-4e5b-91fe-8cfaddf22359 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4077250194 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 427.prim_prince_test.4077250194 |
| Directory | /workspace/427.prim_prince_test/latest |
| Test location | /workspace/coverage/default/428.prim_prince_test.2052827732 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 1839123366 ps |
| CPU time | 30.37 seconds |
| Started | Feb 18 12:36:56 PM PST 24 |
| Finished | Feb 18 12:37:36 PM PST 24 |
| Peak memory | 146832 kb |
| Host | smart-cf016a58-9aae-41f2-98b6-b27bda4e19ae |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2052827732 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 428.prim_prince_test.2052827732 |
| Directory | /workspace/428.prim_prince_test/latest |
| Test location | /workspace/coverage/default/429.prim_prince_test.1378913961 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 2349716690 ps |
| CPU time | 40.49 seconds |
| Started | Feb 18 12:36:53 PM PST 24 |
| Finished | Feb 18 12:37:46 PM PST 24 |
| Peak memory | 146936 kb |
| Host | smart-53507bfa-0a6c-4935-b7bc-d56490115d6f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1378913961 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 429.prim_prince_test.1378913961 |
| Directory | /workspace/429.prim_prince_test/latest |
| Test location | /workspace/coverage/default/43.prim_prince_test.3815627769 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 1804045896 ps |
| CPU time | 31.39 seconds |
| Started | Feb 18 12:36:00 PM PST 24 |
| Finished | Feb 18 12:36:43 PM PST 24 |
| Peak memory | 146892 kb |
| Host | smart-bf5e52fe-b03a-454e-91ee-a5f96c70e5c9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3815627769 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_prince_test.3815627769 |
| Directory | /workspace/43.prim_prince_test/latest |
| Test location | /workspace/coverage/default/430.prim_prince_test.1894872360 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 3529706396 ps |
| CPU time | 59 seconds |
| Started | Feb 18 12:36:53 PM PST 24 |
| Finished | Feb 18 12:38:08 PM PST 24 |
| Peak memory | 146936 kb |
| Host | smart-60b487f1-473d-4a47-bde1-fa91da23bf25 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1894872360 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 430.prim_prince_test.1894872360 |
| Directory | /workspace/430.prim_prince_test/latest |
| Test location | /workspace/coverage/default/431.prim_prince_test.173626345 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 3012189747 ps |
| CPU time | 50.63 seconds |
| Started | Feb 18 12:37:06 PM PST 24 |
| Finished | Feb 18 12:38:09 PM PST 24 |
| Peak memory | 146916 kb |
| Host | smart-2070f31f-205e-4eea-84e1-3cf43f691d00 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=173626345 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 431.prim_prince_test.173626345 |
| Directory | /workspace/431.prim_prince_test/latest |
| Test location | /workspace/coverage/default/432.prim_prince_test.4059195498 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 3485123080 ps |
| CPU time | 60.01 seconds |
| Started | Feb 18 12:37:01 PM PST 24 |
| Finished | Feb 18 12:38:17 PM PST 24 |
| Peak memory | 146944 kb |
| Host | smart-ee454fe8-52a5-47e8-829a-842fcb06e086 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4059195498 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 432.prim_prince_test.4059195498 |
| Directory | /workspace/432.prim_prince_test/latest |
| Test location | /workspace/coverage/default/433.prim_prince_test.1278487075 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 2411028673 ps |
| CPU time | 40.86 seconds |
| Started | Feb 18 12:37:01 PM PST 24 |
| Finished | Feb 18 12:37:53 PM PST 24 |
| Peak memory | 146088 kb |
| Host | smart-8418dc4a-662e-403f-b740-f0c0d4c91568 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1278487075 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 433.prim_prince_test.1278487075 |
| Directory | /workspace/433.prim_prince_test/latest |
| Test location | /workspace/coverage/default/434.prim_prince_test.955730579 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 1523339754 ps |
| CPU time | 26.91 seconds |
| Started | Feb 18 12:37:01 PM PST 24 |
| Finished | Feb 18 12:37:36 PM PST 24 |
| Peak memory | 146848 kb |
| Host | smart-c778fcfc-6b48-47e0-8f0d-d365e445abef |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=955730579 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 434.prim_prince_test.955730579 |
| Directory | /workspace/434.prim_prince_test/latest |
| Test location | /workspace/coverage/default/435.prim_prince_test.2691415188 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 3288850157 ps |
| CPU time | 56.13 seconds |
| Started | Feb 18 12:37:04 PM PST 24 |
| Finished | Feb 18 12:38:14 PM PST 24 |
| Peak memory | 146936 kb |
| Host | smart-6916fb30-ac7a-41f1-9ba8-8e054258b269 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2691415188 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 435.prim_prince_test.2691415188 |
| Directory | /workspace/435.prim_prince_test/latest |
| Test location | /workspace/coverage/default/436.prim_prince_test.987998508 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 2232482648 ps |
| CPU time | 38.45 seconds |
| Started | Feb 18 12:37:13 PM PST 24 |
| Finished | Feb 18 12:38:01 PM PST 24 |
| Peak memory | 146860 kb |
| Host | smart-054d374f-8505-43f2-be77-a8f157ea2328 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=987998508 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 436.prim_prince_test.987998508 |
| Directory | /workspace/436.prim_prince_test/latest |
| Test location | /workspace/coverage/default/437.prim_prince_test.4092376424 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 3194821966 ps |
| CPU time | 53.32 seconds |
| Started | Feb 18 12:36:58 PM PST 24 |
| Finished | Feb 18 12:38:06 PM PST 24 |
| Peak memory | 146944 kb |
| Host | smart-015674bc-a9bd-420c-899d-b4250cf05224 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4092376424 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 437.prim_prince_test.4092376424 |
| Directory | /workspace/437.prim_prince_test/latest |
| Test location | /workspace/coverage/default/438.prim_prince_test.3793025965 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 3087857854 ps |
| CPU time | 51.36 seconds |
| Started | Feb 18 12:36:58 PM PST 24 |
| Finished | Feb 18 12:38:04 PM PST 24 |
| Peak memory | 147024 kb |
| Host | smart-478f056c-addd-4dc0-8df6-38b52a5cf3a7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3793025965 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 438.prim_prince_test.3793025965 |
| Directory | /workspace/438.prim_prince_test/latest |
| Test location | /workspace/coverage/default/439.prim_prince_test.2574271626 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 1563438465 ps |
| CPU time | 26.21 seconds |
| Started | Feb 18 12:36:59 PM PST 24 |
| Finished | Feb 18 12:37:34 PM PST 24 |
| Peak memory | 146828 kb |
| Host | smart-249c04d0-340e-465f-ae5d-04ac139e818a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2574271626 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 439.prim_prince_test.2574271626 |
| Directory | /workspace/439.prim_prince_test/latest |
| Test location | /workspace/coverage/default/44.prim_prince_test.773841387 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 3418094243 ps |
| CPU time | 57.48 seconds |
| Started | Feb 18 12:36:02 PM PST 24 |
| Finished | Feb 18 12:37:16 PM PST 24 |
| Peak memory | 147008 kb |
| Host | smart-52f68601-2d67-439a-9eb9-714916cb0b01 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=773841387 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_prince_test.773841387 |
| Directory | /workspace/44.prim_prince_test/latest |
| Test location | /workspace/coverage/default/440.prim_prince_test.3600862527 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 3273490752 ps |
| CPU time | 56.79 seconds |
| Started | Feb 18 12:37:07 PM PST 24 |
| Finished | Feb 18 12:38:18 PM PST 24 |
| Peak memory | 147060 kb |
| Host | smart-31b43c30-1fb4-4738-9c1c-df3424c3889f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3600862527 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 440.prim_prince_test.3600862527 |
| Directory | /workspace/440.prim_prince_test/latest |
| Test location | /workspace/coverage/default/441.prim_prince_test.327018217 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 758253144 ps |
| CPU time | 12.86 seconds |
| Started | Feb 18 12:36:58 PM PST 24 |
| Finished | Feb 18 12:37:17 PM PST 24 |
| Peak memory | 146912 kb |
| Host | smart-9f458089-d630-4d76-80b0-156e75167c79 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=327018217 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 441.prim_prince_test.327018217 |
| Directory | /workspace/441.prim_prince_test/latest |
| Test location | /workspace/coverage/default/442.prim_prince_test.2934619335 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 2346642785 ps |
| CPU time | 39.91 seconds |
| Started | Feb 18 12:37:03 PM PST 24 |
| Finished | Feb 18 12:37:54 PM PST 24 |
| Peak memory | 146956 kb |
| Host | smart-a8c60059-f6f3-4c7b-b726-b81b6e6a7626 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2934619335 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 442.prim_prince_test.2934619335 |
| Directory | /workspace/442.prim_prince_test/latest |
| Test location | /workspace/coverage/default/443.prim_prince_test.2451125567 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 1216373834 ps |
| CPU time | 20.68 seconds |
| Started | Feb 18 12:37:13 PM PST 24 |
| Finished | Feb 18 12:37:40 PM PST 24 |
| Peak memory | 146744 kb |
| Host | smart-959b2f1b-1006-4fef-9ecd-7994693c80ea |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2451125567 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 443.prim_prince_test.2451125567 |
| Directory | /workspace/443.prim_prince_test/latest |
| Test location | /workspace/coverage/default/444.prim_prince_test.4288862992 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 3083236044 ps |
| CPU time | 49.44 seconds |
| Started | Feb 18 12:37:00 PM PST 24 |
| Finished | Feb 18 12:38:01 PM PST 24 |
| Peak memory | 146892 kb |
| Host | smart-d8ddf836-3315-4940-95f7-5d13c6f00a10 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4288862992 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 444.prim_prince_test.4288862992 |
| Directory | /workspace/444.prim_prince_test/latest |
| Test location | /workspace/coverage/default/445.prim_prince_test.2087054196 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 3745479654 ps |
| CPU time | 64.9 seconds |
| Started | Feb 18 12:37:04 PM PST 24 |
| Finished | Feb 18 12:38:26 PM PST 24 |
| Peak memory | 147032 kb |
| Host | smart-23791e71-a980-4fb1-b31d-e89ee6554f38 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2087054196 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 445.prim_prince_test.2087054196 |
| Directory | /workspace/445.prim_prince_test/latest |
| Test location | /workspace/coverage/default/446.prim_prince_test.368977448 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 3474426431 ps |
| CPU time | 59.46 seconds |
| Started | Feb 18 12:37:03 PM PST 24 |
| Finished | Feb 18 12:38:17 PM PST 24 |
| Peak memory | 146948 kb |
| Host | smart-b60a0fd6-fe74-496b-81ea-f788750118ad |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=368977448 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 446.prim_prince_test.368977448 |
| Directory | /workspace/446.prim_prince_test/latest |
| Test location | /workspace/coverage/default/447.prim_prince_test.2822761688 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 834257460 ps |
| CPU time | 14.23 seconds |
| Started | Feb 18 12:37:13 PM PST 24 |
| Finished | Feb 18 12:37:32 PM PST 24 |
| Peak memory | 146744 kb |
| Host | smart-907659ad-c349-4668-bec7-93f2e889d53a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2822761688 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 447.prim_prince_test.2822761688 |
| Directory | /workspace/447.prim_prince_test/latest |
| Test location | /workspace/coverage/default/448.prim_prince_test.1581155085 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 2608244586 ps |
| CPU time | 44.51 seconds |
| Started | Feb 18 12:37:05 PM PST 24 |
| Finished | Feb 18 12:38:02 PM PST 24 |
| Peak memory | 147040 kb |
| Host | smart-594b850a-8172-4d63-90fa-f63e29a4f82c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1581155085 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 448.prim_prince_test.1581155085 |
| Directory | /workspace/448.prim_prince_test/latest |
| Test location | /workspace/coverage/default/449.prim_prince_test.1970315465 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 1090495483 ps |
| CPU time | 18.68 seconds |
| Started | Feb 18 12:37:05 PM PST 24 |
| Finished | Feb 18 12:37:29 PM PST 24 |
| Peak memory | 146720 kb |
| Host | smart-568350a9-7dfd-46b5-bbd8-01cd37c5bfc6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1970315465 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 449.prim_prince_test.1970315465 |
| Directory | /workspace/449.prim_prince_test/latest |
| Test location | /workspace/coverage/default/45.prim_prince_test.276588076 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 1725657607 ps |
| CPU time | 28.98 seconds |
| Started | Feb 18 12:36:04 PM PST 24 |
| Finished | Feb 18 12:36:41 PM PST 24 |
| Peak memory | 146864 kb |
| Host | smart-5a5d96ad-d955-4ba5-846e-d49e9153f5c9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=276588076 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_prince_test.276588076 |
| Directory | /workspace/45.prim_prince_test/latest |
| Test location | /workspace/coverage/default/450.prim_prince_test.2696695509 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 2720116964 ps |
| CPU time | 44.76 seconds |
| Started | Feb 18 12:37:08 PM PST 24 |
| Finished | Feb 18 12:38:03 PM PST 24 |
| Peak memory | 146948 kb |
| Host | smart-73e3cd8f-c4e9-4a09-b5ff-72d40fbf79ff |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2696695509 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 450.prim_prince_test.2696695509 |
| Directory | /workspace/450.prim_prince_test/latest |
| Test location | /workspace/coverage/default/451.prim_prince_test.335981539 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 2907961405 ps |
| CPU time | 48.44 seconds |
| Started | Feb 18 12:37:08 PM PST 24 |
| Finished | Feb 18 12:38:07 PM PST 24 |
| Peak memory | 146968 kb |
| Host | smart-5dffd9ec-eb0f-4f6b-8b0a-a134c2b8db57 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=335981539 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 451.prim_prince_test.335981539 |
| Directory | /workspace/451.prim_prince_test/latest |
| Test location | /workspace/coverage/default/452.prim_prince_test.530784463 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 2389106983 ps |
| CPU time | 40.04 seconds |
| Started | Feb 18 12:37:05 PM PST 24 |
| Finished | Feb 18 12:37:55 PM PST 24 |
| Peak memory | 146936 kb |
| Host | smart-060e4b61-70d0-4a43-aea2-d3a2744679e9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=530784463 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 452.prim_prince_test.530784463 |
| Directory | /workspace/452.prim_prince_test/latest |
| Test location | /workspace/coverage/default/453.prim_prince_test.2440679159 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 3132870257 ps |
| CPU time | 52.63 seconds |
| Started | Feb 18 12:37:13 PM PST 24 |
| Finished | Feb 18 12:38:19 PM PST 24 |
| Peak memory | 146864 kb |
| Host | smart-9084272e-dfab-4244-8f1b-46f0e4c755be |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2440679159 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 453.prim_prince_test.2440679159 |
| Directory | /workspace/453.prim_prince_test/latest |
| Test location | /workspace/coverage/default/454.prim_prince_test.1419918413 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 3540578937 ps |
| CPU time | 57.46 seconds |
| Started | Feb 18 12:37:08 PM PST 24 |
| Finished | Feb 18 12:38:21 PM PST 24 |
| Peak memory | 146996 kb |
| Host | smart-636411ff-14b8-466b-a563-2fa05465c50f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1419918413 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 454.prim_prince_test.1419918413 |
| Directory | /workspace/454.prim_prince_test/latest |
| Test location | /workspace/coverage/default/455.prim_prince_test.2196131881 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 1452217140 ps |
| CPU time | 24.13 seconds |
| Started | Feb 18 12:37:06 PM PST 24 |
| Finished | Feb 18 12:37:36 PM PST 24 |
| Peak memory | 146820 kb |
| Host | smart-97a7a4ac-a91a-424c-9699-698516fd8680 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2196131881 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 455.prim_prince_test.2196131881 |
| Directory | /workspace/455.prim_prince_test/latest |
| Test location | /workspace/coverage/default/456.prim_prince_test.3346001736 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 2506941807 ps |
| CPU time | 43.04 seconds |
| Started | Feb 18 12:37:05 PM PST 24 |
| Finished | Feb 18 12:38:00 PM PST 24 |
| Peak memory | 146976 kb |
| Host | smart-996d98b6-123f-42f7-95b1-c59b310914c0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3346001736 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 456.prim_prince_test.3346001736 |
| Directory | /workspace/456.prim_prince_test/latest |
| Test location | /workspace/coverage/default/457.prim_prince_test.320710637 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 2816152314 ps |
| CPU time | 47.64 seconds |
| Started | Feb 18 12:37:04 PM PST 24 |
| Finished | Feb 18 12:38:04 PM PST 24 |
| Peak memory | 146976 kb |
| Host | smart-d943a6a6-0ec7-41bd-b810-c2143d769e84 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=320710637 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 457.prim_prince_test.320710637 |
| Directory | /workspace/457.prim_prince_test/latest |
| Test location | /workspace/coverage/default/458.prim_prince_test.2984186570 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 2400305314 ps |
| CPU time | 40.54 seconds |
| Started | Feb 18 12:37:13 PM PST 24 |
| Finished | Feb 18 12:38:04 PM PST 24 |
| Peak memory | 146864 kb |
| Host | smart-8a95239d-8e91-4bb2-abf7-c5428b74f71c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2984186570 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 458.prim_prince_test.2984186570 |
| Directory | /workspace/458.prim_prince_test/latest |
| Test location | /workspace/coverage/default/459.prim_prince_test.1735433604 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 2324894757 ps |
| CPU time | 38.39 seconds |
| Started | Feb 18 12:37:04 PM PST 24 |
| Finished | Feb 18 12:37:51 PM PST 24 |
| Peak memory | 146976 kb |
| Host | smart-dd8151d9-de53-4e31-be4f-84402f0e2498 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1735433604 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 459.prim_prince_test.1735433604 |
| Directory | /workspace/459.prim_prince_test/latest |
| Test location | /workspace/coverage/default/46.prim_prince_test.760525450 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 2055357462 ps |
| CPU time | 34.92 seconds |
| Started | Feb 18 12:35:58 PM PST 24 |
| Finished | Feb 18 12:36:44 PM PST 24 |
| Peak memory | 146928 kb |
| Host | smart-da2bd5fc-e976-486d-b596-59244c3eb5ac |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=760525450 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_prince_test.760525450 |
| Directory | /workspace/46.prim_prince_test/latest |
| Test location | /workspace/coverage/default/460.prim_prince_test.2663047362 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 3521532161 ps |
| CPU time | 58.39 seconds |
| Started | Feb 18 12:37:10 PM PST 24 |
| Finished | Feb 18 12:38:21 PM PST 24 |
| Peak memory | 146956 kb |
| Host | smart-af1a8c32-76a8-4bda-8995-c3416707ce4b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2663047362 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 460.prim_prince_test.2663047362 |
| Directory | /workspace/460.prim_prince_test/latest |
| Test location | /workspace/coverage/default/461.prim_prince_test.4075029465 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 3465817772 ps |
| CPU time | 56.83 seconds |
| Started | Feb 18 12:37:08 PM PST 24 |
| Finished | Feb 18 12:38:19 PM PST 24 |
| Peak memory | 147012 kb |
| Host | smart-941f5400-051f-4401-9274-44e593210deb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4075029465 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 461.prim_prince_test.4075029465 |
| Directory | /workspace/461.prim_prince_test/latest |
| Test location | /workspace/coverage/default/462.prim_prince_test.1693357731 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 1106245548 ps |
| CPU time | 18.72 seconds |
| Started | Feb 18 12:37:07 PM PST 24 |
| Finished | Feb 18 12:37:31 PM PST 24 |
| Peak memory | 146856 kb |
| Host | smart-056240d7-5299-4cc4-8f51-f7a8bc50b21e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1693357731 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 462.prim_prince_test.1693357731 |
| Directory | /workspace/462.prim_prince_test/latest |
| Test location | /workspace/coverage/default/463.prim_prince_test.3121833510 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 3396114595 ps |
| CPU time | 55.94 seconds |
| Started | Feb 18 12:37:15 PM PST 24 |
| Finished | Feb 18 12:38:23 PM PST 24 |
| Peak memory | 146908 kb |
| Host | smart-42353a21-9adc-4832-a768-b6c83b584f88 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3121833510 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 463.prim_prince_test.3121833510 |
| Directory | /workspace/463.prim_prince_test/latest |
| Test location | /workspace/coverage/default/464.prim_prince_test.3807727996 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 1936248663 ps |
| CPU time | 32.3 seconds |
| Started | Feb 18 12:37:09 PM PST 24 |
| Finished | Feb 18 12:37:50 PM PST 24 |
| Peak memory | 146852 kb |
| Host | smart-394637f7-f87f-48f9-b662-55468d1a1716 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3807727996 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 464.prim_prince_test.3807727996 |
| Directory | /workspace/464.prim_prince_test/latest |
| Test location | /workspace/coverage/default/465.prim_prince_test.3647879034 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 3326961476 ps |
| CPU time | 54.28 seconds |
| Started | Feb 18 12:37:13 PM PST 24 |
| Finished | Feb 18 12:38:19 PM PST 24 |
| Peak memory | 146908 kb |
| Host | smart-75701d59-654e-4042-b152-dab366c3028f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3647879034 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 465.prim_prince_test.3647879034 |
| Directory | /workspace/465.prim_prince_test/latest |
| Test location | /workspace/coverage/default/466.prim_prince_test.267643207 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 2431937267 ps |
| CPU time | 40.62 seconds |
| Started | Feb 18 12:37:10 PM PST 24 |
| Finished | Feb 18 12:38:03 PM PST 24 |
| Peak memory | 146972 kb |
| Host | smart-6d314743-8e8d-4f15-afe7-7322c09937f4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=267643207 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 466.prim_prince_test.267643207 |
| Directory | /workspace/466.prim_prince_test/latest |
| Test location | /workspace/coverage/default/467.prim_prince_test.683053036 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 2062539848 ps |
| CPU time | 34.77 seconds |
| Started | Feb 18 12:37:14 PM PST 24 |
| Finished | Feb 18 12:37:57 PM PST 24 |
| Peak memory | 146164 kb |
| Host | smart-0a25626b-ffef-48dd-9af6-4f71aaf3ace8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=683053036 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 467.prim_prince_test.683053036 |
| Directory | /workspace/467.prim_prince_test/latest |
| Test location | /workspace/coverage/default/468.prim_prince_test.1467100508 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 2465777829 ps |
| CPU time | 41.35 seconds |
| Started | Feb 18 12:37:11 PM PST 24 |
| Finished | Feb 18 12:38:03 PM PST 24 |
| Peak memory | 146960 kb |
| Host | smart-18853f55-0e04-47c0-8001-7fba597271d8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1467100508 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 468.prim_prince_test.1467100508 |
| Directory | /workspace/468.prim_prince_test/latest |
| Test location | /workspace/coverage/default/469.prim_prince_test.1485535870 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 2297218830 ps |
| CPU time | 39.15 seconds |
| Started | Feb 18 12:37:10 PM PST 24 |
| Finished | Feb 18 12:38:00 PM PST 24 |
| Peak memory | 147064 kb |
| Host | smart-511df8c7-9b36-48d4-83b3-b42ceeadd0b6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1485535870 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 469.prim_prince_test.1485535870 |
| Directory | /workspace/469.prim_prince_test/latest |
| Test location | /workspace/coverage/default/47.prim_prince_test.1745670069 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 1362273654 ps |
| CPU time | 22.96 seconds |
| Started | Feb 18 12:36:09 PM PST 24 |
| Finished | Feb 18 12:36:39 PM PST 24 |
| Peak memory | 146780 kb |
| Host | smart-33442d39-4af3-4c68-9bdc-20ee6e51efb2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1745670069 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_prince_test.1745670069 |
| Directory | /workspace/47.prim_prince_test/latest |
| Test location | /workspace/coverage/default/470.prim_prince_test.1549609828 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 1736125683 ps |
| CPU time | 28.43 seconds |
| Started | Feb 18 12:37:10 PM PST 24 |
| Finished | Feb 18 12:37:46 PM PST 24 |
| Peak memory | 146916 kb |
| Host | smart-d8b8b5f1-9b44-4bed-8ce2-dbbe010d8f40 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1549609828 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 470.prim_prince_test.1549609828 |
| Directory | /workspace/470.prim_prince_test/latest |
| Test location | /workspace/coverage/default/471.prim_prince_test.2803573549 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 3309555150 ps |
| CPU time | 55.72 seconds |
| Started | Feb 18 12:37:11 PM PST 24 |
| Finished | Feb 18 12:38:22 PM PST 24 |
| Peak memory | 146976 kb |
| Host | smart-2947fa27-eac3-43b9-8cbe-c6a4655514ce |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2803573549 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 471.prim_prince_test.2803573549 |
| Directory | /workspace/471.prim_prince_test/latest |
| Test location | /workspace/coverage/default/472.prim_prince_test.2321077713 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 1206147230 ps |
| CPU time | 20.56 seconds |
| Started | Feb 18 12:37:11 PM PST 24 |
| Finished | Feb 18 12:37:38 PM PST 24 |
| Peak memory | 146820 kb |
| Host | smart-dbfa21c4-afe1-468d-aeef-f3a99599bff7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2321077713 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 472.prim_prince_test.2321077713 |
| Directory | /workspace/472.prim_prince_test/latest |
| Test location | /workspace/coverage/default/473.prim_prince_test.894819296 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 1183053142 ps |
| CPU time | 20.33 seconds |
| Started | Feb 18 12:37:11 PM PST 24 |
| Finished | Feb 18 12:37:38 PM PST 24 |
| Peak memory | 146828 kb |
| Host | smart-f3490f1c-b9f4-4968-a633-d983ba998752 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=894819296 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 473.prim_prince_test.894819296 |
| Directory | /workspace/473.prim_prince_test/latest |
| Test location | /workspace/coverage/default/474.prim_prince_test.485692705 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 3083560572 ps |
| CPU time | 52.12 seconds |
| Started | Feb 18 12:37:14 PM PST 24 |
| Finished | Feb 18 12:38:18 PM PST 24 |
| Peak memory | 146328 kb |
| Host | smart-37f6e29b-2d68-47b1-b954-f1588b643164 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=485692705 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 474.prim_prince_test.485692705 |
| Directory | /workspace/474.prim_prince_test/latest |
| Test location | /workspace/coverage/default/475.prim_prince_test.4060914062 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 1211812123 ps |
| CPU time | 20.99 seconds |
| Started | Feb 18 12:37:15 PM PST 24 |
| Finished | Feb 18 12:37:42 PM PST 24 |
| Peak memory | 146824 kb |
| Host | smart-475dae2c-8cd7-4992-9949-2455c7f2a3b8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4060914062 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 475.prim_prince_test.4060914062 |
| Directory | /workspace/475.prim_prince_test/latest |
| Test location | /workspace/coverage/default/476.prim_prince_test.1978546363 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 2985987598 ps |
| CPU time | 50 seconds |
| Started | Feb 18 12:37:20 PM PST 24 |
| Finished | Feb 18 12:38:22 PM PST 24 |
| Peak memory | 146908 kb |
| Host | smart-f0143617-c5d5-4ea8-9d5b-a4bebd00de73 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1978546363 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 476.prim_prince_test.1978546363 |
| Directory | /workspace/476.prim_prince_test/latest |
| Test location | /workspace/coverage/default/477.prim_prince_test.3221844381 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 780777310 ps |
| CPU time | 13.54 seconds |
| Started | Feb 18 12:37:15 PM PST 24 |
| Finished | Feb 18 12:37:33 PM PST 24 |
| Peak memory | 146768 kb |
| Host | smart-bba580b4-42a8-45f0-a79c-e6fb648a72be |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3221844381 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 477.prim_prince_test.3221844381 |
| Directory | /workspace/477.prim_prince_test/latest |
| Test location | /workspace/coverage/default/478.prim_prince_test.2303382402 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 2018354037 ps |
| CPU time | 34.32 seconds |
| Started | Feb 18 12:37:19 PM PST 24 |
| Finished | Feb 18 12:38:02 PM PST 24 |
| Peak memory | 146840 kb |
| Host | smart-f91e1af1-d866-4c92-b537-f96990d6aaa4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2303382402 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 478.prim_prince_test.2303382402 |
| Directory | /workspace/478.prim_prince_test/latest |
| Test location | /workspace/coverage/default/479.prim_prince_test.2384598818 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 1896058124 ps |
| CPU time | 31.29 seconds |
| Started | Feb 18 12:37:17 PM PST 24 |
| Finished | Feb 18 12:37:56 PM PST 24 |
| Peak memory | 146856 kb |
| Host | smart-3855717e-cca8-4a53-a375-64794064a745 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2384598818 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 479.prim_prince_test.2384598818 |
| Directory | /workspace/479.prim_prince_test/latest |
| Test location | /workspace/coverage/default/48.prim_prince_test.2757120239 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 1641256943 ps |
| CPU time | 27.77 seconds |
| Started | Feb 18 12:36:05 PM PST 24 |
| Finished | Feb 18 12:36:40 PM PST 24 |
| Peak memory | 146856 kb |
| Host | smart-5754fe7e-1eb1-451b-9475-2ded59b236c1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2757120239 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_prince_test.2757120239 |
| Directory | /workspace/48.prim_prince_test/latest |
| Test location | /workspace/coverage/default/480.prim_prince_test.3742910759 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 1556130713 ps |
| CPU time | 25.83 seconds |
| Started | Feb 18 12:37:17 PM PST 24 |
| Finished | Feb 18 12:37:49 PM PST 24 |
| Peak memory | 146944 kb |
| Host | smart-375dd8c6-78bb-411d-9cfe-de71c18df05f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3742910759 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 480.prim_prince_test.3742910759 |
| Directory | /workspace/480.prim_prince_test/latest |
| Test location | /workspace/coverage/default/481.prim_prince_test.2107216196 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 1439361043 ps |
| CPU time | 24.66 seconds |
| Started | Feb 18 12:37:18 PM PST 24 |
| Finished | Feb 18 12:37:50 PM PST 24 |
| Peak memory | 146856 kb |
| Host | smart-aa8d59b4-13a2-492d-8981-fe40700bc1f7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2107216196 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 481.prim_prince_test.2107216196 |
| Directory | /workspace/481.prim_prince_test/latest |
| Test location | /workspace/coverage/default/482.prim_prince_test.1294698391 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 805964246 ps |
| CPU time | 13.32 seconds |
| Started | Feb 18 12:37:15 PM PST 24 |
| Finished | Feb 18 12:37:32 PM PST 24 |
| Peak memory | 146832 kb |
| Host | smart-b189d3bc-cb6f-4b30-b570-cdf7332f5676 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1294698391 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 482.prim_prince_test.1294698391 |
| Directory | /workspace/482.prim_prince_test/latest |
| Test location | /workspace/coverage/default/483.prim_prince_test.109874800 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 2368367987 ps |
| CPU time | 39.51 seconds |
| Started | Feb 18 12:37:17 PM PST 24 |
| Finished | Feb 18 12:38:05 PM PST 24 |
| Peak memory | 146952 kb |
| Host | smart-4bd85de5-e161-43be-b98d-2f5a817b6c3c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=109874800 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 483.prim_prince_test.109874800 |
| Directory | /workspace/483.prim_prince_test/latest |
| Test location | /workspace/coverage/default/484.prim_prince_test.73722679 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 2435819437 ps |
| CPU time | 40.93 seconds |
| Started | Feb 18 12:37:17 PM PST 24 |
| Finished | Feb 18 12:38:08 PM PST 24 |
| Peak memory | 146984 kb |
| Host | smart-ce80322b-f291-4b4e-944b-82abeab030cb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=73722679 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 484.prim_prince_test.73722679 |
| Directory | /workspace/484.prim_prince_test/latest |
| Test location | /workspace/coverage/default/485.prim_prince_test.4091230940 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 3063635205 ps |
| CPU time | 50.97 seconds |
| Started | Feb 18 12:37:18 PM PST 24 |
| Finished | Feb 18 12:38:22 PM PST 24 |
| Peak memory | 146976 kb |
| Host | smart-adc13349-a39e-4197-a2c2-88cd8d872422 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4091230940 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 485.prim_prince_test.4091230940 |
| Directory | /workspace/485.prim_prince_test/latest |
| Test location | /workspace/coverage/default/486.prim_prince_test.4026237427 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 3563738701 ps |
| CPU time | 58.53 seconds |
| Started | Feb 18 12:37:19 PM PST 24 |
| Finished | Feb 18 12:38:31 PM PST 24 |
| Peak memory | 146840 kb |
| Host | smart-e9401f66-4921-4902-9ba6-c494e9f8a713 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4026237427 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 486.prim_prince_test.4026237427 |
| Directory | /workspace/486.prim_prince_test/latest |
| Test location | /workspace/coverage/default/487.prim_prince_test.2451823615 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 2468956705 ps |
| CPU time | 41.63 seconds |
| Started | Feb 18 12:37:18 PM PST 24 |
| Finished | Feb 18 12:38:09 PM PST 24 |
| Peak memory | 146956 kb |
| Host | smart-8cae9614-9592-419b-9cb8-2b450ac016cc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2451823615 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 487.prim_prince_test.2451823615 |
| Directory | /workspace/487.prim_prince_test/latest |
| Test location | /workspace/coverage/default/488.prim_prince_test.3719224104 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 1467794745 ps |
| CPU time | 25.57 seconds |
| Started | Feb 18 12:37:18 PM PST 24 |
| Finished | Feb 18 12:37:51 PM PST 24 |
| Peak memory | 146912 kb |
| Host | smart-e914f77e-de3f-4a99-82fa-5e744ac8a573 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3719224104 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 488.prim_prince_test.3719224104 |
| Directory | /workspace/488.prim_prince_test/latest |
| Test location | /workspace/coverage/default/489.prim_prince_test.383297600 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 3675946450 ps |
| CPU time | 61.21 seconds |
| Started | Feb 18 12:37:15 PM PST 24 |
| Finished | Feb 18 12:38:30 PM PST 24 |
| Peak memory | 146876 kb |
| Host | smart-8ba03cf5-81fa-4fee-9098-04e593dc0462 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=383297600 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 489.prim_prince_test.383297600 |
| Directory | /workspace/489.prim_prince_test/latest |
| Test location | /workspace/coverage/default/49.prim_prince_test.3691326775 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 1189975087 ps |
| CPU time | 19.81 seconds |
| Started | Feb 18 12:35:59 PM PST 24 |
| Finished | Feb 18 12:36:27 PM PST 24 |
| Peak memory | 146864 kb |
| Host | smart-bbe434fe-b951-422a-a7b4-55f14d12e23b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3691326775 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_prince_test.3691326775 |
| Directory | /workspace/49.prim_prince_test/latest |
| Test location | /workspace/coverage/default/490.prim_prince_test.1790913996 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 3021234840 ps |
| CPU time | 50.08 seconds |
| Started | Feb 18 12:37:20 PM PST 24 |
| Finished | Feb 18 12:38:21 PM PST 24 |
| Peak memory | 146840 kb |
| Host | smart-ed276f82-183d-47c0-9cb7-99490e8a307e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1790913996 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 490.prim_prince_test.1790913996 |
| Directory | /workspace/490.prim_prince_test/latest |
| Test location | /workspace/coverage/default/491.prim_prince_test.3292258818 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 1965190378 ps |
| CPU time | 32.65 seconds |
| Started | Feb 18 12:37:17 PM PST 24 |
| Finished | Feb 18 12:37:57 PM PST 24 |
| Peak memory | 146856 kb |
| Host | smart-ebddc84b-0ae3-40cb-8458-9e20cd6c74cd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3292258818 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 491.prim_prince_test.3292258818 |
| Directory | /workspace/491.prim_prince_test/latest |
| Test location | /workspace/coverage/default/492.prim_prince_test.4031553830 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 831822150 ps |
| CPU time | 14.46 seconds |
| Started | Feb 18 12:37:15 PM PST 24 |
| Finished | Feb 18 12:37:34 PM PST 24 |
| Peak memory | 146836 kb |
| Host | smart-c18c9a20-e8cf-41d1-ac03-6d46e4b8f1e1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4031553830 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 492.prim_prince_test.4031553830 |
| Directory | /workspace/492.prim_prince_test/latest |
| Test location | /workspace/coverage/default/493.prim_prince_test.1066769916 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 1664552716 ps |
| CPU time | 28.82 seconds |
| Started | Feb 18 12:37:18 PM PST 24 |
| Finished | Feb 18 12:37:55 PM PST 24 |
| Peak memory | 146920 kb |
| Host | smart-75ad3136-f7c9-4297-bf8d-82578c1c6045 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1066769916 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 493.prim_prince_test.1066769916 |
| Directory | /workspace/493.prim_prince_test/latest |
| Test location | /workspace/coverage/default/494.prim_prince_test.1559909571 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 3057065236 ps |
| CPU time | 51.5 seconds |
| Started | Feb 18 12:37:16 PM PST 24 |
| Finished | Feb 18 12:38:20 PM PST 24 |
| Peak memory | 146956 kb |
| Host | smart-206b32d4-f394-42ee-b04c-b75b23c06604 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1559909571 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 494.prim_prince_test.1559909571 |
| Directory | /workspace/494.prim_prince_test/latest |
| Test location | /workspace/coverage/default/495.prim_prince_test.2832311944 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 3336409621 ps |
| CPU time | 55.52 seconds |
| Started | Feb 18 12:37:14 PM PST 24 |
| Finished | Feb 18 12:38:23 PM PST 24 |
| Peak memory | 146960 kb |
| Host | smart-96cbf2c5-022e-4317-862d-48f396e48818 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2832311944 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 495.prim_prince_test.2832311944 |
| Directory | /workspace/495.prim_prince_test/latest |
| Test location | /workspace/coverage/default/496.prim_prince_test.2422758912 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 3656367278 ps |
| CPU time | 59.03 seconds |
| Started | Feb 18 12:37:15 PM PST 24 |
| Finished | Feb 18 12:38:26 PM PST 24 |
| Peak memory | 146956 kb |
| Host | smart-7e7e600b-619c-49ea-84fb-e929f5b83061 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2422758912 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 496.prim_prince_test.2422758912 |
| Directory | /workspace/496.prim_prince_test/latest |
| Test location | /workspace/coverage/default/497.prim_prince_test.1004722905 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 1340500653 ps |
| CPU time | 22.79 seconds |
| Started | Feb 18 12:37:17 PM PST 24 |
| Finished | Feb 18 12:37:46 PM PST 24 |
| Peak memory | 146836 kb |
| Host | smart-33304d96-458b-45b7-a395-f5f808996270 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1004722905 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 497.prim_prince_test.1004722905 |
| Directory | /workspace/497.prim_prince_test/latest |
| Test location | /workspace/coverage/default/498.prim_prince_test.1848263199 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 2568400924 ps |
| CPU time | 43.97 seconds |
| Started | Feb 18 12:37:18 PM PST 24 |
| Finished | Feb 18 12:38:14 PM PST 24 |
| Peak memory | 147040 kb |
| Host | smart-b1df66e5-662a-4f67-8ba4-507a704dfa21 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1848263199 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 498.prim_prince_test.1848263199 |
| Directory | /workspace/498.prim_prince_test/latest |
| Test location | /workspace/coverage/default/499.prim_prince_test.4000787876 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 3150572059 ps |
| CPU time | 52.12 seconds |
| Started | Feb 18 12:37:17 PM PST 24 |
| Finished | Feb 18 12:38:21 PM PST 24 |
| Peak memory | 146976 kb |
| Host | smart-07f7bfab-8fed-4d44-8583-89b53dcb91e6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4000787876 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 499.prim_prince_test.4000787876 |
| Directory | /workspace/499.prim_prince_test/latest |
| Test location | /workspace/coverage/default/5.prim_prince_test.4279581317 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 3216946508 ps |
| CPU time | 52.92 seconds |
| Started | Feb 18 12:37:06 PM PST 24 |
| Finished | Feb 18 12:38:11 PM PST 24 |
| Peak memory | 145196 kb |
| Host | smart-658b5cf6-c750-4ef5-a79a-02e8293bf208 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4279581317 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_prince_test.4279581317 |
| Directory | /workspace/5.prim_prince_test/latest |
| Test location | /workspace/coverage/default/50.prim_prince_test.2443970592 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 2696820475 ps |
| CPU time | 45.51 seconds |
| Started | Feb 18 12:36:13 PM PST 24 |
| Finished | Feb 18 12:37:16 PM PST 24 |
| Peak memory | 146968 kb |
| Host | smart-3d53f11d-81c6-48d3-8377-d183cc204ed6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2443970592 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 50.prim_prince_test.2443970592 |
| Directory | /workspace/50.prim_prince_test/latest |
| Test location | /workspace/coverage/default/51.prim_prince_test.3918577087 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 1120036994 ps |
| CPU time | 18.36 seconds |
| Started | Feb 18 12:36:00 PM PST 24 |
| Finished | Feb 18 12:36:25 PM PST 24 |
| Peak memory | 146840 kb |
| Host | smart-5970a177-2e8b-4e41-bcf3-af84ba67fa44 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3918577087 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 51.prim_prince_test.3918577087 |
| Directory | /workspace/51.prim_prince_test/latest |
| Test location | /workspace/coverage/default/52.prim_prince_test.3456403353 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 1589039007 ps |
| CPU time | 27.23 seconds |
| Started | Feb 18 12:36:01 PM PST 24 |
| Finished | Feb 18 12:36:38 PM PST 24 |
| Peak memory | 146832 kb |
| Host | smart-9b868b60-50b9-4f15-9969-906f069142e5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3456403353 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 52.prim_prince_test.3456403353 |
| Directory | /workspace/52.prim_prince_test/latest |
| Test location | /workspace/coverage/default/53.prim_prince_test.829680290 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 1662527688 ps |
| CPU time | 27.4 seconds |
| Started | Feb 18 12:36:00 PM PST 24 |
| Finished | Feb 18 12:36:36 PM PST 24 |
| Peak memory | 146864 kb |
| Host | smart-152d8d61-dd21-4f21-8cc1-018a05564c7e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=829680290 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 53.prim_prince_test.829680290 |
| Directory | /workspace/53.prim_prince_test/latest |
| Test location | /workspace/coverage/default/54.prim_prince_test.1910664395 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 3007156901 ps |
| CPU time | 49.07 seconds |
| Started | Feb 18 12:36:00 PM PST 24 |
| Finished | Feb 18 12:37:02 PM PST 24 |
| Peak memory | 146952 kb |
| Host | smart-4c35ce78-5ebb-4dc0-aeab-d225c37a1dd5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1910664395 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 54.prim_prince_test.1910664395 |
| Directory | /workspace/54.prim_prince_test/latest |
| Test location | /workspace/coverage/default/55.prim_prince_test.95159080 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 3413937250 ps |
| CPU time | 58.25 seconds |
| Started | Feb 18 12:36:08 PM PST 24 |
| Finished | Feb 18 12:37:23 PM PST 24 |
| Peak memory | 146988 kb |
| Host | smart-8cd2b6c4-f1bf-478e-a190-f24504e0aec0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=95159080 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 55.prim_prince_test.95159080 |
| Directory | /workspace/55.prim_prince_test/latest |
| Test location | /workspace/coverage/default/56.prim_prince_test.290464029 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 3475042400 ps |
| CPU time | 56.26 seconds |
| Started | Feb 18 12:36:13 PM PST 24 |
| Finished | Feb 18 12:37:26 PM PST 24 |
| Peak memory | 146924 kb |
| Host | smart-0b933870-7f1b-49c3-bc2d-4e8265a8327c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=290464029 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 56.prim_prince_test.290464029 |
| Directory | /workspace/56.prim_prince_test/latest |
| Test location | /workspace/coverage/default/57.prim_prince_test.4292082600 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 1805481737 ps |
| CPU time | 30.27 seconds |
| Started | Feb 18 12:36:14 PM PST 24 |
| Finished | Feb 18 12:36:57 PM PST 24 |
| Peak memory | 146780 kb |
| Host | smart-c73d1e8f-9740-4aba-aa27-5fcae9a33406 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4292082600 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 57.prim_prince_test.4292082600 |
| Directory | /workspace/57.prim_prince_test/latest |
| Test location | /workspace/coverage/default/58.prim_prince_test.4066466263 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 2957739734 ps |
| CPU time | 49.6 seconds |
| Started | Feb 18 12:36:04 PM PST 24 |
| Finished | Feb 18 12:37:07 PM PST 24 |
| Peak memory | 146900 kb |
| Host | smart-1f49ac69-1d0f-4acc-86ce-6386b7badae6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4066466263 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 58.prim_prince_test.4066466263 |
| Directory | /workspace/58.prim_prince_test/latest |
| Test location | /workspace/coverage/default/59.prim_prince_test.2194804883 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 773053428 ps |
| CPU time | 13.15 seconds |
| Started | Feb 18 12:36:00 PM PST 24 |
| Finished | Feb 18 12:36:20 PM PST 24 |
| Peak memory | 146868 kb |
| Host | smart-8d16bfe3-3f24-4c15-909e-7bb950c2493f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2194804883 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 59.prim_prince_test.2194804883 |
| Directory | /workspace/59.prim_prince_test/latest |
| Test location | /workspace/coverage/default/6.prim_prince_test.4198469509 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 2226814074 ps |
| CPU time | 35.64 seconds |
| Started | Feb 18 12:37:24 PM PST 24 |
| Finished | Feb 18 12:38:07 PM PST 24 |
| Peak memory | 146336 kb |
| Host | smart-8ccd9b77-680a-4a4b-844b-b0c8f5ea3373 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4198469509 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_prince_test.4198469509 |
| Directory | /workspace/6.prim_prince_test/latest |
| Test location | /workspace/coverage/default/60.prim_prince_test.3976307068 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 2472406036 ps |
| CPU time | 42.12 seconds |
| Started | Feb 18 12:36:00 PM PST 24 |
| Finished | Feb 18 12:36:55 PM PST 24 |
| Peak memory | 146952 kb |
| Host | smart-c4b601fe-a9b5-4fb0-a8c1-e2626b6cae6b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3976307068 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 60.prim_prince_test.3976307068 |
| Directory | /workspace/60.prim_prince_test/latest |
| Test location | /workspace/coverage/default/61.prim_prince_test.3441452495 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 2310378447 ps |
| CPU time | 38.09 seconds |
| Started | Feb 18 12:35:59 PM PST 24 |
| Finished | Feb 18 12:36:48 PM PST 24 |
| Peak memory | 146952 kb |
| Host | smart-b583e457-e779-474d-98ca-af113e489c67 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3441452495 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 61.prim_prince_test.3441452495 |
| Directory | /workspace/61.prim_prince_test/latest |
| Test location | /workspace/coverage/default/62.prim_prince_test.2113707954 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 2958536098 ps |
| CPU time | 50.69 seconds |
| Started | Feb 18 12:36:04 PM PST 24 |
| Finished | Feb 18 12:37:09 PM PST 24 |
| Peak memory | 146964 kb |
| Host | smart-927af60a-5d48-4991-8d3c-b96df2678eac |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2113707954 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 62.prim_prince_test.2113707954 |
| Directory | /workspace/62.prim_prince_test/latest |
| Test location | /workspace/coverage/default/63.prim_prince_test.2841909449 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 3507657152 ps |
| CPU time | 57.37 seconds |
| Started | Feb 18 12:36:01 PM PST 24 |
| Finished | Feb 18 12:37:14 PM PST 24 |
| Peak memory | 146948 kb |
| Host | smart-8bcc6ae1-6770-493d-a8cd-c80bb294133f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2841909449 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 63.prim_prince_test.2841909449 |
| Directory | /workspace/63.prim_prince_test/latest |
| Test location | /workspace/coverage/default/64.prim_prince_test.3346309166 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 1299364897 ps |
| CPU time | 21.14 seconds |
| Started | Feb 18 12:35:58 PM PST 24 |
| Finished | Feb 18 12:36:26 PM PST 24 |
| Peak memory | 146864 kb |
| Host | smart-e22a2e81-5214-47aa-8a48-7eab6ee2bed3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3346309166 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 64.prim_prince_test.3346309166 |
| Directory | /workspace/64.prim_prince_test/latest |
| Test location | /workspace/coverage/default/65.prim_prince_test.618597519 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 2051930869 ps |
| CPU time | 35 seconds |
| Started | Feb 18 12:35:57 PM PST 24 |
| Finished | Feb 18 12:36:44 PM PST 24 |
| Peak memory | 146868 kb |
| Host | smart-55024054-5143-44c3-89e5-7ae9c1be9625 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=618597519 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 65.prim_prince_test.618597519 |
| Directory | /workspace/65.prim_prince_test/latest |
| Test location | /workspace/coverage/default/66.prim_prince_test.3800388768 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 1815522884 ps |
| CPU time | 30.39 seconds |
| Started | Feb 18 12:36:10 PM PST 24 |
| Finished | Feb 18 12:36:51 PM PST 24 |
| Peak memory | 146780 kb |
| Host | smart-0f9e601c-92fa-42d4-8ba1-57c5822f07f4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3800388768 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 66.prim_prince_test.3800388768 |
| Directory | /workspace/66.prim_prince_test/latest |
| Test location | /workspace/coverage/default/67.prim_prince_test.1213062363 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 822128270 ps |
| CPU time | 13.2 seconds |
| Started | Feb 18 12:36:02 PM PST 24 |
| Finished | Feb 18 12:36:20 PM PST 24 |
| Peak memory | 146928 kb |
| Host | smart-1ba23143-102f-4860-8517-8c626c21b641 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1213062363 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 67.prim_prince_test.1213062363 |
| Directory | /workspace/67.prim_prince_test/latest |
| Test location | /workspace/coverage/default/68.prim_prince_test.2038982592 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 1788990228 ps |
| CPU time | 28.98 seconds |
| Started | Feb 18 12:36:08 PM PST 24 |
| Finished | Feb 18 12:36:43 PM PST 24 |
| Peak memory | 146780 kb |
| Host | smart-821cddee-f56c-4927-9c25-04072916abc8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2038982592 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 68.prim_prince_test.2038982592 |
| Directory | /workspace/68.prim_prince_test/latest |
| Test location | /workspace/coverage/default/69.prim_prince_test.1352858458 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 1214864377 ps |
| CPU time | 20.45 seconds |
| Started | Feb 18 12:36:00 PM PST 24 |
| Finished | Feb 18 12:36:27 PM PST 24 |
| Peak memory | 146844 kb |
| Host | smart-ec189b64-604f-4d1e-9cc7-d9577ee191e0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1352858458 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 69.prim_prince_test.1352858458 |
| Directory | /workspace/69.prim_prince_test/latest |
| Test location | /workspace/coverage/default/7.prim_prince_test.1423945509 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 1357186858 ps |
| CPU time | 22.38 seconds |
| Started | Feb 18 12:35:53 PM PST 24 |
| Finished | Feb 18 12:36:22 PM PST 24 |
| Peak memory | 146868 kb |
| Host | smart-c7cf0e80-bb89-402c-81d8-23853a992f9d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1423945509 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_prince_test.1423945509 |
| Directory | /workspace/7.prim_prince_test/latest |
| Test location | /workspace/coverage/default/70.prim_prince_test.778536617 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 877134950 ps |
| CPU time | 14.95 seconds |
| Started | Feb 18 12:36:12 PM PST 24 |
| Finished | Feb 18 12:36:35 PM PST 24 |
| Peak memory | 146872 kb |
| Host | smart-2a9bcbe6-c727-43ae-84ed-2ebee6e5f2db |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=778536617 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 70.prim_prince_test.778536617 |
| Directory | /workspace/70.prim_prince_test/latest |
| Test location | /workspace/coverage/default/71.prim_prince_test.1153030698 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 3219822040 ps |
| CPU time | 54.93 seconds |
| Started | Feb 18 12:36:04 PM PST 24 |
| Finished | Feb 18 12:37:14 PM PST 24 |
| Peak memory | 146968 kb |
| Host | smart-c770c3ff-18db-403a-a127-78444da2d0c0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1153030698 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 71.prim_prince_test.1153030698 |
| Directory | /workspace/71.prim_prince_test/latest |
| Test location | /workspace/coverage/default/72.prim_prince_test.993249933 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 2618057072 ps |
| CPU time | 45.12 seconds |
| Started | Feb 18 12:36:08 PM PST 24 |
| Finished | Feb 18 12:37:06 PM PST 24 |
| Peak memory | 146988 kb |
| Host | smart-1f126f89-92fd-44ac-826a-88988b507367 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=993249933 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 72.prim_prince_test.993249933 |
| Directory | /workspace/72.prim_prince_test/latest |
| Test location | /workspace/coverage/default/73.prim_prince_test.756221413 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 2397634785 ps |
| CPU time | 40.03 seconds |
| Started | Feb 18 12:36:08 PM PST 24 |
| Finished | Feb 18 12:36:58 PM PST 24 |
| Peak memory | 146924 kb |
| Host | smart-434c56a4-d9e9-430d-b259-d656b4379c78 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=756221413 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 73.prim_prince_test.756221413 |
| Directory | /workspace/73.prim_prince_test/latest |
| Test location | /workspace/coverage/default/74.prim_prince_test.4272278318 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 770906901 ps |
| CPU time | 12.85 seconds |
| Started | Feb 18 12:35:59 PM PST 24 |
| Finished | Feb 18 12:36:17 PM PST 24 |
| Peak memory | 146844 kb |
| Host | smart-6da80970-e15b-433b-a547-53ad3e8addc7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4272278318 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 74.prim_prince_test.4272278318 |
| Directory | /workspace/74.prim_prince_test/latest |
| Test location | /workspace/coverage/default/75.prim_prince_test.1981748893 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 3593106918 ps |
| CPU time | 59.13 seconds |
| Started | Feb 18 12:35:56 PM PST 24 |
| Finished | Feb 18 12:37:10 PM PST 24 |
| Peak memory | 146952 kb |
| Host | smart-fecb7ec4-33dd-4331-bbc3-0163134d40ad |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1981748893 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 75.prim_prince_test.1981748893 |
| Directory | /workspace/75.prim_prince_test/latest |
| Test location | /workspace/coverage/default/76.prim_prince_test.3178493339 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 1940259135 ps |
| CPU time | 31.68 seconds |
| Started | Feb 18 12:36:13 PM PST 24 |
| Finished | Feb 18 12:36:57 PM PST 24 |
| Peak memory | 146780 kb |
| Host | smart-cb0da869-4bfa-4ad0-8cf9-b8fb42960c6e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3178493339 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 76.prim_prince_test.3178493339 |
| Directory | /workspace/76.prim_prince_test/latest |
| Test location | /workspace/coverage/default/77.prim_prince_test.121701997 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 1928802168 ps |
| CPU time | 32.66 seconds |
| Started | Feb 18 12:35:58 PM PST 24 |
| Finished | Feb 18 12:36:41 PM PST 24 |
| Peak memory | 146804 kb |
| Host | smart-058a1cb5-71c8-418d-b3c9-5410a538725f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=121701997 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 77.prim_prince_test.121701997 |
| Directory | /workspace/77.prim_prince_test/latest |
| Test location | /workspace/coverage/default/78.prim_prince_test.3349936591 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 1498423418 ps |
| CPU time | 25.59 seconds |
| Started | Feb 18 12:36:06 PM PST 24 |
| Finished | Feb 18 12:36:38 PM PST 24 |
| Peak memory | 146848 kb |
| Host | smart-fc09efbf-fc55-48a9-9c74-1db1a9f2b7ee |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3349936591 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 78.prim_prince_test.3349936591 |
| Directory | /workspace/78.prim_prince_test/latest |
| Test location | /workspace/coverage/default/79.prim_prince_test.750344749 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 1685740394 ps |
| CPU time | 29.47 seconds |
| Started | Feb 18 12:35:59 PM PST 24 |
| Finished | Feb 18 12:36:38 PM PST 24 |
| Peak memory | 146964 kb |
| Host | smart-a90bbe09-01df-451d-b71d-2547d46f919b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=750344749 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 79.prim_prince_test.750344749 |
| Directory | /workspace/79.prim_prince_test/latest |
| Test location | /workspace/coverage/default/8.prim_prince_test.4122945863 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 768397292 ps |
| CPU time | 12.16 seconds |
| Started | Feb 18 12:37:14 PM PST 24 |
| Finished | Feb 18 12:37:30 PM PST 24 |
| Peak memory | 145756 kb |
| Host | smart-44952d54-6a32-4d68-9a0c-c3095ff83726 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4122945863 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_prince_test.4122945863 |
| Directory | /workspace/8.prim_prince_test/latest |
| Test location | /workspace/coverage/default/80.prim_prince_test.4228933278 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 2794790827 ps |
| CPU time | 47 seconds |
| Started | Feb 18 12:36:15 PM PST 24 |
| Finished | Feb 18 12:37:20 PM PST 24 |
| Peak memory | 146968 kb |
| Host | smart-a0df64b6-9d6e-4dc4-bbab-cf161b2e2158 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4228933278 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 80.prim_prince_test.4228933278 |
| Directory | /workspace/80.prim_prince_test/latest |
| Test location | /workspace/coverage/default/81.prim_prince_test.2376580399 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 3242203929 ps |
| CPU time | 53.75 seconds |
| Started | Feb 18 12:36:11 PM PST 24 |
| Finished | Feb 18 12:37:21 PM PST 24 |
| Peak memory | 147028 kb |
| Host | smart-a811a590-6d34-426e-8bdb-f196ec71973e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2376580399 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 81.prim_prince_test.2376580399 |
| Directory | /workspace/81.prim_prince_test/latest |
| Test location | /workspace/coverage/default/82.prim_prince_test.2875970260 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 1864368284 ps |
| CPU time | 31.68 seconds |
| Started | Feb 18 12:36:05 PM PST 24 |
| Finished | Feb 18 12:36:46 PM PST 24 |
| Peak memory | 146836 kb |
| Host | smart-9340f236-ebe9-4b9e-a5c8-c0d161845de9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2875970260 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 82.prim_prince_test.2875970260 |
| Directory | /workspace/82.prim_prince_test/latest |
| Test location | /workspace/coverage/default/83.prim_prince_test.1091471910 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 3383832870 ps |
| CPU time | 56.68 seconds |
| Started | Feb 18 12:36:00 PM PST 24 |
| Finished | Feb 18 12:37:12 PM PST 24 |
| Peak memory | 146900 kb |
| Host | smart-327b9073-ec90-4449-887b-af0c08a0d19b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1091471910 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 83.prim_prince_test.1091471910 |
| Directory | /workspace/83.prim_prince_test/latest |
| Test location | /workspace/coverage/default/84.prim_prince_test.2560306648 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 1343781983 ps |
| CPU time | 23.77 seconds |
| Started | Feb 18 12:36:20 PM PST 24 |
| Finished | Feb 18 12:36:56 PM PST 24 |
| Peak memory | 146936 kb |
| Host | smart-6c6b965e-1f77-4f24-8a75-b3041a785e4c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2560306648 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 84.prim_prince_test.2560306648 |
| Directory | /workspace/84.prim_prince_test/latest |
| Test location | /workspace/coverage/default/85.prim_prince_test.145714384 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 2726489590 ps |
| CPU time | 45.82 seconds |
| Started | Feb 18 12:36:18 PM PST 24 |
| Finished | Feb 18 12:37:21 PM PST 24 |
| Peak memory | 146988 kb |
| Host | smart-49259baa-2f9d-41f8-a1c9-258df12e0e36 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=145714384 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 85.prim_prince_test.145714384 |
| Directory | /workspace/85.prim_prince_test/latest |
| Test location | /workspace/coverage/default/86.prim_prince_test.3949885576 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 1965120237 ps |
| CPU time | 33.52 seconds |
| Started | Feb 18 12:36:22 PM PST 24 |
| Finished | Feb 18 12:37:09 PM PST 24 |
| Peak memory | 146860 kb |
| Host | smart-e916a839-1c94-40fa-bff4-4c9a86311e84 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3949885576 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 86.prim_prince_test.3949885576 |
| Directory | /workspace/86.prim_prince_test/latest |
| Test location | /workspace/coverage/default/87.prim_prince_test.4109874162 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 2652494872 ps |
| CPU time | 44.63 seconds |
| Started | Feb 18 12:36:05 PM PST 24 |
| Finished | Feb 18 12:37:02 PM PST 24 |
| Peak memory | 146900 kb |
| Host | smart-be55f781-a060-42af-8ee3-94d0faab7b3b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4109874162 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 87.prim_prince_test.4109874162 |
| Directory | /workspace/87.prim_prince_test/latest |
| Test location | /workspace/coverage/default/88.prim_prince_test.571544794 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 1857129469 ps |
| CPU time | 30.76 seconds |
| Started | Feb 18 12:36:00 PM PST 24 |
| Finished | Feb 18 12:36:40 PM PST 24 |
| Peak memory | 146952 kb |
| Host | smart-c30508a9-7c3e-440b-b562-9dd0e784cbd7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=571544794 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 88.prim_prince_test.571544794 |
| Directory | /workspace/88.prim_prince_test/latest |
| Test location | /workspace/coverage/default/89.prim_prince_test.1272728008 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 894600175 ps |
| CPU time | 14.61 seconds |
| Started | Feb 18 12:36:13 PM PST 24 |
| Finished | Feb 18 12:36:37 PM PST 24 |
| Peak memory | 146868 kb |
| Host | smart-8dbee56f-8527-400b-b3fe-37e0ee70afb7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1272728008 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 89.prim_prince_test.1272728008 |
| Directory | /workspace/89.prim_prince_test/latest |
| Test location | /workspace/coverage/default/9.prim_prince_test.2972846505 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 2573544997 ps |
| CPU time | 41.43 seconds |
| Started | Feb 18 12:37:23 PM PST 24 |
| Finished | Feb 18 12:38:13 PM PST 24 |
| Peak memory | 146336 kb |
| Host | smart-ba32bd3f-0b15-4cc7-920a-36a48fc5ff91 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2972846505 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_prince_test.2972846505 |
| Directory | /workspace/9.prim_prince_test/latest |
| Test location | /workspace/coverage/default/90.prim_prince_test.1324887233 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 2543571809 ps |
| CPU time | 41.54 seconds |
| Started | Feb 18 12:36:02 PM PST 24 |
| Finished | Feb 18 12:36:55 PM PST 24 |
| Peak memory | 146976 kb |
| Host | smart-5fb4f385-290e-4490-8e4c-68b88c83798f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1324887233 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 90.prim_prince_test.1324887233 |
| Directory | /workspace/90.prim_prince_test/latest |
| Test location | /workspace/coverage/default/91.prim_prince_test.3941928274 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 1869107570 ps |
| CPU time | 32.1 seconds |
| Started | Feb 18 12:36:25 PM PST 24 |
| Finished | Feb 18 12:37:10 PM PST 24 |
| Peak memory | 146780 kb |
| Host | smart-0ad72852-e0e7-432e-a01d-3499b8eae40d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3941928274 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 91.prim_prince_test.3941928274 |
| Directory | /workspace/91.prim_prince_test/latest |
| Test location | /workspace/coverage/default/92.prim_prince_test.487264532 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 1250996564 ps |
| CPU time | 20.5 seconds |
| Started | Feb 18 12:36:11 PM PST 24 |
| Finished | Feb 18 12:36:40 PM PST 24 |
| Peak memory | 146864 kb |
| Host | smart-bbfdd0b6-79b8-4c91-b447-11c87f5690e4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=487264532 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 92.prim_prince_test.487264532 |
| Directory | /workspace/92.prim_prince_test/latest |
| Test location | /workspace/coverage/default/93.prim_prince_test.3032723137 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 3098180663 ps |
| CPU time | 50.36 seconds |
| Started | Feb 18 12:36:05 PM PST 24 |
| Finished | Feb 18 12:37:06 PM PST 24 |
| Peak memory | 146960 kb |
| Host | smart-73ce6bd8-8d6c-4d4f-bcc5-bcdda6d5d0ea |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3032723137 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 93.prim_prince_test.3032723137 |
| Directory | /workspace/93.prim_prince_test/latest |
| Test location | /workspace/coverage/default/94.prim_prince_test.1080129015 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 2931804086 ps |
| CPU time | 48.29 seconds |
| Started | Feb 18 12:36:11 PM PST 24 |
| Finished | Feb 18 12:37:14 PM PST 24 |
| Peak memory | 147028 kb |
| Host | smart-c53e3dbe-cb12-4410-8323-6810b74ae43d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1080129015 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 94.prim_prince_test.1080129015 |
| Directory | /workspace/94.prim_prince_test/latest |
| Test location | /workspace/coverage/default/95.prim_prince_test.1344449827 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 2883490585 ps |
| CPU time | 49.48 seconds |
| Started | Feb 18 12:36:15 PM PST 24 |
| Finished | Feb 18 12:37:23 PM PST 24 |
| Peak memory | 146980 kb |
| Host | smart-7b8b47b7-0c11-489a-827e-207092357f00 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1344449827 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 95.prim_prince_test.1344449827 |
| Directory | /workspace/95.prim_prince_test/latest |
| Test location | /workspace/coverage/default/96.prim_prince_test.1401814982 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 2823839895 ps |
| CPU time | 46.84 seconds |
| Started | Feb 18 12:36:05 PM PST 24 |
| Finished | Feb 18 12:37:03 PM PST 24 |
| Peak memory | 147044 kb |
| Host | smart-1e35631e-6fef-48f5-bb7e-92c1c1ee0ab0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1401814982 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 96.prim_prince_test.1401814982 |
| Directory | /workspace/96.prim_prince_test/latest |
| Test location | /workspace/coverage/default/97.prim_prince_test.304389622 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 3143551232 ps |
| CPU time | 51.64 seconds |
| Started | Feb 18 12:36:26 PM PST 24 |
| Finished | Feb 18 12:37:35 PM PST 24 |
| Peak memory | 146984 kb |
| Host | smart-5eb30942-f0c1-48e8-aa54-dd712815a55b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=304389622 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 97.prim_prince_test.304389622 |
| Directory | /workspace/97.prim_prince_test/latest |
| Test location | /workspace/coverage/default/98.prim_prince_test.3017492560 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 1609354877 ps |
| CPU time | 27.04 seconds |
| Started | Feb 18 12:36:15 PM PST 24 |
| Finished | Feb 18 12:36:54 PM PST 24 |
| Peak memory | 146848 kb |
| Host | smart-b93ba44f-4225-4624-a92c-90185691782a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3017492560 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 98.prim_prince_test.3017492560 |
| Directory | /workspace/98.prim_prince_test/latest |
| Test location | /workspace/coverage/default/99.prim_prince_test.2136682491 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 3708709187 ps |
| CPU time | 61.88 seconds |
| Started | Feb 18 12:36:07 PM PST 24 |
| Finished | Feb 18 12:37:24 PM PST 24 |
| Peak memory | 146896 kb |
| Host | smart-1e781f04-872b-489e-be44-67e1fff4b61b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2136682491 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 99.prim_prince_test.2136682491 |
| Directory | /workspace/99.prim_prince_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |