Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00 100.00


Total test records in report: 500
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html
T251 /workspace/coverage/default/487.prim_prince_test.4143050547 Jun 27 06:12:18 PM PDT 24 Jun 27 06:12:57 PM PDT 24 1826075064 ps
T252 /workspace/coverage/default/127.prim_prince_test.1114140239 Jun 27 06:10:59 PM PDT 24 Jun 27 06:11:24 PM PDT 24 1058636342 ps
T253 /workspace/coverage/default/399.prim_prince_test.4012172370 Jun 27 06:11:58 PM PDT 24 Jun 27 06:12:52 PM PDT 24 2489051995 ps
T254 /workspace/coverage/default/289.prim_prince_test.945857709 Jun 27 06:11:25 PM PDT 24 Jun 27 06:12:22 PM PDT 24 2850724763 ps
T255 /workspace/coverage/default/367.prim_prince_test.3483358503 Jun 27 06:11:43 PM PDT 24 Jun 27 06:12:23 PM PDT 24 1748024853 ps
T256 /workspace/coverage/default/175.prim_prince_test.1118096539 Jun 27 06:10:56 PM PDT 24 Jun 27 06:11:25 PM PDT 24 1281401502 ps
T257 /workspace/coverage/default/479.prim_prince_test.1566337644 Jun 27 06:12:17 PM PDT 24 Jun 27 06:13:12 PM PDT 24 2548685358 ps
T258 /workspace/coverage/default/146.prim_prince_test.2722975899 Jun 27 06:10:54 PM PDT 24 Jun 27 06:12:04 PM PDT 24 3343947066 ps
T259 /workspace/coverage/default/41.prim_prince_test.1153606914 Jun 27 06:10:15 PM PDT 24 Jun 27 06:11:05 PM PDT 24 2425544278 ps
T260 /workspace/coverage/default/387.prim_prince_test.499234737 Jun 27 06:11:58 PM PDT 24 Jun 27 06:13:16 PM PDT 24 3651962093 ps
T261 /workspace/coverage/default/69.prim_prince_test.3301968546 Jun 27 06:10:27 PM PDT 24 Jun 27 06:10:47 PM PDT 24 829220564 ps
T262 /workspace/coverage/default/115.prim_prince_test.3996466354 Jun 27 06:10:28 PM PDT 24 Jun 27 06:11:27 PM PDT 24 2760057061 ps
T263 /workspace/coverage/default/450.prim_prince_test.4030979655 Jun 27 06:12:17 PM PDT 24 Jun 27 06:13:27 PM PDT 24 3254822428 ps
T264 /workspace/coverage/default/3.prim_prince_test.1886375504 Jun 27 06:10:06 PM PDT 24 Jun 27 06:10:43 PM PDT 24 1833096069 ps
T265 /workspace/coverage/default/375.prim_prince_test.1933280916 Jun 27 06:12:00 PM PDT 24 Jun 27 06:12:42 PM PDT 24 1802373379 ps
T266 /workspace/coverage/default/173.prim_prince_test.1203461060 Jun 27 06:11:01 PM PDT 24 Jun 27 06:11:50 PM PDT 24 2363494893 ps
T267 /workspace/coverage/default/136.prim_prince_test.909462618 Jun 27 06:10:56 PM PDT 24 Jun 27 06:12:03 PM PDT 24 3168208358 ps
T268 /workspace/coverage/default/9.prim_prince_test.2342005480 Jun 27 06:10:06 PM PDT 24 Jun 27 06:11:21 PM PDT 24 3745162661 ps
T269 /workspace/coverage/default/381.prim_prince_test.1625243986 Jun 27 06:11:58 PM PDT 24 Jun 27 06:12:32 PM PDT 24 1569410967 ps
T270 /workspace/coverage/default/120.prim_prince_test.3816177032 Jun 27 06:10:30 PM PDT 24 Jun 27 06:11:17 PM PDT 24 2145973493 ps
T271 /workspace/coverage/default/65.prim_prince_test.2394045279 Jun 27 06:10:25 PM PDT 24 Jun 27 06:11:09 PM PDT 24 1965781504 ps
T272 /workspace/coverage/default/275.prim_prince_test.2745473532 Jun 27 06:11:13 PM PDT 24 Jun 27 06:12:08 PM PDT 24 2749360426 ps
T273 /workspace/coverage/default/204.prim_prince_test.306114800 Jun 27 06:10:57 PM PDT 24 Jun 27 06:11:54 PM PDT 24 2771529403 ps
T274 /workspace/coverage/default/208.prim_prince_test.4206540575 Jun 27 06:11:04 PM PDT 24 Jun 27 06:12:19 PM PDT 24 3588678782 ps
T275 /workspace/coverage/default/191.prim_prince_test.3574810097 Jun 27 06:11:01 PM PDT 24 Jun 27 06:11:43 PM PDT 24 1830270704 ps
T276 /workspace/coverage/default/319.prim_prince_test.1165990632 Jun 27 06:11:43 PM PDT 24 Jun 27 06:12:12 PM PDT 24 1223863940 ps
T277 /workspace/coverage/default/83.prim_prince_test.3202082793 Jun 27 06:10:27 PM PDT 24 Jun 27 06:11:44 PM PDT 24 3623465445 ps
T278 /workspace/coverage/default/86.prim_prince_test.774503959 Jun 27 06:10:28 PM PDT 24 Jun 27 06:11:11 PM PDT 24 1955056122 ps
T279 /workspace/coverage/default/110.prim_prince_test.2059741879 Jun 27 06:10:28 PM PDT 24 Jun 27 06:10:49 PM PDT 24 880345165 ps
T280 /workspace/coverage/default/324.prim_prince_test.4224789374 Jun 27 06:11:43 PM PDT 24 Jun 27 06:12:38 PM PDT 24 2579605523 ps
T281 /workspace/coverage/default/286.prim_prince_test.2323206700 Jun 27 06:11:29 PM PDT 24 Jun 27 06:12:03 PM PDT 24 1568997263 ps
T282 /workspace/coverage/default/431.prim_prince_test.3456004786 Jun 27 06:12:16 PM PDT 24 Jun 27 06:13:11 PM PDT 24 2555410314 ps
T283 /workspace/coverage/default/345.prim_prince_test.2253156023 Jun 27 06:11:46 PM PDT 24 Jun 27 06:12:24 PM PDT 24 1740669196 ps
T284 /workspace/coverage/default/489.prim_prince_test.3931193918 Jun 27 06:12:18 PM PDT 24 Jun 27 06:13:14 PM PDT 24 2446384061 ps
T285 /workspace/coverage/default/212.prim_prince_test.2442489484 Jun 27 06:11:02 PM PDT 24 Jun 27 06:12:10 PM PDT 24 3104622364 ps
T286 /workspace/coverage/default/426.prim_prince_test.3304616509 Jun 27 06:12:15 PM PDT 24 Jun 27 06:13:02 PM PDT 24 2223210718 ps
T287 /workspace/coverage/default/58.prim_prince_test.697896218 Jun 27 06:10:27 PM PDT 24 Jun 27 06:11:21 PM PDT 24 2495175326 ps
T288 /workspace/coverage/default/88.prim_prince_test.3807052910 Jun 27 06:10:28 PM PDT 24 Jun 27 06:11:16 PM PDT 24 2230254726 ps
T289 /workspace/coverage/default/309.prim_prince_test.1181307967 Jun 27 06:11:27 PM PDT 24 Jun 27 06:12:01 PM PDT 24 1552529655 ps
T290 /workspace/coverage/default/57.prim_prince_test.3685503677 Jun 27 06:10:28 PM PDT 24 Jun 27 06:11:40 PM PDT 24 3403638818 ps
T291 /workspace/coverage/default/484.prim_prince_test.3679995332 Jun 27 06:12:17 PM PDT 24 Jun 27 06:12:47 PM PDT 24 1336547010 ps
T292 /workspace/coverage/default/94.prim_prince_test.735910188 Jun 27 06:10:28 PM PDT 24 Jun 27 06:10:55 PM PDT 24 1134821788 ps
T293 /workspace/coverage/default/16.prim_prince_test.4171469727 Jun 27 06:10:11 PM PDT 24 Jun 27 06:10:56 PM PDT 24 2153641072 ps
T294 /workspace/coverage/default/161.prim_prince_test.546466387 Jun 27 06:10:58 PM PDT 24 Jun 27 06:11:27 PM PDT 24 1284726469 ps
T295 /workspace/coverage/default/414.prim_prince_test.2087899699 Jun 27 06:12:00 PM PDT 24 Jun 27 06:12:27 PM PDT 24 1096883728 ps
T296 /workspace/coverage/default/273.prim_prince_test.1490143343 Jun 27 06:11:19 PM PDT 24 Jun 27 06:11:45 PM PDT 24 1158087219 ps
T297 /workspace/coverage/default/436.prim_prince_test.3603737458 Jun 27 06:12:15 PM PDT 24 Jun 27 06:13:15 PM PDT 24 2858857913 ps
T298 /workspace/coverage/default/117.prim_prince_test.3405755289 Jun 27 06:10:28 PM PDT 24 Jun 27 06:11:34 PM PDT 24 3114982631 ps
T299 /workspace/coverage/default/285.prim_prince_test.230562092 Jun 27 06:11:25 PM PDT 24 Jun 27 06:12:05 PM PDT 24 1930740176 ps
T300 /workspace/coverage/default/434.prim_prince_test.2905574480 Jun 27 06:12:21 PM PDT 24 Jun 27 06:13:19 PM PDT 24 2738330034 ps
T301 /workspace/coverage/default/320.prim_prince_test.119631721 Jun 27 06:11:43 PM PDT 24 Jun 27 06:12:12 PM PDT 24 1242418280 ps
T302 /workspace/coverage/default/148.prim_prince_test.4276885446 Jun 27 06:10:55 PM PDT 24 Jun 27 06:11:47 PM PDT 24 2503909460 ps
T303 /workspace/coverage/default/54.prim_prince_test.2029846084 Jun 27 06:10:29 PM PDT 24 Jun 27 06:11:20 PM PDT 24 2278292893 ps
T304 /workspace/coverage/default/180.prim_prince_test.1282117435 Jun 27 06:11:00 PM PDT 24 Jun 27 06:12:14 PM PDT 24 3493228577 ps
T305 /workspace/coverage/default/339.prim_prince_test.3859640026 Jun 27 06:11:42 PM PDT 24 Jun 27 06:12:40 PM PDT 24 2741878315 ps
T306 /workspace/coverage/default/63.prim_prince_test.2983131261 Jun 27 06:10:27 PM PDT 24 Jun 27 06:11:18 PM PDT 24 2315754887 ps
T307 /workspace/coverage/default/402.prim_prince_test.2991900021 Jun 27 06:11:58 PM PDT 24 Jun 27 06:12:36 PM PDT 24 1731428873 ps
T308 /workspace/coverage/default/40.prim_prince_test.1482777074 Jun 27 06:10:12 PM PDT 24 Jun 27 06:11:20 PM PDT 24 3330274700 ps
T309 /workspace/coverage/default/337.prim_prince_test.1249283174 Jun 27 06:11:45 PM PDT 24 Jun 27 06:12:12 PM PDT 24 1161589492 ps
T310 /workspace/coverage/default/5.prim_prince_test.3021941073 Jun 27 06:10:05 PM PDT 24 Jun 27 06:11:07 PM PDT 24 3024936466 ps
T311 /workspace/coverage/default/190.prim_prince_test.4289699298 Jun 27 06:11:00 PM PDT 24 Jun 27 06:11:29 PM PDT 24 1255297754 ps
T312 /workspace/coverage/default/445.prim_prince_test.1668455412 Jun 27 06:12:19 PM PDT 24 Jun 27 06:13:27 PM PDT 24 3244455159 ps
T313 /workspace/coverage/default/26.prim_prince_test.1702262817 Jun 27 06:10:16 PM PDT 24 Jun 27 06:10:33 PM PDT 24 821523513 ps
T314 /workspace/coverage/default/248.prim_prince_test.3575901452 Jun 27 06:11:09 PM PDT 24 Jun 27 06:12:27 PM PDT 24 3699505798 ps
T315 /workspace/coverage/default/217.prim_prince_test.4264955681 Jun 27 06:10:59 PM PDT 24 Jun 27 06:11:29 PM PDT 24 1305507858 ps
T316 /workspace/coverage/default/294.prim_prince_test.2689459158 Jun 27 06:11:26 PM PDT 24 Jun 27 06:12:35 PM PDT 24 3309948172 ps
T317 /workspace/coverage/default/335.prim_prince_test.3281212859 Jun 27 06:11:43 PM PDT 24 Jun 27 06:12:03 PM PDT 24 768806027 ps
T318 /workspace/coverage/default/81.prim_prince_test.2128750782 Jun 27 06:10:27 PM PDT 24 Jun 27 06:11:48 PM PDT 24 3741780086 ps
T319 /workspace/coverage/default/15.prim_prince_test.2929020214 Jun 27 06:10:13 PM PDT 24 Jun 27 06:10:52 PM PDT 24 1819353420 ps
T320 /workspace/coverage/default/72.prim_prince_test.4244035745 Jun 27 06:10:28 PM PDT 24 Jun 27 06:11:39 PM PDT 24 3185234095 ps
T321 /workspace/coverage/default/288.prim_prince_test.632643752 Jun 27 06:11:28 PM PDT 24 Jun 27 06:12:25 PM PDT 24 2722364526 ps
T322 /workspace/coverage/default/358.prim_prince_test.3453880622 Jun 27 06:11:42 PM PDT 24 Jun 27 06:12:52 PM PDT 24 3210148254 ps
T323 /workspace/coverage/default/282.prim_prince_test.1020570373 Jun 27 06:11:19 PM PDT 24 Jun 27 06:12:03 PM PDT 24 2095437874 ps
T324 /workspace/coverage/default/471.prim_prince_test.2636297767 Jun 27 06:12:19 PM PDT 24 Jun 27 06:12:50 PM PDT 24 1455751772 ps
T325 /workspace/coverage/default/449.prim_prince_test.139237477 Jun 27 06:12:15 PM PDT 24 Jun 27 06:12:43 PM PDT 24 1295644425 ps
T326 /workspace/coverage/default/242.prim_prince_test.1020204782 Jun 27 06:11:09 PM PDT 24 Jun 27 06:11:48 PM PDT 24 1906654187 ps
T327 /workspace/coverage/default/106.prim_prince_test.1038686833 Jun 27 06:10:25 PM PDT 24 Jun 27 06:11:37 PM PDT 24 3427130363 ps
T328 /workspace/coverage/default/235.prim_prince_test.1603224330 Jun 27 06:11:00 PM PDT 24 Jun 27 06:12:16 PM PDT 24 3591070665 ps
T329 /workspace/coverage/default/333.prim_prince_test.103138525 Jun 27 06:11:44 PM PDT 24 Jun 27 06:12:51 PM PDT 24 3176775038 ps
T330 /workspace/coverage/default/121.prim_prince_test.1032215426 Jun 27 06:11:00 PM PDT 24 Jun 27 06:11:20 PM PDT 24 828906541 ps
T331 /workspace/coverage/default/56.prim_prince_test.3407741270 Jun 27 06:10:26 PM PDT 24 Jun 27 06:11:06 PM PDT 24 1916842481 ps
T332 /workspace/coverage/default/184.prim_prince_test.341333842 Jun 27 06:11:04 PM PDT 24 Jun 27 06:11:45 PM PDT 24 1978585498 ps
T333 /workspace/coverage/default/43.prim_prince_test.1241901375 Jun 27 06:10:10 PM PDT 24 Jun 27 06:11:12 PM PDT 24 2947244813 ps
T334 /workspace/coverage/default/22.prim_prince_test.2140628014 Jun 27 06:10:17 PM PDT 24 Jun 27 06:10:46 PM PDT 24 1393432620 ps
T335 /workspace/coverage/default/234.prim_prince_test.3623448945 Jun 27 06:11:00 PM PDT 24 Jun 27 06:11:19 PM PDT 24 843072481 ps
T336 /workspace/coverage/default/220.prim_prince_test.150067159 Jun 27 06:11:03 PM PDT 24 Jun 27 06:11:43 PM PDT 24 1782019142 ps
T337 /workspace/coverage/default/198.prim_prince_test.4126444997 Jun 27 06:11:04 PM PDT 24 Jun 27 06:11:50 PM PDT 24 2183418321 ps
T338 /workspace/coverage/default/38.prim_prince_test.2628661853 Jun 27 06:10:12 PM PDT 24 Jun 27 06:11:18 PM PDT 24 3104791007 ps
T339 /workspace/coverage/default/90.prim_prince_test.2648045550 Jun 27 06:10:26 PM PDT 24 Jun 27 06:11:21 PM PDT 24 2664411599 ps
T340 /workspace/coverage/default/386.prim_prince_test.3175125048 Jun 27 06:12:00 PM PDT 24 Jun 27 06:12:49 PM PDT 24 2178713853 ps
T341 /workspace/coverage/default/14.prim_prince_test.421498336 Jun 27 06:10:06 PM PDT 24 Jun 27 06:10:27 PM PDT 24 976188034 ps
T342 /workspace/coverage/default/140.prim_prince_test.429951571 Jun 27 06:10:56 PM PDT 24 Jun 27 06:11:49 PM PDT 24 2545738320 ps
T343 /workspace/coverage/default/295.prim_prince_test.3416398427 Jun 27 06:11:22 PM PDT 24 Jun 27 06:12:29 PM PDT 24 3697847755 ps
T344 /workspace/coverage/default/452.prim_prince_test.1809764693 Jun 27 06:12:19 PM PDT 24 Jun 27 06:13:29 PM PDT 24 3241282857 ps
T345 /workspace/coverage/default/415.prim_prince_test.3585626662 Jun 27 06:12:01 PM PDT 24 Jun 27 06:13:13 PM PDT 24 3392020344 ps
T346 /workspace/coverage/default/292.prim_prince_test.437961229 Jun 27 06:11:30 PM PDT 24 Jun 27 06:12:20 PM PDT 24 2486912550 ps
T347 /workspace/coverage/default/221.prim_prince_test.65469009 Jun 27 06:11:02 PM PDT 24 Jun 27 06:11:53 PM PDT 24 2319751742 ps
T348 /workspace/coverage/default/270.prim_prince_test.753352227 Jun 27 06:11:20 PM PDT 24 Jun 27 06:11:38 PM PDT 24 810443059 ps
T349 /workspace/coverage/default/401.prim_prince_test.629441980 Jun 27 06:12:00 PM PDT 24 Jun 27 06:12:51 PM PDT 24 2272951865 ps
T350 /workspace/coverage/default/27.prim_prince_test.303737037 Jun 27 06:10:12 PM PDT 24 Jun 27 06:10:34 PM PDT 24 1093605271 ps
T351 /workspace/coverage/default/162.prim_prince_test.23873812 Jun 27 06:10:55 PM PDT 24 Jun 27 06:11:29 PM PDT 24 1563375416 ps
T352 /workspace/coverage/default/193.prim_prince_test.1355385159 Jun 27 06:11:04 PM PDT 24 Jun 27 06:12:14 PM PDT 24 3419319319 ps
T353 /workspace/coverage/default/427.prim_prince_test.3870958813 Jun 27 06:12:17 PM PDT 24 Jun 27 06:13:34 PM PDT 24 3696544209 ps
T354 /workspace/coverage/default/52.prim_prince_test.1630333129 Jun 27 06:10:26 PM PDT 24 Jun 27 06:10:48 PM PDT 24 955611836 ps
T355 /workspace/coverage/default/376.prim_prince_test.3648633838 Jun 27 06:11:57 PM PDT 24 Jun 27 06:12:23 PM PDT 24 1200117324 ps
T356 /workspace/coverage/default/462.prim_prince_test.3509848105 Jun 27 06:12:20 PM PDT 24 Jun 27 06:13:15 PM PDT 24 2368869348 ps
T357 /workspace/coverage/default/252.prim_prince_test.825084706 Jun 27 06:11:17 PM PDT 24 Jun 27 06:12:09 PM PDT 24 2503249601 ps
T358 /workspace/coverage/default/300.prim_prince_test.4016209324 Jun 27 06:11:25 PM PDT 24 Jun 27 06:12:09 PM PDT 24 2069949389 ps
T359 /workspace/coverage/default/189.prim_prince_test.264435390 Jun 27 06:11:03 PM PDT 24 Jun 27 06:12:06 PM PDT 24 3157599127 ps
T360 /workspace/coverage/default/499.prim_prince_test.3492352102 Jun 27 06:12:34 PM PDT 24 Jun 27 06:13:08 PM PDT 24 1548605690 ps
T361 /workspace/coverage/default/281.prim_prince_test.1068478438 Jun 27 06:11:13 PM PDT 24 Jun 27 06:11:37 PM PDT 24 1129998587 ps
T362 /workspace/coverage/default/236.prim_prince_test.3472005310 Jun 27 06:11:09 PM PDT 24 Jun 27 06:11:58 PM PDT 24 2169495245 ps
T363 /workspace/coverage/default/329.prim_prince_test.370804369 Jun 27 06:11:41 PM PDT 24 Jun 27 06:12:06 PM PDT 24 1098912150 ps
T364 /workspace/coverage/default/453.prim_prince_test.4064479473 Jun 27 06:12:16 PM PDT 24 Jun 27 06:13:35 PM PDT 24 3744838486 ps
T365 /workspace/coverage/default/260.prim_prince_test.1026827856 Jun 27 06:11:18 PM PDT 24 Jun 27 06:12:30 PM PDT 24 3477379638 ps
T366 /workspace/coverage/default/347.prim_prince_test.587403683 Jun 27 06:11:44 PM PDT 24 Jun 27 06:12:57 PM PDT 24 3542308215 ps
T367 /workspace/coverage/default/439.prim_prince_test.2004685626 Jun 27 06:12:16 PM PDT 24 Jun 27 06:13:12 PM PDT 24 2651643700 ps
T368 /workspace/coverage/default/413.prim_prince_test.2373725238 Jun 27 06:12:04 PM PDT 24 Jun 27 06:12:46 PM PDT 24 1943192869 ps
T369 /workspace/coverage/default/1.prim_prince_test.20620904 Jun 27 06:10:05 PM PDT 24 Jun 27 06:10:44 PM PDT 24 1994798161 ps
T370 /workspace/coverage/default/34.prim_prince_test.2812512854 Jun 27 06:10:12 PM PDT 24 Jun 27 06:10:38 PM PDT 24 1233816477 ps
T371 /workspace/coverage/default/170.prim_prince_test.3299310589 Jun 27 06:10:59 PM PDT 24 Jun 27 06:12:03 PM PDT 24 3073481472 ps
T372 /workspace/coverage/default/370.prim_prince_test.2386928184 Jun 27 06:11:57 PM PDT 24 Jun 27 06:12:36 PM PDT 24 1887139624 ps
T373 /workspace/coverage/default/315.prim_prince_test.2218264527 Jun 27 06:11:41 PM PDT 24 Jun 27 06:12:12 PM PDT 24 1416606380 ps
T374 /workspace/coverage/default/433.prim_prince_test.4251383379 Jun 27 06:12:18 PM PDT 24 Jun 27 06:12:44 PM PDT 24 1120314283 ps
T375 /workspace/coverage/default/62.prim_prince_test.846810675 Jun 27 06:10:29 PM PDT 24 Jun 27 06:11:44 PM PDT 24 3578439495 ps
T376 /workspace/coverage/default/25.prim_prince_test.3891544588 Jun 27 06:10:16 PM PDT 24 Jun 27 06:11:20 PM PDT 24 3202136566 ps
T377 /workspace/coverage/default/139.prim_prince_test.3525838775 Jun 27 06:10:56 PM PDT 24 Jun 27 06:11:18 PM PDT 24 1009469490 ps
T378 /workspace/coverage/default/460.prim_prince_test.3013053130 Jun 27 06:12:17 PM PDT 24 Jun 27 06:13:37 PM PDT 24 3703574388 ps
T379 /workspace/coverage/default/157.prim_prince_test.2801631826 Jun 27 06:10:59 PM PDT 24 Jun 27 06:11:55 PM PDT 24 2586497593 ps
T380 /workspace/coverage/default/181.prim_prince_test.2125799890 Jun 27 06:10:58 PM PDT 24 Jun 27 06:11:34 PM PDT 24 1628627082 ps
T381 /workspace/coverage/default/250.prim_prince_test.3231596292 Jun 27 06:11:09 PM PDT 24 Jun 27 06:11:26 PM PDT 24 754725298 ps
T382 /workspace/coverage/default/20.prim_prince_test.2355243886 Jun 27 06:10:11 PM PDT 24 Jun 27 06:10:47 PM PDT 24 1616309459 ps
T383 /workspace/coverage/default/114.prim_prince_test.1882410739 Jun 27 06:10:28 PM PDT 24 Jun 27 06:10:55 PM PDT 24 1153415088 ps
T384 /workspace/coverage/default/353.prim_prince_test.554064911 Jun 27 06:11:43 PM PDT 24 Jun 27 06:12:58 PM PDT 24 3546032644 ps
T385 /workspace/coverage/default/174.prim_prince_test.1969453213 Jun 27 06:10:58 PM PDT 24 Jun 27 06:11:53 PM PDT 24 2592052793 ps
T386 /workspace/coverage/default/463.prim_prince_test.3485170088 Jun 27 06:12:17 PM PDT 24 Jun 27 06:13:19 PM PDT 24 2794717986 ps
T387 /workspace/coverage/default/366.prim_prince_test.1484541322 Jun 27 06:11:43 PM PDT 24 Jun 27 06:12:55 PM PDT 24 3306000323 ps
T388 /workspace/coverage/default/199.prim_prince_test.2181451241 Jun 27 06:11:01 PM PDT 24 Jun 27 06:12:02 PM PDT 24 2875439062 ps
T389 /workspace/coverage/default/480.prim_prince_test.203515142 Jun 27 06:12:20 PM PDT 24 Jun 27 06:13:16 PM PDT 24 2521770593 ps
T390 /workspace/coverage/default/45.prim_prince_test.4010768392 Jun 27 06:10:13 PM PDT 24 Jun 27 06:10:52 PM PDT 24 1852200450 ps
T391 /workspace/coverage/default/118.prim_prince_test.2585967995 Jun 27 06:10:29 PM PDT 24 Jun 27 06:11:02 PM PDT 24 1470983926 ps
T392 /workspace/coverage/default/322.prim_prince_test.622474832 Jun 27 06:11:42 PM PDT 24 Jun 27 06:12:36 PM PDT 24 2549916642 ps
T393 /workspace/coverage/default/363.prim_prince_test.44518017 Jun 27 06:11:43 PM PDT 24 Jun 27 06:12:44 PM PDT 24 2765645202 ps
T394 /workspace/coverage/default/85.prim_prince_test.2883852290 Jun 27 06:10:27 PM PDT 24 Jun 27 06:11:06 PM PDT 24 1826172602 ps
T395 /workspace/coverage/default/138.prim_prince_test.676667781 Jun 27 06:10:55 PM PDT 24 Jun 27 06:11:28 PM PDT 24 1567582103 ps
T396 /workspace/coverage/default/132.prim_prince_test.2668492933 Jun 27 06:10:58 PM PDT 24 Jun 27 06:11:37 PM PDT 24 1737649647 ps
T397 /workspace/coverage/default/167.prim_prince_test.2598112833 Jun 27 06:10:55 PM PDT 24 Jun 27 06:11:21 PM PDT 24 1202953946 ps
T398 /workspace/coverage/default/410.prim_prince_test.2682176860 Jun 27 06:11:59 PM PDT 24 Jun 27 06:13:22 PM PDT 24 3695119172 ps
T399 /workspace/coverage/default/443.prim_prince_test.1310177399 Jun 27 06:12:22 PM PDT 24 Jun 27 06:13:08 PM PDT 24 2057024631 ps
T400 /workspace/coverage/default/405.prim_prince_test.2023721237 Jun 27 06:12:02 PM PDT 24 Jun 27 06:12:30 PM PDT 24 1172617471 ps
T401 /workspace/coverage/default/8.prim_prince_test.205968319 Jun 27 06:09:59 PM PDT 24 Jun 27 06:11:15 PM PDT 24 3632648296 ps
T402 /workspace/coverage/default/44.prim_prince_test.868154741 Jun 27 06:10:14 PM PDT 24 Jun 27 06:11:26 PM PDT 24 3329413760 ps
T403 /workspace/coverage/default/485.prim_prince_test.3478996316 Jun 27 06:12:19 PM PDT 24 Jun 27 06:12:50 PM PDT 24 1358593770 ps
T404 /workspace/coverage/default/29.prim_prince_test.3620280668 Jun 27 06:10:11 PM PDT 24 Jun 27 06:11:13 PM PDT 24 3032775556 ps
T405 /workspace/coverage/default/332.prim_prince_test.1026651124 Jun 27 06:11:43 PM PDT 24 Jun 27 06:12:58 PM PDT 24 3404576415 ps
T406 /workspace/coverage/default/241.prim_prince_test.528551533 Jun 27 06:11:08 PM PDT 24 Jun 27 06:11:49 PM PDT 24 1977608510 ps
T407 /workspace/coverage/default/256.prim_prince_test.2329693903 Jun 27 06:11:12 PM PDT 24 Jun 27 06:11:49 PM PDT 24 1779480326 ps
T408 /workspace/coverage/default/290.prim_prince_test.4057954941 Jun 27 06:11:24 PM PDT 24 Jun 27 06:12:41 PM PDT 24 3748254683 ps
T409 /workspace/coverage/default/461.prim_prince_test.3355671195 Jun 27 06:12:22 PM PDT 24 Jun 27 06:12:52 PM PDT 24 1267980911 ps
T410 /workspace/coverage/default/163.prim_prince_test.875999386 Jun 27 06:10:54 PM PDT 24 Jun 27 06:11:37 PM PDT 24 2029631017 ps
T411 /workspace/coverage/default/13.prim_prince_test.3635199305 Jun 27 06:10:06 PM PDT 24 Jun 27 06:10:53 PM PDT 24 2210427037 ps
T412 /workspace/coverage/default/21.prim_prince_test.2028746207 Jun 27 06:10:17 PM PDT 24 Jun 27 06:10:44 PM PDT 24 1298209087 ps
T413 /workspace/coverage/default/107.prim_prince_test.2774568431 Jun 27 06:10:29 PM PDT 24 Jun 27 06:11:24 PM PDT 24 2549594675 ps
T414 /workspace/coverage/default/459.prim_prince_test.1242286354 Jun 27 06:12:16 PM PDT 24 Jun 27 06:13:21 PM PDT 24 3106975024 ps
T415 /workspace/coverage/default/99.prim_prince_test.4094793869 Jun 27 06:10:31 PM PDT 24 Jun 27 06:11:11 PM PDT 24 1924922929 ps
T416 /workspace/coverage/default/73.prim_prince_test.500024257 Jun 27 06:10:27 PM PDT 24 Jun 27 06:10:55 PM PDT 24 1278471828 ps
T417 /workspace/coverage/default/130.prim_prince_test.3106304539 Jun 27 06:11:00 PM PDT 24 Jun 27 06:11:58 PM PDT 24 2776722740 ps
T418 /workspace/coverage/default/351.prim_prince_test.2364170308 Jun 27 06:11:42 PM PDT 24 Jun 27 06:12:03 PM PDT 24 919335945 ps
T419 /workspace/coverage/default/379.prim_prince_test.3636370005 Jun 27 06:11:58 PM PDT 24 Jun 27 06:13:12 PM PDT 24 3542473821 ps
T420 /workspace/coverage/default/125.prim_prince_test.1809561285 Jun 27 06:10:57 PM PDT 24 Jun 27 06:11:32 PM PDT 24 1605284206 ps
T421 /workspace/coverage/default/200.prim_prince_test.1446296149 Jun 27 06:11:00 PM PDT 24 Jun 27 06:12:08 PM PDT 24 2975867094 ps
T422 /workspace/coverage/default/229.prim_prince_test.657341446 Jun 27 06:11:01 PM PDT 24 Jun 27 06:11:22 PM PDT 24 900456245 ps
T423 /workspace/coverage/default/266.prim_prince_test.572089928 Jun 27 06:11:19 PM PDT 24 Jun 27 06:12:15 PM PDT 24 2731642068 ps
T424 /workspace/coverage/default/246.prim_prince_test.3172309657 Jun 27 06:11:12 PM PDT 24 Jun 27 06:11:48 PM PDT 24 1772933836 ps
T425 /workspace/coverage/default/474.prim_prince_test.2609645028 Jun 27 06:12:17 PM PDT 24 Jun 27 06:13:22 PM PDT 24 2983390751 ps
T426 /workspace/coverage/default/28.prim_prince_test.2209150006 Jun 27 06:10:12 PM PDT 24 Jun 27 06:10:50 PM PDT 24 1810868825 ps
T427 /workspace/coverage/default/284.prim_prince_test.913486774 Jun 27 06:11:26 PM PDT 24 Jun 27 06:12:43 PM PDT 24 3703635108 ps
T428 /workspace/coverage/default/153.prim_prince_test.222760175 Jun 27 06:10:57 PM PDT 24 Jun 27 06:11:32 PM PDT 24 1707051863 ps
T429 /workspace/coverage/default/435.prim_prince_test.2026580555 Jun 27 06:12:13 PM PDT 24 Jun 27 06:13:07 PM PDT 24 2602835262 ps
T430 /workspace/coverage/default/42.prim_prince_test.3398041979 Jun 27 06:10:12 PM PDT 24 Jun 27 06:10:49 PM PDT 24 1740297457 ps
T431 /workspace/coverage/default/482.prim_prince_test.540774587 Jun 27 06:12:18 PM PDT 24 Jun 27 06:12:47 PM PDT 24 1280591448 ps
T432 /workspace/coverage/default/91.prim_prince_test.1873272843 Jun 27 06:10:27 PM PDT 24 Jun 27 06:11:32 PM PDT 24 3139727772 ps
T433 /workspace/coverage/default/207.prim_prince_test.474564716 Jun 27 06:11:03 PM PDT 24 Jun 27 06:11:57 PM PDT 24 2569126677 ps
T434 /workspace/coverage/default/211.prim_prince_test.1797996022 Jun 27 06:11:04 PM PDT 24 Jun 27 06:11:45 PM PDT 24 1889884610 ps
T435 /workspace/coverage/default/440.prim_prince_test.1490319027 Jun 27 06:12:23 PM PDT 24 Jun 27 06:13:19 PM PDT 24 2580808033 ps
T436 /workspace/coverage/default/142.prim_prince_test.4031739484 Jun 27 06:11:00 PM PDT 24 Jun 27 06:12:03 PM PDT 24 3164163909 ps
T437 /workspace/coverage/default/102.prim_prince_test.324728135 Jun 27 06:10:27 PM PDT 24 Jun 27 06:11:38 PM PDT 24 3453903049 ps
T438 /workspace/coverage/default/276.prim_prince_test.3307781076 Jun 27 06:11:11 PM PDT 24 Jun 27 06:12:24 PM PDT 24 3604717540 ps
T439 /workspace/coverage/default/468.prim_prince_test.2793668777 Jun 27 06:12:20 PM PDT 24 Jun 27 06:13:05 PM PDT 24 1923714035 ps
T440 /workspace/coverage/default/425.prim_prince_test.2496906926 Jun 27 06:12:23 PM PDT 24 Jun 27 06:13:02 PM PDT 24 1749557484 ps
T441 /workspace/coverage/default/237.prim_prince_test.1859518762 Jun 27 06:11:09 PM PDT 24 Jun 27 06:12:09 PM PDT 24 2873845972 ps
T442 /workspace/coverage/default/476.prim_prince_test.2509122510 Jun 27 06:12:23 PM PDT 24 Jun 27 06:13:38 PM PDT 24 3549574852 ps
T443 /workspace/coverage/default/283.prim_prince_test.851578336 Jun 27 06:11:24 PM PDT 24 Jun 27 06:11:59 PM PDT 24 1608471249 ps
T444 /workspace/coverage/default/400.prim_prince_test.313071092 Jun 27 06:12:00 PM PDT 24 Jun 27 06:12:56 PM PDT 24 2420102496 ps
T445 /workspace/coverage/default/192.prim_prince_test.3609869276 Jun 27 06:11:01 PM PDT 24 Jun 27 06:12:24 PM PDT 24 3757313494 ps
T446 /workspace/coverage/default/349.prim_prince_test.1892265196 Jun 27 06:11:42 PM PDT 24 Jun 27 06:12:47 PM PDT 24 3352387061 ps
T447 /workspace/coverage/default/158.prim_prince_test.472315208 Jun 27 06:11:01 PM PDT 24 Jun 27 06:11:50 PM PDT 24 2285299768 ps
T448 /workspace/coverage/default/195.prim_prince_test.678902466 Jun 27 06:11:02 PM PDT 24 Jun 27 06:12:08 PM PDT 24 3139105284 ps
T449 /workspace/coverage/default/104.prim_prince_test.1290537625 Jun 27 06:10:26 PM PDT 24 Jun 27 06:11:40 PM PDT 24 3575516230 ps
T450 /workspace/coverage/default/475.prim_prince_test.28454503 Jun 27 06:12:17 PM PDT 24 Jun 27 06:13:03 PM PDT 24 2120901590 ps
T451 /workspace/coverage/default/272.prim_prince_test.1838818673 Jun 27 06:11:18 PM PDT 24 Jun 27 06:11:42 PM PDT 24 1090834144 ps
T452 /workspace/coverage/default/488.prim_prince_test.1297416424 Jun 27 06:12:23 PM PDT 24 Jun 27 06:13:37 PM PDT 24 3477476848 ps
T453 /workspace/coverage/default/325.prim_prince_test.171723930 Jun 27 06:11:43 PM PDT 24 Jun 27 06:13:00 PM PDT 24 3538678315 ps
T454 /workspace/coverage/default/446.prim_prince_test.3845699333 Jun 27 06:12:15 PM PDT 24 Jun 27 06:12:59 PM PDT 24 2058442860 ps
T455 /workspace/coverage/default/397.prim_prince_test.3466589483 Jun 27 06:11:59 PM PDT 24 Jun 27 06:12:32 PM PDT 24 1425558612 ps
T456 /workspace/coverage/default/390.prim_prince_test.1399865473 Jun 27 06:11:58 PM PDT 24 Jun 27 06:12:50 PM PDT 24 2509272322 ps
T457 /workspace/coverage/default/352.prim_prince_test.2742653917 Jun 27 06:11:43 PM PDT 24 Jun 27 06:12:05 PM PDT 24 873593736 ps
T458 /workspace/coverage/default/75.prim_prince_test.1026077639 Jun 27 06:10:29 PM PDT 24 Jun 27 06:11:21 PM PDT 24 2476516955 ps
T459 /workspace/coverage/default/310.prim_prince_test.1354235103 Jun 27 06:11:25 PM PDT 24 Jun 27 06:11:58 PM PDT 24 1549177905 ps
T460 /workspace/coverage/default/10.prim_prince_test.1247367882 Jun 27 06:09:58 PM PDT 24 Jun 27 06:10:39 PM PDT 24 1931342672 ps
T461 /workspace/coverage/default/179.prim_prince_test.1146153872 Jun 27 06:11:00 PM PDT 24 Jun 27 06:12:04 PM PDT 24 3033580319 ps
T462 /workspace/coverage/default/380.prim_prince_test.1757501031 Jun 27 06:11:59 PM PDT 24 Jun 27 06:12:24 PM PDT 24 1068409068 ps
T463 /workspace/coverage/default/428.prim_prince_test.3223587243 Jun 27 06:12:14 PM PDT 24 Jun 27 06:13:02 PM PDT 24 2421452070 ps
T464 /workspace/coverage/default/365.prim_prince_test.875609887 Jun 27 06:11:41 PM PDT 24 Jun 27 06:12:15 PM PDT 24 1580570063 ps
T465 /workspace/coverage/default/472.prim_prince_test.452546853 Jun 27 06:12:17 PM PDT 24 Jun 27 06:13:23 PM PDT 24 2975640756 ps
T466 /workspace/coverage/default/247.prim_prince_test.529292962 Jun 27 06:11:11 PM PDT 24 Jun 27 06:11:44 PM PDT 24 1661930174 ps
T467 /workspace/coverage/default/262.prim_prince_test.626157848 Jun 27 06:11:17 PM PDT 24 Jun 27 06:12:02 PM PDT 24 2114974149 ps
T468 /workspace/coverage/default/404.prim_prince_test.3784638891 Jun 27 06:11:57 PM PDT 24 Jun 27 06:12:23 PM PDT 24 1175109521 ps
T469 /workspace/coverage/default/245.prim_prince_test.2629332941 Jun 27 06:11:11 PM PDT 24 Jun 27 06:11:38 PM PDT 24 1264511839 ps
T470 /workspace/coverage/default/371.prim_prince_test.880266687 Jun 27 06:11:59 PM PDT 24 Jun 27 06:13:00 PM PDT 24 2859110398 ps
T471 /workspace/coverage/default/336.prim_prince_test.4010112764 Jun 27 06:11:40 PM PDT 24 Jun 27 06:12:14 PM PDT 24 1664316686 ps
T472 /workspace/coverage/default/359.prim_prince_test.3495977991 Jun 27 06:11:42 PM PDT 24 Jun 27 06:12:51 PM PDT 24 3266311211 ps
T473 /workspace/coverage/default/307.prim_prince_test.2450455821 Jun 27 06:11:24 PM PDT 24 Jun 27 06:12:21 PM PDT 24 2827627029 ps
T474 /workspace/coverage/default/385.prim_prince_test.2342473489 Jun 27 06:12:04 PM PDT 24 Jun 27 06:12:23 PM PDT 24 848955676 ps
T475 /workspace/coverage/default/280.prim_prince_test.1000347460 Jun 27 06:11:13 PM PDT 24 Jun 27 06:12:23 PM PDT 24 3476400592 ps
T476 /workspace/coverage/default/328.prim_prince_test.2524797337 Jun 27 06:11:43 PM PDT 24 Jun 27 06:12:06 PM PDT 24 889471087 ps
T477 /workspace/coverage/default/394.prim_prince_test.3683934065 Jun 27 06:11:58 PM PDT 24 Jun 27 06:12:44 PM PDT 24 2206337563 ps
T478 /workspace/coverage/default/265.prim_prince_test.1610960963 Jun 27 06:11:16 PM PDT 24 Jun 27 06:12:01 PM PDT 24 2174320989 ps
T479 /workspace/coverage/default/305.prim_prince_test.3378963547 Jun 27 06:11:26 PM PDT 24 Jun 27 06:12:02 PM PDT 24 1691528530 ps
T480 /workspace/coverage/default/223.prim_prince_test.1927037989 Jun 27 06:10:57 PM PDT 24 Jun 27 06:11:32 PM PDT 24 1685186849 ps
T481 /workspace/coverage/default/372.prim_prince_test.1272895290 Jun 27 06:11:57 PM PDT 24 Jun 27 06:12:26 PM PDT 24 1327041842 ps
T482 /workspace/coverage/default/448.prim_prince_test.896987324 Jun 27 06:12:15 PM PDT 24 Jun 27 06:12:45 PM PDT 24 1358008638 ps
T483 /workspace/coverage/default/317.prim_prince_test.2472471593 Jun 27 06:11:42 PM PDT 24 Jun 27 06:12:03 PM PDT 24 854585030 ps
T484 /workspace/coverage/default/24.prim_prince_test.1744978443 Jun 27 06:10:11 PM PDT 24 Jun 27 06:11:17 PM PDT 24 3332839725 ps
T485 /workspace/coverage/default/80.prim_prince_test.3992092842 Jun 27 06:10:28 PM PDT 24 Jun 27 06:11:08 PM PDT 24 1820376454 ps
T486 /workspace/coverage/default/68.prim_prince_test.1717688181 Jun 27 06:10:26 PM PDT 24 Jun 27 06:11:01 PM PDT 24 1650156015 ps
T487 /workspace/coverage/default/59.prim_prince_test.1716548760 Jun 27 06:10:29 PM PDT 24 Jun 27 06:10:49 PM PDT 24 813155767 ps
T488 /workspace/coverage/default/64.prim_prince_test.2781069606 Jun 27 06:10:27 PM PDT 24 Jun 27 06:11:03 PM PDT 24 1660082159 ps
T489 /workspace/coverage/default/493.prim_prince_test.4279308053 Jun 27 06:12:21 PM PDT 24 Jun 27 06:12:43 PM PDT 24 960301232 ps
T490 /workspace/coverage/default/364.prim_prince_test.3478948692 Jun 27 06:11:42 PM PDT 24 Jun 27 06:12:10 PM PDT 24 1178251031 ps
T491 /workspace/coverage/default/354.prim_prince_test.619412387 Jun 27 06:11:40 PM PDT 24 Jun 27 06:12:21 PM PDT 24 2058604781 ps
T492 /workspace/coverage/default/255.prim_prince_test.829506575 Jun 27 06:11:10 PM PDT 24 Jun 27 06:12:06 PM PDT 24 3081351775 ps
T493 /workspace/coverage/default/178.prim_prince_test.2255829354 Jun 27 06:11:00 PM PDT 24 Jun 27 06:12:07 PM PDT 24 3499277311 ps
T494 /workspace/coverage/default/357.prim_prince_test.2950683237 Jun 27 06:11:42 PM PDT 24 Jun 27 06:12:28 PM PDT 24 2320366374 ps
T495 /workspace/coverage/default/205.prim_prince_test.815140163 Jun 27 06:11:04 PM PDT 24 Jun 27 06:12:06 PM PDT 24 2939120502 ps
T496 /workspace/coverage/default/391.prim_prince_test.2000319800 Jun 27 06:11:58 PM PDT 24 Jun 27 06:13:15 PM PDT 24 3573087499 ps
T497 /workspace/coverage/default/108.prim_prince_test.3914373669 Jun 27 06:10:27 PM PDT 24 Jun 27 06:11:43 PM PDT 24 3610382192 ps
T498 /workspace/coverage/default/409.prim_prince_test.1385523870 Jun 27 06:12:00 PM PDT 24 Jun 27 06:12:52 PM PDT 24 2366472586 ps
T499 /workspace/coverage/default/53.prim_prince_test.1021578553 Jun 27 06:10:27 PM PDT 24 Jun 27 06:11:02 PM PDT 24 1577516593 ps
T500 /workspace/coverage/default/249.prim_prince_test.2472169418 Jun 27 06:11:18 PM PDT 24 Jun 27 06:11:54 PM PDT 24 1714447640 ps

Test location /workspace/coverage/default/105.prim_prince_test.3163986784
Short name T7
Test name
Test status
Simulation time 1811046960 ps
CPU time 30.15 seconds
Started Jun 27 06:10:28 PM PDT 24
Finished Jun 27 06:11:08 PM PDT 24
Peak memory 146740 kb
Host smart-52326fbd-bfb0-4043-a41b-3fabbd2cc32e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163986784 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 105.prim_prince_test.3163986784
Directory /workspace/105.prim_prince_test/latest

Test location /workspace/coverage/default/0.prim_prince_test.2264701180
Short name T119
Test name
Test status
Simulation time 1044037488 ps
CPU time 17.55 seconds
Started Jun 27 06:10:04 PM PDT 24
Finished Jun 27 06:10:27 PM PDT 24
Peak memory 146748 kb
Host smart-7de216cd-dfa4-4cd3-a744-4c3a89570b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264701180 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_prince_test.2264701180
Directory /workspace/0.prim_prince_test/latest

Test location /workspace/coverage/default/1.prim_prince_test.20620904
Short name T369
Test name
Test status
Simulation time 1994798161 ps
CPU time 32.39 seconds
Started Jun 27 06:10:05 PM PDT 24
Finished Jun 27 06:10:44 PM PDT 24
Peak memory 146752 kb
Host smart-0df22ce3-d6d0-44ac-bded-a9c33f02d88e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20620904 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_prince_test.20620904
Directory /workspace/1.prim_prince_test/latest

Test location /workspace/coverage/default/10.prim_prince_test.1247367882
Short name T460
Test name
Test status
Simulation time 1931342672 ps
CPU time 30.78 seconds
Started Jun 27 06:09:58 PM PDT 24
Finished Jun 27 06:10:39 PM PDT 24
Peak memory 146740 kb
Host smart-94bd2d7d-5e47-4490-9de6-53834c815f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247367882 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_prince_test.1247367882
Directory /workspace/10.prim_prince_test/latest

Test location /workspace/coverage/default/100.prim_prince_test.853955974
Short name T236
Test name
Test status
Simulation time 2082655016 ps
CPU time 34.65 seconds
Started Jun 27 06:10:26 PM PDT 24
Finished Jun 27 06:11:10 PM PDT 24
Peak memory 146744 kb
Host smart-31b7c338-aa52-48aa-985f-615f1d77ac29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853955974 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 100.prim_prince_test.853955974
Directory /workspace/100.prim_prince_test/latest

Test location /workspace/coverage/default/101.prim_prince_test.2614399086
Short name T19
Test name
Test status
Simulation time 2962328496 ps
CPU time 49.72 seconds
Started Jun 27 06:10:25 PM PDT 24
Finished Jun 27 06:11:27 PM PDT 24
Peak memory 146800 kb
Host smart-3b01a289-e281-4658-ac81-28f8bc152810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614399086 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 101.prim_prince_test.2614399086
Directory /workspace/101.prim_prince_test/latest

Test location /workspace/coverage/default/102.prim_prince_test.324728135
Short name T437
Test name
Test status
Simulation time 3453903049 ps
CPU time 56.81 seconds
Started Jun 27 06:10:27 PM PDT 24
Finished Jun 27 06:11:38 PM PDT 24
Peak memory 146808 kb
Host smart-536557c0-e07d-4806-ba4f-2a42c3fab0e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324728135 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 102.prim_prince_test.324728135
Directory /workspace/102.prim_prince_test/latest

Test location /workspace/coverage/default/103.prim_prince_test.2641291837
Short name T21
Test name
Test status
Simulation time 1170399708 ps
CPU time 19.94 seconds
Started Jun 27 06:10:28 PM PDT 24
Finished Jun 27 06:10:55 PM PDT 24
Peak memory 146728 kb
Host smart-1951ab65-ffe2-41d2-bd20-edb715138c51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641291837 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 103.prim_prince_test.2641291837
Directory /workspace/103.prim_prince_test/latest

Test location /workspace/coverage/default/104.prim_prince_test.1290537625
Short name T449
Test name
Test status
Simulation time 3575516230 ps
CPU time 59.29 seconds
Started Jun 27 06:10:26 PM PDT 24
Finished Jun 27 06:11:40 PM PDT 24
Peak memory 146788 kb
Host smart-3ca92399-c031-434b-ba40-68d01eab9ed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290537625 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 104.prim_prince_test.1290537625
Directory /workspace/104.prim_prince_test/latest

Test location /workspace/coverage/default/106.prim_prince_test.1038686833
Short name T327
Test name
Test status
Simulation time 3427130363 ps
CPU time 57.54 seconds
Started Jun 27 06:10:25 PM PDT 24
Finished Jun 27 06:11:37 PM PDT 24
Peak memory 146732 kb
Host smart-9484b8f5-4a60-4491-b8c6-26db74e4cf4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038686833 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 106.prim_prince_test.1038686833
Directory /workspace/106.prim_prince_test/latest

Test location /workspace/coverage/default/107.prim_prince_test.2774568431
Short name T413
Test name
Test status
Simulation time 2549594675 ps
CPU time 42.88 seconds
Started Jun 27 06:10:29 PM PDT 24
Finished Jun 27 06:11:24 PM PDT 24
Peak memory 146796 kb
Host smart-87e572ae-6fa0-409a-baea-7e55a7e8f781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774568431 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 107.prim_prince_test.2774568431
Directory /workspace/107.prim_prince_test/latest

Test location /workspace/coverage/default/108.prim_prince_test.3914373669
Short name T497
Test name
Test status
Simulation time 3610382192 ps
CPU time 60.48 seconds
Started Jun 27 06:10:27 PM PDT 24
Finished Jun 27 06:11:43 PM PDT 24
Peak memory 146788 kb
Host smart-d6e2048a-8f3d-4e8e-a6f6-fda74787d3d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914373669 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 108.prim_prince_test.3914373669
Directory /workspace/108.prim_prince_test/latest

Test location /workspace/coverage/default/109.prim_prince_test.556998950
Short name T241
Test name
Test status
Simulation time 1834439839 ps
CPU time 31.75 seconds
Started Jun 27 06:10:27 PM PDT 24
Finished Jun 27 06:11:09 PM PDT 24
Peak memory 146728 kb
Host smart-f9d455e9-94c9-4727-a2c3-18bea6778e38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556998950 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 109.prim_prince_test.556998950
Directory /workspace/109.prim_prince_test/latest

Test location /workspace/coverage/default/11.prim_prince_test.1432650511
Short name T42
Test name
Test status
Simulation time 1869047528 ps
CPU time 30.81 seconds
Started Jun 27 06:10:06 PM PDT 24
Finished Jun 27 06:10:45 PM PDT 24
Peak memory 146700 kb
Host smart-f34fef42-f0d6-4bbf-9e79-42620b86225d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432650511 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_prince_test.1432650511
Directory /workspace/11.prim_prince_test/latest

Test location /workspace/coverage/default/110.prim_prince_test.2059741879
Short name T279
Test name
Test status
Simulation time 880345165 ps
CPU time 14.97 seconds
Started Jun 27 06:10:28 PM PDT 24
Finished Jun 27 06:10:49 PM PDT 24
Peak memory 146736 kb
Host smart-613dc26a-1f72-4b4d-a0fb-ff90942eb7a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059741879 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 110.prim_prince_test.2059741879
Directory /workspace/110.prim_prince_test/latest

Test location /workspace/coverage/default/111.prim_prince_test.1754461763
Short name T156
Test name
Test status
Simulation time 2677164348 ps
CPU time 45.56 seconds
Started Jun 27 06:10:29 PM PDT 24
Finished Jun 27 06:11:29 PM PDT 24
Peak memory 146808 kb
Host smart-94e8b010-a8f9-48db-9c91-fd2063c00eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754461763 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 111.prim_prince_test.1754461763
Directory /workspace/111.prim_prince_test/latest

Test location /workspace/coverage/default/112.prim_prince_test.1693521872
Short name T174
Test name
Test status
Simulation time 823545900 ps
CPU time 13.77 seconds
Started Jun 27 06:10:31 PM PDT 24
Finished Jun 27 06:10:50 PM PDT 24
Peak memory 146680 kb
Host smart-fe890e25-d640-4ff9-be0d-81c1e2a6408d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693521872 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 112.prim_prince_test.1693521872
Directory /workspace/112.prim_prince_test/latest

Test location /workspace/coverage/default/113.prim_prince_test.3961911938
Short name T6
Test name
Test status
Simulation time 2960209333 ps
CPU time 49.08 seconds
Started Jun 27 06:10:29 PM PDT 24
Finished Jun 27 06:11:31 PM PDT 24
Peak memory 146796 kb
Host smart-6f3ac034-eb54-4e17-9d12-e444a58f1300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961911938 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 113.prim_prince_test.3961911938
Directory /workspace/113.prim_prince_test/latest

Test location /workspace/coverage/default/114.prim_prince_test.1882410739
Short name T383
Test name
Test status
Simulation time 1153415088 ps
CPU time 19.46 seconds
Started Jun 27 06:10:28 PM PDT 24
Finished Jun 27 06:10:55 PM PDT 24
Peak memory 146736 kb
Host smart-981b4e86-702e-4a78-86e5-af8f5ba3933d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882410739 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 114.prim_prince_test.1882410739
Directory /workspace/114.prim_prince_test/latest

Test location /workspace/coverage/default/115.prim_prince_test.3996466354
Short name T262
Test name
Test status
Simulation time 2760057061 ps
CPU time 46.29 seconds
Started Jun 27 06:10:28 PM PDT 24
Finished Jun 27 06:11:27 PM PDT 24
Peak memory 146796 kb
Host smart-a63883dc-b12c-4146-9aad-9455814f0fbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996466354 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 115.prim_prince_test.3996466354
Directory /workspace/115.prim_prince_test/latest

Test location /workspace/coverage/default/116.prim_prince_test.3430248879
Short name T63
Test name
Test status
Simulation time 1763256341 ps
CPU time 29.59 seconds
Started Jun 27 06:10:28 PM PDT 24
Finished Jun 27 06:11:07 PM PDT 24
Peak memory 146736 kb
Host smart-b9279c1a-76cc-449e-95ed-686cf6678d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430248879 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 116.prim_prince_test.3430248879
Directory /workspace/116.prim_prince_test/latest

Test location /workspace/coverage/default/117.prim_prince_test.3405755289
Short name T298
Test name
Test status
Simulation time 3114982631 ps
CPU time 51.59 seconds
Started Jun 27 06:10:28 PM PDT 24
Finished Jun 27 06:11:34 PM PDT 24
Peak memory 146800 kb
Host smart-77b9c9c4-ba84-47fb-a065-d5d483c44342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405755289 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 117.prim_prince_test.3405755289
Directory /workspace/117.prim_prince_test/latest

Test location /workspace/coverage/default/118.prim_prince_test.2585967995
Short name T391
Test name
Test status
Simulation time 1470983926 ps
CPU time 24.68 seconds
Started Jun 27 06:10:29 PM PDT 24
Finished Jun 27 06:11:02 PM PDT 24
Peak memory 146732 kb
Host smart-1683dddb-c2ce-4eec-aaf4-566f69ff9f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585967995 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 118.prim_prince_test.2585967995
Directory /workspace/118.prim_prince_test/latest

Test location /workspace/coverage/default/119.prim_prince_test.2087545506
Short name T129
Test name
Test status
Simulation time 801201246 ps
CPU time 13.8 seconds
Started Jun 27 06:10:29 PM PDT 24
Finished Jun 27 06:10:48 PM PDT 24
Peak memory 146732 kb
Host smart-5b3bf7a4-ae50-4a39-ae94-f7477198047e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087545506 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 119.prim_prince_test.2087545506
Directory /workspace/119.prim_prince_test/latest

Test location /workspace/coverage/default/12.prim_prince_test.4285935948
Short name T44
Test name
Test status
Simulation time 836314234 ps
CPU time 13.96 seconds
Started Jun 27 06:10:06 PM PDT 24
Finished Jun 27 06:10:24 PM PDT 24
Peak memory 146700 kb
Host smart-5c5dcf93-b340-4413-bb70-9d98784ad739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285935948 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_prince_test.4285935948
Directory /workspace/12.prim_prince_test/latest

Test location /workspace/coverage/default/120.prim_prince_test.3816177032
Short name T270
Test name
Test status
Simulation time 2145973493 ps
CPU time 36.34 seconds
Started Jun 27 06:10:30 PM PDT 24
Finished Jun 27 06:11:17 PM PDT 24
Peak memory 146728 kb
Host smart-47b43d35-f2da-4acd-ad4d-4b18fc19a030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816177032 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 120.prim_prince_test.3816177032
Directory /workspace/120.prim_prince_test/latest

Test location /workspace/coverage/default/121.prim_prince_test.1032215426
Short name T330
Test name
Test status
Simulation time 828906541 ps
CPU time 14.08 seconds
Started Jun 27 06:11:00 PM PDT 24
Finished Jun 27 06:11:20 PM PDT 24
Peak memory 146736 kb
Host smart-0c66c3a2-2228-4cc8-9e03-7f4a8bff28dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032215426 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 121.prim_prince_test.1032215426
Directory /workspace/121.prim_prince_test/latest

Test location /workspace/coverage/default/122.prim_prince_test.1593519452
Short name T190
Test name
Test status
Simulation time 3640886641 ps
CPU time 60.51 seconds
Started Jun 27 06:10:59 PM PDT 24
Finished Jun 27 06:12:15 PM PDT 24
Peak memory 146800 kb
Host smart-9a7b15ff-3301-45c1-b866-31fc7756c1cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593519452 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 122.prim_prince_test.1593519452
Directory /workspace/122.prim_prince_test/latest

Test location /workspace/coverage/default/123.prim_prince_test.2241352273
Short name T64
Test name
Test status
Simulation time 2756773264 ps
CPU time 45.58 seconds
Started Jun 27 06:10:54 PM PDT 24
Finished Jun 27 06:11:50 PM PDT 24
Peak memory 146800 kb
Host smart-dc4dd465-87ac-4dab-b826-02975933dbc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241352273 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 123.prim_prince_test.2241352273
Directory /workspace/123.prim_prince_test/latest

Test location /workspace/coverage/default/124.prim_prince_test.2588897874
Short name T166
Test name
Test status
Simulation time 1195464365 ps
CPU time 19.57 seconds
Started Jun 27 06:10:55 PM PDT 24
Finished Jun 27 06:11:20 PM PDT 24
Peak memory 146704 kb
Host smart-c82e722d-0683-4cce-ac59-613c35ff38de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588897874 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 124.prim_prince_test.2588897874
Directory /workspace/124.prim_prince_test/latest

Test location /workspace/coverage/default/125.prim_prince_test.1809561285
Short name T420
Test name
Test status
Simulation time 1605284206 ps
CPU time 26.89 seconds
Started Jun 27 06:10:57 PM PDT 24
Finished Jun 27 06:11:32 PM PDT 24
Peak memory 146736 kb
Host smart-41fbb331-bcde-46fb-9bac-475c60f0f368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809561285 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 125.prim_prince_test.1809561285
Directory /workspace/125.prim_prince_test/latest

Test location /workspace/coverage/default/126.prim_prince_test.2970904713
Short name T48
Test name
Test status
Simulation time 1587085088 ps
CPU time 27.09 seconds
Started Jun 27 06:10:55 PM PDT 24
Finished Jun 27 06:11:30 PM PDT 24
Peak memory 146736 kb
Host smart-96f1b265-2f6f-495f-90b9-9684c81e8658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970904713 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 126.prim_prince_test.2970904713
Directory /workspace/126.prim_prince_test/latest

Test location /workspace/coverage/default/127.prim_prince_test.1114140239
Short name T252
Test name
Test status
Simulation time 1058636342 ps
CPU time 17.86 seconds
Started Jun 27 06:10:59 PM PDT 24
Finished Jun 27 06:11:24 PM PDT 24
Peak memory 146744 kb
Host smart-12601926-291e-419c-86ff-d27deeee1013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114140239 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 127.prim_prince_test.1114140239
Directory /workspace/127.prim_prince_test/latest

Test location /workspace/coverage/default/128.prim_prince_test.3590814727
Short name T244
Test name
Test status
Simulation time 1314065289 ps
CPU time 22.51 seconds
Started Jun 27 06:10:56 PM PDT 24
Finished Jun 27 06:11:25 PM PDT 24
Peak memory 146724 kb
Host smart-ddc4c6d3-cf79-4ae8-a17d-5a5d5ea911ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590814727 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 128.prim_prince_test.3590814727
Directory /workspace/128.prim_prince_test/latest

Test location /workspace/coverage/default/129.prim_prince_test.2007421437
Short name T206
Test name
Test status
Simulation time 2591311769 ps
CPU time 44.28 seconds
Started Jun 27 06:10:58 PM PDT 24
Finished Jun 27 06:11:54 PM PDT 24
Peak memory 146764 kb
Host smart-52419938-522c-4dd9-8550-bda83b66ff04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007421437 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 129.prim_prince_test.2007421437
Directory /workspace/129.prim_prince_test/latest

Test location /workspace/coverage/default/13.prim_prince_test.3635199305
Short name T411
Test name
Test status
Simulation time 2210427037 ps
CPU time 37.04 seconds
Started Jun 27 06:10:06 PM PDT 24
Finished Jun 27 06:10:53 PM PDT 24
Peak memory 146756 kb
Host smart-b5b32f2d-8141-46bc-8a86-ddea79d610ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635199305 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_prince_test.3635199305
Directory /workspace/13.prim_prince_test/latest

Test location /workspace/coverage/default/130.prim_prince_test.3106304539
Short name T417
Test name
Test status
Simulation time 2776722740 ps
CPU time 45.75 seconds
Started Jun 27 06:11:00 PM PDT 24
Finished Jun 27 06:11:58 PM PDT 24
Peak memory 146796 kb
Host smart-532759a5-4d78-48f1-bc8f-0d2b61622284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106304539 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 130.prim_prince_test.3106304539
Directory /workspace/130.prim_prince_test/latest

Test location /workspace/coverage/default/131.prim_prince_test.2966749201
Short name T152
Test name
Test status
Simulation time 2269423900 ps
CPU time 38.95 seconds
Started Jun 27 06:10:53 PM PDT 24
Finished Jun 27 06:11:43 PM PDT 24
Peak memory 146800 kb
Host smart-7554d59e-242a-4b65-bb44-c64bf30ac1dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966749201 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 131.prim_prince_test.2966749201
Directory /workspace/131.prim_prince_test/latest

Test location /workspace/coverage/default/132.prim_prince_test.2668492933
Short name T396
Test name
Test status
Simulation time 1737649647 ps
CPU time 29.62 seconds
Started Jun 27 06:10:58 PM PDT 24
Finished Jun 27 06:11:37 PM PDT 24
Peak memory 146700 kb
Host smart-a68f0123-afdd-4773-870a-d7bd4eed33f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668492933 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 132.prim_prince_test.2668492933
Directory /workspace/132.prim_prince_test/latest

Test location /workspace/coverage/default/133.prim_prince_test.4018039960
Short name T141
Test name
Test status
Simulation time 791405972 ps
CPU time 13.91 seconds
Started Jun 27 06:10:58 PM PDT 24
Finished Jun 27 06:11:17 PM PDT 24
Peak memory 146104 kb
Host smart-2e2feb0d-2351-4e2e-8374-77fefd04402c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018039960 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 133.prim_prince_test.4018039960
Directory /workspace/133.prim_prince_test/latest

Test location /workspace/coverage/default/134.prim_prince_test.2515729335
Short name T218
Test name
Test status
Simulation time 1248855678 ps
CPU time 21.04 seconds
Started Jun 27 06:10:56 PM PDT 24
Finished Jun 27 06:11:23 PM PDT 24
Peak memory 146744 kb
Host smart-f4247f87-176b-48cd-96ac-e24335d4d748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515729335 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 134.prim_prince_test.2515729335
Directory /workspace/134.prim_prince_test/latest

Test location /workspace/coverage/default/135.prim_prince_test.1121599573
Short name T115
Test name
Test status
Simulation time 3602319029 ps
CPU time 57.34 seconds
Started Jun 27 06:10:54 PM PDT 24
Finished Jun 27 06:12:04 PM PDT 24
Peak memory 146800 kb
Host smart-80946b8d-e6a0-46e0-b991-1b0c23434553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121599573 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 135.prim_prince_test.1121599573
Directory /workspace/135.prim_prince_test/latest

Test location /workspace/coverage/default/136.prim_prince_test.909462618
Short name T267
Test name
Test status
Simulation time 3168208358 ps
CPU time 53.36 seconds
Started Jun 27 06:10:56 PM PDT 24
Finished Jun 27 06:12:03 PM PDT 24
Peak memory 146808 kb
Host smart-e52a69af-4fa9-4828-a3e0-580c6fd8e1d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909462618 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 136.prim_prince_test.909462618
Directory /workspace/136.prim_prince_test/latest

Test location /workspace/coverage/default/137.prim_prince_test.1874513031
Short name T177
Test name
Test status
Simulation time 3392565500 ps
CPU time 55.71 seconds
Started Jun 27 06:10:54 PM PDT 24
Finished Jun 27 06:12:03 PM PDT 24
Peak memory 146864 kb
Host smart-b6eb3160-d856-48e2-8aba-52c791ef167e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874513031 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 137.prim_prince_test.1874513031
Directory /workspace/137.prim_prince_test/latest

Test location /workspace/coverage/default/138.prim_prince_test.676667781
Short name T395
Test name
Test status
Simulation time 1567582103 ps
CPU time 25.65 seconds
Started Jun 27 06:10:55 PM PDT 24
Finished Jun 27 06:11:28 PM PDT 24
Peak memory 146744 kb
Host smart-4915c874-ba45-49d0-a65c-99bf3780d2f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676667781 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 138.prim_prince_test.676667781
Directory /workspace/138.prim_prince_test/latest

Test location /workspace/coverage/default/139.prim_prince_test.3525838775
Short name T377
Test name
Test status
Simulation time 1009469490 ps
CPU time 16.86 seconds
Started Jun 27 06:10:56 PM PDT 24
Finished Jun 27 06:11:18 PM PDT 24
Peak memory 146724 kb
Host smart-30c817a4-c2b9-4277-aae1-7b9104f05586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525838775 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 139.prim_prince_test.3525838775
Directory /workspace/139.prim_prince_test/latest

Test location /workspace/coverage/default/14.prim_prince_test.421498336
Short name T341
Test name
Test status
Simulation time 976188034 ps
CPU time 16.45 seconds
Started Jun 27 06:10:06 PM PDT 24
Finished Jun 27 06:10:27 PM PDT 24
Peak memory 146688 kb
Host smart-b8dc8f90-69b3-454a-92d1-83e88d1d4d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421498336 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_prince_test.421498336
Directory /workspace/14.prim_prince_test/latest

Test location /workspace/coverage/default/140.prim_prince_test.429951571
Short name T342
Test name
Test status
Simulation time 2545738320 ps
CPU time 42.24 seconds
Started Jun 27 06:10:56 PM PDT 24
Finished Jun 27 06:11:49 PM PDT 24
Peak memory 146808 kb
Host smart-c47d1538-0dcd-4179-b6e1-12458db18f42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429951571 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 140.prim_prince_test.429951571
Directory /workspace/140.prim_prince_test/latest

Test location /workspace/coverage/default/141.prim_prince_test.856890929
Short name T53
Test name
Test status
Simulation time 1065234513 ps
CPU time 17.79 seconds
Started Jun 27 06:11:00 PM PDT 24
Finished Jun 27 06:11:24 PM PDT 24
Peak memory 146748 kb
Host smart-1a498bb7-8f17-4566-b702-8678be8a001b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856890929 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 141.prim_prince_test.856890929
Directory /workspace/141.prim_prince_test/latest

Test location /workspace/coverage/default/142.prim_prince_test.4031739484
Short name T436
Test name
Test status
Simulation time 3164163909 ps
CPU time 50.59 seconds
Started Jun 27 06:11:00 PM PDT 24
Finished Jun 27 06:12:03 PM PDT 24
Peak memory 146804 kb
Host smart-10df8a83-a9ba-4391-91af-1088a65843a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031739484 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 142.prim_prince_test.4031739484
Directory /workspace/142.prim_prince_test/latest

Test location /workspace/coverage/default/143.prim_prince_test.4094544204
Short name T245
Test name
Test status
Simulation time 2429351004 ps
CPU time 40.93 seconds
Started Jun 27 06:10:54 PM PDT 24
Finished Jun 27 06:11:45 PM PDT 24
Peak memory 146792 kb
Host smart-f1e4c7f5-ea79-4bc3-9a2d-fe06ebfec4eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094544204 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 143.prim_prince_test.4094544204
Directory /workspace/143.prim_prince_test/latest

Test location /workspace/coverage/default/144.prim_prince_test.913701489
Short name T114
Test name
Test status
Simulation time 1807755576 ps
CPU time 29.94 seconds
Started Jun 27 06:10:57 PM PDT 24
Finished Jun 27 06:11:35 PM PDT 24
Peak memory 146744 kb
Host smart-cc094c38-b447-4955-8a34-538e9bf30de0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913701489 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 144.prim_prince_test.913701489
Directory /workspace/144.prim_prince_test/latest

Test location /workspace/coverage/default/145.prim_prince_test.3241747563
Short name T137
Test name
Test status
Simulation time 3277198010 ps
CPU time 52.52 seconds
Started Jun 27 06:10:54 PM PDT 24
Finished Jun 27 06:11:59 PM PDT 24
Peak memory 146784 kb
Host smart-2a4dd118-7c50-4244-989d-909dab346790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241747563 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 145.prim_prince_test.3241747563
Directory /workspace/145.prim_prince_test/latest

Test location /workspace/coverage/default/146.prim_prince_test.2722975899
Short name T258
Test name
Test status
Simulation time 3343947066 ps
CPU time 55.92 seconds
Started Jun 27 06:10:54 PM PDT 24
Finished Jun 27 06:12:04 PM PDT 24
Peak memory 146760 kb
Host smart-9634acf8-acae-4f2e-ac21-0d33d0d89bc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722975899 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 146.prim_prince_test.2722975899
Directory /workspace/146.prim_prince_test/latest

Test location /workspace/coverage/default/147.prim_prince_test.870704836
Short name T146
Test name
Test status
Simulation time 2979854577 ps
CPU time 49.44 seconds
Started Jun 27 06:10:56 PM PDT 24
Finished Jun 27 06:11:58 PM PDT 24
Peak memory 146816 kb
Host smart-327c96d9-c6cf-4b4f-977b-b2a5587a9a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870704836 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 147.prim_prince_test.870704836
Directory /workspace/147.prim_prince_test/latest

Test location /workspace/coverage/default/148.prim_prince_test.4276885446
Short name T302
Test name
Test status
Simulation time 2503909460 ps
CPU time 41.32 seconds
Started Jun 27 06:10:55 PM PDT 24
Finished Jun 27 06:11:47 PM PDT 24
Peak memory 146792 kb
Host smart-cc720212-14ac-4a42-b2f1-6b13cb231279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276885446 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 148.prim_prince_test.4276885446
Directory /workspace/148.prim_prince_test/latest

Test location /workspace/coverage/default/149.prim_prince_test.4029712372
Short name T209
Test name
Test status
Simulation time 1023709665 ps
CPU time 17.7 seconds
Started Jun 27 06:10:58 PM PDT 24
Finished Jun 27 06:11:22 PM PDT 24
Peak memory 146700 kb
Host smart-a9860aaf-e3cf-4085-a6bf-00992c8c11a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029712372 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 149.prim_prince_test.4029712372
Directory /workspace/149.prim_prince_test/latest

Test location /workspace/coverage/default/15.prim_prince_test.2929020214
Short name T319
Test name
Test status
Simulation time 1819353420 ps
CPU time 30.82 seconds
Started Jun 27 06:10:13 PM PDT 24
Finished Jun 27 06:10:52 PM PDT 24
Peak memory 146740 kb
Host smart-0c8b551a-aca0-4fbb-98aa-e408b7457866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929020214 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_prince_test.2929020214
Directory /workspace/15.prim_prince_test/latest

Test location /workspace/coverage/default/150.prim_prince_test.1726154507
Short name T104
Test name
Test status
Simulation time 2795828488 ps
CPU time 46.5 seconds
Started Jun 27 06:10:55 PM PDT 24
Finished Jun 27 06:11:53 PM PDT 24
Peak memory 146796 kb
Host smart-11f6c35e-9dd5-4a53-8b27-f254adb5fbd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726154507 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 150.prim_prince_test.1726154507
Directory /workspace/150.prim_prince_test/latest

Test location /workspace/coverage/default/151.prim_prince_test.3200551419
Short name T95
Test name
Test status
Simulation time 2680213118 ps
CPU time 45.46 seconds
Started Jun 27 06:10:58 PM PDT 24
Finished Jun 27 06:11:55 PM PDT 24
Peak memory 146784 kb
Host smart-8f599539-fe1b-48b4-9c42-cd80a114b100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200551419 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 151.prim_prince_test.3200551419
Directory /workspace/151.prim_prince_test/latest

Test location /workspace/coverage/default/152.prim_prince_test.3486623721
Short name T14
Test name
Test status
Simulation time 1063183417 ps
CPU time 17.5 seconds
Started Jun 27 06:11:03 PM PDT 24
Finished Jun 27 06:11:26 PM PDT 24
Peak memory 146672 kb
Host smart-cfca236b-bea1-4c3c-a0c3-a1df610c8809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486623721 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 152.prim_prince_test.3486623721
Directory /workspace/152.prim_prince_test/latest

Test location /workspace/coverage/default/153.prim_prince_test.222760175
Short name T428
Test name
Test status
Simulation time 1707051863 ps
CPU time 28.08 seconds
Started Jun 27 06:10:57 PM PDT 24
Finished Jun 27 06:11:32 PM PDT 24
Peak memory 146700 kb
Host smart-c01321ba-da34-42ff-af93-4b023929c07b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222760175 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 153.prim_prince_test.222760175
Directory /workspace/153.prim_prince_test/latest

Test location /workspace/coverage/default/154.prim_prince_test.1436992533
Short name T56
Test name
Test status
Simulation time 2285769202 ps
CPU time 37.25 seconds
Started Jun 27 06:10:59 PM PDT 24
Finished Jun 27 06:11:46 PM PDT 24
Peak memory 146800 kb
Host smart-c06833e4-cbc5-4297-a17b-b60f5b65c4a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436992533 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 154.prim_prince_test.1436992533
Directory /workspace/154.prim_prince_test/latest

Test location /workspace/coverage/default/155.prim_prince_test.4231241134
Short name T37
Test name
Test status
Simulation time 1151421223 ps
CPU time 19.42 seconds
Started Jun 27 06:10:59 PM PDT 24
Finished Jun 27 06:11:24 PM PDT 24
Peak memory 146732 kb
Host smart-8a75d081-5519-40f4-99ab-0f1672b6a2bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231241134 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 155.prim_prince_test.4231241134
Directory /workspace/155.prim_prince_test/latest

Test location /workspace/coverage/default/156.prim_prince_test.937775249
Short name T143
Test name
Test status
Simulation time 1399699416 ps
CPU time 24 seconds
Started Jun 27 06:10:54 PM PDT 24
Finished Jun 27 06:11:26 PM PDT 24
Peak memory 146748 kb
Host smart-0f98bf13-d97d-48a6-b1d0-cfc7ca383cc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937775249 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 156.prim_prince_test.937775249
Directory /workspace/156.prim_prince_test/latest

Test location /workspace/coverage/default/157.prim_prince_test.2801631826
Short name T379
Test name
Test status
Simulation time 2586497593 ps
CPU time 43.16 seconds
Started Jun 27 06:10:59 PM PDT 24
Finished Jun 27 06:11:55 PM PDT 24
Peak memory 146796 kb
Host smart-a0df76e1-9731-4981-b83c-aaf44bf4f93d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801631826 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 157.prim_prince_test.2801631826
Directory /workspace/157.prim_prince_test/latest

Test location /workspace/coverage/default/158.prim_prince_test.472315208
Short name T447
Test name
Test status
Simulation time 2285299768 ps
CPU time 38.69 seconds
Started Jun 27 06:11:01 PM PDT 24
Finished Jun 27 06:11:50 PM PDT 24
Peak memory 146728 kb
Host smart-d8d11ace-bcdc-4b9c-aa43-6c46d9086ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472315208 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 158.prim_prince_test.472315208
Directory /workspace/158.prim_prince_test/latest

Test location /workspace/coverage/default/159.prim_prince_test.3789439213
Short name T238
Test name
Test status
Simulation time 2827462205 ps
CPU time 46.59 seconds
Started Jun 27 06:10:56 PM PDT 24
Finished Jun 27 06:11:53 PM PDT 24
Peak memory 146768 kb
Host smart-f7d125e1-6f5a-42fb-b12f-fdc505502119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789439213 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 159.prim_prince_test.3789439213
Directory /workspace/159.prim_prince_test/latest

Test location /workspace/coverage/default/16.prim_prince_test.4171469727
Short name T293
Test name
Test status
Simulation time 2153641072 ps
CPU time 36.02 seconds
Started Jun 27 06:10:11 PM PDT 24
Finished Jun 27 06:10:56 PM PDT 24
Peak memory 146808 kb
Host smart-8a5716f3-b086-4455-aebb-353037de4e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171469727 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_prince_test.4171469727
Directory /workspace/16.prim_prince_test/latest

Test location /workspace/coverage/default/160.prim_prince_test.70109426
Short name T162
Test name
Test status
Simulation time 3731260556 ps
CPU time 60.05 seconds
Started Jun 27 06:11:00 PM PDT 24
Finished Jun 27 06:12:14 PM PDT 24
Peak memory 146800 kb
Host smart-7f79f525-c1a0-43e4-9874-e066c021984a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70109426 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 160.prim_prince_test.70109426
Directory /workspace/160.prim_prince_test/latest

Test location /workspace/coverage/default/161.prim_prince_test.546466387
Short name T294
Test name
Test status
Simulation time 1284726469 ps
CPU time 21.87 seconds
Started Jun 27 06:10:58 PM PDT 24
Finished Jun 27 06:11:27 PM PDT 24
Peak memory 146704 kb
Host smart-73143f50-69ab-45f5-bd3e-a779cad5179d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546466387 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 161.prim_prince_test.546466387
Directory /workspace/161.prim_prince_test/latest

Test location /workspace/coverage/default/162.prim_prince_test.23873812
Short name T351
Test name
Test status
Simulation time 1563375416 ps
CPU time 26.74 seconds
Started Jun 27 06:10:55 PM PDT 24
Finished Jun 27 06:11:29 PM PDT 24
Peak memory 146708 kb
Host smart-d34dd1d4-b923-4616-9b8b-6c8eb3e3cc57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23873812 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 162.prim_prince_test.23873812
Directory /workspace/162.prim_prince_test/latest

Test location /workspace/coverage/default/163.prim_prince_test.875999386
Short name T410
Test name
Test status
Simulation time 2029631017 ps
CPU time 34.31 seconds
Started Jun 27 06:10:54 PM PDT 24
Finished Jun 27 06:11:37 PM PDT 24
Peak memory 146736 kb
Host smart-9ec4c9f4-a8bf-4fa9-b9e4-1d764661a5cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875999386 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 163.prim_prince_test.875999386
Directory /workspace/163.prim_prince_test/latest

Test location /workspace/coverage/default/164.prim_prince_test.544807605
Short name T249
Test name
Test status
Simulation time 1256288640 ps
CPU time 21.4 seconds
Started Jun 27 06:10:54 PM PDT 24
Finished Jun 27 06:11:22 PM PDT 24
Peak memory 146732 kb
Host smart-9087de9e-d40a-4f07-b32e-6bd17ebd3bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544807605 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 164.prim_prince_test.544807605
Directory /workspace/164.prim_prince_test/latest

Test location /workspace/coverage/default/165.prim_prince_test.4220178858
Short name T240
Test name
Test status
Simulation time 1475388915 ps
CPU time 24.94 seconds
Started Jun 27 06:11:00 PM PDT 24
Finished Jun 27 06:11:33 PM PDT 24
Peak memory 146732 kb
Host smart-b561d7a0-1d55-4f44-a795-c66ef683cc4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220178858 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 165.prim_prince_test.4220178858
Directory /workspace/165.prim_prince_test/latest

Test location /workspace/coverage/default/166.prim_prince_test.722051545
Short name T158
Test name
Test status
Simulation time 2243060875 ps
CPU time 37.3 seconds
Started Jun 27 06:10:55 PM PDT 24
Finished Jun 27 06:11:42 PM PDT 24
Peak memory 146808 kb
Host smart-7a19d8b0-6a05-491b-97c4-4c0462296825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722051545 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 166.prim_prince_test.722051545
Directory /workspace/166.prim_prince_test/latest

Test location /workspace/coverage/default/167.prim_prince_test.2598112833
Short name T397
Test name
Test status
Simulation time 1202953946 ps
CPU time 19.98 seconds
Started Jun 27 06:10:55 PM PDT 24
Finished Jun 27 06:11:21 PM PDT 24
Peak memory 146736 kb
Host smart-e92ce817-a1e2-4e75-80bc-6e1ed3d22c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598112833 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 167.prim_prince_test.2598112833
Directory /workspace/167.prim_prince_test/latest

Test location /workspace/coverage/default/168.prim_prince_test.1854457694
Short name T35
Test name
Test status
Simulation time 3595499390 ps
CPU time 58.88 seconds
Started Jun 27 06:10:57 PM PDT 24
Finished Jun 27 06:12:10 PM PDT 24
Peak memory 146800 kb
Host smart-0d2650f2-086d-4f59-b619-9442953e275d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854457694 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 168.prim_prince_test.1854457694
Directory /workspace/168.prim_prince_test/latest

Test location /workspace/coverage/default/169.prim_prince_test.379432262
Short name T219
Test name
Test status
Simulation time 2432338831 ps
CPU time 39.35 seconds
Started Jun 27 06:10:53 PM PDT 24
Finished Jun 27 06:11:41 PM PDT 24
Peak memory 146880 kb
Host smart-5b38f271-b4d7-4607-9926-ba1df414f04a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379432262 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 169.prim_prince_test.379432262
Directory /workspace/169.prim_prince_test/latest

Test location /workspace/coverage/default/17.prim_prince_test.978733198
Short name T222
Test name
Test status
Simulation time 3406209406 ps
CPU time 54.95 seconds
Started Jun 27 06:10:17 PM PDT 24
Finished Jun 27 06:11:23 PM PDT 24
Peak memory 146752 kb
Host smart-1a9a81c7-9bb1-478d-a6d8-527f815d37f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978733198 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_prince_test.978733198
Directory /workspace/17.prim_prince_test/latest

Test location /workspace/coverage/default/170.prim_prince_test.3299310589
Short name T371
Test name
Test status
Simulation time 3073481472 ps
CPU time 50.5 seconds
Started Jun 27 06:10:59 PM PDT 24
Finished Jun 27 06:12:03 PM PDT 24
Peak memory 146796 kb
Host smart-78099a20-cc07-44bd-b247-8e250bfd8801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299310589 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 170.prim_prince_test.3299310589
Directory /workspace/170.prim_prince_test/latest

Test location /workspace/coverage/default/171.prim_prince_test.10183173
Short name T33
Test name
Test status
Simulation time 2097463132 ps
CPU time 33.63 seconds
Started Jun 27 06:10:56 PM PDT 24
Finished Jun 27 06:11:38 PM PDT 24
Peak memory 146720 kb
Host smart-0f6285c8-6dc8-40ca-af16-09da437e389e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10183173 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 171.prim_prince_test.10183173
Directory /workspace/171.prim_prince_test/latest

Test location /workspace/coverage/default/172.prim_prince_test.2146518049
Short name T84
Test name
Test status
Simulation time 1903306749 ps
CPU time 31.85 seconds
Started Jun 27 06:10:57 PM PDT 24
Finished Jun 27 06:11:37 PM PDT 24
Peak memory 146736 kb
Host smart-b6044bee-c692-41db-87bb-0f6f1891cb37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146518049 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 172.prim_prince_test.2146518049
Directory /workspace/172.prim_prince_test/latest

Test location /workspace/coverage/default/173.prim_prince_test.1203461060
Short name T266
Test name
Test status
Simulation time 2363494893 ps
CPU time 39.05 seconds
Started Jun 27 06:11:01 PM PDT 24
Finished Jun 27 06:11:50 PM PDT 24
Peak memory 146720 kb
Host smart-1bce7cda-a952-45b2-9ca8-ebbd832dbd69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203461060 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 173.prim_prince_test.1203461060
Directory /workspace/173.prim_prince_test/latest

Test location /workspace/coverage/default/174.prim_prince_test.1969453213
Short name T385
Test name
Test status
Simulation time 2592052793 ps
CPU time 43.34 seconds
Started Jun 27 06:10:58 PM PDT 24
Finished Jun 27 06:11:53 PM PDT 24
Peak memory 146140 kb
Host smart-f53bdb53-4fe9-46d5-934c-a03868be825c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969453213 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 174.prim_prince_test.1969453213
Directory /workspace/174.prim_prince_test/latest

Test location /workspace/coverage/default/175.prim_prince_test.1118096539
Short name T256
Test name
Test status
Simulation time 1281401502 ps
CPU time 22.35 seconds
Started Jun 27 06:10:56 PM PDT 24
Finished Jun 27 06:11:25 PM PDT 24
Peak memory 146736 kb
Host smart-1313981f-271d-427d-95ff-9b8eaa7feef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118096539 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 175.prim_prince_test.1118096539
Directory /workspace/175.prim_prince_test/latest

Test location /workspace/coverage/default/176.prim_prince_test.2474106707
Short name T113
Test name
Test status
Simulation time 1459626048 ps
CPU time 24.5 seconds
Started Jun 27 06:10:58 PM PDT 24
Finished Jun 27 06:11:29 PM PDT 24
Peak memory 146736 kb
Host smart-c2342901-6c76-4199-9f87-cfccbb500518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474106707 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 176.prim_prince_test.2474106707
Directory /workspace/176.prim_prince_test/latest

Test location /workspace/coverage/default/177.prim_prince_test.1764179305
Short name T226
Test name
Test status
Simulation time 2115782357 ps
CPU time 35.86 seconds
Started Jun 27 06:10:58 PM PDT 24
Finished Jun 27 06:11:45 PM PDT 24
Peak memory 146696 kb
Host smart-15a31bbc-80a8-40c0-b7e6-a7a59c0c8684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764179305 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 177.prim_prince_test.1764179305
Directory /workspace/177.prim_prince_test/latest

Test location /workspace/coverage/default/178.prim_prince_test.2255829354
Short name T493
Test name
Test status
Simulation time 3499277311 ps
CPU time 54.47 seconds
Started Jun 27 06:11:00 PM PDT 24
Finished Jun 27 06:12:07 PM PDT 24
Peak memory 146804 kb
Host smart-bc7ce42b-d914-4eb8-a882-32decb352ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255829354 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 178.prim_prince_test.2255829354
Directory /workspace/178.prim_prince_test/latest

Test location /workspace/coverage/default/179.prim_prince_test.1146153872
Short name T461
Test name
Test status
Simulation time 3033580319 ps
CPU time 50.26 seconds
Started Jun 27 06:11:00 PM PDT 24
Finished Jun 27 06:12:04 PM PDT 24
Peak memory 146796 kb
Host smart-ed28b854-652f-415c-b23c-199ec157bf78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146153872 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 179.prim_prince_test.1146153872
Directory /workspace/179.prim_prince_test/latest

Test location /workspace/coverage/default/18.prim_prince_test.3031240555
Short name T186
Test name
Test status
Simulation time 2358838035 ps
CPU time 39.06 seconds
Started Jun 27 06:10:15 PM PDT 24
Finished Jun 27 06:11:04 PM PDT 24
Peak memory 146752 kb
Host smart-311aebb6-3e29-408c-ad7a-31b1ce011e8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031240555 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_prince_test.3031240555
Directory /workspace/18.prim_prince_test/latest

Test location /workspace/coverage/default/180.prim_prince_test.1282117435
Short name T304
Test name
Test status
Simulation time 3493228577 ps
CPU time 58.39 seconds
Started Jun 27 06:11:00 PM PDT 24
Finished Jun 27 06:12:14 PM PDT 24
Peak memory 146796 kb
Host smart-abc1bcf7-05cc-4a6d-a7b5-99471e4e07d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282117435 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 180.prim_prince_test.1282117435
Directory /workspace/180.prim_prince_test/latest

Test location /workspace/coverage/default/181.prim_prince_test.2125799890
Short name T380
Test name
Test status
Simulation time 1628627082 ps
CPU time 27.68 seconds
Started Jun 27 06:10:58 PM PDT 24
Finished Jun 27 06:11:34 PM PDT 24
Peak memory 146700 kb
Host smart-c4b35468-b43c-4681-b008-6704078ba1b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125799890 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 181.prim_prince_test.2125799890
Directory /workspace/181.prim_prince_test/latest

Test location /workspace/coverage/default/182.prim_prince_test.63391257
Short name T94
Test name
Test status
Simulation time 974126495 ps
CPU time 16.63 seconds
Started Jun 27 06:10:56 PM PDT 24
Finished Jun 27 06:11:18 PM PDT 24
Peak memory 146740 kb
Host smart-ee237dc1-39e5-4347-80a4-f6af5af370d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63391257 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 182.prim_prince_test.63391257
Directory /workspace/182.prim_prince_test/latest

Test location /workspace/coverage/default/183.prim_prince_test.1070164656
Short name T60
Test name
Test status
Simulation time 2795784551 ps
CPU time 47.27 seconds
Started Jun 27 06:10:58 PM PDT 24
Finished Jun 27 06:11:58 PM PDT 24
Peak memory 146760 kb
Host smart-2d07ffe5-76fb-44c6-a3cd-ca6f6120d5eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070164656 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 183.prim_prince_test.1070164656
Directory /workspace/183.prim_prince_test/latest

Test location /workspace/coverage/default/184.prim_prince_test.341333842
Short name T332
Test name
Test status
Simulation time 1978585498 ps
CPU time 32.65 seconds
Started Jun 27 06:11:04 PM PDT 24
Finished Jun 27 06:11:45 PM PDT 24
Peak memory 146620 kb
Host smart-3333eb0b-db6e-41fa-8cee-76a39b75d619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341333842 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 184.prim_prince_test.341333842
Directory /workspace/184.prim_prince_test/latest

Test location /workspace/coverage/default/185.prim_prince_test.484325669
Short name T15
Test name
Test status
Simulation time 1298842983 ps
CPU time 21.43 seconds
Started Jun 27 06:11:03 PM PDT 24
Finished Jun 27 06:11:31 PM PDT 24
Peak memory 146680 kb
Host smart-28c17216-f910-470b-bbd1-477b28c57e3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484325669 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 185.prim_prince_test.484325669
Directory /workspace/185.prim_prince_test/latest

Test location /workspace/coverage/default/186.prim_prince_test.2404932706
Short name T74
Test name
Test status
Simulation time 2705251948 ps
CPU time 45.17 seconds
Started Jun 27 06:11:00 PM PDT 24
Finished Jun 27 06:11:57 PM PDT 24
Peak memory 146804 kb
Host smart-8b84635a-6a56-4c14-b475-8453ee7d237b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404932706 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 186.prim_prince_test.2404932706
Directory /workspace/186.prim_prince_test/latest

Test location /workspace/coverage/default/187.prim_prince_test.3805659950
Short name T55
Test name
Test status
Simulation time 1605729326 ps
CPU time 26.85 seconds
Started Jun 27 06:11:00 PM PDT 24
Finished Jun 27 06:11:35 PM PDT 24
Peak memory 146740 kb
Host smart-78b23ddf-cc9d-4290-b9cb-2262bfb17b6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805659950 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 187.prim_prince_test.3805659950
Directory /workspace/187.prim_prince_test/latest

Test location /workspace/coverage/default/188.prim_prince_test.1244855982
Short name T17
Test name
Test status
Simulation time 3324595203 ps
CPU time 54.43 seconds
Started Jun 27 06:11:03 PM PDT 24
Finished Jun 27 06:12:11 PM PDT 24
Peak memory 146736 kb
Host smart-756af151-d4c2-425f-af39-3e59daadf481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244855982 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 188.prim_prince_test.1244855982
Directory /workspace/188.prim_prince_test/latest

Test location /workspace/coverage/default/189.prim_prince_test.264435390
Short name T359
Test name
Test status
Simulation time 3157599127 ps
CPU time 50.42 seconds
Started Jun 27 06:11:03 PM PDT 24
Finished Jun 27 06:12:06 PM PDT 24
Peak memory 146744 kb
Host smart-b8e0b9a9-721b-45da-b474-c51e7572a99c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264435390 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 189.prim_prince_test.264435390
Directory /workspace/189.prim_prince_test/latest

Test location /workspace/coverage/default/19.prim_prince_test.3118895844
Short name T85
Test name
Test status
Simulation time 1280705501 ps
CPU time 21.24 seconds
Started Jun 27 06:10:11 PM PDT 24
Finished Jun 27 06:10:38 PM PDT 24
Peak memory 146744 kb
Host smart-e4e334a2-08a9-454b-819c-c4d3e80a9f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118895844 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_prince_test.3118895844
Directory /workspace/19.prim_prince_test/latest

Test location /workspace/coverage/default/190.prim_prince_test.4289699298
Short name T311
Test name
Test status
Simulation time 1255297754 ps
CPU time 21.37 seconds
Started Jun 27 06:11:00 PM PDT 24
Finished Jun 27 06:11:29 PM PDT 24
Peak memory 146752 kb
Host smart-4db19189-4a2c-4039-b705-eb182e3ee10f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289699298 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 190.prim_prince_test.4289699298
Directory /workspace/190.prim_prince_test/latest

Test location /workspace/coverage/default/191.prim_prince_test.3574810097
Short name T275
Test name
Test status
Simulation time 1830270704 ps
CPU time 30.97 seconds
Started Jun 27 06:11:01 PM PDT 24
Finished Jun 27 06:11:43 PM PDT 24
Peak memory 146720 kb
Host smart-0a69b03f-36b9-4b4b-95cb-969bd6237268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574810097 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 191.prim_prince_test.3574810097
Directory /workspace/191.prim_prince_test/latest

Test location /workspace/coverage/default/192.prim_prince_test.3609869276
Short name T445
Test name
Test status
Simulation time 3757313494 ps
CPU time 63 seconds
Started Jun 27 06:11:01 PM PDT 24
Finished Jun 27 06:12:24 PM PDT 24
Peak memory 146784 kb
Host smart-970de141-0725-45ed-919e-2a690e803a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609869276 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 192.prim_prince_test.3609869276
Directory /workspace/192.prim_prince_test/latest

Test location /workspace/coverage/default/193.prim_prince_test.1355385159
Short name T352
Test name
Test status
Simulation time 3419319319 ps
CPU time 56.48 seconds
Started Jun 27 06:11:04 PM PDT 24
Finished Jun 27 06:12:14 PM PDT 24
Peak memory 146616 kb
Host smart-46ca316b-7ac8-4c08-b557-134c77a57641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355385159 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 193.prim_prince_test.1355385159
Directory /workspace/193.prim_prince_test/latest

Test location /workspace/coverage/default/194.prim_prince_test.3542108203
Short name T101
Test name
Test status
Simulation time 2542019951 ps
CPU time 43.18 seconds
Started Jun 27 06:11:01 PM PDT 24
Finished Jun 27 06:11:59 PM PDT 24
Peak memory 146784 kb
Host smart-15c78c4c-3b18-43dc-899f-532b4b2f9b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542108203 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 194.prim_prince_test.3542108203
Directory /workspace/194.prim_prince_test/latest

Test location /workspace/coverage/default/195.prim_prince_test.678902466
Short name T448
Test name
Test status
Simulation time 3139105284 ps
CPU time 52.64 seconds
Started Jun 27 06:11:02 PM PDT 24
Finished Jun 27 06:12:08 PM PDT 24
Peak memory 146804 kb
Host smart-4806d374-d2aa-4ca2-b86c-0114a1f8c7e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678902466 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 195.prim_prince_test.678902466
Directory /workspace/195.prim_prince_test/latest

Test location /workspace/coverage/default/196.prim_prince_test.1516685431
Short name T8
Test name
Test status
Simulation time 1812543878 ps
CPU time 29.41 seconds
Started Jun 27 06:11:04 PM PDT 24
Finished Jun 27 06:11:41 PM PDT 24
Peak memory 146732 kb
Host smart-4a753b79-a333-411d-b4e5-e31188468d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516685431 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 196.prim_prince_test.1516685431
Directory /workspace/196.prim_prince_test/latest

Test location /workspace/coverage/default/197.prim_prince_test.263141084
Short name T77
Test name
Test status
Simulation time 3438939875 ps
CPU time 56.65 seconds
Started Jun 27 06:11:04 PM PDT 24
Finished Jun 27 06:12:14 PM PDT 24
Peak memory 146804 kb
Host smart-b05feb33-a7ad-466e-8e4d-749c0f6e3f3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263141084 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 197.prim_prince_test.263141084
Directory /workspace/197.prim_prince_test/latest

Test location /workspace/coverage/default/198.prim_prince_test.4126444997
Short name T337
Test name
Test status
Simulation time 2183418321 ps
CPU time 36.28 seconds
Started Jun 27 06:11:04 PM PDT 24
Finished Jun 27 06:11:50 PM PDT 24
Peak memory 146796 kb
Host smart-9c6f3940-6c0d-45ab-945f-a452dde2515b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126444997 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 198.prim_prince_test.4126444997
Directory /workspace/198.prim_prince_test/latest

Test location /workspace/coverage/default/199.prim_prince_test.2181451241
Short name T388
Test name
Test status
Simulation time 2875439062 ps
CPU time 47.94 seconds
Started Jun 27 06:11:01 PM PDT 24
Finished Jun 27 06:12:02 PM PDT 24
Peak memory 146796 kb
Host smart-213ead5a-9f8b-43bf-8d84-417f9deb5eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181451241 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 199.prim_prince_test.2181451241
Directory /workspace/199.prim_prince_test/latest

Test location /workspace/coverage/default/2.prim_prince_test.1772893537
Short name T40
Test name
Test status
Simulation time 3109093034 ps
CPU time 51.34 seconds
Started Jun 27 06:10:06 PM PDT 24
Finished Jun 27 06:11:10 PM PDT 24
Peak memory 146720 kb
Host smart-a616dacf-8fa3-490d-a52a-5104837ab4cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772893537 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_prince_test.1772893537
Directory /workspace/2.prim_prince_test/latest

Test location /workspace/coverage/default/20.prim_prince_test.2355243886
Short name T382
Test name
Test status
Simulation time 1616309459 ps
CPU time 27.99 seconds
Started Jun 27 06:10:11 PM PDT 24
Finished Jun 27 06:10:47 PM PDT 24
Peak memory 146748 kb
Host smart-ca4c05ed-2328-49cd-a93c-8922cfee41d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355243886 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_prince_test.2355243886
Directory /workspace/20.prim_prince_test/latest

Test location /workspace/coverage/default/200.prim_prince_test.1446296149
Short name T421
Test name
Test status
Simulation time 2975867094 ps
CPU time 50.59 seconds
Started Jun 27 06:11:00 PM PDT 24
Finished Jun 27 06:12:08 PM PDT 24
Peak memory 146784 kb
Host smart-00b55af8-3d53-4048-8a10-fb567ea324f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446296149 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 200.prim_prince_test.1446296149
Directory /workspace/200.prim_prince_test/latest

Test location /workspace/coverage/default/201.prim_prince_test.1796596477
Short name T41
Test name
Test status
Simulation time 826203641 ps
CPU time 14.11 seconds
Started Jun 27 06:11:02 PM PDT 24
Finished Jun 27 06:11:22 PM PDT 24
Peak memory 146732 kb
Host smart-01c0b81d-3647-407e-8a52-422e46921b6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796596477 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 201.prim_prince_test.1796596477
Directory /workspace/201.prim_prince_test/latest

Test location /workspace/coverage/default/202.prim_prince_test.3193933622
Short name T20
Test name
Test status
Simulation time 2225239486 ps
CPU time 37.48 seconds
Started Jun 27 06:11:03 PM PDT 24
Finished Jun 27 06:11:51 PM PDT 24
Peak memory 146800 kb
Host smart-3a063c31-b50b-4aab-9d7c-8a512404cbff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193933622 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 202.prim_prince_test.3193933622
Directory /workspace/202.prim_prince_test/latest

Test location /workspace/coverage/default/203.prim_prince_test.222352556
Short name T24
Test name
Test status
Simulation time 3365119662 ps
CPU time 57.17 seconds
Started Jun 27 06:11:01 PM PDT 24
Finished Jun 27 06:12:16 PM PDT 24
Peak memory 146792 kb
Host smart-29e6e81c-1cb1-4054-9488-5eefe1464a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222352556 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 203.prim_prince_test.222352556
Directory /workspace/203.prim_prince_test/latest

Test location /workspace/coverage/default/204.prim_prince_test.306114800
Short name T273
Test name
Test status
Simulation time 2771529403 ps
CPU time 45.77 seconds
Started Jun 27 06:10:57 PM PDT 24
Finished Jun 27 06:11:54 PM PDT 24
Peak memory 146808 kb
Host smart-df3f88f5-6353-4f85-8284-e817cd3e5465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306114800 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 204.prim_prince_test.306114800
Directory /workspace/204.prim_prince_test/latest

Test location /workspace/coverage/default/205.prim_prince_test.815140163
Short name T495
Test name
Test status
Simulation time 2939120502 ps
CPU time 48.93 seconds
Started Jun 27 06:11:04 PM PDT 24
Finished Jun 27 06:12:06 PM PDT 24
Peak memory 146808 kb
Host smart-64c905d3-42d5-4808-8e1c-a700ac2c208f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815140163 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 205.prim_prince_test.815140163
Directory /workspace/205.prim_prince_test/latest

Test location /workspace/coverage/default/206.prim_prince_test.3966745507
Short name T239
Test name
Test status
Simulation time 1576441915 ps
CPU time 26.15 seconds
Started Jun 27 06:11:04 PM PDT 24
Finished Jun 27 06:11:37 PM PDT 24
Peak memory 146744 kb
Host smart-910b35d2-f285-479e-a561-1de38ae8335e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966745507 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 206.prim_prince_test.3966745507
Directory /workspace/206.prim_prince_test/latest

Test location /workspace/coverage/default/207.prim_prince_test.474564716
Short name T433
Test name
Test status
Simulation time 2569126677 ps
CPU time 42.94 seconds
Started Jun 27 06:11:03 PM PDT 24
Finished Jun 27 06:11:57 PM PDT 24
Peak memory 146804 kb
Host smart-26242857-2b70-42e2-acb1-15d18c6270a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474564716 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 207.prim_prince_test.474564716
Directory /workspace/207.prim_prince_test/latest

Test location /workspace/coverage/default/208.prim_prince_test.4206540575
Short name T274
Test name
Test status
Simulation time 3588678782 ps
CPU time 59.9 seconds
Started Jun 27 06:11:04 PM PDT 24
Finished Jun 27 06:12:19 PM PDT 24
Peak memory 146796 kb
Host smart-deb73d80-e31d-4cbd-a231-b9fed37c7075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206540575 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 208.prim_prince_test.4206540575
Directory /workspace/208.prim_prince_test/latest

Test location /workspace/coverage/default/209.prim_prince_test.3449071933
Short name T197
Test name
Test status
Simulation time 2468421396 ps
CPU time 41.61 seconds
Started Jun 27 06:11:04 PM PDT 24
Finished Jun 27 06:11:57 PM PDT 24
Peak memory 146812 kb
Host smart-1ca3e20d-d1f0-48dc-bd54-c4a9101ffc5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449071933 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 209.prim_prince_test.3449071933
Directory /workspace/209.prim_prince_test/latest

Test location /workspace/coverage/default/21.prim_prince_test.2028746207
Short name T412
Test name
Test status
Simulation time 1298209087 ps
CPU time 21.84 seconds
Started Jun 27 06:10:17 PM PDT 24
Finished Jun 27 06:10:44 PM PDT 24
Peak memory 146748 kb
Host smart-8b9e7634-a578-4115-b482-eda354939e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028746207 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_prince_test.2028746207
Directory /workspace/21.prim_prince_test/latest

Test location /workspace/coverage/default/210.prim_prince_test.3486773653
Short name T105
Test name
Test status
Simulation time 3086088546 ps
CPU time 52.47 seconds
Started Jun 27 06:10:58 PM PDT 24
Finished Jun 27 06:12:05 PM PDT 24
Peak memory 146768 kb
Host smart-826100a4-a4e9-4200-b3fe-9159fd652247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486773653 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 210.prim_prince_test.3486773653
Directory /workspace/210.prim_prince_test/latest

Test location /workspace/coverage/default/211.prim_prince_test.1797996022
Short name T434
Test name
Test status
Simulation time 1889884610 ps
CPU time 31.84 seconds
Started Jun 27 06:11:04 PM PDT 24
Finished Jun 27 06:11:45 PM PDT 24
Peak memory 146736 kb
Host smart-836ab0f7-0c97-4d92-bd82-0039beb9ef3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797996022 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 211.prim_prince_test.1797996022
Directory /workspace/211.prim_prince_test/latest

Test location /workspace/coverage/default/212.prim_prince_test.2442489484
Short name T285
Test name
Test status
Simulation time 3104622364 ps
CPU time 52.71 seconds
Started Jun 27 06:11:02 PM PDT 24
Finished Jun 27 06:12:10 PM PDT 24
Peak memory 146784 kb
Host smart-5938fabc-dc93-4035-b962-28abe95fa174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442489484 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 212.prim_prince_test.2442489484
Directory /workspace/212.prim_prince_test/latest

Test location /workspace/coverage/default/213.prim_prince_test.4111555051
Short name T149
Test name
Test status
Simulation time 1429692124 ps
CPU time 24.16 seconds
Started Jun 27 06:11:02 PM PDT 24
Finished Jun 27 06:11:34 PM PDT 24
Peak memory 146732 kb
Host smart-fabcab72-1d50-4546-8b19-e991d5b6183b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111555051 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 213.prim_prince_test.4111555051
Directory /workspace/213.prim_prince_test/latest

Test location /workspace/coverage/default/214.prim_prince_test.3784637552
Short name T9
Test name
Test status
Simulation time 857346224 ps
CPU time 14.68 seconds
Started Jun 27 06:11:04 PM PDT 24
Finished Jun 27 06:11:24 PM PDT 24
Peak memory 146736 kb
Host smart-f7fdd6fe-cb9d-4423-9c12-9e9fa815b2b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784637552 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 214.prim_prince_test.3784637552
Directory /workspace/214.prim_prince_test/latest

Test location /workspace/coverage/default/215.prim_prince_test.1074290017
Short name T128
Test name
Test status
Simulation time 1224108225 ps
CPU time 20.36 seconds
Started Jun 27 06:11:03 PM PDT 24
Finished Jun 27 06:11:30 PM PDT 24
Peak memory 146736 kb
Host smart-2f49d6c2-f49d-4cbc-8856-daf81c0e2744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074290017 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 215.prim_prince_test.1074290017
Directory /workspace/215.prim_prince_test/latest

Test location /workspace/coverage/default/216.prim_prince_test.1541273116
Short name T108
Test name
Test status
Simulation time 1226325010 ps
CPU time 20.85 seconds
Started Jun 27 06:11:03 PM PDT 24
Finished Jun 27 06:11:31 PM PDT 24
Peak memory 146720 kb
Host smart-eb3c3186-ee62-492b-9713-117e731ca09f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541273116 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 216.prim_prince_test.1541273116
Directory /workspace/216.prim_prince_test/latest

Test location /workspace/coverage/default/217.prim_prince_test.4264955681
Short name T315
Test name
Test status
Simulation time 1305507858 ps
CPU time 22.39 seconds
Started Jun 27 06:10:59 PM PDT 24
Finished Jun 27 06:11:29 PM PDT 24
Peak memory 146696 kb
Host smart-6038cb6f-5858-483f-96f0-879de4a7ee62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264955681 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 217.prim_prince_test.4264955681
Directory /workspace/217.prim_prince_test/latest

Test location /workspace/coverage/default/218.prim_prince_test.2348190828
Short name T142
Test name
Test status
Simulation time 3694710795 ps
CPU time 61.53 seconds
Started Jun 27 06:11:02 PM PDT 24
Finished Jun 27 06:12:19 PM PDT 24
Peak memory 146796 kb
Host smart-68ddc7fa-23f7-45c5-8362-ab2d25b33746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348190828 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 218.prim_prince_test.2348190828
Directory /workspace/218.prim_prince_test/latest

Test location /workspace/coverage/default/219.prim_prince_test.3298905459
Short name T232
Test name
Test status
Simulation time 2240297851 ps
CPU time 38.01 seconds
Started Jun 27 06:10:57 PM PDT 24
Finished Jun 27 06:11:46 PM PDT 24
Peak memory 146792 kb
Host smart-0cbf3315-e9ca-40bd-8020-3ea172a90b40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298905459 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 219.prim_prince_test.3298905459
Directory /workspace/219.prim_prince_test/latest

Test location /workspace/coverage/default/22.prim_prince_test.2140628014
Short name T334
Test name
Test status
Simulation time 1393432620 ps
CPU time 22.9 seconds
Started Jun 27 06:10:17 PM PDT 24
Finished Jun 27 06:10:46 PM PDT 24
Peak memory 146700 kb
Host smart-207cef9f-1b66-41c7-a768-c46dbfd59ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140628014 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_prince_test.2140628014
Directory /workspace/22.prim_prince_test/latest

Test location /workspace/coverage/default/220.prim_prince_test.150067159
Short name T336
Test name
Test status
Simulation time 1782019142 ps
CPU time 30.39 seconds
Started Jun 27 06:11:03 PM PDT 24
Finished Jun 27 06:11:43 PM PDT 24
Peak memory 146728 kb
Host smart-701f6c20-a260-4207-86e0-c4f760a6f2d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150067159 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 220.prim_prince_test.150067159
Directory /workspace/220.prim_prince_test/latest

Test location /workspace/coverage/default/221.prim_prince_test.65469009
Short name T347
Test name
Test status
Simulation time 2319751742 ps
CPU time 38.98 seconds
Started Jun 27 06:11:02 PM PDT 24
Finished Jun 27 06:11:53 PM PDT 24
Peak memory 146780 kb
Host smart-40812a4c-af2b-4d40-bdeb-ec99d6275b5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65469009 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 221.prim_prince_test.65469009
Directory /workspace/221.prim_prince_test/latest

Test location /workspace/coverage/default/222.prim_prince_test.3978920427
Short name T237
Test name
Test status
Simulation time 2202121937 ps
CPU time 36.55 seconds
Started Jun 27 06:11:02 PM PDT 24
Finished Jun 27 06:11:49 PM PDT 24
Peak memory 146784 kb
Host smart-05c23049-1574-488b-b74f-60d4c2ed1cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978920427 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 222.prim_prince_test.3978920427
Directory /workspace/222.prim_prince_test/latest

Test location /workspace/coverage/default/223.prim_prince_test.1927037989
Short name T480
Test name
Test status
Simulation time 1685186849 ps
CPU time 27.27 seconds
Started Jun 27 06:10:57 PM PDT 24
Finished Jun 27 06:11:32 PM PDT 24
Peak memory 146720 kb
Host smart-a39c6a4d-a641-4770-85fd-d20b1c6d53ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927037989 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 223.prim_prince_test.1927037989
Directory /workspace/223.prim_prince_test/latest

Test location /workspace/coverage/default/224.prim_prince_test.3213902465
Short name T54
Test name
Test status
Simulation time 3645107870 ps
CPU time 58.88 seconds
Started Jun 27 06:11:03 PM PDT 24
Finished Jun 27 06:12:16 PM PDT 24
Peak memory 146736 kb
Host smart-066a6088-83b7-445c-9318-01f9ac91d89b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213902465 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 224.prim_prince_test.3213902465
Directory /workspace/224.prim_prince_test/latest

Test location /workspace/coverage/default/225.prim_prince_test.3438563235
Short name T204
Test name
Test status
Simulation time 794399507 ps
CPU time 13.33 seconds
Started Jun 27 06:10:59 PM PDT 24
Finished Jun 27 06:11:18 PM PDT 24
Peak memory 146736 kb
Host smart-f6e96b92-09ca-4d13-ad25-58423008a453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438563235 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 225.prim_prince_test.3438563235
Directory /workspace/225.prim_prince_test/latest

Test location /workspace/coverage/default/226.prim_prince_test.2348128506
Short name T66
Test name
Test status
Simulation time 2070315643 ps
CPU time 35.83 seconds
Started Jun 27 06:10:55 PM PDT 24
Finished Jun 27 06:11:42 PM PDT 24
Peak memory 146720 kb
Host smart-67518daf-33af-4f4b-a505-e9207f149389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348128506 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 226.prim_prince_test.2348128506
Directory /workspace/226.prim_prince_test/latest

Test location /workspace/coverage/default/227.prim_prince_test.1328309566
Short name T169
Test name
Test status
Simulation time 3667290179 ps
CPU time 61.8 seconds
Started Jun 27 06:10:58 PM PDT 24
Finished Jun 27 06:12:16 PM PDT 24
Peak memory 146732 kb
Host smart-b974111e-80f6-442c-a922-4b5f12292aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328309566 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 227.prim_prince_test.1328309566
Directory /workspace/227.prim_prince_test/latest

Test location /workspace/coverage/default/228.prim_prince_test.332081930
Short name T28
Test name
Test status
Simulation time 1390301123 ps
CPU time 23.31 seconds
Started Jun 27 06:11:01 PM PDT 24
Finished Jun 27 06:11:31 PM PDT 24
Peak memory 146664 kb
Host smart-716663ff-9ab5-4a92-aa21-58d161b9c2ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332081930 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 228.prim_prince_test.332081930
Directory /workspace/228.prim_prince_test/latest

Test location /workspace/coverage/default/229.prim_prince_test.657341446
Short name T422
Test name
Test status
Simulation time 900456245 ps
CPU time 15.22 seconds
Started Jun 27 06:11:01 PM PDT 24
Finished Jun 27 06:11:22 PM PDT 24
Peak memory 146664 kb
Host smart-fc7337cc-4c09-45bf-8f76-ec72e6f5082b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657341446 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 229.prim_prince_test.657341446
Directory /workspace/229.prim_prince_test/latest

Test location /workspace/coverage/default/23.prim_prince_test.4212783098
Short name T153
Test name
Test status
Simulation time 2418995234 ps
CPU time 38.33 seconds
Started Jun 27 06:10:09 PM PDT 24
Finished Jun 27 06:10:55 PM PDT 24
Peak memory 146744 kb
Host smart-6b10c4a6-35ba-424c-93fe-7ccee60007ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212783098 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_prince_test.4212783098
Directory /workspace/23.prim_prince_test/latest

Test location /workspace/coverage/default/230.prim_prince_test.567938607
Short name T88
Test name
Test status
Simulation time 1828190765 ps
CPU time 31.14 seconds
Started Jun 27 06:10:58 PM PDT 24
Finished Jun 27 06:11:39 PM PDT 24
Peak memory 146676 kb
Host smart-4f12b468-79d5-437a-a83d-1609ba223746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567938607 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 230.prim_prince_test.567938607
Directory /workspace/230.prim_prince_test/latest

Test location /workspace/coverage/default/231.prim_prince_test.604019613
Short name T123
Test name
Test status
Simulation time 2922251065 ps
CPU time 48.93 seconds
Started Jun 27 06:11:00 PM PDT 24
Finished Jun 27 06:12:02 PM PDT 24
Peak memory 146780 kb
Host smart-87a2e5a3-064c-47b6-8b46-87dbf67a7ccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604019613 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 231.prim_prince_test.604019613
Directory /workspace/231.prim_prince_test/latest

Test location /workspace/coverage/default/232.prim_prince_test.3603757880
Short name T49
Test name
Test status
Simulation time 2183718414 ps
CPU time 36.79 seconds
Started Jun 27 06:10:57 PM PDT 24
Finished Jun 27 06:11:44 PM PDT 24
Peak memory 146732 kb
Host smart-6cef5a17-b803-471e-958a-52a949184ccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603757880 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 232.prim_prince_test.3603757880
Directory /workspace/232.prim_prince_test/latest

Test location /workspace/coverage/default/233.prim_prince_test.3994283738
Short name T181
Test name
Test status
Simulation time 1920702542 ps
CPU time 32.27 seconds
Started Jun 27 06:10:57 PM PDT 24
Finished Jun 27 06:11:38 PM PDT 24
Peak memory 146736 kb
Host smart-5dc7317d-a1fd-4e9c-a9dd-1a6dc6837652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994283738 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 233.prim_prince_test.3994283738
Directory /workspace/233.prim_prince_test/latest

Test location /workspace/coverage/default/234.prim_prince_test.3623448945
Short name T335
Test name
Test status
Simulation time 843072481 ps
CPU time 14.18 seconds
Started Jun 27 06:11:00 PM PDT 24
Finished Jun 27 06:11:19 PM PDT 24
Peak memory 146740 kb
Host smart-f7929f4c-ecd9-46ae-853f-8de0bd70bc80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623448945 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 234.prim_prince_test.3623448945
Directory /workspace/234.prim_prince_test/latest

Test location /workspace/coverage/default/235.prim_prince_test.1603224330
Short name T328
Test name
Test status
Simulation time 3591070665 ps
CPU time 59.74 seconds
Started Jun 27 06:11:00 PM PDT 24
Finished Jun 27 06:12:16 PM PDT 24
Peak memory 146804 kb
Host smart-ee0852a5-d538-4b80-80a2-16936ed74de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603224330 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 235.prim_prince_test.1603224330
Directory /workspace/235.prim_prince_test/latest

Test location /workspace/coverage/default/236.prim_prince_test.3472005310
Short name T362
Test name
Test status
Simulation time 2169495245 ps
CPU time 37.21 seconds
Started Jun 27 06:11:09 PM PDT 24
Finished Jun 27 06:11:58 PM PDT 24
Peak memory 146804 kb
Host smart-6b4d9055-f99f-48b1-91ec-a6a0ddd55a3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472005310 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 236.prim_prince_test.3472005310
Directory /workspace/236.prim_prince_test/latest

Test location /workspace/coverage/default/237.prim_prince_test.1859518762
Short name T441
Test name
Test status
Simulation time 2873845972 ps
CPU time 48.54 seconds
Started Jun 27 06:11:09 PM PDT 24
Finished Jun 27 06:12:09 PM PDT 24
Peak memory 146792 kb
Host smart-bf017a50-f476-4214-a3b4-24d14e731139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859518762 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 237.prim_prince_test.1859518762
Directory /workspace/237.prim_prince_test/latest

Test location /workspace/coverage/default/238.prim_prince_test.3016435841
Short name T2
Test name
Test status
Simulation time 1856511545 ps
CPU time 31.13 seconds
Started Jun 27 06:11:09 PM PDT 24
Finished Jun 27 06:11:48 PM PDT 24
Peak memory 146748 kb
Host smart-52b03104-32b4-4646-9251-5bd2b8eff422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016435841 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 238.prim_prince_test.3016435841
Directory /workspace/238.prim_prince_test/latest

Test location /workspace/coverage/default/239.prim_prince_test.3666233816
Short name T31
Test name
Test status
Simulation time 2023780957 ps
CPU time 33.57 seconds
Started Jun 27 06:11:18 PM PDT 24
Finished Jun 27 06:12:01 PM PDT 24
Peak memory 146732 kb
Host smart-bd01c254-fea5-4152-b70b-06ae3a5324f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666233816 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 239.prim_prince_test.3666233816
Directory /workspace/239.prim_prince_test/latest

Test location /workspace/coverage/default/24.prim_prince_test.1744978443
Short name T484
Test name
Test status
Simulation time 3332839725 ps
CPU time 54.53 seconds
Started Jun 27 06:10:11 PM PDT 24
Finished Jun 27 06:11:17 PM PDT 24
Peak memory 146804 kb
Host smart-40fac666-0b1c-43a1-9707-b579807168cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744978443 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_prince_test.1744978443
Directory /workspace/24.prim_prince_test/latest

Test location /workspace/coverage/default/240.prim_prince_test.774855761
Short name T68
Test name
Test status
Simulation time 2558966533 ps
CPU time 42.92 seconds
Started Jun 27 06:11:09 PM PDT 24
Finished Jun 27 06:12:03 PM PDT 24
Peak memory 146796 kb
Host smart-1342f95b-d653-452b-9d3f-0f33cb86a34b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774855761 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 240.prim_prince_test.774855761
Directory /workspace/240.prim_prince_test/latest

Test location /workspace/coverage/default/241.prim_prince_test.528551533
Short name T406
Test name
Test status
Simulation time 1977608510 ps
CPU time 32.63 seconds
Started Jun 27 06:11:08 PM PDT 24
Finished Jun 27 06:11:49 PM PDT 24
Peak memory 146728 kb
Host smart-35665803-6413-4e3b-ba20-448caec85219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528551533 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 241.prim_prince_test.528551533
Directory /workspace/241.prim_prince_test/latest

Test location /workspace/coverage/default/242.prim_prince_test.1020204782
Short name T326
Test name
Test status
Simulation time 1906654187 ps
CPU time 31.33 seconds
Started Jun 27 06:11:09 PM PDT 24
Finished Jun 27 06:11:48 PM PDT 24
Peak memory 146736 kb
Host smart-d09a0779-a7a0-4e19-bc51-985bdef0be06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020204782 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 242.prim_prince_test.1020204782
Directory /workspace/242.prim_prince_test/latest

Test location /workspace/coverage/default/243.prim_prince_test.3936096280
Short name T196
Test name
Test status
Simulation time 3029620145 ps
CPU time 49.65 seconds
Started Jun 27 06:11:17 PM PDT 24
Finished Jun 27 06:12:19 PM PDT 24
Peak memory 146596 kb
Host smart-3d2c3203-2ccd-4d93-afb6-f1868b2154cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936096280 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 243.prim_prince_test.3936096280
Directory /workspace/243.prim_prince_test/latest

Test location /workspace/coverage/default/244.prim_prince_test.270805489
Short name T227
Test name
Test status
Simulation time 2115025170 ps
CPU time 34.61 seconds
Started Jun 27 06:11:19 PM PDT 24
Finished Jun 27 06:12:03 PM PDT 24
Peak memory 146724 kb
Host smart-0d500edb-6f7b-45e5-9b11-8a273b97d079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270805489 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 244.prim_prince_test.270805489
Directory /workspace/244.prim_prince_test/latest

Test location /workspace/coverage/default/245.prim_prince_test.2629332941
Short name T469
Test name
Test status
Simulation time 1264511839 ps
CPU time 21.11 seconds
Started Jun 27 06:11:11 PM PDT 24
Finished Jun 27 06:11:38 PM PDT 24
Peak memory 146720 kb
Host smart-a6ac5eae-beed-4a68-80bc-f16b04b69356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629332941 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 245.prim_prince_test.2629332941
Directory /workspace/245.prim_prince_test/latest

Test location /workspace/coverage/default/246.prim_prince_test.3172309657
Short name T424
Test name
Test status
Simulation time 1772933836 ps
CPU time 28.83 seconds
Started Jun 27 06:11:12 PM PDT 24
Finished Jun 27 06:11:48 PM PDT 24
Peak memory 146736 kb
Host smart-d230a051-2cf6-40b6-9e36-c96dc5173251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172309657 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 246.prim_prince_test.3172309657
Directory /workspace/246.prim_prince_test/latest

Test location /workspace/coverage/default/247.prim_prince_test.529292962
Short name T466
Test name
Test status
Simulation time 1661930174 ps
CPU time 27.18 seconds
Started Jun 27 06:11:11 PM PDT 24
Finished Jun 27 06:11:44 PM PDT 24
Peak memory 146748 kb
Host smart-39aa72dd-bb37-40c2-bdc2-698b10426f95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529292962 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 247.prim_prince_test.529292962
Directory /workspace/247.prim_prince_test/latest

Test location /workspace/coverage/default/248.prim_prince_test.3575901452
Short name T314
Test name
Test status
Simulation time 3699505798 ps
CPU time 62.7 seconds
Started Jun 27 06:11:09 PM PDT 24
Finished Jun 27 06:12:27 PM PDT 24
Peak memory 146808 kb
Host smart-69a7ce12-b0e7-41d2-a835-93843ad8c765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575901452 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 248.prim_prince_test.3575901452
Directory /workspace/248.prim_prince_test/latest

Test location /workspace/coverage/default/249.prim_prince_test.2472169418
Short name T500
Test name
Test status
Simulation time 1714447640 ps
CPU time 28.54 seconds
Started Jun 27 06:11:18 PM PDT 24
Finished Jun 27 06:11:54 PM PDT 24
Peak memory 146732 kb
Host smart-8abe361b-b4d1-4102-8a7e-72ff52a749d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472169418 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 249.prim_prince_test.2472169418
Directory /workspace/249.prim_prince_test/latest

Test location /workspace/coverage/default/25.prim_prince_test.3891544588
Short name T376
Test name
Test status
Simulation time 3202136566 ps
CPU time 52.66 seconds
Started Jun 27 06:10:16 PM PDT 24
Finished Jun 27 06:11:20 PM PDT 24
Peak memory 146804 kb
Host smart-a743adc5-ef6d-4dac-a634-ca33c733472f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891544588 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_prince_test.3891544588
Directory /workspace/25.prim_prince_test/latest

Test location /workspace/coverage/default/250.prim_prince_test.3231596292
Short name T381
Test name
Test status
Simulation time 754725298 ps
CPU time 13.23 seconds
Started Jun 27 06:11:09 PM PDT 24
Finished Jun 27 06:11:26 PM PDT 24
Peak memory 146684 kb
Host smart-5c81f870-197b-4c81-8603-6c9d06f0a9d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231596292 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 250.prim_prince_test.3231596292
Directory /workspace/250.prim_prince_test/latest

Test location /workspace/coverage/default/251.prim_prince_test.815949122
Short name T10
Test name
Test status
Simulation time 1264625125 ps
CPU time 21.27 seconds
Started Jun 27 06:11:10 PM PDT 24
Finished Jun 27 06:11:37 PM PDT 24
Peak memory 146744 kb
Host smart-226250c6-557d-440f-970a-70027c098978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815949122 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 251.prim_prince_test.815949122
Directory /workspace/251.prim_prince_test/latest

Test location /workspace/coverage/default/252.prim_prince_test.825084706
Short name T357
Test name
Test status
Simulation time 2503249601 ps
CPU time 41.28 seconds
Started Jun 27 06:11:17 PM PDT 24
Finished Jun 27 06:12:09 PM PDT 24
Peak memory 146764 kb
Host smart-515419d2-0290-4b50-9ea7-fd24e3c3dee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825084706 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 252.prim_prince_test.825084706
Directory /workspace/252.prim_prince_test/latest

Test location /workspace/coverage/default/253.prim_prince_test.873242732
Short name T103
Test name
Test status
Simulation time 2808244748 ps
CPU time 45.32 seconds
Started Jun 27 06:11:09 PM PDT 24
Finished Jun 27 06:12:05 PM PDT 24
Peak memory 146764 kb
Host smart-3c0bbc25-b722-4f34-9ada-3c95a5b2766f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873242732 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 253.prim_prince_test.873242732
Directory /workspace/253.prim_prince_test/latest

Test location /workspace/coverage/default/254.prim_prince_test.1416909916
Short name T179
Test name
Test status
Simulation time 1663543058 ps
CPU time 27.77 seconds
Started Jun 27 06:11:18 PM PDT 24
Finished Jun 27 06:11:53 PM PDT 24
Peak memory 146732 kb
Host smart-5dc53c09-f0e6-41ac-bbb7-02ccb7c5bab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416909916 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 254.prim_prince_test.1416909916
Directory /workspace/254.prim_prince_test/latest

Test location /workspace/coverage/default/255.prim_prince_test.829506575
Short name T492
Test name
Test status
Simulation time 3081351775 ps
CPU time 47.33 seconds
Started Jun 27 06:11:10 PM PDT 24
Finished Jun 27 06:12:06 PM PDT 24
Peak memory 146812 kb
Host smart-33de0fc2-7574-42ae-80e0-6d8bdd845f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829506575 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 255.prim_prince_test.829506575
Directory /workspace/255.prim_prince_test/latest

Test location /workspace/coverage/default/256.prim_prince_test.2329693903
Short name T407
Test name
Test status
Simulation time 1779480326 ps
CPU time 30 seconds
Started Jun 27 06:11:12 PM PDT 24
Finished Jun 27 06:11:49 PM PDT 24
Peak memory 146656 kb
Host smart-79ff4b74-d95e-49e6-a361-081d289bba0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329693903 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 256.prim_prince_test.2329693903
Directory /workspace/256.prim_prince_test/latest

Test location /workspace/coverage/default/257.prim_prince_test.1016631326
Short name T79
Test name
Test status
Simulation time 2483308448 ps
CPU time 40.59 seconds
Started Jun 27 06:11:16 PM PDT 24
Finished Jun 27 06:12:07 PM PDT 24
Peak memory 146756 kb
Host smart-5add4faf-4275-4dce-9f6f-b0d622bb218e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016631326 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 257.prim_prince_test.1016631326
Directory /workspace/257.prim_prince_test/latest

Test location /workspace/coverage/default/258.prim_prince_test.1353004179
Short name T62
Test name
Test status
Simulation time 2174274137 ps
CPU time 33.93 seconds
Started Jun 27 06:11:11 PM PDT 24
Finished Jun 27 06:11:51 PM PDT 24
Peak memory 146804 kb
Host smart-5aad68b7-9993-4fc4-8778-f7db4624fc38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353004179 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 258.prim_prince_test.1353004179
Directory /workspace/258.prim_prince_test/latest

Test location /workspace/coverage/default/259.prim_prince_test.2140342961
Short name T164
Test name
Test status
Simulation time 1297383597 ps
CPU time 21.21 seconds
Started Jun 27 06:11:09 PM PDT 24
Finished Jun 27 06:11:36 PM PDT 24
Peak memory 146736 kb
Host smart-6c9df97c-c31a-4ed1-b880-92dd03e0974a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140342961 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 259.prim_prince_test.2140342961
Directory /workspace/259.prim_prince_test/latest

Test location /workspace/coverage/default/26.prim_prince_test.1702262817
Short name T313
Test name
Test status
Simulation time 821523513 ps
CPU time 13.74 seconds
Started Jun 27 06:10:16 PM PDT 24
Finished Jun 27 06:10:33 PM PDT 24
Peak memory 146740 kb
Host smart-5c2c0117-3d8f-46cb-9ce9-312043464f77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702262817 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_prince_test.1702262817
Directory /workspace/26.prim_prince_test/latest

Test location /workspace/coverage/default/260.prim_prince_test.1026827856
Short name T365
Test name
Test status
Simulation time 3477379638 ps
CPU time 57.92 seconds
Started Jun 27 06:11:18 PM PDT 24
Finished Jun 27 06:12:30 PM PDT 24
Peak memory 146796 kb
Host smart-c01d711e-a958-4427-a6bf-25a3812c1c63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026827856 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 260.prim_prince_test.1026827856
Directory /workspace/260.prim_prince_test/latest

Test location /workspace/coverage/default/261.prim_prince_test.4117276369
Short name T16
Test name
Test status
Simulation time 811767573 ps
CPU time 13.61 seconds
Started Jun 27 06:11:12 PM PDT 24
Finished Jun 27 06:11:30 PM PDT 24
Peak memory 146736 kb
Host smart-761a2ab4-71c6-4095-a06b-92f1c8d81bae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117276369 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 261.prim_prince_test.4117276369
Directory /workspace/261.prim_prince_test/latest

Test location /workspace/coverage/default/262.prim_prince_test.626157848
Short name T467
Test name
Test status
Simulation time 2114974149 ps
CPU time 35.16 seconds
Started Jun 27 06:11:17 PM PDT 24
Finished Jun 27 06:12:02 PM PDT 24
Peak memory 146700 kb
Host smart-6c24ea9c-1005-47de-929c-5891f0a2ff89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626157848 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 262.prim_prince_test.626157848
Directory /workspace/262.prim_prince_test/latest

Test location /workspace/coverage/default/263.prim_prince_test.2147806782
Short name T172
Test name
Test status
Simulation time 1697040972 ps
CPU time 27.87 seconds
Started Jun 27 06:11:12 PM PDT 24
Finished Jun 27 06:11:47 PM PDT 24
Peak memory 146736 kb
Host smart-211f72be-1d52-44a5-a7b9-20434ca07e8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147806782 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 263.prim_prince_test.2147806782
Directory /workspace/263.prim_prince_test/latest

Test location /workspace/coverage/default/264.prim_prince_test.125740188
Short name T145
Test name
Test status
Simulation time 2649364515 ps
CPU time 44.46 seconds
Started Jun 27 06:11:13 PM PDT 24
Finished Jun 27 06:12:07 PM PDT 24
Peak memory 146812 kb
Host smart-16f8128d-6f14-4541-b308-ea32eff828b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125740188 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 264.prim_prince_test.125740188
Directory /workspace/264.prim_prince_test/latest

Test location /workspace/coverage/default/265.prim_prince_test.1610960963
Short name T478
Test name
Test status
Simulation time 2174320989 ps
CPU time 35.66 seconds
Started Jun 27 06:11:16 PM PDT 24
Finished Jun 27 06:12:01 PM PDT 24
Peak memory 146768 kb
Host smart-d0e9d951-b5c4-4ab7-ad10-60382cbd0974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610960963 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 265.prim_prince_test.1610960963
Directory /workspace/265.prim_prince_test/latest

Test location /workspace/coverage/default/266.prim_prince_test.572089928
Short name T423
Test name
Test status
Simulation time 2731642068 ps
CPU time 44.52 seconds
Started Jun 27 06:11:19 PM PDT 24
Finished Jun 27 06:12:15 PM PDT 24
Peak memory 146780 kb
Host smart-50aee31d-eeae-41b2-80b6-e2e74831ec05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572089928 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 266.prim_prince_test.572089928
Directory /workspace/266.prim_prince_test/latest

Test location /workspace/coverage/default/267.prim_prince_test.2452901760
Short name T93
Test name
Test status
Simulation time 1594028104 ps
CPU time 26.85 seconds
Started Jun 27 06:11:17 PM PDT 24
Finished Jun 27 06:11:51 PM PDT 24
Peak memory 146536 kb
Host smart-c40137fc-9435-4b4a-b008-9b668ea2aec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452901760 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 267.prim_prince_test.2452901760
Directory /workspace/267.prim_prince_test/latest

Test location /workspace/coverage/default/268.prim_prince_test.86280868
Short name T214
Test name
Test status
Simulation time 2034306610 ps
CPU time 33.39 seconds
Started Jun 27 06:11:19 PM PDT 24
Finished Jun 27 06:12:02 PM PDT 24
Peak memory 146712 kb
Host smart-d57d6c99-d12f-4515-93d2-7f40fc8365ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86280868 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 268.prim_prince_test.86280868
Directory /workspace/268.prim_prince_test/latest

Test location /workspace/coverage/default/269.prim_prince_test.749020363
Short name T207
Test name
Test status
Simulation time 2133798202 ps
CPU time 34.92 seconds
Started Jun 27 06:11:19 PM PDT 24
Finished Jun 27 06:12:04 PM PDT 24
Peak memory 146720 kb
Host smart-a7a4b7a4-4e5e-459c-ae63-9709aefd56bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749020363 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 269.prim_prince_test.749020363
Directory /workspace/269.prim_prince_test/latest

Test location /workspace/coverage/default/27.prim_prince_test.303737037
Short name T350
Test name
Test status
Simulation time 1093605271 ps
CPU time 17.68 seconds
Started Jun 27 06:10:12 PM PDT 24
Finished Jun 27 06:10:34 PM PDT 24
Peak memory 146732 kb
Host smart-e4e4423e-e2c1-4f5d-bc7f-5f90fa03824e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303737037 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_prince_test.303737037
Directory /workspace/27.prim_prince_test/latest

Test location /workspace/coverage/default/270.prim_prince_test.753352227
Short name T348
Test name
Test status
Simulation time 810443059 ps
CPU time 13.64 seconds
Started Jun 27 06:11:20 PM PDT 24
Finished Jun 27 06:11:38 PM PDT 24
Peak memory 146724 kb
Host smart-2aa7b683-aa59-417b-a681-5a2244462dff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753352227 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 270.prim_prince_test.753352227
Directory /workspace/270.prim_prince_test/latest

Test location /workspace/coverage/default/271.prim_prince_test.280303980
Short name T58
Test name
Test status
Simulation time 770823845 ps
CPU time 12.79 seconds
Started Jun 27 06:11:08 PM PDT 24
Finished Jun 27 06:11:25 PM PDT 24
Peak memory 146700 kb
Host smart-7174f28b-5597-40d8-bf6c-327378e7840b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280303980 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 271.prim_prince_test.280303980
Directory /workspace/271.prim_prince_test/latest

Test location /workspace/coverage/default/272.prim_prince_test.1838818673
Short name T451
Test name
Test status
Simulation time 1090834144 ps
CPU time 18.66 seconds
Started Jun 27 06:11:18 PM PDT 24
Finished Jun 27 06:11:42 PM PDT 24
Peak memory 146732 kb
Host smart-680a8f46-7137-46b0-88d3-bfed481536bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838818673 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 272.prim_prince_test.1838818673
Directory /workspace/272.prim_prince_test/latest

Test location /workspace/coverage/default/273.prim_prince_test.1490143343
Short name T296
Test name
Test status
Simulation time 1158087219 ps
CPU time 19.31 seconds
Started Jun 27 06:11:19 PM PDT 24
Finished Jun 27 06:11:45 PM PDT 24
Peak memory 146440 kb
Host smart-c8d29782-e606-4b19-99c3-9491cdc22d4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490143343 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 273.prim_prince_test.1490143343
Directory /workspace/273.prim_prince_test/latest

Test location /workspace/coverage/default/274.prim_prince_test.1836591658
Short name T160
Test name
Test status
Simulation time 1352568798 ps
CPU time 22.63 seconds
Started Jun 27 06:11:19 PM PDT 24
Finished Jun 27 06:11:48 PM PDT 24
Peak memory 146732 kb
Host smart-9d708540-3b52-40fd-905c-24752c2ab0bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836591658 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 274.prim_prince_test.1836591658
Directory /workspace/274.prim_prince_test/latest

Test location /workspace/coverage/default/275.prim_prince_test.2745473532
Short name T272
Test name
Test status
Simulation time 2749360426 ps
CPU time 44.82 seconds
Started Jun 27 06:11:13 PM PDT 24
Finished Jun 27 06:12:08 PM PDT 24
Peak memory 146792 kb
Host smart-7447fa97-f34e-40b9-a841-bc90cd618d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745473532 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 275.prim_prince_test.2745473532
Directory /workspace/275.prim_prince_test/latest

Test location /workspace/coverage/default/276.prim_prince_test.3307781076
Short name T438
Test name
Test status
Simulation time 3604717540 ps
CPU time 59.93 seconds
Started Jun 27 06:11:11 PM PDT 24
Finished Jun 27 06:12:24 PM PDT 24
Peak memory 146812 kb
Host smart-f4063368-6613-441c-a82b-fcaf56f0c9a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307781076 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 276.prim_prince_test.3307781076
Directory /workspace/276.prim_prince_test/latest

Test location /workspace/coverage/default/277.prim_prince_test.3068318357
Short name T248
Test name
Test status
Simulation time 3260516421 ps
CPU time 50.25 seconds
Started Jun 27 06:11:10 PM PDT 24
Finished Jun 27 06:12:10 PM PDT 24
Peak memory 146804 kb
Host smart-8263aab5-df04-44c3-81fd-89342acadea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068318357 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 277.prim_prince_test.3068318357
Directory /workspace/277.prim_prince_test/latest

Test location /workspace/coverage/default/278.prim_prince_test.4170743327
Short name T125
Test name
Test status
Simulation time 3103113273 ps
CPU time 52.09 seconds
Started Jun 27 06:11:10 PM PDT 24
Finished Jun 27 06:12:16 PM PDT 24
Peak memory 146800 kb
Host smart-cacd688e-cd9e-4fc1-8adc-d651b928372b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170743327 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 278.prim_prince_test.4170743327
Directory /workspace/278.prim_prince_test/latest

Test location /workspace/coverage/default/279.prim_prince_test.2657147260
Short name T138
Test name
Test status
Simulation time 2655485175 ps
CPU time 43.25 seconds
Started Jun 27 06:11:20 PM PDT 24
Finished Jun 27 06:12:14 PM PDT 24
Peak memory 146780 kb
Host smart-c43d0ce0-865d-4888-bdc4-a175e442d9de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657147260 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 279.prim_prince_test.2657147260
Directory /workspace/279.prim_prince_test/latest

Test location /workspace/coverage/default/28.prim_prince_test.2209150006
Short name T426
Test name
Test status
Simulation time 1810868825 ps
CPU time 30.37 seconds
Started Jun 27 06:10:12 PM PDT 24
Finished Jun 27 06:10:50 PM PDT 24
Peak memory 146676 kb
Host smart-91569bc4-3693-4a2d-9b1f-97d75ad06004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209150006 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_prince_test.2209150006
Directory /workspace/28.prim_prince_test/latest

Test location /workspace/coverage/default/280.prim_prince_test.1000347460
Short name T475
Test name
Test status
Simulation time 3476400592 ps
CPU time 57.68 seconds
Started Jun 27 06:11:13 PM PDT 24
Finished Jun 27 06:12:23 PM PDT 24
Peak memory 146792 kb
Host smart-900b2bfa-81b9-44ab-bd9d-130080b19388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000347460 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 280.prim_prince_test.1000347460
Directory /workspace/280.prim_prince_test/latest

Test location /workspace/coverage/default/281.prim_prince_test.1068478438
Short name T361
Test name
Test status
Simulation time 1129998587 ps
CPU time 18.77 seconds
Started Jun 27 06:11:13 PM PDT 24
Finished Jun 27 06:11:37 PM PDT 24
Peak memory 146728 kb
Host smart-b3302d10-4870-40b3-bee5-7c48d747fa47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068478438 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 281.prim_prince_test.1068478438
Directory /workspace/281.prim_prince_test/latest

Test location /workspace/coverage/default/282.prim_prince_test.1020570373
Short name T323
Test name
Test status
Simulation time 2095437874 ps
CPU time 34.76 seconds
Started Jun 27 06:11:19 PM PDT 24
Finished Jun 27 06:12:03 PM PDT 24
Peak memory 146416 kb
Host smart-040fa0bb-80c7-4c8b-a8ee-a640ca336a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020570373 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 282.prim_prince_test.1020570373
Directory /workspace/282.prim_prince_test/latest

Test location /workspace/coverage/default/283.prim_prince_test.851578336
Short name T443
Test name
Test status
Simulation time 1608471249 ps
CPU time 27.56 seconds
Started Jun 27 06:11:24 PM PDT 24
Finished Jun 27 06:11:59 PM PDT 24
Peak memory 146732 kb
Host smart-b48bca40-daea-47b8-9b38-c4892c938697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851578336 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 283.prim_prince_test.851578336
Directory /workspace/283.prim_prince_test/latest

Test location /workspace/coverage/default/284.prim_prince_test.913486774
Short name T427
Test name
Test status
Simulation time 3703635108 ps
CPU time 62.08 seconds
Started Jun 27 06:11:26 PM PDT 24
Finished Jun 27 06:12:43 PM PDT 24
Peak memory 146756 kb
Host smart-62b80c5d-56a9-4c0c-bc07-0f9dded4532d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913486774 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 284.prim_prince_test.913486774
Directory /workspace/284.prim_prince_test/latest

Test location /workspace/coverage/default/285.prim_prince_test.230562092
Short name T299
Test name
Test status
Simulation time 1930740176 ps
CPU time 32.1 seconds
Started Jun 27 06:11:25 PM PDT 24
Finished Jun 27 06:12:05 PM PDT 24
Peak memory 146744 kb
Host smart-8bcec9e0-805f-4b5d-9309-5fbb8bc82be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230562092 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 285.prim_prince_test.230562092
Directory /workspace/285.prim_prince_test/latest

Test location /workspace/coverage/default/286.prim_prince_test.2323206700
Short name T281
Test name
Test status
Simulation time 1568997263 ps
CPU time 25.94 seconds
Started Jun 27 06:11:29 PM PDT 24
Finished Jun 27 06:12:03 PM PDT 24
Peak memory 146724 kb
Host smart-9af7cb7e-7e80-4876-97d7-cbc52283d74c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323206700 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 286.prim_prince_test.2323206700
Directory /workspace/286.prim_prince_test/latest

Test location /workspace/coverage/default/287.prim_prince_test.703212100
Short name T73
Test name
Test status
Simulation time 2577874736 ps
CPU time 42.1 seconds
Started Jun 27 06:11:24 PM PDT 24
Finished Jun 27 06:12:16 PM PDT 24
Peak memory 146880 kb
Host smart-42195da2-e97b-4718-8116-073c2ce77649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703212100 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 287.prim_prince_test.703212100
Directory /workspace/287.prim_prince_test/latest

Test location /workspace/coverage/default/288.prim_prince_test.632643752
Short name T321
Test name
Test status
Simulation time 2722364526 ps
CPU time 45.7 seconds
Started Jun 27 06:11:28 PM PDT 24
Finished Jun 27 06:12:25 PM PDT 24
Peak memory 146804 kb
Host smart-3e6b62b7-7000-4f05-93ce-2c3c432560ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632643752 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 288.prim_prince_test.632643752
Directory /workspace/288.prim_prince_test/latest

Test location /workspace/coverage/default/289.prim_prince_test.945857709
Short name T254
Test name
Test status
Simulation time 2850724763 ps
CPU time 46.34 seconds
Started Jun 27 06:11:25 PM PDT 24
Finished Jun 27 06:12:22 PM PDT 24
Peak memory 146808 kb
Host smart-e948f7c9-8d07-4284-b0d0-d16cce08947b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945857709 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 289.prim_prince_test.945857709
Directory /workspace/289.prim_prince_test/latest

Test location /workspace/coverage/default/29.prim_prince_test.3620280668
Short name T404
Test name
Test status
Simulation time 3032775556 ps
CPU time 50.96 seconds
Started Jun 27 06:10:11 PM PDT 24
Finished Jun 27 06:11:13 PM PDT 24
Peak memory 146880 kb
Host smart-921ed689-8450-4b69-ad23-0d98a00a6fc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620280668 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_prince_test.3620280668
Directory /workspace/29.prim_prince_test/latest

Test location /workspace/coverage/default/290.prim_prince_test.4057954941
Short name T408
Test name
Test status
Simulation time 3748254683 ps
CPU time 62.36 seconds
Started Jun 27 06:11:24 PM PDT 24
Finished Jun 27 06:12:41 PM PDT 24
Peak memory 146720 kb
Host smart-ac1bf10f-d2da-4e68-80f1-d5612c9e59f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057954941 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 290.prim_prince_test.4057954941
Directory /workspace/290.prim_prince_test/latest

Test location /workspace/coverage/default/291.prim_prince_test.1496433265
Short name T250
Test name
Test status
Simulation time 2809424539 ps
CPU time 46.4 seconds
Started Jun 27 06:11:25 PM PDT 24
Finished Jun 27 06:12:23 PM PDT 24
Peak memory 146800 kb
Host smart-671250cd-8cce-483c-ac87-e84a278611b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496433265 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 291.prim_prince_test.1496433265
Directory /workspace/291.prim_prince_test/latest

Test location /workspace/coverage/default/292.prim_prince_test.437961229
Short name T346
Test name
Test status
Simulation time 2486912550 ps
CPU time 40.49 seconds
Started Jun 27 06:11:30 PM PDT 24
Finished Jun 27 06:12:20 PM PDT 24
Peak memory 146772 kb
Host smart-52bc2cba-da5e-4a67-ad35-b77a83e70556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437961229 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 292.prim_prince_test.437961229
Directory /workspace/292.prim_prince_test/latest

Test location /workspace/coverage/default/293.prim_prince_test.2480524138
Short name T210
Test name
Test status
Simulation time 1164422327 ps
CPU time 19.39 seconds
Started Jun 27 06:11:30 PM PDT 24
Finished Jun 27 06:11:55 PM PDT 24
Peak memory 146700 kb
Host smart-707b9de4-21ad-4f26-80b8-7282ff740dbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480524138 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 293.prim_prince_test.2480524138
Directory /workspace/293.prim_prince_test/latest

Test location /workspace/coverage/default/294.prim_prince_test.2689459158
Short name T316
Test name
Test status
Simulation time 3309948172 ps
CPU time 55.74 seconds
Started Jun 27 06:11:26 PM PDT 24
Finished Jun 27 06:12:35 PM PDT 24
Peak memory 146784 kb
Host smart-9cb81e03-7dfa-47b6-91d2-8f6c566adbd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689459158 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 294.prim_prince_test.2689459158
Directory /workspace/294.prim_prince_test/latest

Test location /workspace/coverage/default/295.prim_prince_test.3416398427
Short name T343
Test name
Test status
Simulation time 3697847755 ps
CPU time 56.03 seconds
Started Jun 27 06:11:22 PM PDT 24
Finished Jun 27 06:12:29 PM PDT 24
Peak memory 146744 kb
Host smart-3696d97d-9870-4bea-8da5-f7d56384a2f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416398427 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 295.prim_prince_test.3416398427
Directory /workspace/295.prim_prince_test/latest

Test location /workspace/coverage/default/296.prim_prince_test.3050031859
Short name T147
Test name
Test status
Simulation time 3573457176 ps
CPU time 57.81 seconds
Started Jun 27 06:11:25 PM PDT 24
Finished Jun 27 06:12:36 PM PDT 24
Peak memory 146796 kb
Host smart-8bf68a69-c950-4144-a0c6-3826504f32a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050031859 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 296.prim_prince_test.3050031859
Directory /workspace/296.prim_prince_test/latest

Test location /workspace/coverage/default/297.prim_prince_test.377454914
Short name T231
Test name
Test status
Simulation time 3377897918 ps
CPU time 56.76 seconds
Started Jun 27 06:11:24 PM PDT 24
Finished Jun 27 06:12:35 PM PDT 24
Peak memory 146812 kb
Host smart-2575e22e-853f-486b-a2b6-8fd684b8aca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377454914 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 297.prim_prince_test.377454914
Directory /workspace/297.prim_prince_test/latest

Test location /workspace/coverage/default/298.prim_prince_test.2297258811
Short name T118
Test name
Test status
Simulation time 1709680486 ps
CPU time 28.44 seconds
Started Jun 27 06:11:30 PM PDT 24
Finished Jun 27 06:12:07 PM PDT 24
Peak memory 146716 kb
Host smart-56847931-17fa-46f1-9331-53c4ff281680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297258811 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 298.prim_prince_test.2297258811
Directory /workspace/298.prim_prince_test/latest

Test location /workspace/coverage/default/299.prim_prince_test.2405303558
Short name T110
Test name
Test status
Simulation time 1381543563 ps
CPU time 23.74 seconds
Started Jun 27 06:11:24 PM PDT 24
Finished Jun 27 06:11:55 PM PDT 24
Peak memory 146740 kb
Host smart-15a94116-d184-449c-a4a2-79e763a69fcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405303558 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 299.prim_prince_test.2405303558
Directory /workspace/299.prim_prince_test/latest

Test location /workspace/coverage/default/3.prim_prince_test.1886375504
Short name T264
Test name
Test status
Simulation time 1833096069 ps
CPU time 30.19 seconds
Started Jun 27 06:10:06 PM PDT 24
Finished Jun 27 06:10:43 PM PDT 24
Peak memory 146748 kb
Host smart-3bfbcd41-305b-45f9-8e3c-c9d2d5ddb75a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886375504 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_prince_test.1886375504
Directory /workspace/3.prim_prince_test/latest

Test location /workspace/coverage/default/30.prim_prince_test.590169994
Short name T205
Test name
Test status
Simulation time 2223327614 ps
CPU time 37.44 seconds
Started Jun 27 06:10:14 PM PDT 24
Finished Jun 27 06:11:01 PM PDT 24
Peak memory 146792 kb
Host smart-d5dad4ab-f0b8-41ac-b225-e2a2153d3585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590169994 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_prince_test.590169994
Directory /workspace/30.prim_prince_test/latest

Test location /workspace/coverage/default/300.prim_prince_test.4016209324
Short name T358
Test name
Test status
Simulation time 2069949389 ps
CPU time 34.6 seconds
Started Jun 27 06:11:25 PM PDT 24
Finished Jun 27 06:12:09 PM PDT 24
Peak memory 146744 kb
Host smart-72898f5e-0446-400f-9a7c-ef2a5524c802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016209324 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 300.prim_prince_test.4016209324
Directory /workspace/300.prim_prince_test/latest

Test location /workspace/coverage/default/301.prim_prince_test.4064526264
Short name T43
Test name
Test status
Simulation time 2287741481 ps
CPU time 37.74 seconds
Started Jun 27 06:11:25 PM PDT 24
Finished Jun 27 06:12:12 PM PDT 24
Peak memory 146796 kb
Host smart-ae6847e6-ee7e-4cbc-b9f8-6568895cf21e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064526264 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 301.prim_prince_test.4064526264
Directory /workspace/301.prim_prince_test/latest

Test location /workspace/coverage/default/302.prim_prince_test.1268261581
Short name T46
Test name
Test status
Simulation time 775538239 ps
CPU time 13.56 seconds
Started Jun 27 06:11:29 PM PDT 24
Finished Jun 27 06:11:48 PM PDT 24
Peak memory 146728 kb
Host smart-d233ff5d-96dc-419e-a0b1-2e748bfca145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268261581 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 302.prim_prince_test.1268261581
Directory /workspace/302.prim_prince_test/latest

Test location /workspace/coverage/default/303.prim_prince_test.1418854388
Short name T126
Test name
Test status
Simulation time 1642754888 ps
CPU time 28.08 seconds
Started Jun 27 06:11:28 PM PDT 24
Finished Jun 27 06:12:03 PM PDT 24
Peak memory 146736 kb
Host smart-48e7e937-4ff5-4e49-9466-e1acfe05c390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418854388 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 303.prim_prince_test.1418854388
Directory /workspace/303.prim_prince_test/latest

Test location /workspace/coverage/default/304.prim_prince_test.1486663279
Short name T107
Test name
Test status
Simulation time 2189592469 ps
CPU time 36.28 seconds
Started Jun 27 06:11:28 PM PDT 24
Finished Jun 27 06:12:12 PM PDT 24
Peak memory 146800 kb
Host smart-0af093c6-ff65-4ba1-ba1e-b1d14fc25abc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486663279 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 304.prim_prince_test.1486663279
Directory /workspace/304.prim_prince_test/latest

Test location /workspace/coverage/default/305.prim_prince_test.3378963547
Short name T479
Test name
Test status
Simulation time 1691528530 ps
CPU time 28.31 seconds
Started Jun 27 06:11:26 PM PDT 24
Finished Jun 27 06:12:02 PM PDT 24
Peak memory 146668 kb
Host smart-0d402ec4-6140-4b2d-a0b5-f16301d27693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378963547 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 305.prim_prince_test.3378963547
Directory /workspace/305.prim_prince_test/latest

Test location /workspace/coverage/default/306.prim_prince_test.2923751492
Short name T18
Test name
Test status
Simulation time 1336769732 ps
CPU time 22.61 seconds
Started Jun 27 06:11:27 PM PDT 24
Finished Jun 27 06:11:56 PM PDT 24
Peak memory 146720 kb
Host smart-e739ee15-6221-48e8-9ed5-cd18f127cb0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923751492 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 306.prim_prince_test.2923751492
Directory /workspace/306.prim_prince_test/latest

Test location /workspace/coverage/default/307.prim_prince_test.2450455821
Short name T473
Test name
Test status
Simulation time 2827627029 ps
CPU time 46.62 seconds
Started Jun 27 06:11:24 PM PDT 24
Finished Jun 27 06:12:21 PM PDT 24
Peak memory 146812 kb
Host smart-6af7e6ec-be9c-452c-a979-a0fc98d5e464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450455821 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 307.prim_prince_test.2450455821
Directory /workspace/307.prim_prince_test/latest

Test location /workspace/coverage/default/308.prim_prince_test.1096388547
Short name T34
Test name
Test status
Simulation time 1993181358 ps
CPU time 32.9 seconds
Started Jun 27 06:11:30 PM PDT 24
Finished Jun 27 06:12:11 PM PDT 24
Peak memory 146728 kb
Host smart-048bb9ac-e8ce-4d39-b930-b83f3aaf3147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096388547 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 308.prim_prince_test.1096388547
Directory /workspace/308.prim_prince_test/latest

Test location /workspace/coverage/default/309.prim_prince_test.1181307967
Short name T289
Test name
Test status
Simulation time 1552529655 ps
CPU time 26.65 seconds
Started Jun 27 06:11:27 PM PDT 24
Finished Jun 27 06:12:01 PM PDT 24
Peak memory 146736 kb
Host smart-0537ad4f-3184-425e-9894-aaf1309595ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181307967 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 309.prim_prince_test.1181307967
Directory /workspace/309.prim_prince_test/latest

Test location /workspace/coverage/default/31.prim_prince_test.3393313952
Short name T80
Test name
Test status
Simulation time 1958776821 ps
CPU time 33 seconds
Started Jun 27 06:10:13 PM PDT 24
Finished Jun 27 06:10:54 PM PDT 24
Peak memory 146744 kb
Host smart-c0f5a35a-d302-4953-98ad-62648e2c019b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393313952 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_prince_test.3393313952
Directory /workspace/31.prim_prince_test/latest

Test location /workspace/coverage/default/310.prim_prince_test.1354235103
Short name T459
Test name
Test status
Simulation time 1549177905 ps
CPU time 25.79 seconds
Started Jun 27 06:11:25 PM PDT 24
Finished Jun 27 06:11:58 PM PDT 24
Peak memory 146668 kb
Host smart-164d599c-d6de-4c1c-9761-e07a6d3fa513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354235103 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 310.prim_prince_test.1354235103
Directory /workspace/310.prim_prince_test/latest

Test location /workspace/coverage/default/311.prim_prince_test.1341009407
Short name T187
Test name
Test status
Simulation time 1716063713 ps
CPU time 29.47 seconds
Started Jun 27 06:11:23 PM PDT 24
Finished Jun 27 06:12:01 PM PDT 24
Peak memory 146736 kb
Host smart-37972ed1-2e07-49c2-91c7-52bbfc981174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341009407 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 311.prim_prince_test.1341009407
Directory /workspace/311.prim_prince_test/latest

Test location /workspace/coverage/default/312.prim_prince_test.1979663865
Short name T215
Test name
Test status
Simulation time 789815142 ps
CPU time 13.56 seconds
Started Jun 27 06:11:29 PM PDT 24
Finished Jun 27 06:11:47 PM PDT 24
Peak memory 146708 kb
Host smart-fe95a896-2181-4248-b7db-dcb4cebbf6d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979663865 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 312.prim_prince_test.1979663865
Directory /workspace/312.prim_prince_test/latest

Test location /workspace/coverage/default/313.prim_prince_test.4218481794
Short name T36
Test name
Test status
Simulation time 1727776387 ps
CPU time 28.38 seconds
Started Jun 27 06:11:28 PM PDT 24
Finished Jun 27 06:12:03 PM PDT 24
Peak memory 146736 kb
Host smart-e757375d-964a-4a09-bf81-a45547afc0b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218481794 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 313.prim_prince_test.4218481794
Directory /workspace/313.prim_prince_test/latest

Test location /workspace/coverage/default/314.prim_prince_test.3772024477
Short name T133
Test name
Test status
Simulation time 2008668416 ps
CPU time 33.47 seconds
Started Jun 27 06:11:41 PM PDT 24
Finished Jun 27 06:12:24 PM PDT 24
Peak memory 146748 kb
Host smart-639bf0b6-6446-4c24-9792-76cd75fb3830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772024477 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 314.prim_prince_test.3772024477
Directory /workspace/314.prim_prince_test/latest

Test location /workspace/coverage/default/315.prim_prince_test.2218264527
Short name T373
Test name
Test status
Simulation time 1416606380 ps
CPU time 23.9 seconds
Started Jun 27 06:11:41 PM PDT 24
Finished Jun 27 06:12:12 PM PDT 24
Peak memory 146740 kb
Host smart-7e9c2a4d-a4f0-4916-ba07-129f18706d84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218264527 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 315.prim_prince_test.2218264527
Directory /workspace/315.prim_prince_test/latest

Test location /workspace/coverage/default/316.prim_prince_test.3235535112
Short name T243
Test name
Test status
Simulation time 3494446477 ps
CPU time 56.76 seconds
Started Jun 27 06:11:44 PM PDT 24
Finished Jun 27 06:12:56 PM PDT 24
Peak memory 146804 kb
Host smart-5692db01-761c-4933-af45-4a56c125fdbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235535112 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 316.prim_prince_test.3235535112
Directory /workspace/316.prim_prince_test/latest

Test location /workspace/coverage/default/317.prim_prince_test.2472471593
Short name T483
Test name
Test status
Simulation time 854585030 ps
CPU time 14.27 seconds
Started Jun 27 06:11:42 PM PDT 24
Finished Jun 27 06:12:03 PM PDT 24
Peak memory 146732 kb
Host smart-0ac683b1-98ea-4123-9c4c-1f38aa76c69f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472471593 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 317.prim_prince_test.2472471593
Directory /workspace/317.prim_prince_test/latest

Test location /workspace/coverage/default/318.prim_prince_test.2248907722
Short name T57
Test name
Test status
Simulation time 1129050322 ps
CPU time 18.55 seconds
Started Jun 27 06:11:40 PM PDT 24
Finished Jun 27 06:12:02 PM PDT 24
Peak memory 146736 kb
Host smart-b02aa44c-4d21-44b1-96c5-076261631985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248907722 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 318.prim_prince_test.2248907722
Directory /workspace/318.prim_prince_test/latest

Test location /workspace/coverage/default/319.prim_prince_test.1165990632
Short name T276
Test name
Test status
Simulation time 1223863940 ps
CPU time 20.93 seconds
Started Jun 27 06:11:43 PM PDT 24
Finished Jun 27 06:12:12 PM PDT 24
Peak memory 146740 kb
Host smart-6cbb5d36-7186-4b6e-b2db-ff27e9f9e044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165990632 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 319.prim_prince_test.1165990632
Directory /workspace/319.prim_prince_test/latest

Test location /workspace/coverage/default/32.prim_prince_test.78434653
Short name T223
Test name
Test status
Simulation time 1068574979 ps
CPU time 17.44 seconds
Started Jun 27 06:10:12 PM PDT 24
Finished Jun 27 06:10:35 PM PDT 24
Peak memory 146736 kb
Host smart-27f1931b-c155-432e-bb5c-5325231031a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78434653 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_prince_test.78434653
Directory /workspace/32.prim_prince_test/latest

Test location /workspace/coverage/default/320.prim_prince_test.119631721
Short name T301
Test name
Test status
Simulation time 1242418280 ps
CPU time 21.16 seconds
Started Jun 27 06:11:43 PM PDT 24
Finished Jun 27 06:12:12 PM PDT 24
Peak memory 146752 kb
Host smart-26a903a1-79f0-425c-8036-3fe069b9d26f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119631721 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 320.prim_prince_test.119631721
Directory /workspace/320.prim_prince_test/latest

Test location /workspace/coverage/default/321.prim_prince_test.1004490630
Short name T216
Test name
Test status
Simulation time 3331313892 ps
CPU time 55.31 seconds
Started Jun 27 06:11:51 PM PDT 24
Finished Jun 27 06:13:00 PM PDT 24
Peak memory 146720 kb
Host smart-1f51ef9f-1017-4fa2-8675-8066162b9750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004490630 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 321.prim_prince_test.1004490630
Directory /workspace/321.prim_prince_test/latest

Test location /workspace/coverage/default/322.prim_prince_test.622474832
Short name T392
Test name
Test status
Simulation time 2549916642 ps
CPU time 42.72 seconds
Started Jun 27 06:11:42 PM PDT 24
Finished Jun 27 06:12:36 PM PDT 24
Peak memory 146812 kb
Host smart-6eef35a1-ea7c-45c9-98b4-0918f28f0412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622474832 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 322.prim_prince_test.622474832
Directory /workspace/322.prim_prince_test/latest

Test location /workspace/coverage/default/323.prim_prince_test.1265662971
Short name T173
Test name
Test status
Simulation time 1952798579 ps
CPU time 32.82 seconds
Started Jun 27 06:11:41 PM PDT 24
Finished Jun 27 06:12:24 PM PDT 24
Peak memory 146732 kb
Host smart-654a67f5-30f7-47b3-bc0e-30f79b16e9a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265662971 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 323.prim_prince_test.1265662971
Directory /workspace/323.prim_prince_test/latest

Test location /workspace/coverage/default/324.prim_prince_test.4224789374
Short name T280
Test name
Test status
Simulation time 2579605523 ps
CPU time 43.03 seconds
Started Jun 27 06:11:43 PM PDT 24
Finished Jun 27 06:12:38 PM PDT 24
Peak memory 146800 kb
Host smart-9ae68d8d-e885-4ea6-8efd-16be987c1f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224789374 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 324.prim_prince_test.4224789374
Directory /workspace/324.prim_prince_test/latest

Test location /workspace/coverage/default/325.prim_prince_test.171723930
Short name T453
Test name
Test status
Simulation time 3538678315 ps
CPU time 59.32 seconds
Started Jun 27 06:11:43 PM PDT 24
Finished Jun 27 06:13:00 PM PDT 24
Peak memory 146756 kb
Host smart-6e11456b-bab6-4099-ab6e-395866044141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171723930 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 325.prim_prince_test.171723930
Directory /workspace/325.prim_prince_test/latest

Test location /workspace/coverage/default/326.prim_prince_test.311693306
Short name T132
Test name
Test status
Simulation time 2326718284 ps
CPU time 39.02 seconds
Started Jun 27 06:11:40 PM PDT 24
Finished Jun 27 06:12:29 PM PDT 24
Peak memory 146808 kb
Host smart-0bfe5586-b107-4380-bc77-499a80e4d7a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311693306 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 326.prim_prince_test.311693306
Directory /workspace/326.prim_prince_test/latest

Test location /workspace/coverage/default/327.prim_prince_test.30021502
Short name T135
Test name
Test status
Simulation time 2487601458 ps
CPU time 41.39 seconds
Started Jun 27 06:11:45 PM PDT 24
Finished Jun 27 06:12:38 PM PDT 24
Peak memory 146508 kb
Host smart-1cc6cc57-f7b9-4d46-b53b-19fab9548fac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30021502 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 327.prim_prince_test.30021502
Directory /workspace/327.prim_prince_test/latest

Test location /workspace/coverage/default/328.prim_prince_test.2524797337
Short name T476
Test name
Test status
Simulation time 889471087 ps
CPU time 15.45 seconds
Started Jun 27 06:11:43 PM PDT 24
Finished Jun 27 06:12:06 PM PDT 24
Peak memory 146736 kb
Host smart-85d0adcd-23c4-4a2d-8c0c-ddfd03d1e75f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524797337 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 328.prim_prince_test.2524797337
Directory /workspace/328.prim_prince_test/latest

Test location /workspace/coverage/default/329.prim_prince_test.370804369
Short name T363
Test name
Test status
Simulation time 1098912150 ps
CPU time 18.82 seconds
Started Jun 27 06:11:41 PM PDT 24
Finished Jun 27 06:12:06 PM PDT 24
Peak memory 146732 kb
Host smart-59eb8e98-6bc8-40a4-83e2-48656c6e7529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370804369 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 329.prim_prince_test.370804369
Directory /workspace/329.prim_prince_test/latest

Test location /workspace/coverage/default/33.prim_prince_test.2223503634
Short name T159
Test name
Test status
Simulation time 2923190357 ps
CPU time 50.24 seconds
Started Jun 27 06:10:14 PM PDT 24
Finished Jun 27 06:11:18 PM PDT 24
Peak memory 146816 kb
Host smart-6e9906e7-6d39-4121-a52f-c3c5f63a9aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223503634 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_prince_test.2223503634
Directory /workspace/33.prim_prince_test/latest

Test location /workspace/coverage/default/330.prim_prince_test.2226356780
Short name T191
Test name
Test status
Simulation time 2516965076 ps
CPU time 41.78 seconds
Started Jun 27 06:11:42 PM PDT 24
Finished Jun 27 06:12:35 PM PDT 24
Peak memory 146796 kb
Host smart-5c8a477b-34f1-4e13-9642-4ab8e85784f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226356780 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 330.prim_prince_test.2226356780
Directory /workspace/330.prim_prince_test/latest

Test location /workspace/coverage/default/331.prim_prince_test.2784404383
Short name T225
Test name
Test status
Simulation time 1764025539 ps
CPU time 29.28 seconds
Started Jun 27 06:11:41 PM PDT 24
Finished Jun 27 06:12:18 PM PDT 24
Peak memory 146728 kb
Host smart-73dae3a8-e0e1-43ae-ba9d-6a5621c8a161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784404383 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 331.prim_prince_test.2784404383
Directory /workspace/331.prim_prince_test/latest

Test location /workspace/coverage/default/332.prim_prince_test.1026651124
Short name T405
Test name
Test status
Simulation time 3404576415 ps
CPU time 57.47 seconds
Started Jun 27 06:11:43 PM PDT 24
Finished Jun 27 06:12:58 PM PDT 24
Peak memory 146796 kb
Host smart-aa83750a-51ad-4eae-8918-397a24386e05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026651124 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 332.prim_prince_test.1026651124
Directory /workspace/332.prim_prince_test/latest

Test location /workspace/coverage/default/333.prim_prince_test.103138525
Short name T329
Test name
Test status
Simulation time 3176775038 ps
CPU time 52.3 seconds
Started Jun 27 06:11:44 PM PDT 24
Finished Jun 27 06:12:51 PM PDT 24
Peak memory 146812 kb
Host smart-d340774d-4b09-4373-ab64-16667a0342a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103138525 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 333.prim_prince_test.103138525
Directory /workspace/333.prim_prince_test/latest

Test location /workspace/coverage/default/334.prim_prince_test.1259098799
Short name T144
Test name
Test status
Simulation time 2543378509 ps
CPU time 42.43 seconds
Started Jun 27 06:11:42 PM PDT 24
Finished Jun 27 06:12:37 PM PDT 24
Peak memory 146800 kb
Host smart-4660d03d-bb84-469a-8f4f-16752fd0ffda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259098799 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 334.prim_prince_test.1259098799
Directory /workspace/334.prim_prince_test/latest

Test location /workspace/coverage/default/335.prim_prince_test.3281212859
Short name T317
Test name
Test status
Simulation time 768806027 ps
CPU time 13.69 seconds
Started Jun 27 06:11:43 PM PDT 24
Finished Jun 27 06:12:03 PM PDT 24
Peak memory 146736 kb
Host smart-6104e802-d943-423e-bfcc-969f164bcab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281212859 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 335.prim_prince_test.3281212859
Directory /workspace/335.prim_prince_test/latest

Test location /workspace/coverage/default/336.prim_prince_test.4010112764
Short name T471
Test name
Test status
Simulation time 1664316686 ps
CPU time 27.84 seconds
Started Jun 27 06:11:40 PM PDT 24
Finished Jun 27 06:12:14 PM PDT 24
Peak memory 146736 kb
Host smart-f98fb735-d2db-400a-aade-d6b0121cc676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010112764 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 336.prim_prince_test.4010112764
Directory /workspace/336.prim_prince_test/latest

Test location /workspace/coverage/default/337.prim_prince_test.1249283174
Short name T309
Test name
Test status
Simulation time 1161589492 ps
CPU time 19.86 seconds
Started Jun 27 06:11:45 PM PDT 24
Finished Jun 27 06:12:12 PM PDT 24
Peak memory 146420 kb
Host smart-11216043-6792-4df7-a60a-89f4a0fd9879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249283174 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 337.prim_prince_test.1249283174
Directory /workspace/337.prim_prince_test/latest

Test location /workspace/coverage/default/338.prim_prince_test.3492399973
Short name T30
Test name
Test status
Simulation time 1292191954 ps
CPU time 22.14 seconds
Started Jun 27 06:11:43 PM PDT 24
Finished Jun 27 06:12:14 PM PDT 24
Peak memory 146736 kb
Host smart-2efa1cf6-4740-43e9-ba3e-27cc41f158a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492399973 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 338.prim_prince_test.3492399973
Directory /workspace/338.prim_prince_test/latest

Test location /workspace/coverage/default/339.prim_prince_test.3859640026
Short name T305
Test name
Test status
Simulation time 2741878315 ps
CPU time 45.8 seconds
Started Jun 27 06:11:42 PM PDT 24
Finished Jun 27 06:12:40 PM PDT 24
Peak memory 146804 kb
Host smart-f853d017-6524-4d75-ac95-e2bc89ca22ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859640026 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 339.prim_prince_test.3859640026
Directory /workspace/339.prim_prince_test/latest

Test location /workspace/coverage/default/34.prim_prince_test.2812512854
Short name T370
Test name
Test status
Simulation time 1233816477 ps
CPU time 20.57 seconds
Started Jun 27 06:10:12 PM PDT 24
Finished Jun 27 06:10:38 PM PDT 24
Peak memory 146632 kb
Host smart-d1e56e36-6aef-4c6b-b9ee-5c6d1d735a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812512854 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_prince_test.2812512854
Directory /workspace/34.prim_prince_test/latest

Test location /workspace/coverage/default/340.prim_prince_test.2722324954
Short name T188
Test name
Test status
Simulation time 3611250117 ps
CPU time 59.15 seconds
Started Jun 27 06:11:41 PM PDT 24
Finished Jun 27 06:12:55 PM PDT 24
Peak memory 146812 kb
Host smart-050054cd-f0a9-48cf-ae80-2a280c4e0382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722324954 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 340.prim_prince_test.2722324954
Directory /workspace/340.prim_prince_test/latest

Test location /workspace/coverage/default/341.prim_prince_test.3581599584
Short name T51
Test name
Test status
Simulation time 927068452 ps
CPU time 15.97 seconds
Started Jun 27 06:11:41 PM PDT 24
Finished Jun 27 06:12:02 PM PDT 24
Peak memory 146724 kb
Host smart-491c1404-5229-43ff-9398-7b74e846badb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581599584 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 341.prim_prince_test.3581599584
Directory /workspace/341.prim_prince_test/latest

Test location /workspace/coverage/default/342.prim_prince_test.3999536859
Short name T208
Test name
Test status
Simulation time 1686595453 ps
CPU time 28.51 seconds
Started Jun 27 06:11:43 PM PDT 24
Finished Jun 27 06:12:22 PM PDT 24
Peak memory 146728 kb
Host smart-f2b22ff3-4ea2-4d90-9c39-ac897e559e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999536859 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 342.prim_prince_test.3999536859
Directory /workspace/342.prim_prince_test/latest

Test location /workspace/coverage/default/343.prim_prince_test.156156343
Short name T185
Test name
Test status
Simulation time 1958206975 ps
CPU time 32.88 seconds
Started Jun 27 06:11:42 PM PDT 24
Finished Jun 27 06:12:25 PM PDT 24
Peak memory 146744 kb
Host smart-3c49658d-d3df-4fdb-b3c5-8dd7160e2b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156156343 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 343.prim_prince_test.156156343
Directory /workspace/343.prim_prince_test/latest

Test location /workspace/coverage/default/344.prim_prince_test.3242864483
Short name T90
Test name
Test status
Simulation time 1873891711 ps
CPU time 31.49 seconds
Started Jun 27 06:11:44 PM PDT 24
Finished Jun 27 06:12:26 PM PDT 24
Peak memory 146732 kb
Host smart-6c31b900-5832-4e79-9f8c-0cda24e1e493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242864483 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 344.prim_prince_test.3242864483
Directory /workspace/344.prim_prince_test/latest

Test location /workspace/coverage/default/345.prim_prince_test.2253156023
Short name T283
Test name
Test status
Simulation time 1740669196 ps
CPU time 28.8 seconds
Started Jun 27 06:11:46 PM PDT 24
Finished Jun 27 06:12:24 PM PDT 24
Peak memory 146728 kb
Host smart-f3016a56-fc82-472c-b670-83c852b62503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253156023 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 345.prim_prince_test.2253156023
Directory /workspace/345.prim_prince_test/latest

Test location /workspace/coverage/default/346.prim_prince_test.4290047577
Short name T176
Test name
Test status
Simulation time 3722857145 ps
CPU time 62.47 seconds
Started Jun 27 06:11:43 PM PDT 24
Finished Jun 27 06:13:04 PM PDT 24
Peak memory 146792 kb
Host smart-ea3ea95e-d55f-4498-80ac-c2fce2e666e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290047577 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 346.prim_prince_test.4290047577
Directory /workspace/346.prim_prince_test/latest

Test location /workspace/coverage/default/347.prim_prince_test.587403683
Short name T366
Test name
Test status
Simulation time 3542308215 ps
CPU time 57.51 seconds
Started Jun 27 06:11:44 PM PDT 24
Finished Jun 27 06:12:57 PM PDT 24
Peak memory 146772 kb
Host smart-c7295fdd-0115-4fcd-8569-68a62c9ee22a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587403683 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 347.prim_prince_test.587403683
Directory /workspace/347.prim_prince_test/latest

Test location /workspace/coverage/default/348.prim_prince_test.3440562
Short name T163
Test name
Test status
Simulation time 1593502505 ps
CPU time 26.88 seconds
Started Jun 27 06:11:41 PM PDT 24
Finished Jun 27 06:12:15 PM PDT 24
Peak memory 146740 kb
Host smart-436f28be-df05-4517-8f2f-fecad979b234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440562 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 348.prim_prince_test.3440562
Directory /workspace/348.prim_prince_test/latest

Test location /workspace/coverage/default/349.prim_prince_test.1892265196
Short name T446
Test name
Test status
Simulation time 3352387061 ps
CPU time 52.03 seconds
Started Jun 27 06:11:42 PM PDT 24
Finished Jun 27 06:12:47 PM PDT 24
Peak memory 146756 kb
Host smart-e77a02b5-69c8-416c-baa0-ac2c44746b0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892265196 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 349.prim_prince_test.1892265196
Directory /workspace/349.prim_prince_test/latest

Test location /workspace/coverage/default/35.prim_prince_test.3119585494
Short name T83
Test name
Test status
Simulation time 2994344209 ps
CPU time 50.58 seconds
Started Jun 27 06:10:11 PM PDT 24
Finished Jun 27 06:11:15 PM PDT 24
Peak memory 146796 kb
Host smart-5a7a6391-292a-4b6f-ba7c-696fbe188066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119585494 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_prince_test.3119585494
Directory /workspace/35.prim_prince_test/latest

Test location /workspace/coverage/default/350.prim_prince_test.2547968030
Short name T155
Test name
Test status
Simulation time 1715538041 ps
CPU time 28.84 seconds
Started Jun 27 06:11:42 PM PDT 24
Finished Jun 27 06:12:19 PM PDT 24
Peak memory 146748 kb
Host smart-fc8ec737-79f6-4883-a66a-111c0bbe95e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547968030 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 350.prim_prince_test.2547968030
Directory /workspace/350.prim_prince_test/latest

Test location /workspace/coverage/default/351.prim_prince_test.2364170308
Short name T418
Test name
Test status
Simulation time 919335945 ps
CPU time 14.79 seconds
Started Jun 27 06:11:42 PM PDT 24
Finished Jun 27 06:12:03 PM PDT 24
Peak memory 146692 kb
Host smart-609046cc-c2d0-433e-aa64-3363cdd22047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364170308 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 351.prim_prince_test.2364170308
Directory /workspace/351.prim_prince_test/latest

Test location /workspace/coverage/default/352.prim_prince_test.2742653917
Short name T457
Test name
Test status
Simulation time 873593736 ps
CPU time 14.81 seconds
Started Jun 27 06:11:43 PM PDT 24
Finished Jun 27 06:12:05 PM PDT 24
Peak memory 146744 kb
Host smart-eaae3658-1c7f-4449-b68a-ef2fa32be12f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742653917 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 352.prim_prince_test.2742653917
Directory /workspace/352.prim_prince_test/latest

Test location /workspace/coverage/default/353.prim_prince_test.554064911
Short name T384
Test name
Test status
Simulation time 3546032644 ps
CPU time 59.32 seconds
Started Jun 27 06:11:43 PM PDT 24
Finished Jun 27 06:12:58 PM PDT 24
Peak memory 146804 kb
Host smart-936ea085-78c5-4052-adb5-d99c72ac4c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554064911 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 353.prim_prince_test.554064911
Directory /workspace/353.prim_prince_test/latest

Test location /workspace/coverage/default/354.prim_prince_test.619412387
Short name T491
Test name
Test status
Simulation time 2058604781 ps
CPU time 33.46 seconds
Started Jun 27 06:11:40 PM PDT 24
Finished Jun 27 06:12:21 PM PDT 24
Peak memory 146680 kb
Host smart-6c910651-41c3-44ba-981b-a312f48aae42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619412387 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 354.prim_prince_test.619412387
Directory /workspace/354.prim_prince_test/latest

Test location /workspace/coverage/default/355.prim_prince_test.1064966102
Short name T198
Test name
Test status
Simulation time 1910044996 ps
CPU time 32.02 seconds
Started Jun 27 06:11:42 PM PDT 24
Finished Jun 27 06:12:25 PM PDT 24
Peak memory 146748 kb
Host smart-38978324-09d6-4295-bea8-f417f18d291a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064966102 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 355.prim_prince_test.1064966102
Directory /workspace/355.prim_prince_test/latest

Test location /workspace/coverage/default/356.prim_prince_test.1086618592
Short name T140
Test name
Test status
Simulation time 1280549715 ps
CPU time 20.63 seconds
Started Jun 27 06:11:44 PM PDT 24
Finished Jun 27 06:12:13 PM PDT 24
Peak memory 146692 kb
Host smart-299a7d61-e1cd-43de-9ad5-b1763f283746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086618592 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 356.prim_prince_test.1086618592
Directory /workspace/356.prim_prince_test/latest

Test location /workspace/coverage/default/357.prim_prince_test.2950683237
Short name T494
Test name
Test status
Simulation time 2320366374 ps
CPU time 36.61 seconds
Started Jun 27 06:11:42 PM PDT 24
Finished Jun 27 06:12:28 PM PDT 24
Peak memory 146768 kb
Host smart-b0e7c318-177c-4b2a-a481-3365e051f16d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950683237 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 357.prim_prince_test.2950683237
Directory /workspace/357.prim_prince_test/latest

Test location /workspace/coverage/default/358.prim_prince_test.3453880622
Short name T322
Test name
Test status
Simulation time 3210148254 ps
CPU time 54.18 seconds
Started Jun 27 06:11:42 PM PDT 24
Finished Jun 27 06:12:52 PM PDT 24
Peak memory 146792 kb
Host smart-05b054d2-7f08-4e36-a45c-ad94940043b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453880622 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 358.prim_prince_test.3453880622
Directory /workspace/358.prim_prince_test/latest

Test location /workspace/coverage/default/359.prim_prince_test.3495977991
Short name T472
Test name
Test status
Simulation time 3266311211 ps
CPU time 54.6 seconds
Started Jun 27 06:11:42 PM PDT 24
Finished Jun 27 06:12:51 PM PDT 24
Peak memory 146816 kb
Host smart-9fd518a1-10c8-4d02-8864-f97046a7da0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495977991 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 359.prim_prince_test.3495977991
Directory /workspace/359.prim_prince_test/latest

Test location /workspace/coverage/default/36.prim_prince_test.774026029
Short name T182
Test name
Test status
Simulation time 3189902505 ps
CPU time 53.8 seconds
Started Jun 27 06:10:12 PM PDT 24
Finished Jun 27 06:11:19 PM PDT 24
Peak memory 146796 kb
Host smart-3e02565a-945a-4c7f-88a4-3df37e87957d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774026029 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_prince_test.774026029
Directory /workspace/36.prim_prince_test/latest

Test location /workspace/coverage/default/360.prim_prince_test.3076462263
Short name T212
Test name
Test status
Simulation time 3617638506 ps
CPU time 60.53 seconds
Started Jun 27 06:11:42 PM PDT 24
Finished Jun 27 06:13:00 PM PDT 24
Peak memory 146800 kb
Host smart-240023f8-290e-4550-8290-71967c93cfac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076462263 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 360.prim_prince_test.3076462263
Directory /workspace/360.prim_prince_test/latest

Test location /workspace/coverage/default/361.prim_prince_test.87966152
Short name T3
Test name
Test status
Simulation time 3726547149 ps
CPU time 63.92 seconds
Started Jun 27 06:11:41 PM PDT 24
Finished Jun 27 06:13:03 PM PDT 24
Peak memory 146780 kb
Host smart-d4b3cd7b-7d2e-4d58-a1fd-a2ba6279fb84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87966152 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 361.prim_prince_test.87966152
Directory /workspace/361.prim_prince_test/latest

Test location /workspace/coverage/default/362.prim_prince_test.2482481049
Short name T61
Test name
Test status
Simulation time 1631416256 ps
CPU time 26.86 seconds
Started Jun 27 06:11:44 PM PDT 24
Finished Jun 27 06:12:21 PM PDT 24
Peak memory 146704 kb
Host smart-a4b9b449-2b35-4813-a480-666abef6f38a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482481049 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 362.prim_prince_test.2482481049
Directory /workspace/362.prim_prince_test/latest

Test location /workspace/coverage/default/363.prim_prince_test.44518017
Short name T393
Test name
Test status
Simulation time 2765645202 ps
CPU time 46.94 seconds
Started Jun 27 06:11:43 PM PDT 24
Finished Jun 27 06:12:44 PM PDT 24
Peak memory 146792 kb
Host smart-60e46f04-2975-4c4c-ab64-4209541e3a26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44518017 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 363.prim_prince_test.44518017
Directory /workspace/363.prim_prince_test/latest

Test location /workspace/coverage/default/364.prim_prince_test.3478948692
Short name T490
Test name
Test status
Simulation time 1178251031 ps
CPU time 19.84 seconds
Started Jun 27 06:11:42 PM PDT 24
Finished Jun 27 06:12:10 PM PDT 24
Peak memory 146696 kb
Host smart-5bb921fd-8979-4fe6-92a7-0ee811d22631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478948692 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 364.prim_prince_test.3478948692
Directory /workspace/364.prim_prince_test/latest

Test location /workspace/coverage/default/365.prim_prince_test.875609887
Short name T464
Test name
Test status
Simulation time 1580570063 ps
CPU time 26.53 seconds
Started Jun 27 06:11:41 PM PDT 24
Finished Jun 27 06:12:15 PM PDT 24
Peak memory 146744 kb
Host smart-ff0375c6-aba5-4628-9ae8-9d2dd9cd5d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875609887 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 365.prim_prince_test.875609887
Directory /workspace/365.prim_prince_test/latest

Test location /workspace/coverage/default/366.prim_prince_test.1484541322
Short name T387
Test name
Test status
Simulation time 3306000323 ps
CPU time 54.8 seconds
Started Jun 27 06:11:43 PM PDT 24
Finished Jun 27 06:12:55 PM PDT 24
Peak memory 146800 kb
Host smart-c03a61f4-820d-41bd-b7f3-a7256a6c622b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484541322 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 366.prim_prince_test.1484541322
Directory /workspace/366.prim_prince_test/latest

Test location /workspace/coverage/default/367.prim_prince_test.3483358503
Short name T255
Test name
Test status
Simulation time 1748024853 ps
CPU time 29.82 seconds
Started Jun 27 06:11:43 PM PDT 24
Finished Jun 27 06:12:23 PM PDT 24
Peak memory 146732 kb
Host smart-f8b9de89-f97f-4a0f-9e70-a050b13dd2de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483358503 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 367.prim_prince_test.3483358503
Directory /workspace/367.prim_prince_test/latest

Test location /workspace/coverage/default/368.prim_prince_test.1289277817
Short name T100
Test name
Test status
Simulation time 1317780976 ps
CPU time 22.49 seconds
Started Jun 27 06:11:42 PM PDT 24
Finished Jun 27 06:12:13 PM PDT 24
Peak memory 146724 kb
Host smart-68804649-0f3c-4a5a-a375-4159c0fd2103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289277817 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 368.prim_prince_test.1289277817
Directory /workspace/368.prim_prince_test/latest

Test location /workspace/coverage/default/369.prim_prince_test.1751618766
Short name T201
Test name
Test status
Simulation time 2579813050 ps
CPU time 43.45 seconds
Started Jun 27 06:11:59 PM PDT 24
Finished Jun 27 06:12:55 PM PDT 24
Peak memory 146720 kb
Host smart-ad91ee8a-cca9-4ddc-9a2f-8c29addc9b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751618766 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 369.prim_prince_test.1751618766
Directory /workspace/369.prim_prince_test/latest

Test location /workspace/coverage/default/37.prim_prince_test.3704288900
Short name T99
Test name
Test status
Simulation time 2180874299 ps
CPU time 35.89 seconds
Started Jun 27 06:10:11 PM PDT 24
Finished Jun 27 06:10:55 PM PDT 24
Peak memory 146808 kb
Host smart-4aac3067-4b5e-49c5-9f5e-28679ce2b9c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704288900 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_prince_test.3704288900
Directory /workspace/37.prim_prince_test/latest

Test location /workspace/coverage/default/370.prim_prince_test.2386928184
Short name T372
Test name
Test status
Simulation time 1887139624 ps
CPU time 31.17 seconds
Started Jun 27 06:11:57 PM PDT 24
Finished Jun 27 06:12:36 PM PDT 24
Peak memory 146720 kb
Host smart-830bccb6-5b94-4907-88f4-69983b4807cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386928184 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 370.prim_prince_test.2386928184
Directory /workspace/370.prim_prince_test/latest

Test location /workspace/coverage/default/371.prim_prince_test.880266687
Short name T470
Test name
Test status
Simulation time 2859110398 ps
CPU time 47.71 seconds
Started Jun 27 06:11:59 PM PDT 24
Finished Jun 27 06:13:00 PM PDT 24
Peak memory 146804 kb
Host smart-d823f62d-b6d9-4aa5-bd3a-db022764891e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880266687 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 371.prim_prince_test.880266687
Directory /workspace/371.prim_prince_test/latest

Test location /workspace/coverage/default/372.prim_prince_test.1272895290
Short name T481
Test name
Test status
Simulation time 1327041842 ps
CPU time 22.52 seconds
Started Jun 27 06:11:57 PM PDT 24
Finished Jun 27 06:12:26 PM PDT 24
Peak memory 146736 kb
Host smart-21ff0937-e82a-4a9e-868f-8719b547052e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272895290 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 372.prim_prince_test.1272895290
Directory /workspace/372.prim_prince_test/latest

Test location /workspace/coverage/default/373.prim_prince_test.116126302
Short name T221
Test name
Test status
Simulation time 1907152850 ps
CPU time 32.42 seconds
Started Jun 27 06:11:58 PM PDT 24
Finished Jun 27 06:12:40 PM PDT 24
Peak memory 146748 kb
Host smart-41f0fd2b-a2c8-47c0-8e5a-08b6c24ff285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116126302 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 373.prim_prince_test.116126302
Directory /workspace/373.prim_prince_test/latest

Test location /workspace/coverage/default/374.prim_prince_test.1953213856
Short name T97
Test name
Test status
Simulation time 1324673348 ps
CPU time 22.74 seconds
Started Jun 27 06:11:59 PM PDT 24
Finished Jun 27 06:12:30 PM PDT 24
Peak memory 146744 kb
Host smart-c0e43a5a-7580-4096-900d-25c167e68f3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953213856 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 374.prim_prince_test.1953213856
Directory /workspace/374.prim_prince_test/latest

Test location /workspace/coverage/default/375.prim_prince_test.1933280916
Short name T265
Test name
Test status
Simulation time 1802373379 ps
CPU time 30.86 seconds
Started Jun 27 06:12:00 PM PDT 24
Finished Jun 27 06:12:42 PM PDT 24
Peak memory 146708 kb
Host smart-10d1bce7-38e8-4a8a-918c-083f345f6caa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933280916 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 375.prim_prince_test.1933280916
Directory /workspace/375.prim_prince_test/latest

Test location /workspace/coverage/default/376.prim_prince_test.3648633838
Short name T355
Test name
Test status
Simulation time 1200117324 ps
CPU time 20.23 seconds
Started Jun 27 06:11:57 PM PDT 24
Finished Jun 27 06:12:23 PM PDT 24
Peak memory 146732 kb
Host smart-94394dd0-1da5-4090-8750-74ba52ff9a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648633838 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 376.prim_prince_test.3648633838
Directory /workspace/376.prim_prince_test/latest

Test location /workspace/coverage/default/377.prim_prince_test.3448965267
Short name T121
Test name
Test status
Simulation time 2135687311 ps
CPU time 35.81 seconds
Started Jun 27 06:11:59 PM PDT 24
Finished Jun 27 06:12:45 PM PDT 24
Peak memory 146736 kb
Host smart-12d5cdd7-7472-4f08-b8c9-d8363e3b1c22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448965267 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 377.prim_prince_test.3448965267
Directory /workspace/377.prim_prince_test/latest

Test location /workspace/coverage/default/378.prim_prince_test.2965868689
Short name T82
Test name
Test status
Simulation time 2386382064 ps
CPU time 40.16 seconds
Started Jun 27 06:11:57 PM PDT 24
Finished Jun 27 06:12:48 PM PDT 24
Peak memory 146864 kb
Host smart-bf5fc678-6ee4-4fb5-a58e-fbdc2b7a767c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965868689 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 378.prim_prince_test.2965868689
Directory /workspace/378.prim_prince_test/latest

Test location /workspace/coverage/default/379.prim_prince_test.3636370005
Short name T419
Test name
Test status
Simulation time 3542473821 ps
CPU time 59.62 seconds
Started Jun 27 06:11:58 PM PDT 24
Finished Jun 27 06:13:12 PM PDT 24
Peak memory 146804 kb
Host smart-ed31ba95-726b-472c-b19a-7c8cefed6399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636370005 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 379.prim_prince_test.3636370005
Directory /workspace/379.prim_prince_test/latest

Test location /workspace/coverage/default/38.prim_prince_test.2628661853
Short name T338
Test name
Test status
Simulation time 3104791007 ps
CPU time 52.66 seconds
Started Jun 27 06:10:12 PM PDT 24
Finished Jun 27 06:11:18 PM PDT 24
Peak memory 146796 kb
Host smart-4a2d7627-9a08-4d8b-b93e-83c6e250c304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628661853 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_prince_test.2628661853
Directory /workspace/38.prim_prince_test/latest

Test location /workspace/coverage/default/380.prim_prince_test.1757501031
Short name T462
Test name
Test status
Simulation time 1068409068 ps
CPU time 18.34 seconds
Started Jun 27 06:11:59 PM PDT 24
Finished Jun 27 06:12:24 PM PDT 24
Peak memory 146732 kb
Host smart-efd2f192-1226-4774-a346-d806c764a324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757501031 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 380.prim_prince_test.1757501031
Directory /workspace/380.prim_prince_test/latest

Test location /workspace/coverage/default/381.prim_prince_test.1625243986
Short name T269
Test name
Test status
Simulation time 1569410967 ps
CPU time 25.56 seconds
Started Jun 27 06:11:58 PM PDT 24
Finished Jun 27 06:12:32 PM PDT 24
Peak memory 146736 kb
Host smart-866baaa6-7a9c-4d2b-ab7c-c13c1f399d44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625243986 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 381.prim_prince_test.1625243986
Directory /workspace/381.prim_prince_test/latest

Test location /workspace/coverage/default/382.prim_prince_test.4219828610
Short name T45
Test name
Test status
Simulation time 2583168112 ps
CPU time 43.42 seconds
Started Jun 27 06:11:59 PM PDT 24
Finished Jun 27 06:12:55 PM PDT 24
Peak memory 146796 kb
Host smart-4ebd68d2-a083-4417-99ac-c4ad7690585d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219828610 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 382.prim_prince_test.4219828610
Directory /workspace/382.prim_prince_test/latest

Test location /workspace/coverage/default/383.prim_prince_test.3794373154
Short name T69
Test name
Test status
Simulation time 2374988794 ps
CPU time 39.4 seconds
Started Jun 27 06:11:58 PM PDT 24
Finished Jun 27 06:12:48 PM PDT 24
Peak memory 146736 kb
Host smart-70ebf233-e159-45f3-a7bf-6cd373795197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794373154 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 383.prim_prince_test.3794373154
Directory /workspace/383.prim_prince_test/latest

Test location /workspace/coverage/default/384.prim_prince_test.213714897
Short name T154
Test name
Test status
Simulation time 1289034284 ps
CPU time 22.55 seconds
Started Jun 27 06:12:00 PM PDT 24
Finished Jun 27 06:12:32 PM PDT 24
Peak memory 146708 kb
Host smart-07c32635-1d6a-443e-a161-8576078df000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213714897 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 384.prim_prince_test.213714897
Directory /workspace/384.prim_prince_test/latest

Test location /workspace/coverage/default/385.prim_prince_test.2342473489
Short name T474
Test name
Test status
Simulation time 848955676 ps
CPU time 14.51 seconds
Started Jun 27 06:12:04 PM PDT 24
Finished Jun 27 06:12:23 PM PDT 24
Peak memory 146724 kb
Host smart-590e2a41-8260-45f7-85df-64387ae7c8e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342473489 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 385.prim_prince_test.2342473489
Directory /workspace/385.prim_prince_test/latest

Test location /workspace/coverage/default/386.prim_prince_test.3175125048
Short name T340
Test name
Test status
Simulation time 2178713853 ps
CPU time 36.81 seconds
Started Jun 27 06:12:00 PM PDT 24
Finished Jun 27 06:12:49 PM PDT 24
Peak memory 146748 kb
Host smart-67d669f2-816e-4b3d-adab-9b2b9935c770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175125048 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 386.prim_prince_test.3175125048
Directory /workspace/386.prim_prince_test/latest

Test location /workspace/coverage/default/387.prim_prince_test.499234737
Short name T260
Test name
Test status
Simulation time 3651962093 ps
CPU time 61.01 seconds
Started Jun 27 06:11:58 PM PDT 24
Finished Jun 27 06:13:16 PM PDT 24
Peak memory 146880 kb
Host smart-aa0fa88f-b367-4c4a-b25c-c84656f50c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499234737 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 387.prim_prince_test.499234737
Directory /workspace/387.prim_prince_test/latest

Test location /workspace/coverage/default/388.prim_prince_test.2867670707
Short name T136
Test name
Test status
Simulation time 3317570824 ps
CPU time 53.3 seconds
Started Jun 27 06:11:58 PM PDT 24
Finished Jun 27 06:13:04 PM PDT 24
Peak memory 146768 kb
Host smart-aa8d35ef-09c7-4817-a3a1-aff3819c15df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867670707 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 388.prim_prince_test.2867670707
Directory /workspace/388.prim_prince_test/latest

Test location /workspace/coverage/default/389.prim_prince_test.2151814456
Short name T23
Test name
Test status
Simulation time 2213598245 ps
CPU time 38.1 seconds
Started Jun 27 06:12:01 PM PDT 24
Finished Jun 27 06:12:52 PM PDT 24
Peak memory 146524 kb
Host smart-b2ef0f97-d384-4dfa-96e5-0fcc693817dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151814456 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 389.prim_prince_test.2151814456
Directory /workspace/389.prim_prince_test/latest

Test location /workspace/coverage/default/39.prim_prince_test.3853055176
Short name T230
Test name
Test status
Simulation time 2398854217 ps
CPU time 41.09 seconds
Started Jun 27 06:10:15 PM PDT 24
Finished Jun 27 06:11:07 PM PDT 24
Peak memory 146816 kb
Host smart-f438ac5a-3f45-47f6-a665-e796c4e20038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853055176 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_prince_test.3853055176
Directory /workspace/39.prim_prince_test/latest

Test location /workspace/coverage/default/390.prim_prince_test.1399865473
Short name T456
Test name
Test status
Simulation time 2509272322 ps
CPU time 41.16 seconds
Started Jun 27 06:11:58 PM PDT 24
Finished Jun 27 06:12:50 PM PDT 24
Peak memory 146804 kb
Host smart-7d16f1cb-b794-4079-9a3b-f93241754d65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399865473 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 390.prim_prince_test.1399865473
Directory /workspace/390.prim_prince_test/latest

Test location /workspace/coverage/default/391.prim_prince_test.2000319800
Short name T496
Test name
Test status
Simulation time 3573087499 ps
CPU time 60 seconds
Started Jun 27 06:11:58 PM PDT 24
Finished Jun 27 06:13:15 PM PDT 24
Peak memory 146800 kb
Host smart-7bcfc44e-b07a-487d-84a9-509834be85f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000319800 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 391.prim_prince_test.2000319800
Directory /workspace/391.prim_prince_test/latest

Test location /workspace/coverage/default/392.prim_prince_test.2427928343
Short name T171
Test name
Test status
Simulation time 3731714566 ps
CPU time 59.81 seconds
Started Jun 27 06:11:59 PM PDT 24
Finished Jun 27 06:13:12 PM PDT 24
Peak memory 146800 kb
Host smart-7f11f394-d379-4c1f-9d12-c19e153d42f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427928343 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 392.prim_prince_test.2427928343
Directory /workspace/392.prim_prince_test/latest

Test location /workspace/coverage/default/393.prim_prince_test.3077738454
Short name T130
Test name
Test status
Simulation time 1854745787 ps
CPU time 30.95 seconds
Started Jun 27 06:12:00 PM PDT 24
Finished Jun 27 06:12:40 PM PDT 24
Peak memory 146736 kb
Host smart-c65cf6e7-9192-46f2-ac17-d714b0f938cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077738454 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 393.prim_prince_test.3077738454
Directory /workspace/393.prim_prince_test/latest

Test location /workspace/coverage/default/394.prim_prince_test.3683934065
Short name T477
Test name
Test status
Simulation time 2206337563 ps
CPU time 36.67 seconds
Started Jun 27 06:11:58 PM PDT 24
Finished Jun 27 06:12:44 PM PDT 24
Peak memory 146808 kb
Host smart-6d811fa1-ac14-4ce3-ac85-dc75975852a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683934065 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 394.prim_prince_test.3683934065
Directory /workspace/394.prim_prince_test/latest

Test location /workspace/coverage/default/395.prim_prince_test.748788600
Short name T70
Test name
Test status
Simulation time 1024883573 ps
CPU time 17.54 seconds
Started Jun 27 06:12:00 PM PDT 24
Finished Jun 27 06:12:25 PM PDT 24
Peak memory 146752 kb
Host smart-087d4405-2252-4e11-8f6f-03edd5cc4963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748788600 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 395.prim_prince_test.748788600
Directory /workspace/395.prim_prince_test/latest

Test location /workspace/coverage/default/396.prim_prince_test.224193025
Short name T242
Test name
Test status
Simulation time 3696745724 ps
CPU time 61.51 seconds
Started Jun 27 06:11:59 PM PDT 24
Finished Jun 27 06:13:17 PM PDT 24
Peak memory 146812 kb
Host smart-5e5f401c-1c0a-4fe6-b3d5-a95bd7325d4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224193025 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 396.prim_prince_test.224193025
Directory /workspace/396.prim_prince_test/latest

Test location /workspace/coverage/default/397.prim_prince_test.3466589483
Short name T455
Test name
Test status
Simulation time 1425558612 ps
CPU time 24.63 seconds
Started Jun 27 06:11:59 PM PDT 24
Finished Jun 27 06:12:32 PM PDT 24
Peak memory 146740 kb
Host smart-ebf9c0b6-3103-4a28-9758-bb0d9fccd020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466589483 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 397.prim_prince_test.3466589483
Directory /workspace/397.prim_prince_test/latest

Test location /workspace/coverage/default/398.prim_prince_test.2895030218
Short name T180
Test name
Test status
Simulation time 3187476275 ps
CPU time 52.48 seconds
Started Jun 27 06:11:58 PM PDT 24
Finished Jun 27 06:13:05 PM PDT 24
Peak memory 146804 kb
Host smart-eb3e6e7f-fbe3-4d35-a771-f999014aec46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895030218 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 398.prim_prince_test.2895030218
Directory /workspace/398.prim_prince_test/latest

Test location /workspace/coverage/default/399.prim_prince_test.4012172370
Short name T253
Test name
Test status
Simulation time 2489051995 ps
CPU time 41.78 seconds
Started Jun 27 06:11:58 PM PDT 24
Finished Jun 27 06:12:52 PM PDT 24
Peak memory 146800 kb
Host smart-56050788-fe8c-40e6-9924-bad4aebc8248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012172370 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 399.prim_prince_test.4012172370
Directory /workspace/399.prim_prince_test/latest

Test location /workspace/coverage/default/4.prim_prince_test.232647652
Short name T124
Test name
Test status
Simulation time 1842444063 ps
CPU time 30.46 seconds
Started Jun 27 06:10:05 PM PDT 24
Finished Jun 27 06:10:44 PM PDT 24
Peak memory 146756 kb
Host smart-fc0c08d1-6d58-4f6a-8ccb-90ccd6df25cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232647652 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_prince_test.232647652
Directory /workspace/4.prim_prince_test/latest

Test location /workspace/coverage/default/40.prim_prince_test.1482777074
Short name T308
Test name
Test status
Simulation time 3330274700 ps
CPU time 55.17 seconds
Started Jun 27 06:10:12 PM PDT 24
Finished Jun 27 06:11:20 PM PDT 24
Peak memory 146808 kb
Host smart-216c1621-6183-4c67-9374-ea9684d26f49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482777074 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_prince_test.1482777074
Directory /workspace/40.prim_prince_test/latest

Test location /workspace/coverage/default/400.prim_prince_test.313071092
Short name T444
Test name
Test status
Simulation time 2420102496 ps
CPU time 41.54 seconds
Started Jun 27 06:12:00 PM PDT 24
Finished Jun 27 06:12:56 PM PDT 24
Peak memory 146776 kb
Host smart-5d327638-6f5f-4bdf-bcd4-70392eed9189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313071092 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 400.prim_prince_test.313071092
Directory /workspace/400.prim_prince_test/latest

Test location /workspace/coverage/default/401.prim_prince_test.629441980
Short name T349
Test name
Test status
Simulation time 2272951865 ps
CPU time 38.33 seconds
Started Jun 27 06:12:00 PM PDT 24
Finished Jun 27 06:12:51 PM PDT 24
Peak memory 146808 kb
Host smart-15448d91-4406-4d8e-baee-042a346e4766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629441980 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 401.prim_prince_test.629441980
Directory /workspace/401.prim_prince_test/latest

Test location /workspace/coverage/default/402.prim_prince_test.2991900021
Short name T307
Test name
Test status
Simulation time 1731428873 ps
CPU time 29.07 seconds
Started Jun 27 06:11:58 PM PDT 24
Finished Jun 27 06:12:36 PM PDT 24
Peak memory 146724 kb
Host smart-09e70436-3b34-4c89-a829-f9f421b80df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991900021 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 402.prim_prince_test.2991900021
Directory /workspace/402.prim_prince_test/latest

Test location /workspace/coverage/default/403.prim_prince_test.1065819095
Short name T27
Test name
Test status
Simulation time 1781409765 ps
CPU time 29.13 seconds
Started Jun 27 06:11:58 PM PDT 24
Finished Jun 27 06:12:35 PM PDT 24
Peak memory 146728 kb
Host smart-348c8f8a-9aa7-4be4-b36f-63b45a3693d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065819095 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 403.prim_prince_test.1065819095
Directory /workspace/403.prim_prince_test/latest

Test location /workspace/coverage/default/404.prim_prince_test.3784638891
Short name T468
Test name
Test status
Simulation time 1175109521 ps
CPU time 19.82 seconds
Started Jun 27 06:11:57 PM PDT 24
Finished Jun 27 06:12:23 PM PDT 24
Peak memory 146748 kb
Host smart-99e338e9-0b7a-4ab1-961f-0cbbaea8a390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784638891 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 404.prim_prince_test.3784638891
Directory /workspace/404.prim_prince_test/latest

Test location /workspace/coverage/default/405.prim_prince_test.2023721237
Short name T400
Test name
Test status
Simulation time 1172617471 ps
CPU time 20.13 seconds
Started Jun 27 06:12:02 PM PDT 24
Finished Jun 27 06:12:30 PM PDT 24
Peak memory 146300 kb
Host smart-b535408c-8029-4857-ab46-e3be0cb0d294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023721237 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 405.prim_prince_test.2023721237
Directory /workspace/405.prim_prince_test/latest

Test location /workspace/coverage/default/406.prim_prince_test.428866482
Short name T26
Test name
Test status
Simulation time 2165890878 ps
CPU time 36.4 seconds
Started Jun 27 06:12:00 PM PDT 24
Finished Jun 27 06:12:48 PM PDT 24
Peak memory 146776 kb
Host smart-ecebbf58-de1b-4153-b86b-68f4b7e95976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428866482 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 406.prim_prince_test.428866482
Directory /workspace/406.prim_prince_test/latest

Test location /workspace/coverage/default/407.prim_prince_test.721559916
Short name T178
Test name
Test status
Simulation time 1180292231 ps
CPU time 20.08 seconds
Started Jun 27 06:12:00 PM PDT 24
Finished Jun 27 06:12:28 PM PDT 24
Peak memory 146748 kb
Host smart-1c574a9b-8383-4caf-a367-aadc6a38d747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721559916 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 407.prim_prince_test.721559916
Directory /workspace/407.prim_prince_test/latest

Test location /workspace/coverage/default/408.prim_prince_test.3443049873
Short name T65
Test name
Test status
Simulation time 3192307146 ps
CPU time 55.22 seconds
Started Jun 27 06:12:00 PM PDT 24
Finished Jun 27 06:13:13 PM PDT 24
Peak memory 146760 kb
Host smart-7a7da0a9-15f4-4086-aae1-19fa82d40bd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443049873 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 408.prim_prince_test.3443049873
Directory /workspace/408.prim_prince_test/latest

Test location /workspace/coverage/default/409.prim_prince_test.1385523870
Short name T498
Test name
Test status
Simulation time 2366472586 ps
CPU time 39.91 seconds
Started Jun 27 06:12:00 PM PDT 24
Finished Jun 27 06:12:52 PM PDT 24
Peak memory 146720 kb
Host smart-d13092b3-6711-4aa6-9f82-90dc252c465f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385523870 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 409.prim_prince_test.1385523870
Directory /workspace/409.prim_prince_test/latest

Test location /workspace/coverage/default/41.prim_prince_test.1153606914
Short name T259
Test name
Test status
Simulation time 2425544278 ps
CPU time 40.14 seconds
Started Jun 27 06:10:15 PM PDT 24
Finished Jun 27 06:11:05 PM PDT 24
Peak memory 146752 kb
Host smart-93341d3a-ed8c-49f2-acb2-f0b1c84de8b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153606914 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_prince_test.1153606914
Directory /workspace/41.prim_prince_test/latest

Test location /workspace/coverage/default/410.prim_prince_test.2682176860
Short name T398
Test name
Test status
Simulation time 3695119172 ps
CPU time 63.76 seconds
Started Jun 27 06:11:59 PM PDT 24
Finished Jun 27 06:13:22 PM PDT 24
Peak memory 146784 kb
Host smart-646c03a4-c2f6-4f9e-989c-0072164b5e02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682176860 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 410.prim_prince_test.2682176860
Directory /workspace/410.prim_prince_test/latest

Test location /workspace/coverage/default/411.prim_prince_test.2803087225
Short name T194
Test name
Test status
Simulation time 1764057427 ps
CPU time 29.55 seconds
Started Jun 27 06:11:56 PM PDT 24
Finished Jun 27 06:12:34 PM PDT 24
Peak memory 146724 kb
Host smart-3ae43e6a-bb51-46de-98a3-a095bf55f5ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803087225 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 411.prim_prince_test.2803087225
Directory /workspace/411.prim_prince_test/latest

Test location /workspace/coverage/default/412.prim_prince_test.2500906466
Short name T117
Test name
Test status
Simulation time 1479475297 ps
CPU time 25.01 seconds
Started Jun 27 06:11:59 PM PDT 24
Finished Jun 27 06:12:33 PM PDT 24
Peak memory 146732 kb
Host smart-8156a81d-3bfe-4d81-bf11-9770218fef92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500906466 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 412.prim_prince_test.2500906466
Directory /workspace/412.prim_prince_test/latest

Test location /workspace/coverage/default/413.prim_prince_test.2373725238
Short name T368
Test name
Test status
Simulation time 1943192869 ps
CPU time 32.68 seconds
Started Jun 27 06:12:04 PM PDT 24
Finished Jun 27 06:12:46 PM PDT 24
Peak memory 146724 kb
Host smart-2596c6d8-1cf6-4106-a386-d7d3777a55e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373725238 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 413.prim_prince_test.2373725238
Directory /workspace/413.prim_prince_test/latest

Test location /workspace/coverage/default/414.prim_prince_test.2087899699
Short name T295
Test name
Test status
Simulation time 1096883728 ps
CPU time 18.94 seconds
Started Jun 27 06:12:00 PM PDT 24
Finished Jun 27 06:12:27 PM PDT 24
Peak memory 146696 kb
Host smart-f4e35e5a-7557-43e3-8761-9c456019652a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087899699 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 414.prim_prince_test.2087899699
Directory /workspace/414.prim_prince_test/latest

Test location /workspace/coverage/default/415.prim_prince_test.3585626662
Short name T345
Test name
Test status
Simulation time 3392020344 ps
CPU time 56.55 seconds
Started Jun 27 06:12:01 PM PDT 24
Finished Jun 27 06:13:13 PM PDT 24
Peak memory 146784 kb
Host smart-fb6d2439-ec91-4887-b28e-bf2430e872a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585626662 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 415.prim_prince_test.3585626662
Directory /workspace/415.prim_prince_test/latest

Test location /workspace/coverage/default/416.prim_prince_test.391888180
Short name T116
Test name
Test status
Simulation time 3012873006 ps
CPU time 50.29 seconds
Started Jun 27 06:11:58 PM PDT 24
Finished Jun 27 06:13:01 PM PDT 24
Peak memory 146796 kb
Host smart-105732ec-1f51-4e25-92c4-bc7518e7af1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391888180 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 416.prim_prince_test.391888180
Directory /workspace/416.prim_prince_test/latest

Test location /workspace/coverage/default/417.prim_prince_test.3898199220
Short name T67
Test name
Test status
Simulation time 2986273260 ps
CPU time 49.79 seconds
Started Jun 27 06:11:58 PM PDT 24
Finished Jun 27 06:13:02 PM PDT 24
Peak memory 146800 kb
Host smart-6187de08-ae5b-4764-8a4f-f93ebfec1456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898199220 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 417.prim_prince_test.3898199220
Directory /workspace/417.prim_prince_test/latest

Test location /workspace/coverage/default/418.prim_prince_test.1599987662
Short name T193
Test name
Test status
Simulation time 1727274584 ps
CPU time 29.04 seconds
Started Jun 27 06:12:19 PM PDT 24
Finished Jun 27 06:12:57 PM PDT 24
Peak memory 146648 kb
Host smart-bb1338d5-b61e-47fa-b815-0331d83a4fc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599987662 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 418.prim_prince_test.1599987662
Directory /workspace/418.prim_prince_test/latest

Test location /workspace/coverage/default/419.prim_prince_test.3566267319
Short name T106
Test name
Test status
Simulation time 2702801637 ps
CPU time 44.16 seconds
Started Jun 27 06:12:22 PM PDT 24
Finished Jun 27 06:13:18 PM PDT 24
Peak memory 146784 kb
Host smart-0d532ec0-af2a-4d66-aac6-40c7ddd9f459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566267319 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 419.prim_prince_test.3566267319
Directory /workspace/419.prim_prince_test/latest

Test location /workspace/coverage/default/42.prim_prince_test.3398041979
Short name T430
Test name
Test status
Simulation time 1740297457 ps
CPU time 29.29 seconds
Started Jun 27 06:10:12 PM PDT 24
Finished Jun 27 06:10:49 PM PDT 24
Peak memory 146660 kb
Host smart-33b7660a-2f45-498c-8f9f-fee0ad223725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398041979 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_prince_test.3398041979
Directory /workspace/42.prim_prince_test/latest

Test location /workspace/coverage/default/420.prim_prince_test.4040255982
Short name T200
Test name
Test status
Simulation time 1950324528 ps
CPU time 31.96 seconds
Started Jun 27 06:12:15 PM PDT 24
Finished Jun 27 06:12:56 PM PDT 24
Peak memory 146736 kb
Host smart-00380392-cad2-4294-ae3c-532570539e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040255982 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 420.prim_prince_test.4040255982
Directory /workspace/420.prim_prince_test/latest

Test location /workspace/coverage/default/421.prim_prince_test.3677430616
Short name T229
Test name
Test status
Simulation time 3484825452 ps
CPU time 58.79 seconds
Started Jun 27 06:12:15 PM PDT 24
Finished Jun 27 06:13:30 PM PDT 24
Peak memory 146800 kb
Host smart-d1c62ecc-d410-4add-8697-02ed713039c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677430616 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 421.prim_prince_test.3677430616
Directory /workspace/421.prim_prince_test/latest

Test location /workspace/coverage/default/422.prim_prince_test.1175882857
Short name T112
Test name
Test status
Simulation time 2534985163 ps
CPU time 42.43 seconds
Started Jun 27 06:12:17 PM PDT 24
Finished Jun 27 06:13:12 PM PDT 24
Peak memory 146796 kb
Host smart-896fefa4-1822-4312-b778-4b5f50d418f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175882857 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 422.prim_prince_test.1175882857
Directory /workspace/422.prim_prince_test/latest

Test location /workspace/coverage/default/423.prim_prince_test.387554535
Short name T203
Test name
Test status
Simulation time 3364054855 ps
CPU time 56.38 seconds
Started Jun 27 06:12:18 PM PDT 24
Finished Jun 27 06:13:29 PM PDT 24
Peak memory 146808 kb
Host smart-9f6a81e9-d888-4a44-95ef-50e4e4f10e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387554535 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 423.prim_prince_test.387554535
Directory /workspace/423.prim_prince_test/latest

Test location /workspace/coverage/default/424.prim_prince_test.1524197658
Short name T199
Test name
Test status
Simulation time 2456601079 ps
CPU time 42.85 seconds
Started Jun 27 06:12:17 PM PDT 24
Finished Jun 27 06:13:13 PM PDT 24
Peak memory 146768 kb
Host smart-9fba3202-9d59-43ac-a3c8-af14bed91791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524197658 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 424.prim_prince_test.1524197658
Directory /workspace/424.prim_prince_test/latest

Test location /workspace/coverage/default/425.prim_prince_test.2496906926
Short name T440
Test name
Test status
Simulation time 1749557484 ps
CPU time 29.55 seconds
Started Jun 27 06:12:23 PM PDT 24
Finished Jun 27 06:13:02 PM PDT 24
Peak memory 146124 kb
Host smart-a54e9afc-c76f-4565-9be4-20dbf8b9d122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496906926 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 425.prim_prince_test.2496906926
Directory /workspace/425.prim_prince_test/latest

Test location /workspace/coverage/default/426.prim_prince_test.3304616509
Short name T286
Test name
Test status
Simulation time 2223210718 ps
CPU time 36.68 seconds
Started Jun 27 06:12:15 PM PDT 24
Finished Jun 27 06:13:02 PM PDT 24
Peak memory 146820 kb
Host smart-a4a99152-d951-44f5-95cd-e2fb89c59a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304616509 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 426.prim_prince_test.3304616509
Directory /workspace/426.prim_prince_test/latest

Test location /workspace/coverage/default/427.prim_prince_test.3870958813
Short name T353
Test name
Test status
Simulation time 3696544209 ps
CPU time 61.31 seconds
Started Jun 27 06:12:17 PM PDT 24
Finished Jun 27 06:13:34 PM PDT 24
Peak memory 146736 kb
Host smart-52f52b08-5270-41fd-9311-82dd98168cf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870958813 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 427.prim_prince_test.3870958813
Directory /workspace/427.prim_prince_test/latest

Test location /workspace/coverage/default/428.prim_prince_test.3223587243
Short name T463
Test name
Test status
Simulation time 2421452070 ps
CPU time 38.7 seconds
Started Jun 27 06:12:14 PM PDT 24
Finished Jun 27 06:13:02 PM PDT 24
Peak memory 146792 kb
Host smart-e1d2c323-63fb-4911-9d58-9a9b31178faa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223587243 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 428.prim_prince_test.3223587243
Directory /workspace/428.prim_prince_test/latest

Test location /workspace/coverage/default/429.prim_prince_test.2500379466
Short name T4
Test name
Test status
Simulation time 1307900620 ps
CPU time 21.51 seconds
Started Jun 27 06:12:15 PM PDT 24
Finished Jun 27 06:12:43 PM PDT 24
Peak memory 146748 kb
Host smart-5e20b928-09b6-4585-b56f-bfbeec3bf9ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500379466 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 429.prim_prince_test.2500379466
Directory /workspace/429.prim_prince_test/latest

Test location /workspace/coverage/default/43.prim_prince_test.1241901375
Short name T333
Test name
Test status
Simulation time 2947244813 ps
CPU time 49.56 seconds
Started Jun 27 06:10:10 PM PDT 24
Finished Jun 27 06:11:12 PM PDT 24
Peak memory 146796 kb
Host smart-ad5685bd-0622-4c37-924e-0b0877f377bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241901375 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_prince_test.1241901375
Directory /workspace/43.prim_prince_test/latest

Test location /workspace/coverage/default/430.prim_prince_test.1021611511
Short name T195
Test name
Test status
Simulation time 3057906040 ps
CPU time 51.24 seconds
Started Jun 27 06:12:19 PM PDT 24
Finished Jun 27 06:13:25 PM PDT 24
Peak memory 146800 kb
Host smart-094baad4-63e2-45ac-aff0-461cb0a294fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021611511 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 430.prim_prince_test.1021611511
Directory /workspace/430.prim_prince_test/latest

Test location /workspace/coverage/default/431.prim_prince_test.3456004786
Short name T282
Test name
Test status
Simulation time 2555410314 ps
CPU time 42.57 seconds
Started Jun 27 06:12:16 PM PDT 24
Finished Jun 27 06:13:11 PM PDT 24
Peak memory 146812 kb
Host smart-3b2dd614-8a60-4a28-9fc4-6aeb00669516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456004786 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 431.prim_prince_test.3456004786
Directory /workspace/431.prim_prince_test/latest

Test location /workspace/coverage/default/432.prim_prince_test.1918897171
Short name T109
Test name
Test status
Simulation time 3696671330 ps
CPU time 61.99 seconds
Started Jun 27 06:12:19 PM PDT 24
Finished Jun 27 06:13:37 PM PDT 24
Peak memory 146800 kb
Host smart-133ce603-d174-4306-9bc1-0a035b1f6d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918897171 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 432.prim_prince_test.1918897171
Directory /workspace/432.prim_prince_test/latest

Test location /workspace/coverage/default/433.prim_prince_test.4251383379
Short name T374
Test name
Test status
Simulation time 1120314283 ps
CPU time 19.24 seconds
Started Jun 27 06:12:18 PM PDT 24
Finished Jun 27 06:12:44 PM PDT 24
Peak memory 146740 kb
Host smart-5c554c08-71b0-43b0-9fb4-ecd5d3d9eb8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251383379 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 433.prim_prince_test.4251383379
Directory /workspace/433.prim_prince_test/latest

Test location /workspace/coverage/default/434.prim_prince_test.2905574480
Short name T300
Test name
Test status
Simulation time 2738330034 ps
CPU time 45.53 seconds
Started Jun 27 06:12:21 PM PDT 24
Finished Jun 27 06:13:19 PM PDT 24
Peak memory 146800 kb
Host smart-2a07b1bf-48be-4460-bcfb-8fa3c8cdf54c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905574480 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 434.prim_prince_test.2905574480
Directory /workspace/434.prim_prince_test/latest

Test location /workspace/coverage/default/435.prim_prince_test.2026580555
Short name T429
Test name
Test status
Simulation time 2602835262 ps
CPU time 43.07 seconds
Started Jun 27 06:12:13 PM PDT 24
Finished Jun 27 06:13:07 PM PDT 24
Peak memory 146780 kb
Host smart-0c441d9f-5a24-4e84-985e-a6fa179942f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026580555 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 435.prim_prince_test.2026580555
Directory /workspace/435.prim_prince_test/latest

Test location /workspace/coverage/default/436.prim_prince_test.3603737458
Short name T297
Test name
Test status
Simulation time 2858857913 ps
CPU time 47.29 seconds
Started Jun 27 06:12:15 PM PDT 24
Finished Jun 27 06:13:15 PM PDT 24
Peak memory 146720 kb
Host smart-d51ec8e4-4907-4129-a47b-66c63e787dd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603737458 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 436.prim_prince_test.3603737458
Directory /workspace/436.prim_prince_test/latest

Test location /workspace/coverage/default/437.prim_prince_test.268670120
Short name T202
Test name
Test status
Simulation time 993888091 ps
CPU time 16.89 seconds
Started Jun 27 06:12:14 PM PDT 24
Finished Jun 27 06:12:37 PM PDT 24
Peak memory 146720 kb
Host smart-b6080e38-1fac-4645-a0f8-30c11510c810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268670120 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 437.prim_prince_test.268670120
Directory /workspace/437.prim_prince_test/latest

Test location /workspace/coverage/default/438.prim_prince_test.3432025046
Short name T96
Test name
Test status
Simulation time 2371733397 ps
CPU time 38.98 seconds
Started Jun 27 06:12:15 PM PDT 24
Finished Jun 27 06:13:04 PM PDT 24
Peak memory 146812 kb
Host smart-01003443-e06a-4e9a-9be2-2ef6ef7af2b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432025046 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 438.prim_prince_test.3432025046
Directory /workspace/438.prim_prince_test/latest

Test location /workspace/coverage/default/439.prim_prince_test.2004685626
Short name T367
Test name
Test status
Simulation time 2651643700 ps
CPU time 44.56 seconds
Started Jun 27 06:12:16 PM PDT 24
Finished Jun 27 06:13:12 PM PDT 24
Peak memory 146808 kb
Host smart-0e8b2411-6712-4616-b228-80a2246c6066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004685626 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 439.prim_prince_test.2004685626
Directory /workspace/439.prim_prince_test/latest

Test location /workspace/coverage/default/44.prim_prince_test.868154741
Short name T402
Test name
Test status
Simulation time 3329413760 ps
CPU time 56.98 seconds
Started Jun 27 06:10:14 PM PDT 24
Finished Jun 27 06:11:26 PM PDT 24
Peak memory 146804 kb
Host smart-12dfb1bd-d9fc-4f63-8003-dd3e3c9ce01d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868154741 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_prince_test.868154741
Directory /workspace/44.prim_prince_test/latest

Test location /workspace/coverage/default/440.prim_prince_test.1490319027
Short name T435
Test name
Test status
Simulation time 2580808033 ps
CPU time 43.4 seconds
Started Jun 27 06:12:23 PM PDT 24
Finished Jun 27 06:13:19 PM PDT 24
Peak memory 146800 kb
Host smart-5ae9bbcc-86f6-427d-9287-488a5dd7245b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490319027 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 440.prim_prince_test.1490319027
Directory /workspace/440.prim_prince_test/latest

Test location /workspace/coverage/default/441.prim_prince_test.1911161130
Short name T161
Test name
Test status
Simulation time 1865554145 ps
CPU time 30.45 seconds
Started Jun 27 06:12:18 PM PDT 24
Finished Jun 27 06:12:57 PM PDT 24
Peak memory 146720 kb
Host smart-ab19f567-11f6-454e-94f2-29be04bada5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911161130 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 441.prim_prince_test.1911161130
Directory /workspace/441.prim_prince_test/latest

Test location /workspace/coverage/default/442.prim_prince_test.2206406783
Short name T75
Test name
Test status
Simulation time 3713470521 ps
CPU time 59.53 seconds
Started Jun 27 06:12:16 PM PDT 24
Finished Jun 27 06:13:29 PM PDT 24
Peak memory 146808 kb
Host smart-26d4a575-f534-4640-9b42-71f4843c1dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206406783 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 442.prim_prince_test.2206406783
Directory /workspace/442.prim_prince_test/latest

Test location /workspace/coverage/default/443.prim_prince_test.1310177399
Short name T399
Test name
Test status
Simulation time 2057024631 ps
CPU time 34.88 seconds
Started Jun 27 06:12:22 PM PDT 24
Finished Jun 27 06:13:08 PM PDT 24
Peak memory 146720 kb
Host smart-319ccac3-458a-4cdc-a521-020a5cf077cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310177399 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 443.prim_prince_test.1310177399
Directory /workspace/443.prim_prince_test/latest

Test location /workspace/coverage/default/444.prim_prince_test.1840512008
Short name T228
Test name
Test status
Simulation time 3572241135 ps
CPU time 59.37 seconds
Started Jun 27 06:12:13 PM PDT 24
Finished Jun 27 06:13:27 PM PDT 24
Peak memory 146792 kb
Host smart-dbda5a56-283f-45dc-82ad-6bd5430441eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840512008 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 444.prim_prince_test.1840512008
Directory /workspace/444.prim_prince_test/latest

Test location /workspace/coverage/default/445.prim_prince_test.1668455412
Short name T312
Test name
Test status
Simulation time 3244455159 ps
CPU time 53.6 seconds
Started Jun 27 06:12:19 PM PDT 24
Finished Jun 27 06:13:27 PM PDT 24
Peak memory 146784 kb
Host smart-6a76de9b-2156-45a3-bf22-00beef788653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668455412 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 445.prim_prince_test.1668455412
Directory /workspace/445.prim_prince_test/latest

Test location /workspace/coverage/default/446.prim_prince_test.3845699333
Short name T454
Test name
Test status
Simulation time 2058442860 ps
CPU time 34.1 seconds
Started Jun 27 06:12:15 PM PDT 24
Finished Jun 27 06:12:59 PM PDT 24
Peak memory 146736 kb
Host smart-3d5d3cce-a6bd-4a29-a7d8-2a5322380174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845699333 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 446.prim_prince_test.3845699333
Directory /workspace/446.prim_prince_test/latest

Test location /workspace/coverage/default/447.prim_prince_test.1318308485
Short name T189
Test name
Test status
Simulation time 2979581918 ps
CPU time 49.33 seconds
Started Jun 27 06:12:13 PM PDT 24
Finished Jun 27 06:13:13 PM PDT 24
Peak memory 146784 kb
Host smart-4c37b2a4-1fc3-4d24-a119-d10f4b28e5ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318308485 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 447.prim_prince_test.1318308485
Directory /workspace/447.prim_prince_test/latest

Test location /workspace/coverage/default/448.prim_prince_test.896987324
Short name T482
Test name
Test status
Simulation time 1358008638 ps
CPU time 22.56 seconds
Started Jun 27 06:12:15 PM PDT 24
Finished Jun 27 06:12:45 PM PDT 24
Peak memory 146732 kb
Host smart-3866f83f-b233-4cf0-9607-62b928153a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896987324 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 448.prim_prince_test.896987324
Directory /workspace/448.prim_prince_test/latest

Test location /workspace/coverage/default/449.prim_prince_test.139237477
Short name T325
Test name
Test status
Simulation time 1295644425 ps
CPU time 21.42 seconds
Started Jun 27 06:12:15 PM PDT 24
Finished Jun 27 06:12:43 PM PDT 24
Peak memory 146744 kb
Host smart-af0a63c5-1980-4dfa-a02f-005e109250f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139237477 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 449.prim_prince_test.139237477
Directory /workspace/449.prim_prince_test/latest

Test location /workspace/coverage/default/45.prim_prince_test.4010768392
Short name T390
Test name
Test status
Simulation time 1852200450 ps
CPU time 30.67 seconds
Started Jun 27 06:10:13 PM PDT 24
Finished Jun 27 06:10:52 PM PDT 24
Peak memory 146036 kb
Host smart-7e112437-3f26-452a-97f4-a639a590c229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010768392 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_prince_test.4010768392
Directory /workspace/45.prim_prince_test/latest

Test location /workspace/coverage/default/450.prim_prince_test.4030979655
Short name T263
Test name
Test status
Simulation time 3254822428 ps
CPU time 54.7 seconds
Started Jun 27 06:12:17 PM PDT 24
Finished Jun 27 06:13:27 PM PDT 24
Peak memory 146800 kb
Host smart-004988e7-56f4-40ac-a2c6-ffe39c353926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030979655 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 450.prim_prince_test.4030979655
Directory /workspace/450.prim_prince_test/latest

Test location /workspace/coverage/default/451.prim_prince_test.3008677260
Short name T224
Test name
Test status
Simulation time 2000005114 ps
CPU time 33.32 seconds
Started Jun 27 06:12:17 PM PDT 24
Finished Jun 27 06:13:01 PM PDT 24
Peak memory 146728 kb
Host smart-ab3169be-8db4-4eb3-97a7-cfbb0961202b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008677260 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 451.prim_prince_test.3008677260
Directory /workspace/451.prim_prince_test/latest

Test location /workspace/coverage/default/452.prim_prince_test.1809764693
Short name T344
Test name
Test status
Simulation time 3241282857 ps
CPU time 53.98 seconds
Started Jun 27 06:12:19 PM PDT 24
Finished Jun 27 06:13:29 PM PDT 24
Peak memory 146812 kb
Host smart-64440ffb-dad0-4bb5-8f59-726e051ca30c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809764693 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 452.prim_prince_test.1809764693
Directory /workspace/452.prim_prince_test/latest

Test location /workspace/coverage/default/453.prim_prince_test.4064479473
Short name T364
Test name
Test status
Simulation time 3744838486 ps
CPU time 61.81 seconds
Started Jun 27 06:12:16 PM PDT 24
Finished Jun 27 06:13:35 PM PDT 24
Peak memory 146880 kb
Host smart-0871be2e-1bad-4e60-bf7d-da601b869292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064479473 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 453.prim_prince_test.4064479473
Directory /workspace/453.prim_prince_test/latest

Test location /workspace/coverage/default/454.prim_prince_test.3134304130
Short name T122
Test name
Test status
Simulation time 1081010351 ps
CPU time 18.47 seconds
Started Jun 27 06:12:17 PM PDT 24
Finished Jun 27 06:12:43 PM PDT 24
Peak memory 146672 kb
Host smart-da682899-80af-49d5-985c-24a6355a7d55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134304130 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 454.prim_prince_test.3134304130
Directory /workspace/454.prim_prince_test/latest

Test location /workspace/coverage/default/455.prim_prince_test.2240715003
Short name T76
Test name
Test status
Simulation time 1697621953 ps
CPU time 29.09 seconds
Started Jun 27 06:12:23 PM PDT 24
Finished Jun 27 06:13:01 PM PDT 24
Peak memory 146724 kb
Host smart-11f31e47-9e8f-47ce-96c1-4fb0388ca44d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240715003 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 455.prim_prince_test.2240715003
Directory /workspace/455.prim_prince_test/latest

Test location /workspace/coverage/default/456.prim_prince_test.2370132980
Short name T247
Test name
Test status
Simulation time 1168828810 ps
CPU time 19.6 seconds
Started Jun 27 06:12:20 PM PDT 24
Finished Jun 27 06:12:48 PM PDT 24
Peak memory 146736 kb
Host smart-af00b526-27f1-4716-b5c1-2d70214b0567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370132980 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 456.prim_prince_test.2370132980
Directory /workspace/456.prim_prince_test/latest

Test location /workspace/coverage/default/457.prim_prince_test.200580352
Short name T235
Test name
Test status
Simulation time 3108077594 ps
CPU time 53 seconds
Started Jun 27 06:12:17 PM PDT 24
Finished Jun 27 06:13:25 PM PDT 24
Peak memory 146808 kb
Host smart-8a2fb630-8353-48c6-93a3-027d3c597213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200580352 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 457.prim_prince_test.200580352
Directory /workspace/457.prim_prince_test/latest

Test location /workspace/coverage/default/458.prim_prince_test.1046045106
Short name T13
Test name
Test status
Simulation time 3183870711 ps
CPU time 53.34 seconds
Started Jun 27 06:12:19 PM PDT 24
Finished Jun 27 06:13:26 PM PDT 24
Peak memory 146736 kb
Host smart-e266aeb8-c172-4f24-a8ed-1a7cf31fac0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046045106 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 458.prim_prince_test.1046045106
Directory /workspace/458.prim_prince_test/latest

Test location /workspace/coverage/default/459.prim_prince_test.1242286354
Short name T414
Test name
Test status
Simulation time 3106975024 ps
CPU time 51.18 seconds
Started Jun 27 06:12:16 PM PDT 24
Finished Jun 27 06:13:21 PM PDT 24
Peak memory 146880 kb
Host smart-f208898e-ce53-4c0f-952a-b7557e03d35a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242286354 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 459.prim_prince_test.1242286354
Directory /workspace/459.prim_prince_test/latest

Test location /workspace/coverage/default/46.prim_prince_test.1169615647
Short name T72
Test name
Test status
Simulation time 2439038747 ps
CPU time 41.28 seconds
Started Jun 27 06:10:14 PM PDT 24
Finished Jun 27 06:11:06 PM PDT 24
Peak memory 146636 kb
Host smart-060834bb-e210-40f0-b234-e55f922d21de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169615647 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_prince_test.1169615647
Directory /workspace/46.prim_prince_test/latest

Test location /workspace/coverage/default/460.prim_prince_test.3013053130
Short name T378
Test name
Test status
Simulation time 3703574388 ps
CPU time 62.53 seconds
Started Jun 27 06:12:17 PM PDT 24
Finished Jun 27 06:13:37 PM PDT 24
Peak memory 146748 kb
Host smart-42656769-e699-4e68-a109-d10a5e80fb4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013053130 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 460.prim_prince_test.3013053130
Directory /workspace/460.prim_prince_test/latest

Test location /workspace/coverage/default/461.prim_prince_test.3355671195
Short name T409
Test name
Test status
Simulation time 1267980911 ps
CPU time 21.63 seconds
Started Jun 27 06:12:22 PM PDT 24
Finished Jun 27 06:12:52 PM PDT 24
Peak memory 146720 kb
Host smart-a0dd1772-a768-45e3-b435-eb3ed675948e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355671195 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 461.prim_prince_test.3355671195
Directory /workspace/461.prim_prince_test/latest

Test location /workspace/coverage/default/462.prim_prince_test.3509848105
Short name T356
Test name
Test status
Simulation time 2368869348 ps
CPU time 41.02 seconds
Started Jun 27 06:12:20 PM PDT 24
Finished Jun 27 06:13:15 PM PDT 24
Peak memory 146760 kb
Host smart-912acc08-ed44-4461-8de4-a0a142023672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509848105 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 462.prim_prince_test.3509848105
Directory /workspace/462.prim_prince_test/latest

Test location /workspace/coverage/default/463.prim_prince_test.3485170088
Short name T386
Test name
Test status
Simulation time 2794717986 ps
CPU time 48.09 seconds
Started Jun 27 06:12:17 PM PDT 24
Finished Jun 27 06:13:19 PM PDT 24
Peak memory 146764 kb
Host smart-83399b2c-584c-40dc-9dc6-e3faef2c20f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485170088 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 463.prim_prince_test.3485170088
Directory /workspace/463.prim_prince_test/latest

Test location /workspace/coverage/default/464.prim_prince_test.3794216860
Short name T170
Test name
Test status
Simulation time 3223200371 ps
CPU time 53.84 seconds
Started Jun 27 06:12:16 PM PDT 24
Finished Jun 27 06:13:24 PM PDT 24
Peak memory 146796 kb
Host smart-8a1678cc-5a05-4158-819f-a774fa1815e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794216860 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 464.prim_prince_test.3794216860
Directory /workspace/464.prim_prince_test/latest

Test location /workspace/coverage/default/465.prim_prince_test.4088716486
Short name T175
Test name
Test status
Simulation time 2947668623 ps
CPU time 47.8 seconds
Started Jun 27 06:12:16 PM PDT 24
Finished Jun 27 06:13:16 PM PDT 24
Peak memory 146796 kb
Host smart-ea930539-e117-4faa-b687-1d6c278e7e3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088716486 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 465.prim_prince_test.4088716486
Directory /workspace/465.prim_prince_test/latest

Test location /workspace/coverage/default/466.prim_prince_test.3047120127
Short name T184
Test name
Test status
Simulation time 1561307394 ps
CPU time 26.32 seconds
Started Jun 27 06:12:17 PM PDT 24
Finished Jun 27 06:12:53 PM PDT 24
Peak memory 146684 kb
Host smart-d92c14e4-23cb-4515-92b4-218cde9fbd1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047120127 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 466.prim_prince_test.3047120127
Directory /workspace/466.prim_prince_test/latest

Test location /workspace/coverage/default/467.prim_prince_test.1170412013
Short name T38
Test name
Test status
Simulation time 1285007408 ps
CPU time 21.37 seconds
Started Jun 27 06:12:17 PM PDT 24
Finished Jun 27 06:12:46 PM PDT 24
Peak memory 146744 kb
Host smart-c4b6eab3-543c-4eac-b6c1-43f5dac3cfaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170412013 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 467.prim_prince_test.1170412013
Directory /workspace/467.prim_prince_test/latest

Test location /workspace/coverage/default/468.prim_prince_test.2793668777
Short name T439
Test name
Test status
Simulation time 1923714035 ps
CPU time 33.04 seconds
Started Jun 27 06:12:20 PM PDT 24
Finished Jun 27 06:13:05 PM PDT 24
Peak memory 146696 kb
Host smart-e40b03bc-130d-43cc-a029-875c49ca85e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793668777 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 468.prim_prince_test.2793668777
Directory /workspace/468.prim_prince_test/latest

Test location /workspace/coverage/default/469.prim_prince_test.4039811947
Short name T111
Test name
Test status
Simulation time 2417879583 ps
CPU time 41.76 seconds
Started Jun 27 06:12:15 PM PDT 24
Finished Jun 27 06:13:09 PM PDT 24
Peak memory 146784 kb
Host smart-5dc06999-524c-40b7-930b-88b0338f7346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039811947 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 469.prim_prince_test.4039811947
Directory /workspace/469.prim_prince_test/latest

Test location /workspace/coverage/default/47.prim_prince_test.2221647
Short name T120
Test name
Test status
Simulation time 2397066852 ps
CPU time 40.77 seconds
Started Jun 27 06:10:14 PM PDT 24
Finished Jun 27 06:11:05 PM PDT 24
Peak memory 146676 kb
Host smart-a5d00739-1c13-496d-9c27-5d9ac64a48de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221647 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_prince_test.2221647
Directory /workspace/47.prim_prince_test/latest

Test location /workspace/coverage/default/470.prim_prince_test.3433270869
Short name T52
Test name
Test status
Simulation time 3322127788 ps
CPU time 55.44 seconds
Started Jun 27 06:12:17 PM PDT 24
Finished Jun 27 06:13:28 PM PDT 24
Peak memory 146792 kb
Host smart-dddfcbf7-2559-4e06-9e69-e951e70fb95f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433270869 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 470.prim_prince_test.3433270869
Directory /workspace/470.prim_prince_test/latest

Test location /workspace/coverage/default/471.prim_prince_test.2636297767
Short name T324
Test name
Test status
Simulation time 1455751772 ps
CPU time 23.49 seconds
Started Jun 27 06:12:19 PM PDT 24
Finished Jun 27 06:12:50 PM PDT 24
Peak memory 146732 kb
Host smart-2da80097-a03a-4c33-a057-5be5fa81f9cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636297767 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 471.prim_prince_test.2636297767
Directory /workspace/471.prim_prince_test/latest

Test location /workspace/coverage/default/472.prim_prince_test.452546853
Short name T465
Test name
Test status
Simulation time 2975640756 ps
CPU time 50.69 seconds
Started Jun 27 06:12:17 PM PDT 24
Finished Jun 27 06:13:23 PM PDT 24
Peak memory 146808 kb
Host smart-d5463ff9-6219-4e56-a473-45cc4e60ee5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452546853 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 472.prim_prince_test.452546853
Directory /workspace/472.prim_prince_test/latest

Test location /workspace/coverage/default/473.prim_prince_test.1088588490
Short name T217
Test name
Test status
Simulation time 2584229522 ps
CPU time 44.96 seconds
Started Jun 27 06:12:20 PM PDT 24
Finished Jun 27 06:13:20 PM PDT 24
Peak memory 146760 kb
Host smart-27917b0b-06e7-4fe9-998b-74aa39d04199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088588490 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 473.prim_prince_test.1088588490
Directory /workspace/473.prim_prince_test/latest

Test location /workspace/coverage/default/474.prim_prince_test.2609645028
Short name T425
Test name
Test status
Simulation time 2983390751 ps
CPU time 50.95 seconds
Started Jun 27 06:12:17 PM PDT 24
Finished Jun 27 06:13:22 PM PDT 24
Peak memory 146764 kb
Host smart-66e45541-8ac9-4781-899e-14e5f2ccf48c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609645028 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 474.prim_prince_test.2609645028
Directory /workspace/474.prim_prince_test/latest

Test location /workspace/coverage/default/475.prim_prince_test.28454503
Short name T450
Test name
Test status
Simulation time 2120901590 ps
CPU time 35.63 seconds
Started Jun 27 06:12:17 PM PDT 24
Finished Jun 27 06:13:03 PM PDT 24
Peak memory 146724 kb
Host smart-d36b1a8b-b427-4a58-ba2d-e50f2542e509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28454503 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 475.prim_prince_test.28454503
Directory /workspace/475.prim_prince_test/latest

Test location /workspace/coverage/default/476.prim_prince_test.2509122510
Short name T442
Test name
Test status
Simulation time 3549574852 ps
CPU time 59.09 seconds
Started Jun 27 06:12:23 PM PDT 24
Finished Jun 27 06:13:38 PM PDT 24
Peak memory 145984 kb
Host smart-5d28cdc7-a727-416b-bfb2-af306eca2745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509122510 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 476.prim_prince_test.2509122510
Directory /workspace/476.prim_prince_test/latest

Test location /workspace/coverage/default/477.prim_prince_test.1057874690
Short name T25
Test name
Test status
Simulation time 3567252601 ps
CPU time 61.98 seconds
Started Jun 27 06:12:17 PM PDT 24
Finished Jun 27 06:13:37 PM PDT 24
Peak memory 146812 kb
Host smart-208c1b40-b0da-454c-8734-da802b2003f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057874690 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 477.prim_prince_test.1057874690
Directory /workspace/477.prim_prince_test/latest

Test location /workspace/coverage/default/478.prim_prince_test.4019642430
Short name T131
Test name
Test status
Simulation time 2063418532 ps
CPU time 34.34 seconds
Started Jun 27 06:12:20 PM PDT 24
Finished Jun 27 06:13:05 PM PDT 24
Peak memory 146740 kb
Host smart-66322932-fc74-4168-b8e1-76d02982dd10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019642430 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 478.prim_prince_test.4019642430
Directory /workspace/478.prim_prince_test/latest

Test location /workspace/coverage/default/479.prim_prince_test.1566337644
Short name T257
Test name
Test status
Simulation time 2548685358 ps
CPU time 42.29 seconds
Started Jun 27 06:12:17 PM PDT 24
Finished Jun 27 06:13:12 PM PDT 24
Peak memory 146732 kb
Host smart-a0fab997-b48d-420d-ac0b-05d5c283614b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566337644 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 479.prim_prince_test.1566337644
Directory /workspace/479.prim_prince_test/latest

Test location /workspace/coverage/default/48.prim_prince_test.4283370927
Short name T5
Test name
Test status
Simulation time 1802344276 ps
CPU time 30.5 seconds
Started Jun 27 06:10:13 PM PDT 24
Finished Jun 27 06:10:51 PM PDT 24
Peak memory 146056 kb
Host smart-ab15bbee-7523-4bf1-8d24-b855ab3d8046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283370927 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_prince_test.4283370927
Directory /workspace/48.prim_prince_test/latest

Test location /workspace/coverage/default/480.prim_prince_test.203515142
Short name T389
Test name
Test status
Simulation time 2521770593 ps
CPU time 42.39 seconds
Started Jun 27 06:12:20 PM PDT 24
Finished Jun 27 06:13:16 PM PDT 24
Peak memory 146808 kb
Host smart-b85b732b-85be-427a-9822-58ac997820df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203515142 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 480.prim_prince_test.203515142
Directory /workspace/480.prim_prince_test/latest

Test location /workspace/coverage/default/481.prim_prince_test.3483870545
Short name T22
Test name
Test status
Simulation time 2811007366 ps
CPU time 43.95 seconds
Started Jun 27 06:12:18 PM PDT 24
Finished Jun 27 06:13:13 PM PDT 24
Peak memory 146796 kb
Host smart-8e7a21f3-bf71-4000-88fd-f34558d53983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483870545 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 481.prim_prince_test.3483870545
Directory /workspace/481.prim_prince_test/latest

Test location /workspace/coverage/default/482.prim_prince_test.540774587
Short name T431
Test name
Test status
Simulation time 1280591448 ps
CPU time 21.51 seconds
Started Jun 27 06:12:18 PM PDT 24
Finished Jun 27 06:12:47 PM PDT 24
Peak memory 146736 kb
Host smart-72718364-79b5-46d0-9d67-7faecde3ec4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540774587 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 482.prim_prince_test.540774587
Directory /workspace/482.prim_prince_test/latest

Test location /workspace/coverage/default/483.prim_prince_test.4189294152
Short name T139
Test name
Test status
Simulation time 2647128550 ps
CPU time 44.46 seconds
Started Jun 27 06:12:20 PM PDT 24
Finished Jun 27 06:13:18 PM PDT 24
Peak memory 146804 kb
Host smart-6cda7a3b-4d65-488e-bf07-c3f89de17978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189294152 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 483.prim_prince_test.4189294152
Directory /workspace/483.prim_prince_test/latest

Test location /workspace/coverage/default/484.prim_prince_test.3679995332
Short name T291
Test name
Test status
Simulation time 1336547010 ps
CPU time 22.37 seconds
Started Jun 27 06:12:17 PM PDT 24
Finished Jun 27 06:12:47 PM PDT 24
Peak memory 146740 kb
Host smart-99584955-c5e8-4cf4-abb4-a97841293e0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679995332 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 484.prim_prince_test.3679995332
Directory /workspace/484.prim_prince_test/latest

Test location /workspace/coverage/default/485.prim_prince_test.3478996316
Short name T403
Test name
Test status
Simulation time 1358593770 ps
CPU time 22.74 seconds
Started Jun 27 06:12:19 PM PDT 24
Finished Jun 27 06:12:50 PM PDT 24
Peak memory 146668 kb
Host smart-8d27830f-222f-4839-8b10-9ecf113ae81e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478996316 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 485.prim_prince_test.3478996316
Directory /workspace/485.prim_prince_test/latest

Test location /workspace/coverage/default/486.prim_prince_test.1662186384
Short name T151
Test name
Test status
Simulation time 2519248675 ps
CPU time 42.18 seconds
Started Jun 27 06:12:20 PM PDT 24
Finished Jun 27 06:13:15 PM PDT 24
Peak memory 146800 kb
Host smart-3245a39e-7d5b-4781-b5e5-557c5f8c7cb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662186384 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 486.prim_prince_test.1662186384
Directory /workspace/486.prim_prince_test/latest

Test location /workspace/coverage/default/487.prim_prince_test.4143050547
Short name T251
Test name
Test status
Simulation time 1826075064 ps
CPU time 30.03 seconds
Started Jun 27 06:12:18 PM PDT 24
Finished Jun 27 06:12:57 PM PDT 24
Peak memory 146736 kb
Host smart-21feb9f5-0dd2-4d5f-a98c-464a4e4bcd6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143050547 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 487.prim_prince_test.4143050547
Directory /workspace/487.prim_prince_test/latest

Test location /workspace/coverage/default/488.prim_prince_test.1297416424
Short name T452
Test name
Test status
Simulation time 3477476848 ps
CPU time 58.2 seconds
Started Jun 27 06:12:23 PM PDT 24
Finished Jun 27 06:13:37 PM PDT 24
Peak memory 146328 kb
Host smart-6abf888c-358f-47f6-8b99-aa7cfce2c4eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297416424 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 488.prim_prince_test.1297416424
Directory /workspace/488.prim_prince_test/latest

Test location /workspace/coverage/default/489.prim_prince_test.3931193918
Short name T284
Test name
Test status
Simulation time 2446384061 ps
CPU time 41.92 seconds
Started Jun 27 06:12:18 PM PDT 24
Finished Jun 27 06:13:14 PM PDT 24
Peak memory 146800 kb
Host smart-68f9a1d1-bb69-4ca5-a7ec-98cf0aecb5d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931193918 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 489.prim_prince_test.3931193918
Directory /workspace/489.prim_prince_test/latest

Test location /workspace/coverage/default/49.prim_prince_test.2336835552
Short name T148
Test name
Test status
Simulation time 2162827507 ps
CPU time 35.91 seconds
Started Jun 27 06:10:11 PM PDT 24
Finished Jun 27 06:10:56 PM PDT 24
Peak memory 146800 kb
Host smart-6249c2b9-c00a-4390-9392-6ae74d2b4deb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336835552 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_prince_test.2336835552
Directory /workspace/49.prim_prince_test/latest

Test location /workspace/coverage/default/490.prim_prince_test.172770237
Short name T81
Test name
Test status
Simulation time 3454934890 ps
CPU time 57.93 seconds
Started Jun 27 06:12:21 PM PDT 24
Finished Jun 27 06:13:35 PM PDT 24
Peak memory 146812 kb
Host smart-8b131b2b-0191-4cef-a311-73ab808f2383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172770237 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 490.prim_prince_test.172770237
Directory /workspace/490.prim_prince_test/latest

Test location /workspace/coverage/default/491.prim_prince_test.543707103
Short name T102
Test name
Test status
Simulation time 1742505730 ps
CPU time 28.5 seconds
Started Jun 27 06:12:21 PM PDT 24
Finished Jun 27 06:12:59 PM PDT 24
Peak memory 146740 kb
Host smart-a8b05268-6ba2-4f0e-b6b8-e26ece5f30ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543707103 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 491.prim_prince_test.543707103
Directory /workspace/491.prim_prince_test/latest

Test location /workspace/coverage/default/492.prim_prince_test.2943549963
Short name T89
Test name
Test status
Simulation time 1525129219 ps
CPU time 25.75 seconds
Started Jun 27 06:12:20 PM PDT 24
Finished Jun 27 06:12:54 PM PDT 24
Peak memory 146736 kb
Host smart-156b8246-bc8e-4aad-abb8-8a8d1c676ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943549963 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 492.prim_prince_test.2943549963
Directory /workspace/492.prim_prince_test/latest

Test location /workspace/coverage/default/493.prim_prince_test.4279308053
Short name T489
Test name
Test status
Simulation time 960301232 ps
CPU time 15.62 seconds
Started Jun 27 06:12:21 PM PDT 24
Finished Jun 27 06:12:43 PM PDT 24
Peak memory 146736 kb
Host smart-6f501e46-9342-4095-beb1-7a6a07cf927a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279308053 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 493.prim_prince_test.4279308053
Directory /workspace/493.prim_prince_test/latest

Test location /workspace/coverage/default/494.prim_prince_test.4268152190
Short name T1
Test name
Test status
Simulation time 2321093803 ps
CPU time 38.52 seconds
Started Jun 27 06:12:21 PM PDT 24
Finished Jun 27 06:13:11 PM PDT 24
Peak memory 146800 kb
Host smart-5e7d460d-c68a-4542-a509-c092b54fad0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268152190 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 494.prim_prince_test.4268152190
Directory /workspace/494.prim_prince_test/latest

Test location /workspace/coverage/default/495.prim_prince_test.4228392941
Short name T39
Test name
Test status
Simulation time 2184523454 ps
CPU time 35.85 seconds
Started Jun 27 06:12:33 PM PDT 24
Finished Jun 27 06:13:19 PM PDT 24
Peak memory 146808 kb
Host smart-09c79837-ab24-4eb7-ac0f-461215cf0e0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228392941 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 495.prim_prince_test.4228392941
Directory /workspace/495.prim_prince_test/latest

Test location /workspace/coverage/default/496.prim_prince_test.2048481631
Short name T87
Test name
Test status
Simulation time 875686403 ps
CPU time 14.74 seconds
Started Jun 27 06:12:34 PM PDT 24
Finished Jun 27 06:12:57 PM PDT 24
Peak memory 146744 kb
Host smart-18e25ee2-a3c3-4dad-914f-680749913288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048481631 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 496.prim_prince_test.2048481631
Directory /workspace/496.prim_prince_test/latest

Test location /workspace/coverage/default/497.prim_prince_test.3392230472
Short name T32
Test name
Test status
Simulation time 3115200864 ps
CPU time 52.66 seconds
Started Jun 27 06:12:31 PM PDT 24
Finished Jun 27 06:13:37 PM PDT 24
Peak memory 146792 kb
Host smart-c6107f46-73aa-44f2-af08-73b4dcb1dae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392230472 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 497.prim_prince_test.3392230472
Directory /workspace/497.prim_prince_test/latest

Test location /workspace/coverage/default/498.prim_prince_test.1876460781
Short name T47
Test name
Test status
Simulation time 1175751038 ps
CPU time 19.5 seconds
Started Jun 27 06:12:32 PM PDT 24
Finished Jun 27 06:12:58 PM PDT 24
Peak memory 146748 kb
Host smart-b2d8fa5c-bc28-4550-a63b-04b43c125ffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876460781 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 498.prim_prince_test.1876460781
Directory /workspace/498.prim_prince_test/latest

Test location /workspace/coverage/default/499.prim_prince_test.3492352102
Short name T360
Test name
Test status
Simulation time 1548605690 ps
CPU time 25.42 seconds
Started Jun 27 06:12:34 PM PDT 24
Finished Jun 27 06:13:08 PM PDT 24
Peak memory 146752 kb
Host smart-94c76796-11ef-4f1d-9b96-54d3e6193baa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492352102 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 499.prim_prince_test.3492352102
Directory /workspace/499.prim_prince_test/latest

Test location /workspace/coverage/default/5.prim_prince_test.3021941073
Short name T310
Test name
Test status
Simulation time 3024936466 ps
CPU time 49.66 seconds
Started Jun 27 06:10:05 PM PDT 24
Finished Jun 27 06:11:07 PM PDT 24
Peak memory 146800 kb
Host smart-1590ea33-6edf-4852-bbc8-09acd02009fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021941073 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_prince_test.3021941073
Directory /workspace/5.prim_prince_test/latest

Test location /workspace/coverage/default/50.prim_prince_test.37245056
Short name T234
Test name
Test status
Simulation time 2829645476 ps
CPU time 45.85 seconds
Started Jun 27 06:10:10 PM PDT 24
Finished Jun 27 06:11:06 PM PDT 24
Peak memory 146812 kb
Host smart-4147b25b-0278-413d-9831-a94fc793460b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37245056 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 50.prim_prince_test.37245056
Directory /workspace/50.prim_prince_test/latest

Test location /workspace/coverage/default/51.prim_prince_test.3419975964
Short name T78
Test name
Test status
Simulation time 1754248384 ps
CPU time 29.55 seconds
Started Jun 27 06:10:32 PM PDT 24
Finished Jun 27 06:11:09 PM PDT 24
Peak memory 146688 kb
Host smart-1de5abaf-162f-403d-88b0-747599152f87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419975964 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 51.prim_prince_test.3419975964
Directory /workspace/51.prim_prince_test/latest

Test location /workspace/coverage/default/52.prim_prince_test.1630333129
Short name T354
Test name
Test status
Simulation time 955611836 ps
CPU time 16.68 seconds
Started Jun 27 06:10:26 PM PDT 24
Finished Jun 27 06:10:48 PM PDT 24
Peak memory 146744 kb
Host smart-ad03efda-f644-4f6c-8972-16b33bdd7d86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630333129 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 52.prim_prince_test.1630333129
Directory /workspace/52.prim_prince_test/latest

Test location /workspace/coverage/default/53.prim_prince_test.1021578553
Short name T499
Test name
Test status
Simulation time 1577516593 ps
CPU time 27.02 seconds
Started Jun 27 06:10:27 PM PDT 24
Finished Jun 27 06:11:02 PM PDT 24
Peak memory 146736 kb
Host smart-311b7695-55bd-423f-a653-196c62d974a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021578553 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 53.prim_prince_test.1021578553
Directory /workspace/53.prim_prince_test/latest

Test location /workspace/coverage/default/54.prim_prince_test.2029846084
Short name T303
Test name
Test status
Simulation time 2278292893 ps
CPU time 38.73 seconds
Started Jun 27 06:10:29 PM PDT 24
Finished Jun 27 06:11:20 PM PDT 24
Peak memory 146816 kb
Host smart-3b8c0499-a625-4a43-a6c9-4ebc8b4b9a58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029846084 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 54.prim_prince_test.2029846084
Directory /workspace/54.prim_prince_test/latest

Test location /workspace/coverage/default/55.prim_prince_test.1411520093
Short name T233
Test name
Test status
Simulation time 2986421329 ps
CPU time 49.46 seconds
Started Jun 27 06:10:26 PM PDT 24
Finished Jun 27 06:11:27 PM PDT 24
Peak memory 146808 kb
Host smart-42718ce4-938a-4ed9-82b3-4e5b3d67c71b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411520093 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 55.prim_prince_test.1411520093
Directory /workspace/55.prim_prince_test/latest

Test location /workspace/coverage/default/56.prim_prince_test.3407741270
Short name T331
Test name
Test status
Simulation time 1916842481 ps
CPU time 31.76 seconds
Started Jun 27 06:10:26 PM PDT 24
Finished Jun 27 06:11:06 PM PDT 24
Peak memory 146712 kb
Host smart-ffa88da0-bdc4-4515-b304-ddea9c01b79f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407741270 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 56.prim_prince_test.3407741270
Directory /workspace/56.prim_prince_test/latest

Test location /workspace/coverage/default/57.prim_prince_test.3685503677
Short name T290
Test name
Test status
Simulation time 3403638818 ps
CPU time 56.52 seconds
Started Jun 27 06:10:28 PM PDT 24
Finished Jun 27 06:11:40 PM PDT 24
Peak memory 146800 kb
Host smart-e58af492-fd74-47a7-ae6e-d530a9ae4bc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685503677 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 57.prim_prince_test.3685503677
Directory /workspace/57.prim_prince_test/latest

Test location /workspace/coverage/default/58.prim_prince_test.697896218
Short name T287
Test name
Test status
Simulation time 2495175326 ps
CPU time 42.13 seconds
Started Jun 27 06:10:27 PM PDT 24
Finished Jun 27 06:11:21 PM PDT 24
Peak memory 146716 kb
Host smart-eb49dabc-64d0-4a19-8ac5-a1af9c63abf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697896218 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 58.prim_prince_test.697896218
Directory /workspace/58.prim_prince_test/latest

Test location /workspace/coverage/default/59.prim_prince_test.1716548760
Short name T487
Test name
Test status
Simulation time 813155767 ps
CPU time 13.72 seconds
Started Jun 27 06:10:29 PM PDT 24
Finished Jun 27 06:10:49 PM PDT 24
Peak memory 146748 kb
Host smart-dc5dc0fc-9557-4bbe-9022-631577739a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716548760 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 59.prim_prince_test.1716548760
Directory /workspace/59.prim_prince_test/latest

Test location /workspace/coverage/default/6.prim_prince_test.1417182211
Short name T167
Test name
Test status
Simulation time 2744998510 ps
CPU time 44.82 seconds
Started Jun 27 06:10:05 PM PDT 24
Finished Jun 27 06:11:00 PM PDT 24
Peak memory 146800 kb
Host smart-bf0dd997-56d8-468b-b2fd-f6656672c7e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417182211 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_prince_test.1417182211
Directory /workspace/6.prim_prince_test/latest

Test location /workspace/coverage/default/60.prim_prince_test.1684234656
Short name T59
Test name
Test status
Simulation time 3456421124 ps
CPU time 57.14 seconds
Started Jun 27 06:10:27 PM PDT 24
Finished Jun 27 06:11:38 PM PDT 24
Peak memory 146808 kb
Host smart-12be93fc-27a7-4fc7-9c1f-9f2b9f888b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684234656 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 60.prim_prince_test.1684234656
Directory /workspace/60.prim_prince_test/latest

Test location /workspace/coverage/default/61.prim_prince_test.3788031277
Short name T71
Test name
Test status
Simulation time 1786651489 ps
CPU time 29.79 seconds
Started Jun 27 06:10:28 PM PDT 24
Finished Jun 27 06:11:07 PM PDT 24
Peak memory 146740 kb
Host smart-5dd9f180-a75f-49fc-8dcf-b203ee1970d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788031277 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 61.prim_prince_test.3788031277
Directory /workspace/61.prim_prince_test/latest

Test location /workspace/coverage/default/62.prim_prince_test.846810675
Short name T375
Test name
Test status
Simulation time 3578439495 ps
CPU time 59.7 seconds
Started Jun 27 06:10:29 PM PDT 24
Finished Jun 27 06:11:44 PM PDT 24
Peak memory 146808 kb
Host smart-d3093678-fc40-4e0f-9f4f-22709e109858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846810675 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 62.prim_prince_test.846810675
Directory /workspace/62.prim_prince_test/latest

Test location /workspace/coverage/default/63.prim_prince_test.2983131261
Short name T306
Test name
Test status
Simulation time 2315754887 ps
CPU time 38.89 seconds
Started Jun 27 06:10:27 PM PDT 24
Finished Jun 27 06:11:18 PM PDT 24
Peak memory 146756 kb
Host smart-4cd9ed3d-dfb9-4e45-8081-293ed212385a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983131261 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 63.prim_prince_test.2983131261
Directory /workspace/63.prim_prince_test/latest

Test location /workspace/coverage/default/64.prim_prince_test.2781069606
Short name T488
Test name
Test status
Simulation time 1660082159 ps
CPU time 28.53 seconds
Started Jun 27 06:10:27 PM PDT 24
Finished Jun 27 06:11:03 PM PDT 24
Peak memory 146664 kb
Host smart-1c056480-8809-483a-95c9-74e3df9b1509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781069606 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 64.prim_prince_test.2781069606
Directory /workspace/64.prim_prince_test/latest

Test location /workspace/coverage/default/65.prim_prince_test.2394045279
Short name T271
Test name
Test status
Simulation time 1965781504 ps
CPU time 33.95 seconds
Started Jun 27 06:10:25 PM PDT 24
Finished Jun 27 06:11:09 PM PDT 24
Peak memory 146744 kb
Host smart-6e371f3b-25ae-4cc1-a4bb-fe83dcb8fc43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394045279 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 65.prim_prince_test.2394045279
Directory /workspace/65.prim_prince_test/latest

Test location /workspace/coverage/default/66.prim_prince_test.1072684523
Short name T192
Test name
Test status
Simulation time 896895063 ps
CPU time 15.06 seconds
Started Jun 27 06:10:27 PM PDT 24
Finished Jun 27 06:10:48 PM PDT 24
Peak memory 146748 kb
Host smart-5a71ee7c-8e3d-41b4-80e2-e745af1e8eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072684523 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 66.prim_prince_test.1072684523
Directory /workspace/66.prim_prince_test/latest

Test location /workspace/coverage/default/67.prim_prince_test.3004468216
Short name T150
Test name
Test status
Simulation time 1865141342 ps
CPU time 31.51 seconds
Started Jun 27 06:10:27 PM PDT 24
Finished Jun 27 06:11:08 PM PDT 24
Peak memory 146744 kb
Host smart-38460620-6769-4100-951a-2a2490637370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004468216 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 67.prim_prince_test.3004468216
Directory /workspace/67.prim_prince_test/latest

Test location /workspace/coverage/default/68.prim_prince_test.1717688181
Short name T486
Test name
Test status
Simulation time 1650156015 ps
CPU time 27.11 seconds
Started Jun 27 06:10:26 PM PDT 24
Finished Jun 27 06:11:01 PM PDT 24
Peak memory 146744 kb
Host smart-0c078114-f17d-4802-8972-526bd2bdecc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717688181 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 68.prim_prince_test.1717688181
Directory /workspace/68.prim_prince_test/latest

Test location /workspace/coverage/default/69.prim_prince_test.3301968546
Short name T261
Test name
Test status
Simulation time 829220564 ps
CPU time 14.39 seconds
Started Jun 27 06:10:27 PM PDT 24
Finished Jun 27 06:10:47 PM PDT 24
Peak memory 146732 kb
Host smart-cb61cb2b-61c6-45a7-8556-0ee38b3e16f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301968546 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 69.prim_prince_test.3301968546
Directory /workspace/69.prim_prince_test/latest

Test location /workspace/coverage/default/7.prim_prince_test.2442140587
Short name T92
Test name
Test status
Simulation time 1740722032 ps
CPU time 28.34 seconds
Started Jun 27 06:09:59 PM PDT 24
Finished Jun 27 06:10:36 PM PDT 24
Peak memory 146728 kb
Host smart-a50803e0-a612-4008-9962-337f00a3499c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442140587 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_prince_test.2442140587
Directory /workspace/7.prim_prince_test/latest

Test location /workspace/coverage/default/70.prim_prince_test.3212787101
Short name T211
Test name
Test status
Simulation time 3355470214 ps
CPU time 55.67 seconds
Started Jun 27 06:10:28 PM PDT 24
Finished Jun 27 06:11:38 PM PDT 24
Peak memory 146756 kb
Host smart-8c92b693-bfcb-478d-98b7-09f1bfa647c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212787101 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 70.prim_prince_test.3212787101
Directory /workspace/70.prim_prince_test/latest

Test location /workspace/coverage/default/71.prim_prince_test.2674044466
Short name T183
Test name
Test status
Simulation time 1203791614 ps
CPU time 20.71 seconds
Started Jun 27 06:10:30 PM PDT 24
Finished Jun 27 06:10:58 PM PDT 24
Peak memory 146736 kb
Host smart-93e3f43f-ee8d-422a-a5a6-7b47207030b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674044466 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 71.prim_prince_test.2674044466
Directory /workspace/71.prim_prince_test/latest

Test location /workspace/coverage/default/72.prim_prince_test.4244035745
Short name T320
Test name
Test status
Simulation time 3185234095 ps
CPU time 54.54 seconds
Started Jun 27 06:10:28 PM PDT 24
Finished Jun 27 06:11:39 PM PDT 24
Peak memory 146768 kb
Host smart-40f8cdf4-ce69-41af-a8e0-c6f8c7fba3a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244035745 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 72.prim_prince_test.4244035745
Directory /workspace/72.prim_prince_test/latest

Test location /workspace/coverage/default/73.prim_prince_test.500024257
Short name T416
Test name
Test status
Simulation time 1278471828 ps
CPU time 21.61 seconds
Started Jun 27 06:10:27 PM PDT 24
Finished Jun 27 06:10:55 PM PDT 24
Peak memory 146732 kb
Host smart-a9376d25-e973-4822-8a26-c1405ba703da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500024257 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 73.prim_prince_test.500024257
Directory /workspace/73.prim_prince_test/latest

Test location /workspace/coverage/default/74.prim_prince_test.780884731
Short name T246
Test name
Test status
Simulation time 1788504425 ps
CPU time 30.87 seconds
Started Jun 27 06:10:27 PM PDT 24
Finished Jun 27 06:11:07 PM PDT 24
Peak memory 146720 kb
Host smart-1db63729-76a9-473f-be53-f2d14ef89037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780884731 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 74.prim_prince_test.780884731
Directory /workspace/74.prim_prince_test/latest

Test location /workspace/coverage/default/75.prim_prince_test.1026077639
Short name T458
Test name
Test status
Simulation time 2476516955 ps
CPU time 40.94 seconds
Started Jun 27 06:10:29 PM PDT 24
Finished Jun 27 06:11:21 PM PDT 24
Peak memory 146808 kb
Host smart-8879461b-c5f2-41f6-a06d-f3527af48376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026077639 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 75.prim_prince_test.1026077639
Directory /workspace/75.prim_prince_test/latest

Test location /workspace/coverage/default/76.prim_prince_test.3697257019
Short name T127
Test name
Test status
Simulation time 967220220 ps
CPU time 17.07 seconds
Started Jun 27 06:10:26 PM PDT 24
Finished Jun 27 06:10:49 PM PDT 24
Peak memory 146728 kb
Host smart-8a020868-73a3-4955-a19f-b046af36a8e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697257019 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 76.prim_prince_test.3697257019
Directory /workspace/76.prim_prince_test/latest

Test location /workspace/coverage/default/77.prim_prince_test.1838952515
Short name T157
Test name
Test status
Simulation time 1110307024 ps
CPU time 19.33 seconds
Started Jun 27 06:10:28 PM PDT 24
Finished Jun 27 06:10:54 PM PDT 24
Peak memory 146740 kb
Host smart-3afba53a-7942-48d6-b759-61aea173a72c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838952515 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 77.prim_prince_test.1838952515
Directory /workspace/77.prim_prince_test/latest

Test location /workspace/coverage/default/78.prim_prince_test.3790171709
Short name T86
Test name
Test status
Simulation time 1465720520 ps
CPU time 24.62 seconds
Started Jun 27 06:10:28 PM PDT 24
Finished Jun 27 06:11:01 PM PDT 24
Peak memory 146732 kb
Host smart-8b751526-4488-4fce-b233-b8f071503591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790171709 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 78.prim_prince_test.3790171709
Directory /workspace/78.prim_prince_test/latest

Test location /workspace/coverage/default/79.prim_prince_test.3325405677
Short name T50
Test name
Test status
Simulation time 2552715124 ps
CPU time 44.98 seconds
Started Jun 27 06:10:26 PM PDT 24
Finished Jun 27 06:11:25 PM PDT 24
Peak memory 146812 kb
Host smart-21e083d1-2fca-4969-8905-1925a1f5791b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325405677 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 79.prim_prince_test.3325405677
Directory /workspace/79.prim_prince_test/latest

Test location /workspace/coverage/default/8.prim_prince_test.205968319
Short name T401
Test name
Test status
Simulation time 3632648296 ps
CPU time 60.22 seconds
Started Jun 27 06:09:59 PM PDT 24
Finished Jun 27 06:11:15 PM PDT 24
Peak memory 146812 kb
Host smart-981bca64-e76a-48c7-93dd-ac8d121f7a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205968319 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_prince_test.205968319
Directory /workspace/8.prim_prince_test/latest

Test location /workspace/coverage/default/80.prim_prince_test.3992092842
Short name T485
Test name
Test status
Simulation time 1820376454 ps
CPU time 30.32 seconds
Started Jun 27 06:10:28 PM PDT 24
Finished Jun 27 06:11:08 PM PDT 24
Peak memory 146740 kb
Host smart-acb1374c-1fa5-47f2-ab6b-43d98c59660d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992092842 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 80.prim_prince_test.3992092842
Directory /workspace/80.prim_prince_test/latest

Test location /workspace/coverage/default/81.prim_prince_test.2128750782
Short name T318
Test name
Test status
Simulation time 3741780086 ps
CPU time 63.65 seconds
Started Jun 27 06:10:27 PM PDT 24
Finished Jun 27 06:11:48 PM PDT 24
Peak memory 146796 kb
Host smart-5c4557fe-1828-4ba0-ad0f-f55101688fc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128750782 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 81.prim_prince_test.2128750782
Directory /workspace/81.prim_prince_test/latest

Test location /workspace/coverage/default/82.prim_prince_test.3276320702
Short name T11
Test name
Test status
Simulation time 1599744467 ps
CPU time 27.03 seconds
Started Jun 27 06:10:29 PM PDT 24
Finished Jun 27 06:11:05 PM PDT 24
Peak memory 146748 kb
Host smart-39abc9bd-eb19-4e12-ba61-677faf512f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276320702 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 82.prim_prince_test.3276320702
Directory /workspace/82.prim_prince_test/latest

Test location /workspace/coverage/default/83.prim_prince_test.3202082793
Short name T277
Test name
Test status
Simulation time 3623465445 ps
CPU time 60.72 seconds
Started Jun 27 06:10:27 PM PDT 24
Finished Jun 27 06:11:44 PM PDT 24
Peak memory 146808 kb
Host smart-0c88b3b0-16e8-4792-a6bb-a863958d96fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202082793 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 83.prim_prince_test.3202082793
Directory /workspace/83.prim_prince_test/latest

Test location /workspace/coverage/default/84.prim_prince_test.1755273797
Short name T12
Test name
Test status
Simulation time 2024422636 ps
CPU time 34.22 seconds
Started Jun 27 06:10:27 PM PDT 24
Finished Jun 27 06:11:11 PM PDT 24
Peak memory 146732 kb
Host smart-0ccaf5fe-765b-49c0-9cd8-d6166ba2f46a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755273797 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 84.prim_prince_test.1755273797
Directory /workspace/84.prim_prince_test/latest

Test location /workspace/coverage/default/85.prim_prince_test.2883852290
Short name T394
Test name
Test status
Simulation time 1826172602 ps
CPU time 30.07 seconds
Started Jun 27 06:10:27 PM PDT 24
Finished Jun 27 06:11:06 PM PDT 24
Peak memory 146744 kb
Host smart-4504025c-fdd7-440c-b931-81605dead46b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883852290 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 85.prim_prince_test.2883852290
Directory /workspace/85.prim_prince_test/latest

Test location /workspace/coverage/default/86.prim_prince_test.774503959
Short name T278
Test name
Test status
Simulation time 1955056122 ps
CPU time 32.85 seconds
Started Jun 27 06:10:28 PM PDT 24
Finished Jun 27 06:11:11 PM PDT 24
Peak memory 146736 kb
Host smart-da1faf98-78d6-4daa-874c-e4ee255f8e68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774503959 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 86.prim_prince_test.774503959
Directory /workspace/86.prim_prince_test/latest

Test location /workspace/coverage/default/87.prim_prince_test.400672121
Short name T213
Test name
Test status
Simulation time 972949731 ps
CPU time 16.23 seconds
Started Jun 27 06:10:29 PM PDT 24
Finished Jun 27 06:10:51 PM PDT 24
Peak memory 146732 kb
Host smart-9a61f39c-83c1-4f09-b5cd-244b1ab9aff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400672121 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 87.prim_prince_test.400672121
Directory /workspace/87.prim_prince_test/latest

Test location /workspace/coverage/default/88.prim_prince_test.3807052910
Short name T288
Test name
Test status
Simulation time 2230254726 ps
CPU time 37.05 seconds
Started Jun 27 06:10:28 PM PDT 24
Finished Jun 27 06:11:16 PM PDT 24
Peak memory 146804 kb
Host smart-c2be4292-ee50-457c-88d5-9b2784144e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807052910 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 88.prim_prince_test.3807052910
Directory /workspace/88.prim_prince_test/latest

Test location /workspace/coverage/default/89.prim_prince_test.2949369971
Short name T134
Test name
Test status
Simulation time 2263753565 ps
CPU time 38.68 seconds
Started Jun 27 06:10:25 PM PDT 24
Finished Jun 27 06:11:15 PM PDT 24
Peak memory 146776 kb
Host smart-09db6772-ebaa-4a9b-b211-481e5e50818e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949369971 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 89.prim_prince_test.2949369971
Directory /workspace/89.prim_prince_test/latest

Test location /workspace/coverage/default/9.prim_prince_test.2342005480
Short name T268
Test name
Test status
Simulation time 3745162661 ps
CPU time 60.98 seconds
Started Jun 27 06:10:06 PM PDT 24
Finished Jun 27 06:11:21 PM PDT 24
Peak memory 146752 kb
Host smart-25f83553-bb74-4416-ae6a-275237f1d5ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342005480 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_prince_test.2342005480
Directory /workspace/9.prim_prince_test/latest

Test location /workspace/coverage/default/90.prim_prince_test.2648045550
Short name T339
Test name
Test status
Simulation time 2664411599 ps
CPU time 43.77 seconds
Started Jun 27 06:10:26 PM PDT 24
Finished Jun 27 06:11:21 PM PDT 24
Peak memory 146864 kb
Host smart-e76a96e0-1a90-4df9-a79f-52ada6a0f9e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648045550 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 90.prim_prince_test.2648045550
Directory /workspace/90.prim_prince_test/latest

Test location /workspace/coverage/default/91.prim_prince_test.1873272843
Short name T432
Test name
Test status
Simulation time 3139727772 ps
CPU time 51.27 seconds
Started Jun 27 06:10:27 PM PDT 24
Finished Jun 27 06:11:32 PM PDT 24
Peak memory 146808 kb
Host smart-0f2af756-f91a-47e9-8a0a-8a5f52a7ca07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873272843 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 91.prim_prince_test.1873272843
Directory /workspace/91.prim_prince_test/latest

Test location /workspace/coverage/default/92.prim_prince_test.226441237
Short name T98
Test name
Test status
Simulation time 3177711762 ps
CPU time 52.2 seconds
Started Jun 27 06:10:27 PM PDT 24
Finished Jun 27 06:11:33 PM PDT 24
Peak memory 146796 kb
Host smart-5dc98dff-d187-469a-9dd0-cb1aef657e0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226441237 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 92.prim_prince_test.226441237
Directory /workspace/92.prim_prince_test/latest

Test location /workspace/coverage/default/93.prim_prince_test.2157927553
Short name T220
Test name
Test status
Simulation time 2012005086 ps
CPU time 35.21 seconds
Started Jun 27 06:10:28 PM PDT 24
Finished Jun 27 06:11:14 PM PDT 24
Peak memory 146704 kb
Host smart-cf863c51-59b9-4961-a920-f97a183b6256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157927553 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 93.prim_prince_test.2157927553
Directory /workspace/93.prim_prince_test/latest

Test location /workspace/coverage/default/94.prim_prince_test.735910188
Short name T292
Test name
Test status
Simulation time 1134821788 ps
CPU time 19.24 seconds
Started Jun 27 06:10:28 PM PDT 24
Finished Jun 27 06:10:55 PM PDT 24
Peak memory 146724 kb
Host smart-a2140f68-bd0f-4c08-8111-3a5a4a465ad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735910188 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 94.prim_prince_test.735910188
Directory /workspace/94.prim_prince_test/latest

Test location /workspace/coverage/default/95.prim_prince_test.3140622640
Short name T29
Test name
Test status
Simulation time 3163571893 ps
CPU time 53.37 seconds
Started Jun 27 06:10:29 PM PDT 24
Finished Jun 27 06:11:38 PM PDT 24
Peak memory 146812 kb
Host smart-5b9fd48c-532d-40a4-9f84-9de8997d1da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140622640 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 95.prim_prince_test.3140622640
Directory /workspace/95.prim_prince_test/latest

Test location /workspace/coverage/default/96.prim_prince_test.635279921
Short name T91
Test name
Test status
Simulation time 1520408015 ps
CPU time 25.49 seconds
Started Jun 27 06:10:30 PM PDT 24
Finished Jun 27 06:11:04 PM PDT 24
Peak memory 146736 kb
Host smart-06c1811e-a6b3-49ff-b942-47295d8b1046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635279921 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 96.prim_prince_test.635279921
Directory /workspace/96.prim_prince_test/latest

Test location /workspace/coverage/default/97.prim_prince_test.947526584
Short name T168
Test name
Test status
Simulation time 3119196589 ps
CPU time 52.05 seconds
Started Jun 27 06:10:27 PM PDT 24
Finished Jun 27 06:11:32 PM PDT 24
Peak memory 146796 kb
Host smart-5aea111d-76b1-4428-a289-ded05222a254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947526584 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 97.prim_prince_test.947526584
Directory /workspace/97.prim_prince_test/latest

Test location /workspace/coverage/default/98.prim_prince_test.1483821116
Short name T165
Test name
Test status
Simulation time 2748745958 ps
CPU time 44.36 seconds
Started Jun 27 06:10:31 PM PDT 24
Finished Jun 27 06:11:26 PM PDT 24
Peak memory 146752 kb
Host smart-2a330934-e479-4559-83b7-a0c8228be321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483821116 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 98.prim_prince_test.1483821116
Directory /workspace/98.prim_prince_test/latest

Test location /workspace/coverage/default/99.prim_prince_test.4094793869
Short name T415
Test name
Test status
Simulation time 1924922929 ps
CPU time 31.14 seconds
Started Jun 27 06:10:31 PM PDT 24
Finished Jun 27 06:11:11 PM PDT 24
Peak memory 146688 kb
Host smart-e3ba8bda-0100-4d5e-853d-76da4abcf09a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094793869 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 99.prim_prince_test.4094793869
Directory /workspace/99.prim_prince_test/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%