SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 | 100.00 | 100.00 |
T251 | /workspace/coverage/default/344.prim_prince_test.3514314796 | Aug 12 04:25:18 PM PDT 24 | Aug 12 04:26:21 PM PDT 24 | 3086934965 ps | ||
T252 | /workspace/coverage/default/117.prim_prince_test.1105832058 | Aug 12 04:24:56 PM PDT 24 | Aug 12 04:25:30 PM PDT 24 | 1538122815 ps | ||
T253 | /workspace/coverage/default/210.prim_prince_test.3387063725 | Aug 12 04:23:46 PM PDT 24 | Aug 12 04:24:50 PM PDT 24 | 3020461729 ps | ||
T254 | /workspace/coverage/default/485.prim_prince_test.660523861 | Aug 12 04:25:19 PM PDT 24 | Aug 12 04:26:19 PM PDT 24 | 2760793106 ps | ||
T255 | /workspace/coverage/default/383.prim_prince_test.3016748156 | Aug 12 04:24:26 PM PDT 24 | Aug 12 04:25:30 PM PDT 24 | 3130049533 ps | ||
T256 | /workspace/coverage/default/394.prim_prince_test.2334670980 | Aug 12 04:26:08 PM PDT 24 | Aug 12 04:27:00 PM PDT 24 | 2564821143 ps | ||
T257 | /workspace/coverage/default/368.prim_prince_test.2028760351 | Aug 12 04:26:39 PM PDT 24 | Aug 12 04:27:24 PM PDT 24 | 2228456829 ps | ||
T258 | /workspace/coverage/default/120.prim_prince_test.606766401 | Aug 12 04:24:55 PM PDT 24 | Aug 12 04:25:55 PM PDT 24 | 2853604376 ps | ||
T259 | /workspace/coverage/default/36.prim_prince_test.2274861826 | Aug 12 04:21:16 PM PDT 24 | Aug 12 04:21:44 PM PDT 24 | 1417621817 ps | ||
T260 | /workspace/coverage/default/97.prim_prince_test.4186921186 | Aug 12 04:23:30 PM PDT 24 | Aug 12 04:24:06 PM PDT 24 | 1716096188 ps | ||
T261 | /workspace/coverage/default/177.prim_prince_test.3062814751 | Aug 12 04:23:46 PM PDT 24 | Aug 12 04:24:13 PM PDT 24 | 1260347826 ps | ||
T262 | /workspace/coverage/default/479.prim_prince_test.2697691637 | Aug 12 04:26:25 PM PDT 24 | Aug 12 04:27:07 PM PDT 24 | 2102148444 ps | ||
T263 | /workspace/coverage/default/260.prim_prince_test.3082008661 | Aug 12 04:26:29 PM PDT 24 | Aug 12 04:27:36 PM PDT 24 | 3225358021 ps | ||
T264 | /workspace/coverage/default/8.prim_prince_test.3421796576 | Aug 12 04:21:10 PM PDT 24 | Aug 12 04:21:45 PM PDT 24 | 1681960954 ps | ||
T265 | /workspace/coverage/default/132.prim_prince_test.1268939944 | Aug 12 04:22:01 PM PDT 24 | Aug 12 04:22:24 PM PDT 24 | 1056593634 ps | ||
T266 | /workspace/coverage/default/78.prim_prince_test.1173378826 | Aug 12 04:26:32 PM PDT 24 | Aug 12 04:27:21 PM PDT 24 | 2440251132 ps | ||
T267 | /workspace/coverage/default/185.prim_prince_test.3094267650 | Aug 12 04:26:14 PM PDT 24 | Aug 12 04:27:03 PM PDT 24 | 2502790725 ps | ||
T268 | /workspace/coverage/default/398.prim_prince_test.4294361447 | Aug 12 04:26:00 PM PDT 24 | Aug 12 04:26:18 PM PDT 24 | 858540864 ps | ||
T269 | /workspace/coverage/default/379.prim_prince_test.1638336325 | Aug 12 04:27:55 PM PDT 24 | Aug 12 04:28:53 PM PDT 24 | 3106506418 ps | ||
T270 | /workspace/coverage/default/337.prim_prince_test.550811627 | Aug 12 04:26:59 PM PDT 24 | Aug 12 04:27:42 PM PDT 24 | 2208563949 ps | ||
T271 | /workspace/coverage/default/38.prim_prince_test.3045078675 | Aug 12 04:22:16 PM PDT 24 | Aug 12 04:22:52 PM PDT 24 | 1769544292 ps | ||
T272 | /workspace/coverage/default/313.prim_prince_test.3091896064 | Aug 12 04:26:57 PM PDT 24 | Aug 12 04:27:29 PM PDT 24 | 1616047917 ps | ||
T273 | /workspace/coverage/default/400.prim_prince_test.680269592 | Aug 12 04:26:29 PM PDT 24 | Aug 12 04:27:15 PM PDT 24 | 2427861111 ps | ||
T274 | /workspace/coverage/default/167.prim_prince_test.4233140790 | Aug 12 04:26:17 PM PDT 24 | Aug 12 04:26:43 PM PDT 24 | 1275946945 ps | ||
T275 | /workspace/coverage/default/228.prim_prince_test.925891985 | Aug 12 04:23:44 PM PDT 24 | Aug 12 04:24:02 PM PDT 24 | 867131232 ps | ||
T276 | /workspace/coverage/default/12.prim_prince_test.272274017 | Aug 12 04:21:16 PM PDT 24 | Aug 12 04:21:58 PM PDT 24 | 2144329818 ps | ||
T277 | /workspace/coverage/default/388.prim_prince_test.2987932357 | Aug 12 04:24:25 PM PDT 24 | Aug 12 04:25:16 PM PDT 24 | 2484637427 ps | ||
T278 | /workspace/coverage/default/442.prim_prince_test.1092972496 | Aug 12 04:26:19 PM PDT 24 | Aug 12 04:26:44 PM PDT 24 | 1289641312 ps | ||
T279 | /workspace/coverage/default/490.prim_prince_test.253374156 | Aug 12 04:25:32 PM PDT 24 | Aug 12 04:26:39 PM PDT 24 | 3337115275 ps | ||
T280 | /workspace/coverage/default/288.prim_prince_test.1717985798 | Aug 12 04:26:26 PM PDT 24 | Aug 12 04:26:51 PM PDT 24 | 1261291021 ps | ||
T281 | /workspace/coverage/default/242.prim_prince_test.2599343168 | Aug 12 04:24:19 PM PDT 24 | Aug 12 04:25:23 PM PDT 24 | 2933670459 ps | ||
T282 | /workspace/coverage/default/85.prim_prince_test.3767589254 | Aug 12 04:26:33 PM PDT 24 | Aug 12 04:27:23 PM PDT 24 | 2512737260 ps | ||
T283 | /workspace/coverage/default/435.prim_prince_test.739294676 | Aug 12 04:26:47 PM PDT 24 | Aug 12 04:28:03 PM PDT 24 | 3714921957 ps | ||
T284 | /workspace/coverage/default/451.prim_prince_test.2461269338 | Aug 12 04:26:20 PM PDT 24 | Aug 12 04:26:55 PM PDT 24 | 1816059615 ps | ||
T285 | /workspace/coverage/default/164.prim_prince_test.43532861 | Aug 12 04:24:05 PM PDT 24 | Aug 12 04:24:55 PM PDT 24 | 2496689423 ps | ||
T286 | /workspace/coverage/default/287.prim_prince_test.2951714156 | Aug 12 04:26:29 PM PDT 24 | Aug 12 04:26:54 PM PDT 24 | 1306092089 ps | ||
T287 | /workspace/coverage/default/273.prim_prince_test.4273214919 | Aug 12 04:26:26 PM PDT 24 | Aug 12 04:27:24 PM PDT 24 | 2850429719 ps | ||
T288 | /workspace/coverage/default/214.prim_prince_test.423205613 | Aug 12 04:23:42 PM PDT 24 | Aug 12 04:24:45 PM PDT 24 | 3058667990 ps | ||
T289 | /workspace/coverage/default/94.prim_prince_test.1488384722 | Aug 12 04:26:51 PM PDT 24 | Aug 12 04:27:14 PM PDT 24 | 1147024904 ps | ||
T290 | /workspace/coverage/default/141.prim_prince_test.2107405663 | Aug 12 04:26:41 PM PDT 24 | Aug 12 04:27:20 PM PDT 24 | 1885904094 ps | ||
T291 | /workspace/coverage/default/151.prim_prince_test.506334755 | Aug 12 04:26:17 PM PDT 24 | Aug 12 04:27:01 PM PDT 24 | 2210290529 ps | ||
T292 | /workspace/coverage/default/1.prim_prince_test.3311822385 | Aug 12 04:21:05 PM PDT 24 | Aug 12 04:21:22 PM PDT 24 | 847751417 ps | ||
T293 | /workspace/coverage/default/498.prim_prince_test.3218169266 | Aug 12 04:25:33 PM PDT 24 | Aug 12 04:26:19 PM PDT 24 | 2286711189 ps | ||
T294 | /workspace/coverage/default/257.prim_prince_test.1004636816 | Aug 12 04:25:47 PM PDT 24 | Aug 12 04:26:50 PM PDT 24 | 3195298238 ps | ||
T295 | /workspace/coverage/default/87.prim_prince_test.3079453509 | Aug 12 04:26:38 PM PDT 24 | Aug 12 04:27:28 PM PDT 24 | 2613372103 ps | ||
T296 | /workspace/coverage/default/286.prim_prince_test.3596087887 | Aug 12 04:26:30 PM PDT 24 | Aug 12 04:26:46 PM PDT 24 | 784852195 ps | ||
T297 | /workspace/coverage/default/28.prim_prince_test.758283388 | Aug 12 04:21:16 PM PDT 24 | Aug 12 04:21:57 PM PDT 24 | 2008879552 ps | ||
T298 | /workspace/coverage/default/280.prim_prince_test.2596057996 | Aug 12 04:25:09 PM PDT 24 | Aug 12 04:26:20 PM PDT 24 | 3430538481 ps | ||
T299 | /workspace/coverage/default/218.prim_prince_test.184621887 | Aug 12 04:27:04 PM PDT 24 | Aug 12 04:27:56 PM PDT 24 | 2649002675 ps | ||
T300 | /workspace/coverage/default/381.prim_prince_test.675875936 | Aug 12 04:24:38 PM PDT 24 | Aug 12 04:25:23 PM PDT 24 | 2171687154 ps | ||
T301 | /workspace/coverage/default/291.prim_prince_test.4037524766 | Aug 12 04:27:34 PM PDT 24 | Aug 12 04:28:37 PM PDT 24 | 3336260729 ps | ||
T302 | /workspace/coverage/default/109.prim_prince_test.4119594861 | Aug 12 04:22:40 PM PDT 24 | Aug 12 04:23:27 PM PDT 24 | 2376261192 ps | ||
T303 | /workspace/coverage/default/241.prim_prince_test.3047724967 | Aug 12 04:24:09 PM PDT 24 | Aug 12 04:25:22 PM PDT 24 | 3434857554 ps | ||
T304 | /workspace/coverage/default/378.prim_prince_test.2565659434 | Aug 12 04:24:38 PM PDT 24 | Aug 12 04:25:45 PM PDT 24 | 3316480741 ps | ||
T305 | /workspace/coverage/default/113.prim_prince_test.3195966340 | Aug 12 04:23:30 PM PDT 24 | Aug 12 04:24:10 PM PDT 24 | 1932876843 ps | ||
T306 | /workspace/coverage/default/208.prim_prince_test.3744563757 | Aug 12 04:23:25 PM PDT 24 | Aug 12 04:24:32 PM PDT 24 | 3218637345 ps | ||
T307 | /workspace/coverage/default/339.prim_prince_test.395268446 | Aug 12 04:23:51 PM PDT 24 | Aug 12 04:24:23 PM PDT 24 | 1495223238 ps | ||
T308 | /workspace/coverage/default/227.prim_prince_test.2099564378 | Aug 12 04:23:46 PM PDT 24 | Aug 12 04:24:28 PM PDT 24 | 2053055297 ps | ||
T309 | /workspace/coverage/default/440.prim_prince_test.3666114704 | Aug 12 04:26:19 PM PDT 24 | Aug 12 04:27:06 PM PDT 24 | 2399614264 ps | ||
T310 | /workspace/coverage/default/296.prim_prince_test.231032620 | Aug 12 04:26:26 PM PDT 24 | Aug 12 04:27:27 PM PDT 24 | 3246390567 ps | ||
T311 | /workspace/coverage/default/74.prim_prince_test.242977817 | Aug 12 04:22:55 PM PDT 24 | Aug 12 04:23:21 PM PDT 24 | 1205012002 ps | ||
T312 | /workspace/coverage/default/324.prim_prince_test.369086625 | Aug 12 04:27:24 PM PDT 24 | Aug 12 04:28:25 PM PDT 24 | 3140972860 ps | ||
T313 | /workspace/coverage/default/81.prim_prince_test.2615640624 | Aug 12 04:26:46 PM PDT 24 | Aug 12 04:27:03 PM PDT 24 | 814270065 ps | ||
T314 | /workspace/coverage/default/434.prim_prince_test.717978328 | Aug 12 04:26:13 PM PDT 24 | Aug 12 04:27:18 PM PDT 24 | 3095899372 ps | ||
T315 | /workspace/coverage/default/467.prim_prince_test.139750426 | Aug 12 04:26:32 PM PDT 24 | Aug 12 04:27:15 PM PDT 24 | 2157621309 ps | ||
T316 | /workspace/coverage/default/493.prim_prince_test.2578512700 | Aug 12 04:25:31 PM PDT 24 | Aug 12 04:25:59 PM PDT 24 | 1306234122 ps | ||
T317 | /workspace/coverage/default/292.prim_prince_test.2453048997 | Aug 12 04:26:25 PM PDT 24 | Aug 12 04:27:08 PM PDT 24 | 2075788780 ps | ||
T318 | /workspace/coverage/default/365.prim_prince_test.2964685457 | Aug 12 04:26:39 PM PDT 24 | Aug 12 04:27:04 PM PDT 24 | 1190596441 ps | ||
T319 | /workspace/coverage/default/297.prim_prince_test.1283718715 | Aug 12 04:26:25 PM PDT 24 | Aug 12 04:27:19 PM PDT 24 | 2850135400 ps | ||
T320 | /workspace/coverage/default/26.prim_prince_test.3143490151 | Aug 12 04:21:16 PM PDT 24 | Aug 12 04:22:25 PM PDT 24 | 3377202790 ps | ||
T321 | /workspace/coverage/default/217.prim_prince_test.2820736169 | Aug 12 04:25:29 PM PDT 24 | Aug 12 04:26:31 PM PDT 24 | 2882234763 ps | ||
T322 | /workspace/coverage/default/350.prim_prince_test.2594594091 | Aug 12 04:23:49 PM PDT 24 | Aug 12 04:25:03 PM PDT 24 | 3422984353 ps | ||
T323 | /workspace/coverage/default/51.prim_prince_test.1214144274 | Aug 12 04:22:18 PM PDT 24 | Aug 12 04:22:51 PM PDT 24 | 1732782070 ps | ||
T324 | /workspace/coverage/default/136.prim_prince_test.2179543262 | Aug 12 04:26:50 PM PDT 24 | Aug 12 04:27:36 PM PDT 24 | 2398673687 ps | ||
T325 | /workspace/coverage/default/115.prim_prince_test.3726149527 | Aug 12 04:26:32 PM PDT 24 | Aug 12 04:27:01 PM PDT 24 | 1478802416 ps | ||
T326 | /workspace/coverage/default/173.prim_prince_test.3493717308 | Aug 12 04:26:16 PM PDT 24 | Aug 12 04:26:56 PM PDT 24 | 1984244865 ps | ||
T327 | /workspace/coverage/default/152.prim_prince_test.298985161 | Aug 12 04:23:07 PM PDT 24 | Aug 12 04:24:02 PM PDT 24 | 2760239576 ps | ||
T328 | /workspace/coverage/default/403.prim_prince_test.517470582 | Aug 12 04:26:23 PM PDT 24 | Aug 12 04:26:54 PM PDT 24 | 1519292144 ps | ||
T329 | /workspace/coverage/default/222.prim_prince_test.3287266649 | Aug 12 04:27:50 PM PDT 24 | Aug 12 04:28:35 PM PDT 24 | 2366772900 ps | ||
T330 | /workspace/coverage/default/309.prim_prince_test.2744081598 | Aug 12 04:24:12 PM PDT 24 | Aug 12 04:25:23 PM PDT 24 | 3414261607 ps | ||
T331 | /workspace/coverage/default/421.prim_prince_test.3175396521 | Aug 12 04:25:56 PM PDT 24 | Aug 12 04:26:51 PM PDT 24 | 2775392544 ps | ||
T332 | /workspace/coverage/default/437.prim_prince_test.2585748675 | Aug 12 04:26:09 PM PDT 24 | Aug 12 04:27:18 PM PDT 24 | 3366421106 ps | ||
T333 | /workspace/coverage/default/188.prim_prince_test.3382481888 | Aug 12 04:26:16 PM PDT 24 | Aug 12 04:26:59 PM PDT 24 | 2148861539 ps | ||
T334 | /workspace/coverage/default/163.prim_prince_test.1966584205 | Aug 12 04:26:16 PM PDT 24 | Aug 12 04:27:28 PM PDT 24 | 3677088273 ps | ||
T335 | /workspace/coverage/default/239.prim_prince_test.1581714712 | Aug 12 04:23:14 PM PDT 24 | Aug 12 04:23:54 PM PDT 24 | 1866463268 ps | ||
T336 | /workspace/coverage/default/372.prim_prince_test.2458136119 | Aug 12 04:24:06 PM PDT 24 | Aug 12 04:24:51 PM PDT 24 | 2137352692 ps | ||
T337 | /workspace/coverage/default/448.prim_prince_test.2101128429 | Aug 12 04:26:32 PM PDT 24 | Aug 12 04:27:17 PM PDT 24 | 2279852302 ps | ||
T338 | /workspace/coverage/default/496.prim_prince_test.2032165391 | Aug 12 04:25:33 PM PDT 24 | Aug 12 04:25:50 PM PDT 24 | 900240537 ps | ||
T339 | /workspace/coverage/default/330.prim_prince_test.694302760 | Aug 12 04:26:43 PM PDT 24 | Aug 12 04:27:42 PM PDT 24 | 3185849214 ps | ||
T340 | /workspace/coverage/default/207.prim_prince_test.1427846814 | Aug 12 04:23:38 PM PDT 24 | Aug 12 04:23:58 PM PDT 24 | 928599870 ps | ||
T341 | /workspace/coverage/default/405.prim_prince_test.1882726149 | Aug 12 04:26:29 PM PDT 24 | Aug 12 04:27:07 PM PDT 24 | 1991229678 ps | ||
T342 | /workspace/coverage/default/67.prim_prince_test.3779530108 | Aug 12 04:22:17 PM PDT 24 | Aug 12 04:22:38 PM PDT 24 | 1026016496 ps | ||
T343 | /workspace/coverage/default/30.prim_prince_test.3552843277 | Aug 12 04:21:15 PM PDT 24 | Aug 12 04:22:23 PM PDT 24 | 3499296770 ps | ||
T344 | /workspace/coverage/default/341.prim_prince_test.3461548931 | Aug 12 04:23:47 PM PDT 24 | Aug 12 04:24:06 PM PDT 24 | 852310931 ps | ||
T345 | /workspace/coverage/default/64.prim_prince_test.1065983833 | Aug 12 04:21:16 PM PDT 24 | Aug 12 04:21:32 PM PDT 24 | 776441257 ps | ||
T346 | /workspace/coverage/default/79.prim_prince_test.546106176 | Aug 12 04:26:26 PM PDT 24 | Aug 12 04:26:43 PM PDT 24 | 839918248 ps | ||
T347 | /workspace/coverage/default/446.prim_prince_test.2599851561 | Aug 12 04:26:28 PM PDT 24 | Aug 12 04:27:00 PM PDT 24 | 1629507266 ps | ||
T348 | /workspace/coverage/default/155.prim_prince_test.43260253 | Aug 12 04:26:16 PM PDT 24 | Aug 12 04:27:02 PM PDT 24 | 2285998659 ps | ||
T349 | /workspace/coverage/default/282.prim_prince_test.824354489 | Aug 12 04:23:25 PM PDT 24 | Aug 12 04:24:18 PM PDT 24 | 2501462879 ps | ||
T350 | /workspace/coverage/default/246.prim_prince_test.2825075337 | Aug 12 04:25:57 PM PDT 24 | Aug 12 04:27:03 PM PDT 24 | 3424978048 ps | ||
T351 | /workspace/coverage/default/418.prim_prince_test.4038887049 | Aug 12 04:25:46 PM PDT 24 | Aug 12 04:26:07 PM PDT 24 | 1052229453 ps | ||
T352 | /workspace/coverage/default/104.prim_prince_test.4015326364 | Aug 12 04:26:25 PM PDT 24 | Aug 12 04:27:30 PM PDT 24 | 3354753304 ps | ||
T353 | /workspace/coverage/default/255.prim_prince_test.1180612318 | Aug 12 04:26:38 PM PDT 24 | Aug 12 04:27:21 PM PDT 24 | 2300277457 ps | ||
T354 | /workspace/coverage/default/77.prim_prince_test.727924210 | Aug 12 04:24:11 PM PDT 24 | Aug 12 04:24:47 PM PDT 24 | 1744767910 ps | ||
T355 | /workspace/coverage/default/376.prim_prince_test.1786829241 | Aug 12 04:27:43 PM PDT 24 | Aug 12 04:27:59 PM PDT 24 | 826169977 ps | ||
T356 | /workspace/coverage/default/236.prim_prince_test.2063500540 | Aug 12 04:27:49 PM PDT 24 | Aug 12 04:28:27 PM PDT 24 | 1939230189 ps | ||
T357 | /workspace/coverage/default/298.prim_prince_test.2900152954 | Aug 12 04:26:42 PM PDT 24 | Aug 12 04:27:36 PM PDT 24 | 2750240425 ps | ||
T358 | /workspace/coverage/default/423.prim_prince_test.1172049698 | Aug 12 04:24:42 PM PDT 24 | Aug 12 04:25:07 PM PDT 24 | 1204609156 ps | ||
T359 | /workspace/coverage/default/407.prim_prince_test.4252437539 | Aug 12 04:26:22 PM PDT 24 | Aug 12 04:26:44 PM PDT 24 | 1124654634 ps | ||
T360 | /workspace/coverage/default/469.prim_prince_test.1931322749 | Aug 12 04:26:19 PM PDT 24 | Aug 12 04:27:08 PM PDT 24 | 2587683563 ps | ||
T361 | /workspace/coverage/default/195.prim_prince_test.834576303 | Aug 12 04:22:28 PM PDT 24 | Aug 12 04:23:33 PM PDT 24 | 3013717206 ps | ||
T362 | /workspace/coverage/default/484.prim_prince_test.1995626617 | Aug 12 04:25:24 PM PDT 24 | Aug 12 04:26:07 PM PDT 24 | 2153338340 ps | ||
T363 | /workspace/coverage/default/253.prim_prince_test.1534051894 | Aug 12 04:26:02 PM PDT 24 | Aug 12 04:26:55 PM PDT 24 | 2685706883 ps | ||
T364 | /workspace/coverage/default/450.prim_prince_test.2179476817 | Aug 12 04:26:24 PM PDT 24 | Aug 12 04:27:17 PM PDT 24 | 2761113391 ps | ||
T365 | /workspace/coverage/default/62.prim_prince_test.2683049564 | Aug 12 04:22:36 PM PDT 24 | Aug 12 04:22:57 PM PDT 24 | 1011648636 ps | ||
T366 | /workspace/coverage/default/265.prim_prince_test.854994009 | Aug 12 04:24:03 PM PDT 24 | Aug 12 04:24:23 PM PDT 24 | 934803320 ps | ||
T367 | /workspace/coverage/default/374.prim_prince_test.701120206 | Aug 12 04:24:58 PM PDT 24 | Aug 12 04:26:09 PM PDT 24 | 3310204383 ps | ||
T368 | /workspace/coverage/default/351.prim_prince_test.1977509180 | Aug 12 04:26:50 PM PDT 24 | Aug 12 04:27:28 PM PDT 24 | 1934924670 ps | ||
T369 | /workspace/coverage/default/384.prim_prince_test.3738435606 | Aug 12 04:25:17 PM PDT 24 | Aug 12 04:25:39 PM PDT 24 | 1036207527 ps | ||
T370 | /workspace/coverage/default/445.prim_prince_test.1313333252 | Aug 12 04:26:28 PM PDT 24 | Aug 12 04:27:18 PM PDT 24 | 2633953028 ps | ||
T371 | /workspace/coverage/default/13.prim_prince_test.2559691589 | Aug 12 04:21:15 PM PDT 24 | Aug 12 04:21:37 PM PDT 24 | 1079137250 ps | ||
T372 | /workspace/coverage/default/358.prim_prince_test.540558508 | Aug 12 04:26:30 PM PDT 24 | Aug 12 04:26:47 PM PDT 24 | 880432123 ps | ||
T373 | /workspace/coverage/default/23.prim_prince_test.2077720608 | Aug 12 04:21:14 PM PDT 24 | Aug 12 04:22:33 PM PDT 24 | 3621399162 ps | ||
T374 | /workspace/coverage/default/272.prim_prince_test.2348839711 | Aug 12 04:26:17 PM PDT 24 | Aug 12 04:27:14 PM PDT 24 | 2906171636 ps | ||
T375 | /workspace/coverage/default/315.prim_prince_test.1851020879 | Aug 12 04:26:57 PM PDT 24 | Aug 12 04:27:29 PM PDT 24 | 1656996874 ps | ||
T376 | /workspace/coverage/default/259.prim_prince_test.2106926375 | Aug 12 04:26:02 PM PDT 24 | Aug 12 04:26:31 PM PDT 24 | 1475202950 ps | ||
T377 | /workspace/coverage/default/454.prim_prince_test.2507294240 | Aug 12 04:24:57 PM PDT 24 | Aug 12 04:25:17 PM PDT 24 | 1023016084 ps | ||
T378 | /workspace/coverage/default/411.prim_prince_test.2119414414 | Aug 12 04:26:13 PM PDT 24 | Aug 12 04:26:35 PM PDT 24 | 1095574824 ps | ||
T379 | /workspace/coverage/default/204.prim_prince_test.3596644328 | Aug 12 04:26:15 PM PDT 24 | Aug 12 04:27:11 PM PDT 24 | 2761542609 ps | ||
T380 | /workspace/coverage/default/416.prim_prince_test.3955627870 | Aug 12 04:26:00 PM PDT 24 | Aug 12 04:26:22 PM PDT 24 | 1064576741 ps | ||
T381 | /workspace/coverage/default/180.prim_prince_test.3583668880 | Aug 12 04:24:12 PM PDT 24 | Aug 12 04:24:35 PM PDT 24 | 1089674697 ps | ||
T382 | /workspace/coverage/default/366.prim_prince_test.4992522 | Aug 12 04:26:34 PM PDT 24 | Aug 12 04:27:39 PM PDT 24 | 3220571938 ps | ||
T383 | /workspace/coverage/default/189.prim_prince_test.2586116809 | Aug 12 04:25:47 PM PDT 24 | Aug 12 04:26:30 PM PDT 24 | 2131865234 ps | ||
T384 | /workspace/coverage/default/349.prim_prince_test.1451336463 | Aug 12 04:26:48 PM PDT 24 | Aug 12 04:27:56 PM PDT 24 | 3629238708 ps | ||
T385 | /workspace/coverage/default/371.prim_prince_test.1898112893 | Aug 12 04:27:50 PM PDT 24 | Aug 12 04:28:51 PM PDT 24 | 3332580894 ps | ||
T386 | /workspace/coverage/default/264.prim_prince_test.4284746021 | Aug 12 04:26:00 PM PDT 24 | Aug 12 04:27:01 PM PDT 24 | 3040932840 ps | ||
T387 | /workspace/coverage/default/226.prim_prince_test.3048428379 | Aug 12 04:22:44 PM PDT 24 | Aug 12 04:23:40 PM PDT 24 | 2809464428 ps | ||
T388 | /workspace/coverage/default/304.prim_prince_test.1532162084 | Aug 12 04:26:17 PM PDT 24 | Aug 12 04:26:58 PM PDT 24 | 2049030181 ps | ||
T389 | /workspace/coverage/default/470.prim_prince_test.355450711 | Aug 12 04:26:32 PM PDT 24 | Aug 12 04:27:01 PM PDT 24 | 1412128520 ps | ||
T390 | /workspace/coverage/default/299.prim_prince_test.2056208899 | Aug 12 04:26:27 PM PDT 24 | Aug 12 04:27:14 PM PDT 24 | 2386561826 ps | ||
T391 | /workspace/coverage/default/25.prim_prince_test.1428516040 | Aug 12 04:22:18 PM PDT 24 | Aug 12 04:23:05 PM PDT 24 | 2422871747 ps | ||
T392 | /workspace/coverage/default/92.prim_prince_test.1637861754 | Aug 12 04:26:34 PM PDT 24 | Aug 12 04:27:47 PM PDT 24 | 3730113372 ps | ||
T393 | /workspace/coverage/default/348.prim_prince_test.2589509344 | Aug 12 04:26:54 PM PDT 24 | Aug 12 04:27:19 PM PDT 24 | 1266803709 ps | ||
T394 | /workspace/coverage/default/233.prim_prince_test.2449490550 | Aug 12 04:23:53 PM PDT 24 | Aug 12 04:24:32 PM PDT 24 | 1847210696 ps | ||
T395 | /workspace/coverage/default/441.prim_prince_test.1451772275 | Aug 12 04:24:49 PM PDT 24 | Aug 12 04:25:33 PM PDT 24 | 1998543714 ps | ||
T396 | /workspace/coverage/default/145.prim_prince_test.2135565285 | Aug 12 04:23:44 PM PDT 24 | Aug 12 04:24:41 PM PDT 24 | 2780558582 ps | ||
T397 | /workspace/coverage/default/127.prim_prince_test.331424213 | Aug 12 04:26:41 PM PDT 24 | Aug 12 04:27:07 PM PDT 24 | 1284928318 ps | ||
T398 | /workspace/coverage/default/43.prim_prince_test.3536456373 | Aug 12 04:22:30 PM PDT 24 | Aug 12 04:23:21 PM PDT 24 | 2476902413 ps | ||
T399 | /workspace/coverage/default/124.prim_prince_test.1494865517 | Aug 12 04:23:03 PM PDT 24 | Aug 12 04:23:28 PM PDT 24 | 1182758083 ps | ||
T400 | /workspace/coverage/default/453.prim_prince_test.3863181913 | Aug 12 04:24:56 PM PDT 24 | Aug 12 04:26:13 PM PDT 24 | 3637338946 ps | ||
T401 | /workspace/coverage/default/408.prim_prince_test.3536171241 | Aug 12 04:26:00 PM PDT 24 | Aug 12 04:27:06 PM PDT 24 | 3261498159 ps | ||
T402 | /workspace/coverage/default/157.prim_prince_test.604587133 | Aug 12 04:22:02 PM PDT 24 | Aug 12 04:23:11 PM PDT 24 | 3194801197 ps | ||
T403 | /workspace/coverage/default/158.prim_prince_test.2720112916 | Aug 12 04:24:38 PM PDT 24 | Aug 12 04:25:27 PM PDT 24 | 2386816253 ps | ||
T404 | /workspace/coverage/default/276.prim_prince_test.954658976 | Aug 12 04:26:28 PM PDT 24 | Aug 12 04:27:36 PM PDT 24 | 3543799546 ps | ||
T405 | /workspace/coverage/default/159.prim_prince_test.3137918097 | Aug 12 04:22:35 PM PDT 24 | Aug 12 04:23:16 PM PDT 24 | 1954966876 ps | ||
T406 | /workspace/coverage/default/225.prim_prince_test.2728957084 | Aug 12 04:23:44 PM PDT 24 | Aug 12 04:24:12 PM PDT 24 | 1342123766 ps | ||
T407 | /workspace/coverage/default/102.prim_prince_test.3101442087 | Aug 12 04:23:42 PM PDT 24 | Aug 12 04:24:52 PM PDT 24 | 3249458941 ps | ||
T408 | /workspace/coverage/default/249.prim_prince_test.398017060 | Aug 12 04:26:32 PM PDT 24 | Aug 12 04:26:59 PM PDT 24 | 1354695815 ps | ||
T409 | /workspace/coverage/default/424.prim_prince_test.1315255327 | Aug 12 04:26:10 PM PDT 24 | Aug 12 04:26:50 PM PDT 24 | 1997244471 ps | ||
T410 | /workspace/coverage/default/4.prim_prince_test.2019426350 | Aug 12 04:21:08 PM PDT 24 | Aug 12 04:21:43 PM PDT 24 | 1734487802 ps | ||
T411 | /workspace/coverage/default/406.prim_prince_test.3866435033 | Aug 12 04:26:00 PM PDT 24 | Aug 12 04:26:19 PM PDT 24 | 921667681 ps | ||
T412 | /workspace/coverage/default/172.prim_prince_test.17995616 | Aug 12 04:26:17 PM PDT 24 | Aug 12 04:26:42 PM PDT 24 | 1234962982 ps | ||
T413 | /workspace/coverage/default/327.prim_prince_test.1164392567 | Aug 12 04:26:30 PM PDT 24 | Aug 12 04:26:46 PM PDT 24 | 787530582 ps | ||
T414 | /workspace/coverage/default/33.prim_prince_test.3109338176 | Aug 12 04:21:06 PM PDT 24 | Aug 12 04:21:42 PM PDT 24 | 1809585151 ps | ||
T415 | /workspace/coverage/default/170.prim_prince_test.3047590358 | Aug 12 04:26:17 PM PDT 24 | Aug 12 04:26:43 PM PDT 24 | 1258628901 ps | ||
T416 | /workspace/coverage/default/175.prim_prince_test.75210673 | Aug 12 04:22:07 PM PDT 24 | Aug 12 04:22:50 PM PDT 24 | 1964727430 ps | ||
T417 | /workspace/coverage/default/340.prim_prince_test.3290366551 | Aug 12 04:26:31 PM PDT 24 | Aug 12 04:26:53 PM PDT 24 | 1051050277 ps | ||
T418 | /workspace/coverage/default/20.prim_prince_test.3146270840 | Aug 12 04:21:17 PM PDT 24 | Aug 12 04:22:08 PM PDT 24 | 2562673163 ps | ||
T419 | /workspace/coverage/default/466.prim_prince_test.817211262 | Aug 12 04:26:18 PM PDT 24 | Aug 12 04:26:47 PM PDT 24 | 1428560480 ps | ||
T420 | /workspace/coverage/default/54.prim_prince_test.2274944346 | Aug 12 04:22:18 PM PDT 24 | Aug 12 04:22:48 PM PDT 24 | 1444889059 ps | ||
T421 | /workspace/coverage/default/107.prim_prince_test.713001535 | Aug 12 04:24:06 PM PDT 24 | Aug 12 04:25:06 PM PDT 24 | 2857934453 ps | ||
T422 | /workspace/coverage/default/160.prim_prince_test.1248128754 | Aug 12 04:26:27 PM PDT 24 | Aug 12 04:27:28 PM PDT 24 | 3086045424 ps | ||
T423 | /workspace/coverage/default/426.prim_prince_test.1618251742 | Aug 12 04:25:55 PM PDT 24 | Aug 12 04:26:31 PM PDT 24 | 1815138762 ps | ||
T424 | /workspace/coverage/default/380.prim_prince_test.3410023829 | Aug 12 04:27:43 PM PDT 24 | Aug 12 04:28:21 PM PDT 24 | 2091429411 ps | ||
T425 | /workspace/coverage/default/108.prim_prince_test.2492409072 | Aug 12 04:24:33 PM PDT 24 | Aug 12 04:25:29 PM PDT 24 | 2534533065 ps | ||
T426 | /workspace/coverage/default/5.prim_prince_test.749228886 | Aug 12 04:21:10 PM PDT 24 | Aug 12 04:21:27 PM PDT 24 | 790858008 ps | ||
T427 | /workspace/coverage/default/203.prim_prince_test.1215431106 | Aug 12 04:25:32 PM PDT 24 | Aug 12 04:26:47 PM PDT 24 | 3563577352 ps | ||
T428 | /workspace/coverage/default/385.prim_prince_test.251172904 | Aug 12 04:26:25 PM PDT 24 | Aug 12 04:27:05 PM PDT 24 | 1938716564 ps | ||
T429 | /workspace/coverage/default/267.prim_prince_test.210801146 | Aug 12 04:26:28 PM PDT 24 | Aug 12 04:27:03 PM PDT 24 | 1700804935 ps | ||
T430 | /workspace/coverage/default/56.prim_prince_test.2634654487 | Aug 12 04:26:32 PM PDT 24 | Aug 12 04:26:56 PM PDT 24 | 1251095698 ps | ||
T431 | /workspace/coverage/default/14.prim_prince_test.1726970629 | Aug 12 04:21:17 PM PDT 24 | Aug 12 04:22:11 PM PDT 24 | 2673438586 ps | ||
T432 | /workspace/coverage/default/66.prim_prince_test.3889369630 | Aug 12 04:22:19 PM PDT 24 | Aug 12 04:23:06 PM PDT 24 | 2250279337 ps | ||
T433 | /workspace/coverage/default/133.prim_prince_test.3377707107 | Aug 12 04:26:42 PM PDT 24 | Aug 12 04:27:29 PM PDT 24 | 2454419777 ps | ||
T434 | /workspace/coverage/default/123.prim_prince_test.78933739 | Aug 12 04:26:38 PM PDT 24 | Aug 12 04:26:56 PM PDT 24 | 907823266 ps | ||
T435 | /workspace/coverage/default/240.prim_prince_test.1185342000 | Aug 12 04:26:02 PM PDT 24 | Aug 12 04:26:39 PM PDT 24 | 1828721605 ps | ||
T436 | /workspace/coverage/default/88.prim_prince_test.569559161 | Aug 12 04:26:18 PM PDT 24 | Aug 12 04:27:29 PM PDT 24 | 3731767613 ps | ||
T437 | /workspace/coverage/default/131.prim_prince_test.1921337847 | Aug 12 04:26:51 PM PDT 24 | Aug 12 04:27:56 PM PDT 24 | 3434737513 ps | ||
T438 | /workspace/coverage/default/201.prim_prince_test.1849354613 | Aug 12 04:25:45 PM PDT 24 | Aug 12 04:26:34 PM PDT 24 | 2529383970 ps | ||
T439 | /workspace/coverage/default/196.prim_prince_test.1234894191 | Aug 12 04:26:33 PM PDT 24 | Aug 12 04:27:04 PM PDT 24 | 1536272599 ps | ||
T440 | /workspace/coverage/default/50.prim_prince_test.393997430 | Aug 12 04:21:14 PM PDT 24 | Aug 12 04:21:40 PM PDT 24 | 1271917282 ps | ||
T441 | /workspace/coverage/default/2.prim_prince_test.3966869254 | Aug 12 04:21:10 PM PDT 24 | Aug 12 04:22:12 PM PDT 24 | 2999490142 ps | ||
T442 | /workspace/coverage/default/89.prim_prince_test.1284401910 | Aug 12 04:26:27 PM PDT 24 | Aug 12 04:27:23 PM PDT 24 | 2825626566 ps | ||
T443 | /workspace/coverage/default/361.prim_prince_test.2478542164 | Aug 12 04:26:26 PM PDT 24 | Aug 12 04:27:14 PM PDT 24 | 2427365772 ps | ||
T444 | /workspace/coverage/default/319.prim_prince_test.766579816 | Aug 12 04:26:29 PM PDT 24 | Aug 12 04:27:12 PM PDT 24 | 2151928621 ps | ||
T445 | /workspace/coverage/default/391.prim_prince_test.3447662083 | Aug 12 04:26:09 PM PDT 24 | Aug 12 04:26:35 PM PDT 24 | 1198509186 ps | ||
T446 | /workspace/coverage/default/402.prim_prince_test.3180478833 | Aug 12 04:26:26 PM PDT 24 | Aug 12 04:27:08 PM PDT 24 | 2091653897 ps | ||
T447 | /workspace/coverage/default/37.prim_prince_test.1655474178 | Aug 12 04:21:17 PM PDT 24 | Aug 12 04:22:05 PM PDT 24 | 2426357471 ps | ||
T448 | /workspace/coverage/default/57.prim_prince_test.1047382487 | Aug 12 04:21:17 PM PDT 24 | Aug 12 04:22:23 PM PDT 24 | 3427024716 ps | ||
T449 | /workspace/coverage/default/331.prim_prince_test.434605115 | Aug 12 04:23:40 PM PDT 24 | Aug 12 04:24:43 PM PDT 24 | 2871850407 ps | ||
T450 | /workspace/coverage/default/279.prim_prince_test.3085171458 | Aug 12 04:23:14 PM PDT 24 | Aug 12 04:24:19 PM PDT 24 | 3053551134 ps | ||
T451 | /workspace/coverage/default/281.prim_prince_test.2462463747 | Aug 12 04:23:13 PM PDT 24 | Aug 12 04:24:19 PM PDT 24 | 3130145173 ps | ||
T452 | /workspace/coverage/default/103.prim_prince_test.1801793513 | Aug 12 04:22:37 PM PDT 24 | Aug 12 04:23:11 PM PDT 24 | 1592957510 ps | ||
T453 | /workspace/coverage/default/303.prim_prince_test.2875565011 | Aug 12 04:23:31 PM PDT 24 | Aug 12 04:24:10 PM PDT 24 | 1920471212 ps | ||
T454 | /workspace/coverage/default/223.prim_prince_test.2082391463 | Aug 12 04:27:04 PM PDT 24 | Aug 12 04:27:26 PM PDT 24 | 1116322646 ps | ||
T455 | /workspace/coverage/default/439.prim_prince_test.4008078791 | Aug 12 04:26:28 PM PDT 24 | Aug 12 04:27:18 PM PDT 24 | 2612472965 ps | ||
T456 | /workspace/coverage/default/230.prim_prince_test.3526890413 | Aug 12 04:27:04 PM PDT 24 | Aug 12 04:28:14 PM PDT 24 | 3605369017 ps | ||
T457 | /workspace/coverage/default/414.prim_prince_test.3081012076 | Aug 12 04:26:14 PM PDT 24 | Aug 12 04:26:39 PM PDT 24 | 1319911684 ps | ||
T458 | /workspace/coverage/default/162.prim_prince_test.2334951384 | Aug 12 04:23:06 PM PDT 24 | Aug 12 04:23:29 PM PDT 24 | 1204983645 ps | ||
T459 | /workspace/coverage/default/392.prim_prince_test.125253330 | Aug 12 04:26:14 PM PDT 24 | Aug 12 04:26:40 PM PDT 24 | 1355941231 ps | ||
T460 | /workspace/coverage/default/52.prim_prince_test.3515657409 | Aug 12 04:24:47 PM PDT 24 | Aug 12 04:25:13 PM PDT 24 | 1216391262 ps | ||
T461 | /workspace/coverage/default/295.prim_prince_test.799331164 | Aug 12 04:26:33 PM PDT 24 | Aug 12 04:26:58 PM PDT 24 | 1219160156 ps | ||
T462 | /workspace/coverage/default/363.prim_prince_test.1796243658 | Aug 12 04:24:01 PM PDT 24 | Aug 12 04:24:44 PM PDT 24 | 1985689061 ps | ||
T463 | /workspace/coverage/default/198.prim_prince_test.2096249997 | Aug 12 04:25:45 PM PDT 24 | Aug 12 04:26:36 PM PDT 24 | 2652371421 ps | ||
T464 | /workspace/coverage/default/215.prim_prince_test.169791140 | Aug 12 04:22:44 PM PDT 24 | Aug 12 04:23:54 PM PDT 24 | 3540015631 ps | ||
T465 | /workspace/coverage/default/0.prim_prince_test.4287339837 | Aug 12 04:21:06 PM PDT 24 | Aug 12 04:22:24 PM PDT 24 | 3710085391 ps | ||
T466 | /workspace/coverage/default/369.prim_prince_test.2793882726 | Aug 12 04:26:26 PM PDT 24 | Aug 12 04:26:50 PM PDT 24 | 1190969112 ps | ||
T467 | /workspace/coverage/default/495.prim_prince_test.3187780024 | Aug 12 04:25:30 PM PDT 24 | Aug 12 04:25:47 PM PDT 24 | 788843423 ps | ||
T468 | /workspace/coverage/default/404.prim_prince_test.356805529 | Aug 12 04:26:22 PM PDT 24 | Aug 12 04:27:32 PM PDT 24 | 3634389351 ps | ||
T469 | /workspace/coverage/default/420.prim_prince_test.957695540 | Aug 12 04:26:22 PM PDT 24 | Aug 12 04:27:29 PM PDT 24 | 3557048758 ps | ||
T470 | /workspace/coverage/default/444.prim_prince_test.2228735242 | Aug 12 04:24:51 PM PDT 24 | Aug 12 04:25:25 PM PDT 24 | 1775829646 ps | ||
T471 | /workspace/coverage/default/396.prim_prince_test.2354479710 | Aug 12 04:26:08 PM PDT 24 | Aug 12 04:26:47 PM PDT 24 | 1973746843 ps | ||
T472 | /workspace/coverage/default/166.prim_prince_test.2930296633 | Aug 12 04:26:23 PM PDT 24 | Aug 12 04:26:39 PM PDT 24 | 811906156 ps | ||
T473 | /workspace/coverage/default/399.prim_prince_test.807575941 | Aug 12 04:25:59 PM PDT 24 | Aug 12 04:26:39 PM PDT 24 | 2011967915 ps | ||
T474 | /workspace/coverage/default/393.prim_prince_test.3189845847 | Aug 12 04:26:09 PM PDT 24 | Aug 12 04:27:10 PM PDT 24 | 3015074938 ps | ||
T475 | /workspace/coverage/default/285.prim_prince_test.2729362251 | Aug 12 04:26:55 PM PDT 24 | Aug 12 04:27:50 PM PDT 24 | 2926258893 ps | ||
T476 | /workspace/coverage/default/232.prim_prince_test.339326408 | Aug 12 04:27:50 PM PDT 24 | Aug 12 04:28:38 PM PDT 24 | 2568555945 ps | ||
T477 | /workspace/coverage/default/433.prim_prince_test.250477327 | Aug 12 04:26:37 PM PDT 24 | Aug 12 04:27:56 PM PDT 24 | 3695250100 ps | ||
T478 | /workspace/coverage/default/346.prim_prince_test.3239802643 | Aug 12 04:24:26 PM PDT 24 | Aug 12 04:24:59 PM PDT 24 | 1604409029 ps | ||
T479 | /workspace/coverage/default/354.prim_prince_test.1908244636 | Aug 12 04:26:45 PM PDT 24 | Aug 12 04:27:54 PM PDT 24 | 3699956342 ps | ||
T480 | /workspace/coverage/default/247.prim_prince_test.528911765 | Aug 12 04:25:58 PM PDT 24 | Aug 12 04:26:42 PM PDT 24 | 2191747546 ps | ||
T481 | /workspace/coverage/default/422.prim_prince_test.4250069077 | Aug 12 04:26:10 PM PDT 24 | Aug 12 04:26:40 PM PDT 24 | 1444738081 ps | ||
T482 | /workspace/coverage/default/269.prim_prince_test.2110122173 | Aug 12 04:26:18 PM PDT 24 | Aug 12 04:26:51 PM PDT 24 | 1795066763 ps | ||
T483 | /workspace/coverage/default/370.prim_prince_test.3894282264 | Aug 12 04:23:58 PM PDT 24 | Aug 12 04:24:53 PM PDT 24 | 2704641358 ps | ||
T484 | /workspace/coverage/default/473.prim_prince_test.2533983195 | Aug 12 04:25:14 PM PDT 24 | Aug 12 04:25:39 PM PDT 24 | 1158576834 ps | ||
T485 | /workspace/coverage/default/231.prim_prince_test.3964539389 | Aug 12 04:27:03 PM PDT 24 | Aug 12 04:28:13 PM PDT 24 | 3520279784 ps | ||
T486 | /workspace/coverage/default/121.prim_prince_test.1644833646 | Aug 12 04:26:37 PM PDT 24 | Aug 12 04:27:39 PM PDT 24 | 3256977764 ps | ||
T487 | /workspace/coverage/default/307.prim_prince_test.3753238798 | Aug 12 04:24:02 PM PDT 24 | Aug 12 04:24:35 PM PDT 24 | 1661069422 ps | ||
T488 | /workspace/coverage/default/320.prim_prince_test.3996976536 | Aug 12 04:26:15 PM PDT 24 | Aug 12 04:26:44 PM PDT 24 | 1529802058 ps | ||
T489 | /workspace/coverage/default/125.prim_prince_test.3016634867 | Aug 12 04:26:38 PM PDT 24 | Aug 12 04:27:17 PM PDT 24 | 2071644110 ps | ||
T490 | /workspace/coverage/default/492.prim_prince_test.3341627882 | Aug 12 04:25:32 PM PDT 24 | Aug 12 04:26:15 PM PDT 24 | 2164768749 ps | ||
T491 | /workspace/coverage/default/174.prim_prince_test.3244964220 | Aug 12 04:26:17 PM PDT 24 | Aug 12 04:26:48 PM PDT 24 | 1558038583 ps | ||
T492 | /workspace/coverage/default/224.prim_prince_test.836566117 | Aug 12 04:25:08 PM PDT 24 | Aug 12 04:25:47 PM PDT 24 | 1815350527 ps | ||
T493 | /workspace/coverage/default/6.prim_prince_test.1879327787 | Aug 12 04:21:04 PM PDT 24 | Aug 12 04:21:49 PM PDT 24 | 2183498848 ps | ||
T494 | /workspace/coverage/default/345.prim_prince_test.1925746325 | Aug 12 04:26:59 PM PDT 24 | Aug 12 04:27:25 PM PDT 24 | 1363313609 ps | ||
T495 | /workspace/coverage/default/482.prim_prince_test.2956500790 | Aug 12 04:27:23 PM PDT 24 | Aug 12 04:27:48 PM PDT 24 | 1223072901 ps | ||
T496 | /workspace/coverage/default/55.prim_prince_test.2787707279 | Aug 12 04:23:16 PM PDT 24 | Aug 12 04:24:24 PM PDT 24 | 3108529198 ps | ||
T497 | /workspace/coverage/default/153.prim_prince_test.1255914708 | Aug 12 04:26:16 PM PDT 24 | Aug 12 04:27:06 PM PDT 24 | 2464186118 ps | ||
T498 | /workspace/coverage/default/45.prim_prince_test.839764051 | Aug 12 04:22:16 PM PDT 24 | Aug 12 04:22:49 PM PDT 24 | 1623649667 ps | ||
T499 | /workspace/coverage/default/252.prim_prince_test.726301415 | Aug 12 04:27:04 PM PDT 24 | Aug 12 04:27:20 PM PDT 24 | 793093171 ps | ||
T500 | /workspace/coverage/default/268.prim_prince_test.4016571532 | Aug 12 04:26:33 PM PDT 24 | Aug 12 04:27:37 PM PDT 24 | 3186093911 ps |
Test location | /workspace/coverage/default/116.prim_prince_test.4237586692 |
Short name | T2 |
Test name | |
Test status | |
Simulation time | 2871723763 ps |
CPU time | 47.56 seconds |
Started | Aug 12 04:26:00 PM PDT 24 |
Finished | Aug 12 04:26:57 PM PDT 24 |
Peak memory | 145736 kb |
Host | smart-0985e654-01b3-4f2e-9473-56f3b07ef8b7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4237586692 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 116.prim_prince_test.4237586692 |
Directory | /workspace/116.prim_prince_test/latest |
Test location | /workspace/coverage/default/0.prim_prince_test.4287339837 |
Short name | T465 |
Test name | |
Test status | |
Simulation time | 3710085391 ps |
CPU time | 63.43 seconds |
Started | Aug 12 04:21:06 PM PDT 24 |
Finished | Aug 12 04:22:24 PM PDT 24 |
Peak memory | 146836 kb |
Host | smart-4109b03f-9413-4d3a-b071-06b88c0a56e2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4287339837 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_prince_test.4287339837 |
Directory | /workspace/0.prim_prince_test/latest |
Test location | /workspace/coverage/default/1.prim_prince_test.3311822385 |
Short name | T292 |
Test name | |
Test status | |
Simulation time | 847751417 ps |
CPU time | 14.08 seconds |
Started | Aug 12 04:21:05 PM PDT 24 |
Finished | Aug 12 04:21:22 PM PDT 24 |
Peak memory | 146224 kb |
Host | smart-e6ef3d68-c798-4cd0-9b1e-661879281657 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3311822385 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_prince_test.3311822385 |
Directory | /workspace/1.prim_prince_test/latest |
Test location | /workspace/coverage/default/10.prim_prince_test.2836356840 |
Short name | T229 |
Test name | |
Test status | |
Simulation time | 3106920984 ps |
CPU time | 51.62 seconds |
Started | Aug 12 04:21:08 PM PDT 24 |
Finished | Aug 12 04:22:10 PM PDT 24 |
Peak memory | 146432 kb |
Host | smart-1d5bd208-825e-4349-87f5-78f551c58a34 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2836356840 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_prince_test.2836356840 |
Directory | /workspace/10.prim_prince_test/latest |
Test location | /workspace/coverage/default/100.prim_prince_test.1111712777 |
Short name | T77 |
Test name | |
Test status | |
Simulation time | 1868897289 ps |
CPU time | 30.41 seconds |
Started | Aug 12 04:26:32 PM PDT 24 |
Finished | Aug 12 04:27:08 PM PDT 24 |
Peak memory | 145188 kb |
Host | smart-ebaffa14-4cf7-48df-9d5e-8760c8678b35 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1111712777 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 100.prim_prince_test.1111712777 |
Directory | /workspace/100.prim_prince_test/latest |
Test location | /workspace/coverage/default/101.prim_prince_test.3236800661 |
Short name | T57 |
Test name | |
Test status | |
Simulation time | 3754416813 ps |
CPU time | 61.71 seconds |
Started | Aug 12 04:26:33 PM PDT 24 |
Finished | Aug 12 04:27:48 PM PDT 24 |
Peak memory | 144684 kb |
Host | smart-106007a8-6751-42a1-a933-d6720512b8ac |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3236800661 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 101.prim_prince_test.3236800661 |
Directory | /workspace/101.prim_prince_test/latest |
Test location | /workspace/coverage/default/102.prim_prince_test.3101442087 |
Short name | T407 |
Test name | |
Test status | |
Simulation time | 3249458941 ps |
CPU time | 56.03 seconds |
Started | Aug 12 04:23:42 PM PDT 24 |
Finished | Aug 12 04:24:52 PM PDT 24 |
Peak memory | 146696 kb |
Host | smart-397c5600-9cba-4438-9296-1689db5359d7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3101442087 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 102.prim_prince_test.3101442087 |
Directory | /workspace/102.prim_prince_test/latest |
Test location | /workspace/coverage/default/103.prim_prince_test.1801793513 |
Short name | T452 |
Test name | |
Test status | |
Simulation time | 1592957510 ps |
CPU time | 27.49 seconds |
Started | Aug 12 04:22:37 PM PDT 24 |
Finished | Aug 12 04:23:11 PM PDT 24 |
Peak memory | 146620 kb |
Host | smart-336f3a83-14c7-4f9f-a88e-6f110b9da8df |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1801793513 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 103.prim_prince_test.1801793513 |
Directory | /workspace/103.prim_prince_test/latest |
Test location | /workspace/coverage/default/104.prim_prince_test.4015326364 |
Short name | T352 |
Test name | |
Test status | |
Simulation time | 3354753304 ps |
CPU time | 54.52 seconds |
Started | Aug 12 04:26:25 PM PDT 24 |
Finished | Aug 12 04:27:30 PM PDT 24 |
Peak memory | 146200 kb |
Host | smart-68c41ebf-3bfa-4b9a-befa-4174534df75c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4015326364 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 104.prim_prince_test.4015326364 |
Directory | /workspace/104.prim_prince_test/latest |
Test location | /workspace/coverage/default/105.prim_prince_test.1782039343 |
Short name | T82 |
Test name | |
Test status | |
Simulation time | 1099913058 ps |
CPU time | 18.26 seconds |
Started | Aug 12 04:26:25 PM PDT 24 |
Finished | Aug 12 04:26:47 PM PDT 24 |
Peak memory | 146136 kb |
Host | smart-f60be46d-a71a-4bec-b094-d399064ee626 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1782039343 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 105.prim_prince_test.1782039343 |
Directory | /workspace/105.prim_prince_test/latest |
Test location | /workspace/coverage/default/106.prim_prince_test.3567861365 |
Short name | T182 |
Test name | |
Test status | |
Simulation time | 2483912691 ps |
CPU time | 39.66 seconds |
Started | Aug 12 04:26:10 PM PDT 24 |
Finished | Aug 12 04:26:57 PM PDT 24 |
Peak memory | 145104 kb |
Host | smart-fe8b52ca-d463-4e11-bfe5-9204f93d1749 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3567861365 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 106.prim_prince_test.3567861365 |
Directory | /workspace/106.prim_prince_test/latest |
Test location | /workspace/coverage/default/107.prim_prince_test.713001535 |
Short name | T421 |
Test name | |
Test status | |
Simulation time | 2857934453 ps |
CPU time | 49.14 seconds |
Started | Aug 12 04:24:06 PM PDT 24 |
Finished | Aug 12 04:25:06 PM PDT 24 |
Peak memory | 146628 kb |
Host | smart-b61de9d8-ebff-4042-abc6-1c35129d3958 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=713001535 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 107.prim_prince_test.713001535 |
Directory | /workspace/107.prim_prince_test/latest |
Test location | /workspace/coverage/default/108.prim_prince_test.2492409072 |
Short name | T425 |
Test name | |
Test status | |
Simulation time | 2534533065 ps |
CPU time | 44.18 seconds |
Started | Aug 12 04:24:33 PM PDT 24 |
Finished | Aug 12 04:25:29 PM PDT 24 |
Peak memory | 146728 kb |
Host | smart-3efeb11b-a1ac-4b40-8fb9-3c2719b69e8b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2492409072 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 108.prim_prince_test.2492409072 |
Directory | /workspace/108.prim_prince_test/latest |
Test location | /workspace/coverage/default/109.prim_prince_test.4119594861 |
Short name | T302 |
Test name | |
Test status | |
Simulation time | 2376261192 ps |
CPU time | 39.19 seconds |
Started | Aug 12 04:22:40 PM PDT 24 |
Finished | Aug 12 04:23:27 PM PDT 24 |
Peak memory | 146504 kb |
Host | smart-2d2e9b83-c700-4f8d-aeb2-484de00230e5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4119594861 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 109.prim_prince_test.4119594861 |
Directory | /workspace/109.prim_prince_test/latest |
Test location | /workspace/coverage/default/11.prim_prince_test.2410165563 |
Short name | T48 |
Test name | |
Test status | |
Simulation time | 3019430783 ps |
CPU time | 49.25 seconds |
Started | Aug 12 04:22:16 PM PDT 24 |
Finished | Aug 12 04:23:16 PM PDT 24 |
Peak memory | 146076 kb |
Host | smart-fec6c823-5224-4f90-903f-795721150bfb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2410165563 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_prince_test.2410165563 |
Directory | /workspace/11.prim_prince_test/latest |
Test location | /workspace/coverage/default/110.prim_prince_test.1545143370 |
Short name | T170 |
Test name | |
Test status | |
Simulation time | 2676839345 ps |
CPU time | 45.76 seconds |
Started | Aug 12 04:24:35 PM PDT 24 |
Finished | Aug 12 04:25:31 PM PDT 24 |
Peak memory | 146620 kb |
Host | smart-271c35e9-215c-4304-a4d2-aabdbafe82c6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1545143370 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 110.prim_prince_test.1545143370 |
Directory | /workspace/110.prim_prince_test/latest |
Test location | /workspace/coverage/default/111.prim_prince_test.2505985269 |
Short name | T20 |
Test name | |
Test status | |
Simulation time | 3538813916 ps |
CPU time | 58.45 seconds |
Started | Aug 12 04:26:26 PM PDT 24 |
Finished | Aug 12 04:27:37 PM PDT 24 |
Peak memory | 146200 kb |
Host | smart-96c03867-2c7d-47cd-a2cd-c000a3325c3b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2505985269 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 111.prim_prince_test.2505985269 |
Directory | /workspace/111.prim_prince_test/latest |
Test location | /workspace/coverage/default/112.prim_prince_test.125543225 |
Short name | T80 |
Test name | |
Test status | |
Simulation time | 1358316585 ps |
CPU time | 22.71 seconds |
Started | Aug 12 04:26:26 PM PDT 24 |
Finished | Aug 12 04:26:54 PM PDT 24 |
Peak memory | 146144 kb |
Host | smart-77b9c943-e247-4c79-b06a-8f9a7819db3d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=125543225 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 112.prim_prince_test.125543225 |
Directory | /workspace/112.prim_prince_test/latest |
Test location | /workspace/coverage/default/113.prim_prince_test.3195966340 |
Short name | T305 |
Test name | |
Test status | |
Simulation time | 1932876843 ps |
CPU time | 32.65 seconds |
Started | Aug 12 04:23:30 PM PDT 24 |
Finished | Aug 12 04:24:10 PM PDT 24 |
Peak memory | 146604 kb |
Host | smart-f3478303-55cb-4d8e-b297-e3540f3f947f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3195966340 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 113.prim_prince_test.3195966340 |
Directory | /workspace/113.prim_prince_test/latest |
Test location | /workspace/coverage/default/114.prim_prince_test.1591971205 |
Short name | T186 |
Test name | |
Test status | |
Simulation time | 2444273813 ps |
CPU time | 41.36 seconds |
Started | Aug 12 04:23:29 PM PDT 24 |
Finished | Aug 12 04:24:19 PM PDT 24 |
Peak memory | 146628 kb |
Host | smart-75840e0c-d79c-481f-b8fe-0f1c09bc7bb9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1591971205 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 114.prim_prince_test.1591971205 |
Directory | /workspace/114.prim_prince_test/latest |
Test location | /workspace/coverage/default/115.prim_prince_test.3726149527 |
Short name | T325 |
Test name | |
Test status | |
Simulation time | 1478802416 ps |
CPU time | 24.3 seconds |
Started | Aug 12 04:26:32 PM PDT 24 |
Finished | Aug 12 04:27:01 PM PDT 24 |
Peak memory | 144912 kb |
Host | smart-e9b92443-641a-4cee-a32c-d0ef8cb68665 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3726149527 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 115.prim_prince_test.3726149527 |
Directory | /workspace/115.prim_prince_test/latest |
Test location | /workspace/coverage/default/117.prim_prince_test.1105832058 |
Short name | T252 |
Test name | |
Test status | |
Simulation time | 1538122815 ps |
CPU time | 27 seconds |
Started | Aug 12 04:24:56 PM PDT 24 |
Finished | Aug 12 04:25:30 PM PDT 24 |
Peak memory | 146604 kb |
Host | smart-8c51d719-322d-4731-b8c2-4964af46e10c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1105832058 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 117.prim_prince_test.1105832058 |
Directory | /workspace/117.prim_prince_test/latest |
Test location | /workspace/coverage/default/118.prim_prince_test.1790704651 |
Short name | T188 |
Test name | |
Test status | |
Simulation time | 1033555358 ps |
CPU time | 16.63 seconds |
Started | Aug 12 04:26:33 PM PDT 24 |
Finished | Aug 12 04:26:53 PM PDT 24 |
Peak memory | 146608 kb |
Host | smart-01b988aa-424c-4add-a86e-ba63dad192f7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1790704651 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 118.prim_prince_test.1790704651 |
Directory | /workspace/118.prim_prince_test/latest |
Test location | /workspace/coverage/default/119.prim_prince_test.981781256 |
Short name | T118 |
Test name | |
Test status | |
Simulation time | 2183589460 ps |
CPU time | 36.78 seconds |
Started | Aug 12 04:26:41 PM PDT 24 |
Finished | Aug 12 04:27:27 PM PDT 24 |
Peak memory | 146436 kb |
Host | smart-87838c75-9e50-43ab-a648-bd57ef57a016 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=981781256 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 119.prim_prince_test.981781256 |
Directory | /workspace/119.prim_prince_test/latest |
Test location | /workspace/coverage/default/12.prim_prince_test.272274017 |
Short name | T276 |
Test name | |
Test status | |
Simulation time | 2144329818 ps |
CPU time | 35.28 seconds |
Started | Aug 12 04:21:16 PM PDT 24 |
Finished | Aug 12 04:21:58 PM PDT 24 |
Peak memory | 146212 kb |
Host | smart-6cdaf00a-91ae-4313-a631-a8f0b552e7a7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=272274017 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_prince_test.272274017 |
Directory | /workspace/12.prim_prince_test/latest |
Test location | /workspace/coverage/default/120.prim_prince_test.606766401 |
Short name | T258 |
Test name | |
Test status | |
Simulation time | 2853604376 ps |
CPU time | 48.57 seconds |
Started | Aug 12 04:24:55 PM PDT 24 |
Finished | Aug 12 04:25:55 PM PDT 24 |
Peak memory | 146660 kb |
Host | smart-8eb5a638-531b-42bf-b5d6-80552f218aff |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=606766401 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 120.prim_prince_test.606766401 |
Directory | /workspace/120.prim_prince_test/latest |
Test location | /workspace/coverage/default/121.prim_prince_test.1644833646 |
Short name | T486 |
Test name | |
Test status | |
Simulation time | 3256977764 ps |
CPU time | 52.1 seconds |
Started | Aug 12 04:26:37 PM PDT 24 |
Finished | Aug 12 04:27:39 PM PDT 24 |
Peak memory | 146184 kb |
Host | smart-3e519212-f023-4ce2-aa30-e6af32a14981 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1644833646 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 121.prim_prince_test.1644833646 |
Directory | /workspace/121.prim_prince_test/latest |
Test location | /workspace/coverage/default/122.prim_prince_test.82739910 |
Short name | T41 |
Test name | |
Test status | |
Simulation time | 2380823972 ps |
CPU time | 38.69 seconds |
Started | Aug 12 04:26:32 PM PDT 24 |
Finished | Aug 12 04:27:18 PM PDT 24 |
Peak memory | 145144 kb |
Host | smart-f6cbf0b1-305d-4bc7-afaa-6abf2130cf70 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=82739910 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 122.prim_prince_test.82739910 |
Directory | /workspace/122.prim_prince_test/latest |
Test location | /workspace/coverage/default/123.prim_prince_test.78933739 |
Short name | T434 |
Test name | |
Test status | |
Simulation time | 907823266 ps |
CPU time | 14.72 seconds |
Started | Aug 12 04:26:38 PM PDT 24 |
Finished | Aug 12 04:26:56 PM PDT 24 |
Peak memory | 146120 kb |
Host | smart-f099e570-69bb-426c-90b2-02261953037c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=78933739 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 123.prim_prince_test.78933739 |
Directory | /workspace/123.prim_prince_test/latest |
Test location | /workspace/coverage/default/124.prim_prince_test.1494865517 |
Short name | T399 |
Test name | |
Test status | |
Simulation time | 1182758083 ps |
CPU time | 20.44 seconds |
Started | Aug 12 04:23:03 PM PDT 24 |
Finished | Aug 12 04:23:28 PM PDT 24 |
Peak memory | 146632 kb |
Host | smart-64c27dac-72d2-4b73-a2f7-22bef6701a3d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1494865517 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 124.prim_prince_test.1494865517 |
Directory | /workspace/124.prim_prince_test/latest |
Test location | /workspace/coverage/default/125.prim_prince_test.3016634867 |
Short name | T489 |
Test name | |
Test status | |
Simulation time | 2071644110 ps |
CPU time | 33.18 seconds |
Started | Aug 12 04:26:38 PM PDT 24 |
Finished | Aug 12 04:27:17 PM PDT 24 |
Peak memory | 146120 kb |
Host | smart-a2ccb5cd-cbd1-4ec1-983c-12ca567090dc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3016634867 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 125.prim_prince_test.3016634867 |
Directory | /workspace/125.prim_prince_test/latest |
Test location | /workspace/coverage/default/126.prim_prince_test.1224881226 |
Short name | T226 |
Test name | |
Test status | |
Simulation time | 2647819127 ps |
CPU time | 45.86 seconds |
Started | Aug 12 04:22:36 PM PDT 24 |
Finished | Aug 12 04:23:33 PM PDT 24 |
Peak memory | 146828 kb |
Host | smart-af45d196-ef53-4700-bc0a-6edf1ed23757 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1224881226 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 126.prim_prince_test.1224881226 |
Directory | /workspace/126.prim_prince_test/latest |
Test location | /workspace/coverage/default/127.prim_prince_test.331424213 |
Short name | T397 |
Test name | |
Test status | |
Simulation time | 1284928318 ps |
CPU time | 21.68 seconds |
Started | Aug 12 04:26:41 PM PDT 24 |
Finished | Aug 12 04:27:07 PM PDT 24 |
Peak memory | 146140 kb |
Host | smart-83812dbf-98f7-4a0a-a83b-dbe64bcf5fd7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=331424213 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 127.prim_prince_test.331424213 |
Directory | /workspace/127.prim_prince_test/latest |
Test location | /workspace/coverage/default/128.prim_prince_test.1673488305 |
Short name | T239 |
Test name | |
Test status | |
Simulation time | 2959115548 ps |
CPU time | 48.67 seconds |
Started | Aug 12 04:26:42 PM PDT 24 |
Finished | Aug 12 04:27:40 PM PDT 24 |
Peak memory | 146196 kb |
Host | smart-818b5cf4-e746-4797-b7c9-a67c33f0a8e0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1673488305 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 128.prim_prince_test.1673488305 |
Directory | /workspace/128.prim_prince_test/latest |
Test location | /workspace/coverage/default/129.prim_prince_test.3579733324 |
Short name | T237 |
Test name | |
Test status | |
Simulation time | 2582909760 ps |
CPU time | 43.9 seconds |
Started | Aug 12 04:24:55 PM PDT 24 |
Finished | Aug 12 04:25:50 PM PDT 24 |
Peak memory | 146684 kb |
Host | smart-9d50c3c9-fcf3-4909-bdcd-1c0c801e44fb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3579733324 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 129.prim_prince_test.3579733324 |
Directory | /workspace/129.prim_prince_test/latest |
Test location | /workspace/coverage/default/13.prim_prince_test.2559691589 |
Short name | T371 |
Test name | |
Test status | |
Simulation time | 1079137250 ps |
CPU time | 18.08 seconds |
Started | Aug 12 04:21:15 PM PDT 24 |
Finished | Aug 12 04:21:37 PM PDT 24 |
Peak memory | 145372 kb |
Host | smart-6a88aa2f-dbc0-4c39-944c-968c1208d20a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2559691589 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_prince_test.2559691589 |
Directory | /workspace/13.prim_prince_test/latest |
Test location | /workspace/coverage/default/130.prim_prince_test.1529566079 |
Short name | T181 |
Test name | |
Test status | |
Simulation time | 1809959089 ps |
CPU time | 30.86 seconds |
Started | Aug 12 04:23:29 PM PDT 24 |
Finished | Aug 12 04:24:07 PM PDT 24 |
Peak memory | 146632 kb |
Host | smart-a66c880d-b0a5-4a4f-aee8-047fc557e91b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1529566079 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 130.prim_prince_test.1529566079 |
Directory | /workspace/130.prim_prince_test/latest |
Test location | /workspace/coverage/default/131.prim_prince_test.1921337847 |
Short name | T437 |
Test name | |
Test status | |
Simulation time | 3434737513 ps |
CPU time | 54.71 seconds |
Started | Aug 12 04:26:51 PM PDT 24 |
Finished | Aug 12 04:27:56 PM PDT 24 |
Peak memory | 146348 kb |
Host | smart-bdcd4b42-5e1a-477e-b6af-39bfdf5f1e98 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1921337847 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 131.prim_prince_test.1921337847 |
Directory | /workspace/131.prim_prince_test/latest |
Test location | /workspace/coverage/default/132.prim_prince_test.1268939944 |
Short name | T265 |
Test name | |
Test status | |
Simulation time | 1056593634 ps |
CPU time | 18.67 seconds |
Started | Aug 12 04:22:01 PM PDT 24 |
Finished | Aug 12 04:22:24 PM PDT 24 |
Peak memory | 146620 kb |
Host | smart-c81af2cd-be83-49dd-881c-4a9ad1764b0c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1268939944 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 132.prim_prince_test.1268939944 |
Directory | /workspace/132.prim_prince_test/latest |
Test location | /workspace/coverage/default/133.prim_prince_test.3377707107 |
Short name | T433 |
Test name | |
Test status | |
Simulation time | 2454419777 ps |
CPU time | 40.03 seconds |
Started | Aug 12 04:26:42 PM PDT 24 |
Finished | Aug 12 04:27:29 PM PDT 24 |
Peak memory | 146196 kb |
Host | smart-674a8744-5066-4243-9766-8c6d5e851a0a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3377707107 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 133.prim_prince_test.3377707107 |
Directory | /workspace/133.prim_prince_test/latest |
Test location | /workspace/coverage/default/134.prim_prince_test.2867006104 |
Short name | T227 |
Test name | |
Test status | |
Simulation time | 1251392119 ps |
CPU time | 21.51 seconds |
Started | Aug 12 04:23:03 PM PDT 24 |
Finished | Aug 12 04:23:29 PM PDT 24 |
Peak memory | 146632 kb |
Host | smart-d37b920a-51d5-4e82-8a32-1ece027dadea |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2867006104 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 134.prim_prince_test.2867006104 |
Directory | /workspace/134.prim_prince_test/latest |
Test location | /workspace/coverage/default/135.prim_prince_test.4044978139 |
Short name | T238 |
Test name | |
Test status | |
Simulation time | 1027459815 ps |
CPU time | 17.05 seconds |
Started | Aug 12 04:26:51 PM PDT 24 |
Finished | Aug 12 04:27:12 PM PDT 24 |
Peak memory | 146408 kb |
Host | smart-8d58cbfd-05d4-496d-bfe3-315b84ce3f95 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4044978139 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 135.prim_prince_test.4044978139 |
Directory | /workspace/135.prim_prince_test/latest |
Test location | /workspace/coverage/default/136.prim_prince_test.2179543262 |
Short name | T324 |
Test name | |
Test status | |
Simulation time | 2398673687 ps |
CPU time | 38.74 seconds |
Started | Aug 12 04:26:50 PM PDT 24 |
Finished | Aug 12 04:27:36 PM PDT 24 |
Peak memory | 146348 kb |
Host | smart-4c7472d3-c8cd-495e-9bba-de3a6b9ce72e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2179543262 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 136.prim_prince_test.2179543262 |
Directory | /workspace/136.prim_prince_test/latest |
Test location | /workspace/coverage/default/137.prim_prince_test.2222571482 |
Short name | T141 |
Test name | |
Test status | |
Simulation time | 1898473429 ps |
CPU time | 31.21 seconds |
Started | Aug 12 04:26:51 PM PDT 24 |
Finished | Aug 12 04:27:28 PM PDT 24 |
Peak memory | 146408 kb |
Host | smart-e717e99c-d441-49c0-ad85-efdccb61b0b6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2222571482 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 137.prim_prince_test.2222571482 |
Directory | /workspace/137.prim_prince_test/latest |
Test location | /workspace/coverage/default/138.prim_prince_test.3281946543 |
Short name | T6 |
Test name | |
Test status | |
Simulation time | 3691986360 ps |
CPU time | 59.58 seconds |
Started | Aug 12 04:26:47 PM PDT 24 |
Finished | Aug 12 04:27:58 PM PDT 24 |
Peak memory | 146264 kb |
Host | smart-7965b718-6a4a-4ea3-9c05-5a3d7e21130b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3281946543 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 138.prim_prince_test.3281946543 |
Directory | /workspace/138.prim_prince_test/latest |
Test location | /workspace/coverage/default/139.prim_prince_test.1175527129 |
Short name | T53 |
Test name | |
Test status | |
Simulation time | 1456989310 ps |
CPU time | 24.6 seconds |
Started | Aug 12 04:26:42 PM PDT 24 |
Finished | Aug 12 04:27:11 PM PDT 24 |
Peak memory | 146132 kb |
Host | smart-fb2b47ce-b999-4f8a-b4e9-61a77570b7b4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1175527129 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 139.prim_prince_test.1175527129 |
Directory | /workspace/139.prim_prince_test/latest |
Test location | /workspace/coverage/default/14.prim_prince_test.1726970629 |
Short name | T431 |
Test name | |
Test status | |
Simulation time | 2673438586 ps |
CPU time | 44.65 seconds |
Started | Aug 12 04:21:17 PM PDT 24 |
Finished | Aug 12 04:22:11 PM PDT 24 |
Peak memory | 146188 kb |
Host | smart-abb40aae-0a1b-41b5-b876-94da297ccd13 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1726970629 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_prince_test.1726970629 |
Directory | /workspace/14.prim_prince_test/latest |
Test location | /workspace/coverage/default/140.prim_prince_test.3215598588 |
Short name | T51 |
Test name | |
Test status | |
Simulation time | 2824425143 ps |
CPU time | 44.61 seconds |
Started | Aug 12 04:26:50 PM PDT 24 |
Finished | Aug 12 04:27:42 PM PDT 24 |
Peak memory | 146272 kb |
Host | smart-5c5b2447-c7bf-4deb-8408-e3516b12b026 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3215598588 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 140.prim_prince_test.3215598588 |
Directory | /workspace/140.prim_prince_test/latest |
Test location | /workspace/coverage/default/141.prim_prince_test.2107405663 |
Short name | T290 |
Test name | |
Test status | |
Simulation time | 1885904094 ps |
CPU time | 31.71 seconds |
Started | Aug 12 04:26:41 PM PDT 24 |
Finished | Aug 12 04:27:20 PM PDT 24 |
Peak memory | 146228 kb |
Host | smart-6c811308-f6e8-4ad3-8960-5a918cc28901 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2107405663 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 141.prim_prince_test.2107405663 |
Directory | /workspace/141.prim_prince_test/latest |
Test location | /workspace/coverage/default/142.prim_prince_test.2623011419 |
Short name | T119 |
Test name | |
Test status | |
Simulation time | 1757337464 ps |
CPU time | 29.02 seconds |
Started | Aug 12 04:27:11 PM PDT 24 |
Finished | Aug 12 04:27:46 PM PDT 24 |
Peak memory | 146432 kb |
Host | smart-efade320-3f60-44bf-9b2a-5693d228496c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2623011419 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 142.prim_prince_test.2623011419 |
Directory | /workspace/142.prim_prince_test/latest |
Test location | /workspace/coverage/default/143.prim_prince_test.1291225879 |
Short name | T40 |
Test name | |
Test status | |
Simulation time | 1949254320 ps |
CPU time | 32.73 seconds |
Started | Aug 12 04:22:16 PM PDT 24 |
Finished | Aug 12 04:22:55 PM PDT 24 |
Peak memory | 146616 kb |
Host | smart-8aeeccbb-6ea4-4126-94a9-c0fcfea7a4f8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1291225879 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 143.prim_prince_test.1291225879 |
Directory | /workspace/143.prim_prince_test/latest |
Test location | /workspace/coverage/default/144.prim_prince_test.2998813660 |
Short name | T120 |
Test name | |
Test status | |
Simulation time | 3752300282 ps |
CPU time | 61.66 seconds |
Started | Aug 12 04:26:32 PM PDT 24 |
Finished | Aug 12 04:27:48 PM PDT 24 |
Peak memory | 144172 kb |
Host | smart-eb1825c4-89f4-467c-8749-5303f2489ee3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2998813660 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 144.prim_prince_test.2998813660 |
Directory | /workspace/144.prim_prince_test/latest |
Test location | /workspace/coverage/default/145.prim_prince_test.2135565285 |
Short name | T396 |
Test name | |
Test status | |
Simulation time | 2780558582 ps |
CPU time | 47.09 seconds |
Started | Aug 12 04:23:44 PM PDT 24 |
Finished | Aug 12 04:24:41 PM PDT 24 |
Peak memory | 146652 kb |
Host | smart-435e67d1-95f4-45fc-aa20-00efc2e49e21 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2135565285 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 145.prim_prince_test.2135565285 |
Directory | /workspace/145.prim_prince_test/latest |
Test location | /workspace/coverage/default/146.prim_prince_test.3585721996 |
Short name | T113 |
Test name | |
Test status | |
Simulation time | 1912710641 ps |
CPU time | 31.3 seconds |
Started | Aug 12 04:26:13 PM PDT 24 |
Finished | Aug 12 04:26:51 PM PDT 24 |
Peak memory | 143768 kb |
Host | smart-08491591-36ad-41d8-9729-4397a7740d30 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3585721996 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 146.prim_prince_test.3585721996 |
Directory | /workspace/146.prim_prince_test/latest |
Test location | /workspace/coverage/default/147.prim_prince_test.3886617514 |
Short name | T25 |
Test name | |
Test status | |
Simulation time | 2080730631 ps |
CPU time | 33.93 seconds |
Started | Aug 12 04:26:14 PM PDT 24 |
Finished | Aug 12 04:26:55 PM PDT 24 |
Peak memory | 146176 kb |
Host | smart-8bcfc29e-4991-474b-b84c-8d16faa0f829 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3886617514 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 147.prim_prince_test.3886617514 |
Directory | /workspace/147.prim_prince_test/latest |
Test location | /workspace/coverage/default/148.prim_prince_test.2324208975 |
Short name | T4 |
Test name | |
Test status | |
Simulation time | 1449159805 ps |
CPU time | 24.07 seconds |
Started | Aug 12 04:26:33 PM PDT 24 |
Finished | Aug 12 04:27:03 PM PDT 24 |
Peak memory | 146016 kb |
Host | smart-6d48b4b0-ef93-4197-af20-065f0321c101 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2324208975 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 148.prim_prince_test.2324208975 |
Directory | /workspace/148.prim_prince_test/latest |
Test location | /workspace/coverage/default/149.prim_prince_test.1528243177 |
Short name | T151 |
Test name | |
Test status | |
Simulation time | 1426209030 ps |
CPU time | 23.18 seconds |
Started | Aug 12 04:26:24 PM PDT 24 |
Finished | Aug 12 04:26:51 PM PDT 24 |
Peak memory | 146320 kb |
Host | smart-b920e00c-0c92-42d9-8aa2-adab0c175362 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1528243177 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 149.prim_prince_test.1528243177 |
Directory | /workspace/149.prim_prince_test/latest |
Test location | /workspace/coverage/default/15.prim_prince_test.568826603 |
Short name | T123 |
Test name | |
Test status | |
Simulation time | 845705040 ps |
CPU time | 14.28 seconds |
Started | Aug 12 04:21:17 PM PDT 24 |
Finished | Aug 12 04:21:35 PM PDT 24 |
Peak memory | 146160 kb |
Host | smart-fb46ccfb-3368-4179-bf5d-888e7ec70dba |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=568826603 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_prince_test.568826603 |
Directory | /workspace/15.prim_prince_test/latest |
Test location | /workspace/coverage/default/150.prim_prince_test.398146572 |
Short name | T108 |
Test name | |
Test status | |
Simulation time | 2808912679 ps |
CPU time | 46.45 seconds |
Started | Aug 12 04:26:13 PM PDT 24 |
Finished | Aug 12 04:27:09 PM PDT 24 |
Peak memory | 144788 kb |
Host | smart-bdf697fa-e71c-4f72-b880-e0b62fca5f09 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=398146572 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 150.prim_prince_test.398146572 |
Directory | /workspace/150.prim_prince_test/latest |
Test location | /workspace/coverage/default/151.prim_prince_test.506334755 |
Short name | T291 |
Test name | |
Test status | |
Simulation time | 2210290529 ps |
CPU time | 35.94 seconds |
Started | Aug 12 04:26:17 PM PDT 24 |
Finished | Aug 12 04:27:01 PM PDT 24 |
Peak memory | 146144 kb |
Host | smart-028abc41-ac4e-4333-b8cc-4e4fee4a0bda |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=506334755 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 151.prim_prince_test.506334755 |
Directory | /workspace/151.prim_prince_test/latest |
Test location | /workspace/coverage/default/152.prim_prince_test.298985161 |
Short name | T327 |
Test name | |
Test status | |
Simulation time | 2760239576 ps |
CPU time | 45.99 seconds |
Started | Aug 12 04:23:07 PM PDT 24 |
Finished | Aug 12 04:24:02 PM PDT 24 |
Peak memory | 146576 kb |
Host | smart-d804b511-e954-430d-87f9-d46aee4ba167 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=298985161 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 152.prim_prince_test.298985161 |
Directory | /workspace/152.prim_prince_test/latest |
Test location | /workspace/coverage/default/153.prim_prince_test.1255914708 |
Short name | T497 |
Test name | |
Test status | |
Simulation time | 2464186118 ps |
CPU time | 41.24 seconds |
Started | Aug 12 04:26:16 PM PDT 24 |
Finished | Aug 12 04:27:06 PM PDT 24 |
Peak memory | 144988 kb |
Host | smart-b9316cbe-a94e-49f6-9632-54b287d924d3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1255914708 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 153.prim_prince_test.1255914708 |
Directory | /workspace/153.prim_prince_test/latest |
Test location | /workspace/coverage/default/154.prim_prince_test.2601165827 |
Short name | T24 |
Test name | |
Test status | |
Simulation time | 3600987053 ps |
CPU time | 59.7 seconds |
Started | Aug 12 04:26:16 PM PDT 24 |
Finished | Aug 12 04:27:28 PM PDT 24 |
Peak memory | 144972 kb |
Host | smart-77673466-cd9f-45a5-aa92-526e947631ea |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2601165827 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 154.prim_prince_test.2601165827 |
Directory | /workspace/154.prim_prince_test/latest |
Test location | /workspace/coverage/default/155.prim_prince_test.43260253 |
Short name | T348 |
Test name | |
Test status | |
Simulation time | 2285998659 ps |
CPU time | 37.8 seconds |
Started | Aug 12 04:26:16 PM PDT 24 |
Finished | Aug 12 04:27:02 PM PDT 24 |
Peak memory | 144764 kb |
Host | smart-4e6d6bc0-7e1e-4304-a23a-71db91d72fd9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=43260253 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 155.prim_prince_test.43260253 |
Directory | /workspace/155.prim_prince_test/latest |
Test location | /workspace/coverage/default/156.prim_prince_test.1349636814 |
Short name | T194 |
Test name | |
Test status | |
Simulation time | 935433544 ps |
CPU time | 15.6 seconds |
Started | Aug 12 04:26:16 PM PDT 24 |
Finished | Aug 12 04:26:35 PM PDT 24 |
Peak memory | 144680 kb |
Host | smart-ec7917d5-08be-4008-b557-d9bdb6910cd0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1349636814 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 156.prim_prince_test.1349636814 |
Directory | /workspace/156.prim_prince_test/latest |
Test location | /workspace/coverage/default/157.prim_prince_test.604587133 |
Short name | T402 |
Test name | |
Test status | |
Simulation time | 3194801197 ps |
CPU time | 55.25 seconds |
Started | Aug 12 04:22:02 PM PDT 24 |
Finished | Aug 12 04:23:11 PM PDT 24 |
Peak memory | 146732 kb |
Host | smart-0ac292ea-62dd-42ff-9846-75063edb0397 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=604587133 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 157.prim_prince_test.604587133 |
Directory | /workspace/157.prim_prince_test/latest |
Test location | /workspace/coverage/default/158.prim_prince_test.2720112916 |
Short name | T403 |
Test name | |
Test status | |
Simulation time | 2386816253 ps |
CPU time | 40.02 seconds |
Started | Aug 12 04:24:38 PM PDT 24 |
Finished | Aug 12 04:25:27 PM PDT 24 |
Peak memory | 146664 kb |
Host | smart-de2150f5-8ee9-4ab9-824b-9a656160ce97 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2720112916 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 158.prim_prince_test.2720112916 |
Directory | /workspace/158.prim_prince_test/latest |
Test location | /workspace/coverage/default/159.prim_prince_test.3137918097 |
Short name | T405 |
Test name | |
Test status | |
Simulation time | 1954966876 ps |
CPU time | 33.35 seconds |
Started | Aug 12 04:22:35 PM PDT 24 |
Finished | Aug 12 04:23:16 PM PDT 24 |
Peak memory | 146664 kb |
Host | smart-c0c26a3c-2ecd-4cd4-9fb9-a67e23d9bc5e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3137918097 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 159.prim_prince_test.3137918097 |
Directory | /workspace/159.prim_prince_test/latest |
Test location | /workspace/coverage/default/16.prim_prince_test.3044393590 |
Short name | T180 |
Test name | |
Test status | |
Simulation time | 2370082768 ps |
CPU time | 40.88 seconds |
Started | Aug 12 04:21:14 PM PDT 24 |
Finished | Aug 12 04:22:05 PM PDT 24 |
Peak memory | 146676 kb |
Host | smart-b7e8f6b2-a71f-4f70-bd1d-30ecf2203f1a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3044393590 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_prince_test.3044393590 |
Directory | /workspace/16.prim_prince_test/latest |
Test location | /workspace/coverage/default/160.prim_prince_test.1248128754 |
Short name | T422 |
Test name | |
Test status | |
Simulation time | 3086045424 ps |
CPU time | 50.35 seconds |
Started | Aug 12 04:26:27 PM PDT 24 |
Finished | Aug 12 04:27:28 PM PDT 24 |
Peak memory | 145152 kb |
Host | smart-2888f708-9aa9-4e5a-ae2b-eb300a729819 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1248128754 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 160.prim_prince_test.1248128754 |
Directory | /workspace/160.prim_prince_test/latest |
Test location | /workspace/coverage/default/161.prim_prince_test.677522600 |
Short name | T106 |
Test name | |
Test status | |
Simulation time | 2232680958 ps |
CPU time | 36.45 seconds |
Started | Aug 12 04:23:06 PM PDT 24 |
Finished | Aug 12 04:23:49 PM PDT 24 |
Peak memory | 146576 kb |
Host | smart-bfa49969-1eb4-4ef9-90d2-48455edb9972 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=677522600 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 161.prim_prince_test.677522600 |
Directory | /workspace/161.prim_prince_test/latest |
Test location | /workspace/coverage/default/162.prim_prince_test.2334951384 |
Short name | T458 |
Test name | |
Test status | |
Simulation time | 1204983645 ps |
CPU time | 19.68 seconds |
Started | Aug 12 04:23:06 PM PDT 24 |
Finished | Aug 12 04:23:29 PM PDT 24 |
Peak memory | 146508 kb |
Host | smart-52befcca-a72c-436a-832b-0f63fbdcd758 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2334951384 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 162.prim_prince_test.2334951384 |
Directory | /workspace/162.prim_prince_test/latest |
Test location | /workspace/coverage/default/163.prim_prince_test.1966584205 |
Short name | T334 |
Test name | |
Test status | |
Simulation time | 3677088273 ps |
CPU time | 59.58 seconds |
Started | Aug 12 04:26:16 PM PDT 24 |
Finished | Aug 12 04:27:28 PM PDT 24 |
Peak memory | 146256 kb |
Host | smart-013755db-bb1b-4c7d-b451-d3487362942b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1966584205 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 163.prim_prince_test.1966584205 |
Directory | /workspace/163.prim_prince_test/latest |
Test location | /workspace/coverage/default/164.prim_prince_test.43532861 |
Short name | T285 |
Test name | |
Test status | |
Simulation time | 2496689423 ps |
CPU time | 41.63 seconds |
Started | Aug 12 04:24:05 PM PDT 24 |
Finished | Aug 12 04:24:55 PM PDT 24 |
Peak memory | 146568 kb |
Host | smart-0b7b4665-e35b-4487-be8c-606c43c0026d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=43532861 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 164.prim_prince_test.43532861 |
Directory | /workspace/164.prim_prince_test/latest |
Test location | /workspace/coverage/default/165.prim_prince_test.3896942193 |
Short name | T9 |
Test name | |
Test status | |
Simulation time | 1908071125 ps |
CPU time | 31.47 seconds |
Started | Aug 12 04:26:30 PM PDT 24 |
Finished | Aug 12 04:27:08 PM PDT 24 |
Peak memory | 146288 kb |
Host | smart-6d438e26-2a7b-458c-8176-64ceba5cf8b9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3896942193 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 165.prim_prince_test.3896942193 |
Directory | /workspace/165.prim_prince_test/latest |
Test location | /workspace/coverage/default/166.prim_prince_test.2930296633 |
Short name | T472 |
Test name | |
Test status | |
Simulation time | 811906156 ps |
CPU time | 13.46 seconds |
Started | Aug 12 04:26:23 PM PDT 24 |
Finished | Aug 12 04:26:39 PM PDT 24 |
Peak memory | 146320 kb |
Host | smart-453ec480-e79f-4f9c-80e6-7c024ddfc0a2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2930296633 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 166.prim_prince_test.2930296633 |
Directory | /workspace/166.prim_prince_test/latest |
Test location | /workspace/coverage/default/167.prim_prince_test.4233140790 |
Short name | T274 |
Test name | |
Test status | |
Simulation time | 1275946945 ps |
CPU time | 21.25 seconds |
Started | Aug 12 04:26:17 PM PDT 24 |
Finished | Aug 12 04:26:43 PM PDT 24 |
Peak memory | 144224 kb |
Host | smart-80b6e2d5-b9fd-4d5c-9a05-3de03aa7dc10 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4233140790 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 167.prim_prince_test.4233140790 |
Directory | /workspace/167.prim_prince_test/latest |
Test location | /workspace/coverage/default/168.prim_prince_test.893248270 |
Short name | T157 |
Test name | |
Test status | |
Simulation time | 3038052925 ps |
CPU time | 50.5 seconds |
Started | Aug 12 04:26:27 PM PDT 24 |
Finished | Aug 12 04:27:28 PM PDT 24 |
Peak memory | 146408 kb |
Host | smart-9e149d47-2ccd-4367-b5a7-71c331d261d0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=893248270 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 168.prim_prince_test.893248270 |
Directory | /workspace/168.prim_prince_test/latest |
Test location | /workspace/coverage/default/169.prim_prince_test.923740771 |
Short name | T189 |
Test name | |
Test status | |
Simulation time | 1746986378 ps |
CPU time | 28.8 seconds |
Started | Aug 12 04:26:28 PM PDT 24 |
Finished | Aug 12 04:27:03 PM PDT 24 |
Peak memory | 146292 kb |
Host | smart-54f70263-35de-4480-9d26-beb441df758f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=923740771 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 169.prim_prince_test.923740771 |
Directory | /workspace/169.prim_prince_test/latest |
Test location | /workspace/coverage/default/17.prim_prince_test.120657529 |
Short name | T60 |
Test name | |
Test status | |
Simulation time | 3189195039 ps |
CPU time | 53.24 seconds |
Started | Aug 12 04:22:24 PM PDT 24 |
Finished | Aug 12 04:23:28 PM PDT 24 |
Peak memory | 146184 kb |
Host | smart-1f9a9e4d-a50a-42f5-8947-02c9c21657f5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=120657529 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_prince_test.120657529 |
Directory | /workspace/17.prim_prince_test/latest |
Test location | /workspace/coverage/default/170.prim_prince_test.3047590358 |
Short name | T415 |
Test name | |
Test status | |
Simulation time | 1258628901 ps |
CPU time | 20.75 seconds |
Started | Aug 12 04:26:17 PM PDT 24 |
Finished | Aug 12 04:26:43 PM PDT 24 |
Peak memory | 146000 kb |
Host | smart-9f2e39d1-deb9-4a86-abeb-083249565a76 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3047590358 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 170.prim_prince_test.3047590358 |
Directory | /workspace/170.prim_prince_test/latest |
Test location | /workspace/coverage/default/171.prim_prince_test.1710637660 |
Short name | T98 |
Test name | |
Test status | |
Simulation time | 1309103675 ps |
CPU time | 21.52 seconds |
Started | Aug 12 04:26:27 PM PDT 24 |
Finished | Aug 12 04:26:53 PM PDT 24 |
Peak memory | 146288 kb |
Host | smart-ebe1e3e5-018b-4d44-ac1c-4e87d803ca3b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1710637660 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 171.prim_prince_test.1710637660 |
Directory | /workspace/171.prim_prince_test/latest |
Test location | /workspace/coverage/default/172.prim_prince_test.17995616 |
Short name | T412 |
Test name | |
Test status | |
Simulation time | 1234962982 ps |
CPU time | 20.37 seconds |
Started | Aug 12 04:26:17 PM PDT 24 |
Finished | Aug 12 04:26:42 PM PDT 24 |
Peak memory | 144520 kb |
Host | smart-42406c90-cecd-42be-bfa8-e99ebf2d4343 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=17995616 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 172.prim_prince_test.17995616 |
Directory | /workspace/172.prim_prince_test/latest |
Test location | /workspace/coverage/default/173.prim_prince_test.3493717308 |
Short name | T326 |
Test name | |
Test status | |
Simulation time | 1984244865 ps |
CPU time | 32.68 seconds |
Started | Aug 12 04:26:16 PM PDT 24 |
Finished | Aug 12 04:26:56 PM PDT 24 |
Peak memory | 146176 kb |
Host | smart-06df620b-0e98-4e30-adbc-bd354641edd3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3493717308 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 173.prim_prince_test.3493717308 |
Directory | /workspace/173.prim_prince_test/latest |
Test location | /workspace/coverage/default/174.prim_prince_test.3244964220 |
Short name | T491 |
Test name | |
Test status | |
Simulation time | 1558038583 ps |
CPU time | 25.82 seconds |
Started | Aug 12 04:26:17 PM PDT 24 |
Finished | Aug 12 04:26:48 PM PDT 24 |
Peak memory | 144352 kb |
Host | smart-bd6a25ce-98b1-40fa-9d2d-9d8ff64b2743 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3244964220 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 174.prim_prince_test.3244964220 |
Directory | /workspace/174.prim_prince_test/latest |
Test location | /workspace/coverage/default/175.prim_prince_test.75210673 |
Short name | T416 |
Test name | |
Test status | |
Simulation time | 1964727430 ps |
CPU time | 34.36 seconds |
Started | Aug 12 04:22:07 PM PDT 24 |
Finished | Aug 12 04:22:50 PM PDT 24 |
Peak memory | 145588 kb |
Host | smart-ea3af92e-146c-4baf-8987-cbda97f56eda |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=75210673 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 175.prim_prince_test.75210673 |
Directory | /workspace/175.prim_prince_test/latest |
Test location | /workspace/coverage/default/176.prim_prince_test.2688995526 |
Short name | T240 |
Test name | |
Test status | |
Simulation time | 2545563745 ps |
CPU time | 42.3 seconds |
Started | Aug 12 04:26:17 PM PDT 24 |
Finished | Aug 12 04:27:08 PM PDT 24 |
Peak memory | 144580 kb |
Host | smart-79c95f8f-0754-438d-a3ab-5e4d2b5099ff |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2688995526 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 176.prim_prince_test.2688995526 |
Directory | /workspace/176.prim_prince_test/latest |
Test location | /workspace/coverage/default/177.prim_prince_test.3062814751 |
Short name | T261 |
Test name | |
Test status | |
Simulation time | 1260347826 ps |
CPU time | 21.71 seconds |
Started | Aug 12 04:23:46 PM PDT 24 |
Finished | Aug 12 04:24:13 PM PDT 24 |
Peak memory | 146664 kb |
Host | smart-cb14a6d0-c66e-4919-a57e-2ab3d1228b39 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3062814751 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 177.prim_prince_test.3062814751 |
Directory | /workspace/177.prim_prince_test/latest |
Test location | /workspace/coverage/default/178.prim_prince_test.611257433 |
Short name | T8 |
Test name | |
Test status | |
Simulation time | 1731971440 ps |
CPU time | 28.38 seconds |
Started | Aug 12 04:26:17 PM PDT 24 |
Finished | Aug 12 04:26:51 PM PDT 24 |
Peak memory | 144536 kb |
Host | smart-93c8a338-f229-4338-95ce-6a068d8135b3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=611257433 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 178.prim_prince_test.611257433 |
Directory | /workspace/178.prim_prince_test/latest |
Test location | /workspace/coverage/default/179.prim_prince_test.3306737760 |
Short name | T110 |
Test name | |
Test status | |
Simulation time | 3646026972 ps |
CPU time | 61.02 seconds |
Started | Aug 12 04:21:58 PM PDT 24 |
Finished | Aug 12 04:23:13 PM PDT 24 |
Peak memory | 146708 kb |
Host | smart-7bebc677-1dd8-406c-82ab-2c9f097beb74 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3306737760 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 179.prim_prince_test.3306737760 |
Directory | /workspace/179.prim_prince_test/latest |
Test location | /workspace/coverage/default/18.prim_prince_test.1923170821 |
Short name | T166 |
Test name | |
Test status | |
Simulation time | 2549948641 ps |
CPU time | 42.07 seconds |
Started | Aug 12 04:21:16 PM PDT 24 |
Finished | Aug 12 04:22:06 PM PDT 24 |
Peak memory | 146332 kb |
Host | smart-2321debb-dbce-4602-9e3f-133a550d1467 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1923170821 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_prince_test.1923170821 |
Directory | /workspace/18.prim_prince_test/latest |
Test location | /workspace/coverage/default/180.prim_prince_test.3583668880 |
Short name | T381 |
Test name | |
Test status | |
Simulation time | 1089674697 ps |
CPU time | 19.15 seconds |
Started | Aug 12 04:24:12 PM PDT 24 |
Finished | Aug 12 04:24:35 PM PDT 24 |
Peak memory | 146656 kb |
Host | smart-561453be-93c1-4c10-a424-62774f81bb1b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3583668880 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 180.prim_prince_test.3583668880 |
Directory | /workspace/180.prim_prince_test/latest |
Test location | /workspace/coverage/default/181.prim_prince_test.378884948 |
Short name | T250 |
Test name | |
Test status | |
Simulation time | 869917851 ps |
CPU time | 14.29 seconds |
Started | Aug 12 04:25:47 PM PDT 24 |
Finished | Aug 12 04:26:05 PM PDT 24 |
Peak memory | 144468 kb |
Host | smart-39a4bc14-66c8-4a13-84b4-e043d5ade1d7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=378884948 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 181.prim_prince_test.378884948 |
Directory | /workspace/181.prim_prince_test/latest |
Test location | /workspace/coverage/default/182.prim_prince_test.762741319 |
Short name | T100 |
Test name | |
Test status | |
Simulation time | 1712663387 ps |
CPU time | 29.88 seconds |
Started | Aug 12 04:25:12 PM PDT 24 |
Finished | Aug 12 04:25:49 PM PDT 24 |
Peak memory | 146660 kb |
Host | smart-c07a94f1-4282-4f35-81b6-2e17eae6e2ae |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=762741319 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 182.prim_prince_test.762741319 |
Directory | /workspace/182.prim_prince_test/latest |
Test location | /workspace/coverage/default/183.prim_prince_test.1024673987 |
Short name | T168 |
Test name | |
Test status | |
Simulation time | 2261214012 ps |
CPU time | 37.8 seconds |
Started | Aug 12 04:24:11 PM PDT 24 |
Finished | Aug 12 04:24:57 PM PDT 24 |
Peak memory | 146660 kb |
Host | smart-07c04893-cf2f-4c5e-80d8-44e009150bed |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1024673987 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 183.prim_prince_test.1024673987 |
Directory | /workspace/183.prim_prince_test/latest |
Test location | /workspace/coverage/default/184.prim_prince_test.1866807115 |
Short name | T179 |
Test name | |
Test status | |
Simulation time | 1369507846 ps |
CPU time | 24.51 seconds |
Started | Aug 12 04:22:44 PM PDT 24 |
Finished | Aug 12 04:23:15 PM PDT 24 |
Peak memory | 146616 kb |
Host | smart-1f2087f2-edd5-4f68-9889-21eab7ea9776 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1866807115 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 184.prim_prince_test.1866807115 |
Directory | /workspace/184.prim_prince_test/latest |
Test location | /workspace/coverage/default/185.prim_prince_test.3094267650 |
Short name | T267 |
Test name | |
Test status | |
Simulation time | 2502790725 ps |
CPU time | 40.57 seconds |
Started | Aug 12 04:26:14 PM PDT 24 |
Finished | Aug 12 04:27:03 PM PDT 24 |
Peak memory | 146240 kb |
Host | smart-04e799d9-0c9f-41cd-b312-206337e2e6ba |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3094267650 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 185.prim_prince_test.3094267650 |
Directory | /workspace/185.prim_prince_test/latest |
Test location | /workspace/coverage/default/186.prim_prince_test.3887666393 |
Short name | T145 |
Test name | |
Test status | |
Simulation time | 857907490 ps |
CPU time | 14.28 seconds |
Started | Aug 12 04:26:13 PM PDT 24 |
Finished | Aug 12 04:26:31 PM PDT 24 |
Peak memory | 143860 kb |
Host | smart-d823fdaa-055d-45bb-aaea-08b7d0b59926 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3887666393 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 186.prim_prince_test.3887666393 |
Directory | /workspace/186.prim_prince_test/latest |
Test location | /workspace/coverage/default/187.prim_prince_test.3702433551 |
Short name | T231 |
Test name | |
Test status | |
Simulation time | 985914359 ps |
CPU time | 17.18 seconds |
Started | Aug 12 04:23:11 PM PDT 24 |
Finished | Aug 12 04:23:33 PM PDT 24 |
Peak memory | 146656 kb |
Host | smart-d8bf00de-ace0-473f-a53b-bd1ee0f1409c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3702433551 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 187.prim_prince_test.3702433551 |
Directory | /workspace/187.prim_prince_test/latest |
Test location | /workspace/coverage/default/188.prim_prince_test.3382481888 |
Short name | T333 |
Test name | |
Test status | |
Simulation time | 2148861539 ps |
CPU time | 35.22 seconds |
Started | Aug 12 04:26:16 PM PDT 24 |
Finished | Aug 12 04:26:59 PM PDT 24 |
Peak memory | 146228 kb |
Host | smart-7788775b-39cc-4db2-9924-e54a0355263b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3382481888 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 188.prim_prince_test.3382481888 |
Directory | /workspace/188.prim_prince_test/latest |
Test location | /workspace/coverage/default/189.prim_prince_test.2586116809 |
Short name | T383 |
Test name | |
Test status | |
Simulation time | 2131865234 ps |
CPU time | 34.87 seconds |
Started | Aug 12 04:25:47 PM PDT 24 |
Finished | Aug 12 04:26:30 PM PDT 24 |
Peak memory | 144716 kb |
Host | smart-0ec75013-07a2-4415-8a4c-a0eb83c9d51f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2586116809 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 189.prim_prince_test.2586116809 |
Directory | /workspace/189.prim_prince_test/latest |
Test location | /workspace/coverage/default/19.prim_prince_test.451074820 |
Short name | T26 |
Test name | |
Test status | |
Simulation time | 2301403119 ps |
CPU time | 39.37 seconds |
Started | Aug 12 04:21:14 PM PDT 24 |
Finished | Aug 12 04:22:04 PM PDT 24 |
Peak memory | 146676 kb |
Host | smart-f3e1e338-208f-437d-83cf-b77874a0843e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=451074820 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_prince_test.451074820 |
Directory | /workspace/19.prim_prince_test/latest |
Test location | /workspace/coverage/default/190.prim_prince_test.700020284 |
Short name | T217 |
Test name | |
Test status | |
Simulation time | 1245144083 ps |
CPU time | 20.88 seconds |
Started | Aug 12 04:26:31 PM PDT 24 |
Finished | Aug 12 04:26:57 PM PDT 24 |
Peak memory | 144100 kb |
Host | smart-025fb94b-58d4-475d-8b99-6c7c9216db82 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=700020284 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 190.prim_prince_test.700020284 |
Directory | /workspace/190.prim_prince_test/latest |
Test location | /workspace/coverage/default/191.prim_prince_test.118910477 |
Short name | T62 |
Test name | |
Test status | |
Simulation time | 2477809225 ps |
CPU time | 40.42 seconds |
Started | Aug 12 04:26:32 PM PDT 24 |
Finished | Aug 12 04:27:21 PM PDT 24 |
Peak memory | 145852 kb |
Host | smart-3bb3fa3c-6800-4cd8-ab23-6576e26ed6ee |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=118910477 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 191.prim_prince_test.118910477 |
Directory | /workspace/191.prim_prince_test/latest |
Test location | /workspace/coverage/default/192.prim_prince_test.2161714742 |
Short name | T10 |
Test name | |
Test status | |
Simulation time | 2109723513 ps |
CPU time | 33.94 seconds |
Started | Aug 12 04:26:39 PM PDT 24 |
Finished | Aug 12 04:27:20 PM PDT 24 |
Peak memory | 146120 kb |
Host | smart-ab4ccf55-34ac-4444-960a-99a2e8cda48e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2161714742 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 192.prim_prince_test.2161714742 |
Directory | /workspace/192.prim_prince_test/latest |
Test location | /workspace/coverage/default/193.prim_prince_test.3375769720 |
Short name | T29 |
Test name | |
Test status | |
Simulation time | 2266290768 ps |
CPU time | 36.49 seconds |
Started | Aug 12 04:26:39 PM PDT 24 |
Finished | Aug 12 04:27:23 PM PDT 24 |
Peak memory | 146184 kb |
Host | smart-07879efd-dbab-435f-b410-7f9f1c5e5055 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3375769720 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 193.prim_prince_test.3375769720 |
Directory | /workspace/193.prim_prince_test/latest |
Test location | /workspace/coverage/default/194.prim_prince_test.2584832792 |
Short name | T50 |
Test name | |
Test status | |
Simulation time | 2197939325 ps |
CPU time | 37.94 seconds |
Started | Aug 12 04:22:20 PM PDT 24 |
Finished | Aug 12 04:23:07 PM PDT 24 |
Peak memory | 146728 kb |
Host | smart-0c0157e6-3d33-4cdc-9d4c-95f01b0a3c26 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2584832792 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 194.prim_prince_test.2584832792 |
Directory | /workspace/194.prim_prince_test/latest |
Test location | /workspace/coverage/default/195.prim_prince_test.834576303 |
Short name | T361 |
Test name | |
Test status | |
Simulation time | 3013717206 ps |
CPU time | 52.06 seconds |
Started | Aug 12 04:22:28 PM PDT 24 |
Finished | Aug 12 04:23:33 PM PDT 24 |
Peak memory | 146652 kb |
Host | smart-e6d737a4-b5bc-4104-a139-f5c3d40c8c30 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=834576303 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 195.prim_prince_test.834576303 |
Directory | /workspace/195.prim_prince_test/latest |
Test location | /workspace/coverage/default/196.prim_prince_test.1234894191 |
Short name | T439 |
Test name | |
Test status | |
Simulation time | 1536272599 ps |
CPU time | 25.18 seconds |
Started | Aug 12 04:26:33 PM PDT 24 |
Finished | Aug 12 04:27:04 PM PDT 24 |
Peak memory | 146016 kb |
Host | smart-8f42f662-fe23-488a-9861-c90740591a8b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1234894191 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 196.prim_prince_test.1234894191 |
Directory | /workspace/196.prim_prince_test/latest |
Test location | /workspace/coverage/default/197.prim_prince_test.1024321651 |
Short name | T167 |
Test name | |
Test status | |
Simulation time | 3509943764 ps |
CPU time | 58.01 seconds |
Started | Aug 12 04:26:32 PM PDT 24 |
Finished | Aug 12 04:27:43 PM PDT 24 |
Peak memory | 144012 kb |
Host | smart-174cd99c-d6a7-4648-b536-d326bfba2964 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1024321651 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 197.prim_prince_test.1024321651 |
Directory | /workspace/197.prim_prince_test/latest |
Test location | /workspace/coverage/default/198.prim_prince_test.2096249997 |
Short name | T463 |
Test name | |
Test status | |
Simulation time | 2652371421 ps |
CPU time | 42.61 seconds |
Started | Aug 12 04:25:45 PM PDT 24 |
Finished | Aug 12 04:26:36 PM PDT 24 |
Peak memory | 144792 kb |
Host | smart-185c845a-1de1-4617-b872-e3529f101a16 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2096249997 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 198.prim_prince_test.2096249997 |
Directory | /workspace/198.prim_prince_test/latest |
Test location | /workspace/coverage/default/199.prim_prince_test.3472086587 |
Short name | T208 |
Test name | |
Test status | |
Simulation time | 1381578092 ps |
CPU time | 22.03 seconds |
Started | Aug 12 04:25:47 PM PDT 24 |
Finished | Aug 12 04:26:14 PM PDT 24 |
Peak memory | 144684 kb |
Host | smart-874df417-5a2c-47fe-837b-94eab156b384 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3472086587 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 199.prim_prince_test.3472086587 |
Directory | /workspace/199.prim_prince_test/latest |
Test location | /workspace/coverage/default/2.prim_prince_test.3966869254 |
Short name | T441 |
Test name | |
Test status | |
Simulation time | 2999490142 ps |
CPU time | 50.66 seconds |
Started | Aug 12 04:21:10 PM PDT 24 |
Finished | Aug 12 04:22:12 PM PDT 24 |
Peak memory | 144828 kb |
Host | smart-33061400-b2ca-4965-bc70-c7cce61a4593 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3966869254 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_prince_test.3966869254 |
Directory | /workspace/2.prim_prince_test/latest |
Test location | /workspace/coverage/default/20.prim_prince_test.3146270840 |
Short name | T418 |
Test name | |
Test status | |
Simulation time | 2562673163 ps |
CPU time | 42.48 seconds |
Started | Aug 12 04:21:17 PM PDT 24 |
Finished | Aug 12 04:22:08 PM PDT 24 |
Peak memory | 146144 kb |
Host | smart-db8e4d76-486f-4f81-9d72-97c907ff4568 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3146270840 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_prince_test.3146270840 |
Directory | /workspace/20.prim_prince_test/latest |
Test location | /workspace/coverage/default/200.prim_prince_test.445561167 |
Short name | T201 |
Test name | |
Test status | |
Simulation time | 1540171598 ps |
CPU time | 26.42 seconds |
Started | Aug 12 04:22:21 PM PDT 24 |
Finished | Aug 12 04:22:53 PM PDT 24 |
Peak memory | 146616 kb |
Host | smart-335095a4-7504-45d7-83fd-ca5db41d0f63 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=445561167 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 200.prim_prince_test.445561167 |
Directory | /workspace/200.prim_prince_test/latest |
Test location | /workspace/coverage/default/201.prim_prince_test.1849354613 |
Short name | T438 |
Test name | |
Test status | |
Simulation time | 2529383970 ps |
CPU time | 40.55 seconds |
Started | Aug 12 04:25:45 PM PDT 24 |
Finished | Aug 12 04:26:34 PM PDT 24 |
Peak memory | 144736 kb |
Host | smart-fc7b17cd-7b3d-4f13-b8d1-17b2cb02426e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1849354613 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 201.prim_prince_test.1849354613 |
Directory | /workspace/201.prim_prince_test/latest |
Test location | /workspace/coverage/default/202.prim_prince_test.4119953547 |
Short name | T129 |
Test name | |
Test status | |
Simulation time | 1736593614 ps |
CPU time | 28.61 seconds |
Started | Aug 12 04:26:57 PM PDT 24 |
Finished | Aug 12 04:27:32 PM PDT 24 |
Peak memory | 146576 kb |
Host | smart-c14e3aeb-7b06-4f7b-87a3-0f1fe165e36c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4119953547 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 202.prim_prince_test.4119953547 |
Directory | /workspace/202.prim_prince_test/latest |
Test location | /workspace/coverage/default/203.prim_prince_test.1215431106 |
Short name | T427 |
Test name | |
Test status | |
Simulation time | 3563577352 ps |
CPU time | 61.14 seconds |
Started | Aug 12 04:25:32 PM PDT 24 |
Finished | Aug 12 04:26:47 PM PDT 24 |
Peak memory | 146652 kb |
Host | smart-edb32f4d-a746-4050-9759-2813b2cf0082 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1215431106 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 203.prim_prince_test.1215431106 |
Directory | /workspace/203.prim_prince_test/latest |
Test location | /workspace/coverage/default/204.prim_prince_test.3596644328 |
Short name | T379 |
Test name | |
Test status | |
Simulation time | 2761542609 ps |
CPU time | 46.08 seconds |
Started | Aug 12 04:26:15 PM PDT 24 |
Finished | Aug 12 04:27:11 PM PDT 24 |
Peak memory | 146620 kb |
Host | smart-0ee8669c-2ffc-4ea5-91f3-71fc89c8eaef |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3596644328 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 204.prim_prince_test.3596644328 |
Directory | /workspace/204.prim_prince_test/latest |
Test location | /workspace/coverage/default/205.prim_prince_test.487551856 |
Short name | T107 |
Test name | |
Test status | |
Simulation time | 2823474798 ps |
CPU time | 46.61 seconds |
Started | Aug 12 04:27:09 PM PDT 24 |
Finished | Aug 12 04:28:04 PM PDT 24 |
Peak memory | 146652 kb |
Host | smart-613fe0f9-660e-40c0-89f4-3efe10d8cdcc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=487551856 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 205.prim_prince_test.487551856 |
Directory | /workspace/205.prim_prince_test/latest |
Test location | /workspace/coverage/default/206.prim_prince_test.3355446748 |
Short name | T70 |
Test name | |
Test status | |
Simulation time | 1718310174 ps |
CPU time | 28.58 seconds |
Started | Aug 12 04:23:39 PM PDT 24 |
Finished | Aug 12 04:24:14 PM PDT 24 |
Peak memory | 146604 kb |
Host | smart-b7be67b9-a815-438a-a4c2-98c393a973d2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3355446748 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 206.prim_prince_test.3355446748 |
Directory | /workspace/206.prim_prince_test/latest |
Test location | /workspace/coverage/default/207.prim_prince_test.1427846814 |
Short name | T340 |
Test name | |
Test status | |
Simulation time | 928599870 ps |
CPU time | 16.2 seconds |
Started | Aug 12 04:23:38 PM PDT 24 |
Finished | Aug 12 04:23:58 PM PDT 24 |
Peak memory | 146588 kb |
Host | smart-ddf1c2a9-87b8-4f8a-9d70-bdd96d9de514 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1427846814 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 207.prim_prince_test.1427846814 |
Directory | /workspace/207.prim_prince_test/latest |
Test location | /workspace/coverage/default/208.prim_prince_test.3744563757 |
Short name | T306 |
Test name | |
Test status | |
Simulation time | 3218637345 ps |
CPU time | 54.67 seconds |
Started | Aug 12 04:23:25 PM PDT 24 |
Finished | Aug 12 04:24:32 PM PDT 24 |
Peak memory | 146828 kb |
Host | smart-29fcc13c-3647-426d-9e92-10d12b772c55 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3744563757 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 208.prim_prince_test.3744563757 |
Directory | /workspace/208.prim_prince_test/latest |
Test location | /workspace/coverage/default/209.prim_prince_test.2048038755 |
Short name | T27 |
Test name | |
Test status | |
Simulation time | 2225879571 ps |
CPU time | 35.87 seconds |
Started | Aug 12 04:27:50 PM PDT 24 |
Finished | Aug 12 04:28:37 PM PDT 24 |
Peak memory | 146628 kb |
Host | smart-1013adca-3cae-425d-a8e2-25f55b7c100e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2048038755 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 209.prim_prince_test.2048038755 |
Directory | /workspace/209.prim_prince_test/latest |
Test location | /workspace/coverage/default/21.prim_prince_test.2940867806 |
Short name | T204 |
Test name | |
Test status | |
Simulation time | 1610393735 ps |
CPU time | 26.99 seconds |
Started | Aug 12 04:22:16 PM PDT 24 |
Finished | Aug 12 04:22:49 PM PDT 24 |
Peak memory | 143928 kb |
Host | smart-cb070295-92bb-42be-bf0a-cb8cfe0c896d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2940867806 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_prince_test.2940867806 |
Directory | /workspace/21.prim_prince_test/latest |
Test location | /workspace/coverage/default/210.prim_prince_test.3387063725 |
Short name | T253 |
Test name | |
Test status | |
Simulation time | 3020461729 ps |
CPU time | 51.74 seconds |
Started | Aug 12 04:23:46 PM PDT 24 |
Finished | Aug 12 04:24:50 PM PDT 24 |
Peak memory | 146652 kb |
Host | smart-801bacb6-85ef-42e4-9e53-7b2792c43766 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3387063725 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 210.prim_prince_test.3387063725 |
Directory | /workspace/210.prim_prince_test/latest |
Test location | /workspace/coverage/default/211.prim_prince_test.918340695 |
Short name | T202 |
Test name | |
Test status | |
Simulation time | 2101850689 ps |
CPU time | 34.74 seconds |
Started | Aug 12 04:27:12 PM PDT 24 |
Finished | Aug 12 04:27:54 PM PDT 24 |
Peak memory | 146572 kb |
Host | smart-b9ccf6fe-9bc6-4a0f-a8be-ced61e5cb7be |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=918340695 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 211.prim_prince_test.918340695 |
Directory | /workspace/211.prim_prince_test/latest |
Test location | /workspace/coverage/default/212.prim_prince_test.3069381771 |
Short name | T210 |
Test name | |
Test status | |
Simulation time | 1261163548 ps |
CPU time | 21.13 seconds |
Started | Aug 12 04:26:45 PM PDT 24 |
Finished | Aug 12 04:27:11 PM PDT 24 |
Peak memory | 146428 kb |
Host | smart-eb2a54fe-ef30-4f85-896d-03c2a8237988 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3069381771 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 212.prim_prince_test.3069381771 |
Directory | /workspace/212.prim_prince_test/latest |
Test location | /workspace/coverage/default/213.prim_prince_test.2019044414 |
Short name | T88 |
Test name | |
Test status | |
Simulation time | 2190668626 ps |
CPU time | 37 seconds |
Started | Aug 12 04:25:23 PM PDT 24 |
Finished | Aug 12 04:26:08 PM PDT 24 |
Peak memory | 146696 kb |
Host | smart-97ead018-1679-4350-9de7-0358ec80a084 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2019044414 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 213.prim_prince_test.2019044414 |
Directory | /workspace/213.prim_prince_test/latest |
Test location | /workspace/coverage/default/214.prim_prince_test.423205613 |
Short name | T288 |
Test name | |
Test status | |
Simulation time | 3058667990 ps |
CPU time | 51.25 seconds |
Started | Aug 12 04:23:42 PM PDT 24 |
Finished | Aug 12 04:24:45 PM PDT 24 |
Peak memory | 146664 kb |
Host | smart-515b8e45-7dad-416b-ac3a-a871c2dfa31e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=423205613 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 214.prim_prince_test.423205613 |
Directory | /workspace/214.prim_prince_test/latest |
Test location | /workspace/coverage/default/215.prim_prince_test.169791140 |
Short name | T464 |
Test name | |
Test status | |
Simulation time | 3540015631 ps |
CPU time | 58.26 seconds |
Started | Aug 12 04:22:44 PM PDT 24 |
Finished | Aug 12 04:23:54 PM PDT 24 |
Peak memory | 146564 kb |
Host | smart-6d5c2c1b-0aa8-4738-85fe-736d1568c6c3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=169791140 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 215.prim_prince_test.169791140 |
Directory | /workspace/215.prim_prince_test/latest |
Test location | /workspace/coverage/default/216.prim_prince_test.469180898 |
Short name | T104 |
Test name | |
Test status | |
Simulation time | 2173604202 ps |
CPU time | 36.85 seconds |
Started | Aug 12 04:23:46 PM PDT 24 |
Finished | Aug 12 04:24:31 PM PDT 24 |
Peak memory | 146660 kb |
Host | smart-a000ae05-5229-41b1-aa2c-a8160201be20 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=469180898 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 216.prim_prince_test.469180898 |
Directory | /workspace/216.prim_prince_test/latest |
Test location | /workspace/coverage/default/217.prim_prince_test.2820736169 |
Short name | T321 |
Test name | |
Test status | |
Simulation time | 2882234763 ps |
CPU time | 50.17 seconds |
Started | Aug 12 04:25:29 PM PDT 24 |
Finished | Aug 12 04:26:31 PM PDT 24 |
Peak memory | 146828 kb |
Host | smart-64e24f51-8369-409d-80ae-4818950c5070 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2820736169 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 217.prim_prince_test.2820736169 |
Directory | /workspace/217.prim_prince_test/latest |
Test location | /workspace/coverage/default/218.prim_prince_test.184621887 |
Short name | T299 |
Test name | |
Test status | |
Simulation time | 2649002675 ps |
CPU time | 43.11 seconds |
Started | Aug 12 04:27:04 PM PDT 24 |
Finished | Aug 12 04:27:56 PM PDT 24 |
Peak memory | 146192 kb |
Host | smart-35454e3a-362c-4e27-854e-71bde117734a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=184621887 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 218.prim_prince_test.184621887 |
Directory | /workspace/218.prim_prince_test/latest |
Test location | /workspace/coverage/default/219.prim_prince_test.4291809407 |
Short name | T143 |
Test name | |
Test status | |
Simulation time | 1811215808 ps |
CPU time | 29.99 seconds |
Started | Aug 12 04:27:03 PM PDT 24 |
Finished | Aug 12 04:27:40 PM PDT 24 |
Peak memory | 146132 kb |
Host | smart-66875635-b0e1-4314-86e2-db4edecf4175 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4291809407 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 219.prim_prince_test.4291809407 |
Directory | /workspace/219.prim_prince_test/latest |
Test location | /workspace/coverage/default/22.prim_prince_test.3381098717 |
Short name | T249 |
Test name | |
Test status | |
Simulation time | 1019610657 ps |
CPU time | 16.98 seconds |
Started | Aug 12 04:21:16 PM PDT 24 |
Finished | Aug 12 04:21:37 PM PDT 24 |
Peak memory | 146184 kb |
Host | smart-a8ca6652-28b9-4345-b8e0-e86583ef4cf4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3381098717 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_prince_test.3381098717 |
Directory | /workspace/22.prim_prince_test/latest |
Test location | /workspace/coverage/default/220.prim_prince_test.3135072882 |
Short name | T241 |
Test name | |
Test status | |
Simulation time | 795072786 ps |
CPU time | 13.32 seconds |
Started | Aug 12 04:23:33 PM PDT 24 |
Finished | Aug 12 04:23:50 PM PDT 24 |
Peak memory | 146556 kb |
Host | smart-23500f13-8e05-428b-850a-115ef1cdc271 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3135072882 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 220.prim_prince_test.3135072882 |
Directory | /workspace/220.prim_prince_test/latest |
Test location | /workspace/coverage/default/221.prim_prince_test.1217729045 |
Short name | T96 |
Test name | |
Test status | |
Simulation time | 3723399008 ps |
CPU time | 63.61 seconds |
Started | Aug 12 04:23:43 PM PDT 24 |
Finished | Aug 12 04:25:01 PM PDT 24 |
Peak memory | 146696 kb |
Host | smart-3dbbea1c-3932-4e4e-b2e2-5a66639326e3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1217729045 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 221.prim_prince_test.1217729045 |
Directory | /workspace/221.prim_prince_test/latest |
Test location | /workspace/coverage/default/222.prim_prince_test.3287266649 |
Short name | T329 |
Test name | |
Test status | |
Simulation time | 2366772900 ps |
CPU time | 37.8 seconds |
Started | Aug 12 04:27:50 PM PDT 24 |
Finished | Aug 12 04:28:35 PM PDT 24 |
Peak memory | 146628 kb |
Host | smart-d1d1bb21-42ea-4010-8ce7-ae26b77c487c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3287266649 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 222.prim_prince_test.3287266649 |
Directory | /workspace/222.prim_prince_test/latest |
Test location | /workspace/coverage/default/223.prim_prince_test.2082391463 |
Short name | T454 |
Test name | |
Test status | |
Simulation time | 1116322646 ps |
CPU time | 18.52 seconds |
Started | Aug 12 04:27:04 PM PDT 24 |
Finished | Aug 12 04:27:26 PM PDT 24 |
Peak memory | 146132 kb |
Host | smart-5bc0c53d-b733-4e32-8828-1a16b504660e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2082391463 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 223.prim_prince_test.2082391463 |
Directory | /workspace/223.prim_prince_test/latest |
Test location | /workspace/coverage/default/224.prim_prince_test.836566117 |
Short name | T492 |
Test name | |
Test status | |
Simulation time | 1815350527 ps |
CPU time | 31.53 seconds |
Started | Aug 12 04:25:08 PM PDT 24 |
Finished | Aug 12 04:25:47 PM PDT 24 |
Peak memory | 146764 kb |
Host | smart-77051dc6-a1cd-41ef-b97d-318fcc1e8d9f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=836566117 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 224.prim_prince_test.836566117 |
Directory | /workspace/224.prim_prince_test/latest |
Test location | /workspace/coverage/default/225.prim_prince_test.2728957084 |
Short name | T406 |
Test name | |
Test status | |
Simulation time | 1342123766 ps |
CPU time | 23.03 seconds |
Started | Aug 12 04:23:44 PM PDT 24 |
Finished | Aug 12 04:24:12 PM PDT 24 |
Peak memory | 146556 kb |
Host | smart-fdc8c3b8-0626-4726-b28b-c26b072c426a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2728957084 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 225.prim_prince_test.2728957084 |
Directory | /workspace/225.prim_prince_test/latest |
Test location | /workspace/coverage/default/226.prim_prince_test.3048428379 |
Short name | T387 |
Test name | |
Test status | |
Simulation time | 2809464428 ps |
CPU time | 46.34 seconds |
Started | Aug 12 04:22:44 PM PDT 24 |
Finished | Aug 12 04:23:40 PM PDT 24 |
Peak memory | 146572 kb |
Host | smart-40c77af9-e947-4b50-8684-0c419c4b0389 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3048428379 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 226.prim_prince_test.3048428379 |
Directory | /workspace/226.prim_prince_test/latest |
Test location | /workspace/coverage/default/227.prim_prince_test.2099564378 |
Short name | T308 |
Test name | |
Test status | |
Simulation time | 2053055297 ps |
CPU time | 34.87 seconds |
Started | Aug 12 04:23:46 PM PDT 24 |
Finished | Aug 12 04:24:28 PM PDT 24 |
Peak memory | 146556 kb |
Host | smart-0935efaf-b663-4367-ba98-a4bd0bbf31d7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2099564378 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 227.prim_prince_test.2099564378 |
Directory | /workspace/227.prim_prince_test/latest |
Test location | /workspace/coverage/default/228.prim_prince_test.925891985 |
Short name | T275 |
Test name | |
Test status | |
Simulation time | 867131232 ps |
CPU time | 14.74 seconds |
Started | Aug 12 04:23:44 PM PDT 24 |
Finished | Aug 12 04:24:02 PM PDT 24 |
Peak memory | 146564 kb |
Host | smart-efe2974d-9092-4758-ae5b-9b2da6caafba |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=925891985 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 228.prim_prince_test.925891985 |
Directory | /workspace/228.prim_prince_test/latest |
Test location | /workspace/coverage/default/229.prim_prince_test.1719554368 |
Short name | T209 |
Test name | |
Test status | |
Simulation time | 1246602666 ps |
CPU time | 20.7 seconds |
Started | Aug 12 04:27:03 PM PDT 24 |
Finished | Aug 12 04:27:28 PM PDT 24 |
Peak memory | 146132 kb |
Host | smart-a072fb09-cd05-4d1c-851b-6ba9c8564ad9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1719554368 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 229.prim_prince_test.1719554368 |
Directory | /workspace/229.prim_prince_test/latest |
Test location | /workspace/coverage/default/23.prim_prince_test.2077720608 |
Short name | T373 |
Test name | |
Test status | |
Simulation time | 3621399162 ps |
CPU time | 62.55 seconds |
Started | Aug 12 04:21:14 PM PDT 24 |
Finished | Aug 12 04:22:33 PM PDT 24 |
Peak memory | 146676 kb |
Host | smart-7a007970-f44d-4b9b-ad11-46765670ce5b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2077720608 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_prince_test.2077720608 |
Directory | /workspace/23.prim_prince_test/latest |
Test location | /workspace/coverage/default/230.prim_prince_test.3526890413 |
Short name | T456 |
Test name | |
Test status | |
Simulation time | 3605369017 ps |
CPU time | 58.7 seconds |
Started | Aug 12 04:27:04 PM PDT 24 |
Finished | Aug 12 04:28:14 PM PDT 24 |
Peak memory | 146196 kb |
Host | smart-5b1c3642-7e97-4fe8-be7e-5cd0a113e914 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3526890413 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 230.prim_prince_test.3526890413 |
Directory | /workspace/230.prim_prince_test/latest |
Test location | /workspace/coverage/default/231.prim_prince_test.3964539389 |
Short name | T485 |
Test name | |
Test status | |
Simulation time | 3520279784 ps |
CPU time | 57.9 seconds |
Started | Aug 12 04:27:03 PM PDT 24 |
Finished | Aug 12 04:28:13 PM PDT 24 |
Peak memory | 146196 kb |
Host | smart-aeed9216-38e4-4367-a50e-c6d3033cbcdb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3964539389 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 231.prim_prince_test.3964539389 |
Directory | /workspace/231.prim_prince_test/latest |
Test location | /workspace/coverage/default/232.prim_prince_test.339326408 |
Short name | T476 |
Test name | |
Test status | |
Simulation time | 2568555945 ps |
CPU time | 41.12 seconds |
Started | Aug 12 04:27:50 PM PDT 24 |
Finished | Aug 12 04:28:38 PM PDT 24 |
Peak memory | 146636 kb |
Host | smart-f04cd8eb-3dd1-4a23-b140-fc0b0a3351f9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=339326408 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 232.prim_prince_test.339326408 |
Directory | /workspace/232.prim_prince_test/latest |
Test location | /workspace/coverage/default/233.prim_prince_test.2449490550 |
Short name | T394 |
Test name | |
Test status | |
Simulation time | 1847210696 ps |
CPU time | 31.46 seconds |
Started | Aug 12 04:23:53 PM PDT 24 |
Finished | Aug 12 04:24:32 PM PDT 24 |
Peak memory | 146632 kb |
Host | smart-4558c8c0-f34f-4921-a9fd-1566ca1d039b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2449490550 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 233.prim_prince_test.2449490550 |
Directory | /workspace/233.prim_prince_test/latest |
Test location | /workspace/coverage/default/234.prim_prince_test.4109390976 |
Short name | T193 |
Test name | |
Test status | |
Simulation time | 1811426941 ps |
CPU time | 30.05 seconds |
Started | Aug 12 04:27:04 PM PDT 24 |
Finished | Aug 12 04:27:40 PM PDT 24 |
Peak memory | 146132 kb |
Host | smart-6c7db1d6-2711-44a3-8d7b-d3a22b123350 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4109390976 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 234.prim_prince_test.4109390976 |
Directory | /workspace/234.prim_prince_test/latest |
Test location | /workspace/coverage/default/235.prim_prince_test.1387135068 |
Short name | T219 |
Test name | |
Test status | |
Simulation time | 3356090514 ps |
CPU time | 56.83 seconds |
Started | Aug 12 04:23:37 PM PDT 24 |
Finished | Aug 12 04:24:48 PM PDT 24 |
Peak memory | 146668 kb |
Host | smart-7ed8f1f0-7048-403d-bf4b-cb7d1654d710 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1387135068 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 235.prim_prince_test.1387135068 |
Directory | /workspace/235.prim_prince_test/latest |
Test location | /workspace/coverage/default/236.prim_prince_test.2063500540 |
Short name | T356 |
Test name | |
Test status | |
Simulation time | 1939230189 ps |
CPU time | 31.27 seconds |
Started | Aug 12 04:27:49 PM PDT 24 |
Finished | Aug 12 04:28:27 PM PDT 24 |
Peak memory | 146564 kb |
Host | smart-7d10f31d-da96-4f09-8b14-3969dc182508 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2063500540 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 236.prim_prince_test.2063500540 |
Directory | /workspace/236.prim_prince_test/latest |
Test location | /workspace/coverage/default/237.prim_prince_test.3390130666 |
Short name | T149 |
Test name | |
Test status | |
Simulation time | 3669910242 ps |
CPU time | 59.65 seconds |
Started | Aug 12 04:27:04 PM PDT 24 |
Finished | Aug 12 04:28:15 PM PDT 24 |
Peak memory | 146196 kb |
Host | smart-37d473e6-99ff-42e3-995f-d61aba1708fe |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3390130666 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 237.prim_prince_test.3390130666 |
Directory | /workspace/237.prim_prince_test/latest |
Test location | /workspace/coverage/default/238.prim_prince_test.3648550093 |
Short name | T214 |
Test name | |
Test status | |
Simulation time | 756484170 ps |
CPU time | 13.25 seconds |
Started | Aug 12 04:24:30 PM PDT 24 |
Finished | Aug 12 04:24:46 PM PDT 24 |
Peak memory | 146632 kb |
Host | smart-314f5712-957f-4285-ad09-37bf7ce6d8b8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3648550093 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 238.prim_prince_test.3648550093 |
Directory | /workspace/238.prim_prince_test/latest |
Test location | /workspace/coverage/default/239.prim_prince_test.1581714712 |
Short name | T335 |
Test name | |
Test status | |
Simulation time | 1866463268 ps |
CPU time | 31.77 seconds |
Started | Aug 12 04:23:14 PM PDT 24 |
Finished | Aug 12 04:23:54 PM PDT 24 |
Peak memory | 146604 kb |
Host | smart-661c937c-96e7-47a8-bb2c-ab2eaa2f2833 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1581714712 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 239.prim_prince_test.1581714712 |
Directory | /workspace/239.prim_prince_test/latest |
Test location | /workspace/coverage/default/24.prim_prince_test.2754805573 |
Short name | T133 |
Test name | |
Test status | |
Simulation time | 3294595041 ps |
CPU time | 56.69 seconds |
Started | Aug 12 04:21:15 PM PDT 24 |
Finished | Aug 12 04:22:25 PM PDT 24 |
Peak memory | 146676 kb |
Host | smart-390d2696-70fc-4f19-a4a8-49092b749721 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2754805573 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_prince_test.2754805573 |
Directory | /workspace/24.prim_prince_test/latest |
Test location | /workspace/coverage/default/240.prim_prince_test.1185342000 |
Short name | T435 |
Test name | |
Test status | |
Simulation time | 1828721605 ps |
CPU time | 30.15 seconds |
Started | Aug 12 04:26:02 PM PDT 24 |
Finished | Aug 12 04:26:39 PM PDT 24 |
Peak memory | 146368 kb |
Host | smart-449a22e5-1217-4bb4-a31a-1a3b568e2e7d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1185342000 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 240.prim_prince_test.1185342000 |
Directory | /workspace/240.prim_prince_test/latest |
Test location | /workspace/coverage/default/241.prim_prince_test.3047724967 |
Short name | T303 |
Test name | |
Test status | |
Simulation time | 3434857554 ps |
CPU time | 59.12 seconds |
Started | Aug 12 04:24:09 PM PDT 24 |
Finished | Aug 12 04:25:22 PM PDT 24 |
Peak memory | 146828 kb |
Host | smart-bd6eff76-39e4-41cc-b9fc-4d6d0f7639c3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3047724967 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 241.prim_prince_test.3047724967 |
Directory | /workspace/241.prim_prince_test/latest |
Test location | /workspace/coverage/default/242.prim_prince_test.2599343168 |
Short name | T281 |
Test name | |
Test status | |
Simulation time | 2933670459 ps |
CPU time | 50.99 seconds |
Started | Aug 12 04:24:19 PM PDT 24 |
Finished | Aug 12 04:25:23 PM PDT 24 |
Peak memory | 146668 kb |
Host | smart-53422491-35f7-4111-939e-e017943a3c85 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2599343168 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 242.prim_prince_test.2599343168 |
Directory | /workspace/242.prim_prince_test/latest |
Test location | /workspace/coverage/default/243.prim_prince_test.1784898851 |
Short name | T109 |
Test name | |
Test status | |
Simulation time | 2452634940 ps |
CPU time | 38.56 seconds |
Started | Aug 12 04:26:39 PM PDT 24 |
Finished | Aug 12 04:27:24 PM PDT 24 |
Peak memory | 146184 kb |
Host | smart-74a5fef8-c014-454e-9bfa-6537b5d683cd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1784898851 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 243.prim_prince_test.1784898851 |
Directory | /workspace/243.prim_prince_test/latest |
Test location | /workspace/coverage/default/244.prim_prince_test.3357621000 |
Short name | T235 |
Test name | |
Test status | |
Simulation time | 3653383148 ps |
CPU time | 58.19 seconds |
Started | Aug 12 04:26:31 PM PDT 24 |
Finished | Aug 12 04:27:40 PM PDT 24 |
Peak memory | 144892 kb |
Host | smart-08fc7306-24cf-41d6-9963-ef51068b8e59 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3357621000 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 244.prim_prince_test.3357621000 |
Directory | /workspace/244.prim_prince_test/latest |
Test location | /workspace/coverage/default/245.prim_prince_test.1452768317 |
Short name | T128 |
Test name | |
Test status | |
Simulation time | 2797491877 ps |
CPU time | 47.16 seconds |
Started | Aug 12 04:26:28 PM PDT 24 |
Finished | Aug 12 04:27:26 PM PDT 24 |
Peak memory | 146416 kb |
Host | smart-6c423a3a-7519-465f-a016-e7f8e60cf67b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1452768317 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 245.prim_prince_test.1452768317 |
Directory | /workspace/245.prim_prince_test/latest |
Test location | /workspace/coverage/default/246.prim_prince_test.2825075337 |
Short name | T350 |
Test name | |
Test status | |
Simulation time | 3424978048 ps |
CPU time | 55.47 seconds |
Started | Aug 12 04:25:57 PM PDT 24 |
Finished | Aug 12 04:27:03 PM PDT 24 |
Peak memory | 146332 kb |
Host | smart-951f577e-b5d0-4589-9463-5226fbe02190 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2825075337 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 246.prim_prince_test.2825075337 |
Directory | /workspace/246.prim_prince_test/latest |
Test location | /workspace/coverage/default/247.prim_prince_test.528911765 |
Short name | T480 |
Test name | |
Test status | |
Simulation time | 2191747546 ps |
CPU time | 36.64 seconds |
Started | Aug 12 04:25:58 PM PDT 24 |
Finished | Aug 12 04:26:42 PM PDT 24 |
Peak memory | 146328 kb |
Host | smart-cd0780b1-4c21-4e72-9e2e-bdf2f338db70 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=528911765 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 247.prim_prince_test.528911765 |
Directory | /workspace/247.prim_prince_test/latest |
Test location | /workspace/coverage/default/248.prim_prince_test.705427532 |
Short name | T172 |
Test name | |
Test status | |
Simulation time | 1167637022 ps |
CPU time | 18.94 seconds |
Started | Aug 12 04:25:47 PM PDT 24 |
Finished | Aug 12 04:26:10 PM PDT 24 |
Peak memory | 145352 kb |
Host | smart-29b888ce-d272-416f-9a8c-cfc6cb32853a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=705427532 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 248.prim_prince_test.705427532 |
Directory | /workspace/248.prim_prince_test/latest |
Test location | /workspace/coverage/default/249.prim_prince_test.398017060 |
Short name | T408 |
Test name | |
Test status | |
Simulation time | 1354695815 ps |
CPU time | 22.31 seconds |
Started | Aug 12 04:26:32 PM PDT 24 |
Finished | Aug 12 04:26:59 PM PDT 24 |
Peak memory | 146116 kb |
Host | smart-4c455e54-375a-468e-a88c-525e56a0d2dd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=398017060 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 249.prim_prince_test.398017060 |
Directory | /workspace/249.prim_prince_test/latest |
Test location | /workspace/coverage/default/25.prim_prince_test.1428516040 |
Short name | T391 |
Test name | |
Test status | |
Simulation time | 2422871747 ps |
CPU time | 39.74 seconds |
Started | Aug 12 04:22:18 PM PDT 24 |
Finished | Aug 12 04:23:05 PM PDT 24 |
Peak memory | 146176 kb |
Host | smart-8f0264d1-0903-4926-96c7-71ad200cb233 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1428516040 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_prince_test.1428516040 |
Directory | /workspace/25.prim_prince_test/latest |
Test location | /workspace/coverage/default/250.prim_prince_test.3399550362 |
Short name | T121 |
Test name | |
Test status | |
Simulation time | 1806476313 ps |
CPU time | 29.94 seconds |
Started | Aug 12 04:25:58 PM PDT 24 |
Finished | Aug 12 04:26:34 PM PDT 24 |
Peak memory | 146268 kb |
Host | smart-afe2c08c-925e-4d9a-99e2-bced60de5921 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3399550362 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 250.prim_prince_test.3399550362 |
Directory | /workspace/250.prim_prince_test/latest |
Test location | /workspace/coverage/default/251.prim_prince_test.1064270518 |
Short name | T156 |
Test name | |
Test status | |
Simulation time | 1111020110 ps |
CPU time | 19.19 seconds |
Started | Aug 12 04:23:10 PM PDT 24 |
Finished | Aug 12 04:23:34 PM PDT 24 |
Peak memory | 146764 kb |
Host | smart-c9c3d85e-bbe3-4dfe-a994-d313c5ef5cbf |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1064270518 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 251.prim_prince_test.1064270518 |
Directory | /workspace/251.prim_prince_test/latest |
Test location | /workspace/coverage/default/252.prim_prince_test.726301415 |
Short name | T499 |
Test name | |
Test status | |
Simulation time | 793093171 ps |
CPU time | 13.03 seconds |
Started | Aug 12 04:27:04 PM PDT 24 |
Finished | Aug 12 04:27:20 PM PDT 24 |
Peak memory | 146728 kb |
Host | smart-ad7b8870-b395-4500-ae47-1fb646d31234 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=726301415 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 252.prim_prince_test.726301415 |
Directory | /workspace/252.prim_prince_test/latest |
Test location | /workspace/coverage/default/253.prim_prince_test.1534051894 |
Short name | T363 |
Test name | |
Test status | |
Simulation time | 2685706883 ps |
CPU time | 44.12 seconds |
Started | Aug 12 04:26:02 PM PDT 24 |
Finished | Aug 12 04:26:55 PM PDT 24 |
Peak memory | 146432 kb |
Host | smart-16f097cd-4959-4fe6-ad61-7045772b3ed2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1534051894 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 253.prim_prince_test.1534051894 |
Directory | /workspace/253.prim_prince_test/latest |
Test location | /workspace/coverage/default/254.prim_prince_test.28655777 |
Short name | T134 |
Test name | |
Test status | |
Simulation time | 1019618108 ps |
CPU time | 16.99 seconds |
Started | Aug 12 04:25:57 PM PDT 24 |
Finished | Aug 12 04:26:17 PM PDT 24 |
Peak memory | 146264 kb |
Host | smart-88f3d3c4-9273-4e56-9697-6acf1b80e92a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=28655777 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 254.prim_prince_test.28655777 |
Directory | /workspace/254.prim_prince_test/latest |
Test location | /workspace/coverage/default/255.prim_prince_test.1180612318 |
Short name | T353 |
Test name | |
Test status | |
Simulation time | 2300277457 ps |
CPU time | 36.61 seconds |
Started | Aug 12 04:26:38 PM PDT 24 |
Finished | Aug 12 04:27:21 PM PDT 24 |
Peak memory | 146184 kb |
Host | smart-cae44d7a-b3eb-4d42-ad45-d53c34d2eb11 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1180612318 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 255.prim_prince_test.1180612318 |
Directory | /workspace/255.prim_prince_test/latest |
Test location | /workspace/coverage/default/256.prim_prince_test.3958154654 |
Short name | T99 |
Test name | |
Test status | |
Simulation time | 2847675089 ps |
CPU time | 46.7 seconds |
Started | Aug 12 04:26:32 PM PDT 24 |
Finished | Aug 12 04:27:30 PM PDT 24 |
Peak memory | 145124 kb |
Host | smart-948be60e-a915-4b89-9071-b5c72ad38460 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3958154654 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 256.prim_prince_test.3958154654 |
Directory | /workspace/256.prim_prince_test/latest |
Test location | /workspace/coverage/default/257.prim_prince_test.1004636816 |
Short name | T294 |
Test name | |
Test status | |
Simulation time | 3195298238 ps |
CPU time | 52.29 seconds |
Started | Aug 12 04:25:47 PM PDT 24 |
Finished | Aug 12 04:26:50 PM PDT 24 |
Peak memory | 144740 kb |
Host | smart-d4dbd7eb-9432-42d9-a22e-ebaa6ac56f90 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1004636816 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 257.prim_prince_test.1004636816 |
Directory | /workspace/257.prim_prince_test/latest |
Test location | /workspace/coverage/default/258.prim_prince_test.2126049795 |
Short name | T7 |
Test name | |
Test status | |
Simulation time | 2277811574 ps |
CPU time | 37.55 seconds |
Started | Aug 12 04:25:58 PM PDT 24 |
Finished | Aug 12 04:26:43 PM PDT 24 |
Peak memory | 146332 kb |
Host | smart-83f867d3-1601-413c-a3b6-5daec5f9e784 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2126049795 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 258.prim_prince_test.2126049795 |
Directory | /workspace/258.prim_prince_test/latest |
Test location | /workspace/coverage/default/259.prim_prince_test.2106926375 |
Short name | T376 |
Test name | |
Test status | |
Simulation time | 1475202950 ps |
CPU time | 24.34 seconds |
Started | Aug 12 04:26:02 PM PDT 24 |
Finished | Aug 12 04:26:31 PM PDT 24 |
Peak memory | 146368 kb |
Host | smart-0587969f-50b8-4b4e-bdbf-04620b5fd0aa |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2106926375 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 259.prim_prince_test.2106926375 |
Directory | /workspace/259.prim_prince_test/latest |
Test location | /workspace/coverage/default/26.prim_prince_test.3143490151 |
Short name | T320 |
Test name | |
Test status | |
Simulation time | 3377202790 ps |
CPU time | 56.42 seconds |
Started | Aug 12 04:21:16 PM PDT 24 |
Finished | Aug 12 04:22:25 PM PDT 24 |
Peak memory | 146488 kb |
Host | smart-d71180d9-22f7-4e1d-9abf-1916f10e4b25 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3143490151 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_prince_test.3143490151 |
Directory | /workspace/26.prim_prince_test/latest |
Test location | /workspace/coverage/default/260.prim_prince_test.3082008661 |
Short name | T263 |
Test name | |
Test status | |
Simulation time | 3225358021 ps |
CPU time | 54.49 seconds |
Started | Aug 12 04:26:29 PM PDT 24 |
Finished | Aug 12 04:27:36 PM PDT 24 |
Peak memory | 146628 kb |
Host | smart-affc5155-6145-44d7-9823-6b89a2fadc0f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3082008661 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 260.prim_prince_test.3082008661 |
Directory | /workspace/260.prim_prince_test/latest |
Test location | /workspace/coverage/default/261.prim_prince_test.2215403514 |
Short name | T89 |
Test name | |
Test status | |
Simulation time | 1850241507 ps |
CPU time | 30.51 seconds |
Started | Aug 12 04:25:58 PM PDT 24 |
Finished | Aug 12 04:26:35 PM PDT 24 |
Peak memory | 146268 kb |
Host | smart-d53d20a0-f301-4d66-ab42-84e587457ac4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2215403514 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 261.prim_prince_test.2215403514 |
Directory | /workspace/261.prim_prince_test/latest |
Test location | /workspace/coverage/default/262.prim_prince_test.2546316322 |
Short name | T36 |
Test name | |
Test status | |
Simulation time | 918443124 ps |
CPU time | 15.18 seconds |
Started | Aug 12 04:26:17 PM PDT 24 |
Finished | Aug 12 04:26:36 PM PDT 24 |
Peak memory | 146140 kb |
Host | smart-c9c1a470-014b-41f4-b94c-e4083e93cdd6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2546316322 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 262.prim_prince_test.2546316322 |
Directory | /workspace/262.prim_prince_test/latest |
Test location | /workspace/coverage/default/263.prim_prince_test.2120807778 |
Short name | T28 |
Test name | |
Test status | |
Simulation time | 2438740684 ps |
CPU time | 39.96 seconds |
Started | Aug 12 04:25:48 PM PDT 24 |
Finished | Aug 12 04:26:36 PM PDT 24 |
Peak memory | 146116 kb |
Host | smart-367b8c5d-4bef-43cc-a924-85a99a517be1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2120807778 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 263.prim_prince_test.2120807778 |
Directory | /workspace/263.prim_prince_test/latest |
Test location | /workspace/coverage/default/264.prim_prince_test.4284746021 |
Short name | T386 |
Test name | |
Test status | |
Simulation time | 3040932840 ps |
CPU time | 50.49 seconds |
Started | Aug 12 04:26:00 PM PDT 24 |
Finished | Aug 12 04:27:01 PM PDT 24 |
Peak memory | 145724 kb |
Host | smart-f8efec03-c35f-4d9a-9779-d947c213df59 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4284746021 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 264.prim_prince_test.4284746021 |
Directory | /workspace/264.prim_prince_test/latest |
Test location | /workspace/coverage/default/265.prim_prince_test.854994009 |
Short name | T366 |
Test name | |
Test status | |
Simulation time | 934803320 ps |
CPU time | 16.08 seconds |
Started | Aug 12 04:24:03 PM PDT 24 |
Finished | Aug 12 04:24:23 PM PDT 24 |
Peak memory | 146572 kb |
Host | smart-5e20b2ee-f26c-4f96-a098-6490f9e86ae2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=854994009 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 265.prim_prince_test.854994009 |
Directory | /workspace/265.prim_prince_test/latest |
Test location | /workspace/coverage/default/266.prim_prince_test.2155973932 |
Short name | T158 |
Test name | |
Test status | |
Simulation time | 3606560128 ps |
CPU time | 59.21 seconds |
Started | Aug 12 04:25:57 PM PDT 24 |
Finished | Aug 12 04:27:08 PM PDT 24 |
Peak memory | 146332 kb |
Host | smart-2b211154-6280-4651-bfe6-ed4448908c9b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2155973932 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 266.prim_prince_test.2155973932 |
Directory | /workspace/266.prim_prince_test/latest |
Test location | /workspace/coverage/default/267.prim_prince_test.210801146 |
Short name | T429 |
Test name | |
Test status | |
Simulation time | 1700804935 ps |
CPU time | 28.86 seconds |
Started | Aug 12 04:26:28 PM PDT 24 |
Finished | Aug 12 04:27:03 PM PDT 24 |
Peak memory | 146424 kb |
Host | smart-194adb83-0648-4e03-98dc-1b139e896b03 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=210801146 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 267.prim_prince_test.210801146 |
Directory | /workspace/267.prim_prince_test/latest |
Test location | /workspace/coverage/default/268.prim_prince_test.4016571532 |
Short name | T500 |
Test name | |
Test status | |
Simulation time | 3186093911 ps |
CPU time | 52.38 seconds |
Started | Aug 12 04:26:33 PM PDT 24 |
Finished | Aug 12 04:27:37 PM PDT 24 |
Peak memory | 146080 kb |
Host | smart-a98c3f84-77e6-41f1-82d9-e4830d8aee42 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4016571532 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 268.prim_prince_test.4016571532 |
Directory | /workspace/268.prim_prince_test/latest |
Test location | /workspace/coverage/default/269.prim_prince_test.2110122173 |
Short name | T482 |
Test name | |
Test status | |
Simulation time | 1795066763 ps |
CPU time | 28.53 seconds |
Started | Aug 12 04:26:18 PM PDT 24 |
Finished | Aug 12 04:26:51 PM PDT 24 |
Peak memory | 145572 kb |
Host | smart-a9c4f1a3-641e-4294-a251-f2be275f940a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2110122173 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 269.prim_prince_test.2110122173 |
Directory | /workspace/269.prim_prince_test/latest |
Test location | /workspace/coverage/default/27.prim_prince_test.2981171969 |
Short name | T125 |
Test name | |
Test status | |
Simulation time | 1197535491 ps |
CPU time | 20.44 seconds |
Started | Aug 12 04:21:14 PM PDT 24 |
Finished | Aug 12 04:21:40 PM PDT 24 |
Peak memory | 146612 kb |
Host | smart-6750b76e-689f-41d0-8dcc-6e63f1276312 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2981171969 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_prince_test.2981171969 |
Directory | /workspace/27.prim_prince_test/latest |
Test location | /workspace/coverage/default/270.prim_prince_test.1879883642 |
Short name | T230 |
Test name | |
Test status | |
Simulation time | 873417069 ps |
CPU time | 14.16 seconds |
Started | Aug 12 04:26:32 PM PDT 24 |
Finished | Aug 12 04:26:50 PM PDT 24 |
Peak memory | 146428 kb |
Host | smart-101f4994-25c2-4e1a-bac1-21b8a43c4e40 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1879883642 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 270.prim_prince_test.1879883642 |
Directory | /workspace/270.prim_prince_test/latest |
Test location | /workspace/coverage/default/271.prim_prince_test.2027425232 |
Short name | T173 |
Test name | |
Test status | |
Simulation time | 2037373966 ps |
CPU time | 32.5 seconds |
Started | Aug 12 04:26:28 PM PDT 24 |
Finished | Aug 12 04:27:06 PM PDT 24 |
Peak memory | 146132 kb |
Host | smart-b1480c15-5f72-4e39-8222-7172c6cfc068 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2027425232 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 271.prim_prince_test.2027425232 |
Directory | /workspace/271.prim_prince_test/latest |
Test location | /workspace/coverage/default/272.prim_prince_test.2348839711 |
Short name | T374 |
Test name | |
Test status | |
Simulation time | 2906171636 ps |
CPU time | 47.81 seconds |
Started | Aug 12 04:26:17 PM PDT 24 |
Finished | Aug 12 04:27:14 PM PDT 24 |
Peak memory | 145160 kb |
Host | smart-153ce65c-67e9-4dc5-9eb5-a8e75594e29a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2348839711 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 272.prim_prince_test.2348839711 |
Directory | /workspace/272.prim_prince_test/latest |
Test location | /workspace/coverage/default/273.prim_prince_test.4273214919 |
Short name | T287 |
Test name | |
Test status | |
Simulation time | 2850429719 ps |
CPU time | 47.85 seconds |
Started | Aug 12 04:26:26 PM PDT 24 |
Finished | Aug 12 04:27:24 PM PDT 24 |
Peak memory | 146696 kb |
Host | smart-7ae986a4-b041-447f-8be9-5db292f1806e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4273214919 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 273.prim_prince_test.4273214919 |
Directory | /workspace/273.prim_prince_test/latest |
Test location | /workspace/coverage/default/274.prim_prince_test.1330683529 |
Short name | T94 |
Test name | |
Test status | |
Simulation time | 773614808 ps |
CPU time | 12.77 seconds |
Started | Aug 12 04:26:28 PM PDT 24 |
Finished | Aug 12 04:26:44 PM PDT 24 |
Peak memory | 146148 kb |
Host | smart-46779715-82b1-420d-b4e9-6d62d62266b6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1330683529 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 274.prim_prince_test.1330683529 |
Directory | /workspace/274.prim_prince_test/latest |
Test location | /workspace/coverage/default/275.prim_prince_test.2665191701 |
Short name | T225 |
Test name | |
Test status | |
Simulation time | 2673352137 ps |
CPU time | 45.49 seconds |
Started | Aug 12 04:23:24 PM PDT 24 |
Finished | Aug 12 04:24:20 PM PDT 24 |
Peak memory | 146668 kb |
Host | smart-959391ae-3d0d-43ee-893a-4800ccf5bc48 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2665191701 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 275.prim_prince_test.2665191701 |
Directory | /workspace/275.prim_prince_test/latest |
Test location | /workspace/coverage/default/276.prim_prince_test.954658976 |
Short name | T404 |
Test name | |
Test status | |
Simulation time | 3543799546 ps |
CPU time | 57.05 seconds |
Started | Aug 12 04:26:28 PM PDT 24 |
Finished | Aug 12 04:27:36 PM PDT 24 |
Peak memory | 146264 kb |
Host | smart-aa3519e6-5430-42fc-9ab7-614c457f48e6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=954658976 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 276.prim_prince_test.954658976 |
Directory | /workspace/276.prim_prince_test/latest |
Test location | /workspace/coverage/default/277.prim_prince_test.1463422217 |
Short name | T83 |
Test name | |
Test status | |
Simulation time | 845700728 ps |
CPU time | 14.6 seconds |
Started | Aug 12 04:23:16 PM PDT 24 |
Finished | Aug 12 04:23:34 PM PDT 24 |
Peak memory | 146588 kb |
Host | smart-f3908a3b-57fd-45e6-bdfa-9843789c590b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1463422217 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 277.prim_prince_test.1463422217 |
Directory | /workspace/277.prim_prince_test/latest |
Test location | /workspace/coverage/default/278.prim_prince_test.2272480571 |
Short name | T23 |
Test name | |
Test status | |
Simulation time | 2732248798 ps |
CPU time | 47.31 seconds |
Started | Aug 12 04:24:56 PM PDT 24 |
Finished | Aug 12 04:25:55 PM PDT 24 |
Peak memory | 146668 kb |
Host | smart-a648e334-7a58-4905-8d79-afe3f02f51d9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2272480571 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 278.prim_prince_test.2272480571 |
Directory | /workspace/278.prim_prince_test/latest |
Test location | /workspace/coverage/default/279.prim_prince_test.3085171458 |
Short name | T450 |
Test name | |
Test status | |
Simulation time | 3053551134 ps |
CPU time | 52.29 seconds |
Started | Aug 12 04:23:14 PM PDT 24 |
Finished | Aug 12 04:24:19 PM PDT 24 |
Peak memory | 146684 kb |
Host | smart-5f2608f6-fbd8-4871-9981-239059a8ccce |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3085171458 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 279.prim_prince_test.3085171458 |
Directory | /workspace/279.prim_prince_test/latest |
Test location | /workspace/coverage/default/28.prim_prince_test.758283388 |
Short name | T297 |
Test name | |
Test status | |
Simulation time | 2008879552 ps |
CPU time | 33.53 seconds |
Started | Aug 12 04:21:16 PM PDT 24 |
Finished | Aug 12 04:21:57 PM PDT 24 |
Peak memory | 144828 kb |
Host | smart-51a73786-fb5e-4356-a8b1-ee94927dedfd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=758283388 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_prince_test.758283388 |
Directory | /workspace/28.prim_prince_test/latest |
Test location | /workspace/coverage/default/280.prim_prince_test.2596057996 |
Short name | T298 |
Test name | |
Test status | |
Simulation time | 3430538481 ps |
CPU time | 57.88 seconds |
Started | Aug 12 04:25:09 PM PDT 24 |
Finished | Aug 12 04:26:20 PM PDT 24 |
Peak memory | 146696 kb |
Host | smart-ff5d7596-8b70-4372-9b97-92d43cbeebc9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2596057996 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 280.prim_prince_test.2596057996 |
Directory | /workspace/280.prim_prince_test/latest |
Test location | /workspace/coverage/default/281.prim_prince_test.2462463747 |
Short name | T451 |
Test name | |
Test status | |
Simulation time | 3130145173 ps |
CPU time | 53.45 seconds |
Started | Aug 12 04:23:13 PM PDT 24 |
Finished | Aug 12 04:24:19 PM PDT 24 |
Peak memory | 146828 kb |
Host | smart-b67c5519-2eca-4520-9042-cfcf5417eef8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2462463747 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 281.prim_prince_test.2462463747 |
Directory | /workspace/281.prim_prince_test/latest |
Test location | /workspace/coverage/default/282.prim_prince_test.824354489 |
Short name | T349 |
Test name | |
Test status | |
Simulation time | 2501462879 ps |
CPU time | 42.44 seconds |
Started | Aug 12 04:23:25 PM PDT 24 |
Finished | Aug 12 04:24:18 PM PDT 24 |
Peak memory | 146636 kb |
Host | smart-ff7586f0-a7e0-496e-ba76-481ee6c3dbe3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=824354489 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 282.prim_prince_test.824354489 |
Directory | /workspace/282.prim_prince_test/latest |
Test location | /workspace/coverage/default/283.prim_prince_test.2226946979 |
Short name | T130 |
Test name | |
Test status | |
Simulation time | 906782311 ps |
CPU time | 15.05 seconds |
Started | Aug 12 04:26:02 PM PDT 24 |
Finished | Aug 12 04:26:20 PM PDT 24 |
Peak memory | 146368 kb |
Host | smart-5bba2b71-320e-4e12-9549-a1b5fae168d2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2226946979 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 283.prim_prince_test.2226946979 |
Directory | /workspace/283.prim_prince_test/latest |
Test location | /workspace/coverage/default/284.prim_prince_test.3451841988 |
Short name | T95 |
Test name | |
Test status | |
Simulation time | 1409482334 ps |
CPU time | 24.34 seconds |
Started | Aug 12 04:23:13 PM PDT 24 |
Finished | Aug 12 04:23:43 PM PDT 24 |
Peak memory | 146588 kb |
Host | smart-d5ef7b3b-07b9-4155-9562-556de45bd20a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3451841988 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 284.prim_prince_test.3451841988 |
Directory | /workspace/284.prim_prince_test/latest |
Test location | /workspace/coverage/default/285.prim_prince_test.2729362251 |
Short name | T475 |
Test name | |
Test status | |
Simulation time | 2926258893 ps |
CPU time | 46.6 seconds |
Started | Aug 12 04:26:55 PM PDT 24 |
Finished | Aug 12 04:27:50 PM PDT 24 |
Peak memory | 145636 kb |
Host | smart-1823450b-6889-4c64-8fb9-f3045c1ddb9a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2729362251 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 285.prim_prince_test.2729362251 |
Directory | /workspace/285.prim_prince_test/latest |
Test location | /workspace/coverage/default/286.prim_prince_test.3596087887 |
Short name | T296 |
Test name | |
Test status | |
Simulation time | 784852195 ps |
CPU time | 13.26 seconds |
Started | Aug 12 04:26:30 PM PDT 24 |
Finished | Aug 12 04:26:46 PM PDT 24 |
Peak memory | 146356 kb |
Host | smart-2e10f4b3-b305-4aeb-be28-b9accf271c1a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3596087887 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 286.prim_prince_test.3596087887 |
Directory | /workspace/286.prim_prince_test/latest |
Test location | /workspace/coverage/default/287.prim_prince_test.2951714156 |
Short name | T286 |
Test name | |
Test status | |
Simulation time | 1306092089 ps |
CPU time | 21.21 seconds |
Started | Aug 12 04:26:29 PM PDT 24 |
Finished | Aug 12 04:26:54 PM PDT 24 |
Peak memory | 146028 kb |
Host | smart-974c2ec5-cb38-4cc1-a12e-156483991118 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2951714156 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 287.prim_prince_test.2951714156 |
Directory | /workspace/287.prim_prince_test/latest |
Test location | /workspace/coverage/default/288.prim_prince_test.1717985798 |
Short name | T280 |
Test name | |
Test status | |
Simulation time | 1261291021 ps |
CPU time | 20.73 seconds |
Started | Aug 12 04:26:26 PM PDT 24 |
Finished | Aug 12 04:26:51 PM PDT 24 |
Peak memory | 146484 kb |
Host | smart-c3a2db0d-f13a-4ff5-a29b-fde8e82c2533 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1717985798 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 288.prim_prince_test.1717985798 |
Directory | /workspace/288.prim_prince_test/latest |
Test location | /workspace/coverage/default/289.prim_prince_test.4126745800 |
Short name | T162 |
Test name | |
Test status | |
Simulation time | 3333715752 ps |
CPU time | 55.35 seconds |
Started | Aug 12 04:26:32 PM PDT 24 |
Finished | Aug 12 04:27:40 PM PDT 24 |
Peak memory | 143992 kb |
Host | smart-9fa564b2-b352-45ce-868f-f16071fd3d09 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4126745800 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 289.prim_prince_test.4126745800 |
Directory | /workspace/289.prim_prince_test/latest |
Test location | /workspace/coverage/default/29.prim_prince_test.3142792867 |
Short name | T69 |
Test name | |
Test status | |
Simulation time | 3513886667 ps |
CPU time | 57.92 seconds |
Started | Aug 12 04:21:18 PM PDT 24 |
Finished | Aug 12 04:22:28 PM PDT 24 |
Peak memory | 146232 kb |
Host | smart-c5e0113e-9202-46ce-9904-54797d3cab50 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3142792867 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_prince_test.3142792867 |
Directory | /workspace/29.prim_prince_test/latest |
Test location | /workspace/coverage/default/290.prim_prince_test.4089398365 |
Short name | T176 |
Test name | |
Test status | |
Simulation time | 1487819357 ps |
CPU time | 23.81 seconds |
Started | Aug 12 04:26:17 PM PDT 24 |
Finished | Aug 12 04:26:46 PM PDT 24 |
Peak memory | 146140 kb |
Host | smart-0162ee36-ae19-4ad3-a039-15ec9bcea2ee |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4089398365 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 290.prim_prince_test.4089398365 |
Directory | /workspace/290.prim_prince_test/latest |
Test location | /workspace/coverage/default/291.prim_prince_test.4037524766 |
Short name | T301 |
Test name | |
Test status | |
Simulation time | 3336260729 ps |
CPU time | 52.95 seconds |
Started | Aug 12 04:27:34 PM PDT 24 |
Finished | Aug 12 04:28:37 PM PDT 24 |
Peak memory | 145092 kb |
Host | smart-975cc4db-99a0-49dc-9566-65ddf2bc83cf |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4037524766 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 291.prim_prince_test.4037524766 |
Directory | /workspace/291.prim_prince_test/latest |
Test location | /workspace/coverage/default/292.prim_prince_test.2453048997 |
Short name | T317 |
Test name | |
Test status | |
Simulation time | 2075788780 ps |
CPU time | 34.47 seconds |
Started | Aug 12 04:26:25 PM PDT 24 |
Finished | Aug 12 04:27:08 PM PDT 24 |
Peak memory | 146264 kb |
Host | smart-863aa466-7270-4219-a184-72e95149d68a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2453048997 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 292.prim_prince_test.2453048997 |
Directory | /workspace/292.prim_prince_test/latest |
Test location | /workspace/coverage/default/293.prim_prince_test.4040308314 |
Short name | T74 |
Test name | |
Test status | |
Simulation time | 876082825 ps |
CPU time | 14.53 seconds |
Started | Aug 12 04:26:39 PM PDT 24 |
Finished | Aug 12 04:26:57 PM PDT 24 |
Peak memory | 146120 kb |
Host | smart-922eedd9-d278-46fc-9ab2-519170c685dd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4040308314 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 293.prim_prince_test.4040308314 |
Directory | /workspace/293.prim_prince_test/latest |
Test location | /workspace/coverage/default/294.prim_prince_test.124066283 |
Short name | T132 |
Test name | |
Test status | |
Simulation time | 2067380916 ps |
CPU time | 34.15 seconds |
Started | Aug 12 04:26:27 PM PDT 24 |
Finished | Aug 12 04:27:08 PM PDT 24 |
Peak memory | 146364 kb |
Host | smart-411c0247-515e-4e8c-b76d-f9abdbd4e706 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=124066283 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 294.prim_prince_test.124066283 |
Directory | /workspace/294.prim_prince_test/latest |
Test location | /workspace/coverage/default/295.prim_prince_test.799331164 |
Short name | T461 |
Test name | |
Test status | |
Simulation time | 1219160156 ps |
CPU time | 20.54 seconds |
Started | Aug 12 04:26:33 PM PDT 24 |
Finished | Aug 12 04:26:58 PM PDT 24 |
Peak memory | 146572 kb |
Host | smart-ac93cff1-88ed-419d-baec-c3aef461803a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=799331164 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 295.prim_prince_test.799331164 |
Directory | /workspace/295.prim_prince_test/latest |
Test location | /workspace/coverage/default/296.prim_prince_test.231032620 |
Short name | T310 |
Test name | |
Test status | |
Simulation time | 3246390567 ps |
CPU time | 52.38 seconds |
Started | Aug 12 04:26:26 PM PDT 24 |
Finished | Aug 12 04:27:27 PM PDT 24 |
Peak memory | 146524 kb |
Host | smart-5ae40445-a248-4ba8-b120-76b25292a826 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=231032620 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 296.prim_prince_test.231032620 |
Directory | /workspace/296.prim_prince_test/latest |
Test location | /workspace/coverage/default/297.prim_prince_test.1283718715 |
Short name | T319 |
Test name | |
Test status | |
Simulation time | 2850135400 ps |
CPU time | 45.83 seconds |
Started | Aug 12 04:26:25 PM PDT 24 |
Finished | Aug 12 04:27:19 PM PDT 24 |
Peak memory | 146492 kb |
Host | smart-2d03283b-66a1-4ba5-9739-22e8268f1f2c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1283718715 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 297.prim_prince_test.1283718715 |
Directory | /workspace/297.prim_prince_test/latest |
Test location | /workspace/coverage/default/298.prim_prince_test.2900152954 |
Short name | T357 |
Test name | |
Test status | |
Simulation time | 2750240425 ps |
CPU time | 44.98 seconds |
Started | Aug 12 04:26:42 PM PDT 24 |
Finished | Aug 12 04:27:36 PM PDT 24 |
Peak memory | 146292 kb |
Host | smart-bed167a9-9b73-41e4-8cfa-bdb087a7584f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2900152954 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 298.prim_prince_test.2900152954 |
Directory | /workspace/298.prim_prince_test/latest |
Test location | /workspace/coverage/default/299.prim_prince_test.2056208899 |
Short name | T390 |
Test name | |
Test status | |
Simulation time | 2386561826 ps |
CPU time | 39.22 seconds |
Started | Aug 12 04:26:27 PM PDT 24 |
Finished | Aug 12 04:27:14 PM PDT 24 |
Peak memory | 145232 kb |
Host | smart-2eb40e74-b514-4418-a54b-2fe5dc3c1e34 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2056208899 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 299.prim_prince_test.2056208899 |
Directory | /workspace/299.prim_prince_test/latest |
Test location | /workspace/coverage/default/3.prim_prince_test.762482324 |
Short name | T47 |
Test name | |
Test status | |
Simulation time | 1219397470 ps |
CPU time | 20.94 seconds |
Started | Aug 12 04:21:04 PM PDT 24 |
Finished | Aug 12 04:21:29 PM PDT 24 |
Peak memory | 145512 kb |
Host | smart-3a26eec4-7a09-4436-b326-d31ef9e713c4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=762482324 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_prince_test.762482324 |
Directory | /workspace/3.prim_prince_test/latest |
Test location | /workspace/coverage/default/30.prim_prince_test.3552843277 |
Short name | T343 |
Test name | |
Test status | |
Simulation time | 3499296770 ps |
CPU time | 57.13 seconds |
Started | Aug 12 04:21:15 PM PDT 24 |
Finished | Aug 12 04:22:23 PM PDT 24 |
Peak memory | 145948 kb |
Host | smart-930ce3ca-bdbf-4930-9f7d-34c114aa1914 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3552843277 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_prince_test.3552843277 |
Directory | /workspace/30.prim_prince_test/latest |
Test location | /workspace/coverage/default/300.prim_prince_test.2067310104 |
Short name | T66 |
Test name | |
Test status | |
Simulation time | 1799786761 ps |
CPU time | 29.49 seconds |
Started | Aug 12 04:26:26 PM PDT 24 |
Finished | Aug 12 04:27:02 PM PDT 24 |
Peak memory | 145368 kb |
Host | smart-fba82751-68e2-4c73-9008-13632befb1bd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2067310104 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 300.prim_prince_test.2067310104 |
Directory | /workspace/300.prim_prince_test/latest |
Test location | /workspace/coverage/default/301.prim_prince_test.3970282624 |
Short name | T17 |
Test name | |
Test status | |
Simulation time | 2130347226 ps |
CPU time | 34.91 seconds |
Started | Aug 12 04:26:32 PM PDT 24 |
Finished | Aug 12 04:27:14 PM PDT 24 |
Peak memory | 146512 kb |
Host | smart-601fd4ae-e4d4-411b-9fa5-d04387103485 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3970282624 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 301.prim_prince_test.3970282624 |
Directory | /workspace/301.prim_prince_test/latest |
Test location | /workspace/coverage/default/302.prim_prince_test.1616001327 |
Short name | T116 |
Test name | |
Test status | |
Simulation time | 1534410315 ps |
CPU time | 25.23 seconds |
Started | Aug 12 04:26:56 PM PDT 24 |
Finished | Aug 12 04:27:26 PM PDT 24 |
Peak memory | 146452 kb |
Host | smart-063f6366-5e41-404f-b086-29ffc30a6ddc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1616001327 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 302.prim_prince_test.1616001327 |
Directory | /workspace/302.prim_prince_test/latest |
Test location | /workspace/coverage/default/303.prim_prince_test.2875565011 |
Short name | T453 |
Test name | |
Test status | |
Simulation time | 1920471212 ps |
CPU time | 32.6 seconds |
Started | Aug 12 04:23:31 PM PDT 24 |
Finished | Aug 12 04:24:10 PM PDT 24 |
Peak memory | 146632 kb |
Host | smart-4abca8ec-8399-4817-b870-b0e8b78696c7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2875565011 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 303.prim_prince_test.2875565011 |
Directory | /workspace/303.prim_prince_test/latest |
Test location | /workspace/coverage/default/304.prim_prince_test.1532162084 |
Short name | T388 |
Test name | |
Test status | |
Simulation time | 2049030181 ps |
CPU time | 33.46 seconds |
Started | Aug 12 04:26:17 PM PDT 24 |
Finished | Aug 12 04:26:58 PM PDT 24 |
Peak memory | 144816 kb |
Host | smart-73617f81-4583-4a47-ba09-057f3939ec6a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1532162084 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 304.prim_prince_test.1532162084 |
Directory | /workspace/304.prim_prince_test/latest |
Test location | /workspace/coverage/default/305.prim_prince_test.3893615461 |
Short name | T127 |
Test name | |
Test status | |
Simulation time | 800030469 ps |
CPU time | 13.7 seconds |
Started | Aug 12 04:23:29 PM PDT 24 |
Finished | Aug 12 04:23:46 PM PDT 24 |
Peak memory | 146596 kb |
Host | smart-45f64c98-0cb5-40f5-a4ca-cb622209b581 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3893615461 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 305.prim_prince_test.3893615461 |
Directory | /workspace/305.prim_prince_test/latest |
Test location | /workspace/coverage/default/306.prim_prince_test.993057967 |
Short name | T35 |
Test name | |
Test status | |
Simulation time | 2724717662 ps |
CPU time | 44.16 seconds |
Started | Aug 12 04:26:17 PM PDT 24 |
Finished | Aug 12 04:27:10 PM PDT 24 |
Peak memory | 144940 kb |
Host | smart-05174894-c01d-412d-8f1d-cd0b33665687 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=993057967 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 306.prim_prince_test.993057967 |
Directory | /workspace/306.prim_prince_test/latest |
Test location | /workspace/coverage/default/307.prim_prince_test.3753238798 |
Short name | T487 |
Test name | |
Test status | |
Simulation time | 1661069422 ps |
CPU time | 27.72 seconds |
Started | Aug 12 04:24:02 PM PDT 24 |
Finished | Aug 12 04:24:35 PM PDT 24 |
Peak memory | 146588 kb |
Host | smart-a72c4fbf-eea1-4a22-abab-36ca63f4e08a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3753238798 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 307.prim_prince_test.3753238798 |
Directory | /workspace/307.prim_prince_test/latest |
Test location | /workspace/coverage/default/308.prim_prince_test.4136552841 |
Short name | T43 |
Test name | |
Test status | |
Simulation time | 1314308207 ps |
CPU time | 21.17 seconds |
Started | Aug 12 04:26:29 PM PDT 24 |
Finished | Aug 12 04:26:54 PM PDT 24 |
Peak memory | 146800 kb |
Host | smart-4e09607d-ff2f-4ea2-b3b4-a55e07e300d6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4136552841 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 308.prim_prince_test.4136552841 |
Directory | /workspace/308.prim_prince_test/latest |
Test location | /workspace/coverage/default/309.prim_prince_test.2744081598 |
Short name | T330 |
Test name | |
Test status | |
Simulation time | 3414261607 ps |
CPU time | 57.57 seconds |
Started | Aug 12 04:24:12 PM PDT 24 |
Finished | Aug 12 04:25:23 PM PDT 24 |
Peak memory | 146628 kb |
Host | smart-610f5a2e-10bf-4f4d-adc6-8ee2283009d1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2744081598 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 309.prim_prince_test.2744081598 |
Directory | /workspace/309.prim_prince_test/latest |
Test location | /workspace/coverage/default/31.prim_prince_test.2255179864 |
Short name | T185 |
Test name | |
Test status | |
Simulation time | 1167685349 ps |
CPU time | 19.21 seconds |
Started | Aug 12 04:21:17 PM PDT 24 |
Finished | Aug 12 04:21:40 PM PDT 24 |
Peak memory | 146204 kb |
Host | smart-3e6ef7b5-6811-4285-a19e-e145ab18236c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2255179864 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_prince_test.2255179864 |
Directory | /workspace/31.prim_prince_test/latest |
Test location | /workspace/coverage/default/310.prim_prince_test.70457060 |
Short name | T71 |
Test name | |
Test status | |
Simulation time | 3050043576 ps |
CPU time | 52.37 seconds |
Started | Aug 12 04:25:12 PM PDT 24 |
Finished | Aug 12 04:26:18 PM PDT 24 |
Peak memory | 146716 kb |
Host | smart-b03723ce-53d1-4739-a578-ef4bac430c9d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=70457060 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 310.prim_prince_test.70457060 |
Directory | /workspace/310.prim_prince_test/latest |
Test location | /workspace/coverage/default/311.prim_prince_test.2761999458 |
Short name | T136 |
Test name | |
Test status | |
Simulation time | 1402287449 ps |
CPU time | 24.87 seconds |
Started | Aug 12 04:23:32 PM PDT 24 |
Finished | Aug 12 04:24:03 PM PDT 24 |
Peak memory | 146656 kb |
Host | smart-433903b6-e782-4a92-8da2-65858732b307 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2761999458 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 311.prim_prince_test.2761999458 |
Directory | /workspace/311.prim_prince_test/latest |
Test location | /workspace/coverage/default/312.prim_prince_test.2128835280 |
Short name | T19 |
Test name | |
Test status | |
Simulation time | 1512989443 ps |
CPU time | 24.21 seconds |
Started | Aug 12 04:26:10 PM PDT 24 |
Finished | Aug 12 04:26:39 PM PDT 24 |
Peak memory | 145432 kb |
Host | smart-374bbbe0-42a7-4d05-833e-87cca7534bdd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2128835280 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 312.prim_prince_test.2128835280 |
Directory | /workspace/312.prim_prince_test/latest |
Test location | /workspace/coverage/default/313.prim_prince_test.3091896064 |
Short name | T272 |
Test name | |
Test status | |
Simulation time | 1616047917 ps |
CPU time | 26.74 seconds |
Started | Aug 12 04:26:57 PM PDT 24 |
Finished | Aug 12 04:27:29 PM PDT 24 |
Peak memory | 146544 kb |
Host | smart-c88829c7-16e0-4391-b187-8c6f2316c8f0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3091896064 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 313.prim_prince_test.3091896064 |
Directory | /workspace/313.prim_prince_test/latest |
Test location | /workspace/coverage/default/314.prim_prince_test.3299941516 |
Short name | T187 |
Test name | |
Test status | |
Simulation time | 2263319593 ps |
CPU time | 36.39 seconds |
Started | Aug 12 04:26:18 PM PDT 24 |
Finished | Aug 12 04:27:01 PM PDT 24 |
Peak memory | 146184 kb |
Host | smart-dbd52156-0bf0-4463-94df-887071f96fff |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3299941516 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 314.prim_prince_test.3299941516 |
Directory | /workspace/314.prim_prince_test/latest |
Test location | /workspace/coverage/default/315.prim_prince_test.1851020879 |
Short name | T375 |
Test name | |
Test status | |
Simulation time | 1656996874 ps |
CPU time | 27.18 seconds |
Started | Aug 12 04:26:57 PM PDT 24 |
Finished | Aug 12 04:27:29 PM PDT 24 |
Peak memory | 146548 kb |
Host | smart-d1352d4d-0c26-47d7-ab94-d4ae4cc7c0a0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1851020879 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 315.prim_prince_test.1851020879 |
Directory | /workspace/315.prim_prince_test/latest |
Test location | /workspace/coverage/default/316.prim_prince_test.2438523130 |
Short name | T192 |
Test name | |
Test status | |
Simulation time | 1129130119 ps |
CPU time | 18.63 seconds |
Started | Aug 12 04:26:18 PM PDT 24 |
Finished | Aug 12 04:26:40 PM PDT 24 |
Peak memory | 146236 kb |
Host | smart-043cd35c-2218-42fe-9b1e-28a174833bd7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2438523130 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 316.prim_prince_test.2438523130 |
Directory | /workspace/316.prim_prince_test/latest |
Test location | /workspace/coverage/default/317.prim_prince_test.2241046082 |
Short name | T73 |
Test name | |
Test status | |
Simulation time | 2850362149 ps |
CPU time | 47.19 seconds |
Started | Aug 12 04:27:23 PM PDT 24 |
Finished | Aug 12 04:28:20 PM PDT 24 |
Peak memory | 144380 kb |
Host | smart-5d7f172b-78c3-4223-bba6-cf40a57bcd00 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2241046082 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 317.prim_prince_test.2241046082 |
Directory | /workspace/317.prim_prince_test/latest |
Test location | /workspace/coverage/default/318.prim_prince_test.1532594525 |
Short name | T159 |
Test name | |
Test status | |
Simulation time | 850292550 ps |
CPU time | 14.76 seconds |
Started | Aug 12 04:24:17 PM PDT 24 |
Finished | Aug 12 04:24:35 PM PDT 24 |
Peak memory | 146556 kb |
Host | smart-b5331d17-25b8-4056-8b7b-39561e67012c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1532594525 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 318.prim_prince_test.1532594525 |
Directory | /workspace/318.prim_prince_test/latest |
Test location | /workspace/coverage/default/319.prim_prince_test.766579816 |
Short name | T444 |
Test name | |
Test status | |
Simulation time | 2151928621 ps |
CPU time | 35.19 seconds |
Started | Aug 12 04:26:29 PM PDT 24 |
Finished | Aug 12 04:27:12 PM PDT 24 |
Peak memory | 146648 kb |
Host | smart-1fd1c333-983b-40bb-89b7-e90b4b0b31de |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=766579816 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 319.prim_prince_test.766579816 |
Directory | /workspace/319.prim_prince_test/latest |
Test location | /workspace/coverage/default/32.prim_prince_test.2847428450 |
Short name | T86 |
Test name | |
Test status | |
Simulation time | 2292376289 ps |
CPU time | 38.06 seconds |
Started | Aug 12 04:22:18 PM PDT 24 |
Finished | Aug 12 04:23:04 PM PDT 24 |
Peak memory | 146468 kb |
Host | smart-5799e4a2-8c33-4722-912e-e37155170e95 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2847428450 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_prince_test.2847428450 |
Directory | /workspace/32.prim_prince_test/latest |
Test location | /workspace/coverage/default/320.prim_prince_test.3996976536 |
Short name | T488 |
Test name | |
Test status | |
Simulation time | 1529802058 ps |
CPU time | 24.21 seconds |
Started | Aug 12 04:26:15 PM PDT 24 |
Finished | Aug 12 04:26:44 PM PDT 24 |
Peak memory | 146476 kb |
Host | smart-b0f7175e-c8fc-41ce-859b-ac17cae8cce7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3996976536 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 320.prim_prince_test.3996976536 |
Directory | /workspace/320.prim_prince_test/latest |
Test location | /workspace/coverage/default/321.prim_prince_test.910953146 |
Short name | T196 |
Test name | |
Test status | |
Simulation time | 3151087702 ps |
CPU time | 53.57 seconds |
Started | Aug 12 04:23:58 PM PDT 24 |
Finished | Aug 12 04:25:04 PM PDT 24 |
Peak memory | 146732 kb |
Host | smart-a04b7787-1506-4346-a6c9-a78d9606e390 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=910953146 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 321.prim_prince_test.910953146 |
Directory | /workspace/321.prim_prince_test/latest |
Test location | /workspace/coverage/default/322.prim_prince_test.198986872 |
Short name | T126 |
Test name | |
Test status | |
Simulation time | 2858450718 ps |
CPU time | 46.15 seconds |
Started | Aug 12 04:26:59 PM PDT 24 |
Finished | Aug 12 04:27:53 PM PDT 24 |
Peak memory | 146620 kb |
Host | smart-6406cda6-cf12-47ba-a845-08bbe967da0f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=198986872 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 322.prim_prince_test.198986872 |
Directory | /workspace/322.prim_prince_test/latest |
Test location | /workspace/coverage/default/323.prim_prince_test.3422713161 |
Short name | T183 |
Test name | |
Test status | |
Simulation time | 3457678957 ps |
CPU time | 56.46 seconds |
Started | Aug 12 04:26:30 PM PDT 24 |
Finished | Aug 12 04:27:37 PM PDT 24 |
Peak memory | 146640 kb |
Host | smart-ee420117-f8b1-4972-83ae-c306626d30bf |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3422713161 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 323.prim_prince_test.3422713161 |
Directory | /workspace/323.prim_prince_test/latest |
Test location | /workspace/coverage/default/324.prim_prince_test.369086625 |
Short name | T312 |
Test name | |
Test status | |
Simulation time | 3140972860 ps |
CPU time | 51.03 seconds |
Started | Aug 12 04:27:24 PM PDT 24 |
Finished | Aug 12 04:28:25 PM PDT 24 |
Peak memory | 146324 kb |
Host | smart-2bd61712-d078-4c45-997b-4b2213afc45e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=369086625 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 324.prim_prince_test.369086625 |
Directory | /workspace/324.prim_prince_test/latest |
Test location | /workspace/coverage/default/325.prim_prince_test.375201063 |
Short name | T114 |
Test name | |
Test status | |
Simulation time | 1786789685 ps |
CPU time | 28.78 seconds |
Started | Aug 12 04:26:17 PM PDT 24 |
Finished | Aug 12 04:26:51 PM PDT 24 |
Peak memory | 145604 kb |
Host | smart-1ceee43f-2572-44c3-897e-e5027fd6379a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=375201063 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 325.prim_prince_test.375201063 |
Directory | /workspace/325.prim_prince_test/latest |
Test location | /workspace/coverage/default/326.prim_prince_test.4199368396 |
Short name | T243 |
Test name | |
Test status | |
Simulation time | 2192653795 ps |
CPU time | 36.36 seconds |
Started | Aug 12 04:26:29 PM PDT 24 |
Finished | Aug 12 04:27:13 PM PDT 24 |
Peak memory | 146640 kb |
Host | smart-1117304a-a3cf-4795-98e7-d3d082686ccb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4199368396 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 326.prim_prince_test.4199368396 |
Directory | /workspace/326.prim_prince_test/latest |
Test location | /workspace/coverage/default/327.prim_prince_test.1164392567 |
Short name | T413 |
Test name | |
Test status | |
Simulation time | 787530582 ps |
CPU time | 13.24 seconds |
Started | Aug 12 04:26:30 PM PDT 24 |
Finished | Aug 12 04:26:46 PM PDT 24 |
Peak memory | 146576 kb |
Host | smart-db3e40b8-0e39-4b80-bc5d-1c0133ef5022 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1164392567 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 327.prim_prince_test.1164392567 |
Directory | /workspace/327.prim_prince_test/latest |
Test location | /workspace/coverage/default/328.prim_prince_test.2082109512 |
Short name | T30 |
Test name | |
Test status | |
Simulation time | 1859741432 ps |
CPU time | 30.5 seconds |
Started | Aug 12 04:27:23 PM PDT 24 |
Finished | Aug 12 04:28:00 PM PDT 24 |
Peak memory | 146204 kb |
Host | smart-91a3c831-f352-4546-ae8b-23c14477bd8a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2082109512 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 328.prim_prince_test.2082109512 |
Directory | /workspace/328.prim_prince_test/latest |
Test location | /workspace/coverage/default/329.prim_prince_test.3474513055 |
Short name | T112 |
Test name | |
Test status | |
Simulation time | 1599393922 ps |
CPU time | 26.7 seconds |
Started | Aug 12 04:27:23 PM PDT 24 |
Finished | Aug 12 04:27:56 PM PDT 24 |
Peak memory | 144740 kb |
Host | smart-6789367d-490b-4961-8d47-d4728cf83276 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3474513055 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 329.prim_prince_test.3474513055 |
Directory | /workspace/329.prim_prince_test/latest |
Test location | /workspace/coverage/default/33.prim_prince_test.3109338176 |
Short name | T414 |
Test name | |
Test status | |
Simulation time | 1809585151 ps |
CPU time | 29.66 seconds |
Started | Aug 12 04:21:06 PM PDT 24 |
Finished | Aug 12 04:21:42 PM PDT 24 |
Peak memory | 146440 kb |
Host | smart-15a6d7d9-a049-459e-b132-93cc1e54b3a9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3109338176 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_prince_test.3109338176 |
Directory | /workspace/33.prim_prince_test/latest |
Test location | /workspace/coverage/default/330.prim_prince_test.694302760 |
Short name | T339 |
Test name | |
Test status | |
Simulation time | 3185849214 ps |
CPU time | 50.88 seconds |
Started | Aug 12 04:26:43 PM PDT 24 |
Finished | Aug 12 04:27:42 PM PDT 24 |
Peak memory | 145652 kb |
Host | smart-f71fd6a0-1b7c-4842-9785-48351fdae709 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=694302760 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 330.prim_prince_test.694302760 |
Directory | /workspace/330.prim_prince_test/latest |
Test location | /workspace/coverage/default/331.prim_prince_test.434605115 |
Short name | T449 |
Test name | |
Test status | |
Simulation time | 2871850407 ps |
CPU time | 50.5 seconds |
Started | Aug 12 04:23:40 PM PDT 24 |
Finished | Aug 12 04:24:43 PM PDT 24 |
Peak memory | 146732 kb |
Host | smart-46b3be10-244c-488c-98a9-be962d576d4c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=434605115 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 331.prim_prince_test.434605115 |
Directory | /workspace/331.prim_prince_test/latest |
Test location | /workspace/coverage/default/332.prim_prince_test.3040902878 |
Short name | T115 |
Test name | |
Test status | |
Simulation time | 3659915564 ps |
CPU time | 62.59 seconds |
Started | Aug 12 04:25:22 PM PDT 24 |
Finished | Aug 12 04:26:40 PM PDT 24 |
Peak memory | 146720 kb |
Host | smart-21b3cdcb-12f7-4821-bb80-7d80c8c7bbfc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3040902878 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 332.prim_prince_test.3040902878 |
Directory | /workspace/332.prim_prince_test/latest |
Test location | /workspace/coverage/default/333.prim_prince_test.1233934337 |
Short name | T190 |
Test name | |
Test status | |
Simulation time | 1616271001 ps |
CPU time | 27.76 seconds |
Started | Aug 12 04:25:12 PM PDT 24 |
Finished | Aug 12 04:25:46 PM PDT 24 |
Peak memory | 146656 kb |
Host | smart-08abd6a9-5cc1-491c-8727-f56c0f46627b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1233934337 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 333.prim_prince_test.1233934337 |
Directory | /workspace/333.prim_prince_test/latest |
Test location | /workspace/coverage/default/334.prim_prince_test.885526044 |
Short name | T169 |
Test name | |
Test status | |
Simulation time | 1992721921 ps |
CPU time | 32.96 seconds |
Started | Aug 12 04:26:30 PM PDT 24 |
Finished | Aug 12 04:27:09 PM PDT 24 |
Peak memory | 146584 kb |
Host | smart-95e290d7-8813-41be-97b0-a3a53fd0841a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=885526044 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 334.prim_prince_test.885526044 |
Directory | /workspace/334.prim_prince_test/latest |
Test location | /workspace/coverage/default/335.prim_prince_test.3787261316 |
Short name | T22 |
Test name | |
Test status | |
Simulation time | 1354751996 ps |
CPU time | 22.77 seconds |
Started | Aug 12 04:26:31 PM PDT 24 |
Finished | Aug 12 04:26:59 PM PDT 24 |
Peak memory | 144244 kb |
Host | smart-14d26186-2d59-45bf-9a57-cf0f688e3e4b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3787261316 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 335.prim_prince_test.3787261316 |
Directory | /workspace/335.prim_prince_test/latest |
Test location | /workspace/coverage/default/336.prim_prince_test.3174924037 |
Short name | T18 |
Test name | |
Test status | |
Simulation time | 2571908184 ps |
CPU time | 41.64 seconds |
Started | Aug 12 04:26:32 PM PDT 24 |
Finished | Aug 12 04:27:22 PM PDT 24 |
Peak memory | 145792 kb |
Host | smart-0f25e691-3119-4724-be44-17cbbb0b41e4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3174924037 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 336.prim_prince_test.3174924037 |
Directory | /workspace/336.prim_prince_test/latest |
Test location | /workspace/coverage/default/337.prim_prince_test.550811627 |
Short name | T270 |
Test name | |
Test status | |
Simulation time | 2208563949 ps |
CPU time | 35.93 seconds |
Started | Aug 12 04:26:59 PM PDT 24 |
Finished | Aug 12 04:27:42 PM PDT 24 |
Peak memory | 146648 kb |
Host | smart-dcf63ad7-1f71-4df2-b3f1-5327ad48914f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=550811627 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 337.prim_prince_test.550811627 |
Directory | /workspace/337.prim_prince_test/latest |
Test location | /workspace/coverage/default/338.prim_prince_test.275927035 |
Short name | T122 |
Test name | |
Test status | |
Simulation time | 2257151708 ps |
CPU time | 36.24 seconds |
Started | Aug 12 04:26:39 PM PDT 24 |
Finished | Aug 12 04:27:23 PM PDT 24 |
Peak memory | 146180 kb |
Host | smart-db74fec1-6633-42c0-b6a2-7e218e281159 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=275927035 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 338.prim_prince_test.275927035 |
Directory | /workspace/338.prim_prince_test/latest |
Test location | /workspace/coverage/default/339.prim_prince_test.395268446 |
Short name | T307 |
Test name | |
Test status | |
Simulation time | 1495223238 ps |
CPU time | 26.04 seconds |
Started | Aug 12 04:23:51 PM PDT 24 |
Finished | Aug 12 04:24:23 PM PDT 24 |
Peak memory | 146564 kb |
Host | smart-13d07ceb-fbf8-4cf9-823c-06d82071068c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=395268446 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 339.prim_prince_test.395268446 |
Directory | /workspace/339.prim_prince_test/latest |
Test location | /workspace/coverage/default/34.prim_prince_test.3727182551 |
Short name | T139 |
Test name | |
Test status | |
Simulation time | 3266134150 ps |
CPU time | 56.03 seconds |
Started | Aug 12 04:23:02 PM PDT 24 |
Finished | Aug 12 04:24:11 PM PDT 24 |
Peak memory | 146828 kb |
Host | smart-19674019-e03c-4edc-90f3-1f42ff49cb5d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3727182551 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_prince_test.3727182551 |
Directory | /workspace/34.prim_prince_test/latest |
Test location | /workspace/coverage/default/340.prim_prince_test.3290366551 |
Short name | T417 |
Test name | |
Test status | |
Simulation time | 1051050277 ps |
CPU time | 17.39 seconds |
Started | Aug 12 04:26:31 PM PDT 24 |
Finished | Aug 12 04:26:53 PM PDT 24 |
Peak memory | 144708 kb |
Host | smart-625b1794-f258-4dc0-b0e2-2b5e28c6f277 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3290366551 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 340.prim_prince_test.3290366551 |
Directory | /workspace/340.prim_prince_test/latest |
Test location | /workspace/coverage/default/341.prim_prince_test.3461548931 |
Short name | T344 |
Test name | |
Test status | |
Simulation time | 852310931 ps |
CPU time | 15.4 seconds |
Started | Aug 12 04:23:47 PM PDT 24 |
Finished | Aug 12 04:24:06 PM PDT 24 |
Peak memory | 146620 kb |
Host | smart-e749717b-ee4d-42fc-ac99-5d4b2c8eafae |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3461548931 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 341.prim_prince_test.3461548931 |
Directory | /workspace/341.prim_prince_test/latest |
Test location | /workspace/coverage/default/342.prim_prince_test.4286589177 |
Short name | T75 |
Test name | |
Test status | |
Simulation time | 2855202988 ps |
CPU time | 49.08 seconds |
Started | Aug 12 04:23:49 PM PDT 24 |
Finished | Aug 12 04:24:49 PM PDT 24 |
Peak memory | 146660 kb |
Host | smart-800c3e52-27e4-47f2-97c2-6ab24a04ba67 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4286589177 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 342.prim_prince_test.4286589177 |
Directory | /workspace/342.prim_prince_test/latest |
Test location | /workspace/coverage/default/343.prim_prince_test.2896455281 |
Short name | T64 |
Test name | |
Test status | |
Simulation time | 3225423494 ps |
CPU time | 54.03 seconds |
Started | Aug 12 04:23:54 PM PDT 24 |
Finished | Aug 12 04:25:01 PM PDT 24 |
Peak memory | 146628 kb |
Host | smart-8e9cd0e9-3655-4616-9e29-9e7f4d3e43cb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2896455281 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 343.prim_prince_test.2896455281 |
Directory | /workspace/343.prim_prince_test/latest |
Test location | /workspace/coverage/default/344.prim_prince_test.3514314796 |
Short name | T251 |
Test name | |
Test status | |
Simulation time | 3086934965 ps |
CPU time | 51.97 seconds |
Started | Aug 12 04:25:18 PM PDT 24 |
Finished | Aug 12 04:26:21 PM PDT 24 |
Peak memory | 146620 kb |
Host | smart-929f65c6-b9b0-4e2d-b240-3459f78859ba |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3514314796 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 344.prim_prince_test.3514314796 |
Directory | /workspace/344.prim_prince_test/latest |
Test location | /workspace/coverage/default/345.prim_prince_test.1925746325 |
Short name | T494 |
Test name | |
Test status | |
Simulation time | 1363313609 ps |
CPU time | 22.21 seconds |
Started | Aug 12 04:26:59 PM PDT 24 |
Finished | Aug 12 04:27:25 PM PDT 24 |
Peak memory | 146572 kb |
Host | smart-c92549c9-dd61-4cd3-935a-70beabe6ba26 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1925746325 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 345.prim_prince_test.1925746325 |
Directory | /workspace/345.prim_prince_test/latest |
Test location | /workspace/coverage/default/346.prim_prince_test.3239802643 |
Short name | T478 |
Test name | |
Test status | |
Simulation time | 1604409029 ps |
CPU time | 27.03 seconds |
Started | Aug 12 04:24:26 PM PDT 24 |
Finished | Aug 12 04:24:59 PM PDT 24 |
Peak memory | 146596 kb |
Host | smart-a9eb2522-8e81-40eb-8980-265a27ec35a3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3239802643 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 346.prim_prince_test.3239802643 |
Directory | /workspace/346.prim_prince_test/latest |
Test location | /workspace/coverage/default/347.prim_prince_test.2391885003 |
Short name | T198 |
Test name | |
Test status | |
Simulation time | 3684397059 ps |
CPU time | 58.14 seconds |
Started | Aug 12 04:26:50 PM PDT 24 |
Finished | Aug 12 04:27:59 PM PDT 24 |
Peak memory | 146348 kb |
Host | smart-2ef113eb-c571-442a-9d8d-3235a9ea1414 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2391885003 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 347.prim_prince_test.2391885003 |
Directory | /workspace/347.prim_prince_test/latest |
Test location | /workspace/coverage/default/348.prim_prince_test.2589509344 |
Short name | T393 |
Test name | |
Test status | |
Simulation time | 1266803709 ps |
CPU time | 20.98 seconds |
Started | Aug 12 04:26:54 PM PDT 24 |
Finished | Aug 12 04:27:19 PM PDT 24 |
Peak memory | 146148 kb |
Host | smart-0ebb5cc0-d918-4dc3-99ec-01817901f5b2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2589509344 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 348.prim_prince_test.2589509344 |
Directory | /workspace/348.prim_prince_test/latest |
Test location | /workspace/coverage/default/349.prim_prince_test.1451336463 |
Short name | T384 |
Test name | |
Test status | |
Simulation time | 3629238708 ps |
CPU time | 58.08 seconds |
Started | Aug 12 04:26:48 PM PDT 24 |
Finished | Aug 12 04:27:56 PM PDT 24 |
Peak memory | 146448 kb |
Host | smart-bd9f08f9-133b-42e2-b24c-0b02ac2dd090 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1451336463 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 349.prim_prince_test.1451336463 |
Directory | /workspace/349.prim_prince_test/latest |
Test location | /workspace/coverage/default/35.prim_prince_test.4213651660 |
Short name | T207 |
Test name | |
Test status | |
Simulation time | 2245797520 ps |
CPU time | 37.43 seconds |
Started | Aug 12 04:21:15 PM PDT 24 |
Finished | Aug 12 04:22:00 PM PDT 24 |
Peak memory | 145416 kb |
Host | smart-e36fbd40-4d82-4acc-9431-9b0036eae62a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4213651660 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_prince_test.4213651660 |
Directory | /workspace/35.prim_prince_test/latest |
Test location | /workspace/coverage/default/350.prim_prince_test.2594594091 |
Short name | T322 |
Test name | |
Test status | |
Simulation time | 3422984353 ps |
CPU time | 59 seconds |
Started | Aug 12 04:23:49 PM PDT 24 |
Finished | Aug 12 04:25:03 PM PDT 24 |
Peak memory | 146696 kb |
Host | smart-583cbe35-6207-4f92-8657-f9d6d65aaa65 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2594594091 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 350.prim_prince_test.2594594091 |
Directory | /workspace/350.prim_prince_test/latest |
Test location | /workspace/coverage/default/351.prim_prince_test.1977509180 |
Short name | T368 |
Test name | |
Test status | |
Simulation time | 1934924670 ps |
CPU time | 31.64 seconds |
Started | Aug 12 04:26:50 PM PDT 24 |
Finished | Aug 12 04:27:28 PM PDT 24 |
Peak memory | 146284 kb |
Host | smart-933d1af9-e526-4e01-b1e6-30d67900ea07 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1977509180 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 351.prim_prince_test.1977509180 |
Directory | /workspace/351.prim_prince_test/latest |
Test location | /workspace/coverage/default/352.prim_prince_test.2528879925 |
Short name | T65 |
Test name | |
Test status | |
Simulation time | 859544022 ps |
CPU time | 14.58 seconds |
Started | Aug 12 04:24:39 PM PDT 24 |
Finished | Aug 12 04:24:57 PM PDT 24 |
Peak memory | 146556 kb |
Host | smart-75f8a74b-ab88-4dd7-8064-0560e533408f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2528879925 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 352.prim_prince_test.2528879925 |
Directory | /workspace/352.prim_prince_test/latest |
Test location | /workspace/coverage/default/353.prim_prince_test.4181966840 |
Short name | T160 |
Test name | |
Test status | |
Simulation time | 1790430942 ps |
CPU time | 30.47 seconds |
Started | Aug 12 04:23:50 PM PDT 24 |
Finished | Aug 12 04:24:28 PM PDT 24 |
Peak memory | 146632 kb |
Host | smart-daef7366-29d0-4d23-8562-efd0af87dd96 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4181966840 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 353.prim_prince_test.4181966840 |
Directory | /workspace/353.prim_prince_test/latest |
Test location | /workspace/coverage/default/354.prim_prince_test.1908244636 |
Short name | T479 |
Test name | |
Test status | |
Simulation time | 3699956342 ps |
CPU time | 59 seconds |
Started | Aug 12 04:26:45 PM PDT 24 |
Finished | Aug 12 04:27:54 PM PDT 24 |
Peak memory | 145652 kb |
Host | smart-afe26da9-f890-43fc-b3b6-87507edc11e2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1908244636 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 354.prim_prince_test.1908244636 |
Directory | /workspace/354.prim_prince_test/latest |
Test location | /workspace/coverage/default/355.prim_prince_test.1549714933 |
Short name | T78 |
Test name | |
Test status | |
Simulation time | 1948142189 ps |
CPU time | 32.42 seconds |
Started | Aug 12 04:25:08 PM PDT 24 |
Finished | Aug 12 04:25:47 PM PDT 24 |
Peak memory | 146588 kb |
Host | smart-ec2951a7-574f-459c-895d-c647a1152e5c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1549714933 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 355.prim_prince_test.1549714933 |
Directory | /workspace/355.prim_prince_test/latest |
Test location | /workspace/coverage/default/356.prim_prince_test.1341590720 |
Short name | T92 |
Test name | |
Test status | |
Simulation time | 1862972837 ps |
CPU time | 30.53 seconds |
Started | Aug 12 04:26:47 PM PDT 24 |
Finished | Aug 12 04:27:24 PM PDT 24 |
Peak memory | 146220 kb |
Host | smart-fd9b0f58-9730-4d1e-b160-1f123160b4fd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1341590720 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 356.prim_prince_test.1341590720 |
Directory | /workspace/356.prim_prince_test/latest |
Test location | /workspace/coverage/default/357.prim_prince_test.1642996759 |
Short name | T72 |
Test name | |
Test status | |
Simulation time | 1676769825 ps |
CPU time | 26.88 seconds |
Started | Aug 12 04:26:30 PM PDT 24 |
Finished | Aug 12 04:27:02 PM PDT 24 |
Peak memory | 145192 kb |
Host | smart-03b19f56-64c6-4708-9207-3281d169d208 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1642996759 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 357.prim_prince_test.1642996759 |
Directory | /workspace/357.prim_prince_test/latest |
Test location | /workspace/coverage/default/358.prim_prince_test.540558508 |
Short name | T372 |
Test name | |
Test status | |
Simulation time | 880432123 ps |
CPU time | 14.04 seconds |
Started | Aug 12 04:26:30 PM PDT 24 |
Finished | Aug 12 04:26:47 PM PDT 24 |
Peak memory | 145220 kb |
Host | smart-4a548461-b5db-45e4-8578-dc2006d9edbe |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=540558508 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 358.prim_prince_test.540558508 |
Directory | /workspace/358.prim_prince_test/latest |
Test location | /workspace/coverage/default/359.prim_prince_test.3648016004 |
Short name | T242 |
Test name | |
Test status | |
Simulation time | 2767857778 ps |
CPU time | 46.3 seconds |
Started | Aug 12 04:26:40 PM PDT 24 |
Finished | Aug 12 04:27:36 PM PDT 24 |
Peak memory | 146516 kb |
Host | smart-358ddc2d-a588-4299-b9b5-8124af08dad2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3648016004 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 359.prim_prince_test.3648016004 |
Directory | /workspace/359.prim_prince_test/latest |
Test location | /workspace/coverage/default/36.prim_prince_test.2274861826 |
Short name | T259 |
Test name | |
Test status | |
Simulation time | 1417621817 ps |
CPU time | 23.23 seconds |
Started | Aug 12 04:21:16 PM PDT 24 |
Finished | Aug 12 04:21:44 PM PDT 24 |
Peak memory | 146308 kb |
Host | smart-94d1bd57-2e3e-43f1-a95b-79bf9c05229b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2274861826 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_prince_test.2274861826 |
Directory | /workspace/36.prim_prince_test/latest |
Test location | /workspace/coverage/default/360.prim_prince_test.4294441758 |
Short name | T205 |
Test name | |
Test status | |
Simulation time | 2214207243 ps |
CPU time | 36.64 seconds |
Started | Aug 12 04:24:07 PM PDT 24 |
Finished | Aug 12 04:24:52 PM PDT 24 |
Peak memory | 146620 kb |
Host | smart-cb98f695-14be-4fd5-91ec-148bb3cdb4d7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4294441758 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 360.prim_prince_test.4294441758 |
Directory | /workspace/360.prim_prince_test/latest |
Test location | /workspace/coverage/default/361.prim_prince_test.2478542164 |
Short name | T443 |
Test name | |
Test status | |
Simulation time | 2427365772 ps |
CPU time | 40.11 seconds |
Started | Aug 12 04:26:26 PM PDT 24 |
Finished | Aug 12 04:27:14 PM PDT 24 |
Peak memory | 146268 kb |
Host | smart-f9cc118c-674a-4c50-a7c0-46790436db30 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2478542164 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 361.prim_prince_test.2478542164 |
Directory | /workspace/361.prim_prince_test/latest |
Test location | /workspace/coverage/default/362.prim_prince_test.1928422093 |
Short name | T56 |
Test name | |
Test status | |
Simulation time | 1602064597 ps |
CPU time | 25.78 seconds |
Started | Aug 12 04:26:55 PM PDT 24 |
Finished | Aug 12 04:27:25 PM PDT 24 |
Peak memory | 146148 kb |
Host | smart-f4d863a5-1414-4c11-9a4d-e943beb56b25 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1928422093 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 362.prim_prince_test.1928422093 |
Directory | /workspace/362.prim_prince_test/latest |
Test location | /workspace/coverage/default/363.prim_prince_test.1796243658 |
Short name | T462 |
Test name | |
Test status | |
Simulation time | 1985689061 ps |
CPU time | 34.28 seconds |
Started | Aug 12 04:24:01 PM PDT 24 |
Finished | Aug 12 04:24:44 PM PDT 24 |
Peak memory | 146656 kb |
Host | smart-2c40072c-f3f2-468a-93b0-932d65bb49e1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1796243658 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 363.prim_prince_test.1796243658 |
Directory | /workspace/363.prim_prince_test/latest |
Test location | /workspace/coverage/default/364.prim_prince_test.130970431 |
Short name | T21 |
Test name | |
Test status | |
Simulation time | 2231959927 ps |
CPU time | 37.45 seconds |
Started | Aug 12 04:26:29 PM PDT 24 |
Finished | Aug 12 04:27:14 PM PDT 24 |
Peak memory | 146628 kb |
Host | smart-8fabcecf-0b5f-439e-82eb-61ee5215ffea |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=130970431 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 364.prim_prince_test.130970431 |
Directory | /workspace/364.prim_prince_test/latest |
Test location | /workspace/coverage/default/365.prim_prince_test.2964685457 |
Short name | T318 |
Test name | |
Test status | |
Simulation time | 1190596441 ps |
CPU time | 20.41 seconds |
Started | Aug 12 04:26:39 PM PDT 24 |
Finished | Aug 12 04:27:04 PM PDT 24 |
Peak memory | 146452 kb |
Host | smart-37a859af-adfa-4bdb-976b-66b443c8d3ab |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2964685457 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 365.prim_prince_test.2964685457 |
Directory | /workspace/365.prim_prince_test/latest |
Test location | /workspace/coverage/default/366.prim_prince_test.4992522 |
Short name | T382 |
Test name | |
Test status | |
Simulation time | 3220571938 ps |
CPU time | 53.3 seconds |
Started | Aug 12 04:26:34 PM PDT 24 |
Finished | Aug 12 04:27:39 PM PDT 24 |
Peak memory | 146300 kb |
Host | smart-99fc0c36-1681-4cc0-a5de-6c90b7689c2a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4992522 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 366.prim_prince_test.4992522 |
Directory | /workspace/366.prim_prince_test/latest |
Test location | /workspace/coverage/default/367.prim_prince_test.3755647067 |
Short name | T224 |
Test name | |
Test status | |
Simulation time | 3563018332 ps |
CPU time | 56.65 seconds |
Started | Aug 12 04:26:24 PM PDT 24 |
Finished | Aug 12 04:27:31 PM PDT 24 |
Peak memory | 146164 kb |
Host | smart-1755ec17-5228-4bec-b46b-2304163227e3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3755647067 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 367.prim_prince_test.3755647067 |
Directory | /workspace/367.prim_prince_test/latest |
Test location | /workspace/coverage/default/368.prim_prince_test.2028760351 |
Short name | T257 |
Test name | |
Test status | |
Simulation time | 2228456829 ps |
CPU time | 36.99 seconds |
Started | Aug 12 04:26:39 PM PDT 24 |
Finished | Aug 12 04:27:24 PM PDT 24 |
Peak memory | 146516 kb |
Host | smart-94c3248b-1a6e-4c18-87bb-29e223d80eab |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2028760351 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 368.prim_prince_test.2028760351 |
Directory | /workspace/368.prim_prince_test/latest |
Test location | /workspace/coverage/default/369.prim_prince_test.2793882726 |
Short name | T466 |
Test name | |
Test status | |
Simulation time | 1190969112 ps |
CPU time | 19.78 seconds |
Started | Aug 12 04:26:26 PM PDT 24 |
Finished | Aug 12 04:26:50 PM PDT 24 |
Peak memory | 146228 kb |
Host | smart-f05a9bf1-4017-4883-961a-303b005d0633 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2793882726 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 369.prim_prince_test.2793882726 |
Directory | /workspace/369.prim_prince_test/latest |
Test location | /workspace/coverage/default/37.prim_prince_test.1655474178 |
Short name | T447 |
Test name | |
Test status | |
Simulation time | 2426357471 ps |
CPU time | 40.08 seconds |
Started | Aug 12 04:21:17 PM PDT 24 |
Finished | Aug 12 04:22:05 PM PDT 24 |
Peak memory | 146144 kb |
Host | smart-97afb4b1-6e3a-434f-931e-d1dcf78b7262 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1655474178 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_prince_test.1655474178 |
Directory | /workspace/37.prim_prince_test/latest |
Test location | /workspace/coverage/default/370.prim_prince_test.3894282264 |
Short name | T483 |
Test name | |
Test status | |
Simulation time | 2704641358 ps |
CPU time | 45.75 seconds |
Started | Aug 12 04:23:58 PM PDT 24 |
Finished | Aug 12 04:24:53 PM PDT 24 |
Peak memory | 146620 kb |
Host | smart-a2936079-df69-4431-a6ac-34148a29506f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3894282264 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 370.prim_prince_test.3894282264 |
Directory | /workspace/370.prim_prince_test/latest |
Test location | /workspace/coverage/default/371.prim_prince_test.1898112893 |
Short name | T385 |
Test name | |
Test status | |
Simulation time | 3332580894 ps |
CPU time | 52.49 seconds |
Started | Aug 12 04:27:50 PM PDT 24 |
Finished | Aug 12 04:28:51 PM PDT 24 |
Peak memory | 146628 kb |
Host | smart-32fd8f54-ca48-423b-8469-9e4563896657 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1898112893 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 371.prim_prince_test.1898112893 |
Directory | /workspace/371.prim_prince_test/latest |
Test location | /workspace/coverage/default/372.prim_prince_test.2458136119 |
Short name | T336 |
Test name | |
Test status | |
Simulation time | 2137352692 ps |
CPU time | 36.31 seconds |
Started | Aug 12 04:24:06 PM PDT 24 |
Finished | Aug 12 04:24:51 PM PDT 24 |
Peak memory | 146596 kb |
Host | smart-c345192e-d687-408b-b0ab-96a0b7fe38cf |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2458136119 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 372.prim_prince_test.2458136119 |
Directory | /workspace/372.prim_prince_test/latest |
Test location | /workspace/coverage/default/373.prim_prince_test.808583936 |
Short name | T248 |
Test name | |
Test status | |
Simulation time | 3121387184 ps |
CPU time | 52.97 seconds |
Started | Aug 12 04:24:05 PM PDT 24 |
Finished | Aug 12 04:25:10 PM PDT 24 |
Peak memory | 146664 kb |
Host | smart-1bb6674f-5ded-4bf9-9144-415be27c6c8b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=808583936 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 373.prim_prince_test.808583936 |
Directory | /workspace/373.prim_prince_test/latest |
Test location | /workspace/coverage/default/374.prim_prince_test.701120206 |
Short name | T367 |
Test name | |
Test status | |
Simulation time | 3310204383 ps |
CPU time | 57.1 seconds |
Started | Aug 12 04:24:58 PM PDT 24 |
Finished | Aug 12 04:26:09 PM PDT 24 |
Peak memory | 146652 kb |
Host | smart-90038715-f135-4cdd-a73f-b48755318702 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=701120206 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 374.prim_prince_test.701120206 |
Directory | /workspace/374.prim_prince_test/latest |
Test location | /workspace/coverage/default/375.prim_prince_test.930785091 |
Short name | T58 |
Test name | |
Test status | |
Simulation time | 865565217 ps |
CPU time | 15.68 seconds |
Started | Aug 12 04:25:31 PM PDT 24 |
Finished | Aug 12 04:25:50 PM PDT 24 |
Peak memory | 146572 kb |
Host | smart-f4a31ab3-9390-4a94-88e8-08f4e85350bf |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=930785091 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 375.prim_prince_test.930785091 |
Directory | /workspace/375.prim_prince_test/latest |
Test location | /workspace/coverage/default/376.prim_prince_test.1786829241 |
Short name | T355 |
Test name | |
Test status | |
Simulation time | 826169977 ps |
CPU time | 13.25 seconds |
Started | Aug 12 04:27:43 PM PDT 24 |
Finished | Aug 12 04:27:59 PM PDT 24 |
Peak memory | 146468 kb |
Host | smart-224f0bff-a0e1-4868-859c-38db034789e8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1786829241 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 376.prim_prince_test.1786829241 |
Directory | /workspace/376.prim_prince_test/latest |
Test location | /workspace/coverage/default/377.prim_prince_test.2647195613 |
Short name | T81 |
Test name | |
Test status | |
Simulation time | 1009691393 ps |
CPU time | 16.08 seconds |
Started | Aug 12 04:27:35 PM PDT 24 |
Finished | Aug 12 04:27:54 PM PDT 24 |
Peak memory | 145596 kb |
Host | smart-804c3981-2c78-4c45-966a-b2b6ff2f1a37 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2647195613 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 377.prim_prince_test.2647195613 |
Directory | /workspace/377.prim_prince_test/latest |
Test location | /workspace/coverage/default/378.prim_prince_test.2565659434 |
Short name | T304 |
Test name | |
Test status | |
Simulation time | 3316480741 ps |
CPU time | 54.92 seconds |
Started | Aug 12 04:24:38 PM PDT 24 |
Finished | Aug 12 04:25:45 PM PDT 24 |
Peak memory | 146628 kb |
Host | smart-8f913852-c32e-4d3f-aa03-677dd55b5671 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2565659434 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 378.prim_prince_test.2565659434 |
Directory | /workspace/378.prim_prince_test/latest |
Test location | /workspace/coverage/default/379.prim_prince_test.1638336325 |
Short name | T269 |
Test name | |
Test status | |
Simulation time | 3106506418 ps |
CPU time | 49.09 seconds |
Started | Aug 12 04:27:55 PM PDT 24 |
Finished | Aug 12 04:28:53 PM PDT 24 |
Peak memory | 146632 kb |
Host | smart-7081a17f-eafa-4937-abed-6574b63f07eb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1638336325 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 379.prim_prince_test.1638336325 |
Directory | /workspace/379.prim_prince_test/latest |
Test location | /workspace/coverage/default/38.prim_prince_test.3045078675 |
Short name | T271 |
Test name | |
Test status | |
Simulation time | 1769544292 ps |
CPU time | 29.7 seconds |
Started | Aug 12 04:22:16 PM PDT 24 |
Finished | Aug 12 04:22:52 PM PDT 24 |
Peak memory | 144292 kb |
Host | smart-054bd8c1-db08-45a1-9afa-ad2036f3c159 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3045078675 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_prince_test.3045078675 |
Directory | /workspace/38.prim_prince_test/latest |
Test location | /workspace/coverage/default/380.prim_prince_test.3410023829 |
Short name | T424 |
Test name | |
Test status | |
Simulation time | 2091429411 ps |
CPU time | 33.01 seconds |
Started | Aug 12 04:27:43 PM PDT 24 |
Finished | Aug 12 04:28:21 PM PDT 24 |
Peak memory | 146272 kb |
Host | smart-54a79088-5581-48fc-9126-ce7cdf503fac |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3410023829 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 380.prim_prince_test.3410023829 |
Directory | /workspace/380.prim_prince_test/latest |
Test location | /workspace/coverage/default/381.prim_prince_test.675875936 |
Short name | T300 |
Test name | |
Test status | |
Simulation time | 2171687154 ps |
CPU time | 36.27 seconds |
Started | Aug 12 04:24:38 PM PDT 24 |
Finished | Aug 12 04:25:23 PM PDT 24 |
Peak memory | 146636 kb |
Host | smart-02c525ff-c7d3-4252-a67e-96f738af0163 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=675875936 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 381.prim_prince_test.675875936 |
Directory | /workspace/381.prim_prince_test/latest |
Test location | /workspace/coverage/default/382.prim_prince_test.1441233239 |
Short name | T223 |
Test name | |
Test status | |
Simulation time | 1517052821 ps |
CPU time | 25.8 seconds |
Started | Aug 12 04:25:16 PM PDT 24 |
Finished | Aug 12 04:25:47 PM PDT 24 |
Peak memory | 146588 kb |
Host | smart-1e1cd524-1543-4c78-8b28-6b3b7ee1faf6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1441233239 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 382.prim_prince_test.1441233239 |
Directory | /workspace/382.prim_prince_test/latest |
Test location | /workspace/coverage/default/383.prim_prince_test.3016748156 |
Short name | T255 |
Test name | |
Test status | |
Simulation time | 3130049533 ps |
CPU time | 52.14 seconds |
Started | Aug 12 04:24:26 PM PDT 24 |
Finished | Aug 12 04:25:30 PM PDT 24 |
Peak memory | 146628 kb |
Host | smart-d0310e8e-64f8-4a98-92c9-338df8d63876 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3016748156 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 383.prim_prince_test.3016748156 |
Directory | /workspace/383.prim_prince_test/latest |
Test location | /workspace/coverage/default/384.prim_prince_test.3738435606 |
Short name | T369 |
Test name | |
Test status | |
Simulation time | 1036207527 ps |
CPU time | 17.95 seconds |
Started | Aug 12 04:25:17 PM PDT 24 |
Finished | Aug 12 04:25:39 PM PDT 24 |
Peak memory | 146556 kb |
Host | smart-96357c33-8716-4f0f-93c7-e7d814e3ebdb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3738435606 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 384.prim_prince_test.3738435606 |
Directory | /workspace/384.prim_prince_test/latest |
Test location | /workspace/coverage/default/385.prim_prince_test.251172904 |
Short name | T428 |
Test name | |
Test status | |
Simulation time | 1938716564 ps |
CPU time | 32.21 seconds |
Started | Aug 12 04:26:25 PM PDT 24 |
Finished | Aug 12 04:27:05 PM PDT 24 |
Peak memory | 146140 kb |
Host | smart-bd7a02c9-5717-4cac-b2bb-d0190ddd3b8e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=251172904 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 385.prim_prince_test.251172904 |
Directory | /workspace/385.prim_prince_test/latest |
Test location | /workspace/coverage/default/386.prim_prince_test.4259997153 |
Short name | T1 |
Test name | |
Test status | |
Simulation time | 2553083774 ps |
CPU time | 41.84 seconds |
Started | Aug 12 04:26:00 PM PDT 24 |
Finished | Aug 12 04:26:51 PM PDT 24 |
Peak memory | 144208 kb |
Host | smart-6be0f4a4-db8b-415e-8d49-1493dcf8c6b9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4259997153 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 386.prim_prince_test.4259997153 |
Directory | /workspace/386.prim_prince_test/latest |
Test location | /workspace/coverage/default/387.prim_prince_test.3751514363 |
Short name | T212 |
Test name | |
Test status | |
Simulation time | 960266189 ps |
CPU time | 17.04 seconds |
Started | Aug 12 04:25:01 PM PDT 24 |
Finished | Aug 12 04:25:23 PM PDT 24 |
Peak memory | 146620 kb |
Host | smart-f7157fac-6266-4b49-832a-5bf92a8fba3e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3751514363 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 387.prim_prince_test.3751514363 |
Directory | /workspace/387.prim_prince_test/latest |
Test location | /workspace/coverage/default/388.prim_prince_test.2987932357 |
Short name | T277 |
Test name | |
Test status | |
Simulation time | 2484637427 ps |
CPU time | 41.91 seconds |
Started | Aug 12 04:24:25 PM PDT 24 |
Finished | Aug 12 04:25:16 PM PDT 24 |
Peak memory | 146620 kb |
Host | smart-e331e1ce-77cf-473b-9468-7f627a4bf5c6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2987932357 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 388.prim_prince_test.2987932357 |
Directory | /workspace/388.prim_prince_test/latest |
Test location | /workspace/coverage/default/389.prim_prince_test.241226857 |
Short name | T233 |
Test name | |
Test status | |
Simulation time | 2893015667 ps |
CPU time | 48.58 seconds |
Started | Aug 12 04:25:17 PM PDT 24 |
Finished | Aug 12 04:26:16 PM PDT 24 |
Peak memory | 146628 kb |
Host | smart-205db1e1-efe2-4a69-afcf-43110592afbb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=241226857 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 389.prim_prince_test.241226857 |
Directory | /workspace/389.prim_prince_test/latest |
Test location | /workspace/coverage/default/39.prim_prince_test.2460038761 |
Short name | T13 |
Test name | |
Test status | |
Simulation time | 1729057243 ps |
CPU time | 28.69 seconds |
Started | Aug 12 04:21:16 PM PDT 24 |
Finished | Aug 12 04:21:51 PM PDT 24 |
Peak memory | 144936 kb |
Host | smart-4c9684e5-f3b3-4bbe-af9e-a0fc6fe0a01c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2460038761 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_prince_test.2460038761 |
Directory | /workspace/39.prim_prince_test/latest |
Test location | /workspace/coverage/default/390.prim_prince_test.1077140156 |
Short name | T234 |
Test name | |
Test status | |
Simulation time | 2603910576 ps |
CPU time | 43.99 seconds |
Started | Aug 12 04:26:10 PM PDT 24 |
Finished | Aug 12 04:27:04 PM PDT 24 |
Peak memory | 146180 kb |
Host | smart-ca4eab6c-adbf-428c-abcc-cd8e3f8da5dc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1077140156 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 390.prim_prince_test.1077140156 |
Directory | /workspace/390.prim_prince_test/latest |
Test location | /workspace/coverage/default/391.prim_prince_test.3447662083 |
Short name | T445 |
Test name | |
Test status | |
Simulation time | 1198509186 ps |
CPU time | 20.4 seconds |
Started | Aug 12 04:26:09 PM PDT 24 |
Finished | Aug 12 04:26:35 PM PDT 24 |
Peak memory | 146116 kb |
Host | smart-0b7d8b95-7192-4eed-b449-7cd763838030 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3447662083 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 391.prim_prince_test.3447662083 |
Directory | /workspace/391.prim_prince_test/latest |
Test location | /workspace/coverage/default/392.prim_prince_test.125253330 |
Short name | T459 |
Test name | |
Test status | |
Simulation time | 1355941231 ps |
CPU time | 21.86 seconds |
Started | Aug 12 04:26:14 PM PDT 24 |
Finished | Aug 12 04:26:40 PM PDT 24 |
Peak memory | 145144 kb |
Host | smart-9bf005fc-1253-481f-bfc7-8d6ff1ec5cee |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=125253330 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 392.prim_prince_test.125253330 |
Directory | /workspace/392.prim_prince_test/latest |
Test location | /workspace/coverage/default/393.prim_prince_test.3189845847 |
Short name | T474 |
Test name | |
Test status | |
Simulation time | 3015074938 ps |
CPU time | 49.77 seconds |
Started | Aug 12 04:26:09 PM PDT 24 |
Finished | Aug 12 04:27:10 PM PDT 24 |
Peak memory | 146180 kb |
Host | smart-9d76b866-677d-4a19-afcb-84e66e6e2940 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3189845847 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 393.prim_prince_test.3189845847 |
Directory | /workspace/393.prim_prince_test/latest |
Test location | /workspace/coverage/default/394.prim_prince_test.2334670980 |
Short name | T256 |
Test name | |
Test status | |
Simulation time | 2564821143 ps |
CPU time | 42.79 seconds |
Started | Aug 12 04:26:08 PM PDT 24 |
Finished | Aug 12 04:27:00 PM PDT 24 |
Peak memory | 146180 kb |
Host | smart-51b75bab-8df5-4752-8efe-ed1a03cc07fc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2334670980 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 394.prim_prince_test.2334670980 |
Directory | /workspace/394.prim_prince_test/latest |
Test location | /workspace/coverage/default/395.prim_prince_test.2770340184 |
Short name | T153 |
Test name | |
Test status | |
Simulation time | 2077937243 ps |
CPU time | 34.29 seconds |
Started | Aug 12 04:26:09 PM PDT 24 |
Finished | Aug 12 04:26:51 PM PDT 24 |
Peak memory | 146116 kb |
Host | smart-6ac2d1be-19c0-46d7-966e-6bfd7278b3a2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2770340184 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 395.prim_prince_test.2770340184 |
Directory | /workspace/395.prim_prince_test/latest |
Test location | /workspace/coverage/default/396.prim_prince_test.2354479710 |
Short name | T471 |
Test name | |
Test status | |
Simulation time | 1973746843 ps |
CPU time | 32.14 seconds |
Started | Aug 12 04:26:08 PM PDT 24 |
Finished | Aug 12 04:26:47 PM PDT 24 |
Peak memory | 146116 kb |
Host | smart-33113649-eda6-4c93-8811-1afad87f2dbb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2354479710 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 396.prim_prince_test.2354479710 |
Directory | /workspace/396.prim_prince_test/latest |
Test location | /workspace/coverage/default/397.prim_prince_test.3756158464 |
Short name | T199 |
Test name | |
Test status | |
Simulation time | 1118135259 ps |
CPU time | 18.34 seconds |
Started | Aug 12 04:26:23 PM PDT 24 |
Finished | Aug 12 04:26:45 PM PDT 24 |
Peak memory | 146032 kb |
Host | smart-1cdcac01-2ef3-4434-a40f-3ba69b4685e0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3756158464 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 397.prim_prince_test.3756158464 |
Directory | /workspace/397.prim_prince_test/latest |
Test location | /workspace/coverage/default/398.prim_prince_test.4294361447 |
Short name | T268 |
Test name | |
Test status | |
Simulation time | 858540864 ps |
CPU time | 14.2 seconds |
Started | Aug 12 04:26:00 PM PDT 24 |
Finished | Aug 12 04:26:18 PM PDT 24 |
Peak memory | 144828 kb |
Host | smart-cd8ffed8-a65c-4a85-a95c-5440ae32424e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4294361447 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 398.prim_prince_test.4294361447 |
Directory | /workspace/398.prim_prince_test/latest |
Test location | /workspace/coverage/default/399.prim_prince_test.807575941 |
Short name | T473 |
Test name | |
Test status | |
Simulation time | 2011967915 ps |
CPU time | 33.48 seconds |
Started | Aug 12 04:25:59 PM PDT 24 |
Finished | Aug 12 04:26:39 PM PDT 24 |
Peak memory | 146552 kb |
Host | smart-8f428667-6268-4c30-9041-b734e354418b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=807575941 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 399.prim_prince_test.807575941 |
Directory | /workspace/399.prim_prince_test/latest |
Test location | /workspace/coverage/default/4.prim_prince_test.2019426350 |
Short name | T410 |
Test name | |
Test status | |
Simulation time | 1734487802 ps |
CPU time | 29.24 seconds |
Started | Aug 12 04:21:08 PM PDT 24 |
Finished | Aug 12 04:21:43 PM PDT 24 |
Peak memory | 146364 kb |
Host | smart-b852c4f9-5a23-4a8e-bcd1-0a27e1431121 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2019426350 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_prince_test.2019426350 |
Directory | /workspace/4.prim_prince_test/latest |
Test location | /workspace/coverage/default/40.prim_prince_test.1142161404 |
Short name | T67 |
Test name | |
Test status | |
Simulation time | 1381816975 ps |
CPU time | 23 seconds |
Started | Aug 12 04:21:16 PM PDT 24 |
Finished | Aug 12 04:21:43 PM PDT 24 |
Peak memory | 146284 kb |
Host | smart-451a1288-6bf6-45bc-84ef-bb22f1ecce3d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1142161404 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_prince_test.1142161404 |
Directory | /workspace/40.prim_prince_test/latest |
Test location | /workspace/coverage/default/400.prim_prince_test.680269592 |
Short name | T273 |
Test name | |
Test status | |
Simulation time | 2427861111 ps |
CPU time | 38.39 seconds |
Started | Aug 12 04:26:29 PM PDT 24 |
Finished | Aug 12 04:27:15 PM PDT 24 |
Peak memory | 146084 kb |
Host | smart-7e292ed5-b379-498c-9671-756765254018 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=680269592 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 400.prim_prince_test.680269592 |
Directory | /workspace/400.prim_prince_test/latest |
Test location | /workspace/coverage/default/401.prim_prince_test.3228952121 |
Short name | T146 |
Test name | |
Test status | |
Simulation time | 2767698856 ps |
CPU time | 47.49 seconds |
Started | Aug 12 04:24:30 PM PDT 24 |
Finished | Aug 12 04:25:29 PM PDT 24 |
Peak memory | 146668 kb |
Host | smart-9e1fe1db-b065-4ee1-b6ce-ff6b9833dc79 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3228952121 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 401.prim_prince_test.3228952121 |
Directory | /workspace/401.prim_prince_test/latest |
Test location | /workspace/coverage/default/402.prim_prince_test.3180478833 |
Short name | T446 |
Test name | |
Test status | |
Simulation time | 2091653897 ps |
CPU time | 34.22 seconds |
Started | Aug 12 04:26:26 PM PDT 24 |
Finished | Aug 12 04:27:08 PM PDT 24 |
Peak memory | 145456 kb |
Host | smart-3bb7fedb-1b58-47be-9d74-57fed927fcb7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3180478833 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 402.prim_prince_test.3180478833 |
Directory | /workspace/402.prim_prince_test/latest |
Test location | /workspace/coverage/default/403.prim_prince_test.517470582 |
Short name | T328 |
Test name | |
Test status | |
Simulation time | 1519292144 ps |
CPU time | 25.05 seconds |
Started | Aug 12 04:26:23 PM PDT 24 |
Finished | Aug 12 04:26:54 PM PDT 24 |
Peak memory | 146116 kb |
Host | smart-78caaebf-e8b4-4f1c-8442-e784fac9d546 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=517470582 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 403.prim_prince_test.517470582 |
Directory | /workspace/403.prim_prince_test/latest |
Test location | /workspace/coverage/default/404.prim_prince_test.356805529 |
Short name | T468 |
Test name | |
Test status | |
Simulation time | 3634389351 ps |
CPU time | 58.32 seconds |
Started | Aug 12 04:26:22 PM PDT 24 |
Finished | Aug 12 04:27:32 PM PDT 24 |
Peak memory | 146180 kb |
Host | smart-c435edc5-7e71-4cda-a82b-f93231815bf9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=356805529 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 404.prim_prince_test.356805529 |
Directory | /workspace/404.prim_prince_test/latest |
Test location | /workspace/coverage/default/405.prim_prince_test.1882726149 |
Short name | T341 |
Test name | |
Test status | |
Simulation time | 1991229678 ps |
CPU time | 31.7 seconds |
Started | Aug 12 04:26:29 PM PDT 24 |
Finished | Aug 12 04:27:07 PM PDT 24 |
Peak memory | 146028 kb |
Host | smart-16f0de90-e2c2-4f11-988f-e33bfb2f8d37 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1882726149 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 405.prim_prince_test.1882726149 |
Directory | /workspace/405.prim_prince_test/latest |
Test location | /workspace/coverage/default/406.prim_prince_test.3866435033 |
Short name | T411 |
Test name | |
Test status | |
Simulation time | 921667681 ps |
CPU time | 15.55 seconds |
Started | Aug 12 04:26:00 PM PDT 24 |
Finished | Aug 12 04:26:19 PM PDT 24 |
Peak memory | 144476 kb |
Host | smart-8022f9b9-8948-4950-8c07-c61a2add471b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3866435033 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 406.prim_prince_test.3866435033 |
Directory | /workspace/406.prim_prince_test/latest |
Test location | /workspace/coverage/default/407.prim_prince_test.4252437539 |
Short name | T359 |
Test name | |
Test status | |
Simulation time | 1124654634 ps |
CPU time | 18.18 seconds |
Started | Aug 12 04:26:22 PM PDT 24 |
Finished | Aug 12 04:26:44 PM PDT 24 |
Peak memory | 146120 kb |
Host | smart-52b94284-f4c0-43d6-830e-bf1d8edc054f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4252437539 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 407.prim_prince_test.4252437539 |
Directory | /workspace/407.prim_prince_test/latest |
Test location | /workspace/coverage/default/408.prim_prince_test.3536171241 |
Short name | T401 |
Test name | |
Test status | |
Simulation time | 3261498159 ps |
CPU time | 54.66 seconds |
Started | Aug 12 04:26:00 PM PDT 24 |
Finished | Aug 12 04:27:06 PM PDT 24 |
Peak memory | 146612 kb |
Host | smart-039c1a1e-b28e-46ad-bb51-2e2a4f96f5fd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3536171241 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 408.prim_prince_test.3536171241 |
Directory | /workspace/408.prim_prince_test/latest |
Test location | /workspace/coverage/default/409.prim_prince_test.28238141 |
Short name | T216 |
Test name | |
Test status | |
Simulation time | 1638784362 ps |
CPU time | 27.5 seconds |
Started | Aug 12 04:26:00 PM PDT 24 |
Finished | Aug 12 04:26:33 PM PDT 24 |
Peak memory | 146548 kb |
Host | smart-eea63e78-ce28-4c05-a2ff-5325ea6b8226 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=28238141 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 409.prim_prince_test.28238141 |
Directory | /workspace/409.prim_prince_test/latest |
Test location | /workspace/coverage/default/41.prim_prince_test.2396886647 |
Short name | T33 |
Test name | |
Test status | |
Simulation time | 1199109509 ps |
CPU time | 19.47 seconds |
Started | Aug 12 04:21:15 PM PDT 24 |
Finished | Aug 12 04:21:38 PM PDT 24 |
Peak memory | 145836 kb |
Host | smart-9a1e3c77-1881-4057-98b4-c15bb383d1e7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2396886647 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_prince_test.2396886647 |
Directory | /workspace/41.prim_prince_test/latest |
Test location | /workspace/coverage/default/410.prim_prince_test.143135319 |
Short name | T175 |
Test name | |
Test status | |
Simulation time | 2709230972 ps |
CPU time | 44.23 seconds |
Started | Aug 12 04:26:00 PM PDT 24 |
Finished | Aug 12 04:26:53 PM PDT 24 |
Peak memory | 144268 kb |
Host | smart-de1d9213-8198-4107-a3c4-e3d39aa0d673 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=143135319 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 410.prim_prince_test.143135319 |
Directory | /workspace/410.prim_prince_test/latest |
Test location | /workspace/coverage/default/411.prim_prince_test.2119414414 |
Short name | T378 |
Test name | |
Test status | |
Simulation time | 1095574824 ps |
CPU time | 17.85 seconds |
Started | Aug 12 04:26:13 PM PDT 24 |
Finished | Aug 12 04:26:35 PM PDT 24 |
Peak memory | 145064 kb |
Host | smart-9dd50a96-2ca2-4457-b488-63a973c70a62 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2119414414 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 411.prim_prince_test.2119414414 |
Directory | /workspace/411.prim_prince_test/latest |
Test location | /workspace/coverage/default/412.prim_prince_test.281995953 |
Short name | T150 |
Test name | |
Test status | |
Simulation time | 3648613043 ps |
CPU time | 61.26 seconds |
Started | Aug 12 04:24:32 PM PDT 24 |
Finished | Aug 12 04:25:46 PM PDT 24 |
Peak memory | 146696 kb |
Host | smart-4841ce26-0cc7-47c7-ac09-37755be98ebf |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=281995953 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 412.prim_prince_test.281995953 |
Directory | /workspace/412.prim_prince_test/latest |
Test location | /workspace/coverage/default/413.prim_prince_test.1982303859 |
Short name | T61 |
Test name | |
Test status | |
Simulation time | 1292463246 ps |
CPU time | 21.06 seconds |
Started | Aug 12 04:26:23 PM PDT 24 |
Finished | Aug 12 04:26:48 PM PDT 24 |
Peak memory | 146044 kb |
Host | smart-55629418-0b1d-43ce-be2b-592a55002fb7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1982303859 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 413.prim_prince_test.1982303859 |
Directory | /workspace/413.prim_prince_test/latest |
Test location | /workspace/coverage/default/414.prim_prince_test.3081012076 |
Short name | T457 |
Test name | |
Test status | |
Simulation time | 1319911684 ps |
CPU time | 21.14 seconds |
Started | Aug 12 04:26:14 PM PDT 24 |
Finished | Aug 12 04:26:39 PM PDT 24 |
Peak memory | 146028 kb |
Host | smart-0c76a5eb-004f-4e48-879c-f5f38e50efcc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3081012076 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 414.prim_prince_test.3081012076 |
Directory | /workspace/414.prim_prince_test/latest |
Test location | /workspace/coverage/default/415.prim_prince_test.1706018307 |
Short name | T97 |
Test name | |
Test status | |
Simulation time | 2054953981 ps |
CPU time | 32.97 seconds |
Started | Aug 12 04:26:24 PM PDT 24 |
Finished | Aug 12 04:27:03 PM PDT 24 |
Peak memory | 146132 kb |
Host | smart-6f215362-f413-4b7f-b158-e0a0d22c983d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1706018307 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 415.prim_prince_test.1706018307 |
Directory | /workspace/415.prim_prince_test/latest |
Test location | /workspace/coverage/default/416.prim_prince_test.3955627870 |
Short name | T380 |
Test name | |
Test status | |
Simulation time | 1064576741 ps |
CPU time | 18.01 seconds |
Started | Aug 12 04:26:00 PM PDT 24 |
Finished | Aug 12 04:26:22 PM PDT 24 |
Peak memory | 146548 kb |
Host | smart-a0729df3-89a2-423e-bf02-cdffe9f30e6a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3955627870 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 416.prim_prince_test.3955627870 |
Directory | /workspace/416.prim_prince_test/latest |
Test location | /workspace/coverage/default/417.prim_prince_test.1039323764 |
Short name | T200 |
Test name | |
Test status | |
Simulation time | 2725565981 ps |
CPU time | 44.79 seconds |
Started | Aug 12 04:26:00 PM PDT 24 |
Finished | Aug 12 04:26:54 PM PDT 24 |
Peak memory | 144376 kb |
Host | smart-e467dbca-0f2a-4342-a269-030646f92937 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1039323764 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 417.prim_prince_test.1039323764 |
Directory | /workspace/417.prim_prince_test/latest |
Test location | /workspace/coverage/default/418.prim_prince_test.4038887049 |
Short name | T351 |
Test name | |
Test status | |
Simulation time | 1052229453 ps |
CPU time | 17.11 seconds |
Started | Aug 12 04:25:46 PM PDT 24 |
Finished | Aug 12 04:26:07 PM PDT 24 |
Peak memory | 144316 kb |
Host | smart-b1f5db67-d61f-4373-8db7-ed680c8bdbb4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4038887049 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 418.prim_prince_test.4038887049 |
Directory | /workspace/418.prim_prince_test/latest |
Test location | /workspace/coverage/default/419.prim_prince_test.699883886 |
Short name | T15 |
Test name | |
Test status | |
Simulation time | 2133440907 ps |
CPU time | 34.35 seconds |
Started | Aug 12 04:26:27 PM PDT 24 |
Finished | Aug 12 04:27:08 PM PDT 24 |
Peak memory | 146200 kb |
Host | smart-1c3ba897-9be5-4d55-8771-bfcf5d95e3cb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=699883886 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 419.prim_prince_test.699883886 |
Directory | /workspace/419.prim_prince_test/latest |
Test location | /workspace/coverage/default/42.prim_prince_test.345378747 |
Short name | T147 |
Test name | |
Test status | |
Simulation time | 3151941964 ps |
CPU time | 53.95 seconds |
Started | Aug 12 04:21:15 PM PDT 24 |
Finished | Aug 12 04:22:22 PM PDT 24 |
Peak memory | 146676 kb |
Host | smart-9302fdad-8a3c-4f37-bd42-7d1d0830c7d5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=345378747 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_prince_test.345378747 |
Directory | /workspace/42.prim_prince_test/latest |
Test location | /workspace/coverage/default/420.prim_prince_test.957695540 |
Short name | T469 |
Test name | |
Test status | |
Simulation time | 3557048758 ps |
CPU time | 56.98 seconds |
Started | Aug 12 04:26:22 PM PDT 24 |
Finished | Aug 12 04:27:29 PM PDT 24 |
Peak memory | 146180 kb |
Host | smart-c31e2ea6-7709-4936-8b62-2c802dc99fc6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=957695540 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 420.prim_prince_test.957695540 |
Directory | /workspace/420.prim_prince_test/latest |
Test location | /workspace/coverage/default/421.prim_prince_test.3175396521 |
Short name | T331 |
Test name | |
Test status | |
Simulation time | 2775392544 ps |
CPU time | 45.53 seconds |
Started | Aug 12 04:25:56 PM PDT 24 |
Finished | Aug 12 04:26:51 PM PDT 24 |
Peak memory | 146304 kb |
Host | smart-7a92a4e7-4ed8-41d6-a348-9472f98b63d4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3175396521 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 421.prim_prince_test.3175396521 |
Directory | /workspace/421.prim_prince_test/latest |
Test location | /workspace/coverage/default/422.prim_prince_test.4250069077 |
Short name | T481 |
Test name | |
Test status | |
Simulation time | 1444738081 ps |
CPU time | 24.33 seconds |
Started | Aug 12 04:26:10 PM PDT 24 |
Finished | Aug 12 04:26:40 PM PDT 24 |
Peak memory | 146364 kb |
Host | smart-cec6f939-4018-4d56-8a0a-ca6f9dba38fe |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4250069077 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 422.prim_prince_test.4250069077 |
Directory | /workspace/422.prim_prince_test/latest |
Test location | /workspace/coverage/default/423.prim_prince_test.1172049698 |
Short name | T358 |
Test name | |
Test status | |
Simulation time | 1204609156 ps |
CPU time | 20.82 seconds |
Started | Aug 12 04:24:42 PM PDT 24 |
Finished | Aug 12 04:25:07 PM PDT 24 |
Peak memory | 146556 kb |
Host | smart-71dd68fb-6ca6-45fe-a904-4c287f1db382 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1172049698 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 423.prim_prince_test.1172049698 |
Directory | /workspace/423.prim_prince_test/latest |
Test location | /workspace/coverage/default/424.prim_prince_test.1315255327 |
Short name | T409 |
Test name | |
Test status | |
Simulation time | 1997244471 ps |
CPU time | 33.18 seconds |
Started | Aug 12 04:26:10 PM PDT 24 |
Finished | Aug 12 04:26:50 PM PDT 24 |
Peak memory | 146364 kb |
Host | smart-1e1e759f-e67a-4d29-b50e-efff464967a2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1315255327 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 424.prim_prince_test.1315255327 |
Directory | /workspace/424.prim_prince_test/latest |
Test location | /workspace/coverage/default/425.prim_prince_test.3777265559 |
Short name | T203 |
Test name | |
Test status | |
Simulation time | 2365929382 ps |
CPU time | 40.65 seconds |
Started | Aug 12 04:26:36 PM PDT 24 |
Finished | Aug 12 04:27:26 PM PDT 24 |
Peak memory | 146668 kb |
Host | smart-11352a67-be27-4e81-8654-7b91c313aece |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3777265559 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 425.prim_prince_test.3777265559 |
Directory | /workspace/425.prim_prince_test/latest |
Test location | /workspace/coverage/default/426.prim_prince_test.1618251742 |
Short name | T423 |
Test name | |
Test status | |
Simulation time | 1815138762 ps |
CPU time | 30.02 seconds |
Started | Aug 12 04:25:55 PM PDT 24 |
Finished | Aug 12 04:26:31 PM PDT 24 |
Peak memory | 145072 kb |
Host | smart-0be7c1cd-1208-4aee-afc4-2b17d60548fe |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1618251742 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 426.prim_prince_test.1618251742 |
Directory | /workspace/426.prim_prince_test/latest |
Test location | /workspace/coverage/default/427.prim_prince_test.2990681241 |
Short name | T135 |
Test name | |
Test status | |
Simulation time | 3264849509 ps |
CPU time | 56.37 seconds |
Started | Aug 12 04:24:39 PM PDT 24 |
Finished | Aug 12 04:25:50 PM PDT 24 |
Peak memory | 146720 kb |
Host | smart-b86642c2-3143-4331-bd20-809e10e58856 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2990681241 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 427.prim_prince_test.2990681241 |
Directory | /workspace/427.prim_prince_test/latest |
Test location | /workspace/coverage/default/428.prim_prince_test.3140802514 |
Short name | T184 |
Test name | |
Test status | |
Simulation time | 1057772121 ps |
CPU time | 18.18 seconds |
Started | Aug 12 04:26:45 PM PDT 24 |
Finished | Aug 12 04:27:08 PM PDT 24 |
Peak memory | 146632 kb |
Host | smart-6c4124da-3669-43e7-b28e-529ab2a917ff |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3140802514 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 428.prim_prince_test.3140802514 |
Directory | /workspace/428.prim_prince_test/latest |
Test location | /workspace/coverage/default/429.prim_prince_test.160217113 |
Short name | T101 |
Test name | |
Test status | |
Simulation time | 1027984157 ps |
CPU time | 17.27 seconds |
Started | Aug 12 04:26:10 PM PDT 24 |
Finished | Aug 12 04:26:31 PM PDT 24 |
Peak memory | 146372 kb |
Host | smart-daa84b98-52c2-4809-816e-cd5e8db5a63b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=160217113 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 429.prim_prince_test.160217113 |
Directory | /workspace/429.prim_prince_test/latest |
Test location | /workspace/coverage/default/43.prim_prince_test.3536456373 |
Short name | T398 |
Test name | |
Test status | |
Simulation time | 2476902413 ps |
CPU time | 41.88 seconds |
Started | Aug 12 04:22:30 PM PDT 24 |
Finished | Aug 12 04:23:21 PM PDT 24 |
Peak memory | 146592 kb |
Host | smart-825989ec-c9f2-4ed9-abeb-692f66709f44 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3536456373 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_prince_test.3536456373 |
Directory | /workspace/43.prim_prince_test/latest |
Test location | /workspace/coverage/default/430.prim_prince_test.2861885480 |
Short name | T46 |
Test name | |
Test status | |
Simulation time | 1042601974 ps |
CPU time | 17.23 seconds |
Started | Aug 12 04:26:09 PM PDT 24 |
Finished | Aug 12 04:26:30 PM PDT 24 |
Peak memory | 146364 kb |
Host | smart-d090e9c4-ee0b-498b-baa4-d447214f4e27 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2861885480 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 430.prim_prince_test.2861885480 |
Directory | /workspace/430.prim_prince_test/latest |
Test location | /workspace/coverage/default/431.prim_prince_test.3774321331 |
Short name | T93 |
Test name | |
Test status | |
Simulation time | 2291868752 ps |
CPU time | 39.2 seconds |
Started | Aug 12 04:26:15 PM PDT 24 |
Finished | Aug 12 04:27:03 PM PDT 24 |
Peak memory | 146620 kb |
Host | smart-9c7bc194-5d7f-4c6c-944f-d01878d8d7f3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3774321331 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 431.prim_prince_test.3774321331 |
Directory | /workspace/431.prim_prince_test/latest |
Test location | /workspace/coverage/default/432.prim_prince_test.1453018129 |
Short name | T55 |
Test name | |
Test status | |
Simulation time | 963148225 ps |
CPU time | 16.37 seconds |
Started | Aug 12 04:26:54 PM PDT 24 |
Finished | Aug 12 04:27:14 PM PDT 24 |
Peak memory | 146412 kb |
Host | smart-e1c000c6-69d9-4159-ab2f-270ab610443a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1453018129 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 432.prim_prince_test.1453018129 |
Directory | /workspace/432.prim_prince_test/latest |
Test location | /workspace/coverage/default/433.prim_prince_test.250477327 |
Short name | T477 |
Test name | |
Test status | |
Simulation time | 3695250100 ps |
CPU time | 63.24 seconds |
Started | Aug 12 04:26:37 PM PDT 24 |
Finished | Aug 12 04:27:56 PM PDT 24 |
Peak memory | 146828 kb |
Host | smart-09fc01f2-6fe7-4df5-b6c9-fad9cc5c6393 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=250477327 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 433.prim_prince_test.250477327 |
Directory | /workspace/433.prim_prince_test/latest |
Test location | /workspace/coverage/default/434.prim_prince_test.717978328 |
Short name | T314 |
Test name | |
Test status | |
Simulation time | 3095899372 ps |
CPU time | 52.62 seconds |
Started | Aug 12 04:26:13 PM PDT 24 |
Finished | Aug 12 04:27:18 PM PDT 24 |
Peak memory | 146664 kb |
Host | smart-81d511d8-e489-482e-9c55-48ba7e3703c5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=717978328 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 434.prim_prince_test.717978328 |
Directory | /workspace/434.prim_prince_test/latest |
Test location | /workspace/coverage/default/435.prim_prince_test.739294676 |
Short name | T283 |
Test name | |
Test status | |
Simulation time | 3714921957 ps |
CPU time | 62.33 seconds |
Started | Aug 12 04:26:47 PM PDT 24 |
Finished | Aug 12 04:28:03 PM PDT 24 |
Peak memory | 146636 kb |
Host | smart-3d16cef0-50c2-4e1e-b83f-9dfbbef76e00 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=739294676 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 435.prim_prince_test.739294676 |
Directory | /workspace/435.prim_prince_test/latest |
Test location | /workspace/coverage/default/436.prim_prince_test.3077120509 |
Short name | T85 |
Test name | |
Test status | |
Simulation time | 1155818141 ps |
CPU time | 19.82 seconds |
Started | Aug 12 04:26:25 PM PDT 24 |
Finished | Aug 12 04:26:50 PM PDT 24 |
Peak memory | 146764 kb |
Host | smart-1f4482d3-66e3-46e0-9713-5388e5b7e9cb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3077120509 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 436.prim_prince_test.3077120509 |
Directory | /workspace/436.prim_prince_test/latest |
Test location | /workspace/coverage/default/437.prim_prince_test.2585748675 |
Short name | T332 |
Test name | |
Test status | |
Simulation time | 3366421106 ps |
CPU time | 56.31 seconds |
Started | Aug 12 04:26:09 PM PDT 24 |
Finished | Aug 12 04:27:18 PM PDT 24 |
Peak memory | 146428 kb |
Host | smart-4a5005ab-2d89-4653-9a91-017353b163a4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2585748675 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 437.prim_prince_test.2585748675 |
Directory | /workspace/437.prim_prince_test/latest |
Test location | /workspace/coverage/default/438.prim_prince_test.2600891754 |
Short name | T215 |
Test name | |
Test status | |
Simulation time | 762884992 ps |
CPU time | 13.38 seconds |
Started | Aug 12 04:24:49 PM PDT 24 |
Finished | Aug 12 04:25:06 PM PDT 24 |
Peak memory | 146556 kb |
Host | smart-0860ecd3-cffa-449f-9286-8450e85a4dbd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2600891754 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 438.prim_prince_test.2600891754 |
Directory | /workspace/438.prim_prince_test/latest |
Test location | /workspace/coverage/default/439.prim_prince_test.4008078791 |
Short name | T455 |
Test name | |
Test status | |
Simulation time | 2612472965 ps |
CPU time | 41.67 seconds |
Started | Aug 12 04:26:28 PM PDT 24 |
Finished | Aug 12 04:27:18 PM PDT 24 |
Peak memory | 146176 kb |
Host | smart-960fe5a1-3765-460b-8cb7-9f92930ffa9a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4008078791 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 439.prim_prince_test.4008078791 |
Directory | /workspace/439.prim_prince_test/latest |
Test location | /workspace/coverage/default/44.prim_prince_test.1160010912 |
Short name | T63 |
Test name | |
Test status | |
Simulation time | 968249454 ps |
CPU time | 15.75 seconds |
Started | Aug 12 04:24:19 PM PDT 24 |
Finished | Aug 12 04:24:38 PM PDT 24 |
Peak memory | 145580 kb |
Host | smart-e468ae27-1922-4f68-85dd-4d7d159382b5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1160010912 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_prince_test.1160010912 |
Directory | /workspace/44.prim_prince_test/latest |
Test location | /workspace/coverage/default/440.prim_prince_test.3666114704 |
Short name | T309 |
Test name | |
Test status | |
Simulation time | 2399614264 ps |
CPU time | 39.12 seconds |
Started | Aug 12 04:26:19 PM PDT 24 |
Finished | Aug 12 04:27:06 PM PDT 24 |
Peak memory | 144952 kb |
Host | smart-14cfea45-73b3-4f95-8367-73ca1d739d5f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3666114704 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 440.prim_prince_test.3666114704 |
Directory | /workspace/440.prim_prince_test/latest |
Test location | /workspace/coverage/default/441.prim_prince_test.1451772275 |
Short name | T395 |
Test name | |
Test status | |
Simulation time | 1998543714 ps |
CPU time | 34.85 seconds |
Started | Aug 12 04:24:49 PM PDT 24 |
Finished | Aug 12 04:25:33 PM PDT 24 |
Peak memory | 146664 kb |
Host | smart-9fb86eb6-337b-4a28-9a6d-3ae41605089a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1451772275 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 441.prim_prince_test.1451772275 |
Directory | /workspace/441.prim_prince_test/latest |
Test location | /workspace/coverage/default/442.prim_prince_test.1092972496 |
Short name | T278 |
Test name | |
Test status | |
Simulation time | 1289641312 ps |
CPU time | 20.98 seconds |
Started | Aug 12 04:26:19 PM PDT 24 |
Finished | Aug 12 04:26:44 PM PDT 24 |
Peak memory | 144924 kb |
Host | smart-5ed86f86-a3f2-4708-8dab-75704ed1769b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1092972496 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 442.prim_prince_test.1092972496 |
Directory | /workspace/442.prim_prince_test/latest |
Test location | /workspace/coverage/default/443.prim_prince_test.3181435491 |
Short name | T117 |
Test name | |
Test status | |
Simulation time | 2438371039 ps |
CPU time | 39.13 seconds |
Started | Aug 12 04:26:28 PM PDT 24 |
Finished | Aug 12 04:27:15 PM PDT 24 |
Peak memory | 146300 kb |
Host | smart-d828a1dd-32d9-40a5-8aa3-f58ecef556da |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3181435491 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 443.prim_prince_test.3181435491 |
Directory | /workspace/443.prim_prince_test/latest |
Test location | /workspace/coverage/default/444.prim_prince_test.2228735242 |
Short name | T470 |
Test name | |
Test status | |
Simulation time | 1775829646 ps |
CPU time | 28.52 seconds |
Started | Aug 12 04:24:51 PM PDT 24 |
Finished | Aug 12 04:25:25 PM PDT 24 |
Peak memory | 145588 kb |
Host | smart-a39dcbb6-9fbd-40f9-978b-df259921392a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2228735242 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 444.prim_prince_test.2228735242 |
Directory | /workspace/444.prim_prince_test/latest |
Test location | /workspace/coverage/default/445.prim_prince_test.1313333252 |
Short name | T370 |
Test name | |
Test status | |
Simulation time | 2633953028 ps |
CPU time | 42.15 seconds |
Started | Aug 12 04:26:28 PM PDT 24 |
Finished | Aug 12 04:27:18 PM PDT 24 |
Peak memory | 146184 kb |
Host | smart-71fd4df3-b68f-4f2d-9a20-c1457ca5333d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1313333252 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 445.prim_prince_test.1313333252 |
Directory | /workspace/445.prim_prince_test/latest |
Test location | /workspace/coverage/default/446.prim_prince_test.2599851561 |
Short name | T347 |
Test name | |
Test status | |
Simulation time | 1629507266 ps |
CPU time | 26.64 seconds |
Started | Aug 12 04:26:28 PM PDT 24 |
Finished | Aug 12 04:27:00 PM PDT 24 |
Peak memory | 146228 kb |
Host | smart-ab5cfcfe-e2ca-4f0f-ba10-696213b6feb1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2599851561 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 446.prim_prince_test.2599851561 |
Directory | /workspace/446.prim_prince_test/latest |
Test location | /workspace/coverage/default/447.prim_prince_test.3338494228 |
Short name | T103 |
Test name | |
Test status | |
Simulation time | 1958818906 ps |
CPU time | 31.43 seconds |
Started | Aug 12 04:26:28 PM PDT 24 |
Finished | Aug 12 04:27:05 PM PDT 24 |
Peak memory | 146176 kb |
Host | smart-8560dcf6-fabb-477e-b000-61a04c6f18cc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3338494228 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 447.prim_prince_test.3338494228 |
Directory | /workspace/447.prim_prince_test/latest |
Test location | /workspace/coverage/default/448.prim_prince_test.2101128429 |
Short name | T337 |
Test name | |
Test status | |
Simulation time | 2279852302 ps |
CPU time | 37.56 seconds |
Started | Aug 12 04:26:32 PM PDT 24 |
Finished | Aug 12 04:27:17 PM PDT 24 |
Peak memory | 144060 kb |
Host | smart-2e48a4cf-22cb-49a4-bb75-cf156d4c805f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2101128429 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 448.prim_prince_test.2101128429 |
Directory | /workspace/448.prim_prince_test/latest |
Test location | /workspace/coverage/default/449.prim_prince_test.771136988 |
Short name | T84 |
Test name | |
Test status | |
Simulation time | 1360993005 ps |
CPU time | 21.67 seconds |
Started | Aug 12 04:26:28 PM PDT 24 |
Finished | Aug 12 04:26:54 PM PDT 24 |
Peak memory | 146232 kb |
Host | smart-a621824e-a656-4b31-9b8b-8155e7b03e1c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=771136988 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 449.prim_prince_test.771136988 |
Directory | /workspace/449.prim_prince_test/latest |
Test location | /workspace/coverage/default/45.prim_prince_test.839764051 |
Short name | T498 |
Test name | |
Test status | |
Simulation time | 1623649667 ps |
CPU time | 27.24 seconds |
Started | Aug 12 04:22:16 PM PDT 24 |
Finished | Aug 12 04:22:49 PM PDT 24 |
Peak memory | 144428 kb |
Host | smart-e04208cd-0f2e-431a-ac40-c92561a90953 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=839764051 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_prince_test.839764051 |
Directory | /workspace/45.prim_prince_test/latest |
Test location | /workspace/coverage/default/450.prim_prince_test.2179476817 |
Short name | T364 |
Test name | |
Test status | |
Simulation time | 2761113391 ps |
CPU time | 44.96 seconds |
Started | Aug 12 04:26:24 PM PDT 24 |
Finished | Aug 12 04:27:17 PM PDT 24 |
Peak memory | 145316 kb |
Host | smart-9e94fdf5-a700-490f-a2de-b8a1b6716af4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2179476817 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 450.prim_prince_test.2179476817 |
Directory | /workspace/450.prim_prince_test/latest |
Test location | /workspace/coverage/default/451.prim_prince_test.2461269338 |
Short name | T284 |
Test name | |
Test status | |
Simulation time | 1816059615 ps |
CPU time | 29.84 seconds |
Started | Aug 12 04:26:20 PM PDT 24 |
Finished | Aug 12 04:26:55 PM PDT 24 |
Peak memory | 146348 kb |
Host | smart-f9477953-52ac-4ea9-98e9-2378ba301184 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2461269338 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 451.prim_prince_test.2461269338 |
Directory | /workspace/451.prim_prince_test/latest |
Test location | /workspace/coverage/default/452.prim_prince_test.3058254726 |
Short name | T12 |
Test name | |
Test status | |
Simulation time | 2990590452 ps |
CPU time | 51.24 seconds |
Started | Aug 12 04:24:55 PM PDT 24 |
Finished | Aug 12 04:25:59 PM PDT 24 |
Peak memory | 146828 kb |
Host | smart-e271624f-4de1-4d4b-b134-b341fc88e50c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3058254726 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 452.prim_prince_test.3058254726 |
Directory | /workspace/452.prim_prince_test/latest |
Test location | /workspace/coverage/default/453.prim_prince_test.3863181913 |
Short name | T400 |
Test name | |
Test status | |
Simulation time | 3637338946 ps |
CPU time | 62.61 seconds |
Started | Aug 12 04:24:56 PM PDT 24 |
Finished | Aug 12 04:26:13 PM PDT 24 |
Peak memory | 146660 kb |
Host | smart-12421b91-b08c-4db7-99f1-1a5c22e12183 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3863181913 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 453.prim_prince_test.3863181913 |
Directory | /workspace/453.prim_prince_test/latest |
Test location | /workspace/coverage/default/454.prim_prince_test.2507294240 |
Short name | T377 |
Test name | |
Test status | |
Simulation time | 1023016084 ps |
CPU time | 17.08 seconds |
Started | Aug 12 04:24:57 PM PDT 24 |
Finished | Aug 12 04:25:17 PM PDT 24 |
Peak memory | 146564 kb |
Host | smart-995c8209-751a-41f8-a4ec-e3124cc705ff |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2507294240 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 454.prim_prince_test.2507294240 |
Directory | /workspace/454.prim_prince_test/latest |
Test location | /workspace/coverage/default/455.prim_prince_test.3379122590 |
Short name | T165 |
Test name | |
Test status | |
Simulation time | 949073922 ps |
CPU time | 15.55 seconds |
Started | Aug 12 04:26:32 PM PDT 24 |
Finished | Aug 12 04:26:51 PM PDT 24 |
Peak memory | 146108 kb |
Host | smart-2695d64d-9ae0-4777-8b0b-0495b3c31619 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3379122590 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 455.prim_prince_test.3379122590 |
Directory | /workspace/455.prim_prince_test/latest |
Test location | /workspace/coverage/default/456.prim_prince_test.1166824920 |
Short name | T34 |
Test name | |
Test status | |
Simulation time | 3249022881 ps |
CPU time | 52.33 seconds |
Started | Aug 12 04:26:24 PM PDT 24 |
Finished | Aug 12 04:27:26 PM PDT 24 |
Peak memory | 145352 kb |
Host | smart-102533d3-1230-4f10-b637-8343d6d60791 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1166824920 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 456.prim_prince_test.1166824920 |
Directory | /workspace/456.prim_prince_test/latest |
Test location | /workspace/coverage/default/457.prim_prince_test.319496991 |
Short name | T195 |
Test name | |
Test status | |
Simulation time | 2592357109 ps |
CPU time | 43.24 seconds |
Started | Aug 12 04:26:12 PM PDT 24 |
Finished | Aug 12 04:27:04 PM PDT 24 |
Peak memory | 146480 kb |
Host | smart-ac571bf3-6c10-4243-a2f9-d33c77c447f3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=319496991 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 457.prim_prince_test.319496991 |
Directory | /workspace/457.prim_prince_test/latest |
Test location | /workspace/coverage/default/458.prim_prince_test.3032845362 |
Short name | T59 |
Test name | |
Test status | |
Simulation time | 2540681348 ps |
CPU time | 42.67 seconds |
Started | Aug 12 04:26:26 PM PDT 24 |
Finished | Aug 12 04:27:18 PM PDT 24 |
Peak memory | 146628 kb |
Host | smart-ff6cc636-d7d8-4233-ab7b-f9d56230f61e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3032845362 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 458.prim_prince_test.3032845362 |
Directory | /workspace/458.prim_prince_test/latest |
Test location | /workspace/coverage/default/459.prim_prince_test.1453503771 |
Short name | T142 |
Test name | |
Test status | |
Simulation time | 2545050169 ps |
CPU time | 41.4 seconds |
Started | Aug 12 04:26:18 PM PDT 24 |
Finished | Aug 12 04:27:08 PM PDT 24 |
Peak memory | 145528 kb |
Host | smart-0325afa4-ecfe-498f-803f-6677f5d29e75 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1453503771 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 459.prim_prince_test.1453503771 |
Directory | /workspace/459.prim_prince_test/latest |
Test location | /workspace/coverage/default/46.prim_prince_test.1457853775 |
Short name | T220 |
Test name | |
Test status | |
Simulation time | 3087950040 ps |
CPU time | 50.19 seconds |
Started | Aug 12 04:21:16 PM PDT 24 |
Finished | Aug 12 04:22:16 PM PDT 24 |
Peak memory | 146268 kb |
Host | smart-37eb6240-2dfa-43ab-9302-2d9cec3eed49 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1457853775 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_prince_test.1457853775 |
Directory | /workspace/46.prim_prince_test/latest |
Test location | /workspace/coverage/default/460.prim_prince_test.4065614090 |
Short name | T45 |
Test name | |
Test status | |
Simulation time | 1931324303 ps |
CPU time | 31.92 seconds |
Started | Aug 12 04:26:41 PM PDT 24 |
Finished | Aug 12 04:27:20 PM PDT 24 |
Peak memory | 146216 kb |
Host | smart-7728db51-aee8-49c3-b976-c1c29629f0fa |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4065614090 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 460.prim_prince_test.4065614090 |
Directory | /workspace/460.prim_prince_test/latest |
Test location | /workspace/coverage/default/461.prim_prince_test.3026380693 |
Short name | T5 |
Test name | |
Test status | |
Simulation time | 3341755888 ps |
CPU time | 58.38 seconds |
Started | Aug 12 04:25:04 PM PDT 24 |
Finished | Aug 12 04:26:18 PM PDT 24 |
Peak memory | 146696 kb |
Host | smart-9805cc42-3f2c-4891-86c1-0c4c348d1420 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3026380693 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 461.prim_prince_test.3026380693 |
Directory | /workspace/461.prim_prince_test/latest |
Test location | /workspace/coverage/default/462.prim_prince_test.3235172068 |
Short name | T52 |
Test name | |
Test status | |
Simulation time | 2605382345 ps |
CPU time | 43.33 seconds |
Started | Aug 12 04:26:41 PM PDT 24 |
Finished | Aug 12 04:27:34 PM PDT 24 |
Peak memory | 146280 kb |
Host | smart-711a0970-5efe-4a96-96ac-1179952e50cc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3235172068 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 462.prim_prince_test.3235172068 |
Directory | /workspace/462.prim_prince_test/latest |
Test location | /workspace/coverage/default/463.prim_prince_test.1811521789 |
Short name | T138 |
Test name | |
Test status | |
Simulation time | 1241125534 ps |
CPU time | 20.58 seconds |
Started | Aug 12 04:26:32 PM PDT 24 |
Finished | Aug 12 04:26:58 PM PDT 24 |
Peak memory | 146512 kb |
Host | smart-60ec5213-b965-4feb-b323-742cab1af448 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1811521789 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 463.prim_prince_test.1811521789 |
Directory | /workspace/463.prim_prince_test/latest |
Test location | /workspace/coverage/default/464.prim_prince_test.1243329782 |
Short name | T44 |
Test name | |
Test status | |
Simulation time | 1778090805 ps |
CPU time | 29.95 seconds |
Started | Aug 12 04:25:03 PM PDT 24 |
Finished | Aug 12 04:25:39 PM PDT 24 |
Peak memory | 146556 kb |
Host | smart-6a39703b-69f0-464f-b581-84439cbe5aa6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1243329782 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 464.prim_prince_test.1243329782 |
Directory | /workspace/464.prim_prince_test/latest |
Test location | /workspace/coverage/default/465.prim_prince_test.124662029 |
Short name | T232 |
Test name | |
Test status | |
Simulation time | 1183888695 ps |
CPU time | 19.67 seconds |
Started | Aug 12 04:26:18 PM PDT 24 |
Finished | Aug 12 04:26:42 PM PDT 24 |
Peak memory | 144176 kb |
Host | smart-947885ec-36a2-4027-921f-18298ab08dd1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=124662029 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 465.prim_prince_test.124662029 |
Directory | /workspace/465.prim_prince_test/latest |
Test location | /workspace/coverage/default/466.prim_prince_test.817211262 |
Short name | T419 |
Test name | |
Test status | |
Simulation time | 1428560480 ps |
CPU time | 23.44 seconds |
Started | Aug 12 04:26:18 PM PDT 24 |
Finished | Aug 12 04:26:47 PM PDT 24 |
Peak memory | 144260 kb |
Host | smart-fb2b0f2f-5700-49e2-ab47-f318672e2f21 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=817211262 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 466.prim_prince_test.817211262 |
Directory | /workspace/466.prim_prince_test/latest |
Test location | /workspace/coverage/default/467.prim_prince_test.139750426 |
Short name | T315 |
Test name | |
Test status | |
Simulation time | 2157621309 ps |
CPU time | 35.53 seconds |
Started | Aug 12 04:26:32 PM PDT 24 |
Finished | Aug 12 04:27:15 PM PDT 24 |
Peak memory | 146572 kb |
Host | smart-25bbf4b1-73a4-434d-a647-36878c4279d2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=139750426 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 467.prim_prince_test.139750426 |
Directory | /workspace/467.prim_prince_test/latest |
Test location | /workspace/coverage/default/468.prim_prince_test.3535874395 |
Short name | T236 |
Test name | |
Test status | |
Simulation time | 2104596424 ps |
CPU time | 34.88 seconds |
Started | Aug 12 04:26:41 PM PDT 24 |
Finished | Aug 12 04:27:24 PM PDT 24 |
Peak memory | 146216 kb |
Host | smart-da8ea1ec-c461-46fb-9497-cd29ea88a334 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3535874395 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 468.prim_prince_test.3535874395 |
Directory | /workspace/468.prim_prince_test/latest |
Test location | /workspace/coverage/default/469.prim_prince_test.1931322749 |
Short name | T360 |
Test name | |
Test status | |
Simulation time | 2587683563 ps |
CPU time | 41.65 seconds |
Started | Aug 12 04:26:19 PM PDT 24 |
Finished | Aug 12 04:27:08 PM PDT 24 |
Peak memory | 146132 kb |
Host | smart-1cc153bb-deb9-404e-92a0-aaab4bde44f7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1931322749 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 469.prim_prince_test.1931322749 |
Directory | /workspace/469.prim_prince_test/latest |
Test location | /workspace/coverage/default/47.prim_prince_test.2965667632 |
Short name | T37 |
Test name | |
Test status | |
Simulation time | 2077136279 ps |
CPU time | 35.88 seconds |
Started | Aug 12 04:21:14 PM PDT 24 |
Finished | Aug 12 04:22:00 PM PDT 24 |
Peak memory | 146612 kb |
Host | smart-d75288b4-005d-4645-9641-89e3bc20e3e9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2965667632 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_prince_test.2965667632 |
Directory | /workspace/47.prim_prince_test/latest |
Test location | /workspace/coverage/default/470.prim_prince_test.355450711 |
Short name | T389 |
Test name | |
Test status | |
Simulation time | 1412128520 ps |
CPU time | 23.68 seconds |
Started | Aug 12 04:26:32 PM PDT 24 |
Finished | Aug 12 04:27:01 PM PDT 24 |
Peak memory | 146488 kb |
Host | smart-d9280de8-44e1-46ac-9445-7b635e31e007 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=355450711 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 470.prim_prince_test.355450711 |
Directory | /workspace/470.prim_prince_test/latest |
Test location | /workspace/coverage/default/471.prim_prince_test.1680945415 |
Short name | T154 |
Test name | |
Test status | |
Simulation time | 1357222425 ps |
CPU time | 22.88 seconds |
Started | Aug 12 04:25:17 PM PDT 24 |
Finished | Aug 12 04:25:45 PM PDT 24 |
Peak memory | 146628 kb |
Host | smart-d8204339-abdb-4646-a00e-137221d6a808 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1680945415 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 471.prim_prince_test.1680945415 |
Directory | /workspace/471.prim_prince_test/latest |
Test location | /workspace/coverage/default/472.prim_prince_test.2756417493 |
Short name | T245 |
Test name | |
Test status | |
Simulation time | 1231861849 ps |
CPU time | 20.85 seconds |
Started | Aug 12 04:26:25 PM PDT 24 |
Finished | Aug 12 04:26:51 PM PDT 24 |
Peak memory | 146012 kb |
Host | smart-dbd9ae40-33ad-4f2f-888c-d7ed7dcd9187 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2756417493 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 472.prim_prince_test.2756417493 |
Directory | /workspace/472.prim_prince_test/latest |
Test location | /workspace/coverage/default/473.prim_prince_test.2533983195 |
Short name | T484 |
Test name | |
Test status | |
Simulation time | 1158576834 ps |
CPU time | 20.02 seconds |
Started | Aug 12 04:25:14 PM PDT 24 |
Finished | Aug 12 04:25:39 PM PDT 24 |
Peak memory | 146556 kb |
Host | smart-75bcb52b-0206-4a33-aec8-2e46b0b9728f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2533983195 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 473.prim_prince_test.2533983195 |
Directory | /workspace/473.prim_prince_test/latest |
Test location | /workspace/coverage/default/474.prim_prince_test.1605111370 |
Short name | T164 |
Test name | |
Test status | |
Simulation time | 3021388778 ps |
CPU time | 46.97 seconds |
Started | Aug 12 04:26:41 PM PDT 24 |
Finished | Aug 12 04:27:36 PM PDT 24 |
Peak memory | 146640 kb |
Host | smart-5af2f627-7b0b-44ce-adcd-85045968e2e9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1605111370 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 474.prim_prince_test.1605111370 |
Directory | /workspace/474.prim_prince_test/latest |
Test location | /workspace/coverage/default/475.prim_prince_test.3888561608 |
Short name | T11 |
Test name | |
Test status | |
Simulation time | 2850505478 ps |
CPU time | 45.99 seconds |
Started | Aug 12 04:26:33 PM PDT 24 |
Finished | Aug 12 04:27:29 PM PDT 24 |
Peak memory | 146304 kb |
Host | smart-4124ce75-3408-4332-9aa4-f9c75b8f25f3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3888561608 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 475.prim_prince_test.3888561608 |
Directory | /workspace/475.prim_prince_test/latest |
Test location | /workspace/coverage/default/476.prim_prince_test.108852206 |
Short name | T111 |
Test name | |
Test status | |
Simulation time | 2776623338 ps |
CPU time | 45.5 seconds |
Started | Aug 12 04:26:32 PM PDT 24 |
Finished | Aug 12 04:27:26 PM PDT 24 |
Peak memory | 144956 kb |
Host | smart-882549d2-f4fc-4d6b-bb97-4c191e326388 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=108852206 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 476.prim_prince_test.108852206 |
Directory | /workspace/476.prim_prince_test/latest |
Test location | /workspace/coverage/default/477.prim_prince_test.1005357113 |
Short name | T76 |
Test name | |
Test status | |
Simulation time | 3063696791 ps |
CPU time | 47.59 seconds |
Started | Aug 12 04:26:41 PM PDT 24 |
Finished | Aug 12 04:27:37 PM PDT 24 |
Peak memory | 146640 kb |
Host | smart-e6493775-c0a7-41c1-83a9-7c3ef770ebd1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1005357113 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 477.prim_prince_test.1005357113 |
Directory | /workspace/477.prim_prince_test/latest |
Test location | /workspace/coverage/default/478.prim_prince_test.2306337683 |
Short name | T174 |
Test name | |
Test status | |
Simulation time | 913289344 ps |
CPU time | 14.5 seconds |
Started | Aug 12 04:25:12 PM PDT 24 |
Finished | Aug 12 04:25:29 PM PDT 24 |
Peak memory | 145588 kb |
Host | smart-db939672-c8a7-4c44-a0ab-619275f49dba |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2306337683 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 478.prim_prince_test.2306337683 |
Directory | /workspace/478.prim_prince_test/latest |
Test location | /workspace/coverage/default/479.prim_prince_test.2697691637 |
Short name | T262 |
Test name | |
Test status | |
Simulation time | 2102148444 ps |
CPU time | 34.82 seconds |
Started | Aug 12 04:26:25 PM PDT 24 |
Finished | Aug 12 04:27:07 PM PDT 24 |
Peak memory | 144784 kb |
Host | smart-df56167b-856a-4b2e-9ed4-4515258a6812 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2697691637 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 479.prim_prince_test.2697691637 |
Directory | /workspace/479.prim_prince_test/latest |
Test location | /workspace/coverage/default/48.prim_prince_test.251589627 |
Short name | T90 |
Test name | |
Test status | |
Simulation time | 1326029199 ps |
CPU time | 22.91 seconds |
Started | Aug 12 04:21:14 PM PDT 24 |
Finished | Aug 12 04:21:43 PM PDT 24 |
Peak memory | 146612 kb |
Host | smart-c58667f9-7346-4e49-8fb0-5854d285bacf |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=251589627 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_prince_test.251589627 |
Directory | /workspace/48.prim_prince_test/latest |
Test location | /workspace/coverage/default/480.prim_prince_test.3037923046 |
Short name | T178 |
Test name | |
Test status | |
Simulation time | 2581466336 ps |
CPU time | 42.53 seconds |
Started | Aug 12 04:26:25 PM PDT 24 |
Finished | Aug 12 04:27:17 PM PDT 24 |
Peak memory | 145104 kb |
Host | smart-19b3da40-61a6-4ab6-aa9a-eaa290a1d3e8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3037923046 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 480.prim_prince_test.3037923046 |
Directory | /workspace/480.prim_prince_test/latest |
Test location | /workspace/coverage/default/481.prim_prince_test.262862543 |
Short name | T211 |
Test name | |
Test status | |
Simulation time | 1396251166 ps |
CPU time | 23.53 seconds |
Started | Aug 12 04:27:23 PM PDT 24 |
Finished | Aug 12 04:27:52 PM PDT 24 |
Peak memory | 144432 kb |
Host | smart-eafab5d4-d235-4754-8fe5-6785aa9ccf01 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=262862543 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 481.prim_prince_test.262862543 |
Directory | /workspace/481.prim_prince_test/latest |
Test location | /workspace/coverage/default/482.prim_prince_test.2956500790 |
Short name | T495 |
Test name | |
Test status | |
Simulation time | 1223072901 ps |
CPU time | 20.4 seconds |
Started | Aug 12 04:27:23 PM PDT 24 |
Finished | Aug 12 04:27:48 PM PDT 24 |
Peak memory | 145912 kb |
Host | smart-32c21e58-e208-43e5-93b3-7c7ddb1ad588 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2956500790 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 482.prim_prince_test.2956500790 |
Directory | /workspace/482.prim_prince_test/latest |
Test location | /workspace/coverage/default/483.prim_prince_test.2629743257 |
Short name | T42 |
Test name | |
Test status | |
Simulation time | 2894698329 ps |
CPU time | 50.02 seconds |
Started | Aug 12 04:25:25 PM PDT 24 |
Finished | Aug 12 04:26:26 PM PDT 24 |
Peak memory | 146668 kb |
Host | smart-c719b311-d878-44d7-9b8f-8f03f6b0bb90 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2629743257 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 483.prim_prince_test.2629743257 |
Directory | /workspace/483.prim_prince_test/latest |
Test location | /workspace/coverage/default/484.prim_prince_test.1995626617 |
Short name | T362 |
Test name | |
Test status | |
Simulation time | 2153338340 ps |
CPU time | 35.56 seconds |
Started | Aug 12 04:25:24 PM PDT 24 |
Finished | Aug 12 04:26:07 PM PDT 24 |
Peak memory | 146696 kb |
Host | smart-46b95249-8843-4611-a597-80c65fc9ea56 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1995626617 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 484.prim_prince_test.1995626617 |
Directory | /workspace/484.prim_prince_test/latest |
Test location | /workspace/coverage/default/485.prim_prince_test.660523861 |
Short name | T254 |
Test name | |
Test status | |
Simulation time | 2760793106 ps |
CPU time | 47.63 seconds |
Started | Aug 12 04:25:19 PM PDT 24 |
Finished | Aug 12 04:26:19 PM PDT 24 |
Peak memory | 146732 kb |
Host | smart-da4741ed-37fb-4217-933d-e683303d2aca |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=660523861 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 485.prim_prince_test.660523861 |
Directory | /workspace/485.prim_prince_test/latest |
Test location | /workspace/coverage/default/486.prim_prince_test.3548088685 |
Short name | T228 |
Test name | |
Test status | |
Simulation time | 1204401811 ps |
CPU time | 20.56 seconds |
Started | Aug 12 04:25:31 PM PDT 24 |
Finished | Aug 12 04:25:57 PM PDT 24 |
Peak memory | 146492 kb |
Host | smart-30bdb0f3-dd95-4b19-88a7-463ebe881639 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3548088685 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 486.prim_prince_test.3548088685 |
Directory | /workspace/486.prim_prince_test/latest |
Test location | /workspace/coverage/default/487.prim_prince_test.1516516677 |
Short name | T177 |
Test name | |
Test status | |
Simulation time | 2856943365 ps |
CPU time | 48.58 seconds |
Started | Aug 12 04:25:23 PM PDT 24 |
Finished | Aug 12 04:26:23 PM PDT 24 |
Peak memory | 146696 kb |
Host | smart-fb248537-3d91-4164-ab09-5545bc8fcd40 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1516516677 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 487.prim_prince_test.1516516677 |
Directory | /workspace/487.prim_prince_test/latest |
Test location | /workspace/coverage/default/488.prim_prince_test.930076489 |
Short name | T155 |
Test name | |
Test status | |
Simulation time | 1697678824 ps |
CPU time | 29.28 seconds |
Started | Aug 12 04:25:31 PM PDT 24 |
Finished | Aug 12 04:26:07 PM PDT 24 |
Peak memory | 146524 kb |
Host | smart-7a6ac51b-1501-46fa-b340-c2896e78776f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=930076489 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 488.prim_prince_test.930076489 |
Directory | /workspace/488.prim_prince_test/latest |
Test location | /workspace/coverage/default/489.prim_prince_test.2532808832 |
Short name | T171 |
Test name | |
Test status | |
Simulation time | 3359387268 ps |
CPU time | 54.99 seconds |
Started | Aug 12 04:27:24 PM PDT 24 |
Finished | Aug 12 04:28:30 PM PDT 24 |
Peak memory | 146232 kb |
Host | smart-8e307c71-d478-4221-a646-959082dba0ba |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2532808832 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 489.prim_prince_test.2532808832 |
Directory | /workspace/489.prim_prince_test/latest |
Test location | /workspace/coverage/default/49.prim_prince_test.780241483 |
Short name | T102 |
Test name | |
Test status | |
Simulation time | 3162649041 ps |
CPU time | 52.46 seconds |
Started | Aug 12 04:21:15 PM PDT 24 |
Finished | Aug 12 04:22:19 PM PDT 24 |
Peak memory | 146192 kb |
Host | smart-35f4f5a1-a854-44b0-86d4-90521cbc2f88 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=780241483 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_prince_test.780241483 |
Directory | /workspace/49.prim_prince_test/latest |
Test location | /workspace/coverage/default/490.prim_prince_test.253374156 |
Short name | T279 |
Test name | |
Test status | |
Simulation time | 3337115275 ps |
CPU time | 55.3 seconds |
Started | Aug 12 04:25:32 PM PDT 24 |
Finished | Aug 12 04:26:39 PM PDT 24 |
Peak memory | 146628 kb |
Host | smart-31455a21-356e-44ea-81a2-0e4e39da5002 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=253374156 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 490.prim_prince_test.253374156 |
Directory | /workspace/490.prim_prince_test/latest |
Test location | /workspace/coverage/default/491.prim_prince_test.3140164601 |
Short name | T197 |
Test name | |
Test status | |
Simulation time | 1096170998 ps |
CPU time | 19.37 seconds |
Started | Aug 12 04:25:47 PM PDT 24 |
Finished | Aug 12 04:26:11 PM PDT 24 |
Peak memory | 146632 kb |
Host | smart-bc6bd8ee-d8dd-4e51-9524-21f475b15690 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3140164601 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 491.prim_prince_test.3140164601 |
Directory | /workspace/491.prim_prince_test/latest |
Test location | /workspace/coverage/default/492.prim_prince_test.3341627882 |
Short name | T490 |
Test name | |
Test status | |
Simulation time | 2164768749 ps |
CPU time | 36.08 seconds |
Started | Aug 12 04:25:32 PM PDT 24 |
Finished | Aug 12 04:26:15 PM PDT 24 |
Peak memory | 146692 kb |
Host | smart-5548da6f-f8a0-4ab4-b88e-f3d7dff1b292 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3341627882 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 492.prim_prince_test.3341627882 |
Directory | /workspace/492.prim_prince_test/latest |
Test location | /workspace/coverage/default/493.prim_prince_test.2578512700 |
Short name | T316 |
Test name | |
Test status | |
Simulation time | 1306234122 ps |
CPU time | 22.48 seconds |
Started | Aug 12 04:25:31 PM PDT 24 |
Finished | Aug 12 04:25:59 PM PDT 24 |
Peak memory | 146632 kb |
Host | smart-b377d2f6-cf0f-42d5-bbe5-a3e1f8362f57 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2578512700 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 493.prim_prince_test.2578512700 |
Directory | /workspace/493.prim_prince_test/latest |
Test location | /workspace/coverage/default/494.prim_prince_test.3683934622 |
Short name | T49 |
Test name | |
Test status | |
Simulation time | 2076242076 ps |
CPU time | 36.37 seconds |
Started | Aug 12 04:25:31 PM PDT 24 |
Finished | Aug 12 04:26:17 PM PDT 24 |
Peak memory | 146632 kb |
Host | smart-ddd8b7d6-d401-4ff0-bdc8-939b6835feff |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3683934622 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 494.prim_prince_test.3683934622 |
Directory | /workspace/494.prim_prince_test/latest |
Test location | /workspace/coverage/default/495.prim_prince_test.3187780024 |
Short name | T467 |
Test name | |
Test status | |
Simulation time | 788843423 ps |
CPU time | 13.82 seconds |
Started | Aug 12 04:25:30 PM PDT 24 |
Finished | Aug 12 04:25:47 PM PDT 24 |
Peak memory | 146596 kb |
Host | smart-ceebfa55-222d-4b9b-a109-d93a1847d796 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3187780024 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 495.prim_prince_test.3187780024 |
Directory | /workspace/495.prim_prince_test/latest |
Test location | /workspace/coverage/default/496.prim_prince_test.2032165391 |
Short name | T338 |
Test name | |
Test status | |
Simulation time | 900240537 ps |
CPU time | 14.77 seconds |
Started | Aug 12 04:25:33 PM PDT 24 |
Finished | Aug 12 04:25:50 PM PDT 24 |
Peak memory | 146628 kb |
Host | smart-c77caf8e-ae0c-4146-b752-7d7e915a2fc7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2032165391 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 496.prim_prince_test.2032165391 |
Directory | /workspace/496.prim_prince_test/latest |
Test location | /workspace/coverage/default/497.prim_prince_test.2583307891 |
Short name | T221 |
Test name | |
Test status | |
Simulation time | 2569145397 ps |
CPU time | 44.46 seconds |
Started | Aug 12 04:25:36 PM PDT 24 |
Finished | Aug 12 04:26:31 PM PDT 24 |
Peak memory | 146684 kb |
Host | smart-4a433dd0-8540-41a8-96b4-8b85b7030210 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2583307891 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 497.prim_prince_test.2583307891 |
Directory | /workspace/497.prim_prince_test/latest |
Test location | /workspace/coverage/default/498.prim_prince_test.3218169266 |
Short name | T293 |
Test name | |
Test status | |
Simulation time | 2286711189 ps |
CPU time | 38.32 seconds |
Started | Aug 12 04:25:33 PM PDT 24 |
Finished | Aug 12 04:26:19 PM PDT 24 |
Peak memory | 146620 kb |
Host | smart-885e1f17-b7c8-4118-aed6-f291f5ae6388 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3218169266 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 498.prim_prince_test.3218169266 |
Directory | /workspace/498.prim_prince_test/latest |
Test location | /workspace/coverage/default/499.prim_prince_test.3897406672 |
Short name | T222 |
Test name | |
Test status | |
Simulation time | 3107331989 ps |
CPU time | 51.37 seconds |
Started | Aug 12 04:25:32 PM PDT 24 |
Finished | Aug 12 04:26:34 PM PDT 24 |
Peak memory | 146692 kb |
Host | smart-65af3889-2ae5-4ffd-9e7a-49b3297170b2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3897406672 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 499.prim_prince_test.3897406672 |
Directory | /workspace/499.prim_prince_test/latest |
Test location | /workspace/coverage/default/5.prim_prince_test.749228886 |
Short name | T426 |
Test name | |
Test status | |
Simulation time | 790858008 ps |
CPU time | 13.67 seconds |
Started | Aug 12 04:21:10 PM PDT 24 |
Finished | Aug 12 04:21:27 PM PDT 24 |
Peak memory | 145016 kb |
Host | smart-014fe426-5d7d-44b1-a1af-6bbdcb79c9fb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=749228886 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_prince_test.749228886 |
Directory | /workspace/5.prim_prince_test/latest |
Test location | /workspace/coverage/default/50.prim_prince_test.393997430 |
Short name | T440 |
Test name | |
Test status | |
Simulation time | 1271917282 ps |
CPU time | 20.82 seconds |
Started | Aug 12 04:21:14 PM PDT 24 |
Finished | Aug 12 04:21:40 PM PDT 24 |
Peak memory | 146264 kb |
Host | smart-51a24064-ca25-4312-8c80-f4aedb302da1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=393997430 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 50.prim_prince_test.393997430 |
Directory | /workspace/50.prim_prince_test/latest |
Test location | /workspace/coverage/default/51.prim_prince_test.1214144274 |
Short name | T323 |
Test name | |
Test status | |
Simulation time | 1732782070 ps |
CPU time | 28.36 seconds |
Started | Aug 12 04:22:18 PM PDT 24 |
Finished | Aug 12 04:22:51 PM PDT 24 |
Peak memory | 145592 kb |
Host | smart-6dd7bc50-a0f6-42c1-be03-b25e6a4e726e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1214144274 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 51.prim_prince_test.1214144274 |
Directory | /workspace/51.prim_prince_test/latest |
Test location | /workspace/coverage/default/52.prim_prince_test.3515657409 |
Short name | T460 |
Test name | |
Test status | |
Simulation time | 1216391262 ps |
CPU time | 21.29 seconds |
Started | Aug 12 04:24:47 PM PDT 24 |
Finished | Aug 12 04:25:13 PM PDT 24 |
Peak memory | 146596 kb |
Host | smart-5d7deb66-b707-4ac6-a179-c53c6fd41103 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3515657409 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 52.prim_prince_test.3515657409 |
Directory | /workspace/52.prim_prince_test/latest |
Test location | /workspace/coverage/default/53.prim_prince_test.387633173 |
Short name | T31 |
Test name | |
Test status | |
Simulation time | 3220623020 ps |
CPU time | 55.15 seconds |
Started | Aug 12 04:22:36 PM PDT 24 |
Finished | Aug 12 04:23:44 PM PDT 24 |
Peak memory | 146828 kb |
Host | smart-26b3dc7f-f598-4733-bc2c-9d6aee108aed |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=387633173 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 53.prim_prince_test.387633173 |
Directory | /workspace/53.prim_prince_test/latest |
Test location | /workspace/coverage/default/54.prim_prince_test.2274944346 |
Short name | T420 |
Test name | |
Test status | |
Simulation time | 1444889059 ps |
CPU time | 24.02 seconds |
Started | Aug 12 04:22:18 PM PDT 24 |
Finished | Aug 12 04:22:48 PM PDT 24 |
Peak memory | 146428 kb |
Host | smart-5af5493d-4945-4eff-9b12-bb948fff1cda |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2274944346 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 54.prim_prince_test.2274944346 |
Directory | /workspace/54.prim_prince_test/latest |
Test location | /workspace/coverage/default/55.prim_prince_test.2787707279 |
Short name | T496 |
Test name | |
Test status | |
Simulation time | 3108529198 ps |
CPU time | 54.1 seconds |
Started | Aug 12 04:23:16 PM PDT 24 |
Finished | Aug 12 04:24:24 PM PDT 24 |
Peak memory | 146692 kb |
Host | smart-92fe952d-3724-4059-b41f-9f1b9be41606 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2787707279 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 55.prim_prince_test.2787707279 |
Directory | /workspace/55.prim_prince_test/latest |
Test location | /workspace/coverage/default/56.prim_prince_test.2634654487 |
Short name | T430 |
Test name | |
Test status | |
Simulation time | 1251095698 ps |
CPU time | 20.19 seconds |
Started | Aug 12 04:26:32 PM PDT 24 |
Finished | Aug 12 04:26:56 PM PDT 24 |
Peak memory | 145664 kb |
Host | smart-6a20ffad-289d-432b-a396-845b52fe645a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2634654487 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 56.prim_prince_test.2634654487 |
Directory | /workspace/56.prim_prince_test/latest |
Test location | /workspace/coverage/default/57.prim_prince_test.1047382487 |
Short name | T448 |
Test name | |
Test status | |
Simulation time | 3427024716 ps |
CPU time | 55.66 seconds |
Started | Aug 12 04:21:17 PM PDT 24 |
Finished | Aug 12 04:22:23 PM PDT 24 |
Peak memory | 146268 kb |
Host | smart-f17a462a-4d5e-4a80-9ff8-bf0ac306e7d8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1047382487 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 57.prim_prince_test.1047382487 |
Directory | /workspace/57.prim_prince_test/latest |
Test location | /workspace/coverage/default/58.prim_prince_test.118301305 |
Short name | T206 |
Test name | |
Test status | |
Simulation time | 2062518541 ps |
CPU time | 34.73 seconds |
Started | Aug 12 04:21:18 PM PDT 24 |
Finished | Aug 12 04:22:00 PM PDT 24 |
Peak memory | 146160 kb |
Host | smart-63d959dd-766f-4cc3-8a8e-594a791eb129 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=118301305 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 58.prim_prince_test.118301305 |
Directory | /workspace/58.prim_prince_test/latest |
Test location | /workspace/coverage/default/59.prim_prince_test.3326664040 |
Short name | T38 |
Test name | |
Test status | |
Simulation time | 3374244222 ps |
CPU time | 55.87 seconds |
Started | Aug 12 04:22:16 PM PDT 24 |
Finished | Aug 12 04:23:24 PM PDT 24 |
Peak memory | 143856 kb |
Host | smart-47ca9fca-2785-457f-8f7e-38f88205bcb3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3326664040 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 59.prim_prince_test.3326664040 |
Directory | /workspace/59.prim_prince_test/latest |
Test location | /workspace/coverage/default/6.prim_prince_test.1879327787 |
Short name | T493 |
Test name | |
Test status | |
Simulation time | 2183498848 ps |
CPU time | 36.54 seconds |
Started | Aug 12 04:21:04 PM PDT 24 |
Finished | Aug 12 04:21:49 PM PDT 24 |
Peak memory | 145588 kb |
Host | smart-6a9fd1a9-80e4-4e25-a7f5-1dbd3f15ade1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1879327787 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_prince_test.1879327787 |
Directory | /workspace/6.prim_prince_test/latest |
Test location | /workspace/coverage/default/60.prim_prince_test.358058055 |
Short name | T131 |
Test name | |
Test status | |
Simulation time | 1080051252 ps |
CPU time | 18.41 seconds |
Started | Aug 12 04:22:17 PM PDT 24 |
Finished | Aug 12 04:22:40 PM PDT 24 |
Peak memory | 144364 kb |
Host | smart-972d8f7f-d37b-4191-ae18-2adeef2bf439 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=358058055 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 60.prim_prince_test.358058055 |
Directory | /workspace/60.prim_prince_test/latest |
Test location | /workspace/coverage/default/61.prim_prince_test.2701687014 |
Short name | T247 |
Test name | |
Test status | |
Simulation time | 2834539286 ps |
CPU time | 46.81 seconds |
Started | Aug 12 04:22:17 PM PDT 24 |
Finished | Aug 12 04:23:13 PM PDT 24 |
Peak memory | 146264 kb |
Host | smart-5da8395e-2736-4f50-afc1-ddff36b9b2bc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2701687014 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 61.prim_prince_test.2701687014 |
Directory | /workspace/61.prim_prince_test/latest |
Test location | /workspace/coverage/default/62.prim_prince_test.2683049564 |
Short name | T365 |
Test name | |
Test status | |
Simulation time | 1011648636 ps |
CPU time | 17.39 seconds |
Started | Aug 12 04:22:36 PM PDT 24 |
Finished | Aug 12 04:22:57 PM PDT 24 |
Peak memory | 146668 kb |
Host | smart-80ce4010-8c17-4788-ae97-3df69bbfffe9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2683049564 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 62.prim_prince_test.2683049564 |
Directory | /workspace/62.prim_prince_test/latest |
Test location | /workspace/coverage/default/63.prim_prince_test.2625491351 |
Short name | T3 |
Test name | |
Test status | |
Simulation time | 3556438279 ps |
CPU time | 57.69 seconds |
Started | Aug 12 04:27:04 PM PDT 24 |
Finished | Aug 12 04:28:13 PM PDT 24 |
Peak memory | 146152 kb |
Host | smart-b6c65719-ff92-4aec-af4d-1f92b2dbd690 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2625491351 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 63.prim_prince_test.2625491351 |
Directory | /workspace/63.prim_prince_test/latest |
Test location | /workspace/coverage/default/64.prim_prince_test.1065983833 |
Short name | T345 |
Test name | |
Test status | |
Simulation time | 776441257 ps |
CPU time | 13.1 seconds |
Started | Aug 12 04:21:16 PM PDT 24 |
Finished | Aug 12 04:21:32 PM PDT 24 |
Peak memory | 145636 kb |
Host | smart-db336b58-5b7e-46e1-92c3-75266dcaa0fa |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1065983833 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 64.prim_prince_test.1065983833 |
Directory | /workspace/64.prim_prince_test/latest |
Test location | /workspace/coverage/default/65.prim_prince_test.2310521899 |
Short name | T14 |
Test name | |
Test status | |
Simulation time | 2024182510 ps |
CPU time | 32.74 seconds |
Started | Aug 12 04:22:18 PM PDT 24 |
Finished | Aug 12 04:22:57 PM PDT 24 |
Peak memory | 145200 kb |
Host | smart-29db82c6-4308-49e8-b9a6-4089205fba5d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2310521899 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 65.prim_prince_test.2310521899 |
Directory | /workspace/65.prim_prince_test/latest |
Test location | /workspace/coverage/default/66.prim_prince_test.3889369630 |
Short name | T432 |
Test name | |
Test status | |
Simulation time | 2250279337 ps |
CPU time | 38.36 seconds |
Started | Aug 12 04:22:19 PM PDT 24 |
Finished | Aug 12 04:23:06 PM PDT 24 |
Peak memory | 146388 kb |
Host | smart-b6ea4773-b9f7-4a65-aac1-1733353ba014 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3889369630 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 66.prim_prince_test.3889369630 |
Directory | /workspace/66.prim_prince_test/latest |
Test location | /workspace/coverage/default/67.prim_prince_test.3779530108 |
Short name | T342 |
Test name | |
Test status | |
Simulation time | 1026016496 ps |
CPU time | 17.1 seconds |
Started | Aug 12 04:22:17 PM PDT 24 |
Finished | Aug 12 04:22:38 PM PDT 24 |
Peak memory | 146116 kb |
Host | smart-fc798998-5712-4899-ae41-d24123049095 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3779530108 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 67.prim_prince_test.3779530108 |
Directory | /workspace/67.prim_prince_test/latest |
Test location | /workspace/coverage/default/68.prim_prince_test.2934225897 |
Short name | T68 |
Test name | |
Test status | |
Simulation time | 1156780588 ps |
CPU time | 19.62 seconds |
Started | Aug 12 04:22:16 PM PDT 24 |
Finished | Aug 12 04:22:40 PM PDT 24 |
Peak memory | 144744 kb |
Host | smart-35efafa5-0851-4ab2-83e6-824c575de472 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2934225897 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 68.prim_prince_test.2934225897 |
Directory | /workspace/68.prim_prince_test/latest |
Test location | /workspace/coverage/default/69.prim_prince_test.360716884 |
Short name | T163 |
Test name | |
Test status | |
Simulation time | 2293607012 ps |
CPU time | 38.87 seconds |
Started | Aug 12 04:22:18 PM PDT 24 |
Finished | Aug 12 04:23:05 PM PDT 24 |
Peak memory | 146084 kb |
Host | smart-f74bbe0f-fe8a-470d-8dda-2872c88af1e9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=360716884 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 69.prim_prince_test.360716884 |
Directory | /workspace/69.prim_prince_test/latest |
Test location | /workspace/coverage/default/7.prim_prince_test.3456321770 |
Short name | T148 |
Test name | |
Test status | |
Simulation time | 1310666446 ps |
CPU time | 22.07 seconds |
Started | Aug 12 04:21:05 PM PDT 24 |
Finished | Aug 12 04:21:32 PM PDT 24 |
Peak memory | 146456 kb |
Host | smart-e5f63b17-c867-4c75-8ac6-354691accb0f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3456321770 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_prince_test.3456321770 |
Directory | /workspace/7.prim_prince_test/latest |
Test location | /workspace/coverage/default/70.prim_prince_test.4010338696 |
Short name | T213 |
Test name | |
Test status | |
Simulation time | 2217799838 ps |
CPU time | 37.11 seconds |
Started | Aug 12 04:22:17 PM PDT 24 |
Finished | Aug 12 04:23:02 PM PDT 24 |
Peak memory | 146068 kb |
Host | smart-30e51ec1-7e3a-4c5d-ace8-739c314f9cf9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4010338696 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 70.prim_prince_test.4010338696 |
Directory | /workspace/70.prim_prince_test/latest |
Test location | /workspace/coverage/default/71.prim_prince_test.1718092580 |
Short name | T246 |
Test name | |
Test status | |
Simulation time | 2222649722 ps |
CPU time | 38.41 seconds |
Started | Aug 12 04:21:40 PM PDT 24 |
Finished | Aug 12 04:22:28 PM PDT 24 |
Peak memory | 146676 kb |
Host | smart-588d8c56-8a70-4a90-ab50-7b2c4ae181fb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1718092580 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 71.prim_prince_test.1718092580 |
Directory | /workspace/71.prim_prince_test/latest |
Test location | /workspace/coverage/default/72.prim_prince_test.611134916 |
Short name | T161 |
Test name | |
Test status | |
Simulation time | 2172597701 ps |
CPU time | 37.4 seconds |
Started | Aug 12 04:21:40 PM PDT 24 |
Finished | Aug 12 04:22:27 PM PDT 24 |
Peak memory | 146676 kb |
Host | smart-7e6eb30b-ec49-44a0-9617-ea4e4cb9871c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=611134916 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 72.prim_prince_test.611134916 |
Directory | /workspace/72.prim_prince_test/latest |
Test location | /workspace/coverage/default/73.prim_prince_test.3266934504 |
Short name | T244 |
Test name | |
Test status | |
Simulation time | 1751178597 ps |
CPU time | 29.5 seconds |
Started | Aug 12 04:22:30 PM PDT 24 |
Finished | Aug 12 04:23:05 PM PDT 24 |
Peak memory | 146328 kb |
Host | smart-f7058f38-0e6e-44c9-b512-31d09fc9869c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3266934504 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 73.prim_prince_test.3266934504 |
Directory | /workspace/73.prim_prince_test/latest |
Test location | /workspace/coverage/default/74.prim_prince_test.242977817 |
Short name | T311 |
Test name | |
Test status | |
Simulation time | 1205012002 ps |
CPU time | 21.13 seconds |
Started | Aug 12 04:22:55 PM PDT 24 |
Finished | Aug 12 04:23:21 PM PDT 24 |
Peak memory | 146588 kb |
Host | smart-c15e648e-637b-421f-b787-22a87ff679e0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=242977817 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 74.prim_prince_test.242977817 |
Directory | /workspace/74.prim_prince_test/latest |
Test location | /workspace/coverage/default/75.prim_prince_test.1150213916 |
Short name | T16 |
Test name | |
Test status | |
Simulation time | 3460653020 ps |
CPU time | 59.36 seconds |
Started | Aug 12 04:22:36 PM PDT 24 |
Finished | Aug 12 04:23:49 PM PDT 24 |
Peak memory | 146472 kb |
Host | smart-d5c91e34-b18f-4f3a-b377-358e49609762 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1150213916 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 75.prim_prince_test.1150213916 |
Directory | /workspace/75.prim_prince_test/latest |
Test location | /workspace/coverage/default/76.prim_prince_test.4233993276 |
Short name | T105 |
Test name | |
Test status | |
Simulation time | 2028997585 ps |
CPU time | 33.16 seconds |
Started | Aug 12 04:26:01 PM PDT 24 |
Finished | Aug 12 04:26:41 PM PDT 24 |
Peak memory | 146568 kb |
Host | smart-e1f9c9fc-818d-4cda-819f-95d6ab8a3c1d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4233993276 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 76.prim_prince_test.4233993276 |
Directory | /workspace/76.prim_prince_test/latest |
Test location | /workspace/coverage/default/77.prim_prince_test.727924210 |
Short name | T354 |
Test name | |
Test status | |
Simulation time | 1744767910 ps |
CPU time | 29.9 seconds |
Started | Aug 12 04:24:11 PM PDT 24 |
Finished | Aug 12 04:24:47 PM PDT 24 |
Peak memory | 146504 kb |
Host | smart-cb553a1f-db34-4449-a037-bb47b6e3b32e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=727924210 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 77.prim_prince_test.727924210 |
Directory | /workspace/77.prim_prince_test/latest |
Test location | /workspace/coverage/default/78.prim_prince_test.1173378826 |
Short name | T266 |
Test name | |
Test status | |
Simulation time | 2440251132 ps |
CPU time | 40.43 seconds |
Started | Aug 12 04:26:32 PM PDT 24 |
Finished | Aug 12 04:27:21 PM PDT 24 |
Peak memory | 144072 kb |
Host | smart-e058445b-2278-4e72-bc4b-03ffb0aa4ce2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1173378826 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 78.prim_prince_test.1173378826 |
Directory | /workspace/78.prim_prince_test/latest |
Test location | /workspace/coverage/default/79.prim_prince_test.546106176 |
Short name | T346 |
Test name | |
Test status | |
Simulation time | 839918248 ps |
CPU time | 14.08 seconds |
Started | Aug 12 04:26:26 PM PDT 24 |
Finished | Aug 12 04:26:43 PM PDT 24 |
Peak memory | 146136 kb |
Host | smart-2365b253-4873-425f-bf07-f3dab6f48a44 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=546106176 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 79.prim_prince_test.546106176 |
Directory | /workspace/79.prim_prince_test/latest |
Test location | /workspace/coverage/default/8.prim_prince_test.3421796576 |
Short name | T264 |
Test name | |
Test status | |
Simulation time | 1681960954 ps |
CPU time | 28.64 seconds |
Started | Aug 12 04:21:10 PM PDT 24 |
Finished | Aug 12 04:21:45 PM PDT 24 |
Peak memory | 144964 kb |
Host | smart-ece5d089-f754-4574-9100-25b56c8c8b79 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3421796576 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_prince_test.3421796576 |
Directory | /workspace/8.prim_prince_test/latest |
Test location | /workspace/coverage/default/80.prim_prince_test.4129992515 |
Short name | T124 |
Test name | |
Test status | |
Simulation time | 2618024526 ps |
CPU time | 42.26 seconds |
Started | Aug 12 04:22:19 PM PDT 24 |
Finished | Aug 12 04:23:09 PM PDT 24 |
Peak memory | 146392 kb |
Host | smart-f3bf00d9-e4f7-4846-94e6-77820b2afdf8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4129992515 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 80.prim_prince_test.4129992515 |
Directory | /workspace/80.prim_prince_test/latest |
Test location | /workspace/coverage/default/81.prim_prince_test.2615640624 |
Short name | T313 |
Test name | |
Test status | |
Simulation time | 814270065 ps |
CPU time | 13.49 seconds |
Started | Aug 12 04:26:46 PM PDT 24 |
Finished | Aug 12 04:27:03 PM PDT 24 |
Peak memory | 146544 kb |
Host | smart-f01b22b2-8cde-490b-bb5f-c4baf06a4574 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2615640624 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 81.prim_prince_test.2615640624 |
Directory | /workspace/81.prim_prince_test/latest |
Test location | /workspace/coverage/default/82.prim_prince_test.3785441873 |
Short name | T191 |
Test name | |
Test status | |
Simulation time | 2228292080 ps |
CPU time | 37.59 seconds |
Started | Aug 12 04:24:25 PM PDT 24 |
Finished | Aug 12 04:25:11 PM PDT 24 |
Peak memory | 146664 kb |
Host | smart-d73d4fe7-710a-4c79-a0fc-8e16fa4f7766 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3785441873 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 82.prim_prince_test.3785441873 |
Directory | /workspace/82.prim_prince_test/latest |
Test location | /workspace/coverage/default/83.prim_prince_test.78456161 |
Short name | T87 |
Test name | |
Test status | |
Simulation time | 928914947 ps |
CPU time | 15.21 seconds |
Started | Aug 12 04:26:34 PM PDT 24 |
Finished | Aug 12 04:26:52 PM PDT 24 |
Peak memory | 146152 kb |
Host | smart-7b8c9863-f449-4423-b61a-a33eb7daee87 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=78456161 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 83.prim_prince_test.78456161 |
Directory | /workspace/83.prim_prince_test/latest |
Test location | /workspace/coverage/default/84.prim_prince_test.94358335 |
Short name | T32 |
Test name | |
Test status | |
Simulation time | 2627356031 ps |
CPU time | 45.54 seconds |
Started | Aug 12 04:24:43 PM PDT 24 |
Finished | Aug 12 04:25:39 PM PDT 24 |
Peak memory | 146664 kb |
Host | smart-15586f69-e9c0-4998-b956-f3e4149128a9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=94358335 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 84.prim_prince_test.94358335 |
Directory | /workspace/84.prim_prince_test/latest |
Test location | /workspace/coverage/default/85.prim_prince_test.3767589254 |
Short name | T282 |
Test name | |
Test status | |
Simulation time | 2512737260 ps |
CPU time | 41.09 seconds |
Started | Aug 12 04:26:33 PM PDT 24 |
Finished | Aug 12 04:27:23 PM PDT 24 |
Peak memory | 144500 kb |
Host | smart-4ecf9a45-060a-4604-8f77-33d9d762c53f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3767589254 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 85.prim_prince_test.3767589254 |
Directory | /workspace/85.prim_prince_test/latest |
Test location | /workspace/coverage/default/86.prim_prince_test.1841417851 |
Short name | T54 |
Test name | |
Test status | |
Simulation time | 1098162213 ps |
CPU time | 18.14 seconds |
Started | Aug 12 04:26:25 PM PDT 24 |
Finished | Aug 12 04:26:47 PM PDT 24 |
Peak memory | 146148 kb |
Host | smart-cc25c5c3-a521-43af-9cf9-7461057aa023 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1841417851 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 86.prim_prince_test.1841417851 |
Directory | /workspace/86.prim_prince_test/latest |
Test location | /workspace/coverage/default/87.prim_prince_test.3079453509 |
Short name | T295 |
Test name | |
Test status | |
Simulation time | 2613372103 ps |
CPU time | 42.29 seconds |
Started | Aug 12 04:26:38 PM PDT 24 |
Finished | Aug 12 04:27:28 PM PDT 24 |
Peak memory | 146196 kb |
Host | smart-37535ea1-0dd4-47a2-8227-7fd6dbbca30f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3079453509 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 87.prim_prince_test.3079453509 |
Directory | /workspace/87.prim_prince_test/latest |
Test location | /workspace/coverage/default/88.prim_prince_test.569559161 |
Short name | T436 |
Test name | |
Test status | |
Simulation time | 3731767613 ps |
CPU time | 60.11 seconds |
Started | Aug 12 04:26:18 PM PDT 24 |
Finished | Aug 12 04:27:29 PM PDT 24 |
Peak memory | 145828 kb |
Host | smart-2877614c-5046-4c4b-ab86-cd76b49212f2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=569559161 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 88.prim_prince_test.569559161 |
Directory | /workspace/88.prim_prince_test/latest |
Test location | /workspace/coverage/default/89.prim_prince_test.1284401910 |
Short name | T442 |
Test name | |
Test status | |
Simulation time | 2825626566 ps |
CPU time | 46.69 seconds |
Started | Aug 12 04:26:27 PM PDT 24 |
Finished | Aug 12 04:27:23 PM PDT 24 |
Peak memory | 146220 kb |
Host | smart-360d44fa-c5a3-4ad4-80a5-d37fec2e4e05 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1284401910 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 89.prim_prince_test.1284401910 |
Directory | /workspace/89.prim_prince_test/latest |
Test location | /workspace/coverage/default/9.prim_prince_test.2070324593 |
Short name | T152 |
Test name | |
Test status | |
Simulation time | 3428767852 ps |
CPU time | 57.68 seconds |
Started | Aug 12 04:21:10 PM PDT 24 |
Finished | Aug 12 04:22:21 PM PDT 24 |
Peak memory | 145204 kb |
Host | smart-7d46a599-f2c0-4079-9a1b-9f23236288a5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2070324593 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_prince_test.2070324593 |
Directory | /workspace/9.prim_prince_test/latest |
Test location | /workspace/coverage/default/90.prim_prince_test.2743691609 |
Short name | T91 |
Test name | |
Test status | |
Simulation time | 2676128446 ps |
CPU time | 42.86 seconds |
Started | Aug 12 04:25:45 PM PDT 24 |
Finished | Aug 12 04:26:36 PM PDT 24 |
Peak memory | 144784 kb |
Host | smart-193e806b-deac-4279-b384-718c8beeff98 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2743691609 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 90.prim_prince_test.2743691609 |
Directory | /workspace/90.prim_prince_test/latest |
Test location | /workspace/coverage/default/91.prim_prince_test.2900031672 |
Short name | T140 |
Test name | |
Test status | |
Simulation time | 3018433843 ps |
CPU time | 50.42 seconds |
Started | Aug 12 04:26:47 PM PDT 24 |
Finished | Aug 12 04:27:48 PM PDT 24 |
Peak memory | 146608 kb |
Host | smart-84b9f04d-63fc-4512-9544-1ea0362fb3b2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2900031672 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 91.prim_prince_test.2900031672 |
Directory | /workspace/91.prim_prince_test/latest |
Test location | /workspace/coverage/default/92.prim_prince_test.1637861754 |
Short name | T392 |
Test name | |
Test status | |
Simulation time | 3730113372 ps |
CPU time | 60.6 seconds |
Started | Aug 12 04:26:34 PM PDT 24 |
Finished | Aug 12 04:27:47 PM PDT 24 |
Peak memory | 146100 kb |
Host | smart-8f6f004a-55f4-4acc-91c7-b2f41d886557 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1637861754 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 92.prim_prince_test.1637861754 |
Directory | /workspace/92.prim_prince_test/latest |
Test location | /workspace/coverage/default/93.prim_prince_test.2436519171 |
Short name | T137 |
Test name | |
Test status | |
Simulation time | 1022437335 ps |
CPU time | 16.96 seconds |
Started | Aug 12 04:26:47 PM PDT 24 |
Finished | Aug 12 04:27:08 PM PDT 24 |
Peak memory | 146544 kb |
Host | smart-b2550378-1d33-496d-a694-4d91d3b931fb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2436519171 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 93.prim_prince_test.2436519171 |
Directory | /workspace/93.prim_prince_test/latest |
Test location | /workspace/coverage/default/94.prim_prince_test.1488384722 |
Short name | T289 |
Test name | |
Test status | |
Simulation time | 1147024904 ps |
CPU time | 18.93 seconds |
Started | Aug 12 04:26:51 PM PDT 24 |
Finished | Aug 12 04:27:14 PM PDT 24 |
Peak memory | 146296 kb |
Host | smart-e1e020db-378c-4999-b92c-2399a039b499 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1488384722 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 94.prim_prince_test.1488384722 |
Directory | /workspace/94.prim_prince_test/latest |
Test location | /workspace/coverage/default/95.prim_prince_test.335231161 |
Short name | T144 |
Test name | |
Test status | |
Simulation time | 2785339409 ps |
CPU time | 45.59 seconds |
Started | Aug 12 04:26:18 PM PDT 24 |
Finished | Aug 12 04:27:13 PM PDT 24 |
Peak memory | 146416 kb |
Host | smart-54faac33-77e8-4ad3-8fa5-b30496750495 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=335231161 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 95.prim_prince_test.335231161 |
Directory | /workspace/95.prim_prince_test/latest |
Test location | /workspace/coverage/default/96.prim_prince_test.476494604 |
Short name | T218 |
Test name | |
Test status | |
Simulation time | 1971323424 ps |
CPU time | 33.8 seconds |
Started | Aug 12 04:24:11 PM PDT 24 |
Finished | Aug 12 04:24:52 PM PDT 24 |
Peak memory | 146588 kb |
Host | smart-5edb30e6-4445-4d4c-8ace-1519c48879ae |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=476494604 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 96.prim_prince_test.476494604 |
Directory | /workspace/96.prim_prince_test/latest |
Test location | /workspace/coverage/default/97.prim_prince_test.4186921186 |
Short name | T260 |
Test name | |
Test status | |
Simulation time | 1716096188 ps |
CPU time | 29.47 seconds |
Started | Aug 12 04:23:30 PM PDT 24 |
Finished | Aug 12 04:24:06 PM PDT 24 |
Peak memory | 146568 kb |
Host | smart-a06d8e31-15a4-4be0-9582-ce1dedd4890f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4186921186 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 97.prim_prince_test.4186921186 |
Directory | /workspace/97.prim_prince_test/latest |
Test location | /workspace/coverage/default/98.prim_prince_test.761216188 |
Short name | T79 |
Test name | |
Test status | |
Simulation time | 1360471031 ps |
CPU time | 22.58 seconds |
Started | Aug 12 04:26:33 PM PDT 24 |
Finished | Aug 12 04:27:01 PM PDT 24 |
Peak memory | 144288 kb |
Host | smart-6734e6e9-bb78-4d11-939e-d316d2e77c92 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=761216188 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 98.prim_prince_test.761216188 |
Directory | /workspace/98.prim_prince_test/latest |
Test location | /workspace/coverage/default/99.prim_prince_test.4121041829 |
Short name | T39 |
Test name | |
Test status | |
Simulation time | 2996916298 ps |
CPU time | 48.67 seconds |
Started | Aug 12 04:26:33 PM PDT 24 |
Finished | Aug 12 04:27:31 PM PDT 24 |
Peak memory | 146156 kb |
Host | smart-04203c36-4027-45dc-acc8-f02ba0c325de |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4121041829 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 99.prim_prince_test.4121041829 |
Directory | /workspace/99.prim_prince_test/latest |
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