SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 | 100.00 | 100.00 |
T251 | /workspace/coverage/default/462.prim_prince_test.1886872131 | Aug 17 04:24:04 PM PDT 24 | Aug 17 04:24:22 PM PDT 24 | 875767546 ps | ||
T252 | /workspace/coverage/default/418.prim_prince_test.790463745 | Aug 17 04:25:48 PM PDT 24 | Aug 17 04:26:20 PM PDT 24 | 1621094905 ps | ||
T253 | /workspace/coverage/default/459.prim_prince_test.1414599133 | Aug 17 04:23:57 PM PDT 24 | Aug 17 04:24:51 PM PDT 24 | 2709336802 ps | ||
T254 | /workspace/coverage/default/0.prim_prince_test.952256895 | Aug 17 04:20:26 PM PDT 24 | Aug 17 04:21:18 PM PDT 24 | 2601813711 ps | ||
T255 | /workspace/coverage/default/389.prim_prince_test.3950012668 | Aug 17 04:25:34 PM PDT 24 | Aug 17 04:26:15 PM PDT 24 | 2144419105 ps | ||
T256 | /workspace/coverage/default/229.prim_prince_test.455780473 | Aug 17 04:24:53 PM PDT 24 | Aug 17 04:26:03 PM PDT 24 | 3618772409 ps | ||
T257 | /workspace/coverage/default/492.prim_prince_test.275501011 | Aug 17 04:24:09 PM PDT 24 | Aug 17 04:25:22 PM PDT 24 | 3519940446 ps | ||
T258 | /workspace/coverage/default/294.prim_prince_test.1023199437 | Aug 17 04:24:34 PM PDT 24 | Aug 17 04:24:59 PM PDT 24 | 1182621483 ps | ||
T259 | /workspace/coverage/default/108.prim_prince_test.3778814099 | Aug 17 04:21:13 PM PDT 24 | Aug 17 04:21:54 PM PDT 24 | 2016738421 ps | ||
T260 | /workspace/coverage/default/373.prim_prince_test.559767224 | Aug 17 04:25:02 PM PDT 24 | Aug 17 04:25:50 PM PDT 24 | 2378611244 ps | ||
T261 | /workspace/coverage/default/227.prim_prince_test.327812924 | Aug 17 04:25:28 PM PDT 24 | Aug 17 04:26:11 PM PDT 24 | 2237620829 ps | ||
T262 | /workspace/coverage/default/101.prim_prince_test.1149195604 | Aug 17 04:22:22 PM PDT 24 | Aug 17 04:22:42 PM PDT 24 | 1009112167 ps | ||
T263 | /workspace/coverage/default/376.prim_prince_test.2471454558 | Aug 17 04:26:04 PM PDT 24 | Aug 17 04:26:53 PM PDT 24 | 2576116556 ps | ||
T264 | /workspace/coverage/default/499.prim_prince_test.304738015 | Aug 17 04:26:14 PM PDT 24 | Aug 17 04:27:22 PM PDT 24 | 3545449856 ps | ||
T265 | /workspace/coverage/default/366.prim_prince_test.2613335993 | Aug 17 04:24:52 PM PDT 24 | Aug 17 04:25:20 PM PDT 24 | 1422518617 ps | ||
T266 | /workspace/coverage/default/21.prim_prince_test.4080910898 | Aug 17 04:20:26 PM PDT 24 | Aug 17 04:21:10 PM PDT 24 | 2212784796 ps | ||
T267 | /workspace/coverage/default/194.prim_prince_test.383908547 | Aug 17 04:21:59 PM PDT 24 | Aug 17 04:22:22 PM PDT 24 | 1121994796 ps | ||
T268 | /workspace/coverage/default/91.prim_prince_test.402458599 | Aug 17 04:25:39 PM PDT 24 | Aug 17 04:26:33 PM PDT 24 | 2810658266 ps | ||
T269 | /workspace/coverage/default/52.prim_prince_test.859173327 | Aug 17 04:20:26 PM PDT 24 | Aug 17 04:21:02 PM PDT 24 | 1758543566 ps | ||
T270 | /workspace/coverage/default/42.prim_prince_test.3717664410 | Aug 17 04:20:25 PM PDT 24 | Aug 17 04:21:24 PM PDT 24 | 2992370545 ps | ||
T271 | /workspace/coverage/default/454.prim_prince_test.2031458429 | Aug 17 04:25:06 PM PDT 24 | Aug 17 04:25:42 PM PDT 24 | 1825864890 ps | ||
T272 | /workspace/coverage/default/381.prim_prince_test.2867869337 | Aug 17 04:23:13 PM PDT 24 | Aug 17 04:24:01 PM PDT 24 | 2247180318 ps | ||
T273 | /workspace/coverage/default/286.prim_prince_test.3588683168 | Aug 17 04:22:15 PM PDT 24 | Aug 17 04:22:49 PM PDT 24 | 1667538053 ps | ||
T274 | /workspace/coverage/default/18.prim_prince_test.159612777 | Aug 17 04:20:25 PM PDT 24 | Aug 17 04:21:10 PM PDT 24 | 2300377795 ps | ||
T275 | /workspace/coverage/default/36.prim_prince_test.3436271604 | Aug 17 04:20:26 PM PDT 24 | Aug 17 04:21:29 PM PDT 24 | 3138013765 ps | ||
T276 | /workspace/coverage/default/338.prim_prince_test.320868332 | Aug 17 04:25:33 PM PDT 24 | Aug 17 04:25:47 PM PDT 24 | 758085698 ps | ||
T277 | /workspace/coverage/default/216.prim_prince_test.2469237716 | Aug 17 04:22:19 PM PDT 24 | Aug 17 04:23:35 PM PDT 24 | 3653983807 ps | ||
T278 | /workspace/coverage/default/221.prim_prince_test.848204208 | Aug 17 04:23:23 PM PDT 24 | Aug 17 04:24:34 PM PDT 24 | 3499701524 ps | ||
T279 | /workspace/coverage/default/128.prim_prince_test.1484474960 | Aug 17 04:25:34 PM PDT 24 | Aug 17 04:26:23 PM PDT 24 | 2598144562 ps | ||
T280 | /workspace/coverage/default/171.prim_prince_test.3627477970 | Aug 17 04:21:14 PM PDT 24 | Aug 17 04:21:31 PM PDT 24 | 802707232 ps | ||
T281 | /workspace/coverage/default/62.prim_prince_test.124703834 | Aug 17 04:21:26 PM PDT 24 | Aug 17 04:21:46 PM PDT 24 | 1052570243 ps | ||
T282 | /workspace/coverage/default/134.prim_prince_test.591589026 | Aug 17 04:22:47 PM PDT 24 | Aug 17 04:23:56 PM PDT 24 | 3284970000 ps | ||
T283 | /workspace/coverage/default/479.prim_prince_test.3092438016 | Aug 17 04:24:31 PM PDT 24 | Aug 17 04:25:04 PM PDT 24 | 1622339966 ps | ||
T284 | /workspace/coverage/default/32.prim_prince_test.493125990 | Aug 17 04:20:25 PM PDT 24 | Aug 17 04:20:45 PM PDT 24 | 967538386 ps | ||
T285 | /workspace/coverage/default/44.prim_prince_test.3305050150 | Aug 17 04:20:26 PM PDT 24 | Aug 17 04:21:22 PM PDT 24 | 2903969891 ps | ||
T286 | /workspace/coverage/default/31.prim_prince_test.1476851368 | Aug 17 04:20:26 PM PDT 24 | Aug 17 04:21:13 PM PDT 24 | 2484586834 ps | ||
T287 | /workspace/coverage/default/432.prim_prince_test.1932299233 | Aug 17 04:24:56 PM PDT 24 | Aug 17 04:25:52 PM PDT 24 | 2963846141 ps | ||
T288 | /workspace/coverage/default/487.prim_prince_test.3491555253 | Aug 17 04:24:10 PM PDT 24 | Aug 17 04:24:41 PM PDT 24 | 1495865731 ps | ||
T289 | /workspace/coverage/default/35.prim_prince_test.1560407414 | Aug 17 04:20:22 PM PDT 24 | Aug 17 04:21:28 PM PDT 24 | 3210509385 ps | ||
T290 | /workspace/coverage/default/24.prim_prince_test.2525791376 | Aug 17 04:20:26 PM PDT 24 | Aug 17 04:21:08 PM PDT 24 | 2194981666 ps | ||
T291 | /workspace/coverage/default/33.prim_prince_test.4094014207 | Aug 17 04:20:22 PM PDT 24 | Aug 17 04:20:54 PM PDT 24 | 1608068740 ps | ||
T292 | /workspace/coverage/default/341.prim_prince_test.2049496164 | Aug 17 04:23:16 PM PDT 24 | Aug 17 04:24:04 PM PDT 24 | 2353898803 ps | ||
T293 | /workspace/coverage/default/287.prim_prince_test.226916549 | Aug 17 04:25:34 PM PDT 24 | Aug 17 04:26:30 PM PDT 24 | 2942456606 ps | ||
T294 | /workspace/coverage/default/51.prim_prince_test.1877911458 | Aug 17 04:20:26 PM PDT 24 | Aug 17 04:21:31 PM PDT 24 | 3208990635 ps | ||
T295 | /workspace/coverage/default/315.prim_prince_test.2514006626 | Aug 17 04:24:11 PM PDT 24 | Aug 17 04:25:26 PM PDT 24 | 3639980436 ps | ||
T296 | /workspace/coverage/default/411.prim_prince_test.2217645615 | Aug 17 04:23:21 PM PDT 24 | Aug 17 04:24:05 PM PDT 24 | 2081315707 ps | ||
T297 | /workspace/coverage/default/56.prim_prince_test.3004369211 | Aug 17 04:20:26 PM PDT 24 | Aug 17 04:21:35 PM PDT 24 | 3686727135 ps | ||
T298 | /workspace/coverage/default/117.prim_prince_test.4190954770 | Aug 17 04:25:24 PM PDT 24 | Aug 17 04:26:12 PM PDT 24 | 2480337107 ps | ||
T299 | /workspace/coverage/default/141.prim_prince_test.3114797645 | Aug 17 04:25:47 PM PDT 24 | Aug 17 04:26:42 PM PDT 24 | 2775914451 ps | ||
T300 | /workspace/coverage/default/463.prim_prince_test.3164301459 | Aug 17 04:24:00 PM PDT 24 | Aug 17 04:24:55 PM PDT 24 | 2651257183 ps | ||
T301 | /workspace/coverage/default/130.prim_prince_test.2649651762 | Aug 17 04:25:33 PM PDT 24 | Aug 17 04:26:32 PM PDT 24 | 3090926548 ps | ||
T302 | /workspace/coverage/default/88.prim_prince_test.3784796735 | Aug 17 04:25:39 PM PDT 24 | Aug 17 04:26:40 PM PDT 24 | 3202526198 ps | ||
T303 | /workspace/coverage/default/127.prim_prince_test.682711081 | Aug 17 04:25:32 PM PDT 24 | Aug 17 04:26:36 PM PDT 24 | 3380233916 ps | ||
T304 | /workspace/coverage/default/261.prim_prince_test.3125211220 | Aug 17 04:23:23 PM PDT 24 | Aug 17 04:24:10 PM PDT 24 | 2238676976 ps | ||
T305 | /workspace/coverage/default/81.prim_prince_test.1216192687 | Aug 17 04:25:33 PM PDT 24 | Aug 17 04:26:32 PM PDT 24 | 2677939655 ps | ||
T306 | /workspace/coverage/default/115.prim_prince_test.332369823 | Aug 17 04:22:58 PM PDT 24 | Aug 17 04:23:55 PM PDT 24 | 2818721868 ps | ||
T307 | /workspace/coverage/default/65.prim_prince_test.4195224986 | Aug 17 04:21:34 PM PDT 24 | Aug 17 04:22:04 PM PDT 24 | 1648156394 ps | ||
T308 | /workspace/coverage/default/269.prim_prince_test.3932583380 | Aug 17 04:25:47 PM PDT 24 | Aug 17 04:26:46 PM PDT 24 | 2736357659 ps | ||
T309 | /workspace/coverage/default/250.prim_prince_test.4291165867 | Aug 17 04:25:26 PM PDT 24 | Aug 17 04:26:05 PM PDT 24 | 2045569812 ps | ||
T310 | /workspace/coverage/default/361.prim_prince_test.193949404 | Aug 17 04:25:45 PM PDT 24 | Aug 17 04:26:18 PM PDT 24 | 1743727925 ps | ||
T311 | /workspace/coverage/default/100.prim_prince_test.1759787037 | Aug 17 04:22:10 PM PDT 24 | Aug 17 04:23:20 PM PDT 24 | 3399583373 ps | ||
T312 | /workspace/coverage/default/312.prim_prince_test.1289319258 | Aug 17 04:25:47 PM PDT 24 | Aug 17 04:26:43 PM PDT 24 | 2870774011 ps | ||
T313 | /workspace/coverage/default/471.prim_prince_test.2515504487 | Aug 17 04:23:59 PM PDT 24 | Aug 17 04:24:52 PM PDT 24 | 2476801249 ps | ||
T314 | /workspace/coverage/default/197.prim_prince_test.970966096 | Aug 17 04:22:00 PM PDT 24 | Aug 17 04:23:04 PM PDT 24 | 3151554746 ps | ||
T315 | /workspace/coverage/default/441.prim_prince_test.48496594 | Aug 17 04:24:56 PM PDT 24 | Aug 17 04:25:13 PM PDT 24 | 870611994 ps | ||
T316 | /workspace/coverage/default/116.prim_prince_test.1370233248 | Aug 17 04:25:34 PM PDT 24 | Aug 17 04:26:47 PM PDT 24 | 3698482903 ps | ||
T317 | /workspace/coverage/default/470.prim_prince_test.645665444 | Aug 17 04:24:05 PM PDT 24 | Aug 17 04:24:50 PM PDT 24 | 2181252885 ps | ||
T318 | /workspace/coverage/default/339.prim_prince_test.2275108303 | Aug 17 04:25:46 PM PDT 24 | Aug 17 04:26:21 PM PDT 24 | 1749258968 ps | ||
T319 | /workspace/coverage/default/220.prim_prince_test.2882923563 | Aug 17 04:25:36 PM PDT 24 | Aug 17 04:25:53 PM PDT 24 | 863696364 ps | ||
T320 | /workspace/coverage/default/168.prim_prince_test.1426373009 | Aug 17 04:24:54 PM PDT 24 | Aug 17 04:25:38 PM PDT 24 | 2239841514 ps | ||
T321 | /workspace/coverage/default/275.prim_prince_test.2483063059 | Aug 17 04:22:53 PM PDT 24 | Aug 17 04:23:34 PM PDT 24 | 1954060866 ps | ||
T322 | /workspace/coverage/default/374.prim_prince_test.3687815439 | Aug 17 04:23:03 PM PDT 24 | Aug 17 04:23:21 PM PDT 24 | 889158507 ps | ||
T323 | /workspace/coverage/default/328.prim_prince_test.2082800291 | Aug 17 04:25:37 PM PDT 24 | Aug 17 04:26:21 PM PDT 24 | 2019190958 ps | ||
T324 | /workspace/coverage/default/367.prim_prince_test.4152079893 | Aug 17 04:25:28 PM PDT 24 | Aug 17 04:26:27 PM PDT 24 | 3053777842 ps | ||
T325 | /workspace/coverage/default/80.prim_prince_test.3506590692 | Aug 17 04:24:50 PM PDT 24 | Aug 17 04:25:35 PM PDT 24 | 2273230324 ps | ||
T326 | /workspace/coverage/default/156.prim_prince_test.824444401 | Aug 17 04:25:26 PM PDT 24 | Aug 17 04:26:13 PM PDT 24 | 2401607331 ps | ||
T327 | /workspace/coverage/default/431.prim_prince_test.194812828 | Aug 17 04:25:48 PM PDT 24 | Aug 17 04:26:22 PM PDT 24 | 1748126237 ps | ||
T328 | /workspace/coverage/default/164.prim_prince_test.1996328701 | Aug 17 04:21:13 PM PDT 24 | Aug 17 04:21:53 PM PDT 24 | 1929559774 ps | ||
T329 | /workspace/coverage/default/327.prim_prince_test.2179032105 | Aug 17 04:25:34 PM PDT 24 | Aug 17 04:26:25 PM PDT 24 | 2754258716 ps | ||
T330 | /workspace/coverage/default/283.prim_prince_test.2977058325 | Aug 17 04:25:34 PM PDT 24 | Aug 17 04:25:53 PM PDT 24 | 948259406 ps | ||
T331 | /workspace/coverage/default/192.prim_prince_test.582974840 | Aug 17 04:26:01 PM PDT 24 | Aug 17 04:26:30 PM PDT 24 | 1431227622 ps | ||
T332 | /workspace/coverage/default/387.prim_prince_test.4194834460 | Aug 17 04:25:48 PM PDT 24 | Aug 17 04:26:59 PM PDT 24 | 3684423146 ps | ||
T333 | /workspace/coverage/default/234.prim_prince_test.3715946520 | Aug 17 04:24:14 PM PDT 24 | Aug 17 04:24:59 PM PDT 24 | 2240292076 ps | ||
T334 | /workspace/coverage/default/187.prim_prince_test.1052077995 | Aug 17 04:21:33 PM PDT 24 | Aug 17 04:22:08 PM PDT 24 | 1700156789 ps | ||
T335 | /workspace/coverage/default/445.prim_prince_test.3729501395 | Aug 17 04:25:40 PM PDT 24 | Aug 17 04:25:57 PM PDT 24 | 879261597 ps | ||
T336 | /workspace/coverage/default/353.prim_prince_test.1635954719 | Aug 17 04:25:12 PM PDT 24 | Aug 17 04:26:01 PM PDT 24 | 2456545134 ps | ||
T337 | /workspace/coverage/default/308.prim_prince_test.659214909 | Aug 17 04:26:04 PM PDT 24 | Aug 17 04:26:42 PM PDT 24 | 1984917802 ps | ||
T338 | /workspace/coverage/default/149.prim_prince_test.1389252609 | Aug 17 04:23:05 PM PDT 24 | Aug 17 04:23:38 PM PDT 24 | 1694449178 ps | ||
T339 | /workspace/coverage/default/494.prim_prince_test.4252929002 | Aug 17 04:24:12 PM PDT 24 | Aug 17 04:25:16 PM PDT 24 | 3142711313 ps | ||
T340 | /workspace/coverage/default/90.prim_prince_test.625336802 | Aug 17 04:25:33 PM PDT 24 | Aug 17 04:26:44 PM PDT 24 | 3637675349 ps | ||
T341 | /workspace/coverage/default/218.prim_prince_test.1054886134 | Aug 17 04:25:37 PM PDT 24 | Aug 17 04:26:17 PM PDT 24 | 2055296016 ps | ||
T342 | /workspace/coverage/default/397.prim_prince_test.3388373244 | Aug 17 04:25:06 PM PDT 24 | Aug 17 04:25:28 PM PDT 24 | 1112090278 ps | ||
T343 | /workspace/coverage/default/262.prim_prince_test.4147091805 | Aug 17 04:25:35 PM PDT 24 | Aug 17 04:25:50 PM PDT 24 | 807399710 ps | ||
T344 | /workspace/coverage/default/469.prim_prince_test.1169909852 | Aug 17 04:23:59 PM PDT 24 | Aug 17 04:25:00 PM PDT 24 | 2975560271 ps | ||
T345 | /workspace/coverage/default/193.prim_prince_test.1427288353 | Aug 17 04:22:30 PM PDT 24 | Aug 17 04:22:53 PM PDT 24 | 1131963836 ps | ||
T346 | /workspace/coverage/default/490.prim_prince_test.3061597023 | Aug 17 04:24:10 PM PDT 24 | Aug 17 04:25:06 PM PDT 24 | 2623425234 ps | ||
T347 | /workspace/coverage/default/79.prim_prince_test.3400145889 | Aug 17 04:22:22 PM PDT 24 | Aug 17 04:23:00 PM PDT 24 | 2009603728 ps | ||
T348 | /workspace/coverage/default/289.prim_prince_test.1649707383 | Aug 17 04:25:20 PM PDT 24 | Aug 17 04:26:31 PM PDT 24 | 3515645768 ps | ||
T349 | /workspace/coverage/default/435.prim_prince_test.3060545475 | Aug 17 04:24:55 PM PDT 24 | Aug 17 04:25:20 PM PDT 24 | 1268480548 ps | ||
T350 | /workspace/coverage/default/482.prim_prince_test.1123436602 | Aug 17 04:26:14 PM PDT 24 | Aug 17 04:26:32 PM PDT 24 | 855571473 ps | ||
T351 | /workspace/coverage/default/249.prim_prince_test.727683808 | Aug 17 04:25:24 PM PDT 24 | Aug 17 04:26:16 PM PDT 24 | 2654216425 ps | ||
T352 | /workspace/coverage/default/447.prim_prince_test.3582497451 | Aug 17 04:25:06 PM PDT 24 | Aug 17 04:25:37 PM PDT 24 | 1579350752 ps | ||
T353 | /workspace/coverage/default/106.prim_prince_test.4113797048 | Aug 17 04:25:32 PM PDT 24 | Aug 17 04:26:16 PM PDT 24 | 2237590033 ps | ||
T354 | /workspace/coverage/default/58.prim_prince_test.2226167657 | Aug 17 04:20:22 PM PDT 24 | Aug 17 04:20:42 PM PDT 24 | 974353370 ps | ||
T355 | /workspace/coverage/default/202.prim_prince_test.1667621206 | Aug 17 04:25:14 PM PDT 24 | Aug 17 04:25:58 PM PDT 24 | 2374710838 ps | ||
T356 | /workspace/coverage/default/416.prim_prince_test.3957857128 | Aug 17 04:23:32 PM PDT 24 | Aug 17 04:24:33 PM PDT 24 | 2965897822 ps | ||
T357 | /workspace/coverage/default/306.prim_prince_test.3040522260 | Aug 17 04:25:35 PM PDT 24 | Aug 17 04:25:54 PM PDT 24 | 990065113 ps | ||
T358 | /workspace/coverage/default/252.prim_prince_test.194845811 | Aug 17 04:25:48 PM PDT 24 | Aug 17 04:26:24 PM PDT 24 | 1800883536 ps | ||
T359 | /workspace/coverage/default/260.prim_prince_test.1528880598 | Aug 17 04:23:50 PM PDT 24 | Aug 17 04:24:16 PM PDT 24 | 1294915990 ps | ||
T360 | /workspace/coverage/default/14.prim_prince_test.2419262923 | Aug 17 04:21:28 PM PDT 24 | Aug 17 04:22:37 PM PDT 24 | 3571216262 ps | ||
T361 | /workspace/coverage/default/295.prim_prince_test.1890249343 | Aug 17 04:23:13 PM PDT 24 | Aug 17 04:24:17 PM PDT 24 | 3142909586 ps | ||
T362 | /workspace/coverage/default/3.prim_prince_test.3399810060 | Aug 17 04:20:22 PM PDT 24 | Aug 17 04:21:22 PM PDT 24 | 2981459920 ps | ||
T363 | /workspace/coverage/default/69.prim_prince_test.1459136509 | Aug 17 04:22:12 PM PDT 24 | Aug 17 04:23:06 PM PDT 24 | 2628757098 ps | ||
T364 | /workspace/coverage/default/124.prim_prince_test.2086893138 | Aug 17 04:23:50 PM PDT 24 | Aug 17 04:24:12 PM PDT 24 | 1122548742 ps | ||
T365 | /workspace/coverage/default/178.prim_prince_test.3281771941 | Aug 17 04:25:11 PM PDT 24 | Aug 17 04:25:35 PM PDT 24 | 1273669228 ps | ||
T366 | /workspace/coverage/default/393.prim_prince_test.1257166175 | Aug 17 04:23:20 PM PDT 24 | Aug 17 04:23:58 PM PDT 24 | 1861431025 ps | ||
T367 | /workspace/coverage/default/345.prim_prince_test.2477615095 | Aug 17 04:25:46 PM PDT 24 | Aug 17 04:26:39 PM PDT 24 | 2737069261 ps | ||
T368 | /workspace/coverage/default/297.prim_prince_test.2959509026 | Aug 17 04:23:15 PM PDT 24 | Aug 17 04:23:42 PM PDT 24 | 1277593856 ps | ||
T369 | /workspace/coverage/default/383.prim_prince_test.778918401 | Aug 17 04:23:09 PM PDT 24 | Aug 17 04:23:48 PM PDT 24 | 1851528905 ps | ||
T370 | /workspace/coverage/default/424.prim_prince_test.260254449 | Aug 17 04:24:59 PM PDT 24 | Aug 17 04:25:16 PM PDT 24 | 850963150 ps | ||
T371 | /workspace/coverage/default/334.prim_prince_test.3235836282 | Aug 17 04:22:44 PM PDT 24 | Aug 17 04:23:14 PM PDT 24 | 1388457294 ps | ||
T372 | /workspace/coverage/default/380.prim_prince_test.4023065566 | Aug 17 04:25:04 PM PDT 24 | Aug 17 04:25:32 PM PDT 24 | 1425604584 ps | ||
T373 | /workspace/coverage/default/468.prim_prince_test.909825171 | Aug 17 04:23:58 PM PDT 24 | Aug 17 04:24:32 PM PDT 24 | 1699043155 ps | ||
T374 | /workspace/coverage/default/151.prim_prince_test.2883727714 | Aug 17 04:24:03 PM PDT 24 | Aug 17 04:24:27 PM PDT 24 | 1202104476 ps | ||
T375 | /workspace/coverage/default/7.prim_prince_test.2783029585 | Aug 17 04:20:23 PM PDT 24 | Aug 17 04:21:13 PM PDT 24 | 2516081934 ps | ||
T376 | /workspace/coverage/default/2.prim_prince_test.1646277130 | Aug 17 04:20:27 PM PDT 24 | Aug 17 04:21:35 PM PDT 24 | 3328551448 ps | ||
T377 | /workspace/coverage/default/241.prim_prince_test.2334577748 | Aug 17 04:25:22 PM PDT 24 | Aug 17 04:26:13 PM PDT 24 | 2564234048 ps | ||
T378 | /workspace/coverage/default/293.prim_prince_test.993288163 | Aug 17 04:26:08 PM PDT 24 | Aug 17 04:27:00 PM PDT 24 | 2497874084 ps | ||
T379 | /workspace/coverage/default/185.prim_prince_test.211913868 | Aug 17 04:21:24 PM PDT 24 | Aug 17 04:22:14 PM PDT 24 | 2462583499 ps | ||
T380 | /workspace/coverage/default/310.prim_prince_test.2097942136 | Aug 17 04:26:01 PM PDT 24 | Aug 17 04:26:18 PM PDT 24 | 891401705 ps | ||
T381 | /workspace/coverage/default/188.prim_prince_test.1010423803 | Aug 17 04:21:20 PM PDT 24 | Aug 17 04:22:02 PM PDT 24 | 2004116719 ps | ||
T382 | /workspace/coverage/default/488.prim_prince_test.658626025 | Aug 17 04:26:13 PM PDT 24 | Aug 17 04:26:30 PM PDT 24 | 810572971 ps | ||
T383 | /workspace/coverage/default/450.prim_prince_test.2257330778 | Aug 17 04:25:07 PM PDT 24 | Aug 17 04:25:29 PM PDT 24 | 1095989039 ps | ||
T384 | /workspace/coverage/default/369.prim_prince_test.958757910 | Aug 17 04:24:52 PM PDT 24 | Aug 17 04:25:42 PM PDT 24 | 2582553971 ps | ||
T385 | /workspace/coverage/default/211.prim_prince_test.187975962 | Aug 17 04:25:33 PM PDT 24 | Aug 17 04:26:41 PM PDT 24 | 3645389643 ps | ||
T386 | /workspace/coverage/default/321.prim_prince_test.1710459323 | Aug 17 04:25:22 PM PDT 24 | Aug 17 04:26:27 PM PDT 24 | 3291866764 ps | ||
T387 | /workspace/coverage/default/268.prim_prince_test.3241603559 | Aug 17 04:22:46 PM PDT 24 | Aug 17 04:23:21 PM PDT 24 | 1745602275 ps | ||
T388 | /workspace/coverage/default/107.prim_prince_test.3027435410 | Aug 17 04:24:59 PM PDT 24 | Aug 17 04:26:01 PM PDT 24 | 3267906848 ps | ||
T389 | /workspace/coverage/default/37.prim_prince_test.3781310098 | Aug 17 04:20:26 PM PDT 24 | Aug 17 04:21:10 PM PDT 24 | 2113088235 ps | ||
T390 | /workspace/coverage/default/495.prim_prince_test.3570374515 | Aug 17 04:24:09 PM PDT 24 | Aug 17 04:25:05 PM PDT 24 | 2617294307 ps | ||
T391 | /workspace/coverage/default/77.prim_prince_test.2072226664 | Aug 17 04:25:34 PM PDT 24 | Aug 17 04:26:22 PM PDT 24 | 2469599842 ps | ||
T392 | /workspace/coverage/default/132.prim_prince_test.2274339555 | Aug 17 04:25:34 PM PDT 24 | Aug 17 04:25:53 PM PDT 24 | 986548482 ps | ||
T393 | /workspace/coverage/default/109.prim_prince_test.3026399252 | Aug 17 04:25:33 PM PDT 24 | Aug 17 04:26:32 PM PDT 24 | 3057471785 ps | ||
T394 | /workspace/coverage/default/53.prim_prince_test.2679614616 | Aug 17 04:20:27 PM PDT 24 | Aug 17 04:21:01 PM PDT 24 | 1704847237 ps | ||
T395 | /workspace/coverage/default/190.prim_prince_test.3300956344 | Aug 17 04:24:04 PM PDT 24 | Aug 17 04:25:21 PM PDT 24 | 3644050296 ps | ||
T396 | /workspace/coverage/default/493.prim_prince_test.83549221 | Aug 17 04:24:10 PM PDT 24 | Aug 17 04:25:14 PM PDT 24 | 3130309372 ps | ||
T397 | /workspace/coverage/default/199.prim_prince_test.1119878624 | Aug 17 04:21:38 PM PDT 24 | Aug 17 04:22:05 PM PDT 24 | 1305819461 ps | ||
T398 | /workspace/coverage/default/29.prim_prince_test.2112895301 | Aug 17 04:22:30 PM PDT 24 | Aug 17 04:23:22 PM PDT 24 | 2559383265 ps | ||
T399 | /workspace/coverage/default/420.prim_prince_test.2848264818 | Aug 17 04:23:45 PM PDT 24 | Aug 17 04:24:20 PM PDT 24 | 1724039411 ps | ||
T400 | /workspace/coverage/default/436.prim_prince_test.3693003334 | Aug 17 04:25:08 PM PDT 24 | Aug 17 04:26:03 PM PDT 24 | 2696202880 ps | ||
T401 | /workspace/coverage/default/318.prim_prince_test.2889454992 | Aug 17 04:22:39 PM PDT 24 | Aug 17 04:23:20 PM PDT 24 | 1891229146 ps | ||
T402 | /workspace/coverage/default/225.prim_prince_test.1627771800 | Aug 17 04:22:36 PM PDT 24 | Aug 17 04:23:23 PM PDT 24 | 2204991567 ps | ||
T403 | /workspace/coverage/default/276.prim_prince_test.3148375821 | Aug 17 04:26:08 PM PDT 24 | Aug 17 04:27:17 PM PDT 24 | 3327633172 ps | ||
T404 | /workspace/coverage/default/169.prim_prince_test.3419309367 | Aug 17 04:22:07 PM PDT 24 | Aug 17 04:23:13 PM PDT 24 | 3184825804 ps | ||
T405 | /workspace/coverage/default/301.prim_prince_test.133571182 | Aug 17 04:25:35 PM PDT 24 | Aug 17 04:26:01 PM PDT 24 | 1346308904 ps | ||
T406 | /workspace/coverage/default/119.prim_prince_test.1697582557 | Aug 17 04:25:33 PM PDT 24 | Aug 17 04:26:22 PM PDT 24 | 2540612418 ps | ||
T407 | /workspace/coverage/default/352.prim_prince_test.1032571953 | Aug 17 04:25:43 PM PDT 24 | Aug 17 04:26:45 PM PDT 24 | 3282096974 ps | ||
T408 | /workspace/coverage/default/17.prim_prince_test.412724270 | Aug 17 04:20:28 PM PDT 24 | Aug 17 04:21:19 PM PDT 24 | 2685319573 ps | ||
T409 | /workspace/coverage/default/84.prim_prince_test.2305912088 | Aug 17 04:24:58 PM PDT 24 | Aug 17 04:25:27 PM PDT 24 | 1426218168 ps | ||
T410 | /workspace/coverage/default/406.prim_prince_test.1058388979 | Aug 17 04:25:34 PM PDT 24 | Aug 17 04:25:50 PM PDT 24 | 806054896 ps | ||
T411 | /workspace/coverage/default/414.prim_prince_test.387800935 | Aug 17 04:24:59 PM PDT 24 | Aug 17 04:25:36 PM PDT 24 | 1845132290 ps | ||
T412 | /workspace/coverage/default/224.prim_prince_test.3355737656 | Aug 17 04:24:53 PM PDT 24 | Aug 17 04:25:41 PM PDT 24 | 2460014027 ps | ||
T413 | /workspace/coverage/default/451.prim_prince_test.2769318850 | Aug 17 04:25:39 PM PDT 24 | Aug 17 04:26:26 PM PDT 24 | 2405876832 ps | ||
T414 | /workspace/coverage/default/372.prim_prince_test.801590068 | Aug 17 04:26:01 PM PDT 24 | Aug 17 04:26:29 PM PDT 24 | 1453176085 ps | ||
T415 | /workspace/coverage/default/395.prim_prince_test.2854511892 | Aug 17 04:25:32 PM PDT 24 | Aug 17 04:25:52 PM PDT 24 | 1004588511 ps | ||
T416 | /workspace/coverage/default/162.prim_prince_test.2636363630 | Aug 17 04:22:47 PM PDT 24 | Aug 17 04:23:46 PM PDT 24 | 2793643479 ps | ||
T417 | /workspace/coverage/default/388.prim_prince_test.486615780 | Aug 17 04:23:10 PM PDT 24 | Aug 17 04:23:56 PM PDT 24 | 2261917855 ps | ||
T418 | /workspace/coverage/default/213.prim_prince_test.3995027761 | Aug 17 04:25:09 PM PDT 24 | Aug 17 04:25:33 PM PDT 24 | 1227539734 ps | ||
T419 | /workspace/coverage/default/461.prim_prince_test.2744713523 | Aug 17 04:23:58 PM PDT 24 | Aug 17 04:24:46 PM PDT 24 | 2524230895 ps | ||
T420 | /workspace/coverage/default/370.prim_prince_test.2282017433 | Aug 17 04:23:05 PM PDT 24 | Aug 17 04:23:31 PM PDT 24 | 1267093386 ps | ||
T421 | /workspace/coverage/default/456.prim_prince_test.4126886916 | Aug 17 04:25:06 PM PDT 24 | Aug 17 04:25:23 PM PDT 24 | 894703597 ps | ||
T422 | /workspace/coverage/default/291.prim_prince_test.361006197 | Aug 17 04:25:38 PM PDT 24 | Aug 17 04:26:00 PM PDT 24 | 1169163353 ps | ||
T423 | /workspace/coverage/default/57.prim_prince_test.1215449773 | Aug 17 04:20:27 PM PDT 24 | Aug 17 04:21:25 PM PDT 24 | 2840624880 ps | ||
T424 | /workspace/coverage/default/207.prim_prince_test.985103094 | Aug 17 04:23:49 PM PDT 24 | Aug 17 04:24:05 PM PDT 24 | 770233055 ps | ||
T425 | /workspace/coverage/default/30.prim_prince_test.2091886126 | Aug 17 04:21:41 PM PDT 24 | Aug 17 04:22:08 PM PDT 24 | 1306175237 ps | ||
T426 | /workspace/coverage/default/102.prim_prince_test.4109450955 | Aug 17 04:22:36 PM PDT 24 | Aug 17 04:23:00 PM PDT 24 | 1105160231 ps | ||
T427 | /workspace/coverage/default/154.prim_prince_test.3492994130 | Aug 17 04:22:17 PM PDT 24 | Aug 17 04:23:09 PM PDT 24 | 2417048357 ps | ||
T428 | /workspace/coverage/default/332.prim_prince_test.668399700 | Aug 17 04:23:16 PM PDT 24 | Aug 17 04:24:12 PM PDT 24 | 2763059535 ps | ||
T429 | /workspace/coverage/default/303.prim_prince_test.3656822929 | Aug 17 04:24:54 PM PDT 24 | Aug 17 04:26:05 PM PDT 24 | 3667042870 ps | ||
T430 | /workspace/coverage/default/118.prim_prince_test.1977948420 | Aug 17 04:25:00 PM PDT 24 | Aug 17 04:26:05 PM PDT 24 | 3479257561 ps | ||
T431 | /workspace/coverage/default/170.prim_prince_test.989176298 | Aug 17 04:23:59 PM PDT 24 | Aug 17 04:24:20 PM PDT 24 | 939880353 ps | ||
T432 | /workspace/coverage/default/446.prim_prince_test.1384467656 | Aug 17 04:25:34 PM PDT 24 | Aug 17 04:26:31 PM PDT 24 | 2952976693 ps | ||
T433 | /workspace/coverage/default/253.prim_prince_test.62237392 | Aug 17 04:25:15 PM PDT 24 | Aug 17 04:25:32 PM PDT 24 | 886490527 ps | ||
T434 | /workspace/coverage/default/281.prim_prince_test.583919327 | Aug 17 04:22:46 PM PDT 24 | Aug 17 04:23:20 PM PDT 24 | 1663650721 ps | ||
T435 | /workspace/coverage/default/402.prim_prince_test.3269769220 | Aug 17 04:25:12 PM PDT 24 | Aug 17 04:26:01 PM PDT 24 | 2572629238 ps | ||
T436 | /workspace/coverage/default/137.prim_prince_test.3640712878 | Aug 17 04:26:02 PM PDT 24 | Aug 17 04:26:59 PM PDT 24 | 2798475247 ps | ||
T437 | /workspace/coverage/default/73.prim_prince_test.1975150941 | Aug 17 04:24:50 PM PDT 24 | Aug 17 04:26:02 PM PDT 24 | 3715515743 ps | ||
T438 | /workspace/coverage/default/55.prim_prince_test.4290532814 | Aug 17 04:20:26 PM PDT 24 | Aug 17 04:21:05 PM PDT 24 | 2000823843 ps | ||
T439 | /workspace/coverage/default/351.prim_prince_test.502158797 | Aug 17 04:22:52 PM PDT 24 | Aug 17 04:23:24 PM PDT 24 | 1547885376 ps | ||
T440 | /workspace/coverage/default/238.prim_prince_test.1058328318 | Aug 17 04:22:02 PM PDT 24 | Aug 17 04:22:43 PM PDT 24 | 1971883276 ps | ||
T441 | /workspace/coverage/default/28.prim_prince_test.3664736789 | Aug 17 04:20:28 PM PDT 24 | Aug 17 04:21:01 PM PDT 24 | 1711482951 ps | ||
T442 | /workspace/coverage/default/160.prim_prince_test.966768332 | Aug 17 04:21:15 PM PDT 24 | Aug 17 04:22:11 PM PDT 24 | 2710789790 ps | ||
T443 | /workspace/coverage/default/335.prim_prince_test.4252567496 | Aug 17 04:22:46 PM PDT 24 | Aug 17 04:23:16 PM PDT 24 | 1339649055 ps | ||
T444 | /workspace/coverage/default/491.prim_prince_test.36501131 | Aug 17 04:26:04 PM PDT 24 | Aug 17 04:26:24 PM PDT 24 | 947540042 ps | ||
T445 | /workspace/coverage/default/74.prim_prince_test.4163267487 | Aug 17 04:25:00 PM PDT 24 | Aug 17 04:26:09 PM PDT 24 | 3687611686 ps | ||
T446 | /workspace/coverage/default/391.prim_prince_test.478618806 | Aug 17 04:24:59 PM PDT 24 | Aug 17 04:25:15 PM PDT 24 | 808749919 ps | ||
T447 | /workspace/coverage/default/440.prim_prince_test.3445054596 | Aug 17 04:24:56 PM PDT 24 | Aug 17 04:25:11 PM PDT 24 | 782922320 ps | ||
T448 | /workspace/coverage/default/39.prim_prince_test.3726795399 | Aug 17 04:21:27 PM PDT 24 | Aug 17 04:22:09 PM PDT 24 | 2121358757 ps | ||
T449 | /workspace/coverage/default/274.prim_prince_test.536751932 | Aug 17 04:25:34 PM PDT 24 | Aug 17 04:26:37 PM PDT 24 | 3259325874 ps | ||
T450 | /workspace/coverage/default/256.prim_prince_test.2291840730 | Aug 17 04:25:34 PM PDT 24 | Aug 17 04:26:19 PM PDT 24 | 2321395769 ps | ||
T451 | /workspace/coverage/default/467.prim_prince_test.1748822778 | Aug 17 04:23:55 PM PDT 24 | Aug 17 04:24:27 PM PDT 24 | 1569132958 ps | ||
T452 | /workspace/coverage/default/237.prim_prince_test.3097270057 | Aug 17 04:24:16 PM PDT 24 | Aug 17 04:25:18 PM PDT 24 | 3140803028 ps | ||
T453 | /workspace/coverage/default/131.prim_prince_test.2374120066 | Aug 17 04:25:46 PM PDT 24 | Aug 17 04:26:32 PM PDT 24 | 2279963188 ps | ||
T454 | /workspace/coverage/default/349.prim_prince_test.4188022365 | Aug 17 04:25:34 PM PDT 24 | Aug 17 04:25:51 PM PDT 24 | 824128397 ps | ||
T455 | /workspace/coverage/default/182.prim_prince_test.542484976 | Aug 17 04:25:11 PM PDT 24 | Aug 17 04:26:00 PM PDT 24 | 2514141460 ps | ||
T456 | /workspace/coverage/default/299.prim_prince_test.2777292741 | Aug 17 04:24:54 PM PDT 24 | Aug 17 04:25:53 PM PDT 24 | 3040972754 ps | ||
T457 | /workspace/coverage/default/34.prim_prince_test.371412709 | Aug 17 04:21:28 PM PDT 24 | Aug 17 04:22:30 PM PDT 24 | 3188050952 ps | ||
T458 | /workspace/coverage/default/489.prim_prince_test.2654856877 | Aug 17 04:26:14 PM PDT 24 | Aug 17 04:26:39 PM PDT 24 | 1197018439 ps | ||
T459 | /workspace/coverage/default/377.prim_prince_test.3526956701 | Aug 17 04:25:02 PM PDT 24 | Aug 17 04:25:24 PM PDT 24 | 1091046293 ps | ||
T460 | /workspace/coverage/default/458.prim_prince_test.3367440380 | Aug 17 04:25:39 PM PDT 24 | Aug 17 04:26:24 PM PDT 24 | 2287983650 ps | ||
T461 | /workspace/coverage/default/206.prim_prince_test.2359359980 | Aug 17 04:25:10 PM PDT 24 | Aug 17 04:25:37 PM PDT 24 | 1424348598 ps | ||
T462 | /workspace/coverage/default/159.prim_prince_test.4027103595 | Aug 17 04:25:14 PM PDT 24 | Aug 17 04:25:48 PM PDT 24 | 1766665898 ps | ||
T463 | /workspace/coverage/default/288.prim_prince_test.916109920 | Aug 17 04:24:48 PM PDT 24 | Aug 17 04:25:59 PM PDT 24 | 3641966920 ps | ||
T464 | /workspace/coverage/default/129.prim_prince_test.1063617722 | Aug 17 04:25:32 PM PDT 24 | Aug 17 04:26:14 PM PDT 24 | 2146377680 ps | ||
T465 | /workspace/coverage/default/481.prim_prince_test.961384744 | Aug 17 04:25:12 PM PDT 24 | Aug 17 04:26:10 PM PDT 24 | 2911930963 ps | ||
T466 | /workspace/coverage/default/176.prim_prince_test.1742494972 | Aug 17 04:25:54 PM PDT 24 | Aug 17 04:26:54 PM PDT 24 | 3107739936 ps | ||
T467 | /workspace/coverage/default/23.prim_prince_test.1185126775 | Aug 17 04:20:25 PM PDT 24 | Aug 17 04:21:35 PM PDT 24 | 3606436322 ps | ||
T468 | /workspace/coverage/default/155.prim_prince_test.2122804174 | Aug 17 04:21:11 PM PDT 24 | Aug 17 04:22:06 PM PDT 24 | 2593041916 ps | ||
T469 | /workspace/coverage/default/350.prim_prince_test.1176046500 | Aug 17 04:22:58 PM PDT 24 | Aug 17 04:23:28 PM PDT 24 | 1482534816 ps | ||
T470 | /workspace/coverage/default/354.prim_prince_test.1982112203 | Aug 17 04:25:03 PM PDT 24 | Aug 17 04:25:49 PM PDT 24 | 2434086370 ps | ||
T471 | /workspace/coverage/default/223.prim_prince_test.2380840821 | Aug 17 04:24:17 PM PDT 24 | Aug 17 04:25:26 PM PDT 24 | 3380453158 ps | ||
T472 | /workspace/coverage/default/152.prim_prince_test.2706943526 | Aug 17 04:23:03 PM PDT 24 | Aug 17 04:24:12 PM PDT 24 | 3476742024 ps | ||
T473 | /workspace/coverage/default/180.prim_prince_test.1664003392 | Aug 17 04:21:17 PM PDT 24 | Aug 17 04:22:25 PM PDT 24 | 3340771475 ps | ||
T474 | /workspace/coverage/default/326.prim_prince_test.2342752375 | Aug 17 04:25:24 PM PDT 24 | Aug 17 04:25:53 PM PDT 24 | 1528636253 ps | ||
T475 | /workspace/coverage/default/371.prim_prince_test.437955015 | Aug 17 04:24:14 PM PDT 24 | Aug 17 04:25:21 PM PDT 24 | 3350429678 ps | ||
T476 | /workspace/coverage/default/439.prim_prince_test.3617400546 | Aug 17 04:24:55 PM PDT 24 | Aug 17 04:25:25 PM PDT 24 | 1595560598 ps | ||
T477 | /workspace/coverage/default/166.prim_prince_test.865627989 | Aug 17 04:21:12 PM PDT 24 | Aug 17 04:21:31 PM PDT 24 | 913556425 ps | ||
T478 | /workspace/coverage/default/186.prim_prince_test.3256083845 | Aug 17 04:22:17 PM PDT 24 | Aug 17 04:23:05 PM PDT 24 | 2161810908 ps | ||
T479 | /workspace/coverage/default/239.prim_prince_test.2220271592 | Aug 17 04:25:23 PM PDT 24 | Aug 17 04:25:41 PM PDT 24 | 883512395 ps | ||
T480 | /workspace/coverage/default/263.prim_prince_test.3048725110 | Aug 17 04:22:50 PM PDT 24 | Aug 17 04:23:24 PM PDT 24 | 1729393973 ps | ||
T481 | /workspace/coverage/default/208.prim_prince_test.2078899728 | Aug 17 04:25:01 PM PDT 24 | Aug 17 04:26:09 PM PDT 24 | 3611848820 ps | ||
T482 | /workspace/coverage/default/5.prim_prince_test.3901596615 | Aug 17 04:20:26 PM PDT 24 | Aug 17 04:21:33 PM PDT 24 | 3282199674 ps | ||
T483 | /workspace/coverage/default/421.prim_prince_test.439088917 | Aug 17 04:23:47 PM PDT 24 | Aug 17 04:25:03 PM PDT 24 | 3731550654 ps | ||
T484 | /workspace/coverage/default/333.prim_prince_test.30345638 | Aug 17 04:25:45 PM PDT 24 | Aug 17 04:26:46 PM PDT 24 | 3102927573 ps | ||
T485 | /workspace/coverage/default/486.prim_prince_test.1575608742 | Aug 17 04:26:04 PM PDT 24 | Aug 17 04:27:05 PM PDT 24 | 3035294321 ps | ||
T486 | /workspace/coverage/default/452.prim_prince_test.4165266486 | Aug 17 04:23:48 PM PDT 24 | Aug 17 04:24:44 PM PDT 24 | 2803360089 ps | ||
T487 | /workspace/coverage/default/449.prim_prince_test.443050509 | Aug 17 04:24:56 PM PDT 24 | Aug 17 04:25:13 PM PDT 24 | 894827809 ps | ||
T488 | /workspace/coverage/default/217.prim_prince_test.426072436 | Aug 17 04:22:20 PM PDT 24 | Aug 17 04:22:54 PM PDT 24 | 1645075494 ps | ||
T489 | /workspace/coverage/default/158.prim_prince_test.2319671461 | Aug 17 04:25:26 PM PDT 24 | Aug 17 04:26:04 PM PDT 24 | 1894003239 ps | ||
T490 | /workspace/coverage/default/277.prim_prince_test.491693610 | Aug 17 04:25:02 PM PDT 24 | Aug 17 04:26:12 PM PDT 24 | 3453367100 ps | ||
T491 | /workspace/coverage/default/99.prim_prince_test.3703971080 | Aug 17 04:25:14 PM PDT 24 | Aug 17 04:26:06 PM PDT 24 | 2724755718 ps | ||
T492 | /workspace/coverage/default/342.prim_prince_test.3052970169 | Aug 17 04:25:46 PM PDT 24 | Aug 17 04:26:31 PM PDT 24 | 2296978421 ps | ||
T493 | /workspace/coverage/default/68.prim_prince_test.2016251737 | Aug 17 04:24:59 PM PDT 24 | Aug 17 04:25:31 PM PDT 24 | 1654514517 ps | ||
T494 | /workspace/coverage/default/41.prim_prince_test.277437516 | Aug 17 04:20:21 PM PDT 24 | Aug 17 04:21:16 PM PDT 24 | 2669534494 ps | ||
T495 | /workspace/coverage/default/150.prim_prince_test.427392737 | Aug 17 04:21:59 PM PDT 24 | Aug 17 04:23:11 PM PDT 24 | 3547201445 ps | ||
T496 | /workspace/coverage/default/70.prim_prince_test.1075753204 | Aug 17 04:25:34 PM PDT 24 | Aug 17 04:26:03 PM PDT 24 | 1478903882 ps | ||
T497 | /workspace/coverage/default/400.prim_prince_test.3699067225 | Aug 17 04:24:58 PM PDT 24 | Aug 17 04:25:58 PM PDT 24 | 3001665078 ps | ||
T498 | /workspace/coverage/default/322.prim_prince_test.3700863272 | Aug 17 04:25:34 PM PDT 24 | Aug 17 04:26:14 PM PDT 24 | 2032166355 ps | ||
T499 | /workspace/coverage/default/266.prim_prince_test.2063108066 | Aug 17 04:22:18 PM PDT 24 | Aug 17 04:22:41 PM PDT 24 | 1136191970 ps | ||
T500 | /workspace/coverage/default/444.prim_prince_test.452406577 | Aug 17 04:25:07 PM PDT 24 | Aug 17 04:25:55 PM PDT 24 | 2490230912 ps |
Test location | /workspace/coverage/default/19.prim_prince_test.984318400 |
Short name | T5 |
Test name | |
Test status | |
Simulation time | 2975412643 ps |
CPU time | 48.11 seconds |
Started | Aug 17 04:20:26 PM PDT 24 |
Finished | Aug 17 04:21:23 PM PDT 24 |
Peak memory | 145752 kb |
Host | smart-3ea1da47-414f-465c-b24f-1340efb33edb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=984318400 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_prince_test.984318400 |
Directory | /workspace/19.prim_prince_test/latest |
Test location | /workspace/coverage/default/0.prim_prince_test.952256895 |
Short name | T254 |
Test name | |
Test status | |
Simulation time | 2601813711 ps |
CPU time | 42.45 seconds |
Started | Aug 17 04:20:26 PM PDT 24 |
Finished | Aug 17 04:21:18 PM PDT 24 |
Peak memory | 146896 kb |
Host | smart-f5d5e8c2-85a3-4ff4-9823-6e4117d00a49 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=952256895 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_prince_test.952256895 |
Directory | /workspace/0.prim_prince_test/latest |
Test location | /workspace/coverage/default/1.prim_prince_test.2116799853 |
Short name | T145 |
Test name | |
Test status | |
Simulation time | 1711370739 ps |
CPU time | 28.26 seconds |
Started | Aug 17 04:20:28 PM PDT 24 |
Finished | Aug 17 04:21:02 PM PDT 24 |
Peak memory | 146196 kb |
Host | smart-42ef2b1f-79d5-49d0-a71d-f911007d0d66 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2116799853 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_prince_test.2116799853 |
Directory | /workspace/1.prim_prince_test/latest |
Test location | /workspace/coverage/default/10.prim_prince_test.3172859740 |
Short name | T48 |
Test name | |
Test status | |
Simulation time | 1812452860 ps |
CPU time | 30.04 seconds |
Started | Aug 17 04:20:26 PM PDT 24 |
Finished | Aug 17 04:21:02 PM PDT 24 |
Peak memory | 145136 kb |
Host | smart-659ffe8f-0bf3-439d-9e58-e798932e473c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3172859740 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_prince_test.3172859740 |
Directory | /workspace/10.prim_prince_test/latest |
Test location | /workspace/coverage/default/100.prim_prince_test.1759787037 |
Short name | T311 |
Test name | |
Test status | |
Simulation time | 3399583373 ps |
CPU time | 57.33 seconds |
Started | Aug 17 04:22:10 PM PDT 24 |
Finished | Aug 17 04:23:20 PM PDT 24 |
Peak memory | 146900 kb |
Host | smart-7193ab67-e593-41e4-afec-b1d3249a53ab |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1759787037 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 100.prim_prince_test.1759787037 |
Directory | /workspace/100.prim_prince_test/latest |
Test location | /workspace/coverage/default/101.prim_prince_test.1149195604 |
Short name | T262 |
Test name | |
Test status | |
Simulation time | 1009112167 ps |
CPU time | 16.76 seconds |
Started | Aug 17 04:22:22 PM PDT 24 |
Finished | Aug 17 04:22:42 PM PDT 24 |
Peak memory | 146320 kb |
Host | smart-76445b9b-2a08-4891-8a9e-448becccfb20 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1149195604 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 101.prim_prince_test.1149195604 |
Directory | /workspace/101.prim_prince_test/latest |
Test location | /workspace/coverage/default/102.prim_prince_test.4109450955 |
Short name | T426 |
Test name | |
Test status | |
Simulation time | 1105160231 ps |
CPU time | 19.18 seconds |
Started | Aug 17 04:22:36 PM PDT 24 |
Finished | Aug 17 04:23:00 PM PDT 24 |
Peak memory | 146568 kb |
Host | smart-faa2014e-a405-4270-847c-7e9ed49d557e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4109450955 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 102.prim_prince_test.4109450955 |
Directory | /workspace/102.prim_prince_test/latest |
Test location | /workspace/coverage/default/103.prim_prince_test.4029276431 |
Short name | T142 |
Test name | |
Test status | |
Simulation time | 1811269671 ps |
CPU time | 29.41 seconds |
Started | Aug 17 04:25:40 PM PDT 24 |
Finished | Aug 17 04:26:15 PM PDT 24 |
Peak memory | 146132 kb |
Host | smart-06ad8cdc-c7b4-46b9-848a-85e94ab3cc65 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4029276431 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 103.prim_prince_test.4029276431 |
Directory | /workspace/103.prim_prince_test/latest |
Test location | /workspace/coverage/default/104.prim_prince_test.2676717856 |
Short name | T51 |
Test name | |
Test status | |
Simulation time | 2245169455 ps |
CPU time | 36.06 seconds |
Started | Aug 17 04:25:02 PM PDT 24 |
Finished | Aug 17 04:25:44 PM PDT 24 |
Peak memory | 146192 kb |
Host | smart-55e77eff-6514-4e69-96f0-e186696e7f6a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2676717856 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 104.prim_prince_test.2676717856 |
Directory | /workspace/104.prim_prince_test/latest |
Test location | /workspace/coverage/default/105.prim_prince_test.1370162541 |
Short name | T241 |
Test name | |
Test status | |
Simulation time | 3519300985 ps |
CPU time | 55.92 seconds |
Started | Aug 17 04:25:29 PM PDT 24 |
Finished | Aug 17 04:26:35 PM PDT 24 |
Peak memory | 145636 kb |
Host | smart-6578ec5e-d00e-41b9-aadc-23c2690f61bf |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1370162541 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 105.prim_prince_test.1370162541 |
Directory | /workspace/105.prim_prince_test/latest |
Test location | /workspace/coverage/default/106.prim_prince_test.4113797048 |
Short name | T353 |
Test name | |
Test status | |
Simulation time | 2237590033 ps |
CPU time | 36.5 seconds |
Started | Aug 17 04:25:32 PM PDT 24 |
Finished | Aug 17 04:26:16 PM PDT 24 |
Peak memory | 146212 kb |
Host | smart-fe0b2bb8-605c-4c4b-89f5-e323d437e7db |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4113797048 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 106.prim_prince_test.4113797048 |
Directory | /workspace/106.prim_prince_test/latest |
Test location | /workspace/coverage/default/107.prim_prince_test.3027435410 |
Short name | T388 |
Test name | |
Test status | |
Simulation time | 3267906848 ps |
CPU time | 51.89 seconds |
Started | Aug 17 04:24:59 PM PDT 24 |
Finished | Aug 17 04:26:01 PM PDT 24 |
Peak memory | 146192 kb |
Host | smart-44dff152-0d98-4775-9609-7b2d41e04feb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3027435410 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 107.prim_prince_test.3027435410 |
Directory | /workspace/107.prim_prince_test/latest |
Test location | /workspace/coverage/default/108.prim_prince_test.3778814099 |
Short name | T259 |
Test name | |
Test status | |
Simulation time | 2016738421 ps |
CPU time | 33.91 seconds |
Started | Aug 17 04:21:13 PM PDT 24 |
Finished | Aug 17 04:21:54 PM PDT 24 |
Peak memory | 146320 kb |
Host | smart-d3d47ca2-9395-4677-bd52-3a4f94e3c946 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3778814099 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 108.prim_prince_test.3778814099 |
Directory | /workspace/108.prim_prince_test/latest |
Test location | /workspace/coverage/default/109.prim_prince_test.3026399252 |
Short name | T393 |
Test name | |
Test status | |
Simulation time | 3057471785 ps |
CPU time | 49.08 seconds |
Started | Aug 17 04:25:33 PM PDT 24 |
Finished | Aug 17 04:26:32 PM PDT 24 |
Peak memory | 146196 kb |
Host | smart-56cbe055-9434-440c-ac5f-92f43ec01954 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3026399252 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 109.prim_prince_test.3026399252 |
Directory | /workspace/109.prim_prince_test/latest |
Test location | /workspace/coverage/default/11.prim_prince_test.4091686468 |
Short name | T21 |
Test name | |
Test status | |
Simulation time | 3370157374 ps |
CPU time | 55.67 seconds |
Started | Aug 17 04:20:26 PM PDT 24 |
Finished | Aug 17 04:21:33 PM PDT 24 |
Peak memory | 146140 kb |
Host | smart-2f4a60b0-c09e-43f0-8cd4-18b43ed4d6f1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4091686468 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_prince_test.4091686468 |
Directory | /workspace/11.prim_prince_test/latest |
Test location | /workspace/coverage/default/110.prim_prince_test.3331204089 |
Short name | T85 |
Test name | |
Test status | |
Simulation time | 3646693774 ps |
CPU time | 58.69 seconds |
Started | Aug 17 04:25:25 PM PDT 24 |
Finished | Aug 17 04:26:35 PM PDT 24 |
Peak memory | 145292 kb |
Host | smart-de21daac-62a0-4b99-ad86-041b7172ff99 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3331204089 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 110.prim_prince_test.3331204089 |
Directory | /workspace/110.prim_prince_test/latest |
Test location | /workspace/coverage/default/111.prim_prince_test.2541982963 |
Short name | T32 |
Test name | |
Test status | |
Simulation time | 2764031920 ps |
CPU time | 46.7 seconds |
Started | Aug 17 04:21:13 PM PDT 24 |
Finished | Aug 17 04:22:09 PM PDT 24 |
Peak memory | 146384 kb |
Host | smart-fc8a8d5a-7d97-4545-a4c2-5825c9fd8836 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2541982963 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 111.prim_prince_test.2541982963 |
Directory | /workspace/111.prim_prince_test/latest |
Test location | /workspace/coverage/default/112.prim_prince_test.3659763661 |
Short name | T128 |
Test name | |
Test status | |
Simulation time | 1647399927 ps |
CPU time | 27.98 seconds |
Started | Aug 17 04:22:03 PM PDT 24 |
Finished | Aug 17 04:22:37 PM PDT 24 |
Peak memory | 146436 kb |
Host | smart-17d7c19a-b8d9-4f7d-8a18-a5174cb304ea |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3659763661 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 112.prim_prince_test.3659763661 |
Directory | /workspace/112.prim_prince_test/latest |
Test location | /workspace/coverage/default/113.prim_prince_test.3177622073 |
Short name | T184 |
Test name | |
Test status | |
Simulation time | 2016685682 ps |
CPU time | 32.49 seconds |
Started | Aug 17 04:25:00 PM PDT 24 |
Finished | Aug 17 04:25:39 PM PDT 24 |
Peak memory | 146128 kb |
Host | smart-6b9fa36a-ed86-41e9-a2dd-d5ed2c91b575 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3177622073 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 113.prim_prince_test.3177622073 |
Directory | /workspace/113.prim_prince_test/latest |
Test location | /workspace/coverage/default/114.prim_prince_test.1634817286 |
Short name | T214 |
Test name | |
Test status | |
Simulation time | 3398769304 ps |
CPU time | 54.28 seconds |
Started | Aug 17 04:25:33 PM PDT 24 |
Finished | Aug 17 04:26:37 PM PDT 24 |
Peak memory | 146196 kb |
Host | smart-7452c279-0784-4d89-8427-ac30dd69d693 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1634817286 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 114.prim_prince_test.1634817286 |
Directory | /workspace/114.prim_prince_test/latest |
Test location | /workspace/coverage/default/115.prim_prince_test.332369823 |
Short name | T306 |
Test name | |
Test status | |
Simulation time | 2818721868 ps |
CPU time | 47.43 seconds |
Started | Aug 17 04:22:58 PM PDT 24 |
Finished | Aug 17 04:23:55 PM PDT 24 |
Peak memory | 146660 kb |
Host | smart-d9cd29ee-7a79-4793-9b3b-d4e00f017f56 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=332369823 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 115.prim_prince_test.332369823 |
Directory | /workspace/115.prim_prince_test/latest |
Test location | /workspace/coverage/default/116.prim_prince_test.1370233248 |
Short name | T316 |
Test name | |
Test status | |
Simulation time | 3698482903 ps |
CPU time | 60.23 seconds |
Started | Aug 17 04:25:34 PM PDT 24 |
Finished | Aug 17 04:26:47 PM PDT 24 |
Peak memory | 146188 kb |
Host | smart-8d760ca5-9c81-4b36-9b7d-abff97a51403 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1370233248 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 116.prim_prince_test.1370233248 |
Directory | /workspace/116.prim_prince_test/latest |
Test location | /workspace/coverage/default/117.prim_prince_test.4190954770 |
Short name | T298 |
Test name | |
Test status | |
Simulation time | 2480337107 ps |
CPU time | 40.17 seconds |
Started | Aug 17 04:25:24 PM PDT 24 |
Finished | Aug 17 04:26:12 PM PDT 24 |
Peak memory | 145636 kb |
Host | smart-7627571b-4f47-4136-8fc4-de50d9e7975e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4190954770 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 117.prim_prince_test.4190954770 |
Directory | /workspace/117.prim_prince_test/latest |
Test location | /workspace/coverage/default/118.prim_prince_test.1977948420 |
Short name | T430 |
Test name | |
Test status | |
Simulation time | 3479257561 ps |
CPU time | 55.24 seconds |
Started | Aug 17 04:25:00 PM PDT 24 |
Finished | Aug 17 04:26:05 PM PDT 24 |
Peak memory | 146192 kb |
Host | smart-3baefe15-eea8-4822-9041-d9590d42c931 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1977948420 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 118.prim_prince_test.1977948420 |
Directory | /workspace/118.prim_prince_test/latest |
Test location | /workspace/coverage/default/119.prim_prince_test.1697582557 |
Short name | T406 |
Test name | |
Test status | |
Simulation time | 2540612418 ps |
CPU time | 41.16 seconds |
Started | Aug 17 04:25:33 PM PDT 24 |
Finished | Aug 17 04:26:22 PM PDT 24 |
Peak memory | 146196 kb |
Host | smart-cec805ae-119b-4a7c-bb7d-90a633685a6b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1697582557 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 119.prim_prince_test.1697582557 |
Directory | /workspace/119.prim_prince_test/latest |
Test location | /workspace/coverage/default/12.prim_prince_test.1658317096 |
Short name | T165 |
Test name | |
Test status | |
Simulation time | 2798201833 ps |
CPU time | 45.77 seconds |
Started | Aug 17 04:20:26 PM PDT 24 |
Finished | Aug 17 04:21:21 PM PDT 24 |
Peak memory | 146312 kb |
Host | smart-5abe4089-c6f5-4742-864a-e64fc54b268c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1658317096 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_prince_test.1658317096 |
Directory | /workspace/12.prim_prince_test/latest |
Test location | /workspace/coverage/default/120.prim_prince_test.1507140823 |
Short name | T89 |
Test name | |
Test status | |
Simulation time | 2975023706 ps |
CPU time | 47.21 seconds |
Started | Aug 17 04:25:34 PM PDT 24 |
Finished | Aug 17 04:26:30 PM PDT 24 |
Peak memory | 146196 kb |
Host | smart-939470ee-35ce-437d-a583-bb2720194410 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1507140823 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 120.prim_prince_test.1507140823 |
Directory | /workspace/120.prim_prince_test/latest |
Test location | /workspace/coverage/default/121.prim_prince_test.2359801965 |
Short name | T130 |
Test name | |
Test status | |
Simulation time | 2082259960 ps |
CPU time | 35.09 seconds |
Started | Aug 17 04:21:13 PM PDT 24 |
Finished | Aug 17 04:21:55 PM PDT 24 |
Peak memory | 146580 kb |
Host | smart-fd118d4a-ef00-40d6-ba3d-d677dfdb290c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2359801965 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 121.prim_prince_test.2359801965 |
Directory | /workspace/121.prim_prince_test/latest |
Test location | /workspace/coverage/default/122.prim_prince_test.1132901915 |
Short name | T98 |
Test name | |
Test status | |
Simulation time | 3507586430 ps |
CPU time | 59.16 seconds |
Started | Aug 17 04:24:32 PM PDT 24 |
Finished | Aug 17 04:25:44 PM PDT 24 |
Peak memory | 146516 kb |
Host | smart-4d44346a-d8a4-4762-ad15-d2cd56dddcb9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1132901915 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 122.prim_prince_test.1132901915 |
Directory | /workspace/122.prim_prince_test/latest |
Test location | /workspace/coverage/default/123.prim_prince_test.543211221 |
Short name | T66 |
Test name | |
Test status | |
Simulation time | 2888130972 ps |
CPU time | 50.11 seconds |
Started | Aug 17 04:22:58 PM PDT 24 |
Finished | Aug 17 04:24:00 PM PDT 24 |
Peak memory | 146628 kb |
Host | smart-5f12f9f8-556a-4e20-9075-247a51c9dbc4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=543211221 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 123.prim_prince_test.543211221 |
Directory | /workspace/123.prim_prince_test/latest |
Test location | /workspace/coverage/default/124.prim_prince_test.2086893138 |
Short name | T364 |
Test name | |
Test status | |
Simulation time | 1122548742 ps |
CPU time | 18.94 seconds |
Started | Aug 17 04:23:50 PM PDT 24 |
Finished | Aug 17 04:24:12 PM PDT 24 |
Peak memory | 146452 kb |
Host | smart-92f7a8c6-b726-45a1-a03c-75dc301dfa57 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2086893138 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 124.prim_prince_test.2086893138 |
Directory | /workspace/124.prim_prince_test/latest |
Test location | /workspace/coverage/default/125.prim_prince_test.1840698437 |
Short name | T163 |
Test name | |
Test status | |
Simulation time | 2167366520 ps |
CPU time | 35.44 seconds |
Started | Aug 17 04:25:34 PM PDT 24 |
Finished | Aug 17 04:26:17 PM PDT 24 |
Peak memory | 146196 kb |
Host | smart-8d4102bd-f111-43b9-b301-b698245da661 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1840698437 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 125.prim_prince_test.1840698437 |
Directory | /workspace/125.prim_prince_test/latest |
Test location | /workspace/coverage/default/126.prim_prince_test.1304633433 |
Short name | T44 |
Test name | |
Test status | |
Simulation time | 2855821757 ps |
CPU time | 45.04 seconds |
Started | Aug 17 04:25:33 PM PDT 24 |
Finished | Aug 17 04:26:27 PM PDT 24 |
Peak memory | 145892 kb |
Host | smart-2ac6f63d-13ea-4ffc-8e80-c657cb320cc8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1304633433 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 126.prim_prince_test.1304633433 |
Directory | /workspace/126.prim_prince_test/latest |
Test location | /workspace/coverage/default/127.prim_prince_test.682711081 |
Short name | T303 |
Test name | |
Test status | |
Simulation time | 3380233916 ps |
CPU time | 53.57 seconds |
Started | Aug 17 04:25:32 PM PDT 24 |
Finished | Aug 17 04:26:36 PM PDT 24 |
Peak memory | 146220 kb |
Host | smart-b99797da-31d8-406a-8a7c-7dbed3060480 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=682711081 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 127.prim_prince_test.682711081 |
Directory | /workspace/127.prim_prince_test/latest |
Test location | /workspace/coverage/default/128.prim_prince_test.1484474960 |
Short name | T279 |
Test name | |
Test status | |
Simulation time | 2598144562 ps |
CPU time | 41.61 seconds |
Started | Aug 17 04:25:34 PM PDT 24 |
Finished | Aug 17 04:26:23 PM PDT 24 |
Peak memory | 146060 kb |
Host | smart-87f18bd2-1c4b-4335-a15f-f9aefd999ebd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1484474960 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 128.prim_prince_test.1484474960 |
Directory | /workspace/128.prim_prince_test/latest |
Test location | /workspace/coverage/default/129.prim_prince_test.1063617722 |
Short name | T464 |
Test name | |
Test status | |
Simulation time | 2146377680 ps |
CPU time | 34.64 seconds |
Started | Aug 17 04:25:32 PM PDT 24 |
Finished | Aug 17 04:26:14 PM PDT 24 |
Peak memory | 146148 kb |
Host | smart-660ec4bd-8ec8-4839-945f-f52e957f1f51 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1063617722 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 129.prim_prince_test.1063617722 |
Directory | /workspace/129.prim_prince_test/latest |
Test location | /workspace/coverage/default/13.prim_prince_test.3600316017 |
Short name | T149 |
Test name | |
Test status | |
Simulation time | 2967760921 ps |
CPU time | 48.15 seconds |
Started | Aug 17 04:20:26 PM PDT 24 |
Finished | Aug 17 04:21:23 PM PDT 24 |
Peak memory | 146172 kb |
Host | smart-e1574dba-ef04-4d15-b35a-2a5d1cfeca58 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3600316017 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_prince_test.3600316017 |
Directory | /workspace/13.prim_prince_test/latest |
Test location | /workspace/coverage/default/130.prim_prince_test.2649651762 |
Short name | T301 |
Test name | |
Test status | |
Simulation time | 3090926548 ps |
CPU time | 49.47 seconds |
Started | Aug 17 04:25:33 PM PDT 24 |
Finished | Aug 17 04:26:32 PM PDT 24 |
Peak memory | 146196 kb |
Host | smart-2084f242-56d9-4bc0-a8c3-e776e27f4ef7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2649651762 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 130.prim_prince_test.2649651762 |
Directory | /workspace/130.prim_prince_test/latest |
Test location | /workspace/coverage/default/131.prim_prince_test.2374120066 |
Short name | T453 |
Test name | |
Test status | |
Simulation time | 2279963188 ps |
CPU time | 37.75 seconds |
Started | Aug 17 04:25:46 PM PDT 24 |
Finished | Aug 17 04:26:32 PM PDT 24 |
Peak memory | 145728 kb |
Host | smart-eca3233a-1fed-4faa-b24b-f5d06f846225 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2374120066 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 131.prim_prince_test.2374120066 |
Directory | /workspace/131.prim_prince_test/latest |
Test location | /workspace/coverage/default/132.prim_prince_test.2274339555 |
Short name | T392 |
Test name | |
Test status | |
Simulation time | 986548482 ps |
CPU time | 15.92 seconds |
Started | Aug 17 04:25:34 PM PDT 24 |
Finished | Aug 17 04:25:53 PM PDT 24 |
Peak memory | 146148 kb |
Host | smart-c6d41f8c-29b1-4cc4-843f-48ba7ea77089 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2274339555 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 132.prim_prince_test.2274339555 |
Directory | /workspace/132.prim_prince_test/latest |
Test location | /workspace/coverage/default/133.prim_prince_test.2027588811 |
Short name | T54 |
Test name | |
Test status | |
Simulation time | 1043422039 ps |
CPU time | 17.49 seconds |
Started | Aug 17 04:24:16 PM PDT 24 |
Finished | Aug 17 04:24:37 PM PDT 24 |
Peak memory | 146592 kb |
Host | smart-e6cfa5f5-3b92-46fc-85b7-a4ee8c40dd82 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2027588811 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 133.prim_prince_test.2027588811 |
Directory | /workspace/133.prim_prince_test/latest |
Test location | /workspace/coverage/default/134.prim_prince_test.591589026 |
Short name | T282 |
Test name | |
Test status | |
Simulation time | 3284970000 ps |
CPU time | 56.06 seconds |
Started | Aug 17 04:22:47 PM PDT 24 |
Finished | Aug 17 04:23:56 PM PDT 24 |
Peak memory | 146496 kb |
Host | smart-8d0e8d42-9a7e-4888-80e4-210f95a13b5e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=591589026 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 134.prim_prince_test.591589026 |
Directory | /workspace/134.prim_prince_test/latest |
Test location | /workspace/coverage/default/135.prim_prince_test.886548085 |
Short name | T191 |
Test name | |
Test status | |
Simulation time | 2434049755 ps |
CPU time | 38.46 seconds |
Started | Aug 17 04:25:47 PM PDT 24 |
Finished | Aug 17 04:26:32 PM PDT 24 |
Peak memory | 144600 kb |
Host | smart-890dcb32-6d01-4a74-9348-a1a4c70af92a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=886548085 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 135.prim_prince_test.886548085 |
Directory | /workspace/135.prim_prince_test/latest |
Test location | /workspace/coverage/default/136.prim_prince_test.1856521096 |
Short name | T18 |
Test name | |
Test status | |
Simulation time | 2288880066 ps |
CPU time | 37.59 seconds |
Started | Aug 17 04:23:51 PM PDT 24 |
Finished | Aug 17 04:24:36 PM PDT 24 |
Peak memory | 146516 kb |
Host | smart-eabf92b1-fc8c-4ac9-874f-59bfd939d265 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1856521096 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 136.prim_prince_test.1856521096 |
Directory | /workspace/136.prim_prince_test/latest |
Test location | /workspace/coverage/default/137.prim_prince_test.3640712878 |
Short name | T436 |
Test name | |
Test status | |
Simulation time | 2798475247 ps |
CPU time | 47.1 seconds |
Started | Aug 17 04:26:02 PM PDT 24 |
Finished | Aug 17 04:26:59 PM PDT 24 |
Peak memory | 146300 kb |
Host | smart-6bf93e9e-9847-4a6b-8dc5-a85851f1e68d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3640712878 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 137.prim_prince_test.3640712878 |
Directory | /workspace/137.prim_prince_test/latest |
Test location | /workspace/coverage/default/138.prim_prince_test.1294531693 |
Short name | T141 |
Test name | |
Test status | |
Simulation time | 1044676156 ps |
CPU time | 18.46 seconds |
Started | Aug 17 04:23:40 PM PDT 24 |
Finished | Aug 17 04:24:03 PM PDT 24 |
Peak memory | 146576 kb |
Host | smart-aa29538f-b735-4c1c-b349-883fe841d4ad |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1294531693 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 138.prim_prince_test.1294531693 |
Directory | /workspace/138.prim_prince_test/latest |
Test location | /workspace/coverage/default/139.prim_prince_test.2575763216 |
Short name | T58 |
Test name | |
Test status | |
Simulation time | 2579153632 ps |
CPU time | 41.12 seconds |
Started | Aug 17 04:25:45 PM PDT 24 |
Finished | Aug 17 04:26:33 PM PDT 24 |
Peak memory | 146220 kb |
Host | smart-b1692291-1991-4312-bc0b-cc8c47c4674d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2575763216 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 139.prim_prince_test.2575763216 |
Directory | /workspace/139.prim_prince_test/latest |
Test location | /workspace/coverage/default/14.prim_prince_test.2419262923 |
Short name | T360 |
Test name | |
Test status | |
Simulation time | 3571216262 ps |
CPU time | 57.79 seconds |
Started | Aug 17 04:21:28 PM PDT 24 |
Finished | Aug 17 04:22:37 PM PDT 24 |
Peak memory | 146156 kb |
Host | smart-3822eb91-5e0d-4709-89c7-cc7813945f34 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2419262923 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_prince_test.2419262923 |
Directory | /workspace/14.prim_prince_test/latest |
Test location | /workspace/coverage/default/140.prim_prince_test.3987770340 |
Short name | T180 |
Test name | |
Test status | |
Simulation time | 2986354526 ps |
CPU time | 49.93 seconds |
Started | Aug 17 04:24:33 PM PDT 24 |
Finished | Aug 17 04:25:33 PM PDT 24 |
Peak memory | 146656 kb |
Host | smart-1f3a6a07-4ff8-4378-8de9-041d8a49ed57 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3987770340 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 140.prim_prince_test.3987770340 |
Directory | /workspace/140.prim_prince_test/latest |
Test location | /workspace/coverage/default/141.prim_prince_test.3114797645 |
Short name | T299 |
Test name | |
Test status | |
Simulation time | 2775914451 ps |
CPU time | 45.52 seconds |
Started | Aug 17 04:25:47 PM PDT 24 |
Finished | Aug 17 04:26:42 PM PDT 24 |
Peak memory | 145252 kb |
Host | smart-befbcc60-c9a8-4c70-af99-dcc72775dcd5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3114797645 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 141.prim_prince_test.3114797645 |
Directory | /workspace/141.prim_prince_test/latest |
Test location | /workspace/coverage/default/142.prim_prince_test.3626013172 |
Short name | T161 |
Test name | |
Test status | |
Simulation time | 1017913041 ps |
CPU time | 17.43 seconds |
Started | Aug 17 04:22:51 PM PDT 24 |
Finished | Aug 17 04:23:12 PM PDT 24 |
Peak memory | 146584 kb |
Host | smart-a207cad0-274a-446b-a938-be62fdcc478f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3626013172 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 142.prim_prince_test.3626013172 |
Directory | /workspace/142.prim_prince_test/latest |
Test location | /workspace/coverage/default/143.prim_prince_test.4248572595 |
Short name | T244 |
Test name | |
Test status | |
Simulation time | 2105898537 ps |
CPU time | 35.5 seconds |
Started | Aug 17 04:21:53 PM PDT 24 |
Finished | Aug 17 04:22:36 PM PDT 24 |
Peak memory | 146524 kb |
Host | smart-07013fb0-a34c-4a92-9e50-0f3ef0a0d7cc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4248572595 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 143.prim_prince_test.4248572595 |
Directory | /workspace/143.prim_prince_test/latest |
Test location | /workspace/coverage/default/144.prim_prince_test.3822755127 |
Short name | T200 |
Test name | |
Test status | |
Simulation time | 1665418882 ps |
CPU time | 27.37 seconds |
Started | Aug 17 04:25:26 PM PDT 24 |
Finished | Aug 17 04:25:59 PM PDT 24 |
Peak memory | 146328 kb |
Host | smart-615ac65a-33c9-41f0-813b-81284c029fea |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3822755127 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 144.prim_prince_test.3822755127 |
Directory | /workspace/144.prim_prince_test/latest |
Test location | /workspace/coverage/default/145.prim_prince_test.3532673893 |
Short name | T56 |
Test name | |
Test status | |
Simulation time | 3454180242 ps |
CPU time | 59.57 seconds |
Started | Aug 17 04:24:04 PM PDT 24 |
Finished | Aug 17 04:25:17 PM PDT 24 |
Peak memory | 146900 kb |
Host | smart-1f65a2e5-9aa0-49c7-9c59-ae4e2a2afe31 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3532673893 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 145.prim_prince_test.3532673893 |
Directory | /workspace/145.prim_prince_test/latest |
Test location | /workspace/coverage/default/146.prim_prince_test.1209327798 |
Short name | T25 |
Test name | |
Test status | |
Simulation time | 1610127245 ps |
CPU time | 26.56 seconds |
Started | Aug 17 04:24:01 PM PDT 24 |
Finished | Aug 17 04:24:33 PM PDT 24 |
Peak memory | 146504 kb |
Host | smart-ec43de8f-40b8-4be5-8c98-1a911db5ad1b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1209327798 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 146.prim_prince_test.1209327798 |
Directory | /workspace/146.prim_prince_test/latest |
Test location | /workspace/coverage/default/147.prim_prince_test.3184316507 |
Short name | T55 |
Test name | |
Test status | |
Simulation time | 2662151961 ps |
CPU time | 44.64 seconds |
Started | Aug 17 04:22:31 PM PDT 24 |
Finished | Aug 17 04:23:25 PM PDT 24 |
Peak memory | 146648 kb |
Host | smart-84e93075-c2c4-43f3-b648-37b60a85d07b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3184316507 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 147.prim_prince_test.3184316507 |
Directory | /workspace/147.prim_prince_test/latest |
Test location | /workspace/coverage/default/148.prim_prince_test.2558867162 |
Short name | T71 |
Test name | |
Test status | |
Simulation time | 3487672374 ps |
CPU time | 57.66 seconds |
Started | Aug 17 04:24:01 PM PDT 24 |
Finished | Aug 17 04:25:10 PM PDT 24 |
Peak memory | 146568 kb |
Host | smart-7e7d22b6-5352-4014-9603-71660621cdc0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2558867162 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 148.prim_prince_test.2558867162 |
Directory | /workspace/148.prim_prince_test/latest |
Test location | /workspace/coverage/default/149.prim_prince_test.1389252609 |
Short name | T338 |
Test name | |
Test status | |
Simulation time | 1694449178 ps |
CPU time | 27.63 seconds |
Started | Aug 17 04:23:05 PM PDT 24 |
Finished | Aug 17 04:23:38 PM PDT 24 |
Peak memory | 146564 kb |
Host | smart-6be26103-69d2-4504-9923-909929e30104 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1389252609 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 149.prim_prince_test.1389252609 |
Directory | /workspace/149.prim_prince_test/latest |
Test location | /workspace/coverage/default/15.prim_prince_test.1758272689 |
Short name | T17 |
Test name | |
Test status | |
Simulation time | 1114745963 ps |
CPU time | 18.67 seconds |
Started | Aug 17 04:20:21 PM PDT 24 |
Finished | Aug 17 04:20:44 PM PDT 24 |
Peak memory | 144524 kb |
Host | smart-33d767a4-3659-4270-b67b-efa5ebd07072 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1758272689 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_prince_test.1758272689 |
Directory | /workspace/15.prim_prince_test/latest |
Test location | /workspace/coverage/default/150.prim_prince_test.427392737 |
Short name | T495 |
Test name | |
Test status | |
Simulation time | 3547201445 ps |
CPU time | 59.5 seconds |
Started | Aug 17 04:21:59 PM PDT 24 |
Finished | Aug 17 04:23:11 PM PDT 24 |
Peak memory | 146908 kb |
Host | smart-670db3be-9817-4418-9a86-9fe5ff0c71c6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=427392737 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 150.prim_prince_test.427392737 |
Directory | /workspace/150.prim_prince_test/latest |
Test location | /workspace/coverage/default/151.prim_prince_test.2883727714 |
Short name | T374 |
Test name | |
Test status | |
Simulation time | 1202104476 ps |
CPU time | 19.89 seconds |
Started | Aug 17 04:24:03 PM PDT 24 |
Finished | Aug 17 04:24:27 PM PDT 24 |
Peak memory | 146564 kb |
Host | smart-3aa8a4c8-5c9f-4c91-9c5a-c8d8f670e174 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2883727714 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 151.prim_prince_test.2883727714 |
Directory | /workspace/151.prim_prince_test/latest |
Test location | /workspace/coverage/default/152.prim_prince_test.2706943526 |
Short name | T472 |
Test name | |
Test status | |
Simulation time | 3476742024 ps |
CPU time | 57.37 seconds |
Started | Aug 17 04:23:03 PM PDT 24 |
Finished | Aug 17 04:24:12 PM PDT 24 |
Peak memory | 146576 kb |
Host | smart-d08d665a-cc7c-4b2d-873a-34e3d05737c5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2706943526 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 152.prim_prince_test.2706943526 |
Directory | /workspace/152.prim_prince_test/latest |
Test location | /workspace/coverage/default/153.prim_prince_test.3574727660 |
Short name | T178 |
Test name | |
Test status | |
Simulation time | 3065132748 ps |
CPU time | 51.66 seconds |
Started | Aug 17 04:24:00 PM PDT 24 |
Finished | Aug 17 04:25:02 PM PDT 24 |
Peak memory | 146572 kb |
Host | smart-84806181-b6e9-419b-b317-fb35b584774c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3574727660 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 153.prim_prince_test.3574727660 |
Directory | /workspace/153.prim_prince_test/latest |
Test location | /workspace/coverage/default/154.prim_prince_test.3492994130 |
Short name | T427 |
Test name | |
Test status | |
Simulation time | 2417048357 ps |
CPU time | 41.99 seconds |
Started | Aug 17 04:22:17 PM PDT 24 |
Finished | Aug 17 04:23:09 PM PDT 24 |
Peak memory | 146624 kb |
Host | smart-afeaa5a7-d0b4-412d-9cb6-f1b8a55ec009 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3492994130 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 154.prim_prince_test.3492994130 |
Directory | /workspace/154.prim_prince_test/latest |
Test location | /workspace/coverage/default/155.prim_prince_test.2122804174 |
Short name | T468 |
Test name | |
Test status | |
Simulation time | 2593041916 ps |
CPU time | 44.71 seconds |
Started | Aug 17 04:21:11 PM PDT 24 |
Finished | Aug 17 04:22:06 PM PDT 24 |
Peak memory | 146624 kb |
Host | smart-3a2e4e6e-e391-42c1-a0cb-b51605bdc42f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2122804174 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 155.prim_prince_test.2122804174 |
Directory | /workspace/155.prim_prince_test/latest |
Test location | /workspace/coverage/default/156.prim_prince_test.824444401 |
Short name | T326 |
Test name | |
Test status | |
Simulation time | 2401607331 ps |
CPU time | 39.25 seconds |
Started | Aug 17 04:25:26 PM PDT 24 |
Finished | Aug 17 04:26:13 PM PDT 24 |
Peak memory | 146424 kb |
Host | smart-104cda2c-06bc-4539-8559-037aae6a80c0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=824444401 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 156.prim_prince_test.824444401 |
Directory | /workspace/156.prim_prince_test/latest |
Test location | /workspace/coverage/default/157.prim_prince_test.2292003144 |
Short name | T197 |
Test name | |
Test status | |
Simulation time | 1644059190 ps |
CPU time | 27.34 seconds |
Started | Aug 17 04:23:01 PM PDT 24 |
Finished | Aug 17 04:23:35 PM PDT 24 |
Peak memory | 146512 kb |
Host | smart-9f96cee4-5481-4972-8687-4305819bc087 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2292003144 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 157.prim_prince_test.2292003144 |
Directory | /workspace/157.prim_prince_test/latest |
Test location | /workspace/coverage/default/158.prim_prince_test.2319671461 |
Short name | T489 |
Test name | |
Test status | |
Simulation time | 1894003239 ps |
CPU time | 31.44 seconds |
Started | Aug 17 04:25:26 PM PDT 24 |
Finished | Aug 17 04:26:04 PM PDT 24 |
Peak memory | 146352 kb |
Host | smart-a28f0ab7-f0f9-4998-86cd-7554ee99fc78 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2319671461 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 158.prim_prince_test.2319671461 |
Directory | /workspace/158.prim_prince_test/latest |
Test location | /workspace/coverage/default/159.prim_prince_test.4027103595 |
Short name | T462 |
Test name | |
Test status | |
Simulation time | 1766665898 ps |
CPU time | 28.6 seconds |
Started | Aug 17 04:25:14 PM PDT 24 |
Finished | Aug 17 04:25:48 PM PDT 24 |
Peak memory | 146236 kb |
Host | smart-b1e91778-967e-4ff9-b13b-07628a6852ae |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4027103595 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 159.prim_prince_test.4027103595 |
Directory | /workspace/159.prim_prince_test/latest |
Test location | /workspace/coverage/default/16.prim_prince_test.873883885 |
Short name | T170 |
Test name | |
Test status | |
Simulation time | 1530150309 ps |
CPU time | 25.24 seconds |
Started | Aug 17 04:20:16 PM PDT 24 |
Finished | Aug 17 04:20:46 PM PDT 24 |
Peak memory | 145460 kb |
Host | smart-52e74d05-d627-474b-8220-b49df78c580a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=873883885 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_prince_test.873883885 |
Directory | /workspace/16.prim_prince_test/latest |
Test location | /workspace/coverage/default/160.prim_prince_test.966768332 |
Short name | T442 |
Test name | |
Test status | |
Simulation time | 2710789790 ps |
CPU time | 45.63 seconds |
Started | Aug 17 04:21:15 PM PDT 24 |
Finished | Aug 17 04:22:11 PM PDT 24 |
Peak memory | 146900 kb |
Host | smart-1dee40fc-aa4e-4656-804f-882b18c41bdd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=966768332 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 160.prim_prince_test.966768332 |
Directory | /workspace/160.prim_prince_test/latest |
Test location | /workspace/coverage/default/161.prim_prince_test.2058999524 |
Short name | T206 |
Test name | |
Test status | |
Simulation time | 2106619266 ps |
CPU time | 35.97 seconds |
Started | Aug 17 04:21:12 PM PDT 24 |
Finished | Aug 17 04:21:56 PM PDT 24 |
Peak memory | 146572 kb |
Host | smart-0986d979-ab2a-48d9-a025-0ddf82fd653c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2058999524 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 161.prim_prince_test.2058999524 |
Directory | /workspace/161.prim_prince_test/latest |
Test location | /workspace/coverage/default/162.prim_prince_test.2636363630 |
Short name | T416 |
Test name | |
Test status | |
Simulation time | 2793643479 ps |
CPU time | 48.21 seconds |
Started | Aug 17 04:22:47 PM PDT 24 |
Finished | Aug 17 04:23:46 PM PDT 24 |
Peak memory | 146488 kb |
Host | smart-ff45fd58-4b99-4f18-a073-85a18c08d0d0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2636363630 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 162.prim_prince_test.2636363630 |
Directory | /workspace/162.prim_prince_test/latest |
Test location | /workspace/coverage/default/163.prim_prince_test.865376087 |
Short name | T186 |
Test name | |
Test status | |
Simulation time | 2912086659 ps |
CPU time | 47.4 seconds |
Started | Aug 17 04:25:04 PM PDT 24 |
Finished | Aug 17 04:26:00 PM PDT 24 |
Peak memory | 146212 kb |
Host | smart-7673a9dc-1442-47dc-8029-1655cc91d83e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=865376087 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 163.prim_prince_test.865376087 |
Directory | /workspace/163.prim_prince_test/latest |
Test location | /workspace/coverage/default/164.prim_prince_test.1996328701 |
Short name | T328 |
Test name | |
Test status | |
Simulation time | 1929559774 ps |
CPU time | 32.9 seconds |
Started | Aug 17 04:21:13 PM PDT 24 |
Finished | Aug 17 04:21:53 PM PDT 24 |
Peak memory | 146580 kb |
Host | smart-a7806b12-03a3-4482-8442-f851d5ea76c4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1996328701 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 164.prim_prince_test.1996328701 |
Directory | /workspace/164.prim_prince_test/latest |
Test location | /workspace/coverage/default/165.prim_prince_test.575494148 |
Short name | T108 |
Test name | |
Test status | |
Simulation time | 3665287195 ps |
CPU time | 61.86 seconds |
Started | Aug 17 04:21:14 PM PDT 24 |
Finished | Aug 17 04:22:29 PM PDT 24 |
Peak memory | 146380 kb |
Host | smart-40c4aad2-0825-4902-be18-0a19f0236b4a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=575494148 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 165.prim_prince_test.575494148 |
Directory | /workspace/165.prim_prince_test/latest |
Test location | /workspace/coverage/default/166.prim_prince_test.865627989 |
Short name | T477 |
Test name | |
Test status | |
Simulation time | 913556425 ps |
CPU time | 15.74 seconds |
Started | Aug 17 04:21:12 PM PDT 24 |
Finished | Aug 17 04:21:31 PM PDT 24 |
Peak memory | 146540 kb |
Host | smart-c5cb257f-0058-4ff1-a622-abeaa6f7f155 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=865627989 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 166.prim_prince_test.865627989 |
Directory | /workspace/166.prim_prince_test/latest |
Test location | /workspace/coverage/default/167.prim_prince_test.12406117 |
Short name | T146 |
Test name | |
Test status | |
Simulation time | 1285988108 ps |
CPU time | 21.66 seconds |
Started | Aug 17 04:21:14 PM PDT 24 |
Finished | Aug 17 04:21:40 PM PDT 24 |
Peak memory | 146484 kb |
Host | smart-4afb2231-4a6d-4fea-b466-79ac21e0d2bb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=12406117 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 167.prim_prince_test.12406117 |
Directory | /workspace/167.prim_prince_test/latest |
Test location | /workspace/coverage/default/168.prim_prince_test.1426373009 |
Short name | T320 |
Test name | |
Test status | |
Simulation time | 2239841514 ps |
CPU time | 36.48 seconds |
Started | Aug 17 04:24:54 PM PDT 24 |
Finished | Aug 17 04:25:38 PM PDT 24 |
Peak memory | 145452 kb |
Host | smart-2e7ff73c-fd09-4ef5-9774-69af2ff20c1c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1426373009 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 168.prim_prince_test.1426373009 |
Directory | /workspace/168.prim_prince_test/latest |
Test location | /workspace/coverage/default/169.prim_prince_test.3419309367 |
Short name | T404 |
Test name | |
Test status | |
Simulation time | 3184825804 ps |
CPU time | 53.38 seconds |
Started | Aug 17 04:22:07 PM PDT 24 |
Finished | Aug 17 04:23:13 PM PDT 24 |
Peak memory | 146900 kb |
Host | smart-bcd29967-1e78-4649-a7a6-82c25dd9b65b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3419309367 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 169.prim_prince_test.3419309367 |
Directory | /workspace/169.prim_prince_test/latest |
Test location | /workspace/coverage/default/17.prim_prince_test.412724270 |
Short name | T408 |
Test name | |
Test status | |
Simulation time | 2685319573 ps |
CPU time | 43.48 seconds |
Started | Aug 17 04:20:28 PM PDT 24 |
Finished | Aug 17 04:21:19 PM PDT 24 |
Peak memory | 146256 kb |
Host | smart-35f3e575-3bc9-4602-abb7-ebe13196c7b9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=412724270 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_prince_test.412724270 |
Directory | /workspace/17.prim_prince_test/latest |
Test location | /workspace/coverage/default/170.prim_prince_test.989176298 |
Short name | T431 |
Test name | |
Test status | |
Simulation time | 939880353 ps |
CPU time | 17.12 seconds |
Started | Aug 17 04:23:59 PM PDT 24 |
Finished | Aug 17 04:24:20 PM PDT 24 |
Peak memory | 146432 kb |
Host | smart-f87d363e-93b6-46a0-b417-feaff93a803e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=989176298 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 170.prim_prince_test.989176298 |
Directory | /workspace/170.prim_prince_test/latest |
Test location | /workspace/coverage/default/171.prim_prince_test.3627477970 |
Short name | T280 |
Test name | |
Test status | |
Simulation time | 802707232 ps |
CPU time | 13.51 seconds |
Started | Aug 17 04:21:14 PM PDT 24 |
Finished | Aug 17 04:21:31 PM PDT 24 |
Peak memory | 146580 kb |
Host | smart-8bd1b8a8-53c1-4d3c-be84-3ce8a36d86f4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3627477970 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 171.prim_prince_test.3627477970 |
Directory | /workspace/171.prim_prince_test/latest |
Test location | /workspace/coverage/default/172.prim_prince_test.4258134005 |
Short name | T207 |
Test name | |
Test status | |
Simulation time | 1883432275 ps |
CPU time | 31.94 seconds |
Started | Aug 17 04:25:10 PM PDT 24 |
Finished | Aug 17 04:25:49 PM PDT 24 |
Peak memory | 146304 kb |
Host | smart-0fd186d8-f8da-409d-a027-88b0f593d2d2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4258134005 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 172.prim_prince_test.4258134005 |
Directory | /workspace/172.prim_prince_test/latest |
Test location | /workspace/coverage/default/173.prim_prince_test.228595671 |
Short name | T227 |
Test name | |
Test status | |
Simulation time | 1990181506 ps |
CPU time | 32.7 seconds |
Started | Aug 17 04:21:14 PM PDT 24 |
Finished | Aug 17 04:21:53 PM PDT 24 |
Peak memory | 146316 kb |
Host | smart-022261f8-b338-4ca4-9263-167e45c1cb05 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=228595671 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 173.prim_prince_test.228595671 |
Directory | /workspace/173.prim_prince_test/latest |
Test location | /workspace/coverage/default/174.prim_prince_test.1335650791 |
Short name | T237 |
Test name | |
Test status | |
Simulation time | 2661228910 ps |
CPU time | 44.17 seconds |
Started | Aug 17 04:24:03 PM PDT 24 |
Finished | Aug 17 04:24:57 PM PDT 24 |
Peak memory | 146384 kb |
Host | smart-60180561-3b07-4db3-aa3a-9e201792da74 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1335650791 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 174.prim_prince_test.1335650791 |
Directory | /workspace/174.prim_prince_test/latest |
Test location | /workspace/coverage/default/175.prim_prince_test.903406580 |
Short name | T69 |
Test name | |
Test status | |
Simulation time | 2784176110 ps |
CPU time | 47.48 seconds |
Started | Aug 17 04:21:11 PM PDT 24 |
Finished | Aug 17 04:22:09 PM PDT 24 |
Peak memory | 146588 kb |
Host | smart-793d04ce-d3a1-453c-a649-b14450654471 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=903406580 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 175.prim_prince_test.903406580 |
Directory | /workspace/175.prim_prince_test/latest |
Test location | /workspace/coverage/default/176.prim_prince_test.1742494972 |
Short name | T466 |
Test name | |
Test status | |
Simulation time | 3107739936 ps |
CPU time | 50.38 seconds |
Started | Aug 17 04:25:54 PM PDT 24 |
Finished | Aug 17 04:26:54 PM PDT 24 |
Peak memory | 146336 kb |
Host | smart-47dbe2e5-f0b5-4bce-a4a3-9ddaf21c50b9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1742494972 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 176.prim_prince_test.1742494972 |
Directory | /workspace/176.prim_prince_test/latest |
Test location | /workspace/coverage/default/177.prim_prince_test.1236283259 |
Short name | T65 |
Test name | |
Test status | |
Simulation time | 3641629502 ps |
CPU time | 60.5 seconds |
Started | Aug 17 04:24:03 PM PDT 24 |
Finished | Aug 17 04:25:17 PM PDT 24 |
Peak memory | 146384 kb |
Host | smart-fb91c0de-5ad6-436c-82bf-6fbbc887e2f1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1236283259 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 177.prim_prince_test.1236283259 |
Directory | /workspace/177.prim_prince_test/latest |
Test location | /workspace/coverage/default/178.prim_prince_test.3281771941 |
Short name | T365 |
Test name | |
Test status | |
Simulation time | 1273669228 ps |
CPU time | 20.38 seconds |
Started | Aug 17 04:25:11 PM PDT 24 |
Finished | Aug 17 04:25:35 PM PDT 24 |
Peak memory | 145932 kb |
Host | smart-f87c3575-9685-4209-bc57-835bd6a1aed1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3281771941 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 178.prim_prince_test.3281771941 |
Directory | /workspace/178.prim_prince_test/latest |
Test location | /workspace/coverage/default/179.prim_prince_test.263266592 |
Short name | T113 |
Test name | |
Test status | |
Simulation time | 2023182634 ps |
CPU time | 32.39 seconds |
Started | Aug 17 04:25:37 PM PDT 24 |
Finished | Aug 17 04:26:16 PM PDT 24 |
Peak memory | 146108 kb |
Host | smart-0655009d-ad37-4b4d-bfd0-d90821532252 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=263266592 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 179.prim_prince_test.263266592 |
Directory | /workspace/179.prim_prince_test/latest |
Test location | /workspace/coverage/default/18.prim_prince_test.159612777 |
Short name | T274 |
Test name | |
Test status | |
Simulation time | 2300377795 ps |
CPU time | 37.95 seconds |
Started | Aug 17 04:20:25 PM PDT 24 |
Finished | Aug 17 04:21:10 PM PDT 24 |
Peak memory | 146284 kb |
Host | smart-30f4873b-baac-4c9f-a01b-7909943e69a8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=159612777 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_prince_test.159612777 |
Directory | /workspace/18.prim_prince_test/latest |
Test location | /workspace/coverage/default/180.prim_prince_test.1664003392 |
Short name | T473 |
Test name | |
Test status | |
Simulation time | 3340771475 ps |
CPU time | 56.13 seconds |
Started | Aug 17 04:21:17 PM PDT 24 |
Finished | Aug 17 04:22:25 PM PDT 24 |
Peak memory | 146900 kb |
Host | smart-dd614d46-b80c-47b8-bbdf-7b144e7cf84e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1664003392 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 180.prim_prince_test.1664003392 |
Directory | /workspace/180.prim_prince_test/latest |
Test location | /workspace/coverage/default/181.prim_prince_test.1518494012 |
Short name | T193 |
Test name | |
Test status | |
Simulation time | 1598709556 ps |
CPU time | 25.74 seconds |
Started | Aug 17 04:24:54 PM PDT 24 |
Finished | Aug 17 04:25:24 PM PDT 24 |
Peak memory | 145808 kb |
Host | smart-5fa84d49-e30a-4a25-a890-2387f8b75dbb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1518494012 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 181.prim_prince_test.1518494012 |
Directory | /workspace/181.prim_prince_test/latest |
Test location | /workspace/coverage/default/182.prim_prince_test.542484976 |
Short name | T455 |
Test name | |
Test status | |
Simulation time | 2514141460 ps |
CPU time | 41.11 seconds |
Started | Aug 17 04:25:11 PM PDT 24 |
Finished | Aug 17 04:26:00 PM PDT 24 |
Peak memory | 145644 kb |
Host | smart-d1ef6294-951a-4c88-b585-6183af20f936 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=542484976 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 182.prim_prince_test.542484976 |
Directory | /workspace/182.prim_prince_test/latest |
Test location | /workspace/coverage/default/183.prim_prince_test.3982615670 |
Short name | T118 |
Test name | |
Test status | |
Simulation time | 2931016604 ps |
CPU time | 47.91 seconds |
Started | Aug 17 04:21:13 PM PDT 24 |
Finished | Aug 17 04:22:11 PM PDT 24 |
Peak memory | 146644 kb |
Host | smart-fcd32a63-72bd-4741-a8c5-1b8eee8bd3b1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3982615670 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 183.prim_prince_test.3982615670 |
Directory | /workspace/183.prim_prince_test/latest |
Test location | /workspace/coverage/default/184.prim_prince_test.1317018394 |
Short name | T250 |
Test name | |
Test status | |
Simulation time | 3434857962 ps |
CPU time | 55.19 seconds |
Started | Aug 17 04:25:13 PM PDT 24 |
Finished | Aug 17 04:26:18 PM PDT 24 |
Peak memory | 145328 kb |
Host | smart-9748e8a9-0fd6-4320-8661-d8f7201dfe5f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1317018394 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 184.prim_prince_test.1317018394 |
Directory | /workspace/184.prim_prince_test/latest |
Test location | /workspace/coverage/default/185.prim_prince_test.211913868 |
Short name | T379 |
Test name | |
Test status | |
Simulation time | 2462583499 ps |
CPU time | 41.27 seconds |
Started | Aug 17 04:21:24 PM PDT 24 |
Finished | Aug 17 04:22:14 PM PDT 24 |
Peak memory | 146536 kb |
Host | smart-9d146031-9423-4608-8f2a-cfbfc39d5ea6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=211913868 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 185.prim_prince_test.211913868 |
Directory | /workspace/185.prim_prince_test/latest |
Test location | /workspace/coverage/default/186.prim_prince_test.3256083845 |
Short name | T478 |
Test name | |
Test status | |
Simulation time | 2161810908 ps |
CPU time | 38.32 seconds |
Started | Aug 17 04:22:17 PM PDT 24 |
Finished | Aug 17 04:23:05 PM PDT 24 |
Peak memory | 146624 kb |
Host | smart-9055287f-b66a-4a60-879c-669780c335ee |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3256083845 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 186.prim_prince_test.3256083845 |
Directory | /workspace/186.prim_prince_test/latest |
Test location | /workspace/coverage/default/187.prim_prince_test.1052077995 |
Short name | T334 |
Test name | |
Test status | |
Simulation time | 1700156789 ps |
CPU time | 28.6 seconds |
Started | Aug 17 04:21:33 PM PDT 24 |
Finished | Aug 17 04:22:08 PM PDT 24 |
Peak memory | 146424 kb |
Host | smart-a7d14ce2-8295-4505-9ad3-0fd3c58beb58 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1052077995 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 187.prim_prince_test.1052077995 |
Directory | /workspace/187.prim_prince_test/latest |
Test location | /workspace/coverage/default/188.prim_prince_test.1010423803 |
Short name | T381 |
Test name | |
Test status | |
Simulation time | 2004116719 ps |
CPU time | 34.46 seconds |
Started | Aug 17 04:21:20 PM PDT 24 |
Finished | Aug 17 04:22:02 PM PDT 24 |
Peak memory | 146524 kb |
Host | smart-1399455d-d7fd-42ef-a5d6-3b0dabb4a64c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1010423803 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 188.prim_prince_test.1010423803 |
Directory | /workspace/188.prim_prince_test/latest |
Test location | /workspace/coverage/default/189.prim_prince_test.3193913037 |
Short name | T133 |
Test name | |
Test status | |
Simulation time | 2465797299 ps |
CPU time | 40.15 seconds |
Started | Aug 17 04:25:14 PM PDT 24 |
Finished | Aug 17 04:26:02 PM PDT 24 |
Peak memory | 146392 kb |
Host | smart-a9d9b148-d005-4ffa-9450-208bdf141d8a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3193913037 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 189.prim_prince_test.3193913037 |
Directory | /workspace/189.prim_prince_test/latest |
Test location | /workspace/coverage/default/190.prim_prince_test.3300956344 |
Short name | T395 |
Test name | |
Test status | |
Simulation time | 3644050296 ps |
CPU time | 62.83 seconds |
Started | Aug 17 04:24:04 PM PDT 24 |
Finished | Aug 17 04:25:21 PM PDT 24 |
Peak memory | 146900 kb |
Host | smart-bc35b696-1f6b-400c-a740-661e588efa9e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3300956344 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 190.prim_prince_test.3300956344 |
Directory | /workspace/190.prim_prince_test/latest |
Test location | /workspace/coverage/default/191.prim_prince_test.204409750 |
Short name | T47 |
Test name | |
Test status | |
Simulation time | 3058516417 ps |
CPU time | 51.29 seconds |
Started | Aug 17 04:21:24 PM PDT 24 |
Finished | Aug 17 04:22:27 PM PDT 24 |
Peak memory | 146352 kb |
Host | smart-0e9ac95a-a904-4cd9-b304-aa86d707d6df |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=204409750 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 191.prim_prince_test.204409750 |
Directory | /workspace/191.prim_prince_test/latest |
Test location | /workspace/coverage/default/192.prim_prince_test.582974840 |
Short name | T331 |
Test name | |
Test status | |
Simulation time | 1431227622 ps |
CPU time | 23.95 seconds |
Started | Aug 17 04:26:01 PM PDT 24 |
Finished | Aug 17 04:26:30 PM PDT 24 |
Peak memory | 146432 kb |
Host | smart-88c92536-6dd8-4235-a6be-83f854d0a0ea |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=582974840 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 192.prim_prince_test.582974840 |
Directory | /workspace/192.prim_prince_test/latest |
Test location | /workspace/coverage/default/193.prim_prince_test.1427288353 |
Short name | T345 |
Test name | |
Test status | |
Simulation time | 1131963836 ps |
CPU time | 18.86 seconds |
Started | Aug 17 04:22:30 PM PDT 24 |
Finished | Aug 17 04:22:53 PM PDT 24 |
Peak memory | 146508 kb |
Host | smart-4dd47151-e4b6-497d-8b3f-6bd6569e96fe |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1427288353 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 193.prim_prince_test.1427288353 |
Directory | /workspace/193.prim_prince_test/latest |
Test location | /workspace/coverage/default/194.prim_prince_test.383908547 |
Short name | T267 |
Test name | |
Test status | |
Simulation time | 1121994796 ps |
CPU time | 19.32 seconds |
Started | Aug 17 04:21:59 PM PDT 24 |
Finished | Aug 17 04:22:22 PM PDT 24 |
Peak memory | 146472 kb |
Host | smart-3227f818-c367-4476-b50e-eef5ce40902e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=383908547 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 194.prim_prince_test.383908547 |
Directory | /workspace/194.prim_prince_test/latest |
Test location | /workspace/coverage/default/195.prim_prince_test.1108864841 |
Short name | T210 |
Test name | |
Test status | |
Simulation time | 1323057732 ps |
CPU time | 22.83 seconds |
Started | Aug 17 04:21:21 PM PDT 24 |
Finished | Aug 17 04:21:50 PM PDT 24 |
Peak memory | 146524 kb |
Host | smart-e77bb805-ac13-4fd7-9af8-41b9affec2a3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1108864841 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 195.prim_prince_test.1108864841 |
Directory | /workspace/195.prim_prince_test/latest |
Test location | /workspace/coverage/default/196.prim_prince_test.797481349 |
Short name | T139 |
Test name | |
Test status | |
Simulation time | 1479602835 ps |
CPU time | 24.86 seconds |
Started | Aug 17 04:21:38 PM PDT 24 |
Finished | Aug 17 04:22:08 PM PDT 24 |
Peak memory | 146432 kb |
Host | smart-e4232292-e2e0-4aa8-a11b-fd655fe873b6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=797481349 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 196.prim_prince_test.797481349 |
Directory | /workspace/196.prim_prince_test/latest |
Test location | /workspace/coverage/default/197.prim_prince_test.970966096 |
Short name | T314 |
Test name | |
Test status | |
Simulation time | 3151554746 ps |
CPU time | 52.58 seconds |
Started | Aug 17 04:22:00 PM PDT 24 |
Finished | Aug 17 04:23:04 PM PDT 24 |
Peak memory | 146900 kb |
Host | smart-871fa853-20b1-4d13-8e39-2261a8627af7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=970966096 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 197.prim_prince_test.970966096 |
Directory | /workspace/197.prim_prince_test/latest |
Test location | /workspace/coverage/default/198.prim_prince_test.3219393370 |
Short name | T169 |
Test name | |
Test status | |
Simulation time | 1083946421 ps |
CPU time | 18.32 seconds |
Started | Aug 17 04:22:00 PM PDT 24 |
Finished | Aug 17 04:22:22 PM PDT 24 |
Peak memory | 146836 kb |
Host | smart-02e83b5d-7237-4c43-83b5-4c40c960a921 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3219393370 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 198.prim_prince_test.3219393370 |
Directory | /workspace/198.prim_prince_test/latest |
Test location | /workspace/coverage/default/199.prim_prince_test.1119878624 |
Short name | T397 |
Test name | |
Test status | |
Simulation time | 1305819461 ps |
CPU time | 22.17 seconds |
Started | Aug 17 04:21:38 PM PDT 24 |
Finished | Aug 17 04:22:05 PM PDT 24 |
Peak memory | 146424 kb |
Host | smart-fe4d09e4-7325-4129-b91d-59a609923b82 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1119878624 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 199.prim_prince_test.1119878624 |
Directory | /workspace/199.prim_prince_test/latest |
Test location | /workspace/coverage/default/2.prim_prince_test.1646277130 |
Short name | T376 |
Test name | |
Test status | |
Simulation time | 3328551448 ps |
CPU time | 56.1 seconds |
Started | Aug 17 04:20:27 PM PDT 24 |
Finished | Aug 17 04:21:35 PM PDT 24 |
Peak memory | 146340 kb |
Host | smart-265c208e-5d5c-4e6c-a354-b9159d13c931 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1646277130 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_prince_test.1646277130 |
Directory | /workspace/2.prim_prince_test/latest |
Test location | /workspace/coverage/default/20.prim_prince_test.1495597979 |
Short name | T92 |
Test name | |
Test status | |
Simulation time | 764302923 ps |
CPU time | 12.68 seconds |
Started | Aug 17 04:20:27 PM PDT 24 |
Finished | Aug 17 04:20:42 PM PDT 24 |
Peak memory | 145004 kb |
Host | smart-3d138abc-f8ed-4ed1-afb1-e113d8dfd6cd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1495597979 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_prince_test.1495597979 |
Directory | /workspace/20.prim_prince_test/latest |
Test location | /workspace/coverage/default/200.prim_prince_test.4226248053 |
Short name | T119 |
Test name | |
Test status | |
Simulation time | 2717025093 ps |
CPU time | 45.31 seconds |
Started | Aug 17 04:21:50 PM PDT 24 |
Finished | Aug 17 04:22:44 PM PDT 24 |
Peak memory | 146648 kb |
Host | smart-3c2bfe3e-aa10-4239-a732-8a51eaef0d8d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4226248053 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 200.prim_prince_test.4226248053 |
Directory | /workspace/200.prim_prince_test/latest |
Test location | /workspace/coverage/default/201.prim_prince_test.1442719704 |
Short name | T31 |
Test name | |
Test status | |
Simulation time | 2903526777 ps |
CPU time | 47.92 seconds |
Started | Aug 17 04:21:41 PM PDT 24 |
Finished | Aug 17 04:22:39 PM PDT 24 |
Peak memory | 146648 kb |
Host | smart-d5969e57-d955-4559-868a-91e696099d05 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1442719704 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 201.prim_prince_test.1442719704 |
Directory | /workspace/201.prim_prince_test/latest |
Test location | /workspace/coverage/default/202.prim_prince_test.1667621206 |
Short name | T355 |
Test name | |
Test status | |
Simulation time | 2374710838 ps |
CPU time | 37.64 seconds |
Started | Aug 17 04:25:14 PM PDT 24 |
Finished | Aug 17 04:25:58 PM PDT 24 |
Peak memory | 146248 kb |
Host | smart-2fa7f23a-2d60-4815-a068-e1d23c2dfd0e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1667621206 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 202.prim_prince_test.1667621206 |
Directory | /workspace/202.prim_prince_test/latest |
Test location | /workspace/coverage/default/203.prim_prince_test.3124389959 |
Short name | T183 |
Test name | |
Test status | |
Simulation time | 1544039642 ps |
CPU time | 25.7 seconds |
Started | Aug 17 04:25:51 PM PDT 24 |
Finished | Aug 17 04:26:22 PM PDT 24 |
Peak memory | 146148 kb |
Host | smart-8a61a6e3-edf6-431b-abd0-af686b87e09c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3124389959 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 203.prim_prince_test.3124389959 |
Directory | /workspace/203.prim_prince_test/latest |
Test location | /workspace/coverage/default/204.prim_prince_test.2903070824 |
Short name | T57 |
Test name | |
Test status | |
Simulation time | 3244272057 ps |
CPU time | 51.17 seconds |
Started | Aug 17 04:25:33 PM PDT 24 |
Finished | Aug 17 04:26:34 PM PDT 24 |
Peak memory | 146196 kb |
Host | smart-93d30fa4-6c47-4183-a0d5-f19ae4de1607 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2903070824 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 204.prim_prince_test.2903070824 |
Directory | /workspace/204.prim_prince_test/latest |
Test location | /workspace/coverage/default/205.prim_prince_test.853927319 |
Short name | T79 |
Test name | |
Test status | |
Simulation time | 779193114 ps |
CPU time | 12.74 seconds |
Started | Aug 17 04:25:24 PM PDT 24 |
Finished | Aug 17 04:25:39 PM PDT 24 |
Peak memory | 146192 kb |
Host | smart-375ac37c-d9aa-4db2-bc6c-f0b527064cf3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=853927319 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 205.prim_prince_test.853927319 |
Directory | /workspace/205.prim_prince_test/latest |
Test location | /workspace/coverage/default/206.prim_prince_test.2359359980 |
Short name | T461 |
Test name | |
Test status | |
Simulation time | 1424348598 ps |
CPU time | 22.9 seconds |
Started | Aug 17 04:25:10 PM PDT 24 |
Finished | Aug 17 04:25:37 PM PDT 24 |
Peak memory | 146156 kb |
Host | smart-e4e65cda-087f-466d-af73-ce170ba7945d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2359359980 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 206.prim_prince_test.2359359980 |
Directory | /workspace/206.prim_prince_test/latest |
Test location | /workspace/coverage/default/207.prim_prince_test.985103094 |
Short name | T424 |
Test name | |
Test status | |
Simulation time | 770233055 ps |
CPU time | 13.5 seconds |
Started | Aug 17 04:23:49 PM PDT 24 |
Finished | Aug 17 04:24:05 PM PDT 24 |
Peak memory | 146596 kb |
Host | smart-6b23424d-6065-49d1-a15e-f84bdc6704e3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=985103094 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 207.prim_prince_test.985103094 |
Directory | /workspace/207.prim_prince_test/latest |
Test location | /workspace/coverage/default/208.prim_prince_test.2078899728 |
Short name | T481 |
Test name | |
Test status | |
Simulation time | 3611848820 ps |
CPU time | 57.37 seconds |
Started | Aug 17 04:25:01 PM PDT 24 |
Finished | Aug 17 04:26:09 PM PDT 24 |
Peak memory | 146192 kb |
Host | smart-18cd44f9-20de-437c-b888-416ce78f28e4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2078899728 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 208.prim_prince_test.2078899728 |
Directory | /workspace/208.prim_prince_test/latest |
Test location | /workspace/coverage/default/209.prim_prince_test.3891369983 |
Short name | T195 |
Test name | |
Test status | |
Simulation time | 995478279 ps |
CPU time | 16.45 seconds |
Started | Aug 17 04:25:09 PM PDT 24 |
Finished | Aug 17 04:25:29 PM PDT 24 |
Peak memory | 146156 kb |
Host | smart-04c5b448-bd74-461f-8698-f030b1108b12 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3891369983 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 209.prim_prince_test.3891369983 |
Directory | /workspace/209.prim_prince_test/latest |
Test location | /workspace/coverage/default/21.prim_prince_test.4080910898 |
Short name | T266 |
Test name | |
Test status | |
Simulation time | 2212784796 ps |
CPU time | 36.95 seconds |
Started | Aug 17 04:20:26 PM PDT 24 |
Finished | Aug 17 04:21:10 PM PDT 24 |
Peak memory | 146184 kb |
Host | smart-a54cd9f4-3e28-4f5e-97b8-d2ec6d43cadd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4080910898 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_prince_test.4080910898 |
Directory | /workspace/21.prim_prince_test/latest |
Test location | /workspace/coverage/default/210.prim_prince_test.760743061 |
Short name | T13 |
Test name | |
Test status | |
Simulation time | 3241012955 ps |
CPU time | 51.96 seconds |
Started | Aug 17 04:25:32 PM PDT 24 |
Finished | Aug 17 04:26:35 PM PDT 24 |
Peak memory | 146220 kb |
Host | smart-8a4402c0-5586-4f1a-be9a-e92fdfbf610e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=760743061 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 210.prim_prince_test.760743061 |
Directory | /workspace/210.prim_prince_test/latest |
Test location | /workspace/coverage/default/211.prim_prince_test.187975962 |
Short name | T385 |
Test name | |
Test status | |
Simulation time | 3645389643 ps |
CPU time | 57.91 seconds |
Started | Aug 17 04:25:33 PM PDT 24 |
Finished | Aug 17 04:26:41 PM PDT 24 |
Peak memory | 146220 kb |
Host | smart-fb71dfaf-2f76-4e2d-8acf-ce2689ff63f5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=187975962 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 211.prim_prince_test.187975962 |
Directory | /workspace/211.prim_prince_test/latest |
Test location | /workspace/coverage/default/212.prim_prince_test.3429432809 |
Short name | T68 |
Test name | |
Test status | |
Simulation time | 2941722192 ps |
CPU time | 47.83 seconds |
Started | Aug 17 04:21:41 PM PDT 24 |
Finished | Aug 17 04:22:38 PM PDT 24 |
Peak memory | 146384 kb |
Host | smart-55b41725-4331-4c6e-a0cb-9f6814ac222c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3429432809 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 212.prim_prince_test.3429432809 |
Directory | /workspace/212.prim_prince_test/latest |
Test location | /workspace/coverage/default/213.prim_prince_test.3995027761 |
Short name | T418 |
Test name | |
Test status | |
Simulation time | 1227539734 ps |
CPU time | 20.03 seconds |
Started | Aug 17 04:25:09 PM PDT 24 |
Finished | Aug 17 04:25:33 PM PDT 24 |
Peak memory | 146156 kb |
Host | smart-c8ad279a-e654-4226-8b20-2ac2da7de048 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3995027761 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 213.prim_prince_test.3995027761 |
Directory | /workspace/213.prim_prince_test/latest |
Test location | /workspace/coverage/default/214.prim_prince_test.229103670 |
Short name | T160 |
Test name | |
Test status | |
Simulation time | 1706701223 ps |
CPU time | 29.44 seconds |
Started | Aug 17 04:23:50 PM PDT 24 |
Finished | Aug 17 04:24:26 PM PDT 24 |
Peak memory | 146572 kb |
Host | smart-3789e60d-1e1d-4604-9a70-731fdf611079 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=229103670 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 214.prim_prince_test.229103670 |
Directory | /workspace/214.prim_prince_test/latest |
Test location | /workspace/coverage/default/215.prim_prince_test.1649571144 |
Short name | T131 |
Test name | |
Test status | |
Simulation time | 3726900182 ps |
CPU time | 59.54 seconds |
Started | Aug 17 04:26:04 PM PDT 24 |
Finished | Aug 17 04:27:14 PM PDT 24 |
Peak memory | 146348 kb |
Host | smart-71705450-e706-4ab3-b359-6a80ae08183d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1649571144 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 215.prim_prince_test.1649571144 |
Directory | /workspace/215.prim_prince_test/latest |
Test location | /workspace/coverage/default/216.prim_prince_test.2469237716 |
Short name | T277 |
Test name | |
Test status | |
Simulation time | 3653983807 ps |
CPU time | 62.09 seconds |
Started | Aug 17 04:22:19 PM PDT 24 |
Finished | Aug 17 04:23:35 PM PDT 24 |
Peak memory | 146632 kb |
Host | smart-05ac95ea-b106-46bf-b4ab-47cb8fe55892 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2469237716 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 216.prim_prince_test.2469237716 |
Directory | /workspace/216.prim_prince_test/latest |
Test location | /workspace/coverage/default/217.prim_prince_test.426072436 |
Short name | T488 |
Test name | |
Test status | |
Simulation time | 1645075494 ps |
CPU time | 28.03 seconds |
Started | Aug 17 04:22:20 PM PDT 24 |
Finished | Aug 17 04:22:54 PM PDT 24 |
Peak memory | 146532 kb |
Host | smart-3f68bcb8-ecfe-42ab-95a2-f223aaf3cbff |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=426072436 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 217.prim_prince_test.426072436 |
Directory | /workspace/217.prim_prince_test/latest |
Test location | /workspace/coverage/default/218.prim_prince_test.1054886134 |
Short name | T341 |
Test name | |
Test status | |
Simulation time | 2055296016 ps |
CPU time | 33.48 seconds |
Started | Aug 17 04:25:37 PM PDT 24 |
Finished | Aug 17 04:26:17 PM PDT 24 |
Peak memory | 146156 kb |
Host | smart-45181d75-ca60-419b-8056-f9c4319c965d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1054886134 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 218.prim_prince_test.1054886134 |
Directory | /workspace/218.prim_prince_test/latest |
Test location | /workspace/coverage/default/219.prim_prince_test.3787925184 |
Short name | T136 |
Test name | |
Test status | |
Simulation time | 3188106550 ps |
CPU time | 52.15 seconds |
Started | Aug 17 04:22:30 PM PDT 24 |
Finished | Aug 17 04:23:33 PM PDT 24 |
Peak memory | 146572 kb |
Host | smart-66f6e01d-51a2-4f4d-87e3-591ed452567c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3787925184 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 219.prim_prince_test.3787925184 |
Directory | /workspace/219.prim_prince_test/latest |
Test location | /workspace/coverage/default/22.prim_prince_test.986788298 |
Short name | T74 |
Test name | |
Test status | |
Simulation time | 3445785820 ps |
CPU time | 56.36 seconds |
Started | Aug 17 04:20:27 PM PDT 24 |
Finished | Aug 17 04:21:34 PM PDT 24 |
Peak memory | 144676 kb |
Host | smart-70081fe4-0de4-4138-9172-c66ea5d689e5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=986788298 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_prince_test.986788298 |
Directory | /workspace/22.prim_prince_test/latest |
Test location | /workspace/coverage/default/220.prim_prince_test.2882923563 |
Short name | T319 |
Test name | |
Test status | |
Simulation time | 863696364 ps |
CPU time | 13.93 seconds |
Started | Aug 17 04:25:36 PM PDT 24 |
Finished | Aug 17 04:25:53 PM PDT 24 |
Peak memory | 146092 kb |
Host | smart-086da0bf-f088-4095-a0cc-5cfe128091e3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2882923563 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 220.prim_prince_test.2882923563 |
Directory | /workspace/220.prim_prince_test/latest |
Test location | /workspace/coverage/default/221.prim_prince_test.848204208 |
Short name | T278 |
Test name | |
Test status | |
Simulation time | 3499701524 ps |
CPU time | 58.42 seconds |
Started | Aug 17 04:23:23 PM PDT 24 |
Finished | Aug 17 04:24:34 PM PDT 24 |
Peak memory | 146564 kb |
Host | smart-2246b2a7-b766-4279-be3f-65d1ae715ee7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=848204208 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 221.prim_prince_test.848204208 |
Directory | /workspace/221.prim_prince_test/latest |
Test location | /workspace/coverage/default/222.prim_prince_test.1346429942 |
Short name | T243 |
Test name | |
Test status | |
Simulation time | 1199454213 ps |
CPU time | 19.81 seconds |
Started | Aug 17 04:25:51 PM PDT 24 |
Finished | Aug 17 04:26:15 PM PDT 24 |
Peak memory | 146148 kb |
Host | smart-9f76e2b4-aa79-446d-acf1-a7c4fe70e0ce |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1346429942 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 222.prim_prince_test.1346429942 |
Directory | /workspace/222.prim_prince_test/latest |
Test location | /workspace/coverage/default/223.prim_prince_test.2380840821 |
Short name | T471 |
Test name | |
Test status | |
Simulation time | 3380453158 ps |
CPU time | 56.65 seconds |
Started | Aug 17 04:24:17 PM PDT 24 |
Finished | Aug 17 04:25:26 PM PDT 24 |
Peak memory | 146384 kb |
Host | smart-58dff884-e252-448d-9cb2-acb2ad359b0b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2380840821 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 223.prim_prince_test.2380840821 |
Directory | /workspace/223.prim_prince_test/latest |
Test location | /workspace/coverage/default/224.prim_prince_test.3355737656 |
Short name | T412 |
Test name | |
Test status | |
Simulation time | 2460014027 ps |
CPU time | 40.06 seconds |
Started | Aug 17 04:24:53 PM PDT 24 |
Finished | Aug 17 04:25:41 PM PDT 24 |
Peak memory | 145252 kb |
Host | smart-bce8dc74-8a04-4b4b-947a-6470ece5b15a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3355737656 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 224.prim_prince_test.3355737656 |
Directory | /workspace/224.prim_prince_test/latest |
Test location | /workspace/coverage/default/225.prim_prince_test.1627771800 |
Short name | T402 |
Test name | |
Test status | |
Simulation time | 2204991567 ps |
CPU time | 37.88 seconds |
Started | Aug 17 04:22:36 PM PDT 24 |
Finished | Aug 17 04:23:23 PM PDT 24 |
Peak memory | 146384 kb |
Host | smart-e6e292c8-e261-4254-9be3-67d387ceb332 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1627771800 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 225.prim_prince_test.1627771800 |
Directory | /workspace/225.prim_prince_test/latest |
Test location | /workspace/coverage/default/226.prim_prince_test.4188451447 |
Short name | T91 |
Test name | |
Test status | |
Simulation time | 3306557924 ps |
CPU time | 55.55 seconds |
Started | Aug 17 04:22:02 PM PDT 24 |
Finished | Aug 17 04:23:08 PM PDT 24 |
Peak memory | 146636 kb |
Host | smart-138db87d-dfd0-4d5c-af4e-9d416efc03f4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4188451447 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 226.prim_prince_test.4188451447 |
Directory | /workspace/226.prim_prince_test/latest |
Test location | /workspace/coverage/default/227.prim_prince_test.327812924 |
Short name | T261 |
Test name | |
Test status | |
Simulation time | 2237620829 ps |
CPU time | 36.15 seconds |
Started | Aug 17 04:25:28 PM PDT 24 |
Finished | Aug 17 04:26:11 PM PDT 24 |
Peak memory | 146388 kb |
Host | smart-59eeff54-83fa-4b3f-b7a2-dbbcb1d83543 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=327812924 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 227.prim_prince_test.327812924 |
Directory | /workspace/227.prim_prince_test/latest |
Test location | /workspace/coverage/default/228.prim_prince_test.3591931605 |
Short name | T30 |
Test name | |
Test status | |
Simulation time | 3351991790 ps |
CPU time | 56.86 seconds |
Started | Aug 17 04:21:58 PM PDT 24 |
Finished | Aug 17 04:23:08 PM PDT 24 |
Peak memory | 146644 kb |
Host | smart-5ddce623-b223-4071-a476-9a7976459481 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3591931605 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 228.prim_prince_test.3591931605 |
Directory | /workspace/228.prim_prince_test/latest |
Test location | /workspace/coverage/default/229.prim_prince_test.455780473 |
Short name | T256 |
Test name | |
Test status | |
Simulation time | 3618772409 ps |
CPU time | 58.8 seconds |
Started | Aug 17 04:24:53 PM PDT 24 |
Finished | Aug 17 04:26:03 PM PDT 24 |
Peak memory | 145052 kb |
Host | smart-781d9628-50f8-43ca-b4f9-65a58060b6a1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=455780473 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 229.prim_prince_test.455780473 |
Directory | /workspace/229.prim_prince_test/latest |
Test location | /workspace/coverage/default/23.prim_prince_test.1185126775 |
Short name | T467 |
Test name | |
Test status | |
Simulation time | 3606436322 ps |
CPU time | 58.86 seconds |
Started | Aug 17 04:20:25 PM PDT 24 |
Finished | Aug 17 04:21:35 PM PDT 24 |
Peak memory | 146216 kb |
Host | smart-1b5035a8-a724-4703-af00-c3c1e5af4371 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1185126775 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_prince_test.1185126775 |
Directory | /workspace/23.prim_prince_test/latest |
Test location | /workspace/coverage/default/230.prim_prince_test.665444752 |
Short name | T209 |
Test name | |
Test status | |
Simulation time | 3265003869 ps |
CPU time | 53.76 seconds |
Started | Aug 17 04:25:08 PM PDT 24 |
Finished | Aug 17 04:26:13 PM PDT 24 |
Peak memory | 146352 kb |
Host | smart-0020e7c6-9dbc-44d7-9f46-e687a6fdd922 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=665444752 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 230.prim_prince_test.665444752 |
Directory | /workspace/230.prim_prince_test/latest |
Test location | /workspace/coverage/default/231.prim_prince_test.4284284258 |
Short name | T174 |
Test name | |
Test status | |
Simulation time | 3444287994 ps |
CPU time | 56.96 seconds |
Started | Aug 17 04:25:08 PM PDT 24 |
Finished | Aug 17 04:26:17 PM PDT 24 |
Peak memory | 145472 kb |
Host | smart-9ca309d9-7b45-4d70-9f91-2e54c89a5816 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4284284258 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 231.prim_prince_test.4284284258 |
Directory | /workspace/231.prim_prince_test/latest |
Test location | /workspace/coverage/default/232.prim_prince_test.3805220057 |
Short name | T2 |
Test name | |
Test status | |
Simulation time | 2591487246 ps |
CPU time | 42.83 seconds |
Started | Aug 17 04:25:08 PM PDT 24 |
Finished | Aug 17 04:26:00 PM PDT 24 |
Peak memory | 145332 kb |
Host | smart-27f8a45a-700a-4102-b194-d7d4e4849ade |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3805220057 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 232.prim_prince_test.3805220057 |
Directory | /workspace/232.prim_prince_test/latest |
Test location | /workspace/coverage/default/233.prim_prince_test.4028816302 |
Short name | T35 |
Test name | |
Test status | |
Simulation time | 1605988018 ps |
CPU time | 26.6 seconds |
Started | Aug 17 04:25:22 PM PDT 24 |
Finished | Aug 17 04:25:55 PM PDT 24 |
Peak memory | 146028 kb |
Host | smart-ddb602a6-795c-47ba-aa0d-30f4bca8f10f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4028816302 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 233.prim_prince_test.4028816302 |
Directory | /workspace/233.prim_prince_test/latest |
Test location | /workspace/coverage/default/234.prim_prince_test.3715946520 |
Short name | T333 |
Test name | |
Test status | |
Simulation time | 2240292076 ps |
CPU time | 36.87 seconds |
Started | Aug 17 04:24:14 PM PDT 24 |
Finished | Aug 17 04:24:59 PM PDT 24 |
Peak memory | 146572 kb |
Host | smart-6ecca35c-27c2-409f-90c9-ec67ce7fe0a9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3715946520 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 234.prim_prince_test.3715946520 |
Directory | /workspace/234.prim_prince_test/latest |
Test location | /workspace/coverage/default/235.prim_prince_test.3611749350 |
Short name | T245 |
Test name | |
Test status | |
Simulation time | 1901740707 ps |
CPU time | 31.38 seconds |
Started | Aug 17 04:24:53 PM PDT 24 |
Finished | Aug 17 04:25:31 PM PDT 24 |
Peak memory | 146192 kb |
Host | smart-292828b1-25f3-436c-8d47-1a7ebcfb044b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3611749350 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 235.prim_prince_test.3611749350 |
Directory | /workspace/235.prim_prince_test/latest |
Test location | /workspace/coverage/default/236.prim_prince_test.3468123881 |
Short name | T132 |
Test name | |
Test status | |
Simulation time | 904184961 ps |
CPU time | 15.37 seconds |
Started | Aug 17 04:22:30 PM PDT 24 |
Finished | Aug 17 04:22:49 PM PDT 24 |
Peak memory | 146424 kb |
Host | smart-62b8cb27-0bc7-42ba-aa70-fe45e06c76c9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3468123881 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 236.prim_prince_test.3468123881 |
Directory | /workspace/236.prim_prince_test/latest |
Test location | /workspace/coverage/default/237.prim_prince_test.3097270057 |
Short name | T452 |
Test name | |
Test status | |
Simulation time | 3140803028 ps |
CPU time | 50.96 seconds |
Started | Aug 17 04:24:16 PM PDT 24 |
Finished | Aug 17 04:25:18 PM PDT 24 |
Peak memory | 146384 kb |
Host | smart-a23b5bf5-3746-4add-8748-8437ead5075a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3097270057 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 237.prim_prince_test.3097270057 |
Directory | /workspace/237.prim_prince_test/latest |
Test location | /workspace/coverage/default/238.prim_prince_test.1058328318 |
Short name | T440 |
Test name | |
Test status | |
Simulation time | 1971883276 ps |
CPU time | 33.98 seconds |
Started | Aug 17 04:22:02 PM PDT 24 |
Finished | Aug 17 04:22:43 PM PDT 24 |
Peak memory | 146576 kb |
Host | smart-b7c90218-70af-4791-9b3c-f990e28054fd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1058328318 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 238.prim_prince_test.1058328318 |
Directory | /workspace/238.prim_prince_test/latest |
Test location | /workspace/coverage/default/239.prim_prince_test.2220271592 |
Short name | T479 |
Test name | |
Test status | |
Simulation time | 883512395 ps |
CPU time | 14.84 seconds |
Started | Aug 17 04:25:23 PM PDT 24 |
Finished | Aug 17 04:25:41 PM PDT 24 |
Peak memory | 146656 kb |
Host | smart-252ed03f-4413-4e07-ba83-1ea94e678470 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2220271592 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 239.prim_prince_test.2220271592 |
Directory | /workspace/239.prim_prince_test/latest |
Test location | /workspace/coverage/default/24.prim_prince_test.2525791376 |
Short name | T290 |
Test name | |
Test status | |
Simulation time | 2194981666 ps |
CPU time | 35.09 seconds |
Started | Aug 17 04:20:26 PM PDT 24 |
Finished | Aug 17 04:21:08 PM PDT 24 |
Peak memory | 146168 kb |
Host | smart-378027af-f8ba-4fd7-9073-394f9593d095 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2525791376 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_prince_test.2525791376 |
Directory | /workspace/24.prim_prince_test/latest |
Test location | /workspace/coverage/default/240.prim_prince_test.1810941289 |
Short name | T75 |
Test name | |
Test status | |
Simulation time | 3357941078 ps |
CPU time | 55.53 seconds |
Started | Aug 17 04:25:07 PM PDT 24 |
Finished | Aug 17 04:26:14 PM PDT 24 |
Peak memory | 146348 kb |
Host | smart-afc0b427-e12d-4c6b-83f9-68ad90afdc5c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1810941289 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 240.prim_prince_test.1810941289 |
Directory | /workspace/240.prim_prince_test/latest |
Test location | /workspace/coverage/default/241.prim_prince_test.2334577748 |
Short name | T377 |
Test name | |
Test status | |
Simulation time | 2564234048 ps |
CPU time | 42.1 seconds |
Started | Aug 17 04:25:22 PM PDT 24 |
Finished | Aug 17 04:26:13 PM PDT 24 |
Peak memory | 146160 kb |
Host | smart-058def81-855e-4582-bfd7-831332b1cd32 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2334577748 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 241.prim_prince_test.2334577748 |
Directory | /workspace/241.prim_prince_test/latest |
Test location | /workspace/coverage/default/242.prim_prince_test.2117072355 |
Short name | T249 |
Test name | |
Test status | |
Simulation time | 2483111402 ps |
CPU time | 41.73 seconds |
Started | Aug 17 04:24:17 PM PDT 24 |
Finished | Aug 17 04:25:08 PM PDT 24 |
Peak memory | 146384 kb |
Host | smart-d40c8d60-e115-4ff9-8bd3-118a695c2bb0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2117072355 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 242.prim_prince_test.2117072355 |
Directory | /workspace/242.prim_prince_test/latest |
Test location | /workspace/coverage/default/243.prim_prince_test.841154487 |
Short name | T124 |
Test name | |
Test status | |
Simulation time | 2217326134 ps |
CPU time | 35.71 seconds |
Started | Aug 17 04:25:24 PM PDT 24 |
Finished | Aug 17 04:26:07 PM PDT 24 |
Peak memory | 146004 kb |
Host | smart-6620dafd-5a7b-4da8-86d9-883be15204b8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=841154487 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 243.prim_prince_test.841154487 |
Directory | /workspace/243.prim_prince_test/latest |
Test location | /workspace/coverage/default/244.prim_prince_test.1094724863 |
Short name | T28 |
Test name | |
Test status | |
Simulation time | 3722412981 ps |
CPU time | 65.17 seconds |
Started | Aug 17 04:22:07 PM PDT 24 |
Finished | Aug 17 04:23:27 PM PDT 24 |
Peak memory | 146624 kb |
Host | smart-61d598b9-bcb8-45fd-b8c0-a58f2226510e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1094724863 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 244.prim_prince_test.1094724863 |
Directory | /workspace/244.prim_prince_test/latest |
Test location | /workspace/coverage/default/245.prim_prince_test.3911764146 |
Short name | T221 |
Test name | |
Test status | |
Simulation time | 2496897087 ps |
CPU time | 40.66 seconds |
Started | Aug 17 04:25:48 PM PDT 24 |
Finished | Aug 17 04:26:37 PM PDT 24 |
Peak memory | 146428 kb |
Host | smart-c499da66-a896-4f32-8716-50c41c09cf46 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3911764146 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 245.prim_prince_test.3911764146 |
Directory | /workspace/245.prim_prince_test/latest |
Test location | /workspace/coverage/default/246.prim_prince_test.4202985374 |
Short name | T9 |
Test name | |
Test status | |
Simulation time | 1591597096 ps |
CPU time | 26.32 seconds |
Started | Aug 17 04:25:48 PM PDT 24 |
Finished | Aug 17 04:26:19 PM PDT 24 |
Peak memory | 146340 kb |
Host | smart-eb148e32-b496-4a46-bf90-626f646f0d59 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4202985374 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 246.prim_prince_test.4202985374 |
Directory | /workspace/246.prim_prince_test/latest |
Test location | /workspace/coverage/default/247.prim_prince_test.2728928447 |
Short name | T67 |
Test name | |
Test status | |
Simulation time | 2478868114 ps |
CPU time | 39.8 seconds |
Started | Aug 17 04:25:34 PM PDT 24 |
Finished | Aug 17 04:26:22 PM PDT 24 |
Peak memory | 146212 kb |
Host | smart-0139d725-acc7-4955-beeb-04a5b8f6cbcf |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2728928447 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 247.prim_prince_test.2728928447 |
Directory | /workspace/247.prim_prince_test/latest |
Test location | /workspace/coverage/default/248.prim_prince_test.231869680 |
Short name | T242 |
Test name | |
Test status | |
Simulation time | 3143008794 ps |
CPU time | 50.01 seconds |
Started | Aug 17 04:25:24 PM PDT 24 |
Finished | Aug 17 04:26:24 PM PDT 24 |
Peak memory | 146200 kb |
Host | smart-7063f846-7952-4219-bd97-cf5170e49bee |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=231869680 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 248.prim_prince_test.231869680 |
Directory | /workspace/248.prim_prince_test/latest |
Test location | /workspace/coverage/default/249.prim_prince_test.727683808 |
Short name | T351 |
Test name | |
Test status | |
Simulation time | 2654216425 ps |
CPU time | 43.14 seconds |
Started | Aug 17 04:25:24 PM PDT 24 |
Finished | Aug 17 04:26:16 PM PDT 24 |
Peak memory | 146228 kb |
Host | smart-ca2ee1b3-91ee-4456-8dfb-eb6cab4d8740 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=727683808 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 249.prim_prince_test.727683808 |
Directory | /workspace/249.prim_prince_test/latest |
Test location | /workspace/coverage/default/25.prim_prince_test.2041206882 |
Short name | T53 |
Test name | |
Test status | |
Simulation time | 1669127200 ps |
CPU time | 28.5 seconds |
Started | Aug 17 04:20:26 PM PDT 24 |
Finished | Aug 17 04:21:00 PM PDT 24 |
Peak memory | 146096 kb |
Host | smart-8d1072c0-4449-43b5-8850-97b01321b218 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2041206882 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_prince_test.2041206882 |
Directory | /workspace/25.prim_prince_test/latest |
Test location | /workspace/coverage/default/250.prim_prince_test.4291165867 |
Short name | T309 |
Test name | |
Test status | |
Simulation time | 2045569812 ps |
CPU time | 32.88 seconds |
Started | Aug 17 04:25:26 PM PDT 24 |
Finished | Aug 17 04:26:05 PM PDT 24 |
Peak memory | 146156 kb |
Host | smart-47e2c4de-ecd7-43e0-a2ea-1d563467a818 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4291165867 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 250.prim_prince_test.4291165867 |
Directory | /workspace/250.prim_prince_test/latest |
Test location | /workspace/coverage/default/251.prim_prince_test.1214169213 |
Short name | T126 |
Test name | |
Test status | |
Simulation time | 3305648429 ps |
CPU time | 53.59 seconds |
Started | Aug 17 04:25:24 PM PDT 24 |
Finished | Aug 17 04:26:28 PM PDT 24 |
Peak memory | 146004 kb |
Host | smart-7e8b8a1a-d5eb-46ff-8d25-d9d8fb78906d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1214169213 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 251.prim_prince_test.1214169213 |
Directory | /workspace/251.prim_prince_test/latest |
Test location | /workspace/coverage/default/252.prim_prince_test.194845811 |
Short name | T358 |
Test name | |
Test status | |
Simulation time | 1800883536 ps |
CPU time | 29.48 seconds |
Started | Aug 17 04:25:48 PM PDT 24 |
Finished | Aug 17 04:26:24 PM PDT 24 |
Peak memory | 146468 kb |
Host | smart-133a6c69-03de-4f26-82be-0d306f1a2349 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=194845811 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 252.prim_prince_test.194845811 |
Directory | /workspace/252.prim_prince_test/latest |
Test location | /workspace/coverage/default/253.prim_prince_test.62237392 |
Short name | T433 |
Test name | |
Test status | |
Simulation time | 886490527 ps |
CPU time | 14.35 seconds |
Started | Aug 17 04:25:15 PM PDT 24 |
Finished | Aug 17 04:25:32 PM PDT 24 |
Peak memory | 146112 kb |
Host | smart-34d7587b-3ba5-4631-8c32-6925600e6a9f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=62237392 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 253.prim_prince_test.62237392 |
Directory | /workspace/253.prim_prince_test/latest |
Test location | /workspace/coverage/default/254.prim_prince_test.2872855371 |
Short name | T157 |
Test name | |
Test status | |
Simulation time | 2516392420 ps |
CPU time | 39.65 seconds |
Started | Aug 17 04:25:35 PM PDT 24 |
Finished | Aug 17 04:26:21 PM PDT 24 |
Peak memory | 146212 kb |
Host | smart-5ecd7c01-f8fc-4759-b367-90db5bda47b9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2872855371 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 254.prim_prince_test.2872855371 |
Directory | /workspace/254.prim_prince_test/latest |
Test location | /workspace/coverage/default/255.prim_prince_test.4188415283 |
Short name | T215 |
Test name | |
Test status | |
Simulation time | 2479898504 ps |
CPU time | 39.78 seconds |
Started | Aug 17 04:25:48 PM PDT 24 |
Finished | Aug 17 04:26:35 PM PDT 24 |
Peak memory | 146404 kb |
Host | smart-eeaa8776-e8ac-46ed-9f5e-76b97809df37 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4188415283 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 255.prim_prince_test.4188415283 |
Directory | /workspace/255.prim_prince_test/latest |
Test location | /workspace/coverage/default/256.prim_prince_test.2291840730 |
Short name | T450 |
Test name | |
Test status | |
Simulation time | 2321395769 ps |
CPU time | 37.19 seconds |
Started | Aug 17 04:25:34 PM PDT 24 |
Finished | Aug 17 04:26:19 PM PDT 24 |
Peak memory | 146212 kb |
Host | smart-830dc031-0ef4-491f-b7b6-509bfb0d979d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2291840730 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 256.prim_prince_test.2291840730 |
Directory | /workspace/256.prim_prince_test/latest |
Test location | /workspace/coverage/default/257.prim_prince_test.3679498995 |
Short name | T102 |
Test name | |
Test status | |
Simulation time | 2444072514 ps |
CPU time | 41.36 seconds |
Started | Aug 17 04:22:54 PM PDT 24 |
Finished | Aug 17 04:23:44 PM PDT 24 |
Peak memory | 146648 kb |
Host | smart-8ee7154e-a54a-42f2-9239-b4db88c88ef1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3679498995 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 257.prim_prince_test.3679498995 |
Directory | /workspace/257.prim_prince_test/latest |
Test location | /workspace/coverage/default/258.prim_prince_test.3560193725 |
Short name | T122 |
Test name | |
Test status | |
Simulation time | 933358700 ps |
CPU time | 14.64 seconds |
Started | Aug 17 04:24:58 PM PDT 24 |
Finished | Aug 17 04:25:15 PM PDT 24 |
Peak memory | 146336 kb |
Host | smart-df8d9970-172a-47aa-9db9-268a20d3fdb2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3560193725 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 258.prim_prince_test.3560193725 |
Directory | /workspace/258.prim_prince_test/latest |
Test location | /workspace/coverage/default/259.prim_prince_test.2704548853 |
Short name | T228 |
Test name | |
Test status | |
Simulation time | 3739734327 ps |
CPU time | 62.03 seconds |
Started | Aug 17 04:25:02 PM PDT 24 |
Finished | Aug 17 04:26:17 PM PDT 24 |
Peak memory | 146424 kb |
Host | smart-97c18b7e-e09d-4047-9755-7e2ccd62cf69 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2704548853 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 259.prim_prince_test.2704548853 |
Directory | /workspace/259.prim_prince_test/latest |
Test location | /workspace/coverage/default/26.prim_prince_test.2037016935 |
Short name | T230 |
Test name | |
Test status | |
Simulation time | 2428773499 ps |
CPU time | 39.48 seconds |
Started | Aug 17 04:20:16 PM PDT 24 |
Finished | Aug 17 04:21:03 PM PDT 24 |
Peak memory | 145036 kb |
Host | smart-763e48e7-c0b6-4f7f-825b-6fa47be7a932 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2037016935 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_prince_test.2037016935 |
Directory | /workspace/26.prim_prince_test/latest |
Test location | /workspace/coverage/default/260.prim_prince_test.1528880598 |
Short name | T359 |
Test name | |
Test status | |
Simulation time | 1294915990 ps |
CPU time | 21.56 seconds |
Started | Aug 17 04:23:50 PM PDT 24 |
Finished | Aug 17 04:24:16 PM PDT 24 |
Peak memory | 146452 kb |
Host | smart-d1f974c0-de96-4a63-a010-ff0e04ffbeba |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1528880598 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 260.prim_prince_test.1528880598 |
Directory | /workspace/260.prim_prince_test/latest |
Test location | /workspace/coverage/default/261.prim_prince_test.3125211220 |
Short name | T304 |
Test name | |
Test status | |
Simulation time | 2238676976 ps |
CPU time | 38.17 seconds |
Started | Aug 17 04:23:23 PM PDT 24 |
Finished | Aug 17 04:24:10 PM PDT 24 |
Peak memory | 146644 kb |
Host | smart-5f890189-6552-4e69-be6d-31c0a9c22219 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3125211220 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 261.prim_prince_test.3125211220 |
Directory | /workspace/261.prim_prince_test/latest |
Test location | /workspace/coverage/default/262.prim_prince_test.4147091805 |
Short name | T343 |
Test name | |
Test status | |
Simulation time | 807399710 ps |
CPU time | 13.07 seconds |
Started | Aug 17 04:25:35 PM PDT 24 |
Finished | Aug 17 04:25:50 PM PDT 24 |
Peak memory | 146728 kb |
Host | smart-3205f986-68ca-479b-b74c-8480fc119a11 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4147091805 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 262.prim_prince_test.4147091805 |
Directory | /workspace/262.prim_prince_test/latest |
Test location | /workspace/coverage/default/263.prim_prince_test.3048725110 |
Short name | T480 |
Test name | |
Test status | |
Simulation time | 1729393973 ps |
CPU time | 29 seconds |
Started | Aug 17 04:22:50 PM PDT 24 |
Finished | Aug 17 04:23:24 PM PDT 24 |
Peak memory | 146504 kb |
Host | smart-36368df0-0a2b-44a5-83c7-d2efdd05d0d3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3048725110 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 263.prim_prince_test.3048725110 |
Directory | /workspace/263.prim_prince_test/latest |
Test location | /workspace/coverage/default/264.prim_prince_test.4173900710 |
Short name | T187 |
Test name | |
Test status | |
Simulation time | 1656691241 ps |
CPU time | 26.59 seconds |
Started | Aug 17 04:25:53 PM PDT 24 |
Finished | Aug 17 04:26:25 PM PDT 24 |
Peak memory | 146276 kb |
Host | smart-59b1051e-792f-48a4-b8e7-90081bf415bc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4173900710 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 264.prim_prince_test.4173900710 |
Directory | /workspace/264.prim_prince_test/latest |
Test location | /workspace/coverage/default/265.prim_prince_test.2430077257 |
Short name | T60 |
Test name | |
Test status | |
Simulation time | 2924813088 ps |
CPU time | 49.96 seconds |
Started | Aug 17 04:22:47 PM PDT 24 |
Finished | Aug 17 04:23:47 PM PDT 24 |
Peak memory | 146628 kb |
Host | smart-01aa76a8-4d05-420d-8a62-7013001541cc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2430077257 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 265.prim_prince_test.2430077257 |
Directory | /workspace/265.prim_prince_test/latest |
Test location | /workspace/coverage/default/266.prim_prince_test.2063108066 |
Short name | T499 |
Test name | |
Test status | |
Simulation time | 1136191970 ps |
CPU time | 19.44 seconds |
Started | Aug 17 04:22:18 PM PDT 24 |
Finished | Aug 17 04:22:41 PM PDT 24 |
Peak memory | 146564 kb |
Host | smart-6bc68d36-ccc6-4d00-be55-ad08bcb4320c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2063108066 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 266.prim_prince_test.2063108066 |
Directory | /workspace/266.prim_prince_test/latest |
Test location | /workspace/coverage/default/267.prim_prince_test.1003394477 |
Short name | T42 |
Test name | |
Test status | |
Simulation time | 3444152226 ps |
CPU time | 55.15 seconds |
Started | Aug 17 04:25:34 PM PDT 24 |
Finished | Aug 17 04:26:39 PM PDT 24 |
Peak memory | 146196 kb |
Host | smart-0801bd61-31b6-4831-92cd-2288f5642a50 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1003394477 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 267.prim_prince_test.1003394477 |
Directory | /workspace/267.prim_prince_test/latest |
Test location | /workspace/coverage/default/268.prim_prince_test.3241603559 |
Short name | T387 |
Test name | |
Test status | |
Simulation time | 1745602275 ps |
CPU time | 29.12 seconds |
Started | Aug 17 04:22:46 PM PDT 24 |
Finished | Aug 17 04:23:21 PM PDT 24 |
Peak memory | 146584 kb |
Host | smart-831f05ee-34b4-4b58-99d6-9f6e626d4312 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3241603559 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 268.prim_prince_test.3241603559 |
Directory | /workspace/268.prim_prince_test/latest |
Test location | /workspace/coverage/default/269.prim_prince_test.3932583380 |
Short name | T308 |
Test name | |
Test status | |
Simulation time | 2736357659 ps |
CPU time | 44.91 seconds |
Started | Aug 17 04:25:47 PM PDT 24 |
Finished | Aug 17 04:26:46 PM PDT 24 |
Peak memory | 146336 kb |
Host | smart-5673ff82-22fb-41f8-a3c0-c1796bc1955a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3932583380 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 269.prim_prince_test.3932583380 |
Directory | /workspace/269.prim_prince_test/latest |
Test location | /workspace/coverage/default/27.prim_prince_test.4080462331 |
Short name | T121 |
Test name | |
Test status | |
Simulation time | 1916913547 ps |
CPU time | 32.27 seconds |
Started | Aug 17 04:20:25 PM PDT 24 |
Finished | Aug 17 04:21:05 PM PDT 24 |
Peak memory | 145328 kb |
Host | smart-0cb1c963-736a-4614-bc11-6c55ec555b47 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4080462331 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_prince_test.4080462331 |
Directory | /workspace/27.prim_prince_test/latest |
Test location | /workspace/coverage/default/270.prim_prince_test.1937793919 |
Short name | T172 |
Test name | |
Test status | |
Simulation time | 1391444169 ps |
CPU time | 23.92 seconds |
Started | Aug 17 04:22:46 PM PDT 24 |
Finished | Aug 17 04:23:15 PM PDT 24 |
Peak memory | 146584 kb |
Host | smart-cfbdb286-27e0-4b23-9a04-f452bb9b8a10 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1937793919 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 270.prim_prince_test.1937793919 |
Directory | /workspace/270.prim_prince_test/latest |
Test location | /workspace/coverage/default/271.prim_prince_test.4134408645 |
Short name | T188 |
Test name | |
Test status | |
Simulation time | 2984652050 ps |
CPU time | 47.38 seconds |
Started | Aug 17 04:25:34 PM PDT 24 |
Finished | Aug 17 04:26:31 PM PDT 24 |
Peak memory | 146196 kb |
Host | smart-32ac0aa8-63d6-47d7-91c3-b49e58c7f163 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4134408645 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 271.prim_prince_test.4134408645 |
Directory | /workspace/271.prim_prince_test/latest |
Test location | /workspace/coverage/default/272.prim_prince_test.1705693687 |
Short name | T96 |
Test name | |
Test status | |
Simulation time | 3392399713 ps |
CPU time | 56.41 seconds |
Started | Aug 17 04:25:20 PM PDT 24 |
Finished | Aug 17 04:26:29 PM PDT 24 |
Peak memory | 145592 kb |
Host | smart-f05b2902-dfb1-472b-bfcb-af236c6163da |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1705693687 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 272.prim_prince_test.1705693687 |
Directory | /workspace/272.prim_prince_test/latest |
Test location | /workspace/coverage/default/273.prim_prince_test.269974912 |
Short name | T185 |
Test name | |
Test status | |
Simulation time | 2791470358 ps |
CPU time | 46.54 seconds |
Started | Aug 17 04:22:18 PM PDT 24 |
Finished | Aug 17 04:23:14 PM PDT 24 |
Peak memory | 146596 kb |
Host | smart-0fa273e3-c1e4-4314-925d-db6157f9a723 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=269974912 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 273.prim_prince_test.269974912 |
Directory | /workspace/273.prim_prince_test/latest |
Test location | /workspace/coverage/default/274.prim_prince_test.536751932 |
Short name | T449 |
Test name | |
Test status | |
Simulation time | 3259325874 ps |
CPU time | 52.66 seconds |
Started | Aug 17 04:25:34 PM PDT 24 |
Finished | Aug 17 04:26:37 PM PDT 24 |
Peak memory | 146192 kb |
Host | smart-ba47a4ec-5474-4d73-aa4e-faee87334fe4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=536751932 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 274.prim_prince_test.536751932 |
Directory | /workspace/274.prim_prince_test/latest |
Test location | /workspace/coverage/default/275.prim_prince_test.2483063059 |
Short name | T321 |
Test name | |
Test status | |
Simulation time | 1954060866 ps |
CPU time | 33.27 seconds |
Started | Aug 17 04:22:53 PM PDT 24 |
Finished | Aug 17 04:23:34 PM PDT 24 |
Peak memory | 146572 kb |
Host | smart-9f0dae4c-f763-4bcd-be95-47fb9893cca1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2483063059 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 275.prim_prince_test.2483063059 |
Directory | /workspace/275.prim_prince_test/latest |
Test location | /workspace/coverage/default/276.prim_prince_test.3148375821 |
Short name | T403 |
Test name | |
Test status | |
Simulation time | 3327633172 ps |
CPU time | 56.07 seconds |
Started | Aug 17 04:26:08 PM PDT 24 |
Finished | Aug 17 04:27:17 PM PDT 24 |
Peak memory | 144384 kb |
Host | smart-f959071c-90a9-48ea-a0b9-6fc8e7d098d8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3148375821 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 276.prim_prince_test.3148375821 |
Directory | /workspace/276.prim_prince_test/latest |
Test location | /workspace/coverage/default/277.prim_prince_test.491693610 |
Short name | T490 |
Test name | |
Test status | |
Simulation time | 3453367100 ps |
CPU time | 57.66 seconds |
Started | Aug 17 04:25:02 PM PDT 24 |
Finished | Aug 17 04:26:12 PM PDT 24 |
Peak memory | 146432 kb |
Host | smart-e65be9a8-5941-4643-b56e-600de815eed3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=491693610 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 277.prim_prince_test.491693610 |
Directory | /workspace/277.prim_prince_test/latest |
Test location | /workspace/coverage/default/278.prim_prince_test.2281093261 |
Short name | T15 |
Test name | |
Test status | |
Simulation time | 1548655445 ps |
CPU time | 25.12 seconds |
Started | Aug 17 04:24:48 PM PDT 24 |
Finished | Aug 17 04:25:18 PM PDT 24 |
Peak memory | 146220 kb |
Host | smart-cd384226-90bd-4790-8ec9-1e4137f9e66c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2281093261 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 278.prim_prince_test.2281093261 |
Directory | /workspace/278.prim_prince_test/latest |
Test location | /workspace/coverage/default/279.prim_prince_test.2378429990 |
Short name | T11 |
Test name | |
Test status | |
Simulation time | 1854578734 ps |
CPU time | 29.72 seconds |
Started | Aug 17 04:25:33 PM PDT 24 |
Finished | Aug 17 04:26:08 PM PDT 24 |
Peak memory | 146728 kb |
Host | smart-63688ffa-770b-47fc-8ffd-be4d57e03de3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2378429990 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 279.prim_prince_test.2378429990 |
Directory | /workspace/279.prim_prince_test/latest |
Test location | /workspace/coverage/default/28.prim_prince_test.3664736789 |
Short name | T441 |
Test name | |
Test status | |
Simulation time | 1711482951 ps |
CPU time | 28.23 seconds |
Started | Aug 17 04:20:28 PM PDT 24 |
Finished | Aug 17 04:21:01 PM PDT 24 |
Peak memory | 146200 kb |
Host | smart-37ec03a4-6315-4d54-aa2b-67dd67c532a4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3664736789 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_prince_test.3664736789 |
Directory | /workspace/28.prim_prince_test/latest |
Test location | /workspace/coverage/default/280.prim_prince_test.407539139 |
Short name | T73 |
Test name | |
Test status | |
Simulation time | 3038102424 ps |
CPU time | 48.53 seconds |
Started | Aug 17 04:25:35 PM PDT 24 |
Finished | Aug 17 04:26:32 PM PDT 24 |
Peak memory | 146192 kb |
Host | smart-59e3e030-cff7-4ffb-ada7-b435bca91385 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=407539139 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 280.prim_prince_test.407539139 |
Directory | /workspace/280.prim_prince_test/latest |
Test location | /workspace/coverage/default/281.prim_prince_test.583919327 |
Short name | T434 |
Test name | |
Test status | |
Simulation time | 1663650721 ps |
CPU time | 27.84 seconds |
Started | Aug 17 04:22:46 PM PDT 24 |
Finished | Aug 17 04:23:20 PM PDT 24 |
Peak memory | 146520 kb |
Host | smart-280a12d3-aa21-4689-aca5-95c06c986992 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=583919327 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 281.prim_prince_test.583919327 |
Directory | /workspace/281.prim_prince_test/latest |
Test location | /workspace/coverage/default/282.prim_prince_test.2253772564 |
Short name | T247 |
Test name | |
Test status | |
Simulation time | 1690474767 ps |
CPU time | 27.68 seconds |
Started | Aug 17 04:25:02 PM PDT 24 |
Finished | Aug 17 04:25:36 PM PDT 24 |
Peak memory | 146140 kb |
Host | smart-40db9486-ac34-499b-a9e1-3d4ac7717376 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2253772564 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 282.prim_prince_test.2253772564 |
Directory | /workspace/282.prim_prince_test/latest |
Test location | /workspace/coverage/default/283.prim_prince_test.2977058325 |
Short name | T330 |
Test name | |
Test status | |
Simulation time | 948259406 ps |
CPU time | 15.63 seconds |
Started | Aug 17 04:25:34 PM PDT 24 |
Finished | Aug 17 04:25:53 PM PDT 24 |
Peak memory | 146132 kb |
Host | smart-c465b8c3-3ea6-4a14-a91e-ef2ba37d3b55 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2977058325 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 283.prim_prince_test.2977058325 |
Directory | /workspace/283.prim_prince_test/latest |
Test location | /workspace/coverage/default/284.prim_prince_test.3960459293 |
Short name | T204 |
Test name | |
Test status | |
Simulation time | 2107049263 ps |
CPU time | 34.08 seconds |
Started | Aug 17 04:25:32 PM PDT 24 |
Finished | Aug 17 04:26:13 PM PDT 24 |
Peak memory | 146132 kb |
Host | smart-7cb66d88-e560-4925-b72d-75cfe68a632d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3960459293 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 284.prim_prince_test.3960459293 |
Directory | /workspace/284.prim_prince_test/latest |
Test location | /workspace/coverage/default/285.prim_prince_test.1384201559 |
Short name | T232 |
Test name | |
Test status | |
Simulation time | 1539716047 ps |
CPU time | 24.85 seconds |
Started | Aug 17 04:25:35 PM PDT 24 |
Finished | Aug 17 04:26:04 PM PDT 24 |
Peak memory | 146132 kb |
Host | smart-d93ee869-0102-4ba1-a04e-8068cf828564 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1384201559 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 285.prim_prince_test.1384201559 |
Directory | /workspace/285.prim_prince_test/latest |
Test location | /workspace/coverage/default/286.prim_prince_test.3588683168 |
Short name | T273 |
Test name | |
Test status | |
Simulation time | 1667538053 ps |
CPU time | 28.1 seconds |
Started | Aug 17 04:22:15 PM PDT 24 |
Finished | Aug 17 04:22:49 PM PDT 24 |
Peak memory | 146584 kb |
Host | smart-d2ef1e5a-7c52-4ce6-a5e6-b5ee92cce4a6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3588683168 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 286.prim_prince_test.3588683168 |
Directory | /workspace/286.prim_prince_test/latest |
Test location | /workspace/coverage/default/287.prim_prince_test.226916549 |
Short name | T293 |
Test name | |
Test status | |
Simulation time | 2942456606 ps |
CPU time | 46.94 seconds |
Started | Aug 17 04:25:34 PM PDT 24 |
Finished | Aug 17 04:26:30 PM PDT 24 |
Peak memory | 146192 kb |
Host | smart-c85b32e4-9530-4c38-b2a7-3e874293265f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=226916549 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 287.prim_prince_test.226916549 |
Directory | /workspace/287.prim_prince_test/latest |
Test location | /workspace/coverage/default/288.prim_prince_test.916109920 |
Short name | T463 |
Test name | |
Test status | |
Simulation time | 3641966920 ps |
CPU time | 59.75 seconds |
Started | Aug 17 04:24:48 PM PDT 24 |
Finished | Aug 17 04:25:59 PM PDT 24 |
Peak memory | 145372 kb |
Host | smart-9c321f30-b1a8-462c-ab99-76598fed2e8d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=916109920 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 288.prim_prince_test.916109920 |
Directory | /workspace/288.prim_prince_test/latest |
Test location | /workspace/coverage/default/289.prim_prince_test.1649707383 |
Short name | T348 |
Test name | |
Test status | |
Simulation time | 3515645768 ps |
CPU time | 58.8 seconds |
Started | Aug 17 04:25:20 PM PDT 24 |
Finished | Aug 17 04:26:31 PM PDT 24 |
Peak memory | 145068 kb |
Host | smart-776f4422-dd4d-4cb8-b79c-7c68cbc5a460 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1649707383 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 289.prim_prince_test.1649707383 |
Directory | /workspace/289.prim_prince_test/latest |
Test location | /workspace/coverage/default/29.prim_prince_test.2112895301 |
Short name | T398 |
Test name | |
Test status | |
Simulation time | 2559383265 ps |
CPU time | 42.62 seconds |
Started | Aug 17 04:22:30 PM PDT 24 |
Finished | Aug 17 04:23:22 PM PDT 24 |
Peak memory | 146584 kb |
Host | smart-5883dd30-a159-4ba8-acd8-cb929357463e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2112895301 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_prince_test.2112895301 |
Directory | /workspace/29.prim_prince_test/latest |
Test location | /workspace/coverage/default/290.prim_prince_test.256816026 |
Short name | T248 |
Test name | |
Test status | |
Simulation time | 1650485607 ps |
CPU time | 25.37 seconds |
Started | Aug 17 04:24:57 PM PDT 24 |
Finished | Aug 17 04:25:27 PM PDT 24 |
Peak memory | 146100 kb |
Host | smart-926c6586-e52c-494e-9118-d3dee7937726 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=256816026 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 290.prim_prince_test.256816026 |
Directory | /workspace/290.prim_prince_test/latest |
Test location | /workspace/coverage/default/291.prim_prince_test.361006197 |
Short name | T422 |
Test name | |
Test status | |
Simulation time | 1169163353 ps |
CPU time | 18.84 seconds |
Started | Aug 17 04:25:38 PM PDT 24 |
Finished | Aug 17 04:26:00 PM PDT 24 |
Peak memory | 146156 kb |
Host | smart-6d05347d-c4d2-4dec-bd32-a024cef4ca8e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=361006197 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 291.prim_prince_test.361006197 |
Directory | /workspace/291.prim_prince_test/latest |
Test location | /workspace/coverage/default/292.prim_prince_test.974290888 |
Short name | T93 |
Test name | |
Test status | |
Simulation time | 3613978257 ps |
CPU time | 61.13 seconds |
Started | Aug 17 04:23:52 PM PDT 24 |
Finished | Aug 17 04:25:07 PM PDT 24 |
Peak memory | 146596 kb |
Host | smart-64272ae4-7136-427e-a845-5fc5d0418406 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=974290888 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 292.prim_prince_test.974290888 |
Directory | /workspace/292.prim_prince_test/latest |
Test location | /workspace/coverage/default/293.prim_prince_test.993288163 |
Short name | T378 |
Test name | |
Test status | |
Simulation time | 2497874084 ps |
CPU time | 41.96 seconds |
Started | Aug 17 04:26:08 PM PDT 24 |
Finished | Aug 17 04:27:00 PM PDT 24 |
Peak memory | 143020 kb |
Host | smart-58e68f90-9adb-4a86-91a8-9f6b2a3d355c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=993288163 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 293.prim_prince_test.993288163 |
Directory | /workspace/293.prim_prince_test/latest |
Test location | /workspace/coverage/default/294.prim_prince_test.1023199437 |
Short name | T258 |
Test name | |
Test status | |
Simulation time | 1182621483 ps |
CPU time | 20.29 seconds |
Started | Aug 17 04:24:34 PM PDT 24 |
Finished | Aug 17 04:24:59 PM PDT 24 |
Peak memory | 146836 kb |
Host | smart-f1f566db-6677-496a-8f70-5a1c50469555 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1023199437 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 294.prim_prince_test.1023199437 |
Directory | /workspace/294.prim_prince_test/latest |
Test location | /workspace/coverage/default/295.prim_prince_test.1890249343 |
Short name | T361 |
Test name | |
Test status | |
Simulation time | 3142909586 ps |
CPU time | 52.68 seconds |
Started | Aug 17 04:23:13 PM PDT 24 |
Finished | Aug 17 04:24:17 PM PDT 24 |
Peak memory | 146568 kb |
Host | smart-b604b887-905d-4347-879c-81b0d155ec09 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1890249343 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 295.prim_prince_test.1890249343 |
Directory | /workspace/295.prim_prince_test/latest |
Test location | /workspace/coverage/default/296.prim_prince_test.1134922779 |
Short name | T213 |
Test name | |
Test status | |
Simulation time | 3719418420 ps |
CPU time | 60.54 seconds |
Started | Aug 17 04:25:38 PM PDT 24 |
Finished | Aug 17 04:26:50 PM PDT 24 |
Peak memory | 146212 kb |
Host | smart-968ee453-e5cc-4442-8ac8-6976c3f52c8e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1134922779 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 296.prim_prince_test.1134922779 |
Directory | /workspace/296.prim_prince_test/latest |
Test location | /workspace/coverage/default/297.prim_prince_test.2959509026 |
Short name | T368 |
Test name | |
Test status | |
Simulation time | 1277593856 ps |
CPU time | 21.8 seconds |
Started | Aug 17 04:23:15 PM PDT 24 |
Finished | Aug 17 04:23:42 PM PDT 24 |
Peak memory | 146508 kb |
Host | smart-a61da920-4de4-4e69-bdb3-5a9cf873f2f7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2959509026 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 297.prim_prince_test.2959509026 |
Directory | /workspace/297.prim_prince_test/latest |
Test location | /workspace/coverage/default/298.prim_prince_test.4175450452 |
Short name | T20 |
Test name | |
Test status | |
Simulation time | 3430380900 ps |
CPU time | 55.96 seconds |
Started | Aug 17 04:22:31 PM PDT 24 |
Finished | Aug 17 04:23:37 PM PDT 24 |
Peak memory | 146500 kb |
Host | smart-421646fb-1d36-4a31-84b4-45c3a2fe843a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4175450452 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 298.prim_prince_test.4175450452 |
Directory | /workspace/298.prim_prince_test/latest |
Test location | /workspace/coverage/default/299.prim_prince_test.2777292741 |
Short name | T456 |
Test name | |
Test status | |
Simulation time | 3040972754 ps |
CPU time | 49.71 seconds |
Started | Aug 17 04:24:54 PM PDT 24 |
Finished | Aug 17 04:25:53 PM PDT 24 |
Peak memory | 145248 kb |
Host | smart-5f0d80c7-c3ed-4996-b0ef-5de3563fb2e3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2777292741 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 299.prim_prince_test.2777292741 |
Directory | /workspace/299.prim_prince_test/latest |
Test location | /workspace/coverage/default/3.prim_prince_test.3399810060 |
Short name | T362 |
Test name | |
Test status | |
Simulation time | 2981459920 ps |
CPU time | 49.35 seconds |
Started | Aug 17 04:20:22 PM PDT 24 |
Finished | Aug 17 04:21:22 PM PDT 24 |
Peak memory | 146304 kb |
Host | smart-b54e249e-8b22-4862-a58c-07b4ee37f97a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3399810060 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_prince_test.3399810060 |
Directory | /workspace/3.prim_prince_test/latest |
Test location | /workspace/coverage/default/30.prim_prince_test.2091886126 |
Short name | T425 |
Test name | |
Test status | |
Simulation time | 1306175237 ps |
CPU time | 22.08 seconds |
Started | Aug 17 04:21:41 PM PDT 24 |
Finished | Aug 17 04:22:08 PM PDT 24 |
Peak memory | 146520 kb |
Host | smart-1c9a14b8-f5fc-40bf-b291-bc1e12eb0b79 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2091886126 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_prince_test.2091886126 |
Directory | /workspace/30.prim_prince_test/latest |
Test location | /workspace/coverage/default/300.prim_prince_test.1965642214 |
Short name | T64 |
Test name | |
Test status | |
Simulation time | 3350454754 ps |
CPU time | 56.87 seconds |
Started | Aug 17 04:22:27 PM PDT 24 |
Finished | Aug 17 04:23:37 PM PDT 24 |
Peak memory | 146644 kb |
Host | smart-51781006-85b0-42b4-8b9e-c19de0e49902 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1965642214 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 300.prim_prince_test.1965642214 |
Directory | /workspace/300.prim_prince_test/latest |
Test location | /workspace/coverage/default/301.prim_prince_test.133571182 |
Short name | T405 |
Test name | |
Test status | |
Simulation time | 1346308904 ps |
CPU time | 21.68 seconds |
Started | Aug 17 04:25:35 PM PDT 24 |
Finished | Aug 17 04:26:01 PM PDT 24 |
Peak memory | 146112 kb |
Host | smart-4b8ca1f6-2619-437d-9475-6a8d02f600e0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=133571182 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 301.prim_prince_test.133571182 |
Directory | /workspace/301.prim_prince_test/latest |
Test location | /workspace/coverage/default/302.prim_prince_test.1506415873 |
Short name | T225 |
Test name | |
Test status | |
Simulation time | 850829222 ps |
CPU time | 14.42 seconds |
Started | Aug 17 04:22:51 PM PDT 24 |
Finished | Aug 17 04:23:08 PM PDT 24 |
Peak memory | 146580 kb |
Host | smart-8a77cf0f-9525-4ba2-9e9f-1946f98d4f3e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1506415873 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 302.prim_prince_test.1506415873 |
Directory | /workspace/302.prim_prince_test/latest |
Test location | /workspace/coverage/default/303.prim_prince_test.3656822929 |
Short name | T429 |
Test name | |
Test status | |
Simulation time | 3667042870 ps |
CPU time | 59.4 seconds |
Started | Aug 17 04:24:54 PM PDT 24 |
Finished | Aug 17 04:26:05 PM PDT 24 |
Peak memory | 145456 kb |
Host | smart-66bce634-3e4e-44dd-bd5e-e1ce276f74fd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3656822929 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 303.prim_prince_test.3656822929 |
Directory | /workspace/303.prim_prince_test/latest |
Test location | /workspace/coverage/default/304.prim_prince_test.2973962698 |
Short name | T84 |
Test name | |
Test status | |
Simulation time | 2075546914 ps |
CPU time | 35.08 seconds |
Started | Aug 17 04:25:07 PM PDT 24 |
Finished | Aug 17 04:25:50 PM PDT 24 |
Peak memory | 146472 kb |
Host | smart-30249904-0c52-40fa-8106-3d91c285426a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2973962698 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 304.prim_prince_test.2973962698 |
Directory | /workspace/304.prim_prince_test/latest |
Test location | /workspace/coverage/default/305.prim_prince_test.2132656166 |
Short name | T135 |
Test name | |
Test status | |
Simulation time | 1028632511 ps |
CPU time | 16.64 seconds |
Started | Aug 17 04:25:35 PM PDT 24 |
Finished | Aug 17 04:25:55 PM PDT 24 |
Peak memory | 146044 kb |
Host | smart-829aacd1-9b49-45fe-9160-8b5cc0c34fda |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2132656166 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 305.prim_prince_test.2132656166 |
Directory | /workspace/305.prim_prince_test/latest |
Test location | /workspace/coverage/default/306.prim_prince_test.3040522260 |
Short name | T357 |
Test name | |
Test status | |
Simulation time | 990065113 ps |
CPU time | 16.01 seconds |
Started | Aug 17 04:25:35 PM PDT 24 |
Finished | Aug 17 04:25:54 PM PDT 24 |
Peak memory | 146044 kb |
Host | smart-18d7a064-1c12-4c8d-b93a-141ee655386e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3040522260 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 306.prim_prince_test.3040522260 |
Directory | /workspace/306.prim_prince_test/latest |
Test location | /workspace/coverage/default/307.prim_prince_test.596058122 |
Short name | T236 |
Test name | |
Test status | |
Simulation time | 2890638864 ps |
CPU time | 49.14 seconds |
Started | Aug 17 04:26:08 PM PDT 24 |
Finished | Aug 17 04:27:08 PM PDT 24 |
Peak memory | 143316 kb |
Host | smart-b704f934-58a0-4149-9798-79cd90ea052b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=596058122 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 307.prim_prince_test.596058122 |
Directory | /workspace/307.prim_prince_test/latest |
Test location | /workspace/coverage/default/308.prim_prince_test.659214909 |
Short name | T337 |
Test name | |
Test status | |
Simulation time | 1984917802 ps |
CPU time | 32.16 seconds |
Started | Aug 17 04:26:04 PM PDT 24 |
Finished | Aug 17 04:26:42 PM PDT 24 |
Peak memory | 146292 kb |
Host | smart-8fcfdd05-8298-4a19-bccb-b8f3a69d0688 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=659214909 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 308.prim_prince_test.659214909 |
Directory | /workspace/308.prim_prince_test/latest |
Test location | /workspace/coverage/default/309.prim_prince_test.3718012126 |
Short name | T218 |
Test name | |
Test status | |
Simulation time | 2707435650 ps |
CPU time | 45.87 seconds |
Started | Aug 17 04:22:35 PM PDT 24 |
Finished | Aug 17 04:23:31 PM PDT 24 |
Peak memory | 146648 kb |
Host | smart-bd78b1fc-65ef-413c-ae3a-d8faddfbef8d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3718012126 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 309.prim_prince_test.3718012126 |
Directory | /workspace/309.prim_prince_test/latest |
Test location | /workspace/coverage/default/31.prim_prince_test.1476851368 |
Short name | T286 |
Test name | |
Test status | |
Simulation time | 2484586834 ps |
CPU time | 39.86 seconds |
Started | Aug 17 04:20:26 PM PDT 24 |
Finished | Aug 17 04:21:13 PM PDT 24 |
Peak memory | 146212 kb |
Host | smart-22782b97-6cdc-4b5b-a686-97607d2fefd0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1476851368 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_prince_test.1476851368 |
Directory | /workspace/31.prim_prince_test/latest |
Test location | /workspace/coverage/default/310.prim_prince_test.2097942136 |
Short name | T380 |
Test name | |
Test status | |
Simulation time | 891401705 ps |
CPU time | 14.51 seconds |
Started | Aug 17 04:26:01 PM PDT 24 |
Finished | Aug 17 04:26:18 PM PDT 24 |
Peak memory | 146208 kb |
Host | smart-6ea99f1a-cda1-4020-9155-bfcc3c219305 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2097942136 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 310.prim_prince_test.2097942136 |
Directory | /workspace/310.prim_prince_test/latest |
Test location | /workspace/coverage/default/311.prim_prince_test.433293807 |
Short name | T194 |
Test name | |
Test status | |
Simulation time | 2086237016 ps |
CPU time | 35.77 seconds |
Started | Aug 17 04:24:13 PM PDT 24 |
Finished | Aug 17 04:24:57 PM PDT 24 |
Peak memory | 146564 kb |
Host | smart-2b8d2289-ea8d-4be9-91b5-7304033d2ba6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=433293807 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 311.prim_prince_test.433293807 |
Directory | /workspace/311.prim_prince_test/latest |
Test location | /workspace/coverage/default/312.prim_prince_test.1289319258 |
Short name | T312 |
Test name | |
Test status | |
Simulation time | 2870774011 ps |
CPU time | 46.57 seconds |
Started | Aug 17 04:25:47 PM PDT 24 |
Finished | Aug 17 04:26:43 PM PDT 24 |
Peak memory | 144540 kb |
Host | smart-d3a357e3-97f3-47af-8cd4-8e1591773425 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1289319258 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 312.prim_prince_test.1289319258 |
Directory | /workspace/312.prim_prince_test/latest |
Test location | /workspace/coverage/default/313.prim_prince_test.338518170 |
Short name | T153 |
Test name | |
Test status | |
Simulation time | 3214137035 ps |
CPU time | 54.35 seconds |
Started | Aug 17 04:22:31 PM PDT 24 |
Finished | Aug 17 04:23:37 PM PDT 24 |
Peak memory | 146648 kb |
Host | smart-cdb634b8-76d1-45c7-aad9-f25ca6e0ef1e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=338518170 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 313.prim_prince_test.338518170 |
Directory | /workspace/313.prim_prince_test/latest |
Test location | /workspace/coverage/default/314.prim_prince_test.2140498738 |
Short name | T63 |
Test name | |
Test status | |
Simulation time | 904166832 ps |
CPU time | 15.02 seconds |
Started | Aug 17 04:24:14 PM PDT 24 |
Finished | Aug 17 04:24:32 PM PDT 24 |
Peak memory | 146508 kb |
Host | smart-c03a3cd6-72c2-4013-a0dd-e23470c91925 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2140498738 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 314.prim_prince_test.2140498738 |
Directory | /workspace/314.prim_prince_test/latest |
Test location | /workspace/coverage/default/315.prim_prince_test.2514006626 |
Short name | T295 |
Test name | |
Test status | |
Simulation time | 3639980436 ps |
CPU time | 61.11 seconds |
Started | Aug 17 04:24:11 PM PDT 24 |
Finished | Aug 17 04:25:26 PM PDT 24 |
Peak memory | 146644 kb |
Host | smart-748474cd-292c-4382-894d-95a210a9a021 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2514006626 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 315.prim_prince_test.2514006626 |
Directory | /workspace/315.prim_prince_test/latest |
Test location | /workspace/coverage/default/316.prim_prince_test.3245345930 |
Short name | T173 |
Test name | |
Test status | |
Simulation time | 2466949217 ps |
CPU time | 40.59 seconds |
Started | Aug 17 04:26:01 PM PDT 24 |
Finished | Aug 17 04:26:50 PM PDT 24 |
Peak memory | 146496 kb |
Host | smart-21737414-8370-4b30-a870-e268317e9506 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3245345930 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 316.prim_prince_test.3245345930 |
Directory | /workspace/316.prim_prince_test/latest |
Test location | /workspace/coverage/default/317.prim_prince_test.4084696635 |
Short name | T147 |
Test name | |
Test status | |
Simulation time | 1010607299 ps |
CPU time | 16.46 seconds |
Started | Aug 17 04:25:14 PM PDT 24 |
Finished | Aug 17 04:25:34 PM PDT 24 |
Peak memory | 144832 kb |
Host | smart-b55a978d-8881-40b2-b73a-46728cea6341 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4084696635 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 317.prim_prince_test.4084696635 |
Directory | /workspace/317.prim_prince_test/latest |
Test location | /workspace/coverage/default/318.prim_prince_test.2889454992 |
Short name | T401 |
Test name | |
Test status | |
Simulation time | 1891229146 ps |
CPU time | 32.81 seconds |
Started | Aug 17 04:22:39 PM PDT 24 |
Finished | Aug 17 04:23:20 PM PDT 24 |
Peak memory | 146568 kb |
Host | smart-5fcae0f7-913c-4f9c-83fd-359826494ce6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2889454992 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 318.prim_prince_test.2889454992 |
Directory | /workspace/318.prim_prince_test/latest |
Test location | /workspace/coverage/default/319.prim_prince_test.1786284352 |
Short name | T97 |
Test name | |
Test status | |
Simulation time | 2354211423 ps |
CPU time | 38.93 seconds |
Started | Aug 17 04:25:02 PM PDT 24 |
Finished | Aug 17 04:25:49 PM PDT 24 |
Peak memory | 146188 kb |
Host | smart-fa008e2b-eafd-4d43-af39-e5fb748974a4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1786284352 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 319.prim_prince_test.1786284352 |
Directory | /workspace/319.prim_prince_test/latest |
Test location | /workspace/coverage/default/32.prim_prince_test.493125990 |
Short name | T284 |
Test name | |
Test status | |
Simulation time | 967538386 ps |
CPU time | 15.92 seconds |
Started | Aug 17 04:20:25 PM PDT 24 |
Finished | Aug 17 04:20:45 PM PDT 24 |
Peak memory | 146240 kb |
Host | smart-7a214ff1-4aa3-4d3a-9f69-4d3860a5aa83 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=493125990 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_prince_test.493125990 |
Directory | /workspace/32.prim_prince_test/latest |
Test location | /workspace/coverage/default/320.prim_prince_test.2501738224 |
Short name | T211 |
Test name | |
Test status | |
Simulation time | 2114235898 ps |
CPU time | 35.98 seconds |
Started | Aug 17 04:22:45 PM PDT 24 |
Finished | Aug 17 04:23:29 PM PDT 24 |
Peak memory | 146564 kb |
Host | smart-9b0617ea-4101-4eee-9931-db3e989e086e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2501738224 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 320.prim_prince_test.2501738224 |
Directory | /workspace/320.prim_prince_test/latest |
Test location | /workspace/coverage/default/321.prim_prince_test.1710459323 |
Short name | T386 |
Test name | |
Test status | |
Simulation time | 3291866764 ps |
CPU time | 53.45 seconds |
Started | Aug 17 04:25:22 PM PDT 24 |
Finished | Aug 17 04:26:27 PM PDT 24 |
Peak memory | 146108 kb |
Host | smart-63542e19-5865-4457-9b92-a02a6a547823 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1710459323 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 321.prim_prince_test.1710459323 |
Directory | /workspace/321.prim_prince_test/latest |
Test location | /workspace/coverage/default/322.prim_prince_test.3700863272 |
Short name | T498 |
Test name | |
Test status | |
Simulation time | 2032166355 ps |
CPU time | 33.09 seconds |
Started | Aug 17 04:25:34 PM PDT 24 |
Finished | Aug 17 04:26:14 PM PDT 24 |
Peak memory | 146148 kb |
Host | smart-658d6129-33f8-404f-b5f9-d71fa1544c42 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3700863272 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 322.prim_prince_test.3700863272 |
Directory | /workspace/322.prim_prince_test/latest |
Test location | /workspace/coverage/default/323.prim_prince_test.436033103 |
Short name | T50 |
Test name | |
Test status | |
Simulation time | 3731431341 ps |
CPU time | 59.4 seconds |
Started | Aug 17 04:25:34 PM PDT 24 |
Finished | Aug 17 04:26:44 PM PDT 24 |
Peak memory | 146036 kb |
Host | smart-1a2258e8-da59-4141-a8e2-fbb22ff6d707 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=436033103 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 323.prim_prince_test.436033103 |
Directory | /workspace/323.prim_prince_test/latest |
Test location | /workspace/coverage/default/324.prim_prince_test.3413280067 |
Short name | T4 |
Test name | |
Test status | |
Simulation time | 3331914502 ps |
CPU time | 53.48 seconds |
Started | Aug 17 04:25:34 PM PDT 24 |
Finished | Aug 17 04:26:38 PM PDT 24 |
Peak memory | 146212 kb |
Host | smart-4788aa36-1c2c-4d8e-b08c-a2d94d1b87af |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3413280067 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 324.prim_prince_test.3413280067 |
Directory | /workspace/324.prim_prince_test/latest |
Test location | /workspace/coverage/default/325.prim_prince_test.2512346485 |
Short name | T7 |
Test name | |
Test status | |
Simulation time | 785466681 ps |
CPU time | 13.07 seconds |
Started | Aug 17 04:24:52 PM PDT 24 |
Finished | Aug 17 04:25:08 PM PDT 24 |
Peak memory | 145620 kb |
Host | smart-29cd7add-a9fc-43be-9570-c958630c8148 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2512346485 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 325.prim_prince_test.2512346485 |
Directory | /workspace/325.prim_prince_test/latest |
Test location | /workspace/coverage/default/326.prim_prince_test.2342752375 |
Short name | T474 |
Test name | |
Test status | |
Simulation time | 1528636253 ps |
CPU time | 24 seconds |
Started | Aug 17 04:25:24 PM PDT 24 |
Finished | Aug 17 04:25:53 PM PDT 24 |
Peak memory | 146092 kb |
Host | smart-561f7af9-c53d-46bf-a73e-d9f6153e65c4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2342752375 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 326.prim_prince_test.2342752375 |
Directory | /workspace/326.prim_prince_test/latest |
Test location | /workspace/coverage/default/327.prim_prince_test.2179032105 |
Short name | T329 |
Test name | |
Test status | |
Simulation time | 2754258716 ps |
CPU time | 43.54 seconds |
Started | Aug 17 04:25:34 PM PDT 24 |
Finished | Aug 17 04:26:25 PM PDT 24 |
Peak memory | 146212 kb |
Host | smart-4f9628f6-5dd4-4989-ba26-9a7d9fee1385 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2179032105 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 327.prim_prince_test.2179032105 |
Directory | /workspace/327.prim_prince_test/latest |
Test location | /workspace/coverage/default/328.prim_prince_test.2082800291 |
Short name | T323 |
Test name | |
Test status | |
Simulation time | 2019190958 ps |
CPU time | 34.67 seconds |
Started | Aug 17 04:25:37 PM PDT 24 |
Finished | Aug 17 04:26:21 PM PDT 24 |
Peak memory | 145716 kb |
Host | smart-cc98e005-517e-4687-8ada-5d603d9d0470 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2082800291 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 328.prim_prince_test.2082800291 |
Directory | /workspace/328.prim_prince_test/latest |
Test location | /workspace/coverage/default/329.prim_prince_test.4163777172 |
Short name | T90 |
Test name | |
Test status | |
Simulation time | 2618936794 ps |
CPU time | 45.32 seconds |
Started | Aug 17 04:26:00 PM PDT 24 |
Finished | Aug 17 04:26:56 PM PDT 24 |
Peak memory | 146460 kb |
Host | smart-37c02e8d-a93f-4d28-9720-2361bf195628 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4163777172 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 329.prim_prince_test.4163777172 |
Directory | /workspace/329.prim_prince_test/latest |
Test location | /workspace/coverage/default/33.prim_prince_test.4094014207 |
Short name | T291 |
Test name | |
Test status | |
Simulation time | 1608068740 ps |
CPU time | 26.42 seconds |
Started | Aug 17 04:20:22 PM PDT 24 |
Finished | Aug 17 04:20:54 PM PDT 24 |
Peak memory | 146248 kb |
Host | smart-4721bb03-518d-45e7-8671-32a8e21ada5a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4094014207 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_prince_test.4094014207 |
Directory | /workspace/33.prim_prince_test/latest |
Test location | /workspace/coverage/default/330.prim_prince_test.319436513 |
Short name | T29 |
Test name | |
Test status | |
Simulation time | 2458635978 ps |
CPU time | 40.17 seconds |
Started | Aug 17 04:24:56 PM PDT 24 |
Finished | Aug 17 04:25:44 PM PDT 24 |
Peak memory | 145992 kb |
Host | smart-a1832071-dbc2-4009-a79f-a1173923d87b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=319436513 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 330.prim_prince_test.319436513 |
Directory | /workspace/330.prim_prince_test/latest |
Test location | /workspace/coverage/default/331.prim_prince_test.283457511 |
Short name | T1 |
Test name | |
Test status | |
Simulation time | 757467938 ps |
CPU time | 13.2 seconds |
Started | Aug 17 04:22:47 PM PDT 24 |
Finished | Aug 17 04:23:03 PM PDT 24 |
Peak memory | 146564 kb |
Host | smart-855cdaab-b937-4641-8c6d-353d9d85ce94 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=283457511 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 331.prim_prince_test.283457511 |
Directory | /workspace/331.prim_prince_test/latest |
Test location | /workspace/coverage/default/332.prim_prince_test.668399700 |
Short name | T428 |
Test name | |
Test status | |
Simulation time | 2763059535 ps |
CPU time | 45.75 seconds |
Started | Aug 17 04:23:16 PM PDT 24 |
Finished | Aug 17 04:24:12 PM PDT 24 |
Peak memory | 146584 kb |
Host | smart-c09bb606-71cc-4925-a403-2e9b5b1228de |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=668399700 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 332.prim_prince_test.668399700 |
Directory | /workspace/332.prim_prince_test/latest |
Test location | /workspace/coverage/default/333.prim_prince_test.30345638 |
Short name | T484 |
Test name | |
Test status | |
Simulation time | 3102927573 ps |
CPU time | 50.68 seconds |
Started | Aug 17 04:25:45 PM PDT 24 |
Finished | Aug 17 04:26:46 PM PDT 24 |
Peak memory | 146360 kb |
Host | smart-ecb90411-7374-462d-b670-46fc9dcd3eb8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=30345638 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 333.prim_prince_test.30345638 |
Directory | /workspace/333.prim_prince_test/latest |
Test location | /workspace/coverage/default/334.prim_prince_test.3235836282 |
Short name | T371 |
Test name | |
Test status | |
Simulation time | 1388457294 ps |
CPU time | 24.14 seconds |
Started | Aug 17 04:22:44 PM PDT 24 |
Finished | Aug 17 04:23:14 PM PDT 24 |
Peak memory | 146568 kb |
Host | smart-97731963-885f-4380-9fce-81f0e128c909 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3235836282 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 334.prim_prince_test.3235836282 |
Directory | /workspace/334.prim_prince_test/latest |
Test location | /workspace/coverage/default/335.prim_prince_test.4252567496 |
Short name | T443 |
Test name | |
Test status | |
Simulation time | 1339649055 ps |
CPU time | 23.69 seconds |
Started | Aug 17 04:22:46 PM PDT 24 |
Finished | Aug 17 04:23:16 PM PDT 24 |
Peak memory | 146560 kb |
Host | smart-0dd22c10-53c8-4884-9583-a87c791337aa |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4252567496 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 335.prim_prince_test.4252567496 |
Directory | /workspace/335.prim_prince_test/latest |
Test location | /workspace/coverage/default/336.prim_prince_test.504866411 |
Short name | T150 |
Test name | |
Test status | |
Simulation time | 3512629219 ps |
CPU time | 59.07 seconds |
Started | Aug 17 04:22:45 PM PDT 24 |
Finished | Aug 17 04:23:58 PM PDT 24 |
Peak memory | 146648 kb |
Host | smart-fdd12add-afea-4c4d-a9a4-20b9c4425c9d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=504866411 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 336.prim_prince_test.504866411 |
Directory | /workspace/336.prim_prince_test/latest |
Test location | /workspace/coverage/default/337.prim_prince_test.4287386662 |
Short name | T189 |
Test name | |
Test status | |
Simulation time | 1140223988 ps |
CPU time | 19.13 seconds |
Started | Aug 17 04:22:46 PM PDT 24 |
Finished | Aug 17 04:23:10 PM PDT 24 |
Peak memory | 146520 kb |
Host | smart-c463281e-7aad-4f2e-9511-aba5f4a8c28d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4287386662 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 337.prim_prince_test.4287386662 |
Directory | /workspace/337.prim_prince_test/latest |
Test location | /workspace/coverage/default/338.prim_prince_test.320868332 |
Short name | T276 |
Test name | |
Test status | |
Simulation time | 758085698 ps |
CPU time | 12.15 seconds |
Started | Aug 17 04:25:33 PM PDT 24 |
Finished | Aug 17 04:25:47 PM PDT 24 |
Peak memory | 146280 kb |
Host | smart-c284b78b-f336-4cf4-ad96-25b6fd29b501 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=320868332 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 338.prim_prince_test.320868332 |
Directory | /workspace/338.prim_prince_test/latest |
Test location | /workspace/coverage/default/339.prim_prince_test.2275108303 |
Short name | T318 |
Test name | |
Test status | |
Simulation time | 1749258968 ps |
CPU time | 29.13 seconds |
Started | Aug 17 04:25:46 PM PDT 24 |
Finished | Aug 17 04:26:21 PM PDT 24 |
Peak memory | 146268 kb |
Host | smart-a6467a39-de80-4fac-8487-e06667871e0b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2275108303 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 339.prim_prince_test.2275108303 |
Directory | /workspace/339.prim_prince_test/latest |
Test location | /workspace/coverage/default/34.prim_prince_test.371412709 |
Short name | T457 |
Test name | |
Test status | |
Simulation time | 3188050952 ps |
CPU time | 52.53 seconds |
Started | Aug 17 04:21:28 PM PDT 24 |
Finished | Aug 17 04:22:30 PM PDT 24 |
Peak memory | 144900 kb |
Host | smart-4a997985-5893-4f9e-aab5-58d3826c603b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=371412709 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_prince_test.371412709 |
Directory | /workspace/34.prim_prince_test/latest |
Test location | /workspace/coverage/default/340.prim_prince_test.2568224852 |
Short name | T217 |
Test name | |
Test status | |
Simulation time | 1934347718 ps |
CPU time | 31.96 seconds |
Started | Aug 17 04:25:46 PM PDT 24 |
Finished | Aug 17 04:26:24 PM PDT 24 |
Peak memory | 146284 kb |
Host | smart-f43fc904-ac92-40ff-ade5-3953f2095050 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2568224852 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 340.prim_prince_test.2568224852 |
Directory | /workspace/340.prim_prince_test/latest |
Test location | /workspace/coverage/default/341.prim_prince_test.2049496164 |
Short name | T292 |
Test name | |
Test status | |
Simulation time | 2353898803 ps |
CPU time | 39.77 seconds |
Started | Aug 17 04:23:16 PM PDT 24 |
Finished | Aug 17 04:24:04 PM PDT 24 |
Peak memory | 146632 kb |
Host | smart-546e3c85-f53d-4279-9a22-d125077a09e5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2049496164 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 341.prim_prince_test.2049496164 |
Directory | /workspace/341.prim_prince_test/latest |
Test location | /workspace/coverage/default/342.prim_prince_test.3052970169 |
Short name | T492 |
Test name | |
Test status | |
Simulation time | 2296978421 ps |
CPU time | 37.68 seconds |
Started | Aug 17 04:25:46 PM PDT 24 |
Finished | Aug 17 04:26:31 PM PDT 24 |
Peak memory | 146152 kb |
Host | smart-8c12a4d8-6ba0-4035-9dfc-89de2298eb76 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3052970169 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 342.prim_prince_test.3052970169 |
Directory | /workspace/342.prim_prince_test/latest |
Test location | /workspace/coverage/default/343.prim_prince_test.1533622346 |
Short name | T49 |
Test name | |
Test status | |
Simulation time | 2193912739 ps |
CPU time | 38.31 seconds |
Started | Aug 17 04:22:47 PM PDT 24 |
Finished | Aug 17 04:23:35 PM PDT 24 |
Peak memory | 146624 kb |
Host | smart-cc589338-e359-4822-8ab3-1f3b2e0d29cb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1533622346 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 343.prim_prince_test.1533622346 |
Directory | /workspace/343.prim_prince_test/latest |
Test location | /workspace/coverage/default/344.prim_prince_test.3574192181 |
Short name | T19 |
Test name | |
Test status | |
Simulation time | 1653454238 ps |
CPU time | 28.68 seconds |
Started | Aug 17 04:23:04 PM PDT 24 |
Finished | Aug 17 04:23:39 PM PDT 24 |
Peak memory | 146320 kb |
Host | smart-0330a165-d967-4ba9-b2cc-44aba3a76956 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3574192181 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 344.prim_prince_test.3574192181 |
Directory | /workspace/344.prim_prince_test/latest |
Test location | /workspace/coverage/default/345.prim_prince_test.2477615095 |
Short name | T367 |
Test name | |
Test status | |
Simulation time | 2737069261 ps |
CPU time | 44.71 seconds |
Started | Aug 17 04:25:46 PM PDT 24 |
Finished | Aug 17 04:26:39 PM PDT 24 |
Peak memory | 146140 kb |
Host | smart-bd401577-62aa-4c0a-8c23-f59f74c9179d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2477615095 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 345.prim_prince_test.2477615095 |
Directory | /workspace/345.prim_prince_test/latest |
Test location | /workspace/coverage/default/346.prim_prince_test.1880855489 |
Short name | T39 |
Test name | |
Test status | |
Simulation time | 1648422680 ps |
CPU time | 27.98 seconds |
Started | Aug 17 04:23:48 PM PDT 24 |
Finished | Aug 17 04:24:21 PM PDT 24 |
Peak memory | 146504 kb |
Host | smart-1819f2fc-de33-4270-bc1c-74b560a280c8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1880855489 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 346.prim_prince_test.1880855489 |
Directory | /workspace/346.prim_prince_test/latest |
Test location | /workspace/coverage/default/347.prim_prince_test.430161231 |
Short name | T27 |
Test name | |
Test status | |
Simulation time | 1367120544 ps |
CPU time | 23.07 seconds |
Started | Aug 17 04:25:45 PM PDT 24 |
Finished | Aug 17 04:26:13 PM PDT 24 |
Peak memory | 146228 kb |
Host | smart-13c0f6a0-8433-4df2-8dcc-960ef046b422 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=430161231 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 347.prim_prince_test.430161231 |
Directory | /workspace/347.prim_prince_test/latest |
Test location | /workspace/coverage/default/348.prim_prince_test.2289997068 |
Short name | T134 |
Test name | |
Test status | |
Simulation time | 1516385398 ps |
CPU time | 25.66 seconds |
Started | Aug 17 04:25:11 PM PDT 24 |
Finished | Aug 17 04:25:43 PM PDT 24 |
Peak memory | 146392 kb |
Host | smart-46ee1358-f21a-4f19-9e31-f0eeb7db79fc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2289997068 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 348.prim_prince_test.2289997068 |
Directory | /workspace/348.prim_prince_test/latest |
Test location | /workspace/coverage/default/349.prim_prince_test.4188022365 |
Short name | T454 |
Test name | |
Test status | |
Simulation time | 824128397 ps |
CPU time | 13.54 seconds |
Started | Aug 17 04:25:34 PM PDT 24 |
Finished | Aug 17 04:25:51 PM PDT 24 |
Peak memory | 145552 kb |
Host | smart-6e82624c-4371-4cf4-9c71-4ab298c57bed |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4188022365 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 349.prim_prince_test.4188022365 |
Directory | /workspace/349.prim_prince_test/latest |
Test location | /workspace/coverage/default/35.prim_prince_test.1560407414 |
Short name | T289 |
Test name | |
Test status | |
Simulation time | 3210509385 ps |
CPU time | 53.87 seconds |
Started | Aug 17 04:20:22 PM PDT 24 |
Finished | Aug 17 04:21:28 PM PDT 24 |
Peak memory | 146304 kb |
Host | smart-b2b9706e-7a90-4b6e-910f-7e45d21db029 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1560407414 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_prince_test.1560407414 |
Directory | /workspace/35.prim_prince_test/latest |
Test location | /workspace/coverage/default/350.prim_prince_test.1176046500 |
Short name | T469 |
Test name | |
Test status | |
Simulation time | 1482534816 ps |
CPU time | 25.09 seconds |
Started | Aug 17 04:22:58 PM PDT 24 |
Finished | Aug 17 04:23:28 PM PDT 24 |
Peak memory | 146320 kb |
Host | smart-5cc1b34e-ef1f-4403-a1c6-1237592783dd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1176046500 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 350.prim_prince_test.1176046500 |
Directory | /workspace/350.prim_prince_test/latest |
Test location | /workspace/coverage/default/351.prim_prince_test.502158797 |
Short name | T439 |
Test name | |
Test status | |
Simulation time | 1547885376 ps |
CPU time | 26.25 seconds |
Started | Aug 17 04:22:52 PM PDT 24 |
Finished | Aug 17 04:23:24 PM PDT 24 |
Peak memory | 146836 kb |
Host | smart-e00ee311-539a-4404-b80e-7b5ab78733a4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=502158797 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 351.prim_prince_test.502158797 |
Directory | /workspace/351.prim_prince_test/latest |
Test location | /workspace/coverage/default/352.prim_prince_test.1032571953 |
Short name | T407 |
Test name | |
Test status | |
Simulation time | 3282096974 ps |
CPU time | 52.45 seconds |
Started | Aug 17 04:25:43 PM PDT 24 |
Finished | Aug 17 04:26:45 PM PDT 24 |
Peak memory | 146216 kb |
Host | smart-921f9723-1179-4198-9290-17be15530f15 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1032571953 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 352.prim_prince_test.1032571953 |
Directory | /workspace/352.prim_prince_test/latest |
Test location | /workspace/coverage/default/353.prim_prince_test.1635954719 |
Short name | T336 |
Test name | |
Test status | |
Simulation time | 2456545134 ps |
CPU time | 40.47 seconds |
Started | Aug 17 04:25:12 PM PDT 24 |
Finished | Aug 17 04:26:01 PM PDT 24 |
Peak memory | 146312 kb |
Host | smart-12456cd0-5cf1-49ee-a2b5-6a1d2890c577 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1635954719 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 353.prim_prince_test.1635954719 |
Directory | /workspace/353.prim_prince_test/latest |
Test location | /workspace/coverage/default/354.prim_prince_test.1982112203 |
Short name | T470 |
Test name | |
Test status | |
Simulation time | 2434086370 ps |
CPU time | 39.17 seconds |
Started | Aug 17 04:25:03 PM PDT 24 |
Finished | Aug 17 04:25:49 PM PDT 24 |
Peak memory | 146204 kb |
Host | smart-51c533f1-5051-46f3-8b90-7d866a1b26e0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1982112203 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 354.prim_prince_test.1982112203 |
Directory | /workspace/354.prim_prince_test/latest |
Test location | /workspace/coverage/default/355.prim_prince_test.3936449182 |
Short name | T40 |
Test name | |
Test status | |
Simulation time | 2488980736 ps |
CPU time | 40.5 seconds |
Started | Aug 17 04:23:51 PM PDT 24 |
Finished | Aug 17 04:24:40 PM PDT 24 |
Peak memory | 146524 kb |
Host | smart-fd46cdd3-b4c2-4f11-b4fc-9ecf8a112c89 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3936449182 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 355.prim_prince_test.3936449182 |
Directory | /workspace/355.prim_prince_test/latest |
Test location | /workspace/coverage/default/356.prim_prince_test.688668015 |
Short name | T199 |
Test name | |
Test status | |
Simulation time | 3258116958 ps |
CPU time | 53.87 seconds |
Started | Aug 17 04:24:34 PM PDT 24 |
Finished | Aug 17 04:25:40 PM PDT 24 |
Peak memory | 146496 kb |
Host | smart-40b494b0-0551-47ba-8011-9b720b47da05 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=688668015 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 356.prim_prince_test.688668015 |
Directory | /workspace/356.prim_prince_test/latest |
Test location | /workspace/coverage/default/357.prim_prince_test.2365126440 |
Short name | T111 |
Test name | |
Test status | |
Simulation time | 3550779180 ps |
CPU time | 59.71 seconds |
Started | Aug 17 04:26:08 PM PDT 24 |
Finished | Aug 17 04:27:21 PM PDT 24 |
Peak memory | 143280 kb |
Host | smart-261ba3e6-9f83-4d6c-95ee-b7ad1e2d1775 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2365126440 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 357.prim_prince_test.2365126440 |
Directory | /workspace/357.prim_prince_test/latest |
Test location | /workspace/coverage/default/358.prim_prince_test.1269653340 |
Short name | T109 |
Test name | |
Test status | |
Simulation time | 1501860154 ps |
CPU time | 24.42 seconds |
Started | Aug 17 04:25:34 PM PDT 24 |
Finished | Aug 17 04:26:03 PM PDT 24 |
Peak memory | 145060 kb |
Host | smart-6088bedd-2bb0-4f3f-8be1-9ede90aa3df9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1269653340 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 358.prim_prince_test.1269653340 |
Directory | /workspace/358.prim_prince_test/latest |
Test location | /workspace/coverage/default/359.prim_prince_test.3163561992 |
Short name | T99 |
Test name | |
Test status | |
Simulation time | 1170205207 ps |
CPU time | 20.39 seconds |
Started | Aug 17 04:26:08 PM PDT 24 |
Finished | Aug 17 04:26:33 PM PDT 24 |
Peak memory | 143256 kb |
Host | smart-a1dfb1b4-aadd-43b5-84f1-33d410f52c14 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3163561992 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 359.prim_prince_test.3163561992 |
Directory | /workspace/359.prim_prince_test/latest |
Test location | /workspace/coverage/default/36.prim_prince_test.3436271604 |
Short name | T275 |
Test name | |
Test status | |
Simulation time | 3138013765 ps |
CPU time | 52.31 seconds |
Started | Aug 17 04:20:26 PM PDT 24 |
Finished | Aug 17 04:21:29 PM PDT 24 |
Peak memory | 145356 kb |
Host | smart-ab733b58-fc09-4b3a-a4c0-0341fdbd09f3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3436271604 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_prince_test.3436271604 |
Directory | /workspace/36.prim_prince_test/latest |
Test location | /workspace/coverage/default/360.prim_prince_test.701533275 |
Short name | T167 |
Test name | |
Test status | |
Simulation time | 1964170219 ps |
CPU time | 32.69 seconds |
Started | Aug 17 04:22:52 PM PDT 24 |
Finished | Aug 17 04:23:32 PM PDT 24 |
Peak memory | 146532 kb |
Host | smart-960c4c4b-6d96-456a-822d-f84f602e6510 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=701533275 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 360.prim_prince_test.701533275 |
Directory | /workspace/360.prim_prince_test/latest |
Test location | /workspace/coverage/default/361.prim_prince_test.193949404 |
Short name | T310 |
Test name | |
Test status | |
Simulation time | 1743727925 ps |
CPU time | 28.21 seconds |
Started | Aug 17 04:25:45 PM PDT 24 |
Finished | Aug 17 04:26:18 PM PDT 24 |
Peak memory | 146172 kb |
Host | smart-b5632c37-b3ff-4e8e-bd4f-01697cedf194 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=193949404 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 361.prim_prince_test.193949404 |
Directory | /workspace/361.prim_prince_test/latest |
Test location | /workspace/coverage/default/362.prim_prince_test.4092972522 |
Short name | T106 |
Test name | |
Test status | |
Simulation time | 2167867219 ps |
CPU time | 34.42 seconds |
Started | Aug 17 04:25:14 PM PDT 24 |
Finished | Aug 17 04:25:54 PM PDT 24 |
Peak memory | 144932 kb |
Host | smart-242afb0e-d067-4fef-a037-84ac86a5be5c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4092972522 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 362.prim_prince_test.4092972522 |
Directory | /workspace/362.prim_prince_test/latest |
Test location | /workspace/coverage/default/363.prim_prince_test.1578956090 |
Short name | T82 |
Test name | |
Test status | |
Simulation time | 934510605 ps |
CPU time | 15.4 seconds |
Started | Aug 17 04:26:04 PM PDT 24 |
Finished | Aug 17 04:26:22 PM PDT 24 |
Peak memory | 146284 kb |
Host | smart-25410303-01fe-46eb-b4ce-6d0da5dc3920 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1578956090 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 363.prim_prince_test.1578956090 |
Directory | /workspace/363.prim_prince_test/latest |
Test location | /workspace/coverage/default/364.prim_prince_test.3848585682 |
Short name | T78 |
Test name | |
Test status | |
Simulation time | 3061432627 ps |
CPU time | 49.95 seconds |
Started | Aug 17 04:25:48 PM PDT 24 |
Finished | Aug 17 04:26:48 PM PDT 24 |
Peak memory | 146296 kb |
Host | smart-7332e0fb-41f9-41ca-a899-a4ccba7353b0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3848585682 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 364.prim_prince_test.3848585682 |
Directory | /workspace/364.prim_prince_test/latest |
Test location | /workspace/coverage/default/365.prim_prince_test.121642738 |
Short name | T239 |
Test name | |
Test status | |
Simulation time | 3381400700 ps |
CPU time | 54.07 seconds |
Started | Aug 17 04:24:54 PM PDT 24 |
Finished | Aug 17 04:25:58 PM PDT 24 |
Peak memory | 145492 kb |
Host | smart-9ddda78b-1f0a-48f9-b1a5-becf1c3d4374 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=121642738 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 365.prim_prince_test.121642738 |
Directory | /workspace/365.prim_prince_test/latest |
Test location | /workspace/coverage/default/366.prim_prince_test.2613335993 |
Short name | T265 |
Test name | |
Test status | |
Simulation time | 1422518617 ps |
CPU time | 23.03 seconds |
Started | Aug 17 04:24:52 PM PDT 24 |
Finished | Aug 17 04:25:20 PM PDT 24 |
Peak memory | 145208 kb |
Host | smart-2c577675-c903-432c-9b6d-09dc814ef6c7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2613335993 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 366.prim_prince_test.2613335993 |
Directory | /workspace/366.prim_prince_test/latest |
Test location | /workspace/coverage/default/367.prim_prince_test.4152079893 |
Short name | T324 |
Test name | |
Test status | |
Simulation time | 3053777842 ps |
CPU time | 49.19 seconds |
Started | Aug 17 04:25:28 PM PDT 24 |
Finished | Aug 17 04:26:27 PM PDT 24 |
Peak memory | 146380 kb |
Host | smart-8f3e1034-5699-4633-8789-fa625973709a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4152079893 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 367.prim_prince_test.4152079893 |
Directory | /workspace/367.prim_prince_test/latest |
Test location | /workspace/coverage/default/368.prim_prince_test.1631541947 |
Short name | T123 |
Test name | |
Test status | |
Simulation time | 2286170153 ps |
CPU time | 37.29 seconds |
Started | Aug 17 04:24:54 PM PDT 24 |
Finished | Aug 17 04:25:38 PM PDT 24 |
Peak memory | 145180 kb |
Host | smart-bf7d6b78-56d4-414e-b182-ed0ba5f8795e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1631541947 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 368.prim_prince_test.1631541947 |
Directory | /workspace/368.prim_prince_test/latest |
Test location | /workspace/coverage/default/369.prim_prince_test.958757910 |
Short name | T384 |
Test name | |
Test status | |
Simulation time | 2582553971 ps |
CPU time | 42.1 seconds |
Started | Aug 17 04:24:52 PM PDT 24 |
Finished | Aug 17 04:25:42 PM PDT 24 |
Peak memory | 145044 kb |
Host | smart-42fd3691-2f30-4db8-9ab8-d87e62029d21 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=958757910 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 369.prim_prince_test.958757910 |
Directory | /workspace/369.prim_prince_test/latest |
Test location | /workspace/coverage/default/37.prim_prince_test.3781310098 |
Short name | T389 |
Test name | |
Test status | |
Simulation time | 2113088235 ps |
CPU time | 36.11 seconds |
Started | Aug 17 04:20:26 PM PDT 24 |
Finished | Aug 17 04:21:10 PM PDT 24 |
Peak memory | 146836 kb |
Host | smart-394048c6-1715-4893-a6f8-7989c60d9054 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3781310098 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_prince_test.3781310098 |
Directory | /workspace/37.prim_prince_test/latest |
Test location | /workspace/coverage/default/370.prim_prince_test.2282017433 |
Short name | T420 |
Test name | |
Test status | |
Simulation time | 1267093386 ps |
CPU time | 21.56 seconds |
Started | Aug 17 04:23:05 PM PDT 24 |
Finished | Aug 17 04:23:31 PM PDT 24 |
Peak memory | 146424 kb |
Host | smart-6f1fc33c-c8f4-48c4-aed8-617f15215ed4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2282017433 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 370.prim_prince_test.2282017433 |
Directory | /workspace/370.prim_prince_test/latest |
Test location | /workspace/coverage/default/371.prim_prince_test.437955015 |
Short name | T475 |
Test name | |
Test status | |
Simulation time | 3350429678 ps |
CPU time | 55.71 seconds |
Started | Aug 17 04:24:14 PM PDT 24 |
Finished | Aug 17 04:25:21 PM PDT 24 |
Peak memory | 146564 kb |
Host | smart-5eb3953c-fbd2-4196-8edd-cf8e3ed3f1b4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=437955015 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 371.prim_prince_test.437955015 |
Directory | /workspace/371.prim_prince_test/latest |
Test location | /workspace/coverage/default/372.prim_prince_test.801590068 |
Short name | T414 |
Test name | |
Test status | |
Simulation time | 1453176085 ps |
CPU time | 23.66 seconds |
Started | Aug 17 04:26:01 PM PDT 24 |
Finished | Aug 17 04:26:29 PM PDT 24 |
Peak memory | 146292 kb |
Host | smart-9c24a0b1-e307-48ae-91d0-a112e83d8033 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=801590068 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 372.prim_prince_test.801590068 |
Directory | /workspace/372.prim_prince_test/latest |
Test location | /workspace/coverage/default/373.prim_prince_test.559767224 |
Short name | T260 |
Test name | |
Test status | |
Simulation time | 2378611244 ps |
CPU time | 39.29 seconds |
Started | Aug 17 04:25:02 PM PDT 24 |
Finished | Aug 17 04:25:50 PM PDT 24 |
Peak memory | 146196 kb |
Host | smart-daaab1b0-411c-4b37-9cde-a6a0d4fc2839 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=559767224 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 373.prim_prince_test.559767224 |
Directory | /workspace/373.prim_prince_test/latest |
Test location | /workspace/coverage/default/374.prim_prince_test.3687815439 |
Short name | T322 |
Test name | |
Test status | |
Simulation time | 889158507 ps |
CPU time | 15.09 seconds |
Started | Aug 17 04:23:03 PM PDT 24 |
Finished | Aug 17 04:23:21 PM PDT 24 |
Peak memory | 146512 kb |
Host | smart-ee9ee737-1d49-45ce-aa87-8841e1de1593 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3687815439 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 374.prim_prince_test.3687815439 |
Directory | /workspace/374.prim_prince_test/latest |
Test location | /workspace/coverage/default/375.prim_prince_test.2477506249 |
Short name | T34 |
Test name | |
Test status | |
Simulation time | 2097866727 ps |
CPU time | 35.93 seconds |
Started | Aug 17 04:23:04 PM PDT 24 |
Finished | Aug 17 04:23:49 PM PDT 24 |
Peak memory | 146424 kb |
Host | smart-cdb82f81-2a8d-464f-baa8-9e0bb695e907 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2477506249 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 375.prim_prince_test.2477506249 |
Directory | /workspace/375.prim_prince_test/latest |
Test location | /workspace/coverage/default/376.prim_prince_test.2471454558 |
Short name | T263 |
Test name | |
Test status | |
Simulation time | 2576116556 ps |
CPU time | 41.83 seconds |
Started | Aug 17 04:26:04 PM PDT 24 |
Finished | Aug 17 04:26:53 PM PDT 24 |
Peak memory | 146340 kb |
Host | smart-d5b535f3-f212-4ac7-8ad3-fd00b7c80da4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2471454558 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 376.prim_prince_test.2471454558 |
Directory | /workspace/376.prim_prince_test/latest |
Test location | /workspace/coverage/default/377.prim_prince_test.3526956701 |
Short name | T459 |
Test name | |
Test status | |
Simulation time | 1091046293 ps |
CPU time | 18.19 seconds |
Started | Aug 17 04:25:02 PM PDT 24 |
Finished | Aug 17 04:25:24 PM PDT 24 |
Peak memory | 146124 kb |
Host | smart-08303267-9c5e-4b89-99bd-ba3987eab8b1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3526956701 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 377.prim_prince_test.3526956701 |
Directory | /workspace/377.prim_prince_test/latest |
Test location | /workspace/coverage/default/378.prim_prince_test.583588113 |
Short name | T14 |
Test name | |
Test status | |
Simulation time | 3325315142 ps |
CPU time | 54.48 seconds |
Started | Aug 17 04:25:47 PM PDT 24 |
Finished | Aug 17 04:26:52 PM PDT 24 |
Peak memory | 145068 kb |
Host | smart-9c6fccfb-88e7-472f-b4aa-a08039d1ca01 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=583588113 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 378.prim_prince_test.583588113 |
Directory | /workspace/378.prim_prince_test/latest |
Test location | /workspace/coverage/default/379.prim_prince_test.380444461 |
Short name | T238 |
Test name | |
Test status | |
Simulation time | 3234191402 ps |
CPU time | 54 seconds |
Started | Aug 17 04:23:04 PM PDT 24 |
Finished | Aug 17 04:24:10 PM PDT 24 |
Peak memory | 146584 kb |
Host | smart-4f8a64ef-64a1-4028-aff1-67d9755e6af1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=380444461 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 379.prim_prince_test.380444461 |
Directory | /workspace/379.prim_prince_test/latest |
Test location | /workspace/coverage/default/38.prim_prince_test.2080862598 |
Short name | T151 |
Test name | |
Test status | |
Simulation time | 3552672598 ps |
CPU time | 58.33 seconds |
Started | Aug 17 04:20:27 PM PDT 24 |
Finished | Aug 17 04:21:37 PM PDT 24 |
Peak memory | 144860 kb |
Host | smart-0c52ead6-61ed-479f-82e4-25f83a8cbac9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2080862598 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_prince_test.2080862598 |
Directory | /workspace/38.prim_prince_test/latest |
Test location | /workspace/coverage/default/380.prim_prince_test.4023065566 |
Short name | T372 |
Test name | |
Test status | |
Simulation time | 1425604584 ps |
CPU time | 23.52 seconds |
Started | Aug 17 04:25:04 PM PDT 24 |
Finished | Aug 17 04:25:32 PM PDT 24 |
Peak memory | 146140 kb |
Host | smart-b3d2f439-4896-440b-b4f1-03c64e9faf81 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4023065566 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 380.prim_prince_test.4023065566 |
Directory | /workspace/380.prim_prince_test/latest |
Test location | /workspace/coverage/default/381.prim_prince_test.2867869337 |
Short name | T272 |
Test name | |
Test status | |
Simulation time | 2247180318 ps |
CPU time | 38.77 seconds |
Started | Aug 17 04:23:13 PM PDT 24 |
Finished | Aug 17 04:24:01 PM PDT 24 |
Peak memory | 146624 kb |
Host | smart-3a1ca163-1833-43ec-a460-7a7c9241f6a4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2867869337 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 381.prim_prince_test.2867869337 |
Directory | /workspace/381.prim_prince_test/latest |
Test location | /workspace/coverage/default/382.prim_prince_test.2024110408 |
Short name | T171 |
Test name | |
Test status | |
Simulation time | 2141995045 ps |
CPU time | 35.04 seconds |
Started | Aug 17 04:25:48 PM PDT 24 |
Finished | Aug 17 04:26:30 PM PDT 24 |
Peak memory | 146304 kb |
Host | smart-a40c53fe-8cbd-451a-9c65-9a6f2003b955 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2024110408 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 382.prim_prince_test.2024110408 |
Directory | /workspace/382.prim_prince_test/latest |
Test location | /workspace/coverage/default/383.prim_prince_test.778918401 |
Short name | T369 |
Test name | |
Test status | |
Simulation time | 1851528905 ps |
CPU time | 31.49 seconds |
Started | Aug 17 04:23:09 PM PDT 24 |
Finished | Aug 17 04:23:48 PM PDT 24 |
Peak memory | 146572 kb |
Host | smart-0468bcb0-ce62-4e64-a2e3-57d88573c41c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=778918401 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 383.prim_prince_test.778918401 |
Directory | /workspace/383.prim_prince_test/latest |
Test location | /workspace/coverage/default/384.prim_prince_test.3666592578 |
Short name | T222 |
Test name | |
Test status | |
Simulation time | 1219994247 ps |
CPU time | 20.07 seconds |
Started | Aug 17 04:25:48 PM PDT 24 |
Finished | Aug 17 04:26:12 PM PDT 24 |
Peak memory | 145424 kb |
Host | smart-9ac53e6a-6da1-4ea5-96ee-28433a6e7622 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3666592578 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 384.prim_prince_test.3666592578 |
Directory | /workspace/384.prim_prince_test/latest |
Test location | /workspace/coverage/default/385.prim_prince_test.4172435358 |
Short name | T100 |
Test name | |
Test status | |
Simulation time | 2717995125 ps |
CPU time | 44.27 seconds |
Started | Aug 17 04:25:48 PM PDT 24 |
Finished | Aug 17 04:26:41 PM PDT 24 |
Peak memory | 146420 kb |
Host | smart-ad376f3b-18c6-4507-9a25-051017ef1651 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4172435358 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 385.prim_prince_test.4172435358 |
Directory | /workspace/385.prim_prince_test/latest |
Test location | /workspace/coverage/default/386.prim_prince_test.3766739670 |
Short name | T156 |
Test name | |
Test status | |
Simulation time | 2961488339 ps |
CPU time | 47.03 seconds |
Started | Aug 17 04:25:26 PM PDT 24 |
Finished | Aug 17 04:26:22 PM PDT 24 |
Peak memory | 145616 kb |
Host | smart-4293cc61-7be9-4fdc-9aae-a8dbf6f640a5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3766739670 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 386.prim_prince_test.3766739670 |
Directory | /workspace/386.prim_prince_test/latest |
Test location | /workspace/coverage/default/387.prim_prince_test.4194834460 |
Short name | T332 |
Test name | |
Test status | |
Simulation time | 3684423146 ps |
CPU time | 59.04 seconds |
Started | Aug 17 04:25:48 PM PDT 24 |
Finished | Aug 17 04:26:59 PM PDT 24 |
Peak memory | 146428 kb |
Host | smart-3388bdaa-7e58-4350-8ad6-ef203af66e23 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4194834460 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 387.prim_prince_test.4194834460 |
Directory | /workspace/387.prim_prince_test/latest |
Test location | /workspace/coverage/default/388.prim_prince_test.486615780 |
Short name | T417 |
Test name | |
Test status | |
Simulation time | 2261917855 ps |
CPU time | 38.23 seconds |
Started | Aug 17 04:23:10 PM PDT 24 |
Finished | Aug 17 04:23:56 PM PDT 24 |
Peak memory | 146660 kb |
Host | smart-177cb9ec-2c06-4bcc-aaa3-743dbc777b8c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=486615780 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 388.prim_prince_test.486615780 |
Directory | /workspace/388.prim_prince_test/latest |
Test location | /workspace/coverage/default/389.prim_prince_test.3950012668 |
Short name | T255 |
Test name | |
Test status | |
Simulation time | 2144419105 ps |
CPU time | 34.81 seconds |
Started | Aug 17 04:25:34 PM PDT 24 |
Finished | Aug 17 04:26:15 PM PDT 24 |
Peak memory | 146132 kb |
Host | smart-a981a080-c62a-449c-8ed4-913a218be03c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3950012668 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 389.prim_prince_test.3950012668 |
Directory | /workspace/389.prim_prince_test/latest |
Test location | /workspace/coverage/default/39.prim_prince_test.3726795399 |
Short name | T448 |
Test name | |
Test status | |
Simulation time | 2121358757 ps |
CPU time | 35.55 seconds |
Started | Aug 17 04:21:27 PM PDT 24 |
Finished | Aug 17 04:22:09 PM PDT 24 |
Peak memory | 143960 kb |
Host | smart-b82912c7-26f6-4015-a717-8a5f87784554 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3726795399 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_prince_test.3726795399 |
Directory | /workspace/39.prim_prince_test/latest |
Test location | /workspace/coverage/default/390.prim_prince_test.1490374838 |
Short name | T120 |
Test name | |
Test status | |
Simulation time | 3364462483 ps |
CPU time | 53.31 seconds |
Started | Aug 17 04:25:33 PM PDT 24 |
Finished | Aug 17 04:26:36 PM PDT 24 |
Peak memory | 146196 kb |
Host | smart-7f1be943-568d-4a61-a0cc-01e5c9f055c7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1490374838 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 390.prim_prince_test.1490374838 |
Directory | /workspace/390.prim_prince_test/latest |
Test location | /workspace/coverage/default/391.prim_prince_test.478618806 |
Short name | T446 |
Test name | |
Test status | |
Simulation time | 808749919 ps |
CPU time | 13.37 seconds |
Started | Aug 17 04:24:59 PM PDT 24 |
Finished | Aug 17 04:25:15 PM PDT 24 |
Peak memory | 146108 kb |
Host | smart-af3a8199-59a8-48b9-8eea-934b82d5d3db |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=478618806 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 391.prim_prince_test.478618806 |
Directory | /workspace/391.prim_prince_test/latest |
Test location | /workspace/coverage/default/392.prim_prince_test.2383286493 |
Short name | T24 |
Test name | |
Test status | |
Simulation time | 2496355963 ps |
CPU time | 42.96 seconds |
Started | Aug 17 04:23:19 PM PDT 24 |
Finished | Aug 17 04:24:11 PM PDT 24 |
Peak memory | 146628 kb |
Host | smart-c63270b9-2329-4ede-984f-f2d50288a3a6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2383286493 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 392.prim_prince_test.2383286493 |
Directory | /workspace/392.prim_prince_test/latest |
Test location | /workspace/coverage/default/393.prim_prince_test.1257166175 |
Short name | T366 |
Test name | |
Test status | |
Simulation time | 1861431025 ps |
CPU time | 31.74 seconds |
Started | Aug 17 04:23:20 PM PDT 24 |
Finished | Aug 17 04:23:58 PM PDT 24 |
Peak memory | 146592 kb |
Host | smart-7805ee9c-7c2f-4235-a8d6-f88a4f09fcc6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1257166175 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 393.prim_prince_test.1257166175 |
Directory | /workspace/393.prim_prince_test/latest |
Test location | /workspace/coverage/default/394.prim_prince_test.2406699103 |
Short name | T181 |
Test name | |
Test status | |
Simulation time | 1927320231 ps |
CPU time | 31.5 seconds |
Started | Aug 17 04:25:33 PM PDT 24 |
Finished | Aug 17 04:26:10 PM PDT 24 |
Peak memory | 146272 kb |
Host | smart-c8e26ee5-f1db-4c3a-8a98-2a6d474ac34a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2406699103 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 394.prim_prince_test.2406699103 |
Directory | /workspace/394.prim_prince_test/latest |
Test location | /workspace/coverage/default/395.prim_prince_test.2854511892 |
Short name | T415 |
Test name | |
Test status | |
Simulation time | 1004588511 ps |
CPU time | 16.46 seconds |
Started | Aug 17 04:25:32 PM PDT 24 |
Finished | Aug 17 04:25:52 PM PDT 24 |
Peak memory | 146156 kb |
Host | smart-3e42b1d2-23ce-4483-bbd2-b4fd7442fabd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2854511892 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 395.prim_prince_test.2854511892 |
Directory | /workspace/395.prim_prince_test/latest |
Test location | /workspace/coverage/default/396.prim_prince_test.4284616123 |
Short name | T175 |
Test name | |
Test status | |
Simulation time | 3090393404 ps |
CPU time | 50.4 seconds |
Started | Aug 17 04:24:50 PM PDT 24 |
Finished | Aug 17 04:25:50 PM PDT 24 |
Peak memory | 146168 kb |
Host | smart-63403dd9-4185-4c52-8b3a-328f91df724c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4284616123 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 396.prim_prince_test.4284616123 |
Directory | /workspace/396.prim_prince_test/latest |
Test location | /workspace/coverage/default/397.prim_prince_test.3388373244 |
Short name | T342 |
Test name | |
Test status | |
Simulation time | 1112090278 ps |
CPU time | 18.4 seconds |
Started | Aug 17 04:25:06 PM PDT 24 |
Finished | Aug 17 04:25:28 PM PDT 24 |
Peak memory | 145904 kb |
Host | smart-fc7fb382-61fd-4a93-a1ac-5b53f4f1cf49 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3388373244 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 397.prim_prince_test.3388373244 |
Directory | /workspace/397.prim_prince_test/latest |
Test location | /workspace/coverage/default/398.prim_prince_test.4293078968 |
Short name | T12 |
Test name | |
Test status | |
Simulation time | 2837739837 ps |
CPU time | 47.1 seconds |
Started | Aug 17 04:25:06 PM PDT 24 |
Finished | Aug 17 04:26:03 PM PDT 24 |
Peak memory | 146208 kb |
Host | smart-e81698e2-c6ae-4eb2-8ec2-5d98df451b07 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4293078968 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 398.prim_prince_test.4293078968 |
Directory | /workspace/398.prim_prince_test/latest |
Test location | /workspace/coverage/default/399.prim_prince_test.1738821595 |
Short name | T220 |
Test name | |
Test status | |
Simulation time | 2400896606 ps |
CPU time | 39.3 seconds |
Started | Aug 17 04:24:50 PM PDT 24 |
Finished | Aug 17 04:25:38 PM PDT 24 |
Peak memory | 146168 kb |
Host | smart-02789823-be7c-4581-96be-e296b5bc0ae5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1738821595 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 399.prim_prince_test.1738821595 |
Directory | /workspace/399.prim_prince_test/latest |
Test location | /workspace/coverage/default/4.prim_prince_test.2705070907 |
Short name | T224 |
Test name | |
Test status | |
Simulation time | 1605872116 ps |
CPU time | 26.88 seconds |
Started | Aug 17 04:20:26 PM PDT 24 |
Finished | Aug 17 04:20:58 PM PDT 24 |
Peak memory | 146120 kb |
Host | smart-33f18b0f-1241-4ded-b029-084a9dea4810 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2705070907 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_prince_test.2705070907 |
Directory | /workspace/4.prim_prince_test/latest |
Test location | /workspace/coverage/default/40.prim_prince_test.3303907462 |
Short name | T46 |
Test name | |
Test status | |
Simulation time | 1121164766 ps |
CPU time | 18.73 seconds |
Started | Aug 17 04:20:15 PM PDT 24 |
Finished | Aug 17 04:20:38 PM PDT 24 |
Peak memory | 145396 kb |
Host | smart-38494a3e-6415-45e8-ab75-3884027b067c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3303907462 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_prince_test.3303907462 |
Directory | /workspace/40.prim_prince_test/latest |
Test location | /workspace/coverage/default/400.prim_prince_test.3699067225 |
Short name | T497 |
Test name | |
Test status | |
Simulation time | 3001665078 ps |
CPU time | 49.47 seconds |
Started | Aug 17 04:24:58 PM PDT 24 |
Finished | Aug 17 04:25:58 PM PDT 24 |
Peak memory | 146168 kb |
Host | smart-79ff31ff-4311-4d8c-b865-817c927cc30c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3699067225 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 400.prim_prince_test.3699067225 |
Directory | /workspace/400.prim_prince_test/latest |
Test location | /workspace/coverage/default/401.prim_prince_test.264150085 |
Short name | T94 |
Test name | |
Test status | |
Simulation time | 3286555487 ps |
CPU time | 52.69 seconds |
Started | Aug 17 04:25:24 PM PDT 24 |
Finished | Aug 17 04:26:26 PM PDT 24 |
Peak memory | 145668 kb |
Host | smart-bd3f5f88-342f-4736-88a9-9a5df90fbe70 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=264150085 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 401.prim_prince_test.264150085 |
Directory | /workspace/401.prim_prince_test/latest |
Test location | /workspace/coverage/default/402.prim_prince_test.3269769220 |
Short name | T435 |
Test name | |
Test status | |
Simulation time | 2572629238 ps |
CPU time | 41.37 seconds |
Started | Aug 17 04:25:12 PM PDT 24 |
Finished | Aug 17 04:26:01 PM PDT 24 |
Peak memory | 146324 kb |
Host | smart-0f57dbd7-8cdf-4372-ad1a-6d6d7b4a6ab8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3269769220 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 402.prim_prince_test.3269769220 |
Directory | /workspace/402.prim_prince_test/latest |
Test location | /workspace/coverage/default/403.prim_prince_test.2923956596 |
Short name | T208 |
Test name | |
Test status | |
Simulation time | 3155671970 ps |
CPU time | 50.48 seconds |
Started | Aug 17 04:25:32 PM PDT 24 |
Finished | Aug 17 04:26:33 PM PDT 24 |
Peak memory | 146328 kb |
Host | smart-fc8f5d6e-118e-49cb-ac74-e99b1ebc6ad0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2923956596 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 403.prim_prince_test.2923956596 |
Directory | /workspace/403.prim_prince_test/latest |
Test location | /workspace/coverage/default/404.prim_prince_test.4246929332 |
Short name | T201 |
Test name | |
Test status | |
Simulation time | 3507550957 ps |
CPU time | 56.77 seconds |
Started | Aug 17 04:25:32 PM PDT 24 |
Finished | Aug 17 04:26:40 PM PDT 24 |
Peak memory | 146316 kb |
Host | smart-31fb7a7b-36c7-48c0-a546-38fc42c0d5ef |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4246929332 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 404.prim_prince_test.4246929332 |
Directory | /workspace/404.prim_prince_test/latest |
Test location | /workspace/coverage/default/405.prim_prince_test.407508910 |
Short name | T177 |
Test name | |
Test status | |
Simulation time | 1658678766 ps |
CPU time | 27.72 seconds |
Started | Aug 17 04:23:30 PM PDT 24 |
Finished | Aug 17 04:24:03 PM PDT 24 |
Peak memory | 146516 kb |
Host | smart-6722ad2b-1cc5-47f2-a168-b87b68813e2d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=407508910 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 405.prim_prince_test.407508910 |
Directory | /workspace/405.prim_prince_test/latest |
Test location | /workspace/coverage/default/406.prim_prince_test.1058388979 |
Short name | T410 |
Test name | |
Test status | |
Simulation time | 806054896 ps |
CPU time | 12.94 seconds |
Started | Aug 17 04:25:34 PM PDT 24 |
Finished | Aug 17 04:25:50 PM PDT 24 |
Peak memory | 146464 kb |
Host | smart-a357b22d-e352-4460-baec-23c6069d7d21 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1058388979 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 406.prim_prince_test.1058388979 |
Directory | /workspace/406.prim_prince_test/latest |
Test location | /workspace/coverage/default/407.prim_prince_test.2221702788 |
Short name | T95 |
Test name | |
Test status | |
Simulation time | 2225427727 ps |
CPU time | 36.09 seconds |
Started | Aug 17 04:24:50 PM PDT 24 |
Finished | Aug 17 04:25:33 PM PDT 24 |
Peak memory | 146168 kb |
Host | smart-68be7d8c-d616-476c-a3cb-1cfeabf7b9dc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2221702788 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 407.prim_prince_test.2221702788 |
Directory | /workspace/407.prim_prince_test/latest |
Test location | /workspace/coverage/default/408.prim_prince_test.992868503 |
Short name | T155 |
Test name | |
Test status | |
Simulation time | 1782484519 ps |
CPU time | 29.07 seconds |
Started | Aug 17 04:25:06 PM PDT 24 |
Finished | Aug 17 04:25:41 PM PDT 24 |
Peak memory | 146148 kb |
Host | smart-9a70eba8-249a-4426-8a10-3627f74eddc4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=992868503 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 408.prim_prince_test.992868503 |
Directory | /workspace/408.prim_prince_test/latest |
Test location | /workspace/coverage/default/409.prim_prince_test.284696408 |
Short name | T240 |
Test name | |
Test status | |
Simulation time | 2634871642 ps |
CPU time | 42.15 seconds |
Started | Aug 17 04:25:11 PM PDT 24 |
Finished | Aug 17 04:26:02 PM PDT 24 |
Peak memory | 146260 kb |
Host | smart-cebc0738-ef33-4335-9179-9b87060ed55e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=284696408 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 409.prim_prince_test.284696408 |
Directory | /workspace/409.prim_prince_test/latest |
Test location | /workspace/coverage/default/41.prim_prince_test.277437516 |
Short name | T494 |
Test name | |
Test status | |
Simulation time | 2669534494 ps |
CPU time | 44.72 seconds |
Started | Aug 17 04:20:21 PM PDT 24 |
Finished | Aug 17 04:21:16 PM PDT 24 |
Peak memory | 144972 kb |
Host | smart-af067bc9-fc1a-4834-ae45-627b6e27018a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=277437516 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_prince_test.277437516 |
Directory | /workspace/41.prim_prince_test/latest |
Test location | /workspace/coverage/default/410.prim_prince_test.2193139360 |
Short name | T114 |
Test name | |
Test status | |
Simulation time | 1155741191 ps |
CPU time | 19.14 seconds |
Started | Aug 17 04:24:49 PM PDT 24 |
Finished | Aug 17 04:25:12 PM PDT 24 |
Peak memory | 145100 kb |
Host | smart-70ba319b-e5af-4437-af96-a49a935f6f76 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2193139360 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 410.prim_prince_test.2193139360 |
Directory | /workspace/410.prim_prince_test/latest |
Test location | /workspace/coverage/default/411.prim_prince_test.2217645615 |
Short name | T296 |
Test name | |
Test status | |
Simulation time | 2081315707 ps |
CPU time | 35.92 seconds |
Started | Aug 17 04:23:21 PM PDT 24 |
Finished | Aug 17 04:24:05 PM PDT 24 |
Peak memory | 146572 kb |
Host | smart-0454d2f5-492e-4518-9f8b-64aadda0d230 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2217645615 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 411.prim_prince_test.2217645615 |
Directory | /workspace/411.prim_prince_test/latest |
Test location | /workspace/coverage/default/412.prim_prince_test.3071864482 |
Short name | T87 |
Test name | |
Test status | |
Simulation time | 3444556084 ps |
CPU time | 55.48 seconds |
Started | Aug 17 04:25:34 PM PDT 24 |
Finished | Aug 17 04:26:40 PM PDT 24 |
Peak memory | 146188 kb |
Host | smart-92a3d82c-78c9-4d5a-af2a-a61ddb5bab20 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3071864482 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 412.prim_prince_test.3071864482 |
Directory | /workspace/412.prim_prince_test/latest |
Test location | /workspace/coverage/default/413.prim_prince_test.1258763461 |
Short name | T45 |
Test name | |
Test status | |
Simulation time | 2688710828 ps |
CPU time | 44.18 seconds |
Started | Aug 17 04:24:58 PM PDT 24 |
Finished | Aug 17 04:25:51 PM PDT 24 |
Peak memory | 144496 kb |
Host | smart-e2fce627-0333-4f2f-a433-f928ea8a8f52 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1258763461 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 413.prim_prince_test.1258763461 |
Directory | /workspace/413.prim_prince_test/latest |
Test location | /workspace/coverage/default/414.prim_prince_test.387800935 |
Short name | T411 |
Test name | |
Test status | |
Simulation time | 1845132290 ps |
CPU time | 30.59 seconds |
Started | Aug 17 04:24:59 PM PDT 24 |
Finished | Aug 17 04:25:36 PM PDT 24 |
Peak memory | 146224 kb |
Host | smart-8e8ff63d-5442-49f8-abb2-01ccef2f600e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=387800935 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 414.prim_prince_test.387800935 |
Directory | /workspace/414.prim_prince_test/latest |
Test location | /workspace/coverage/default/415.prim_prince_test.872128585 |
Short name | T148 |
Test name | |
Test status | |
Simulation time | 1398976986 ps |
CPU time | 24.05 seconds |
Started | Aug 17 04:23:33 PM PDT 24 |
Finished | Aug 17 04:24:02 PM PDT 24 |
Peak memory | 146596 kb |
Host | smart-3f6ee1db-590a-4a22-8e52-7beed763ae51 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=872128585 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 415.prim_prince_test.872128585 |
Directory | /workspace/415.prim_prince_test/latest |
Test location | /workspace/coverage/default/416.prim_prince_test.3957857128 |
Short name | T356 |
Test name | |
Test status | |
Simulation time | 2965897822 ps |
CPU time | 50.16 seconds |
Started | Aug 17 04:23:32 PM PDT 24 |
Finished | Aug 17 04:24:33 PM PDT 24 |
Peak memory | 146648 kb |
Host | smart-cdb75f5c-7c50-44bf-9093-15fabc5c88f5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3957857128 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 416.prim_prince_test.3957857128 |
Directory | /workspace/416.prim_prince_test/latest |
Test location | /workspace/coverage/default/417.prim_prince_test.323218667 |
Short name | T223 |
Test name | |
Test status | |
Simulation time | 1049976507 ps |
CPU time | 18.28 seconds |
Started | Aug 17 04:23:30 PM PDT 24 |
Finished | Aug 17 04:23:52 PM PDT 24 |
Peak memory | 146516 kb |
Host | smart-b78a36ee-d85d-47de-a89d-f591269b6aab |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=323218667 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 417.prim_prince_test.323218667 |
Directory | /workspace/417.prim_prince_test/latest |
Test location | /workspace/coverage/default/418.prim_prince_test.790463745 |
Short name | T252 |
Test name | |
Test status | |
Simulation time | 1621094905 ps |
CPU time | 26.55 seconds |
Started | Aug 17 04:25:48 PM PDT 24 |
Finished | Aug 17 04:26:20 PM PDT 24 |
Peak memory | 146284 kb |
Host | smart-9335e302-3f3f-4a45-8693-5d8f481efaae |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=790463745 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 418.prim_prince_test.790463745 |
Directory | /workspace/418.prim_prince_test/latest |
Test location | /workspace/coverage/default/419.prim_prince_test.2134682811 |
Short name | T190 |
Test name | |
Test status | |
Simulation time | 3140888308 ps |
CPU time | 54.35 seconds |
Started | Aug 17 04:23:46 PM PDT 24 |
Finished | Aug 17 04:24:54 PM PDT 24 |
Peak memory | 145668 kb |
Host | smart-8d29cbf9-4f7b-46f8-ab30-f3e9589f8ece |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2134682811 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 419.prim_prince_test.2134682811 |
Directory | /workspace/419.prim_prince_test/latest |
Test location | /workspace/coverage/default/42.prim_prince_test.3717664410 |
Short name | T270 |
Test name | |
Test status | |
Simulation time | 2992370545 ps |
CPU time | 49.35 seconds |
Started | Aug 17 04:20:25 PM PDT 24 |
Finished | Aug 17 04:21:24 PM PDT 24 |
Peak memory | 146260 kb |
Host | smart-c6bd2179-3e13-4875-b055-fd513c2555ca |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3717664410 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_prince_test.3717664410 |
Directory | /workspace/42.prim_prince_test/latest |
Test location | /workspace/coverage/default/420.prim_prince_test.2848264818 |
Short name | T399 |
Test name | |
Test status | |
Simulation time | 1724039411 ps |
CPU time | 28.59 seconds |
Started | Aug 17 04:23:45 PM PDT 24 |
Finished | Aug 17 04:24:20 PM PDT 24 |
Peak memory | 146512 kb |
Host | smart-42763e31-835b-418c-8fa4-0ec19f5da788 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2848264818 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 420.prim_prince_test.2848264818 |
Directory | /workspace/420.prim_prince_test/latest |
Test location | /workspace/coverage/default/421.prim_prince_test.439088917 |
Short name | T483 |
Test name | |
Test status | |
Simulation time | 3731550654 ps |
CPU time | 62.8 seconds |
Started | Aug 17 04:23:47 PM PDT 24 |
Finished | Aug 17 04:25:03 PM PDT 24 |
Peak memory | 146576 kb |
Host | smart-74d0c562-758d-4744-959b-dccc7bad1f63 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=439088917 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 421.prim_prince_test.439088917 |
Directory | /workspace/421.prim_prince_test/latest |
Test location | /workspace/coverage/default/422.prim_prince_test.2082729774 |
Short name | T216 |
Test name | |
Test status | |
Simulation time | 1956459673 ps |
CPU time | 30.37 seconds |
Started | Aug 17 04:24:57 PM PDT 24 |
Finished | Aug 17 04:25:32 PM PDT 24 |
Peak memory | 146156 kb |
Host | smart-7d07033b-07d3-466b-bb87-2014f7be3706 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2082729774 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 422.prim_prince_test.2082729774 |
Directory | /workspace/422.prim_prince_test/latest |
Test location | /workspace/coverage/default/423.prim_prince_test.3267281469 |
Short name | T138 |
Test name | |
Test status | |
Simulation time | 1533544679 ps |
CPU time | 25.55 seconds |
Started | Aug 17 04:23:47 PM PDT 24 |
Finished | Aug 17 04:24:18 PM PDT 24 |
Peak memory | 146504 kb |
Host | smart-364894c6-7460-4ca0-b671-d6de6c7d3602 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3267281469 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 423.prim_prince_test.3267281469 |
Directory | /workspace/423.prim_prince_test/latest |
Test location | /workspace/coverage/default/424.prim_prince_test.260254449 |
Short name | T370 |
Test name | |
Test status | |
Simulation time | 850963150 ps |
CPU time | 14 seconds |
Started | Aug 17 04:24:59 PM PDT 24 |
Finished | Aug 17 04:25:16 PM PDT 24 |
Peak memory | 146076 kb |
Host | smart-2f40dd4c-a782-417b-ae3f-7aaa8184de77 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=260254449 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 424.prim_prince_test.260254449 |
Directory | /workspace/424.prim_prince_test/latest |
Test location | /workspace/coverage/default/425.prim_prince_test.3280937647 |
Short name | T162 |
Test name | |
Test status | |
Simulation time | 1574286448 ps |
CPU time | 26.03 seconds |
Started | Aug 17 04:24:59 PM PDT 24 |
Finished | Aug 17 04:25:30 PM PDT 24 |
Peak memory | 146204 kb |
Host | smart-f12cd645-0f13-4dd6-b398-b6a6fd6e1d13 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3280937647 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 425.prim_prince_test.3280937647 |
Directory | /workspace/425.prim_prince_test/latest |
Test location | /workspace/coverage/default/426.prim_prince_test.2046063973 |
Short name | T166 |
Test name | |
Test status | |
Simulation time | 1614290780 ps |
CPU time | 27.51 seconds |
Started | Aug 17 04:25:05 PM PDT 24 |
Finished | Aug 17 04:25:39 PM PDT 24 |
Peak memory | 146456 kb |
Host | smart-f22b2aaf-3adb-4f2c-ab01-ed69969d5eec |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2046063973 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 426.prim_prince_test.2046063973 |
Directory | /workspace/426.prim_prince_test/latest |
Test location | /workspace/coverage/default/427.prim_prince_test.1719959618 |
Short name | T168 |
Test name | |
Test status | |
Simulation time | 2415737962 ps |
CPU time | 40.6 seconds |
Started | Aug 17 04:25:05 PM PDT 24 |
Finished | Aug 17 04:25:55 PM PDT 24 |
Peak memory | 146520 kb |
Host | smart-380091ac-06f7-47a5-b425-742d721232d1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1719959618 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 427.prim_prince_test.1719959618 |
Directory | /workspace/427.prim_prince_test/latest |
Test location | /workspace/coverage/default/428.prim_prince_test.974537005 |
Short name | T196 |
Test name | |
Test status | |
Simulation time | 2862233278 ps |
CPU time | 48.27 seconds |
Started | Aug 17 04:25:04 PM PDT 24 |
Finished | Aug 17 04:26:03 PM PDT 24 |
Peak memory | 146412 kb |
Host | smart-8284e1f9-ecf2-435d-9454-23d4fa31db63 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=974537005 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 428.prim_prince_test.974537005 |
Directory | /workspace/428.prim_prince_test/latest |
Test location | /workspace/coverage/default/429.prim_prince_test.3713672148 |
Short name | T104 |
Test name | |
Test status | |
Simulation time | 2893219594 ps |
CPU time | 48.18 seconds |
Started | Aug 17 04:23:33 PM PDT 24 |
Finished | Aug 17 04:24:32 PM PDT 24 |
Peak memory | 146644 kb |
Host | smart-412d538d-aec9-4dc7-af36-6351c07cb4ec |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3713672148 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 429.prim_prince_test.3713672148 |
Directory | /workspace/429.prim_prince_test/latest |
Test location | /workspace/coverage/default/43.prim_prince_test.583537349 |
Short name | T179 |
Test name | |
Test status | |
Simulation time | 1323182221 ps |
CPU time | 22.58 seconds |
Started | Aug 17 04:21:40 PM PDT 24 |
Finished | Aug 17 04:22:07 PM PDT 24 |
Peak memory | 146284 kb |
Host | smart-13ed80c8-b110-4ad2-8ed5-33dde9a661da |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=583537349 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_prince_test.583537349 |
Directory | /workspace/43.prim_prince_test/latest |
Test location | /workspace/coverage/default/430.prim_prince_test.3634764250 |
Short name | T203 |
Test name | |
Test status | |
Simulation time | 3305183393 ps |
CPU time | 52.49 seconds |
Started | Aug 17 04:25:49 PM PDT 24 |
Finished | Aug 17 04:26:50 PM PDT 24 |
Peak memory | 146340 kb |
Host | smart-3bad3cc2-6a84-4b85-8725-72bfdc2f0c17 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3634764250 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 430.prim_prince_test.3634764250 |
Directory | /workspace/430.prim_prince_test/latest |
Test location | /workspace/coverage/default/431.prim_prince_test.194812828 |
Short name | T327 |
Test name | |
Test status | |
Simulation time | 1748126237 ps |
CPU time | 28.52 seconds |
Started | Aug 17 04:25:48 PM PDT 24 |
Finished | Aug 17 04:26:22 PM PDT 24 |
Peak memory | 146284 kb |
Host | smart-e6a6802f-1c2f-4888-ac23-ef4c8b0de93f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=194812828 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 431.prim_prince_test.194812828 |
Directory | /workspace/431.prim_prince_test/latest |
Test location | /workspace/coverage/default/432.prim_prince_test.1932299233 |
Short name | T287 |
Test name | |
Test status | |
Simulation time | 2963846141 ps |
CPU time | 47.61 seconds |
Started | Aug 17 04:24:56 PM PDT 24 |
Finished | Aug 17 04:25:52 PM PDT 24 |
Peak memory | 145660 kb |
Host | smart-6dc5490c-a592-4508-8491-3f1556198fd8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1932299233 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 432.prim_prince_test.1932299233 |
Directory | /workspace/432.prim_prince_test/latest |
Test location | /workspace/coverage/default/433.prim_prince_test.3835327589 |
Short name | T129 |
Test name | |
Test status | |
Simulation time | 1145484474 ps |
CPU time | 18.05 seconds |
Started | Aug 17 04:25:32 PM PDT 24 |
Finished | Aug 17 04:25:54 PM PDT 24 |
Peak memory | 145596 kb |
Host | smart-c49638c6-27ed-48cc-8b40-afc0c49544c0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3835327589 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 433.prim_prince_test.3835327589 |
Directory | /workspace/433.prim_prince_test/latest |
Test location | /workspace/coverage/default/434.prim_prince_test.1760923210 |
Short name | T140 |
Test name | |
Test status | |
Simulation time | 968371247 ps |
CPU time | 15.79 seconds |
Started | Aug 17 04:24:57 PM PDT 24 |
Finished | Aug 17 04:25:16 PM PDT 24 |
Peak memory | 146252 kb |
Host | smart-f3697e03-4c5c-48b4-94e0-f7d5feea3333 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1760923210 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 434.prim_prince_test.1760923210 |
Directory | /workspace/434.prim_prince_test/latest |
Test location | /workspace/coverage/default/435.prim_prince_test.3060545475 |
Short name | T349 |
Test name | |
Test status | |
Simulation time | 1268480548 ps |
CPU time | 20.6 seconds |
Started | Aug 17 04:24:55 PM PDT 24 |
Finished | Aug 17 04:25:20 PM PDT 24 |
Peak memory | 146172 kb |
Host | smart-57e179e5-1a96-4101-8b79-6d54259e78d4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3060545475 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 435.prim_prince_test.3060545475 |
Directory | /workspace/435.prim_prince_test/latest |
Test location | /workspace/coverage/default/436.prim_prince_test.3693003334 |
Short name | T400 |
Test name | |
Test status | |
Simulation time | 2696202880 ps |
CPU time | 44.93 seconds |
Started | Aug 17 04:25:08 PM PDT 24 |
Finished | Aug 17 04:26:03 PM PDT 24 |
Peak memory | 146368 kb |
Host | smart-e3fd36dc-b3b0-4ff8-b051-c1d15318c2fc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3693003334 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 436.prim_prince_test.3693003334 |
Directory | /workspace/436.prim_prince_test/latest |
Test location | /workspace/coverage/default/437.prim_prince_test.1042068458 |
Short name | T144 |
Test name | |
Test status | |
Simulation time | 1867576252 ps |
CPU time | 31.76 seconds |
Started | Aug 17 04:25:08 PM PDT 24 |
Finished | Aug 17 04:25:47 PM PDT 24 |
Peak memory | 146304 kb |
Host | smart-eaa633f5-4942-4e89-be02-51cb08e3bc25 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1042068458 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 437.prim_prince_test.1042068458 |
Directory | /workspace/437.prim_prince_test/latest |
Test location | /workspace/coverage/default/438.prim_prince_test.3517962482 |
Short name | T159 |
Test name | |
Test status | |
Simulation time | 2717439247 ps |
CPU time | 43.89 seconds |
Started | Aug 17 04:24:56 PM PDT 24 |
Finished | Aug 17 04:25:48 PM PDT 24 |
Peak memory | 146124 kb |
Host | smart-cadc322d-0308-4526-9016-9f9f47a91c56 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3517962482 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 438.prim_prince_test.3517962482 |
Directory | /workspace/438.prim_prince_test/latest |
Test location | /workspace/coverage/default/439.prim_prince_test.3617400546 |
Short name | T476 |
Test name | |
Test status | |
Simulation time | 1595560598 ps |
CPU time | 25.93 seconds |
Started | Aug 17 04:24:55 PM PDT 24 |
Finished | Aug 17 04:25:25 PM PDT 24 |
Peak memory | 146032 kb |
Host | smart-1e202e6c-2115-499d-80e7-df712004e7f3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3617400546 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 439.prim_prince_test.3617400546 |
Directory | /workspace/439.prim_prince_test/latest |
Test location | /workspace/coverage/default/44.prim_prince_test.3305050150 |
Short name | T285 |
Test name | |
Test status | |
Simulation time | 2903969891 ps |
CPU time | 47.49 seconds |
Started | Aug 17 04:20:26 PM PDT 24 |
Finished | Aug 17 04:21:22 PM PDT 24 |
Peak memory | 145068 kb |
Host | smart-d0142460-0f70-4bf4-89ab-0b2313bee5a1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3305050150 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_prince_test.3305050150 |
Directory | /workspace/44.prim_prince_test/latest |
Test location | /workspace/coverage/default/440.prim_prince_test.3445054596 |
Short name | T447 |
Test name | |
Test status | |
Simulation time | 782922320 ps |
CPU time | 12.93 seconds |
Started | Aug 17 04:24:56 PM PDT 24 |
Finished | Aug 17 04:25:11 PM PDT 24 |
Peak memory | 145444 kb |
Host | smart-fef240cb-2fe9-462a-bf4d-6b29a8eb20e8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3445054596 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 440.prim_prince_test.3445054596 |
Directory | /workspace/440.prim_prince_test/latest |
Test location | /workspace/coverage/default/441.prim_prince_test.48496594 |
Short name | T315 |
Test name | |
Test status | |
Simulation time | 870611994 ps |
CPU time | 14.19 seconds |
Started | Aug 17 04:24:56 PM PDT 24 |
Finished | Aug 17 04:25:13 PM PDT 24 |
Peak memory | 145316 kb |
Host | smart-5f3f41b7-3a69-46b5-815c-82af401237e4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=48496594 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 441.prim_prince_test.48496594 |
Directory | /workspace/441.prim_prince_test/latest |
Test location | /workspace/coverage/default/442.prim_prince_test.2027680723 |
Short name | T62 |
Test name | |
Test status | |
Simulation time | 1033648391 ps |
CPU time | 17.96 seconds |
Started | Aug 17 04:23:47 PM PDT 24 |
Finished | Aug 17 04:24:09 PM PDT 24 |
Peak memory | 146576 kb |
Host | smart-5ccee976-c4fe-432a-a521-773ba403e3fe |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2027680723 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 442.prim_prince_test.2027680723 |
Directory | /workspace/442.prim_prince_test/latest |
Test location | /workspace/coverage/default/443.prim_prince_test.2170840283 |
Short name | T235 |
Test name | |
Test status | |
Simulation time | 2329842138 ps |
CPU time | 37.75 seconds |
Started | Aug 17 04:25:39 PM PDT 24 |
Finished | Aug 17 04:26:24 PM PDT 24 |
Peak memory | 146196 kb |
Host | smart-eaae1ade-75bf-42d3-8c4a-972bf337affe |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2170840283 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 443.prim_prince_test.2170840283 |
Directory | /workspace/443.prim_prince_test/latest |
Test location | /workspace/coverage/default/444.prim_prince_test.452406577 |
Short name | T500 |
Test name | |
Test status | |
Simulation time | 2490230912 ps |
CPU time | 40.24 seconds |
Started | Aug 17 04:25:07 PM PDT 24 |
Finished | Aug 17 04:25:55 PM PDT 24 |
Peak memory | 146212 kb |
Host | smart-7b63515c-edf0-4897-9d02-67c8be0e44f1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=452406577 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 444.prim_prince_test.452406577 |
Directory | /workspace/444.prim_prince_test/latest |
Test location | /workspace/coverage/default/445.prim_prince_test.3729501395 |
Short name | T335 |
Test name | |
Test status | |
Simulation time | 879261597 ps |
CPU time | 14.27 seconds |
Started | Aug 17 04:25:40 PM PDT 24 |
Finished | Aug 17 04:25:57 PM PDT 24 |
Peak memory | 146132 kb |
Host | smart-40be32b4-9f75-4484-95f7-9ec77b941d2b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3729501395 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 445.prim_prince_test.3729501395 |
Directory | /workspace/445.prim_prince_test/latest |
Test location | /workspace/coverage/default/446.prim_prince_test.1384467656 |
Short name | T432 |
Test name | |
Test status | |
Simulation time | 2952976693 ps |
CPU time | 47.3 seconds |
Started | Aug 17 04:25:34 PM PDT 24 |
Finished | Aug 17 04:26:31 PM PDT 24 |
Peak memory | 146196 kb |
Host | smart-02b869c0-cfd7-4e78-9416-442abe41b328 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1384467656 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 446.prim_prince_test.1384467656 |
Directory | /workspace/446.prim_prince_test/latest |
Test location | /workspace/coverage/default/447.prim_prince_test.3582497451 |
Short name | T352 |
Test name | |
Test status | |
Simulation time | 1579350752 ps |
CPU time | 26.06 seconds |
Started | Aug 17 04:25:06 PM PDT 24 |
Finished | Aug 17 04:25:37 PM PDT 24 |
Peak memory | 146144 kb |
Host | smart-e67a9b75-acbd-47a6-996e-1333fdc931a2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3582497451 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 447.prim_prince_test.3582497451 |
Directory | /workspace/447.prim_prince_test/latest |
Test location | /workspace/coverage/default/448.prim_prince_test.2994490852 |
Short name | T22 |
Test name | |
Test status | |
Simulation time | 2221803793 ps |
CPU time | 36.12 seconds |
Started | Aug 17 04:25:06 PM PDT 24 |
Finished | Aug 17 04:25:49 PM PDT 24 |
Peak memory | 145916 kb |
Host | smart-4a048b63-d0cd-4dcd-88c0-10c32c099598 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2994490852 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 448.prim_prince_test.2994490852 |
Directory | /workspace/448.prim_prince_test/latest |
Test location | /workspace/coverage/default/449.prim_prince_test.443050509 |
Short name | T487 |
Test name | |
Test status | |
Simulation time | 894827809 ps |
CPU time | 14.52 seconds |
Started | Aug 17 04:24:56 PM PDT 24 |
Finished | Aug 17 04:25:13 PM PDT 24 |
Peak memory | 146184 kb |
Host | smart-0dfe7114-6e28-40dd-84c7-aeb291e919fe |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=443050509 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 449.prim_prince_test.443050509 |
Directory | /workspace/449.prim_prince_test/latest |
Test location | /workspace/coverage/default/45.prim_prince_test.3273330172 |
Short name | T88 |
Test name | |
Test status | |
Simulation time | 2377533093 ps |
CPU time | 38.26 seconds |
Started | Aug 17 04:20:26 PM PDT 24 |
Finished | Aug 17 04:21:11 PM PDT 24 |
Peak memory | 145500 kb |
Host | smart-62b15657-fef0-4d1b-9a22-f74d770bd4a0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3273330172 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_prince_test.3273330172 |
Directory | /workspace/45.prim_prince_test/latest |
Test location | /workspace/coverage/default/450.prim_prince_test.2257330778 |
Short name | T383 |
Test name | |
Test status | |
Simulation time | 1095989039 ps |
CPU time | 18.15 seconds |
Started | Aug 17 04:25:07 PM PDT 24 |
Finished | Aug 17 04:25:29 PM PDT 24 |
Peak memory | 146144 kb |
Host | smart-24869251-b352-4bd2-9bf4-6046da1b5f81 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2257330778 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 450.prim_prince_test.2257330778 |
Directory | /workspace/450.prim_prince_test/latest |
Test location | /workspace/coverage/default/451.prim_prince_test.2769318850 |
Short name | T413 |
Test name | |
Test status | |
Simulation time | 2405876832 ps |
CPU time | 39.18 seconds |
Started | Aug 17 04:25:39 PM PDT 24 |
Finished | Aug 17 04:26:26 PM PDT 24 |
Peak memory | 146196 kb |
Host | smart-a7b84209-79cf-40fa-9835-5c5602cf32a0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2769318850 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 451.prim_prince_test.2769318850 |
Directory | /workspace/451.prim_prince_test/latest |
Test location | /workspace/coverage/default/452.prim_prince_test.4165266486 |
Short name | T486 |
Test name | |
Test status | |
Simulation time | 2803360089 ps |
CPU time | 47.01 seconds |
Started | Aug 17 04:23:48 PM PDT 24 |
Finished | Aug 17 04:24:44 PM PDT 24 |
Peak memory | 146656 kb |
Host | smart-5372c6bc-5784-421c-89e5-5fcebcd016ad |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4165266486 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 452.prim_prince_test.4165266486 |
Directory | /workspace/452.prim_prince_test/latest |
Test location | /workspace/coverage/default/453.prim_prince_test.1536674365 |
Short name | T52 |
Test name | |
Test status | |
Simulation time | 3755578618 ps |
CPU time | 60.25 seconds |
Started | Aug 17 04:25:39 PM PDT 24 |
Finished | Aug 17 04:26:51 PM PDT 24 |
Peak memory | 146196 kb |
Host | smart-529ee1ca-829e-48d1-9651-72e46730bd65 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1536674365 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 453.prim_prince_test.1536674365 |
Directory | /workspace/453.prim_prince_test/latest |
Test location | /workspace/coverage/default/454.prim_prince_test.2031458429 |
Short name | T271 |
Test name | |
Test status | |
Simulation time | 1825864890 ps |
CPU time | 29.92 seconds |
Started | Aug 17 04:25:06 PM PDT 24 |
Finished | Aug 17 04:25:42 PM PDT 24 |
Peak memory | 146144 kb |
Host | smart-b1abb31f-300b-4987-bdba-59cf4d4a122f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2031458429 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 454.prim_prince_test.2031458429 |
Directory | /workspace/454.prim_prince_test/latest |
Test location | /workspace/coverage/default/455.prim_prince_test.2445129310 |
Short name | T83 |
Test name | |
Test status | |
Simulation time | 2769219428 ps |
CPU time | 47.26 seconds |
Started | Aug 17 04:23:46 PM PDT 24 |
Finished | Aug 17 04:24:45 PM PDT 24 |
Peak memory | 146644 kb |
Host | smart-1f0d65e5-f957-4595-b329-884a146d98bd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2445129310 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 455.prim_prince_test.2445129310 |
Directory | /workspace/455.prim_prince_test/latest |
Test location | /workspace/coverage/default/456.prim_prince_test.4126886916 |
Short name | T421 |
Test name | |
Test status | |
Simulation time | 894703597 ps |
CPU time | 14.59 seconds |
Started | Aug 17 04:25:06 PM PDT 24 |
Finished | Aug 17 04:25:23 PM PDT 24 |
Peak memory | 146144 kb |
Host | smart-621b0766-61ac-4476-a6e6-06029cd40209 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4126886916 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 456.prim_prince_test.4126886916 |
Directory | /workspace/456.prim_prince_test/latest |
Test location | /workspace/coverage/default/457.prim_prince_test.1848485478 |
Short name | T6 |
Test name | |
Test status | |
Simulation time | 3444739102 ps |
CPU time | 55.77 seconds |
Started | Aug 17 04:25:06 PM PDT 24 |
Finished | Aug 17 04:26:13 PM PDT 24 |
Peak memory | 146208 kb |
Host | smart-0bf20f6e-602f-4c2f-93b8-04c9400c5da4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1848485478 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 457.prim_prince_test.1848485478 |
Directory | /workspace/457.prim_prince_test/latest |
Test location | /workspace/coverage/default/458.prim_prince_test.3367440380 |
Short name | T460 |
Test name | |
Test status | |
Simulation time | 2287983650 ps |
CPU time | 37.34 seconds |
Started | Aug 17 04:25:39 PM PDT 24 |
Finished | Aug 17 04:26:24 PM PDT 24 |
Peak memory | 146108 kb |
Host | smart-f3e67e1a-54af-4cf9-8cc7-cef10b3686f4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3367440380 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 458.prim_prince_test.3367440380 |
Directory | /workspace/458.prim_prince_test/latest |
Test location | /workspace/coverage/default/459.prim_prince_test.1414599133 |
Short name | T253 |
Test name | |
Test status | |
Simulation time | 2709336802 ps |
CPU time | 45.26 seconds |
Started | Aug 17 04:23:57 PM PDT 24 |
Finished | Aug 17 04:24:51 PM PDT 24 |
Peak memory | 146656 kb |
Host | smart-c797a28d-0fa3-48f8-ac02-a04492029ccf |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1414599133 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 459.prim_prince_test.1414599133 |
Directory | /workspace/459.prim_prince_test/latest |
Test location | /workspace/coverage/default/46.prim_prince_test.200869370 |
Short name | T127 |
Test name | |
Test status | |
Simulation time | 3386400566 ps |
CPU time | 56.53 seconds |
Started | Aug 17 04:20:25 PM PDT 24 |
Finished | Aug 17 04:21:33 PM PDT 24 |
Peak memory | 145216 kb |
Host | smart-9341bfe1-912d-49c2-a036-fa7421e292cb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=200869370 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_prince_test.200869370 |
Directory | /workspace/46.prim_prince_test/latest |
Test location | /workspace/coverage/default/460.prim_prince_test.1785339439 |
Short name | T101 |
Test name | |
Test status | |
Simulation time | 1663452537 ps |
CPU time | 27.29 seconds |
Started | Aug 17 04:23:56 PM PDT 24 |
Finished | Aug 17 04:24:29 PM PDT 24 |
Peak memory | 146512 kb |
Host | smart-e745b895-ae77-470d-9313-7d0809830177 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1785339439 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 460.prim_prince_test.1785339439 |
Directory | /workspace/460.prim_prince_test/latest |
Test location | /workspace/coverage/default/461.prim_prince_test.2744713523 |
Short name | T419 |
Test name | |
Test status | |
Simulation time | 2524230895 ps |
CPU time | 40.37 seconds |
Started | Aug 17 04:23:58 PM PDT 24 |
Finished | Aug 17 04:24:46 PM PDT 24 |
Peak memory | 146576 kb |
Host | smart-633aa6e7-26c8-4b2b-9510-b6abd8179b93 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2744713523 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 461.prim_prince_test.2744713523 |
Directory | /workspace/461.prim_prince_test/latest |
Test location | /workspace/coverage/default/462.prim_prince_test.1886872131 |
Short name | T251 |
Test name | |
Test status | |
Simulation time | 875767546 ps |
CPU time | 15.05 seconds |
Started | Aug 17 04:24:04 PM PDT 24 |
Finished | Aug 17 04:24:22 PM PDT 24 |
Peak memory | 146584 kb |
Host | smart-a63117cb-91bb-488e-92f8-6adfe9c9e69f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1886872131 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 462.prim_prince_test.1886872131 |
Directory | /workspace/462.prim_prince_test/latest |
Test location | /workspace/coverage/default/463.prim_prince_test.3164301459 |
Short name | T300 |
Test name | |
Test status | |
Simulation time | 2651257183 ps |
CPU time | 44.87 seconds |
Started | Aug 17 04:24:00 PM PDT 24 |
Finished | Aug 17 04:24:55 PM PDT 24 |
Peak memory | 146384 kb |
Host | smart-d36c041b-9a28-49dd-9020-9827149ae17f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3164301459 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 463.prim_prince_test.3164301459 |
Directory | /workspace/463.prim_prince_test/latest |
Test location | /workspace/coverage/default/464.prim_prince_test.701435289 |
Short name | T143 |
Test name | |
Test status | |
Simulation time | 1896921170 ps |
CPU time | 32.83 seconds |
Started | Aug 17 04:23:57 PM PDT 24 |
Finished | Aug 17 04:24:37 PM PDT 24 |
Peak memory | 146572 kb |
Host | smart-21c08b1c-ca59-4158-8c26-2023505584ef |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=701435289 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 464.prim_prince_test.701435289 |
Directory | /workspace/464.prim_prince_test/latest |
Test location | /workspace/coverage/default/465.prim_prince_test.1516949163 |
Short name | T72 |
Test name | |
Test status | |
Simulation time | 1056811058 ps |
CPU time | 17.93 seconds |
Started | Aug 17 04:23:58 PM PDT 24 |
Finished | Aug 17 04:24:19 PM PDT 24 |
Peak memory | 146508 kb |
Host | smart-af2fe9ea-7f0c-412e-b0bc-8de9eb1cdddb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1516949163 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 465.prim_prince_test.1516949163 |
Directory | /workspace/465.prim_prince_test/latest |
Test location | /workspace/coverage/default/466.prim_prince_test.2854311801 |
Short name | T212 |
Test name | |
Test status | |
Simulation time | 2127868018 ps |
CPU time | 35.55 seconds |
Started | Aug 17 04:23:58 PM PDT 24 |
Finished | Aug 17 04:24:41 PM PDT 24 |
Peak memory | 146508 kb |
Host | smart-7e35de46-d0b3-4606-9c3c-b02aaaec6963 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2854311801 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 466.prim_prince_test.2854311801 |
Directory | /workspace/466.prim_prince_test/latest |
Test location | /workspace/coverage/default/467.prim_prince_test.1748822778 |
Short name | T451 |
Test name | |
Test status | |
Simulation time | 1569132958 ps |
CPU time | 26.01 seconds |
Started | Aug 17 04:23:55 PM PDT 24 |
Finished | Aug 17 04:24:27 PM PDT 24 |
Peak memory | 146564 kb |
Host | smart-7ae67c4d-c614-4ebe-a0d1-e5ea30d6b58e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1748822778 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 467.prim_prince_test.1748822778 |
Directory | /workspace/467.prim_prince_test/latest |
Test location | /workspace/coverage/default/468.prim_prince_test.909825171 |
Short name | T373 |
Test name | |
Test status | |
Simulation time | 1699043155 ps |
CPU time | 28.22 seconds |
Started | Aug 17 04:23:58 PM PDT 24 |
Finished | Aug 17 04:24:32 PM PDT 24 |
Peak memory | 146516 kb |
Host | smart-bbfa8c07-52b6-422f-a04d-b40d33fea1b9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=909825171 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 468.prim_prince_test.909825171 |
Directory | /workspace/468.prim_prince_test/latest |
Test location | /workspace/coverage/default/469.prim_prince_test.1169909852 |
Short name | T344 |
Test name | |
Test status | |
Simulation time | 2975560271 ps |
CPU time | 50.17 seconds |
Started | Aug 17 04:23:59 PM PDT 24 |
Finished | Aug 17 04:25:00 PM PDT 24 |
Peak memory | 146640 kb |
Host | smart-7b3be312-3012-485a-af3c-c5e6acdd63de |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1169909852 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 469.prim_prince_test.1169909852 |
Directory | /workspace/469.prim_prince_test/latest |
Test location | /workspace/coverage/default/47.prim_prince_test.4286345767 |
Short name | T76 |
Test name | |
Test status | |
Simulation time | 1773179753 ps |
CPU time | 30.32 seconds |
Started | Aug 17 04:21:40 PM PDT 24 |
Finished | Aug 17 04:22:17 PM PDT 24 |
Peak memory | 146368 kb |
Host | smart-52158fc2-0899-4e81-9d8d-f6d6428749a0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4286345767 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_prince_test.4286345767 |
Directory | /workspace/47.prim_prince_test/latest |
Test location | /workspace/coverage/default/470.prim_prince_test.645665444 |
Short name | T317 |
Test name | |
Test status | |
Simulation time | 2181252885 ps |
CPU time | 36.89 seconds |
Started | Aug 17 04:24:05 PM PDT 24 |
Finished | Aug 17 04:24:50 PM PDT 24 |
Peak memory | 146652 kb |
Host | smart-c0019f3a-9f26-4e87-8a77-0e2da947859e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=645665444 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 470.prim_prince_test.645665444 |
Directory | /workspace/470.prim_prince_test/latest |
Test location | /workspace/coverage/default/471.prim_prince_test.2515504487 |
Short name | T313 |
Test name | |
Test status | |
Simulation time | 2476801249 ps |
CPU time | 42.92 seconds |
Started | Aug 17 04:23:59 PM PDT 24 |
Finished | Aug 17 04:24:52 PM PDT 24 |
Peak memory | 146632 kb |
Host | smart-f986a928-150b-4c01-9377-c35237e833ad |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2515504487 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 471.prim_prince_test.2515504487 |
Directory | /workspace/471.prim_prince_test/latest |
Test location | /workspace/coverage/default/472.prim_prince_test.333513735 |
Short name | T38 |
Test name | |
Test status | |
Simulation time | 3242035421 ps |
CPU time | 56 seconds |
Started | Aug 17 04:24:09 PM PDT 24 |
Finished | Aug 17 04:25:18 PM PDT 24 |
Peak memory | 146636 kb |
Host | smart-c748fd21-0551-4251-9e21-b77f82952106 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=333513735 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 472.prim_prince_test.333513735 |
Directory | /workspace/472.prim_prince_test/latest |
Test location | /workspace/coverage/default/473.prim_prince_test.3513605229 |
Short name | T182 |
Test name | |
Test status | |
Simulation time | 2553686533 ps |
CPU time | 40.56 seconds |
Started | Aug 17 04:25:52 PM PDT 24 |
Finished | Aug 17 04:26:40 PM PDT 24 |
Peak memory | 146212 kb |
Host | smart-35225760-909e-4198-bf02-a0aa0fd0fcab |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3513605229 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 473.prim_prince_test.3513605229 |
Directory | /workspace/473.prim_prince_test/latest |
Test location | /workspace/coverage/default/474.prim_prince_test.3413727359 |
Short name | T226 |
Test name | |
Test status | |
Simulation time | 1528191042 ps |
CPU time | 25.8 seconds |
Started | Aug 17 04:26:15 PM PDT 24 |
Finished | Aug 17 04:26:46 PM PDT 24 |
Peak memory | 146136 kb |
Host | smart-882edaea-036b-48f7-80ee-9a34c52fd4b9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3413727359 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 474.prim_prince_test.3413727359 |
Directory | /workspace/474.prim_prince_test/latest |
Test location | /workspace/coverage/default/475.prim_prince_test.3590689087 |
Short name | T229 |
Test name | |
Test status | |
Simulation time | 3644120866 ps |
CPU time | 59.67 seconds |
Started | Aug 17 04:25:24 PM PDT 24 |
Finished | Aug 17 04:26:36 PM PDT 24 |
Peak memory | 146160 kb |
Host | smart-c4f8c9f2-b4eb-46ce-a64f-85ee00144f43 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3590689087 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 475.prim_prince_test.3590689087 |
Directory | /workspace/475.prim_prince_test/latest |
Test location | /workspace/coverage/default/476.prim_prince_test.2405160430 |
Short name | T80 |
Test name | |
Test status | |
Simulation time | 2769609826 ps |
CPU time | 43.31 seconds |
Started | Aug 17 04:25:40 PM PDT 24 |
Finished | Aug 17 04:26:31 PM PDT 24 |
Peak memory | 146032 kb |
Host | smart-4d685a19-46a7-43f5-af22-71db2f1ba4bb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2405160430 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 476.prim_prince_test.2405160430 |
Directory | /workspace/476.prim_prince_test/latest |
Test location | /workspace/coverage/default/477.prim_prince_test.1286566897 |
Short name | T81 |
Test name | |
Test status | |
Simulation time | 2260481666 ps |
CPU time | 37.46 seconds |
Started | Aug 17 04:25:12 PM PDT 24 |
Finished | Aug 17 04:25:58 PM PDT 24 |
Peak memory | 144452 kb |
Host | smart-79d77b01-d394-43f4-99cd-57420dec40fc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1286566897 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 477.prim_prince_test.1286566897 |
Directory | /workspace/477.prim_prince_test/latest |
Test location | /workspace/coverage/default/478.prim_prince_test.779650098 |
Short name | T234 |
Test name | |
Test status | |
Simulation time | 2093540951 ps |
CPU time | 36.24 seconds |
Started | Aug 17 04:24:09 PM PDT 24 |
Finished | Aug 17 04:24:54 PM PDT 24 |
Peak memory | 146580 kb |
Host | smart-bc79fee3-8d1c-4f10-9658-15c1fb079905 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=779650098 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 478.prim_prince_test.779650098 |
Directory | /workspace/478.prim_prince_test/latest |
Test location | /workspace/coverage/default/479.prim_prince_test.3092438016 |
Short name | T283 |
Test name | |
Test status | |
Simulation time | 1622339966 ps |
CPU time | 27.02 seconds |
Started | Aug 17 04:24:31 PM PDT 24 |
Finished | Aug 17 04:25:04 PM PDT 24 |
Peak memory | 146452 kb |
Host | smart-dcc843a9-c3cb-4b88-abe7-185d71ce64e2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3092438016 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 479.prim_prince_test.3092438016 |
Directory | /workspace/479.prim_prince_test/latest |
Test location | /workspace/coverage/default/48.prim_prince_test.3437677096 |
Short name | T176 |
Test name | |
Test status | |
Simulation time | 3709703731 ps |
CPU time | 61.85 seconds |
Started | Aug 17 04:20:27 PM PDT 24 |
Finished | Aug 17 04:21:41 PM PDT 24 |
Peak memory | 146208 kb |
Host | smart-05f20bd9-f3c4-4594-bf2c-ed93c096e7e0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3437677096 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_prince_test.3437677096 |
Directory | /workspace/48.prim_prince_test/latest |
Test location | /workspace/coverage/default/480.prim_prince_test.1799577238 |
Short name | T70 |
Test name | |
Test status | |
Simulation time | 3687230719 ps |
CPU time | 60.6 seconds |
Started | Aug 17 04:25:12 PM PDT 24 |
Finished | Aug 17 04:26:25 PM PDT 24 |
Peak memory | 145052 kb |
Host | smart-a841b283-1ce6-4c54-aadc-ffdf4f17159c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1799577238 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 480.prim_prince_test.1799577238 |
Directory | /workspace/480.prim_prince_test/latest |
Test location | /workspace/coverage/default/481.prim_prince_test.961384744 |
Short name | T465 |
Test name | |
Test status | |
Simulation time | 2911930963 ps |
CPU time | 47.55 seconds |
Started | Aug 17 04:25:12 PM PDT 24 |
Finished | Aug 17 04:26:10 PM PDT 24 |
Peak memory | 144040 kb |
Host | smart-d6c746db-c291-4c4a-bbcc-7c74cfde6af4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=961384744 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 481.prim_prince_test.961384744 |
Directory | /workspace/481.prim_prince_test/latest |
Test location | /workspace/coverage/default/482.prim_prince_test.1123436602 |
Short name | T350 |
Test name | |
Test status | |
Simulation time | 855571473 ps |
CPU time | 14.33 seconds |
Started | Aug 17 04:26:14 PM PDT 24 |
Finished | Aug 17 04:26:32 PM PDT 24 |
Peak memory | 146136 kb |
Host | smart-27cea911-9498-4375-a162-15a16018a07d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1123436602 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 482.prim_prince_test.1123436602 |
Directory | /workspace/482.prim_prince_test/latest |
Test location | /workspace/coverage/default/483.prim_prince_test.611845508 |
Short name | T233 |
Test name | |
Test status | |
Simulation time | 3384607279 ps |
CPU time | 55.91 seconds |
Started | Aug 17 04:25:12 PM PDT 24 |
Finished | Aug 17 04:26:20 PM PDT 24 |
Peak memory | 143908 kb |
Host | smart-b8c301a8-1529-4824-b36a-fb69486100da |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=611845508 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 483.prim_prince_test.611845508 |
Directory | /workspace/483.prim_prince_test/latest |
Test location | /workspace/coverage/default/484.prim_prince_test.2506457071 |
Short name | T37 |
Test name | |
Test status | |
Simulation time | 3690526519 ps |
CPU time | 60.3 seconds |
Started | Aug 17 04:25:24 PM PDT 24 |
Finished | Aug 17 04:26:37 PM PDT 24 |
Peak memory | 146160 kb |
Host | smart-edea9ed5-13d1-4fd9-b395-749b131aead4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2506457071 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 484.prim_prince_test.2506457071 |
Directory | /workspace/484.prim_prince_test/latest |
Test location | /workspace/coverage/default/485.prim_prince_test.945539960 |
Short name | T59 |
Test name | |
Test status | |
Simulation time | 2135206823 ps |
CPU time | 34.92 seconds |
Started | Aug 17 04:25:12 PM PDT 24 |
Finished | Aug 17 04:25:55 PM PDT 24 |
Peak memory | 144048 kb |
Host | smart-9ad1c925-5624-4998-8461-7b76332ca7c8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=945539960 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 485.prim_prince_test.945539960 |
Directory | /workspace/485.prim_prince_test/latest |
Test location | /workspace/coverage/default/486.prim_prince_test.1575608742 |
Short name | T485 |
Test name | |
Test status | |
Simulation time | 3035294321 ps |
CPU time | 49.88 seconds |
Started | Aug 17 04:26:04 PM PDT 24 |
Finished | Aug 17 04:27:05 PM PDT 24 |
Peak memory | 145052 kb |
Host | smart-c77f3185-6626-494c-b105-9ad3bd9c8b3c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1575608742 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 486.prim_prince_test.1575608742 |
Directory | /workspace/486.prim_prince_test/latest |
Test location | /workspace/coverage/default/487.prim_prince_test.3491555253 |
Short name | T288 |
Test name | |
Test status | |
Simulation time | 1495865731 ps |
CPU time | 25.17 seconds |
Started | Aug 17 04:24:10 PM PDT 24 |
Finished | Aug 17 04:24:41 PM PDT 24 |
Peak memory | 146564 kb |
Host | smart-37a4a3e4-25ab-430c-b7f0-b0a7af440244 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3491555253 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 487.prim_prince_test.3491555253 |
Directory | /workspace/487.prim_prince_test/latest |
Test location | /workspace/coverage/default/488.prim_prince_test.658626025 |
Short name | T382 |
Test name | |
Test status | |
Simulation time | 810572971 ps |
CPU time | 13.52 seconds |
Started | Aug 17 04:26:13 PM PDT 24 |
Finished | Aug 17 04:26:30 PM PDT 24 |
Peak memory | 146144 kb |
Host | smart-98a4b373-aba9-47cc-8a34-4bd56e33738e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=658626025 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 488.prim_prince_test.658626025 |
Directory | /workspace/488.prim_prince_test/latest |
Test location | /workspace/coverage/default/489.prim_prince_test.2654856877 |
Short name | T458 |
Test name | |
Test status | |
Simulation time | 1197018439 ps |
CPU time | 20.05 seconds |
Started | Aug 17 04:26:14 PM PDT 24 |
Finished | Aug 17 04:26:39 PM PDT 24 |
Peak memory | 146136 kb |
Host | smart-6144c60c-c118-422b-b912-1c3a5ec3a3cd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2654856877 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 489.prim_prince_test.2654856877 |
Directory | /workspace/489.prim_prince_test/latest |
Test location | /workspace/coverage/default/49.prim_prince_test.571428968 |
Short name | T205 |
Test name | |
Test status | |
Simulation time | 1314296721 ps |
CPU time | 21.93 seconds |
Started | Aug 17 04:20:26 PM PDT 24 |
Finished | Aug 17 04:20:53 PM PDT 24 |
Peak memory | 145268 kb |
Host | smart-419c6eba-743d-4304-9d29-4e6a73835285 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=571428968 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_prince_test.571428968 |
Directory | /workspace/49.prim_prince_test/latest |
Test location | /workspace/coverage/default/490.prim_prince_test.3061597023 |
Short name | T346 |
Test name | |
Test status | |
Simulation time | 2623425234 ps |
CPU time | 45.42 seconds |
Started | Aug 17 04:24:10 PM PDT 24 |
Finished | Aug 17 04:25:06 PM PDT 24 |
Peak memory | 146644 kb |
Host | smart-074043f6-d65b-4d1b-9ee6-098c58211913 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3061597023 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 490.prim_prince_test.3061597023 |
Directory | /workspace/490.prim_prince_test/latest |
Test location | /workspace/coverage/default/491.prim_prince_test.36501131 |
Short name | T444 |
Test name | |
Test status | |
Simulation time | 947540042 ps |
CPU time | 15.85 seconds |
Started | Aug 17 04:26:04 PM PDT 24 |
Finished | Aug 17 04:26:24 PM PDT 24 |
Peak memory | 145604 kb |
Host | smart-01e91ce0-0b94-4043-a8e8-443922a32e6e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=36501131 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 491.prim_prince_test.36501131 |
Directory | /workspace/491.prim_prince_test/latest |
Test location | /workspace/coverage/default/492.prim_prince_test.275501011 |
Short name | T257 |
Test name | |
Test status | |
Simulation time | 3519940446 ps |
CPU time | 59.2 seconds |
Started | Aug 17 04:24:09 PM PDT 24 |
Finished | Aug 17 04:25:22 PM PDT 24 |
Peak memory | 146636 kb |
Host | smart-1dbac52e-7bcb-4571-acc2-a6f2b46d2b7a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=275501011 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 492.prim_prince_test.275501011 |
Directory | /workspace/492.prim_prince_test/latest |
Test location | /workspace/coverage/default/493.prim_prince_test.83549221 |
Short name | T396 |
Test name | |
Test status | |
Simulation time | 3130309372 ps |
CPU time | 52.57 seconds |
Started | Aug 17 04:24:10 PM PDT 24 |
Finished | Aug 17 04:25:14 PM PDT 24 |
Peak memory | 146608 kb |
Host | smart-d4fea602-406d-4937-bf98-46be52671c1f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=83549221 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 493.prim_prince_test.83549221 |
Directory | /workspace/493.prim_prince_test/latest |
Test location | /workspace/coverage/default/494.prim_prince_test.4252929002 |
Short name | T339 |
Test name | |
Test status | |
Simulation time | 3142711313 ps |
CPU time | 52.55 seconds |
Started | Aug 17 04:24:12 PM PDT 24 |
Finished | Aug 17 04:25:16 PM PDT 24 |
Peak memory | 146648 kb |
Host | smart-5bc7d11e-9f18-4eb8-9585-b444a3e2cbdb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4252929002 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 494.prim_prince_test.4252929002 |
Directory | /workspace/494.prim_prince_test/latest |
Test location | /workspace/coverage/default/495.prim_prince_test.3570374515 |
Short name | T390 |
Test name | |
Test status | |
Simulation time | 2617294307 ps |
CPU time | 45.5 seconds |
Started | Aug 17 04:24:09 PM PDT 24 |
Finished | Aug 17 04:25:05 PM PDT 24 |
Peak memory | 146488 kb |
Host | smart-c0f74ba1-f685-49ab-8367-da61f24073bf |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3570374515 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 495.prim_prince_test.3570374515 |
Directory | /workspace/495.prim_prince_test/latest |
Test location | /workspace/coverage/default/496.prim_prince_test.506502789 |
Short name | T107 |
Test name | |
Test status | |
Simulation time | 2853566684 ps |
CPU time | 46.77 seconds |
Started | Aug 17 04:26:15 PM PDT 24 |
Finished | Aug 17 04:27:11 PM PDT 24 |
Peak memory | 146208 kb |
Host | smart-8ce27b90-b899-4c75-8feb-d0f5561ec43c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=506502789 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 496.prim_prince_test.506502789 |
Directory | /workspace/496.prim_prince_test/latest |
Test location | /workspace/coverage/default/497.prim_prince_test.1383794210 |
Short name | T103 |
Test name | |
Test status | |
Simulation time | 2670088464 ps |
CPU time | 44.43 seconds |
Started | Aug 17 04:26:04 PM PDT 24 |
Finished | Aug 17 04:26:59 PM PDT 24 |
Peak memory | 145444 kb |
Host | smart-51b0c6e0-fe2d-490d-aef3-3db096863615 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1383794210 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 497.prim_prince_test.1383794210 |
Directory | /workspace/497.prim_prince_test/latest |
Test location | /workspace/coverage/default/498.prim_prince_test.1074975244 |
Short name | T198 |
Test name | |
Test status | |
Simulation time | 1335373731 ps |
CPU time | 23.05 seconds |
Started | Aug 17 04:24:24 PM PDT 24 |
Finished | Aug 17 04:24:52 PM PDT 24 |
Peak memory | 146836 kb |
Host | smart-1deadea2-8460-416f-8dc9-331109519b50 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1074975244 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 498.prim_prince_test.1074975244 |
Directory | /workspace/498.prim_prince_test/latest |
Test location | /workspace/coverage/default/499.prim_prince_test.304738015 |
Short name | T264 |
Test name | |
Test status | |
Simulation time | 3545449856 ps |
CPU time | 56.99 seconds |
Started | Aug 17 04:26:14 PM PDT 24 |
Finished | Aug 17 04:27:22 PM PDT 24 |
Peak memory | 146208 kb |
Host | smart-f97a0d8a-10de-4d9d-bf2a-5a0d574a87ff |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=304738015 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 499.prim_prince_test.304738015 |
Directory | /workspace/499.prim_prince_test/latest |
Test location | /workspace/coverage/default/5.prim_prince_test.3901596615 |
Short name | T482 |
Test name | |
Test status | |
Simulation time | 3282199674 ps |
CPU time | 55.31 seconds |
Started | Aug 17 04:20:26 PM PDT 24 |
Finished | Aug 17 04:21:33 PM PDT 24 |
Peak memory | 146132 kb |
Host | smart-cbca33ab-768a-4864-8a0b-dbaffd58ea1c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3901596615 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_prince_test.3901596615 |
Directory | /workspace/5.prim_prince_test/latest |
Test location | /workspace/coverage/default/50.prim_prince_test.2403823419 |
Short name | T246 |
Test name | |
Test status | |
Simulation time | 2984138160 ps |
CPU time | 48.62 seconds |
Started | Aug 17 04:20:26 PM PDT 24 |
Finished | Aug 17 04:21:25 PM PDT 24 |
Peak memory | 146900 kb |
Host | smart-47035066-9429-47ce-ba61-2a7fb264d90d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2403823419 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 50.prim_prince_test.2403823419 |
Directory | /workspace/50.prim_prince_test/latest |
Test location | /workspace/coverage/default/51.prim_prince_test.1877911458 |
Short name | T294 |
Test name | |
Test status | |
Simulation time | 3208990635 ps |
CPU time | 53.46 seconds |
Started | Aug 17 04:20:26 PM PDT 24 |
Finished | Aug 17 04:21:31 PM PDT 24 |
Peak memory | 144992 kb |
Host | smart-1752195c-7dcf-464e-be81-775d1216dd13 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1877911458 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 51.prim_prince_test.1877911458 |
Directory | /workspace/51.prim_prince_test/latest |
Test location | /workspace/coverage/default/52.prim_prince_test.859173327 |
Short name | T269 |
Test name | |
Test status | |
Simulation time | 1758543566 ps |
CPU time | 29.83 seconds |
Started | Aug 17 04:20:26 PM PDT 24 |
Finished | Aug 17 04:21:02 PM PDT 24 |
Peak memory | 146092 kb |
Host | smart-4851dbfb-ee15-4df3-b72b-7ad22d8f31bd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=859173327 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 52.prim_prince_test.859173327 |
Directory | /workspace/52.prim_prince_test/latest |
Test location | /workspace/coverage/default/53.prim_prince_test.2679614616 |
Short name | T394 |
Test name | |
Test status | |
Simulation time | 1704847237 ps |
CPU time | 28.48 seconds |
Started | Aug 17 04:20:27 PM PDT 24 |
Finished | Aug 17 04:21:01 PM PDT 24 |
Peak memory | 144888 kb |
Host | smart-4dce5b11-e6bd-49c9-9800-baa0127fb75e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2679614616 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 53.prim_prince_test.2679614616 |
Directory | /workspace/53.prim_prince_test/latest |
Test location | /workspace/coverage/default/54.prim_prince_test.3833728010 |
Short name | T3 |
Test name | |
Test status | |
Simulation time | 2027923919 ps |
CPU time | 33.26 seconds |
Started | Aug 17 04:21:28 PM PDT 24 |
Finished | Aug 17 04:22:08 PM PDT 24 |
Peak memory | 146092 kb |
Host | smart-91e64b92-625c-4ffd-93f5-28c8b25626d8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3833728010 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 54.prim_prince_test.3833728010 |
Directory | /workspace/54.prim_prince_test/latest |
Test location | /workspace/coverage/default/55.prim_prince_test.4290532814 |
Short name | T438 |
Test name | |
Test status | |
Simulation time | 2000823843 ps |
CPU time | 32.59 seconds |
Started | Aug 17 04:20:26 PM PDT 24 |
Finished | Aug 17 04:21:05 PM PDT 24 |
Peak memory | 146192 kb |
Host | smart-878a2e10-0292-4ad8-9bc4-f6f83cbc35ef |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4290532814 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 55.prim_prince_test.4290532814 |
Directory | /workspace/55.prim_prince_test/latest |
Test location | /workspace/coverage/default/56.prim_prince_test.3004369211 |
Short name | T297 |
Test name | |
Test status | |
Simulation time | 3686727135 ps |
CPU time | 59.04 seconds |
Started | Aug 17 04:20:26 PM PDT 24 |
Finished | Aug 17 04:21:35 PM PDT 24 |
Peak memory | 146180 kb |
Host | smart-2648ec99-0625-46a8-8b17-9382519eb679 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3004369211 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 56.prim_prince_test.3004369211 |
Directory | /workspace/56.prim_prince_test/latest |
Test location | /workspace/coverage/default/57.prim_prince_test.1215449773 |
Short name | T423 |
Test name | |
Test status | |
Simulation time | 2840624880 ps |
CPU time | 47.76 seconds |
Started | Aug 17 04:20:27 PM PDT 24 |
Finished | Aug 17 04:21:25 PM PDT 24 |
Peak memory | 146364 kb |
Host | smart-691f99cc-4b3a-43ad-83d9-da001be29d28 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1215449773 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 57.prim_prince_test.1215449773 |
Directory | /workspace/57.prim_prince_test/latest |
Test location | /workspace/coverage/default/58.prim_prince_test.2226167657 |
Short name | T354 |
Test name | |
Test status | |
Simulation time | 974353370 ps |
CPU time | 16.6 seconds |
Started | Aug 17 04:20:22 PM PDT 24 |
Finished | Aug 17 04:20:42 PM PDT 24 |
Peak memory | 145300 kb |
Host | smart-8d8878b7-0ed0-4729-8972-9592d59c41b9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2226167657 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 58.prim_prince_test.2226167657 |
Directory | /workspace/58.prim_prince_test/latest |
Test location | /workspace/coverage/default/59.prim_prince_test.3635886047 |
Short name | T26 |
Test name | |
Test status | |
Simulation time | 2447315590 ps |
CPU time | 40.52 seconds |
Started | Aug 17 04:21:27 PM PDT 24 |
Finished | Aug 17 04:22:15 PM PDT 24 |
Peak memory | 144308 kb |
Host | smart-e160eb5d-f105-4cab-9a00-6dbce8267bd5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3635886047 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 59.prim_prince_test.3635886047 |
Directory | /workspace/59.prim_prince_test/latest |
Test location | /workspace/coverage/default/6.prim_prince_test.2014847042 |
Short name | T158 |
Test name | |
Test status | |
Simulation time | 2366754752 ps |
CPU time | 38.66 seconds |
Started | Aug 17 04:20:27 PM PDT 24 |
Finished | Aug 17 04:21:13 PM PDT 24 |
Peak memory | 146236 kb |
Host | smart-86ed4e41-65e0-4b0d-9227-ce4573536c6d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2014847042 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_prince_test.2014847042 |
Directory | /workspace/6.prim_prince_test/latest |
Test location | /workspace/coverage/default/60.prim_prince_test.2217522167 |
Short name | T202 |
Test name | |
Test status | |
Simulation time | 2500137481 ps |
CPU time | 41.12 seconds |
Started | Aug 17 04:21:27 PM PDT 24 |
Finished | Aug 17 04:22:16 PM PDT 24 |
Peak memory | 146064 kb |
Host | smart-7df08843-d716-49bc-8339-b03828e73f92 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2217522167 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 60.prim_prince_test.2217522167 |
Directory | /workspace/60.prim_prince_test/latest |
Test location | /workspace/coverage/default/61.prim_prince_test.352300993 |
Short name | T137 |
Test name | |
Test status | |
Simulation time | 2438558550 ps |
CPU time | 41.43 seconds |
Started | Aug 17 04:20:26 PM PDT 24 |
Finished | Aug 17 04:21:16 PM PDT 24 |
Peak memory | 146900 kb |
Host | smart-74ce707b-56d6-452b-816e-e9246309a9a2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=352300993 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 61.prim_prince_test.352300993 |
Directory | /workspace/61.prim_prince_test/latest |
Test location | /workspace/coverage/default/62.prim_prince_test.124703834 |
Short name | T281 |
Test name | |
Test status | |
Simulation time | 1052570243 ps |
CPU time | 16.87 seconds |
Started | Aug 17 04:21:26 PM PDT 24 |
Finished | Aug 17 04:21:46 PM PDT 24 |
Peak memory | 145064 kb |
Host | smart-986df18f-ec10-43c6-8c40-de8a2b5d5963 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=124703834 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 62.prim_prince_test.124703834 |
Directory | /workspace/62.prim_prince_test/latest |
Test location | /workspace/coverage/default/63.prim_prince_test.799006117 |
Short name | T33 |
Test name | |
Test status | |
Simulation time | 1927420673 ps |
CPU time | 30.99 seconds |
Started | Aug 17 04:21:26 PM PDT 24 |
Finished | Aug 17 04:22:03 PM PDT 24 |
Peak memory | 145016 kb |
Host | smart-bb69a0cb-58ee-4c10-9d96-4e8825278ac5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=799006117 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 63.prim_prince_test.799006117 |
Directory | /workspace/63.prim_prince_test/latest |
Test location | /workspace/coverage/default/64.prim_prince_test.3637011909 |
Short name | T192 |
Test name | |
Test status | |
Simulation time | 1720635144 ps |
CPU time | 28.72 seconds |
Started | Aug 17 04:20:22 PM PDT 24 |
Finished | Aug 17 04:20:57 PM PDT 24 |
Peak memory | 146160 kb |
Host | smart-11686b76-47fb-4545-8ef6-fe500d354515 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3637011909 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 64.prim_prince_test.3637011909 |
Directory | /workspace/64.prim_prince_test/latest |
Test location | /workspace/coverage/default/65.prim_prince_test.4195224986 |
Short name | T307 |
Test name | |
Test status | |
Simulation time | 1648156394 ps |
CPU time | 26.08 seconds |
Started | Aug 17 04:21:34 PM PDT 24 |
Finished | Aug 17 04:22:04 PM PDT 24 |
Peak memory | 145224 kb |
Host | smart-1825cb18-b0ee-4e65-9baf-6386537b734e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4195224986 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 65.prim_prince_test.4195224986 |
Directory | /workspace/65.prim_prince_test/latest |
Test location | /workspace/coverage/default/66.prim_prince_test.2881236381 |
Short name | T86 |
Test name | |
Test status | |
Simulation time | 2512011285 ps |
CPU time | 40.77 seconds |
Started | Aug 17 04:24:48 PM PDT 24 |
Finished | Aug 17 04:25:37 PM PDT 24 |
Peak memory | 144976 kb |
Host | smart-9c81d81a-ac9d-42a7-a000-8190bfd99b99 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2881236381 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 66.prim_prince_test.2881236381 |
Directory | /workspace/66.prim_prince_test/latest |
Test location | /workspace/coverage/default/67.prim_prince_test.272864849 |
Short name | T61 |
Test name | |
Test status | |
Simulation time | 2511913017 ps |
CPU time | 40.79 seconds |
Started | Aug 17 04:24:59 PM PDT 24 |
Finished | Aug 17 04:25:47 PM PDT 24 |
Peak memory | 146172 kb |
Host | smart-5ff2485c-7c88-4ee0-9bfe-5178dda75627 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=272864849 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 67.prim_prince_test.272864849 |
Directory | /workspace/67.prim_prince_test/latest |
Test location | /workspace/coverage/default/68.prim_prince_test.2016251737 |
Short name | T493 |
Test name | |
Test status | |
Simulation time | 1654514517 ps |
CPU time | 27.11 seconds |
Started | Aug 17 04:24:59 PM PDT 24 |
Finished | Aug 17 04:25:31 PM PDT 24 |
Peak memory | 146016 kb |
Host | smart-b5419fab-c48c-414a-9b86-56dac4c907e8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2016251737 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 68.prim_prince_test.2016251737 |
Directory | /workspace/68.prim_prince_test/latest |
Test location | /workspace/coverage/default/69.prim_prince_test.1459136509 |
Short name | T363 |
Test name | |
Test status | |
Simulation time | 2628757098 ps |
CPU time | 44.18 seconds |
Started | Aug 17 04:22:12 PM PDT 24 |
Finished | Aug 17 04:23:06 PM PDT 24 |
Peak memory | 146500 kb |
Host | smart-20525523-6b9e-4d89-a4b9-f69fb3ea7678 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1459136509 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 69.prim_prince_test.1459136509 |
Directory | /workspace/69.prim_prince_test/latest |
Test location | /workspace/coverage/default/7.prim_prince_test.2783029585 |
Short name | T375 |
Test name | |
Test status | |
Simulation time | 2516081934 ps |
CPU time | 41.66 seconds |
Started | Aug 17 04:20:23 PM PDT 24 |
Finished | Aug 17 04:21:13 PM PDT 24 |
Peak memory | 146304 kb |
Host | smart-912e79bb-3949-4d3c-b99d-f1b6bcec879b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2783029585 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_prince_test.2783029585 |
Directory | /workspace/7.prim_prince_test/latest |
Test location | /workspace/coverage/default/70.prim_prince_test.1075753204 |
Short name | T496 |
Test name | |
Test status | |
Simulation time | 1478903882 ps |
CPU time | 23.97 seconds |
Started | Aug 17 04:25:34 PM PDT 24 |
Finished | Aug 17 04:26:03 PM PDT 24 |
Peak memory | 146120 kb |
Host | smart-c1e9b7b0-5489-4525-89e3-4ef09d7ce2d4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1075753204 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 70.prim_prince_test.1075753204 |
Directory | /workspace/70.prim_prince_test/latest |
Test location | /workspace/coverage/default/71.prim_prince_test.3656749772 |
Short name | T125 |
Test name | |
Test status | |
Simulation time | 1788956874 ps |
CPU time | 29.26 seconds |
Started | Aug 17 04:25:25 PM PDT 24 |
Finished | Aug 17 04:26:00 PM PDT 24 |
Peak memory | 145816 kb |
Host | smart-3511da55-e7cb-46ea-8d19-644e7f2d9386 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3656749772 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 71.prim_prince_test.3656749772 |
Directory | /workspace/71.prim_prince_test/latest |
Test location | /workspace/coverage/default/72.prim_prince_test.3753179211 |
Short name | T110 |
Test name | |
Test status | |
Simulation time | 2635776331 ps |
CPU time | 42.72 seconds |
Started | Aug 17 04:24:48 PM PDT 24 |
Finished | Aug 17 04:25:39 PM PDT 24 |
Peak memory | 145072 kb |
Host | smart-56825c0a-9fbf-4f0b-9f43-d11e67e70e55 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3753179211 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 72.prim_prince_test.3753179211 |
Directory | /workspace/72.prim_prince_test/latest |
Test location | /workspace/coverage/default/73.prim_prince_test.1975150941 |
Short name | T437 |
Test name | |
Test status | |
Simulation time | 3715515743 ps |
CPU time | 60.65 seconds |
Started | Aug 17 04:24:50 PM PDT 24 |
Finished | Aug 17 04:26:02 PM PDT 24 |
Peak memory | 146172 kb |
Host | smart-56b446a5-d818-475c-93c5-2e082016a295 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1975150941 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 73.prim_prince_test.1975150941 |
Directory | /workspace/73.prim_prince_test/latest |
Test location | /workspace/coverage/default/74.prim_prince_test.4163267487 |
Short name | T445 |
Test name | |
Test status | |
Simulation time | 3687611686 ps |
CPU time | 58.31 seconds |
Started | Aug 17 04:25:00 PM PDT 24 |
Finished | Aug 17 04:26:09 PM PDT 24 |
Peak memory | 146196 kb |
Host | smart-d1f2d206-96d3-4ab1-966d-d2e31c78d198 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4163267487 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 74.prim_prince_test.4163267487 |
Directory | /workspace/74.prim_prince_test/latest |
Test location | /workspace/coverage/default/75.prim_prince_test.2373171283 |
Short name | T23 |
Test name | |
Test status | |
Simulation time | 1366185056 ps |
CPU time | 22.37 seconds |
Started | Aug 17 04:24:58 PM PDT 24 |
Finished | Aug 17 04:25:25 PM PDT 24 |
Peak memory | 146264 kb |
Host | smart-3096828a-7401-4243-944f-880f2b0ce0a3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2373171283 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 75.prim_prince_test.2373171283 |
Directory | /workspace/75.prim_prince_test/latest |
Test location | /workspace/coverage/default/76.prim_prince_test.1899967260 |
Short name | T77 |
Test name | |
Test status | |
Simulation time | 1106997970 ps |
CPU time | 17.68 seconds |
Started | Aug 17 04:24:49 PM PDT 24 |
Finished | Aug 17 04:25:10 PM PDT 24 |
Peak memory | 146124 kb |
Host | smart-f6b19d01-243b-4821-8344-bbf21d8fd7dc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1899967260 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 76.prim_prince_test.1899967260 |
Directory | /workspace/76.prim_prince_test/latest |
Test location | /workspace/coverage/default/77.prim_prince_test.2072226664 |
Short name | T391 |
Test name | |
Test status | |
Simulation time | 2469599842 ps |
CPU time | 40 seconds |
Started | Aug 17 04:25:34 PM PDT 24 |
Finished | Aug 17 04:26:22 PM PDT 24 |
Peak memory | 146184 kb |
Host | smart-f14cbe58-4dcb-4e09-a0f8-6a57c0f2d64d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2072226664 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 77.prim_prince_test.2072226664 |
Directory | /workspace/77.prim_prince_test/latest |
Test location | /workspace/coverage/default/78.prim_prince_test.1811283321 |
Short name | T36 |
Test name | |
Test status | |
Simulation time | 2044792918 ps |
CPU time | 33.6 seconds |
Started | Aug 17 04:25:34 PM PDT 24 |
Finished | Aug 17 04:26:15 PM PDT 24 |
Peak memory | 146120 kb |
Host | smart-23faca68-b697-4e4a-934f-d1f106de984d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1811283321 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 78.prim_prince_test.1811283321 |
Directory | /workspace/78.prim_prince_test/latest |
Test location | /workspace/coverage/default/79.prim_prince_test.3400145889 |
Short name | T347 |
Test name | |
Test status | |
Simulation time | 2009603728 ps |
CPU time | 32.08 seconds |
Started | Aug 17 04:22:22 PM PDT 24 |
Finished | Aug 17 04:23:00 PM PDT 24 |
Peak memory | 146332 kb |
Host | smart-75cf7af1-ff79-4214-ae72-74466532aa14 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3400145889 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 79.prim_prince_test.3400145889 |
Directory | /workspace/79.prim_prince_test/latest |
Test location | /workspace/coverage/default/8.prim_prince_test.3971569890 |
Short name | T152 |
Test name | |
Test status | |
Simulation time | 2831914542 ps |
CPU time | 48.03 seconds |
Started | Aug 17 04:20:27 PM PDT 24 |
Finished | Aug 17 04:21:25 PM PDT 24 |
Peak memory | 146340 kb |
Host | smart-e5ef1aba-4f3e-4ad5-91fd-0c6c4fffac27 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3971569890 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_prince_test.3971569890 |
Directory | /workspace/8.prim_prince_test/latest |
Test location | /workspace/coverage/default/80.prim_prince_test.3506590692 |
Short name | T325 |
Test name | |
Test status | |
Simulation time | 2273230324 ps |
CPU time | 37.91 seconds |
Started | Aug 17 04:24:50 PM PDT 24 |
Finished | Aug 17 04:25:35 PM PDT 24 |
Peak memory | 146128 kb |
Host | smart-dbc4fe15-745c-4cf4-b45a-fbf10665cca7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3506590692 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 80.prim_prince_test.3506590692 |
Directory | /workspace/80.prim_prince_test/latest |
Test location | /workspace/coverage/default/81.prim_prince_test.1216192687 |
Short name | T305 |
Test name | |
Test status | |
Simulation time | 2677939655 ps |
CPU time | 44.33 seconds |
Started | Aug 17 04:25:33 PM PDT 24 |
Finished | Aug 17 04:26:32 PM PDT 24 |
Peak memory | 146184 kb |
Host | smart-a7cdbc32-8e25-4305-bc72-1452a7c11de2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1216192687 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 81.prim_prince_test.1216192687 |
Directory | /workspace/81.prim_prince_test/latest |
Test location | /workspace/coverage/default/82.prim_prince_test.2170513403 |
Short name | T231 |
Test name | |
Test status | |
Simulation time | 1997256319 ps |
CPU time | 32.53 seconds |
Started | Aug 17 04:25:00 PM PDT 24 |
Finished | Aug 17 04:25:39 PM PDT 24 |
Peak memory | 146132 kb |
Host | smart-bcb724b0-ab21-4dd4-ba88-2f7405087bf7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2170513403 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 82.prim_prince_test.2170513403 |
Directory | /workspace/82.prim_prince_test/latest |
Test location | /workspace/coverage/default/83.prim_prince_test.1561774115 |
Short name | T10 |
Test name | |
Test status | |
Simulation time | 2100670117 ps |
CPU time | 34.21 seconds |
Started | Aug 17 04:24:59 PM PDT 24 |
Finished | Aug 17 04:25:40 PM PDT 24 |
Peak memory | 146132 kb |
Host | smart-2c563943-76bb-46fd-833c-067729863560 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1561774115 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 83.prim_prince_test.1561774115 |
Directory | /workspace/83.prim_prince_test/latest |
Test location | /workspace/coverage/default/84.prim_prince_test.2305912088 |
Short name | T409 |
Test name | |
Test status | |
Simulation time | 1426218168 ps |
CPU time | 23.68 seconds |
Started | Aug 17 04:24:58 PM PDT 24 |
Finished | Aug 17 04:25:27 PM PDT 24 |
Peak memory | 144580 kb |
Host | smart-13865fd5-77cd-429b-924a-b2898301f672 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2305912088 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 84.prim_prince_test.2305912088 |
Directory | /workspace/84.prim_prince_test/latest |
Test location | /workspace/coverage/default/85.prim_prince_test.1450491072 |
Short name | T219 |
Test name | |
Test status | |
Simulation time | 1413287887 ps |
CPU time | 23.86 seconds |
Started | Aug 17 04:25:33 PM PDT 24 |
Finished | Aug 17 04:26:02 PM PDT 24 |
Peak memory | 146120 kb |
Host | smart-0405991f-e7e5-4b9d-b996-adaae9030614 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1450491072 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 85.prim_prince_test.1450491072 |
Directory | /workspace/85.prim_prince_test/latest |
Test location | /workspace/coverage/default/86.prim_prince_test.1831443500 |
Short name | T115 |
Test name | |
Test status | |
Simulation time | 3203664816 ps |
CPU time | 52.32 seconds |
Started | Aug 17 04:24:49 PM PDT 24 |
Finished | Aug 17 04:25:51 PM PDT 24 |
Peak memory | 144460 kb |
Host | smart-40953211-ca76-40ea-b2ee-a6266b1942b8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1831443500 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 86.prim_prince_test.1831443500 |
Directory | /workspace/86.prim_prince_test/latest |
Test location | /workspace/coverage/default/87.prim_prince_test.1049813762 |
Short name | T105 |
Test name | |
Test status | |
Simulation time | 3210980527 ps |
CPU time | 54.28 seconds |
Started | Aug 17 04:21:52 PM PDT 24 |
Finished | Aug 17 04:22:59 PM PDT 24 |
Peak memory | 146500 kb |
Host | smart-a062d058-ced0-40a2-bf87-efcb0ffbf79e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1049813762 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 87.prim_prince_test.1049813762 |
Directory | /workspace/87.prim_prince_test/latest |
Test location | /workspace/coverage/default/88.prim_prince_test.3784796735 |
Short name | T302 |
Test name | |
Test status | |
Simulation time | 3202526198 ps |
CPU time | 51.46 seconds |
Started | Aug 17 04:25:39 PM PDT 24 |
Finished | Aug 17 04:26:40 PM PDT 24 |
Peak memory | 145988 kb |
Host | smart-d617773b-9f5a-46c6-8f95-77cdc5ef5cb3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3784796735 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 88.prim_prince_test.3784796735 |
Directory | /workspace/88.prim_prince_test/latest |
Test location | /workspace/coverage/default/89.prim_prince_test.3131299737 |
Short name | T116 |
Test name | |
Test status | |
Simulation time | 2008458202 ps |
CPU time | 32.56 seconds |
Started | Aug 17 04:24:51 PM PDT 24 |
Finished | Aug 17 04:25:30 PM PDT 24 |
Peak memory | 144840 kb |
Host | smart-4f2692c0-c5f8-46e4-a1e3-b498a552f8fc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3131299737 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 89.prim_prince_test.3131299737 |
Directory | /workspace/89.prim_prince_test/latest |
Test location | /workspace/coverage/default/9.prim_prince_test.2687536226 |
Short name | T16 |
Test name | |
Test status | |
Simulation time | 2646902789 ps |
CPU time | 43.77 seconds |
Started | Aug 17 04:21:27 PM PDT 24 |
Finished | Aug 17 04:22:19 PM PDT 24 |
Peak memory | 144672 kb |
Host | smart-4aa4f32c-9469-4c0a-ba6a-97ef53f70c57 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2687536226 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_prince_test.2687536226 |
Directory | /workspace/9.prim_prince_test/latest |
Test location | /workspace/coverage/default/90.prim_prince_test.625336802 |
Short name | T340 |
Test name | |
Test status | |
Simulation time | 3637675349 ps |
CPU time | 58.82 seconds |
Started | Aug 17 04:25:33 PM PDT 24 |
Finished | Aug 17 04:26:44 PM PDT 24 |
Peak memory | 146176 kb |
Host | smart-3914ba3c-f82b-417a-9708-289e237cd9a6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=625336802 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 90.prim_prince_test.625336802 |
Directory | /workspace/90.prim_prince_test/latest |
Test location | /workspace/coverage/default/91.prim_prince_test.402458599 |
Short name | T268 |
Test name | |
Test status | |
Simulation time | 2810658266 ps |
CPU time | 45.31 seconds |
Started | Aug 17 04:25:39 PM PDT 24 |
Finished | Aug 17 04:26:33 PM PDT 24 |
Peak memory | 146192 kb |
Host | smart-fc0ebb28-74c7-4135-83c4-9f5cf23aa495 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=402458599 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 91.prim_prince_test.402458599 |
Directory | /workspace/91.prim_prince_test/latest |
Test location | /workspace/coverage/default/92.prim_prince_test.1767010179 |
Short name | T43 |
Test name | |
Test status | |
Simulation time | 2238605465 ps |
CPU time | 38.13 seconds |
Started | Aug 17 04:22:25 PM PDT 24 |
Finished | Aug 17 04:23:12 PM PDT 24 |
Peak memory | 146640 kb |
Host | smart-5adc4d36-540a-425f-94ea-285d16ab87af |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1767010179 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 92.prim_prince_test.1767010179 |
Directory | /workspace/92.prim_prince_test/latest |
Test location | /workspace/coverage/default/93.prim_prince_test.1218455334 |
Short name | T8 |
Test name | |
Test status | |
Simulation time | 2736454880 ps |
CPU time | 44.24 seconds |
Started | Aug 17 04:25:33 PM PDT 24 |
Finished | Aug 17 04:26:26 PM PDT 24 |
Peak memory | 146184 kb |
Host | smart-e1183905-a013-448e-b845-399cb8dbd04e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1218455334 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 93.prim_prince_test.1218455334 |
Directory | /workspace/93.prim_prince_test/latest |
Test location | /workspace/coverage/default/94.prim_prince_test.3015772898 |
Short name | T154 |
Test name | |
Test status | |
Simulation time | 2787525788 ps |
CPU time | 45.22 seconds |
Started | Aug 17 04:24:49 PM PDT 24 |
Finished | Aug 17 04:25:43 PM PDT 24 |
Peak memory | 144340 kb |
Host | smart-3d6f19b5-a95a-4d93-bf0a-a2c6249b6b10 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3015772898 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 94.prim_prince_test.3015772898 |
Directory | /workspace/94.prim_prince_test/latest |
Test location | /workspace/coverage/default/95.prim_prince_test.1461559547 |
Short name | T41 |
Test name | |
Test status | |
Simulation time | 2719384176 ps |
CPU time | 44.12 seconds |
Started | Aug 17 04:25:00 PM PDT 24 |
Finished | Aug 17 04:25:53 PM PDT 24 |
Peak memory | 146196 kb |
Host | smart-fe69dd6e-6ced-4c37-80ee-8ed053e7976f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1461559547 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 95.prim_prince_test.1461559547 |
Directory | /workspace/95.prim_prince_test/latest |
Test location | /workspace/coverage/default/96.prim_prince_test.4070072512 |
Short name | T117 |
Test name | |
Test status | |
Simulation time | 2262744793 ps |
CPU time | 36.59 seconds |
Started | Aug 17 04:25:33 PM PDT 24 |
Finished | Aug 17 04:26:17 PM PDT 24 |
Peak memory | 145940 kb |
Host | smart-b8cd44e7-0119-4280-8135-caa8f75ab504 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4070072512 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 96.prim_prince_test.4070072512 |
Directory | /workspace/96.prim_prince_test/latest |
Test location | /workspace/coverage/default/97.prim_prince_test.725651676 |
Short name | T164 |
Test name | |
Test status | |
Simulation time | 2079434270 ps |
CPU time | 33.9 seconds |
Started | Aug 17 04:24:51 PM PDT 24 |
Finished | Aug 17 04:25:31 PM PDT 24 |
Peak memory | 144416 kb |
Host | smart-867cf93e-3a9e-486b-97d9-84e476fc1071 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=725651676 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 97.prim_prince_test.725651676 |
Directory | /workspace/97.prim_prince_test/latest |
Test location | /workspace/coverage/default/98.prim_prince_test.3570889144 |
Short name | T112 |
Test name | |
Test status | |
Simulation time | 2450977103 ps |
CPU time | 39.28 seconds |
Started | Aug 17 04:25:39 PM PDT 24 |
Finished | Aug 17 04:26:26 PM PDT 24 |
Peak memory | 146192 kb |
Host | smart-d663ca2e-e8ca-47c4-b3a5-ca64503d32ec |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3570889144 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 98.prim_prince_test.3570889144 |
Directory | /workspace/98.prim_prince_test/latest |
Test location | /workspace/coverage/default/99.prim_prince_test.3703971080 |
Short name | T491 |
Test name | |
Test status | |
Simulation time | 2724755718 ps |
CPU time | 43.45 seconds |
Started | Aug 17 04:25:14 PM PDT 24 |
Finished | Aug 17 04:26:06 PM PDT 24 |
Peak memory | 146176 kb |
Host | smart-71c4ad29-c36f-4086-8902-7fb56c2b095f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3703971080 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 99.prim_prince_test.3703971080 |
Directory | /workspace/99.prim_prince_test/latest |
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