| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 | 100.00 | 100.00 | 100.00 | 100.00 |
| T251 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/248.prim_prince_test.1878520072 | Aug 21 02:38:32 AM UTC 24 | Aug 21 02:39:23 AM UTC 24 | 2315158691 ps | ||
| T252 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/261.prim_prince_test.2749644489 | Aug 21 02:39:06 AM UTC 24 | Aug 21 02:39:25 AM UTC 24 | 813667047 ps | ||
| T253 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/237.prim_prince_test.2523768455 | Aug 21 02:38:06 AM UTC 24 | Aug 21 02:39:25 AM UTC 24 | 3702459422 ps | ||
| T254 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/246.prim_prince_test.2497298536 | Aug 21 02:38:32 AM UTC 24 | Aug 21 02:39:28 AM UTC 24 | 2596566304 ps | ||
| T255 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/263.prim_prince_test.1633800673 | Aug 21 02:39:09 AM UTC 24 | Aug 21 02:39:29 AM UTC 24 | 864941336 ps | ||
| T256 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/256.prim_prince_test.2621496867 | Aug 21 02:38:50 AM UTC 24 | Aug 21 02:39:32 AM UTC 24 | 1891023933 ps | ||
| T257 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/245.prim_prince_test.3253606770 | Aug 21 02:38:25 AM UTC 24 | Aug 21 02:39:33 AM UTC 24 | 3079460382 ps | ||
| T258 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/266.prim_prince_test.2290422708 | Aug 21 02:39:16 AM UTC 24 | Aug 21 02:39:34 AM UTC 24 | 793321345 ps | ||
| T259 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/265.prim_prince_test.2030383927 | Aug 21 02:39:14 AM UTC 24 | Aug 21 02:39:35 AM UTC 24 | 898110820 ps | ||
| T260 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/269.prim_prince_test.1531734460 | Aug 21 02:39:24 AM UTC 24 | Aug 21 02:39:42 AM UTC 24 | 792190096 ps | ||
| T261 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/267.prim_prince_test.4142344737 | Aug 21 02:39:18 AM UTC 24 | Aug 21 02:39:43 AM UTC 24 | 1139171080 ps | ||
| T262 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/273.prim_prince_test.2506249142 | Aug 21 02:39:28 AM UTC 24 | Aug 21 02:39:50 AM UTC 24 | 919271698 ps | ||
| T263 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/253.prim_prince_test.2641378286 | Aug 21 02:38:47 AM UTC 24 | Aug 21 02:39:51 AM UTC 24 | 2887434998 ps | ||
| T264 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/259.prim_prince_test.833348071 | Aug 21 02:39:00 AM UTC 24 | Aug 21 02:39:58 AM UTC 24 | 2655950536 ps | ||
| T265 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/260.prim_prince_test.2477325777 | Aug 21 02:39:00 AM UTC 24 | Aug 21 02:40:00 AM UTC 24 | 2760552876 ps | ||
| T266 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/252.prim_prince_test.1429632952 | Aug 21 02:38:45 AM UTC 24 | Aug 21 02:40:00 AM UTC 24 | 3442554424 ps | ||
| T267 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/264.prim_prince_test.533309245 | Aug 21 02:39:10 AM UTC 24 | Aug 21 02:40:03 AM UTC 24 | 2450548334 ps | ||
| T268 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/255.prim_prince_test.2750835653 | Aug 21 02:38:48 AM UTC 24 | Aug 21 02:40:06 AM UTC 24 | 3581735040 ps | ||
| T269 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/257.prim_prince_test.1793199878 | Aug 21 02:38:53 AM UTC 24 | Aug 21 02:40:06 AM UTC 24 | 3374786825 ps | ||
| T270 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/270.prim_prince_test.293481030 | Aug 21 02:39:24 AM UTC 24 | Aug 21 02:40:08 AM UTC 24 | 2014996257 ps | ||
| T271 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/277.prim_prince_test.1210767177 | Aug 21 02:39:36 AM UTC 24 | Aug 21 02:40:09 AM UTC 24 | 1462322583 ps | ||
| T272 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/278.prim_prince_test.1610143102 | Aug 21 02:39:36 AM UTC 24 | Aug 21 02:40:11 AM UTC 24 | 1591905336 ps | ||
| T273 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/268.prim_prince_test.3083551333 | Aug 21 02:39:20 AM UTC 24 | Aug 21 02:40:14 AM UTC 24 | 2464420885 ps | ||
| T274 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/272.prim_prince_test.2471775511 | Aug 21 02:39:26 AM UTC 24 | Aug 21 02:40:16 AM UTC 24 | 2300439945 ps | ||
| T275 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/275.prim_prince_test.1126197498 | Aug 21 02:39:32 AM UTC 24 | Aug 21 02:40:22 AM UTC 24 | 2256175360 ps | ||
| T276 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/274.prim_prince_test.2128012953 | Aug 21 02:39:29 AM UTC 24 | Aug 21 02:40:22 AM UTC 24 | 2427337003 ps | ||
| T277 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/279.prim_prince_test.895563456 | Aug 21 02:39:43 AM UTC 24 | Aug 21 02:40:22 AM UTC 24 | 1789643071 ps | ||
| T278 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/285.prim_prince_test.94662 | Aug 21 02:40:01 AM UTC 24 | Aug 21 02:40:23 AM UTC 24 | 1002564506 ps | ||
| T279 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/262.prim_prince_test.1601259977 | Aug 21 02:39:08 AM UTC 24 | Aug 21 02:40:27 AM UTC 24 | 3663434170 ps | ||
| T280 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/280.prim_prince_test.501548026 | Aug 21 02:39:44 AM UTC 24 | Aug 21 02:40:33 AM UTC 24 | 2252301749 ps | ||
| T281 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/282.prim_prince_test.681677780 | Aug 21 02:39:51 AM UTC 24 | Aug 21 02:40:34 AM UTC 24 | 1956022504 ps | ||
| T282 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/293.prim_prince_test.761371328 | Aug 21 02:40:17 AM UTC 24 | Aug 21 02:40:36 AM UTC 24 | 827297969 ps | ||
| T283 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/271.prim_prince_test.2651825902 | Aug 21 02:39:26 AM UTC 24 | Aug 21 02:40:40 AM UTC 24 | 3414708782 ps | ||
| T284 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/292.prim_prince_test.366996238 | Aug 21 02:40:14 AM UTC 24 | Aug 21 02:40:43 AM UTC 24 | 1283072842 ps | ||
| T285 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/294.prim_prince_test.993570070 | Aug 21 02:40:23 AM UTC 24 | Aug 21 02:40:48 AM UTC 24 | 1090048488 ps | ||
| T286 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/276.prim_prince_test.2222676941 | Aug 21 02:39:34 AM UTC 24 | Aug 21 02:40:52 AM UTC 24 | 3654844128 ps | ||
| T287 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/290.prim_prince_test.535684050 | Aug 21 02:40:09 AM UTC 24 | Aug 21 02:40:53 AM UTC 24 | 1970795734 ps | ||
| T288 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/295.prim_prince_test.1526443896 | Aug 21 02:40:24 AM UTC 24 | Aug 21 02:40:58 AM UTC 24 | 1542783597 ps | ||
| T289 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/302.prim_prince_test.2212858276 | Aug 21 02:40:41 AM UTC 24 | Aug 21 02:40:58 AM UTC 24 | 760049366 ps | ||
| T290 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/281.prim_prince_test.2444992670 | Aug 21 02:39:50 AM UTC 24 | Aug 21 02:40:59 AM UTC 24 | 3140925578 ps | ||
| T291 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/288.prim_prince_test.4010560978 | Aug 21 02:40:07 AM UTC 24 | Aug 21 02:41:00 AM UTC 24 | 2455402707 ps | ||
| T292 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/300.prim_prince_test.3701687243 | Aug 21 02:40:35 AM UTC 24 | Aug 21 02:41:02 AM UTC 24 | 1199355634 ps | ||
| T293 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/297.prim_prince_test.188192794 | Aug 21 02:40:24 AM UTC 24 | Aug 21 02:41:07 AM UTC 24 | 1985668882 ps | ||
| T294 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/283.prim_prince_test.289989027 | Aug 21 02:39:59 AM UTC 24 | Aug 21 02:41:09 AM UTC 24 | 3150623744 ps | ||
| T295 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/286.prim_prince_test.2773472066 | Aug 21 02:40:05 AM UTC 24 | Aug 21 02:41:09 AM UTC 24 | 2976748361 ps | ||
| T296 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/289.prim_prince_test.2823886794 | Aug 21 02:40:09 AM UTC 24 | Aug 21 02:41:15 AM UTC 24 | 3030426476 ps | ||
| T297 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/287.prim_prince_test.3780460735 | Aug 21 02:40:06 AM UTC 24 | Aug 21 02:41:19 AM UTC 24 | 3413587588 ps | ||
| T298 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/296.prim_prince_test.4023171009 | Aug 21 02:40:24 AM UTC 24 | Aug 21 02:41:19 AM UTC 24 | 2563518078 ps | ||
| T299 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/284.prim_prince_test.3170925434 | Aug 21 02:40:01 AM UTC 24 | Aug 21 02:41:20 AM UTC 24 | 3631216020 ps | ||
| T300 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/291.prim_prince_test.903849078 | Aug 21 02:40:11 AM UTC 24 | Aug 21 02:41:25 AM UTC 24 | 3390763006 ps | ||
| T301 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/311.prim_prince_test.3879297711 | Aug 21 02:41:03 AM UTC 24 | Aug 21 02:41:29 AM UTC 24 | 1159884596 ps | ||
| T302 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/305.prim_prince_test.3271737796 | Aug 21 02:40:53 AM UTC 24 | Aug 21 02:41:32 AM UTC 24 | 1743813577 ps | ||
| T303 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/304.prim_prince_test.1005539825 | Aug 21 02:40:49 AM UTC 24 | Aug 21 02:41:37 AM UTC 24 | 2203306723 ps | ||
| T304 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/303.prim_prince_test.3746917802 | Aug 21 02:40:44 AM UTC 24 | Aug 21 02:41:42 AM UTC 24 | 2687942632 ps | ||
| T305 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/299.prim_prince_test.2961604965 | Aug 21 02:40:34 AM UTC 24 | Aug 21 02:41:42 AM UTC 24 | 3175449364 ps | ||
| T306 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/315.prim_prince_test.1235847574 | Aug 21 02:41:16 AM UTC 24 | Aug 21 02:41:44 AM UTC 24 | 1230985655 ps | ||
| T307 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/301.prim_prince_test.76752425 | Aug 21 02:40:37 AM UTC 24 | Aug 21 02:41:46 AM UTC 24 | 3191719529 ps | ||
| T308 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/298.prim_prince_test.1150484213 | Aug 21 02:40:28 AM UTC 24 | Aug 21 02:41:47 AM UTC 24 | 3663540539 ps | ||
| T309 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/306.prim_prince_test.3863484510 | Aug 21 02:40:54 AM UTC 24 | Aug 21 02:41:54 AM UTC 24 | 2745757633 ps | ||
| T310 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/322.prim_prince_test.3871508933 | Aug 21 02:41:38 AM UTC 24 | Aug 21 02:41:55 AM UTC 24 | 767581560 ps | ||
| T311 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/309.prim_prince_test.2012546767 | Aug 21 02:41:00 AM UTC 24 | Aug 21 02:41:56 AM UTC 24 | 2516758369 ps | ||
| T312 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/316.prim_prince_test.1017384647 | Aug 21 02:41:20 AM UTC 24 | Aug 21 02:42:02 AM UTC 24 | 1892025717 ps | ||
| T313 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/317.prim_prince_test.2952106334 | Aug 21 02:41:20 AM UTC 24 | Aug 21 02:42:07 AM UTC 24 | 2098761992 ps | ||
| T314 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/307.prim_prince_test.2838687131 | Aug 21 02:40:59 AM UTC 24 | Aug 21 02:42:10 AM UTC 24 | 3238435285 ps | ||
| T315 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/321.prim_prince_test.3176058167 | Aug 21 02:41:33 AM UTC 24 | Aug 21 02:42:10 AM UTC 24 | 1682139198 ps | ||
| T316 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/308.prim_prince_test.1363676216 | Aug 21 02:40:59 AM UTC 24 | Aug 21 02:42:10 AM UTC 24 | 3219793764 ps | ||
| T317 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/324.prim_prince_test.1904555595 | Aug 21 02:41:43 AM UTC 24 | Aug 21 02:42:11 AM UTC 24 | 1213472432 ps | ||
| T318 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/319.prim_prince_test.3033369966 | Aug 21 02:41:25 AM UTC 24 | Aug 21 02:42:12 AM UTC 24 | 2094056051 ps | ||
| T319 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/327.prim_prince_test.1141776433 | Aug 21 02:41:47 AM UTC 24 | Aug 21 02:42:17 AM UTC 24 | 1335107906 ps | ||
| T320 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/318.prim_prince_test.205523116 | Aug 21 02:41:20 AM UTC 24 | Aug 21 02:42:18 AM UTC 24 | 2640400096 ps | ||
| T321 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/313.prim_prince_test.2391699037 | Aug 21 02:41:10 AM UTC 24 | Aug 21 02:42:21 AM UTC 24 | 3258759140 ps | ||
| T322 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/310.prim_prince_test.553798118 | Aug 21 02:41:00 AM UTC 24 | Aug 21 02:42:22 AM UTC 24 | 3740860931 ps | ||
| T323 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/331.prim_prince_test.3253413211 | Aug 21 02:42:03 AM UTC 24 | Aug 21 02:42:23 AM UTC 24 | 840205494 ps | ||
| T324 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/314.prim_prince_test.3252270394 | Aug 21 02:41:10 AM UTC 24 | Aug 21 02:42:26 AM UTC 24 | 3488080422 ps | ||
| T325 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/312.prim_prince_test.938251645 | Aug 21 02:41:08 AM UTC 24 | Aug 21 02:42:27 AM UTC 24 | 3641798851 ps | ||
| T326 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/323.prim_prince_test.3497355417 | Aug 21 02:41:43 AM UTC 24 | Aug 21 02:42:29 AM UTC 24 | 2077157246 ps | ||
| T327 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/320.prim_prince_test.2430533886 | Aug 21 02:41:30 AM UTC 24 | Aug 21 02:42:29 AM UTC 24 | 2752464374 ps | ||
| T328 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/335.prim_prince_test.3164293825 | Aug 21 02:42:12 AM UTC 24 | Aug 21 02:42:34 AM UTC 24 | 1005035424 ps | ||
| T329 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/325.prim_prince_test.3175349769 | Aug 21 02:41:45 AM UTC 24 | Aug 21 02:42:36 AM UTC 24 | 2301285288 ps | ||
| T330 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/340.prim_prince_test.3321627117 | Aug 21 02:42:21 AM UTC 24 | Aug 21 02:42:40 AM UTC 24 | 831471168 ps | ||
| T331 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/333.prim_prince_test.3652629694 | Aug 21 02:42:10 AM UTC 24 | Aug 21 02:42:40 AM UTC 24 | 1371273665 ps | ||
| T332 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/334.prim_prince_test.1152452896 | Aug 21 02:42:10 AM UTC 24 | Aug 21 02:42:42 AM UTC 24 | 1392628064 ps | ||
| T333 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/346.prim_prince_test.1470720597 | Aug 21 02:42:30 AM UTC 24 | Aug 21 02:42:52 AM UTC 24 | 986104174 ps | ||
| T334 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/347.prim_prince_test.1958719994 | Aug 21 02:42:35 AM UTC 24 | Aug 21 02:42:56 AM UTC 24 | 915243639 ps | ||
| T335 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/326.prim_prince_test.3027732174 | Aug 21 02:41:46 AM UTC 24 | Aug 21 02:42:56 AM UTC 24 | 3239880668 ps | ||
| T336 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/345.prim_prince_test.3100267916 | Aug 21 02:42:30 AM UTC 24 | Aug 21 02:42:59 AM UTC 24 | 1289609724 ps | ||
| T337 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/330.prim_prince_test.1798009954 | Aug 21 02:41:57 AM UTC 24 | Aug 21 02:42:59 AM UTC 24 | 2851308731 ps | ||
| T338 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/343.prim_prince_test.1840735189 | Aug 21 02:42:26 AM UTC 24 | Aug 21 02:43:03 AM UTC 24 | 1633640356 ps | ||
| T339 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/338.prim_prince_test.547504864 | Aug 21 02:42:18 AM UTC 24 | Aug 21 02:43:03 AM UTC 24 | 2065832685 ps | ||
| T340 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/328.prim_prince_test.1905971786 | Aug 21 02:41:55 AM UTC 24 | Aug 21 02:43:05 AM UTC 24 | 3218490024 ps | ||
| T341 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/341.prim_prince_test.2121199891 | Aug 21 02:42:22 AM UTC 24 | Aug 21 02:43:09 AM UTC 24 | 2130768483 ps | ||
| T342 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/332.prim_prince_test.2011228016 | Aug 21 02:42:08 AM UTC 24 | Aug 21 02:43:09 AM UTC 24 | 2835613283 ps | ||
| T343 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/350.prim_prince_test.3104894525 | Aug 21 02:42:41 AM UTC 24 | Aug 21 02:43:15 AM UTC 24 | 1516050369 ps | ||
| T344 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/336.prim_prince_test.1525975227 | Aug 21 02:42:12 AM UTC 24 | Aug 21 02:43:15 AM UTC 24 | 2946546625 ps | ||
| T345 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/329.prim_prince_test.1798660374 | Aug 21 02:41:56 AM UTC 24 | Aug 21 02:43:15 AM UTC 24 | 3688334336 ps | ||
| T346 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/337.prim_prince_test.131492000 | Aug 21 02:42:13 AM UTC 24 | Aug 21 02:43:16 AM UTC 24 | 2881235178 ps | ||
| T347 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/344.prim_prince_test.615836254 | Aug 21 02:42:28 AM UTC 24 | Aug 21 02:43:19 AM UTC 24 | 2331061346 ps | ||
| T348 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/339.prim_prince_test.104451684 | Aug 21 02:42:19 AM UTC 24 | Aug 21 02:43:22 AM UTC 24 | 2893886566 ps | ||
| T349 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/349.prim_prince_test.1195680039 | Aug 21 02:42:40 AM UTC 24 | Aug 21 02:43:22 AM UTC 24 | 1909918466 ps | ||
| T350 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/342.prim_prince_test.3207836956 | Aug 21 02:42:23 AM UTC 24 | Aug 21 02:43:24 AM UTC 24 | 2795244846 ps | ||
| T351 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/355.prim_prince_test.2868000725 | Aug 21 02:42:59 AM UTC 24 | Aug 21 02:43:25 AM UTC 24 | 1124789600 ps | ||
| T352 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/353.prim_prince_test.1201727707 | Aug 21 02:42:57 AM UTC 24 | Aug 21 02:43:27 AM UTC 24 | 1344307086 ps | ||
| T353 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/360.prim_prince_test.3124661186 | Aug 21 02:43:10 AM UTC 24 | Aug 21 02:43:30 AM UTC 24 | 897950895 ps | ||
| T354 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/362.prim_prince_test.654721393 | Aug 21 02:43:16 AM UTC 24 | Aug 21 02:43:38 AM UTC 24 | 978096943 ps | ||
| T355 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/352.prim_prince_test.2762528949 | Aug 21 02:42:54 AM UTC 24 | Aug 21 02:43:39 AM UTC 24 | 2047241053 ps | ||
| T356 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/357.prim_prince_test.1409410859 | Aug 21 02:43:03 AM UTC 24 | Aug 21 02:43:43 AM UTC 24 | 1759080277 ps | ||
| T357 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/351.prim_prince_test.3982630365 | Aug 21 02:42:42 AM UTC 24 | Aug 21 02:43:50 AM UTC 24 | 3098750526 ps | ||
| T358 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/356.prim_prince_test.3306001438 | Aug 21 02:42:59 AM UTC 24 | Aug 21 02:43:51 AM UTC 24 | 2352926860 ps | ||
| T359 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/348.prim_prince_test.1170100003 | Aug 21 02:42:37 AM UTC 24 | Aug 21 02:43:57 AM UTC 24 | 3666092040 ps | ||
| T360 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/367.prim_prince_test.2665576058 | Aug 21 02:43:23 AM UTC 24 | Aug 21 02:43:59 AM UTC 24 | 1625006040 ps | ||
| T361 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/354.prim_prince_test.1016975199 | Aug 21 02:42:58 AM UTC 24 | Aug 21 02:44:00 AM UTC 24 | 2837216829 ps | ||
| T362 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/374.prim_prince_test.4075298483 | Aug 21 02:43:40 AM UTC 24 | Aug 21 02:44:01 AM UTC 24 | 877535887 ps | ||
| T363 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/375.prim_prince_test.1117079721 | Aug 21 02:43:43 AM UTC 24 | Aug 21 02:44:03 AM UTC 24 | 829312832 ps | ||
| T364 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/368.prim_prince_test.2412613558 | Aug 21 02:43:24 AM UTC 24 | Aug 21 02:44:04 AM UTC 24 | 1789972970 ps | ||
| T365 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/369.prim_prince_test.3397419194 | Aug 21 02:43:25 AM UTC 24 | Aug 21 02:44:09 AM UTC 24 | 1991759850 ps | ||
| T366 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/378.prim_prince_test.2848887833 | Aug 21 02:43:52 AM UTC 24 | Aug 21 02:44:11 AM UTC 24 | 824329650 ps | ||
| T367 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/359.prim_prince_test.2778998559 | Aug 21 02:43:05 AM UTC 24 | Aug 21 02:44:11 AM UTC 24 | 3012974197 ps | ||
| T368 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/372.prim_prince_test.235241263 | Aug 21 02:43:32 AM UTC 24 | Aug 21 02:44:12 AM UTC 24 | 1799430057 ps | ||
| T369 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/358.prim_prince_test.75892391 | Aug 21 02:43:04 AM UTC 24 | Aug 21 02:44:15 AM UTC 24 | 3232713415 ps | ||
| T370 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/370.prim_prince_test.3240416658 | Aug 21 02:43:26 AM UTC 24 | Aug 21 02:44:19 AM UTC 24 | 2400602943 ps | ||
| T371 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/363.prim_prince_test.3398352666 | Aug 21 02:43:16 AM UTC 24 | Aug 21 02:44:20 AM UTC 24 | 2889893069 ps | ||
| T372 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/366.prim_prince_test.3395480640 | Aug 21 02:43:19 AM UTC 24 | Aug 21 02:44:21 AM UTC 24 | 2822016170 ps | ||
| T373 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/379.prim_prince_test.2051851335 | Aug 21 02:43:58 AM UTC 24 | Aug 21 02:44:22 AM UTC 24 | 1077298479 ps | ||
| T374 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/382.prim_prince_test.319627623 | Aug 21 02:44:01 AM UTC 24 | Aug 21 02:44:23 AM UTC 24 | 962925430 ps | ||
| T375 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/380.prim_prince_test.1879597831 | Aug 21 02:44:00 AM UTC 24 | Aug 21 02:44:25 AM UTC 24 | 1089934332 ps | ||
| T376 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/373.prim_prince_test.3908871829 | Aug 21 02:43:40 AM UTC 24 | Aug 21 02:44:26 AM UTC 24 | 2075140770 ps | ||
| T377 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/361.prim_prince_test.2070061446 | Aug 21 02:43:11 AM UTC 24 | Aug 21 02:44:32 AM UTC 24 | 3710840693 ps | ||
| T378 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/388.prim_prince_test.2974357446 | Aug 21 02:44:13 AM UTC 24 | Aug 21 02:44:35 AM UTC 24 | 957019940 ps | ||
| T379 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/364.prim_prince_test.848524375 | Aug 21 02:43:16 AM UTC 24 | Aug 21 02:44:36 AM UTC 24 | 3679481694 ps | ||
| T380 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/384.prim_prince_test.4112092852 | Aug 21 02:44:05 AM UTC 24 | Aug 21 02:44:37 AM UTC 24 | 1432579759 ps | ||
| T381 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/365.prim_prince_test.380423317 | Aug 21 02:43:17 AM UTC 24 | Aug 21 02:44:39 AM UTC 24 | 3735266605 ps | ||
| T382 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/387.prim_prince_test.1271865278 | Aug 21 02:44:12 AM UTC 24 | Aug 21 02:44:40 AM UTC 24 | 1244513243 ps | ||
| T383 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/376.prim_prince_test.2960878288 | Aug 21 02:43:51 AM UTC 24 | Aug 21 02:44:40 AM UTC 24 | 2269575349 ps | ||
| T384 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/393.prim_prince_test.2957958257 | Aug 21 02:44:23 AM UTC 24 | Aug 21 02:44:42 AM UTC 24 | 806025937 ps | ||
| T385 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/381.prim_prince_test.2295247438 | Aug 21 02:44:01 AM UTC 24 | Aug 21 02:44:43 AM UTC 24 | 1907620951 ps | ||
| T386 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/371.prim_prince_test.3127039831 | Aug 21 02:43:30 AM UTC 24 | Aug 21 02:44:46 AM UTC 24 | 3457703277 ps | ||
| T387 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/389.prim_prince_test.420635299 | Aug 21 02:44:15 AM UTC 24 | Aug 21 02:44:48 AM UTC 24 | 1455798837 ps | ||
| T388 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/377.prim_prince_test.2120755513 | Aug 21 02:43:51 AM UTC 24 | Aug 21 02:44:53 AM UTC 24 | 2875681249 ps | ||
| T389 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/400.prim_prince_test.952872267 | Aug 21 02:44:38 AM UTC 24 | Aug 21 02:45:02 AM UTC 24 | 1048938079 ps | ||
| T390 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/385.prim_prince_test.1904298621 | Aug 21 02:44:10 AM UTC 24 | Aug 21 02:45:03 AM UTC 24 | 2442181140 ps | ||
| T391 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/403.prim_prince_test.1111376253 | Aug 21 02:44:41 AM UTC 24 | Aug 21 02:45:04 AM UTC 24 | 1018821052 ps | ||
| T392 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/390.prim_prince_test.3832557455 | Aug 21 02:44:19 AM UTC 24 | Aug 21 02:45:08 AM UTC 24 | 2230638031 ps | ||
| T393 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/392.prim_prince_test.1003447009 | Aug 21 02:44:22 AM UTC 24 | Aug 21 02:45:10 AM UTC 24 | 2201785201 ps | ||
| T394 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/399.prim_prince_test.3162470608 | Aug 21 02:44:38 AM UTC 24 | Aug 21 02:45:14 AM UTC 24 | 1617325884 ps | ||
| T395 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/396.prim_prince_test.1354151263 | Aug 21 02:44:27 AM UTC 24 | Aug 21 02:45:15 AM UTC 24 | 2127903263 ps | ||
| T396 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/397.prim_prince_test.2720243082 | Aug 21 02:44:32 AM UTC 24 | Aug 21 02:45:20 AM UTC 24 | 2192386457 ps | ||
| T397 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/391.prim_prince_test.4027675741 | Aug 21 02:44:21 AM UTC 24 | Aug 21 02:45:22 AM UTC 24 | 2831400510 ps | ||
| T398 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/383.prim_prince_test.696703890 | Aug 21 02:44:03 AM UTC 24 | Aug 21 02:45:23 AM UTC 24 | 3672423977 ps | ||
| T399 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/398.prim_prince_test.125164388 | Aug 21 02:44:36 AM UTC 24 | Aug 21 02:45:25 AM UTC 24 | 2289344877 ps | ||
| T400 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/386.prim_prince_test.552065110 | Aug 21 02:44:12 AM UTC 24 | Aug 21 02:45:26 AM UTC 24 | 3411012053 ps | ||
| T401 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/408.prim_prince_test.2322617604 | Aug 21 02:44:54 AM UTC 24 | Aug 21 02:45:28 AM UTC 24 | 1522261379 ps | ||
| T402 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/401.prim_prince_test.659695863 | Aug 21 02:44:40 AM UTC 24 | Aug 21 02:45:28 AM UTC 24 | 2184888128 ps | ||
| T403 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/402.prim_prince_test.128823183 | Aug 21 02:44:41 AM UTC 24 | Aug 21 02:45:33 AM UTC 24 | 2365448271 ps | ||
| T404 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/394.prim_prince_test.1767866938 | Aug 21 02:44:24 AM UTC 24 | Aug 21 02:45:34 AM UTC 24 | 3223041750 ps | ||
| T405 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/395.prim_prince_test.1797581375 | Aug 21 02:44:25 AM UTC 24 | Aug 21 02:45:36 AM UTC 24 | 3234229666 ps | ||
| T406 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/411.prim_prince_test.4032643929 | Aug 21 02:45:05 AM UTC 24 | Aug 21 02:45:37 AM UTC 24 | 1423538257 ps | ||
| T407 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/407.prim_prince_test.4040262971 | Aug 21 02:44:49 AM UTC 24 | Aug 21 02:45:44 AM UTC 24 | 2539806659 ps | ||
| T408 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/404.prim_prince_test.141839790 | Aug 21 02:44:42 AM UTC 24 | Aug 21 02:45:45 AM UTC 24 | 2908502597 ps | ||
| T409 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/415.prim_prince_test.3403299743 | Aug 21 02:45:16 AM UTC 24 | Aug 21 02:45:46 AM UTC 24 | 1345666228 ps | ||
| T410 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/420.prim_prince_test.2365157521 | Aug 21 02:45:27 AM UTC 24 | Aug 21 02:45:47 AM UTC 24 | 869261726 ps | ||
| T411 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/406.prim_prince_test.3592939903 | Aug 21 02:44:47 AM UTC 24 | Aug 21 02:45:51 AM UTC 24 | 3003292708 ps | ||
| T412 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/405.prim_prince_test.3554811111 | Aug 21 02:44:45 AM UTC 24 | Aug 21 02:45:53 AM UTC 24 | 3153686760 ps | ||
| T413 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/418.prim_prince_test.2960768385 | Aug 21 02:45:23 AM UTC 24 | Aug 21 02:45:53 AM UTC 24 | 1342029677 ps | ||
| T414 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/409.prim_prince_test.1022001951 | Aug 21 02:45:03 AM UTC 24 | Aug 21 02:45:54 AM UTC 24 | 2291368248 ps | ||
| T415 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/423.prim_prince_test.1010768876 | Aug 21 02:45:34 AM UTC 24 | Aug 21 02:45:54 AM UTC 24 | 877433200 ps | ||
| T416 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/424.prim_prince_test.3263309730 | Aug 21 02:45:35 AM UTC 24 | Aug 21 02:45:56 AM UTC 24 | 912646335 ps | ||
| T417 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/429.prim_prince_test.1228852318 | Aug 21 02:45:47 AM UTC 24 | Aug 21 02:46:08 AM UTC 24 | 890143107 ps | ||
| T418 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/413.prim_prince_test.1394086703 | Aug 21 02:45:11 AM UTC 24 | Aug 21 02:46:08 AM UTC 24 | 2672360497 ps | ||
| T419 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/428.prim_prince_test.2098899383 | Aug 21 02:45:46 AM UTC 24 | Aug 21 02:46:09 AM UTC 24 | 1011535721 ps | ||
| T420 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/414.prim_prince_test.1264144473 | Aug 21 02:45:15 AM UTC 24 | Aug 21 02:46:16 AM UTC 24 | 2837878786 ps | ||
| T421 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/433.prim_prince_test.3395255983 | Aug 21 02:45:55 AM UTC 24 | Aug 21 02:46:17 AM UTC 24 | 978981434 ps | ||
| T422 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/410.prim_prince_test.272982784 | Aug 21 02:45:04 AM UTC 24 | Aug 21 02:46:17 AM UTC 24 | 3368936302 ps | ||
| T423 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/432.prim_prince_test.1841896027 | Aug 21 02:45:53 AM UTC 24 | Aug 21 02:46:23 AM UTC 24 | 1329880001 ps | ||
| T424 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/412.prim_prince_test.1632188031 | Aug 21 02:45:10 AM UTC 24 | Aug 21 02:46:25 AM UTC 24 | 3512948691 ps | ||
| T425 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/434.prim_prince_test.2121462111 | Aug 21 02:45:55 AM UTC 24 | Aug 21 02:46:31 AM UTC 24 | 1615508222 ps | ||
| T426 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/431.prim_prince_test.3194012372 | Aug 21 02:45:52 AM UTC 24 | Aug 21 02:46:31 AM UTC 24 | 1752874724 ps | ||
| T427 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/422.prim_prince_test.61211684 | Aug 21 02:45:29 AM UTC 24 | Aug 21 02:46:32 AM UTC 24 | 2886800396 ps | ||
| T428 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/417.prim_prince_test.3962646025 | Aug 21 02:45:23 AM UTC 24 | Aug 21 02:46:34 AM UTC 24 | 3272632338 ps | ||
| T429 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/419.prim_prince_test.1034556941 | Aug 21 02:45:26 AM UTC 24 | Aug 21 02:46:36 AM UTC 24 | 3266367623 ps | ||
| T430 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/416.prim_prince_test.3084817906 | Aug 21 02:45:21 AM UTC 24 | Aug 21 02:46:37 AM UTC 24 | 3539381258 ps | ||
| T431 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/421.prim_prince_test.717016195 | Aug 21 02:45:29 AM UTC 24 | Aug 21 02:46:40 AM UTC 24 | 3255020622 ps | ||
| T432 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/436.prim_prince_test.3140145059 | Aug 21 02:45:57 AM UTC 24 | Aug 21 02:46:43 AM UTC 24 | 2082128516 ps | ||
| T433 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/426.prim_prince_test.749848855 | Aug 21 02:45:38 AM UTC 24 | Aug 21 02:46:43 AM UTC 24 | 3029825035 ps | ||
| T434 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/430.prim_prince_test.2056475287 | Aug 21 02:45:47 AM UTC 24 | Aug 21 02:46:43 AM UTC 24 | 2577524784 ps | ||
| T435 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/435.prim_prince_test.2009840682 | Aug 21 02:45:55 AM UTC 24 | Aug 21 02:46:44 AM UTC 24 | 2210660196 ps | ||
| T436 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/442.prim_prince_test.1864019467 | Aug 21 02:46:18 AM UTC 24 | Aug 21 02:46:44 AM UTC 24 | 1151932063 ps | ||
| T437 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/441.prim_prince_test.1708111809 | Aug 21 02:46:18 AM UTC 24 | Aug 21 02:46:48 AM UTC 24 | 1367518237 ps | ||
| T438 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/437.prim_prince_test.3553286610 | Aug 21 02:46:08 AM UTC 24 | Aug 21 02:46:49 AM UTC 24 | 1845421467 ps | ||
| T439 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/445.prim_prince_test.2796396824 | Aug 21 02:46:32 AM UTC 24 | Aug 21 02:46:51 AM UTC 24 | 845339153 ps | ||
| T440 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/446.prim_prince_test.4080073429 | Aug 21 02:46:32 AM UTC 24 | Aug 21 02:46:55 AM UTC 24 | 1014815308 ps | ||
| T441 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/425.prim_prince_test.1639133790 | Aug 21 02:45:38 AM UTC 24 | Aug 21 02:46:56 AM UTC 24 | 3661666305 ps | ||
| T442 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/439.prim_prince_test.3673942003 | Aug 21 02:46:10 AM UTC 24 | Aug 21 02:46:58 AM UTC 24 | 2191148918 ps | ||
| T443 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/427.prim_prince_test.19251443 | Aug 21 02:45:45 AM UTC 24 | Aug 21 02:46:59 AM UTC 24 | 3438563040 ps | ||
| T444 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/454.prim_prince_test.1437836745 | Aug 21 02:46:45 AM UTC 24 | Aug 21 02:47:05 AM UTC 24 | 859580939 ps | ||
| T445 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/452.prim_prince_test.1197594389 | Aug 21 02:46:43 AM UTC 24 | Aug 21 02:47:05 AM UTC 24 | 949925035 ps | ||
| T446 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/438.prim_prince_test.1158319243 | Aug 21 02:46:09 AM UTC 24 | Aug 21 02:47:12 AM UTC 24 | 2844414983 ps | ||
| T447 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/440.prim_prince_test.1155859850 | Aug 21 02:46:18 AM UTC 24 | Aug 21 02:47:14 AM UTC 24 | 2535220448 ps | ||
| T448 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/460.prim_prince_test.2930872059 | Aug 21 02:46:56 AM UTC 24 | Aug 21 02:47:15 AM UTC 24 | 824240795 ps | ||
| T449 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/453.prim_prince_test.2285398278 | Aug 21 02:46:45 AM UTC 24 | Aug 21 02:47:18 AM UTC 24 | 1471124670 ps | ||
| T450 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/462.prim_prince_test.2662615623 | Aug 21 02:46:58 AM UTC 24 | Aug 21 02:47:18 AM UTC 24 | 860799036 ps | ||
| T451 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/455.prim_prince_test.1447752429 | Aug 21 02:46:45 AM UTC 24 | Aug 21 02:47:18 AM UTC 24 | 1503012149 ps | ||
| T452 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/447.prim_prince_test.935286825 | Aug 21 02:46:33 AM UTC 24 | Aug 21 02:47:20 AM UTC 24 | 2175476869 ps | ||
| T453 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/443.prim_prince_test.3422100188 | Aug 21 02:46:24 AM UTC 24 | Aug 21 02:47:23 AM UTC 24 | 2708614836 ps | ||
| T454 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/444.prim_prince_test.1397027623 | Aug 21 02:46:26 AM UTC 24 | Aug 21 02:47:25 AM UTC 24 | 2688914614 ps | ||
| T455 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/464.prim_prince_test.3036334847 | Aug 21 02:47:05 AM UTC 24 | Aug 21 02:47:26 AM UTC 24 | 894969060 ps | ||
| T456 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/465.prim_prince_test.897424773 | Aug 21 02:47:06 AM UTC 24 | Aug 21 02:47:27 AM UTC 24 | 894695634 ps | ||
| T457 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/448.prim_prince_test.3487293279 | Aug 21 02:46:35 AM UTC 24 | Aug 21 02:47:33 AM UTC 24 | 2704416439 ps | ||
| T458 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/468.prim_prince_test.2962226019 | Aug 21 02:47:16 AM UTC 24 | Aug 21 02:47:36 AM UTC 24 | 907421440 ps | ||
| T459 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/451.prim_prince_test.3133694349 | Aug 21 02:46:40 AM UTC 24 | Aug 21 02:47:39 AM UTC 24 | 2689955112 ps | ||
| T460 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/457.prim_prince_test.1713182148 | Aug 21 02:46:49 AM UTC 24 | Aug 21 02:47:42 AM UTC 24 | 2420073762 ps | ||
| T461 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/456.prim_prince_test.3787837646 | Aug 21 02:46:45 AM UTC 24 | Aug 21 02:47:42 AM UTC 24 | 2618356368 ps | ||
| T462 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/450.prim_prince_test.41860187 | Aug 21 02:46:38 AM UTC 24 | Aug 21 02:47:46 AM UTC 24 | 3115702171 ps | ||
| T463 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/463.prim_prince_test.651621084 | Aug 21 02:46:59 AM UTC 24 | Aug 21 02:47:47 AM UTC 24 | 2204143949 ps | ||
| T464 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/470.prim_prince_test.2590826010 | Aug 21 02:47:19 AM UTC 24 | Aug 21 02:47:49 AM UTC 24 | 1310372893 ps | ||
| T465 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/458.prim_prince_test.442074324 | Aug 21 02:46:49 AM UTC 24 | Aug 21 02:47:50 AM UTC 24 | 2772805475 ps | ||
| T466 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/449.prim_prince_test.3410814217 | Aug 21 02:46:37 AM UTC 24 | Aug 21 02:47:57 AM UTC 24 | 3709642628 ps | ||
| T467 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/459.prim_prince_test.449690030 | Aug 21 02:46:51 AM UTC 24 | Aug 21 02:47:57 AM UTC 24 | 3019336568 ps | ||
| T468 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/472.prim_prince_test.2685550609 | Aug 21 02:47:22 AM UTC 24 | Aug 21 02:47:58 AM UTC 24 | 1647607078 ps | ||
| T469 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/476.prim_prince_test.4152464105 | Aug 21 02:47:28 AM UTC 24 | Aug 21 02:48:00 AM UTC 24 | 1450278264 ps | ||
| T470 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/477.prim_prince_test.379821375 | Aug 21 02:47:34 AM UTC 24 | Aug 21 02:48:03 AM UTC 24 | 1270951051 ps | ||
| T471 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/461.prim_prince_test.2632626873 | Aug 21 02:46:57 AM UTC 24 | Aug 21 02:48:04 AM UTC 24 | 3123509994 ps | ||
| T472 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/467.prim_prince_test.1103555402 | Aug 21 02:47:15 AM UTC 24 | Aug 21 02:48:10 AM UTC 24 | 2523412325 ps | ||
| T473 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/471.prim_prince_test.398845675 | Aug 21 02:47:19 AM UTC 24 | Aug 21 02:48:16 AM UTC 24 | 2592948186 ps | ||
| T474 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/466.prim_prince_test.3038542242 | Aug 21 02:47:13 AM UTC 24 | Aug 21 02:48:19 AM UTC 24 | 3038797243 ps | ||
| T475 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/478.prim_prince_test.728108969 | Aug 21 02:47:37 AM UTC 24 | Aug 21 02:48:20 AM UTC 24 | 1931487688 ps | ||
| T476 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/484.prim_prince_test.3489445809 | Aug 21 02:47:49 AM UTC 24 | Aug 21 02:48:22 AM UTC 24 | 1459284123 ps | ||
| T477 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/479.prim_prince_test.2798143220 | Aug 21 02:47:40 AM UTC 24 | Aug 21 02:48:24 AM UTC 24 | 2022846373 ps | ||
| T478 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/473.prim_prince_test.3555847293 | Aug 21 02:47:24 AM UTC 24 | Aug 21 02:48:31 AM UTC 24 | 3105243075 ps | ||
| T479 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/474.prim_prince_test.2351449335 | Aug 21 02:47:26 AM UTC 24 | Aug 21 02:48:34 AM UTC 24 | 3173858091 ps | ||
| T480 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/469.prim_prince_test.2966217681 | Aug 21 02:47:19 AM UTC 24 | Aug 21 02:48:35 AM UTC 24 | 3515142617 ps | ||
| T481 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/487.prim_prince_test.3360438504 | Aug 21 02:47:58 AM UTC 24 | Aug 21 02:48:42 AM UTC 24 | 1990755638 ps | ||
| T482 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/481.prim_prince_test.778738353 | Aug 21 02:47:43 AM UTC 24 | Aug 21 02:48:43 AM UTC 24 | 2777288642 ps | ||
| T483 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/489.prim_prince_test.650030966 | Aug 21 02:48:01 AM UTC 24 | Aug 21 02:48:43 AM UTC 24 | 1907213597 ps | ||
| T484 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/498.prim_prince_test.3508649103 | Aug 21 02:48:25 AM UTC 24 | Aug 21 02:48:43 AM UTC 24 | 817769274 ps | ||
| T485 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/492.prim_prince_test.640887474 | Aug 21 02:48:06 AM UTC 24 | Aug 21 02:48:46 AM UTC 24 | 1859158372 ps | ||
| T486 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/475.prim_prince_test.1852954094 | Aug 21 02:47:27 AM UTC 24 | Aug 21 02:48:47 AM UTC 24 | 3726868034 ps | ||
| T487 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/482.prim_prince_test.797772233 | Aug 21 02:47:46 AM UTC 24 | Aug 21 02:48:49 AM UTC 24 | 2886634467 ps | ||
| T488 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/494.prim_prince_test.47372639 | Aug 21 02:48:16 AM UTC 24 | Aug 21 02:48:51 AM UTC 24 | 1580486241 ps | ||
| T489 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/480.prim_prince_test.3120007903 | Aug 21 02:47:43 AM UTC 24 | Aug 21 02:48:52 AM UTC 24 | 3208043284 ps | ||
| T490 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/499.prim_prince_test.583416343 | Aug 21 02:48:32 AM UTC 24 | Aug 21 02:48:56 AM UTC 24 | 1082503156 ps | ||
| T491 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/497.prim_prince_test.570352515 | Aug 21 02:48:23 AM UTC 24 | Aug 21 02:49:00 AM UTC 24 | 1638429389 ps | ||
| T492 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/483.prim_prince_test.2247753821 | Aug 21 02:47:48 AM UTC 24 | Aug 21 02:49:02 AM UTC 24 | 3384452699 ps | ||
| T493 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/493.prim_prince_test.2377074634 | Aug 21 02:48:11 AM UTC 24 | Aug 21 02:49:03 AM UTC 24 | 2380036733 ps | ||
| T494 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/485.prim_prince_test.4203332875 | Aug 21 02:47:51 AM UTC 24 | Aug 21 02:49:10 AM UTC 24 | 3636267494 ps | ||
| T495 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/486.prim_prince_test.855565544 | Aug 21 02:47:58 AM UTC 24 | Aug 21 02:49:10 AM UTC 24 | 3300260605 ps | ||
| T496 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/495.prim_prince_test.532092064 | Aug 21 02:48:19 AM UTC 24 | Aug 21 02:49:13 AM UTC 24 | 2400732829 ps | ||
| T497 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/488.prim_prince_test.4036189885 | Aug 21 02:47:59 AM UTC 24 | Aug 21 02:49:13 AM UTC 24 | 3385189834 ps | ||
| T498 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/496.prim_prince_test.3400687353 | Aug 21 02:48:20 AM UTC 24 | Aug 21 02:49:13 AM UTC 24 | 2391472126 ps | ||
| T499 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/490.prim_prince_test.2966646907 | Aug 21 02:48:03 AM UTC 24 | Aug 21 02:49:19 AM UTC 24 | 3431921177 ps | ||
| T500 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/491.prim_prince_test.405447487 | Aug 21 02:48:04 AM UTC 24 | Aug 21 02:49:20 AM UTC 24 | 3428148741 ps |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/1.prim_prince_test.2095625659 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 1039114989 ps |
| CPU time | 17.99 seconds |
| Started | Aug 21 02:27:53 AM UTC 24 |
| Finished | Aug 21 02:28:16 AM UTC 24 |
| Peak memory | 154596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2095625659 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_prince_test.2095625659 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/1.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/0.prim_prince_test.1345322200 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 2875811493 ps |
| CPU time | 49.45 seconds |
| Started | Aug 21 02:27:53 AM UTC 24 |
| Finished | Aug 21 02:28:56 AM UTC 24 |
| Peak memory | 154660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1345322200 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_prince_test.1345322200 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/0.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/10.prim_prince_test.1472118714 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 3285285420 ps |
| CPU time | 56.25 seconds |
| Started | Aug 21 02:27:55 AM UTC 24 |
| Finished | Aug 21 02:29:07 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1472118714 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_prince_test.1472118714 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/10.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/100.prim_prince_test.1199552477 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 1171576757 ps |
| CPU time | 20.16 seconds |
| Started | Aug 21 02:32:08 AM UTC 24 |
| Finished | Aug 21 02:32:34 AM UTC 24 |
| Peak memory | 154596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1199552477 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 100.prim_prince_test.1199552477 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/100.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/101.prim_prince_test.16740221 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 3628689824 ps |
| CPU time | 61.46 seconds |
| Started | Aug 21 02:32:09 AM UTC 24 |
| Finished | Aug 21 02:33:28 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=16740221 -assert nopostproc +UVM_TEST NAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pri m_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 101.prim_prince_test.16740221 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/101.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/102.prim_prince_test.4240173861 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 2224134076 ps |
| CPU time | 37.6 seconds |
| Started | Aug 21 02:32:15 AM UTC 24 |
| Finished | Aug 21 02:33:04 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4240173861 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 102.prim_prince_test.4240173861 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/102.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/103.prim_prince_test.2025005042 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 2009917008 ps |
| CPU time | 34.6 seconds |
| Started | Aug 21 02:32:21 AM UTC 24 |
| Finished | Aug 21 02:33:06 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2025005042 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 103.prim_prince_test.2025005042 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/103.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/104.prim_prince_test.3592754876 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 2041920662 ps |
| CPU time | 34.95 seconds |
| Started | Aug 21 02:32:36 AM UTC 24 |
| Finished | Aug 21 02:33:20 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3592754876 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 104.prim_prince_test.3592754876 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/104.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/105.prim_prince_test.2968446790 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 1821084836 ps |
| CPU time | 31.02 seconds |
| Started | Aug 21 02:32:37 AM UTC 24 |
| Finished | Aug 21 02:33:17 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2968446790 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 105.prim_prince_test.2968446790 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/105.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/106.prim_prince_test.4224231889 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 2371564248 ps |
| CPU time | 40.46 seconds |
| Started | Aug 21 02:32:42 AM UTC 24 |
| Finished | Aug 21 02:33:34 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4224231889 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 106.prim_prince_test.4224231889 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/106.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/107.prim_prince_test.1444452163 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 1485018711 ps |
| CPU time | 25.51 seconds |
| Started | Aug 21 02:32:44 AM UTC 24 |
| Finished | Aug 21 02:33:17 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1444452163 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 107.prim_prince_test.1444452163 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/107.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/108.prim_prince_test.1244054965 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 1040861925 ps |
| CPU time | 18.11 seconds |
| Started | Aug 21 02:32:44 AM UTC 24 |
| Finished | Aug 21 02:33:08 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1244054965 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 108.prim_prince_test.1244054965 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/108.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/109.prim_prince_test.742461113 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 1315328197 ps |
| CPU time | 22.55 seconds |
| Started | Aug 21 02:32:49 AM UTC 24 |
| Finished | Aug 21 02:33:18 AM UTC 24 |
| Peak memory | 156052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=742461113 -assert nopostproc +UVM_TES TNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pr im_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 109.prim_prince_test.742461113 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/109.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/11.prim_prince_test.534601915 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 977095898 ps |
| CPU time | 17.06 seconds |
| Started | Aug 21 02:27:55 AM UTC 24 |
| Finished | Aug 21 02:28:17 AM UTC 24 |
| Peak memory | 154596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=534601915 -assert nopostproc +UVM_TES TNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pr im_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_prince_test.534601915 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/11.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/110.prim_prince_test.881728018 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 3335003179 ps |
| CPU time | 56.6 seconds |
| Started | Aug 21 02:32:49 AM UTC 24 |
| Finished | Aug 21 02:34:01 AM UTC 24 |
| Peak memory | 154668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=881728018 -assert nopostproc +UVM_TES TNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pr im_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 110.prim_prince_test.881728018 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/110.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/111.prim_prince_test.1088281883 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 2185945002 ps |
| CPU time | 37.74 seconds |
| Started | Aug 21 02:32:54 AM UTC 24 |
| Finished | Aug 21 02:33:43 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1088281883 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 111.prim_prince_test.1088281883 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/111.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/112.prim_prince_test.935360881 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 1461833572 ps |
| CPU time | 25.24 seconds |
| Started | Aug 21 02:33:00 AM UTC 24 |
| Finished | Aug 21 02:33:33 AM UTC 24 |
| Peak memory | 154604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=935360881 -assert nopostproc +UVM_TES TNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pr im_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 112.prim_prince_test.935360881 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/112.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/113.prim_prince_test.3080867841 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 1190742121 ps |
| CPU time | 20.51 seconds |
| Started | Aug 21 02:33:01 AM UTC 24 |
| Finished | Aug 21 02:33:28 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3080867841 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 113.prim_prince_test.3080867841 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/113.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/114.prim_prince_test.4195432717 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 3478097211 ps |
| CPU time | 58.88 seconds |
| Started | Aug 21 02:33:02 AM UTC 24 |
| Finished | Aug 21 02:34:18 AM UTC 24 |
| Peak memory | 154668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4195432717 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 114.prim_prince_test.4195432717 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/114.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/115.prim_prince_test.3591933836 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 2357206405 ps |
| CPU time | 40.02 seconds |
| Started | Aug 21 02:33:04 AM UTC 24 |
| Finished | Aug 21 02:33:56 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3591933836 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 115.prim_prince_test.3591933836 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/115.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/116.prim_prince_test.1672307239 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 3029347724 ps |
| CPU time | 51.45 seconds |
| Started | Aug 21 02:33:06 AM UTC 24 |
| Finished | Aug 21 02:34:12 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1672307239 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 116.prim_prince_test.1672307239 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/116.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/117.prim_prince_test.1189845617 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 797199699 ps |
| CPU time | 13.95 seconds |
| Started | Aug 21 02:33:07 AM UTC 24 |
| Finished | Aug 21 02:33:26 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1189845617 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 117.prim_prince_test.1189845617 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/117.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/118.prim_prince_test.2318859244 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 3153185375 ps |
| CPU time | 53.65 seconds |
| Started | Aug 21 02:33:09 AM UTC 24 |
| Finished | Aug 21 02:34:17 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2318859244 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 118.prim_prince_test.2318859244 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/118.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/119.prim_prince_test.2735310994 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 1490865963 ps |
| CPU time | 25.51 seconds |
| Started | Aug 21 02:33:09 AM UTC 24 |
| Finished | Aug 21 02:33:42 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2735310994 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 119.prim_prince_test.2735310994 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/119.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/12.prim_prince_test.2834432599 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 1965259558 ps |
| CPU time | 34.06 seconds |
| Started | Aug 21 02:27:55 AM UTC 24 |
| Finished | Aug 21 02:28:39 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2834432599 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_prince_test.2834432599 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/12.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/120.prim_prince_test.396782711 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 1004911531 ps |
| CPU time | 17.32 seconds |
| Started | Aug 21 02:33:13 AM UTC 24 |
| Finished | Aug 21 02:33:36 AM UTC 24 |
| Peak memory | 154604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=396782711 -assert nopostproc +UVM_TES TNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pr im_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 120.prim_prince_test.396782711 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/120.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/121.prim_prince_test.4210926152 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 3314263322 ps |
| CPU time | 55.97 seconds |
| Started | Aug 21 02:33:16 AM UTC 24 |
| Finished | Aug 21 02:34:28 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4210926152 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 121.prim_prince_test.4210926152 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/121.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/122.prim_prince_test.2508435176 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 3665553151 ps |
| CPU time | 62.3 seconds |
| Started | Aug 21 02:33:18 AM UTC 24 |
| Finished | Aug 21 02:34:37 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2508435176 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 122.prim_prince_test.2508435176 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/122.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/123.prim_prince_test.3163661253 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 3298355537 ps |
| CPU time | 56.02 seconds |
| Started | Aug 21 02:33:18 AM UTC 24 |
| Finished | Aug 21 02:34:30 AM UTC 24 |
| Peak memory | 154660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3163661253 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 123.prim_prince_test.3163661253 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/123.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/124.prim_prince_test.140119337 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 779323657 ps |
| CPU time | 13.55 seconds |
| Started | Aug 21 02:33:19 AM UTC 24 |
| Finished | Aug 21 02:33:37 AM UTC 24 |
| Peak memory | 154608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=140119337 -assert nopostproc +UVM_TES TNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pr im_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 124.prim_prince_test.140119337 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/124.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/125.prim_prince_test.3765922210 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 944703557 ps |
| CPU time | 16.46 seconds |
| Started | Aug 21 02:33:21 AM UTC 24 |
| Finished | Aug 21 02:33:43 AM UTC 24 |
| Peak memory | 154604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3765922210 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 125.prim_prince_test.3765922210 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/125.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/126.prim_prince_test.435622463 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 881812951 ps |
| CPU time | 15.47 seconds |
| Started | Aug 21 02:33:27 AM UTC 24 |
| Finished | Aug 21 02:33:47 AM UTC 24 |
| Peak memory | 154604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=435622463 -assert nopostproc +UVM_TES TNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pr im_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 126.prim_prince_test.435622463 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/126.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/127.prim_prince_test.3614867941 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 1646695033 ps |
| CPU time | 28.13 seconds |
| Started | Aug 21 02:33:28 AM UTC 24 |
| Finished | Aug 21 02:34:05 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3614867941 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 127.prim_prince_test.3614867941 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/127.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/128.prim_prince_test.3304748496 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 1336607101 ps |
| CPU time | 23.1 seconds |
| Started | Aug 21 02:33:29 AM UTC 24 |
| Finished | Aug 21 02:33:59 AM UTC 24 |
| Peak memory | 154604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3304748496 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 128.prim_prince_test.3304748496 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/128.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/129.prim_prince_test.1252932161 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 1402187725 ps |
| CPU time | 24.14 seconds |
| Started | Aug 21 02:33:29 AM UTC 24 |
| Finished | Aug 21 02:34:01 AM UTC 24 |
| Peak memory | 154596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1252932161 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 129.prim_prince_test.1252932161 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/129.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/13.prim_prince_test.2026470106 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 886978272 ps |
| CPU time | 15.91 seconds |
| Started | Aug 21 02:27:55 AM UTC 24 |
| Finished | Aug 21 02:28:16 AM UTC 24 |
| Peak memory | 154652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2026470106 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_prince_test.2026470106 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/13.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/130.prim_prince_test.736904038 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 949149016 ps |
| CPU time | 16.53 seconds |
| Started | Aug 21 02:33:34 AM UTC 24 |
| Finished | Aug 21 02:33:56 AM UTC 24 |
| Peak memory | 154604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=736904038 -assert nopostproc +UVM_TES TNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pr im_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 130.prim_prince_test.736904038 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/130.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/131.prim_prince_test.1573137938 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 1457272344 ps |
| CPU time | 24.67 seconds |
| Started | Aug 21 02:33:35 AM UTC 24 |
| Finished | Aug 21 02:34:07 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1573137938 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 131.prim_prince_test.1573137938 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/131.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/132.prim_prince_test.913167129 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 3350596514 ps |
| CPU time | 57.32 seconds |
| Started | Aug 21 02:33:36 AM UTC 24 |
| Finished | Aug 21 02:34:50 AM UTC 24 |
| Peak memory | 154672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=913167129 -assert nopostproc +UVM_TES TNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pr im_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 132.prim_prince_test.913167129 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/132.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/133.prim_prince_test.865154998 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 1546288986 ps |
| CPU time | 26.44 seconds |
| Started | Aug 21 02:33:37 AM UTC 24 |
| Finished | Aug 21 02:34:12 AM UTC 24 |
| Peak memory | 154604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=865154998 -assert nopostproc +UVM_TES TNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pr im_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 133.prim_prince_test.865154998 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/133.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/134.prim_prince_test.3785131923 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 3543609727 ps |
| CPU time | 60.03 seconds |
| Started | Aug 21 02:33:43 AM UTC 24 |
| Finished | Aug 21 02:34:59 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3785131923 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 134.prim_prince_test.3785131923 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/134.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/135.prim_prince_test.3094722904 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 3423616268 ps |
| CPU time | 57.93 seconds |
| Started | Aug 21 02:33:44 AM UTC 24 |
| Finished | Aug 21 02:34:58 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3094722904 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 135.prim_prince_test.3094722904 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/135.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/136.prim_prince_test.2074691771 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 3121561367 ps |
| CPU time | 52.82 seconds |
| Started | Aug 21 02:33:44 AM UTC 24 |
| Finished | Aug 21 02:34:52 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2074691771 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 136.prim_prince_test.2074691771 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/136.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/137.prim_prince_test.2473539355 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 3673219477 ps |
| CPU time | 62.3 seconds |
| Started | Aug 21 02:33:48 AM UTC 24 |
| Finished | Aug 21 02:35:07 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2473539355 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 137.prim_prince_test.2473539355 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/137.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/138.prim_prince_test.2439267673 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 2464786840 ps |
| CPU time | 41.58 seconds |
| Started | Aug 21 02:33:57 AM UTC 24 |
| Finished | Aug 21 02:34:51 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2439267673 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 138.prim_prince_test.2439267673 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/138.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/139.prim_prince_test.3341051762 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 3399286234 ps |
| CPU time | 57.92 seconds |
| Started | Aug 21 02:33:57 AM UTC 24 |
| Finished | Aug 21 02:35:11 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3341051762 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 139.prim_prince_test.3341051762 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/139.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/14.prim_prince_test.1490958856 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 1647835944 ps |
| CPU time | 29.12 seconds |
| Started | Aug 21 02:27:56 AM UTC 24 |
| Finished | Aug 21 02:28:33 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1490958856 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_prince_test.1490958856 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/14.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/140.prim_prince_test.1099144622 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 1177560006 ps |
| CPU time | 20.34 seconds |
| Started | Aug 21 02:34:00 AM UTC 24 |
| Finished | Aug 21 02:34:27 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1099144622 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 140.prim_prince_test.1099144622 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/140.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/141.prim_prince_test.868288301 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 2154191863 ps |
| CPU time | 36.7 seconds |
| Started | Aug 21 02:34:01 AM UTC 24 |
| Finished | Aug 21 02:34:48 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=868288301 -assert nopostproc +UVM_TES TNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pr im_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 141.prim_prince_test.868288301 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/141.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/142.prim_prince_test.3548211939 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 1451162576 ps |
| CPU time | 24.61 seconds |
| Started | Aug 21 02:34:02 AM UTC 24 |
| Finished | Aug 21 02:34:34 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3548211939 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 142.prim_prince_test.3548211939 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/142.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/143.prim_prince_test.4199538162 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 936217925 ps |
| CPU time | 16.11 seconds |
| Started | Aug 21 02:34:05 AM UTC 24 |
| Finished | Aug 21 02:34:27 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4199538162 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 143.prim_prince_test.4199538162 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/143.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/144.prim_prince_test.1366063835 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 1491841573 ps |
| CPU time | 25.52 seconds |
| Started | Aug 21 02:34:08 AM UTC 24 |
| Finished | Aug 21 02:34:42 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1366063835 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 144.prim_prince_test.1366063835 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/144.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/145.prim_prince_test.1533962025 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 1372107065 ps |
| CPU time | 23.42 seconds |
| Started | Aug 21 02:34:12 AM UTC 24 |
| Finished | Aug 21 02:34:43 AM UTC 24 |
| Peak memory | 156056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1533962025 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 145.prim_prince_test.1533962025 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/145.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/146.prim_prince_test.19589461 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 3564350718 ps |
| CPU time | 60.59 seconds |
| Started | Aug 21 02:34:13 AM UTC 24 |
| Finished | Aug 21 02:35:31 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=19589461 -assert nopostproc +UVM_TEST NAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pri m_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 146.prim_prince_test.19589461 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/146.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/147.prim_prince_test.3014720624 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 2272686828 ps |
| CPU time | 38.45 seconds |
| Started | Aug 21 02:34:19 AM UTC 24 |
| Finished | Aug 21 02:35:09 AM UTC 24 |
| Peak memory | 154668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3014720624 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 147.prim_prince_test.3014720624 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/147.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/148.prim_prince_test.2252693684 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 3709298486 ps |
| CPU time | 62.62 seconds |
| Started | Aug 21 02:34:19 AM UTC 24 |
| Finished | Aug 21 02:35:39 AM UTC 24 |
| Peak memory | 154668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2252693684 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 148.prim_prince_test.2252693684 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/148.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/149.prim_prince_test.167447124 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 2203826549 ps |
| CPU time | 37.24 seconds |
| Started | Aug 21 02:34:28 AM UTC 24 |
| Finished | Aug 21 02:35:16 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=167447124 -assert nopostproc +UVM_TES TNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pr im_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 149.prim_prince_test.167447124 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/149.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/15.prim_prince_test.4228337761 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 900008707 ps |
| CPU time | 15.97 seconds |
| Started | Aug 21 02:28:16 AM UTC 24 |
| Finished | Aug 21 02:28:37 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4228337761 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_prince_test.4228337761 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/15.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/150.prim_prince_test.2810216278 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 1821571475 ps |
| CPU time | 30.99 seconds |
| Started | Aug 21 02:34:28 AM UTC 24 |
| Finished | Aug 21 02:35:08 AM UTC 24 |
| Peak memory | 154604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2810216278 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 150.prim_prince_test.2810216278 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/150.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/151.prim_prince_test.608695660 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 2560382904 ps |
| CPU time | 43.41 seconds |
| Started | Aug 21 02:34:29 AM UTC 24 |
| Finished | Aug 21 02:35:25 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=608695660 -assert nopostproc +UVM_TES TNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pr im_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 151.prim_prince_test.608695660 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/151.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/152.prim_prince_test.3455524423 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 1022950790 ps |
| CPU time | 17.6 seconds |
| Started | Aug 21 02:34:30 AM UTC 24 |
| Finished | Aug 21 02:34:53 AM UTC 24 |
| Peak memory | 154604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3455524423 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 152.prim_prince_test.3455524423 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/152.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/153.prim_prince_test.1959432899 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 1016443380 ps |
| CPU time | 17.81 seconds |
| Started | Aug 21 02:34:35 AM UTC 24 |
| Finished | Aug 21 02:34:59 AM UTC 24 |
| Peak memory | 154604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1959432899 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 153.prim_prince_test.1959432899 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/153.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/154.prim_prince_test.2474932360 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 2145115831 ps |
| CPU time | 36.33 seconds |
| Started | Aug 21 02:34:38 AM UTC 24 |
| Finished | Aug 21 02:35:25 AM UTC 24 |
| Peak memory | 154604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2474932360 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 154.prim_prince_test.2474932360 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/154.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/155.prim_prince_test.4151193352 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 2491269498 ps |
| CPU time | 42.22 seconds |
| Started | Aug 21 02:34:42 AM UTC 24 |
| Finished | Aug 21 02:35:37 AM UTC 24 |
| Peak memory | 154668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4151193352 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 155.prim_prince_test.4151193352 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/155.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/156.prim_prince_test.974465935 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 2140648253 ps |
| CPU time | 36.46 seconds |
| Started | Aug 21 02:34:44 AM UTC 24 |
| Finished | Aug 21 02:35:31 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=974465935 -assert nopostproc +UVM_TES TNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pr im_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 156.prim_prince_test.974465935 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/156.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/157.prim_prince_test.2062158259 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 2213604015 ps |
| CPU time | 37.83 seconds |
| Started | Aug 21 02:34:49 AM UTC 24 |
| Finished | Aug 21 02:35:38 AM UTC 24 |
| Peak memory | 154668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2062158259 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 157.prim_prince_test.2062158259 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/157.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/158.prim_prince_test.3652603780 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 3478383527 ps |
| CPU time | 58.48 seconds |
| Started | Aug 21 02:34:50 AM UTC 24 |
| Finished | Aug 21 02:36:05 AM UTC 24 |
| Peak memory | 154668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3652603780 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 158.prim_prince_test.3652603780 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/158.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/159.prim_prince_test.2355240524 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 2003766448 ps |
| CPU time | 34.2 seconds |
| Started | Aug 21 02:34:51 AM UTC 24 |
| Finished | Aug 21 02:35:36 AM UTC 24 |
| Peak memory | 154604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2355240524 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 159.prim_prince_test.2355240524 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/159.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/16.prim_prince_test.358003757 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 3286306402 ps |
| CPU time | 56.15 seconds |
| Started | Aug 21 02:28:17 AM UTC 24 |
| Finished | Aug 21 02:29:29 AM UTC 24 |
| Peak memory | 154660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=358003757 -assert nopostproc +UVM_TES TNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pr im_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_prince_test.358003757 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/16.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/160.prim_prince_test.2268513807 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 3463704385 ps |
| CPU time | 58.8 seconds |
| Started | Aug 21 02:34:53 AM UTC 24 |
| Finished | Aug 21 02:36:08 AM UTC 24 |
| Peak memory | 154668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2268513807 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 160.prim_prince_test.2268513807 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/160.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/161.prim_prince_test.3339580581 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 2232046971 ps |
| CPU time | 37.77 seconds |
| Started | Aug 21 02:34:54 AM UTC 24 |
| Finished | Aug 21 02:35:42 AM UTC 24 |
| Peak memory | 154668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3339580581 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 161.prim_prince_test.3339580581 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/161.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/162.prim_prince_test.3317411542 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 2938616163 ps |
| CPU time | 49.94 seconds |
| Started | Aug 21 02:34:59 AM UTC 24 |
| Finished | Aug 21 02:36:03 AM UTC 24 |
| Peak memory | 154668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3317411542 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 162.prim_prince_test.3317411542 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/162.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/163.prim_prince_test.352971659 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 829240775 ps |
| CPU time | 14.6 seconds |
| Started | Aug 21 02:35:00 AM UTC 24 |
| Finished | Aug 21 02:35:19 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=352971659 -assert nopostproc +UVM_TES TNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pr im_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 163.prim_prince_test.352971659 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/163.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/164.prim_prince_test.4193153345 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 2965659719 ps |
| CPU time | 50.01 seconds |
| Started | Aug 21 02:35:00 AM UTC 24 |
| Finished | Aug 21 02:36:04 AM UTC 24 |
| Peak memory | 154668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4193153345 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 164.prim_prince_test.4193153345 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/164.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/165.prim_prince_test.612482368 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 3705572429 ps |
| CPU time | 62.77 seconds |
| Started | Aug 21 02:35:08 AM UTC 24 |
| Finished | Aug 21 02:36:28 AM UTC 24 |
| Peak memory | 154668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=612482368 -assert nopostproc +UVM_TES TNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pr im_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 165.prim_prince_test.612482368 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/165.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/166.prim_prince_test.697962803 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 1506268197 ps |
| CPU time | 25.84 seconds |
| Started | Aug 21 02:35:09 AM UTC 24 |
| Finished | Aug 21 02:35:43 AM UTC 24 |
| Peak memory | 156052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=697962803 -assert nopostproc +UVM_TES TNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pr im_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 166.prim_prince_test.697962803 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/166.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/167.prim_prince_test.1178438217 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 2947226032 ps |
| CPU time | 49.45 seconds |
| Started | Aug 21 02:35:10 AM UTC 24 |
| Finished | Aug 21 02:36:14 AM UTC 24 |
| Peak memory | 154668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1178438217 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 167.prim_prince_test.1178438217 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/167.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/168.prim_prince_test.3469453933 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 1364677284 ps |
| CPU time | 23.46 seconds |
| Started | Aug 21 02:35:12 AM UTC 24 |
| Finished | Aug 21 02:35:43 AM UTC 24 |
| Peak memory | 154604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3469453933 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 168.prim_prince_test.3469453933 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/168.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/169.prim_prince_test.1924886784 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 3391571757 ps |
| CPU time | 57.27 seconds |
| Started | Aug 21 02:35:16 AM UTC 24 |
| Finished | Aug 21 02:36:30 AM UTC 24 |
| Peak memory | 154668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1924886784 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 169.prim_prince_test.1924886784 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/169.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/17.prim_prince_test.1647422379 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 2250260257 ps |
| CPU time | 38.94 seconds |
| Started | Aug 21 02:28:19 AM UTC 24 |
| Finished | Aug 21 02:29:08 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1647422379 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_prince_test.1647422379 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/17.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/170.prim_prince_test.157111723 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 3158444009 ps |
| CPU time | 53.77 seconds |
| Started | Aug 21 02:35:20 AM UTC 24 |
| Finished | Aug 21 02:36:29 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=157111723 -assert nopostproc +UVM_TES TNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pr im_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 170.prim_prince_test.157111723 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/170.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/171.prim_prince_test.1702817994 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 3441046528 ps |
| CPU time | 57.97 seconds |
| Started | Aug 21 02:35:23 AM UTC 24 |
| Finished | Aug 21 02:36:38 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1702817994 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 171.prim_prince_test.1702817994 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/171.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/172.prim_prince_test.3782201240 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 3319574306 ps |
| CPU time | 55.92 seconds |
| Started | Aug 21 02:35:26 AM UTC 24 |
| Finished | Aug 21 02:36:37 AM UTC 24 |
| Peak memory | 154472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3782201240 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 172.prim_prince_test.3782201240 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/172.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/173.prim_prince_test.2905580506 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 3167525831 ps |
| CPU time | 53.09 seconds |
| Started | Aug 21 02:35:26 AM UTC 24 |
| Finished | Aug 21 02:36:34 AM UTC 24 |
| Peak memory | 154440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2905580506 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 173.prim_prince_test.2905580506 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/173.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/174.prim_prince_test.3489005550 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 2076109277 ps |
| CPU time | 35.59 seconds |
| Started | Aug 21 02:35:32 AM UTC 24 |
| Finished | Aug 21 02:36:18 AM UTC 24 |
| Peak memory | 154604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3489005550 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 174.prim_prince_test.3489005550 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/174.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/175.prim_prince_test.3198029783 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 2049220976 ps |
| CPU time | 34.25 seconds |
| Started | Aug 21 02:35:32 AM UTC 24 |
| Finished | Aug 21 02:36:16 AM UTC 24 |
| Peak memory | 154604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3198029783 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 175.prim_prince_test.3198029783 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/175.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/176.prim_prince_test.3469301209 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 2804712347 ps |
| CPU time | 47.27 seconds |
| Started | Aug 21 02:35:37 AM UTC 24 |
| Finished | Aug 21 02:36:38 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3469301209 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 176.prim_prince_test.3469301209 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/176.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/177.prim_prince_test.982663823 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 2353760462 ps |
| CPU time | 40.07 seconds |
| Started | Aug 21 02:35:37 AM UTC 24 |
| Finished | Aug 21 02:36:28 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=982663823 -assert nopostproc +UVM_TES TNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pr im_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 177.prim_prince_test.982663823 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/177.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/178.prim_prince_test.3299632984 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 959521935 ps |
| CPU time | 16.49 seconds |
| Started | Aug 21 02:35:39 AM UTC 24 |
| Finished | Aug 21 02:36:01 AM UTC 24 |
| Peak memory | 154604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3299632984 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 178.prim_prince_test.3299632984 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/178.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/179.prim_prince_test.4239842753 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 1332147702 ps |
| CPU time | 23.3 seconds |
| Started | Aug 21 02:35:40 AM UTC 24 |
| Finished | Aug 21 02:36:10 AM UTC 24 |
| Peak memory | 154604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4239842753 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 179.prim_prince_test.4239842753 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/179.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/18.prim_prince_test.3801725217 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 759862198 ps |
| CPU time | 13.38 seconds |
| Started | Aug 21 02:28:24 AM UTC 24 |
| Finished | Aug 21 02:28:41 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3801725217 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_prince_test.3801725217 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/18.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/180.prim_prince_test.4022704194 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 783021083 ps |
| CPU time | 13.49 seconds |
| Started | Aug 21 02:35:43 AM UTC 24 |
| Finished | Aug 21 02:36:01 AM UTC 24 |
| Peak memory | 154604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4022704194 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 180.prim_prince_test.4022704194 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/180.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/181.prim_prince_test.887678360 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 3075908767 ps |
| CPU time | 52.16 seconds |
| Started | Aug 21 02:35:43 AM UTC 24 |
| Finished | Aug 21 02:36:50 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=887678360 -assert nopostproc +UVM_TES TNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pr im_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 181.prim_prince_test.887678360 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/181.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/182.prim_prince_test.18992141 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 1231336578 ps |
| CPU time | 21.47 seconds |
| Started | Aug 21 02:35:43 AM UTC 24 |
| Finished | Aug 21 02:36:11 AM UTC 24 |
| Peak memory | 154604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=18992141 -assert nopostproc +UVM_TEST NAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pri m_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 182.prim_prince_test.18992141 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/182.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/183.prim_prince_test.4148330261 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 3659335039 ps |
| CPU time | 61.56 seconds |
| Started | Aug 21 02:36:02 AM UTC 24 |
| Finished | Aug 21 02:37:21 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4148330261 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 183.prim_prince_test.4148330261 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/183.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/184.prim_prince_test.2745454960 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 1772339319 ps |
| CPU time | 30.04 seconds |
| Started | Aug 21 02:36:02 AM UTC 24 |
| Finished | Aug 21 02:36:41 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2745454960 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 184.prim_prince_test.2745454960 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/184.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/185.prim_prince_test.1332125662 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 968232458 ps |
| CPU time | 16.49 seconds |
| Started | Aug 21 02:36:04 AM UTC 24 |
| Finished | Aug 21 02:36:26 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1332125662 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 185.prim_prince_test.1332125662 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/185.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/186.prim_prince_test.2103085709 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 3735589780 ps |
| CPU time | 62.54 seconds |
| Started | Aug 21 02:36:05 AM UTC 24 |
| Finished | Aug 21 02:37:25 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2103085709 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 186.prim_prince_test.2103085709 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/186.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/187.prim_prince_test.877351649 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 1214718841 ps |
| CPU time | 20.66 seconds |
| Started | Aug 21 02:36:06 AM UTC 24 |
| Finished | Aug 21 02:36:33 AM UTC 24 |
| Peak memory | 154604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=877351649 -assert nopostproc +UVM_TES TNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pr im_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 187.prim_prince_test.877351649 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/187.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/188.prim_prince_test.640224593 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 1921300811 ps |
| CPU time | 32.61 seconds |
| Started | Aug 21 02:36:09 AM UTC 24 |
| Finished | Aug 21 02:36:51 AM UTC 24 |
| Peak memory | 154604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=640224593 -assert nopostproc +UVM_TES TNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pr im_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 188.prim_prince_test.640224593 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/188.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/189.prim_prince_test.106163006 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 1329471229 ps |
| CPU time | 22.96 seconds |
| Started | Aug 21 02:36:11 AM UTC 24 |
| Finished | Aug 21 02:36:41 AM UTC 24 |
| Peak memory | 154604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=106163006 -assert nopostproc +UVM_TES TNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pr im_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 189.prim_prince_test.106163006 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/189.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/19.prim_prince_test.2424690615 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 1170682109 ps |
| CPU time | 20.71 seconds |
| Started | Aug 21 02:28:34 AM UTC 24 |
| Finished | Aug 21 02:29:00 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2424690615 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_prince_test.2424690615 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/19.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/190.prim_prince_test.162213062 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 3725509432 ps |
| CPU time | 63.27 seconds |
| Started | Aug 21 02:36:12 AM UTC 24 |
| Finished | Aug 21 02:37:33 AM UTC 24 |
| Peak memory | 154668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=162213062 -assert nopostproc +UVM_TES TNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pr im_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 190.prim_prince_test.162213062 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/190.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/191.prim_prince_test.3295594087 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 2518607125 ps |
| CPU time | 42.2 seconds |
| Started | Aug 21 02:36:14 AM UTC 24 |
| Finished | Aug 21 02:37:09 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3295594087 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 191.prim_prince_test.3295594087 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/191.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/192.prim_prince_test.1365177867 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 2199301878 ps |
| CPU time | 36.87 seconds |
| Started | Aug 21 02:36:17 AM UTC 24 |
| Finished | Aug 21 02:37:06 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1365177867 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 192.prim_prince_test.1365177867 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/192.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/193.prim_prince_test.3741212950 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 2580786758 ps |
| CPU time | 43.93 seconds |
| Started | Aug 21 02:36:18 AM UTC 24 |
| Finished | Aug 21 02:37:15 AM UTC 24 |
| Peak memory | 154652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3741212950 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 193.prim_prince_test.3741212950 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/193.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/194.prim_prince_test.2620723348 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 2395762533 ps |
| CPU time | 40.81 seconds |
| Started | Aug 21 02:36:27 AM UTC 24 |
| Finished | Aug 21 02:37:19 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2620723348 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 194.prim_prince_test.2620723348 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/194.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/195.prim_prince_test.268665750 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 897540244 ps |
| CPU time | 15.65 seconds |
| Started | Aug 21 02:36:30 AM UTC 24 |
| Finished | Aug 21 02:36:50 AM UTC 24 |
| Peak memory | 154604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=268665750 -assert nopostproc +UVM_TES TNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pr im_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 195.prim_prince_test.268665750 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/195.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/196.prim_prince_test.960202297 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 2515742508 ps |
| CPU time | 42.15 seconds |
| Started | Aug 21 02:36:30 AM UTC 24 |
| Finished | Aug 21 02:37:24 AM UTC 24 |
| Peak memory | 154668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=960202297 -assert nopostproc +UVM_TES TNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pr im_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 196.prim_prince_test.960202297 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/196.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/197.prim_prince_test.3039628148 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 818323975 ps |
| CPU time | 14.37 seconds |
| Started | Aug 21 02:36:31 AM UTC 24 |
| Finished | Aug 21 02:36:50 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3039628148 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 197.prim_prince_test.3039628148 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/197.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/198.prim_prince_test.4028493368 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 1370977344 ps |
| CPU time | 23.36 seconds |
| Started | Aug 21 02:36:31 AM UTC 24 |
| Finished | Aug 21 02:37:01 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4028493368 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 198.prim_prince_test.4028493368 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/198.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/199.prim_prince_test.15248053 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 2194890487 ps |
| CPU time | 36.93 seconds |
| Started | Aug 21 02:36:34 AM UTC 24 |
| Finished | Aug 21 02:37:22 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=15248053 -assert nopostproc +UVM_TEST NAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pri m_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 199.prim_prince_test.15248053 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/199.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/2.prim_prince_test.2602498311 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 3725173948 ps |
| CPU time | 64.22 seconds |
| Started | Aug 21 02:27:53 AM UTC 24 |
| Finished | Aug 21 02:29:14 AM UTC 24 |
| Peak memory | 154660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2602498311 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_prince_test.2602498311 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/2.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/20.prim_prince_test.214545533 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 2003716813 ps |
| CPU time | 34.52 seconds |
| Started | Aug 21 02:28:37 AM UTC 24 |
| Finished | Aug 21 02:29:21 AM UTC 24 |
| Peak memory | 154596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=214545533 -assert nopostproc +UVM_TES TNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pr im_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_prince_test.214545533 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/20.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/200.prim_prince_test.3127948574 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 2416994011 ps |
| CPU time | 40.94 seconds |
| Started | Aug 21 02:36:35 AM UTC 24 |
| Finished | Aug 21 02:37:28 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3127948574 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 200.prim_prince_test.3127948574 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/200.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/201.prim_prince_test.2476104791 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 2951442761 ps |
| CPU time | 49.6 seconds |
| Started | Aug 21 02:36:38 AM UTC 24 |
| Finished | Aug 21 02:37:42 AM UTC 24 |
| Peak memory | 154660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2476104791 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 201.prim_prince_test.2476104791 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/201.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/202.prim_prince_test.3916514779 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 1865247358 ps |
| CPU time | 32.04 seconds |
| Started | Aug 21 02:36:38 AM UTC 24 |
| Finished | Aug 21 02:37:20 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3916514779 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 202.prim_prince_test.3916514779 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/202.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/203.prim_prince_test.3493121451 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 2068907498 ps |
| CPU time | 35.01 seconds |
| Started | Aug 21 02:36:39 AM UTC 24 |
| Finished | Aug 21 02:37:25 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3493121451 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 203.prim_prince_test.3493121451 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/203.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/204.prim_prince_test.3070721513 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 2748909675 ps |
| CPU time | 46.59 seconds |
| Started | Aug 21 02:36:42 AM UTC 24 |
| Finished | Aug 21 02:37:42 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3070721513 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 204.prim_prince_test.3070721513 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/204.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/205.prim_prince_test.3665523827 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 852551367 ps |
| CPU time | 14.78 seconds |
| Started | Aug 21 02:36:42 AM UTC 24 |
| Finished | Aug 21 02:37:02 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3665523827 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 205.prim_prince_test.3665523827 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/205.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/206.prim_prince_test.2678743993 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 1407478167 ps |
| CPU time | 24.45 seconds |
| Started | Aug 21 02:36:51 AM UTC 24 |
| Finished | Aug 21 02:37:22 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2678743993 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 206.prim_prince_test.2678743993 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/206.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/207.prim_prince_test.2758657757 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 2214812349 ps |
| CPU time | 37.97 seconds |
| Started | Aug 21 02:36:52 AM UTC 24 |
| Finished | Aug 21 02:37:41 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2758657757 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 207.prim_prince_test.2758657757 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/207.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/208.prim_prince_test.3325759583 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 2765951882 ps |
| CPU time | 46.82 seconds |
| Started | Aug 21 02:36:52 AM UTC 24 |
| Finished | Aug 21 02:37:52 AM UTC 24 |
| Peak memory | 156116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3325759583 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 208.prim_prince_test.3325759583 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/208.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/209.prim_prince_test.3757986185 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 2086787785 ps |
| CPU time | 34.96 seconds |
| Started | Aug 21 02:36:52 AM UTC 24 |
| Finished | Aug 21 02:37:37 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3757986185 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 209.prim_prince_test.3757986185 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/209.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/21.prim_prince_test.4120325110 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 2152073701 ps |
| CPU time | 36.82 seconds |
| Started | Aug 21 02:28:37 AM UTC 24 |
| Finished | Aug 21 02:29:24 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4120325110 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_prince_test.4120325110 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/21.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/210.prim_prince_test.2039099927 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 2319261433 ps |
| CPU time | 39.39 seconds |
| Started | Aug 21 02:37:02 AM UTC 24 |
| Finished | Aug 21 02:37:53 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2039099927 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 210.prim_prince_test.2039099927 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/210.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/211.prim_prince_test.1545336430 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 963505472 ps |
| CPU time | 16.67 seconds |
| Started | Aug 21 02:37:03 AM UTC 24 |
| Finished | Aug 21 02:37:25 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1545336430 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 211.prim_prince_test.1545336430 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/211.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/212.prim_prince_test.3066473181 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 2451722234 ps |
| CPU time | 41.28 seconds |
| Started | Aug 21 02:37:06 AM UTC 24 |
| Finished | Aug 21 02:37:59 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3066473181 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 212.prim_prince_test.3066473181 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/212.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/213.prim_prince_test.3264835740 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 1320218533 ps |
| CPU time | 22.61 seconds |
| Started | Aug 21 02:37:10 AM UTC 24 |
| Finished | Aug 21 02:37:40 AM UTC 24 |
| Peak memory | 154596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3264835740 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 213.prim_prince_test.3264835740 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/213.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/214.prim_prince_test.3122740824 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 3417845601 ps |
| CPU time | 58.05 seconds |
| Started | Aug 21 02:37:16 AM UTC 24 |
| Finished | Aug 21 02:38:31 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3122740824 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 214.prim_prince_test.3122740824 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/214.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/215.prim_prince_test.2177834192 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 2074971927 ps |
| CPU time | 35.26 seconds |
| Started | Aug 21 02:37:19 AM UTC 24 |
| Finished | Aug 21 02:38:05 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2177834192 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 215.prim_prince_test.2177834192 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/215.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/216.prim_prince_test.575474236 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 2834809182 ps |
| CPU time | 47.86 seconds |
| Started | Aug 21 02:37:20 AM UTC 24 |
| Finished | Aug 21 02:38:22 AM UTC 24 |
| Peak memory | 154672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=575474236 -assert nopostproc +UVM_TES TNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pr im_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 216.prim_prince_test.575474236 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/216.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/217.prim_prince_test.4271037768 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 1999124970 ps |
| CPU time | 34.07 seconds |
| Started | Aug 21 02:37:22 AM UTC 24 |
| Finished | Aug 21 02:38:06 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4271037768 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 217.prim_prince_test.4271037768 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/217.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/218.prim_prince_test.473846855 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 1092416074 ps |
| CPU time | 18.88 seconds |
| Started | Aug 21 02:37:23 AM UTC 24 |
| Finished | Aug 21 02:37:48 AM UTC 24 |
| Peak memory | 154604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=473846855 -assert nopostproc +UVM_TES TNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pr im_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 218.prim_prince_test.473846855 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/218.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/219.prim_prince_test.363708809 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 3135015934 ps |
| CPU time | 53.31 seconds |
| Started | Aug 21 02:37:23 AM UTC 24 |
| Finished | Aug 21 02:38:31 AM UTC 24 |
| Peak memory | 154668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=363708809 -assert nopostproc +UVM_TES TNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pr im_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 219.prim_prince_test.363708809 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/219.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/22.prim_prince_test.1673272159 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 1747277080 ps |
| CPU time | 30 seconds |
| Started | Aug 21 02:28:38 AM UTC 24 |
| Finished | Aug 21 02:29:16 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1673272159 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_prince_test.1673272159 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/22.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/220.prim_prince_test.2151268205 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 2321170598 ps |
| CPU time | 39.09 seconds |
| Started | Aug 21 02:37:25 AM UTC 24 |
| Finished | Aug 21 02:38:15 AM UTC 24 |
| Peak memory | 154648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2151268205 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 220.prim_prince_test.2151268205 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/220.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/221.prim_prince_test.1659937893 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 1987450204 ps |
| CPU time | 33.79 seconds |
| Started | Aug 21 02:37:26 AM UTC 24 |
| Finished | Aug 21 02:38:10 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1659937893 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 221.prim_prince_test.1659937893 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/221.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/222.prim_prince_test.3987839614 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 1111692884 ps |
| CPU time | 19.1 seconds |
| Started | Aug 21 02:37:26 AM UTC 24 |
| Finished | Aug 21 02:37:51 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3987839614 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 222.prim_prince_test.3987839614 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/222.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/223.prim_prince_test.3819062620 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 2145918381 ps |
| CPU time | 36.44 seconds |
| Started | Aug 21 02:37:26 AM UTC 24 |
| Finished | Aug 21 02:38:13 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3819062620 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 223.prim_prince_test.3819062620 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/223.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/224.prim_prince_test.3373476108 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 2937238693 ps |
| CPU time | 49.38 seconds |
| Started | Aug 21 02:37:29 AM UTC 24 |
| Finished | Aug 21 02:38:33 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3373476108 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 224.prim_prince_test.3373476108 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/224.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/225.prim_prince_test.2109508163 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 2618019579 ps |
| CPU time | 44.37 seconds |
| Started | Aug 21 02:37:34 AM UTC 24 |
| Finished | Aug 21 02:38:31 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2109508163 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 225.prim_prince_test.2109508163 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/225.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/226.prim_prince_test.3228597013 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 1734424006 ps |
| CPU time | 29.53 seconds |
| Started | Aug 21 02:37:37 AM UTC 24 |
| Finished | Aug 21 02:38:16 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3228597013 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 226.prim_prince_test.3228597013 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/226.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/227.prim_prince_test.2934180479 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 2518695879 ps |
| CPU time | 43.02 seconds |
| Started | Aug 21 02:37:41 AM UTC 24 |
| Finished | Aug 21 02:38:36 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2934180479 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 227.prim_prince_test.2934180479 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/227.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/228.prim_prince_test.1592421322 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 880970192 ps |
| CPU time | 15.3 seconds |
| Started | Aug 21 02:37:42 AM UTC 24 |
| Finished | Aug 21 02:38:02 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1592421322 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 228.prim_prince_test.1592421322 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/228.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/229.prim_prince_test.2973694140 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 3002048346 ps |
| CPU time | 50.51 seconds |
| Started | Aug 21 02:37:43 AM UTC 24 |
| Finished | Aug 21 02:38:47 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2973694140 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 229.prim_prince_test.2973694140 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/229.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/23.prim_prince_test.1905596990 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 1141190776 ps |
| CPU time | 19.55 seconds |
| Started | Aug 21 02:28:40 AM UTC 24 |
| Finished | Aug 21 02:29:05 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1905596990 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_prince_test.1905596990 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/23.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/230.prim_prince_test.2835047967 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 1522380305 ps |
| CPU time | 26.05 seconds |
| Started | Aug 21 02:37:44 AM UTC 24 |
| Finished | Aug 21 02:38:18 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2835047967 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 230.prim_prince_test.2835047967 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/230.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/231.prim_prince_test.1034056499 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 1885790070 ps |
| CPU time | 32.1 seconds |
| Started | Aug 21 02:37:49 AM UTC 24 |
| Finished | Aug 21 02:38:31 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1034056499 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 231.prim_prince_test.1034056499 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/231.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/232.prim_prince_test.72011390 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 2735035961 ps |
| CPU time | 46.29 seconds |
| Started | Aug 21 02:37:52 AM UTC 24 |
| Finished | Aug 21 02:38:51 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=72011390 -assert nopostproc +UVM_TEST NAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pri m_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 232.prim_prince_test.72011390 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/232.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/233.prim_prince_test.2187125877 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 2993251700 ps |
| CPU time | 50.79 seconds |
| Started | Aug 21 02:37:53 AM UTC 24 |
| Finished | Aug 21 02:38:59 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2187125877 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 233.prim_prince_test.2187125877 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/233.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/234.prim_prince_test.2746589895 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 3432020638 ps |
| CPU time | 57.73 seconds |
| Started | Aug 21 02:37:53 AM UTC 24 |
| Finished | Aug 21 02:39:07 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2746589895 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 234.prim_prince_test.2746589895 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/234.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/235.prim_prince_test.2295052148 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 2151708091 ps |
| CPU time | 36.44 seconds |
| Started | Aug 21 02:38:00 AM UTC 24 |
| Finished | Aug 21 02:38:47 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2295052148 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 235.prim_prince_test.2295052148 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/235.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/236.prim_prince_test.3315451630 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 2906489965 ps |
| CPU time | 49.05 seconds |
| Started | Aug 21 02:38:02 AM UTC 24 |
| Finished | Aug 21 02:39:05 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3315451630 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 236.prim_prince_test.3315451630 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/236.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/237.prim_prince_test.2523768455 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 3702459422 ps |
| CPU time | 62.35 seconds |
| Started | Aug 21 02:38:06 AM UTC 24 |
| Finished | Aug 21 02:39:25 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2523768455 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 237.prim_prince_test.2523768455 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/237.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/238.prim_prince_test.894053447 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 799496034 ps |
| CPU time | 13.79 seconds |
| Started | Aug 21 02:38:07 AM UTC 24 |
| Finished | Aug 21 02:38:25 AM UTC 24 |
| Peak memory | 154604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=894053447 -assert nopostproc +UVM_TES TNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pr im_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 238.prim_prince_test.894053447 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/238.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/239.prim_prince_test.744745192 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 1767402278 ps |
| CPU time | 30.2 seconds |
| Started | Aug 21 02:38:11 AM UTC 24 |
| Finished | Aug 21 02:38:50 AM UTC 24 |
| Peak memory | 154604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=744745192 -assert nopostproc +UVM_TES TNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pr im_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 239.prim_prince_test.744745192 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/239.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/24.prim_prince_test.3774392910 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 2422055000 ps |
| CPU time | 42.17 seconds |
| Started | Aug 21 02:28:42 AM UTC 24 |
| Finished | Aug 21 02:29:36 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3774392910 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_prince_test.3774392910 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/24.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/240.prim_prince_test.825454648 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 2819417651 ps |
| CPU time | 47.61 seconds |
| Started | Aug 21 02:38:14 AM UTC 24 |
| Finished | Aug 21 02:39:15 AM UTC 24 |
| Peak memory | 154668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=825454648 -assert nopostproc +UVM_TES TNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pr im_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 240.prim_prince_test.825454648 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/240.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/241.prim_prince_test.2200907260 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 1345651695 ps |
| CPU time | 23.37 seconds |
| Started | Aug 21 02:38:16 AM UTC 24 |
| Finished | Aug 21 02:38:46 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2200907260 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 241.prim_prince_test.2200907260 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/241.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/242.prim_prince_test.1154326691 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 1201538354 ps |
| CPU time | 20.65 seconds |
| Started | Aug 21 02:38:17 AM UTC 24 |
| Finished | Aug 21 02:38:44 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1154326691 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 242.prim_prince_test.1154326691 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/242.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/243.prim_prince_test.3473830315 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 2979930835 ps |
| CPU time | 50.27 seconds |
| Started | Aug 21 02:38:18 AM UTC 24 |
| Finished | Aug 21 02:39:23 AM UTC 24 |
| Peak memory | 154660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3473830315 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 243.prim_prince_test.3473830315 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/243.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/244.prim_prince_test.228623090 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 1647601378 ps |
| CPU time | 27.74 seconds |
| Started | Aug 21 02:38:23 AM UTC 24 |
| Finished | Aug 21 02:38:59 AM UTC 24 |
| Peak memory | 154604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=228623090 -assert nopostproc +UVM_TES TNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pr im_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 244.prim_prince_test.228623090 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/244.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/245.prim_prince_test.3253606770 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 3079460382 ps |
| CPU time | 52.41 seconds |
| Started | Aug 21 02:38:25 AM UTC 24 |
| Finished | Aug 21 02:39:33 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3253606770 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 245.prim_prince_test.3253606770 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/245.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/246.prim_prince_test.2497298536 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 2596566304 ps |
| CPU time | 43.61 seconds |
| Started | Aug 21 02:38:32 AM UTC 24 |
| Finished | Aug 21 02:39:28 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2497298536 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 246.prim_prince_test.2497298536 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/246.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/247.prim_prince_test.3857118937 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 1731995189 ps |
| CPU time | 29.49 seconds |
| Started | Aug 21 02:38:32 AM UTC 24 |
| Finished | Aug 21 02:39:10 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3857118937 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 247.prim_prince_test.3857118937 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/247.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/248.prim_prince_test.1878520072 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 2315158691 ps |
| CPU time | 40.07 seconds |
| Started | Aug 21 02:38:32 AM UTC 24 |
| Finished | Aug 21 02:39:23 AM UTC 24 |
| Peak memory | 154660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1878520072 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 248.prim_prince_test.1878520072 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/248.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/249.prim_prince_test.1553596360 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 1926255824 ps |
| CPU time | 32.83 seconds |
| Started | Aug 21 02:38:32 AM UTC 24 |
| Finished | Aug 21 02:39:14 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1553596360 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 249.prim_prince_test.1553596360 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/249.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/25.prim_prince_test.3679639050 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 2049570322 ps |
| CPU time | 35.16 seconds |
| Started | Aug 21 02:28:46 AM UTC 24 |
| Finished | Aug 21 02:29:31 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3679639050 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_prince_test.3679639050 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/25.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/250.prim_prince_test.3541746384 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 761874047 ps |
| CPU time | 13.39 seconds |
| Started | Aug 21 02:38:34 AM UTC 24 |
| Finished | Aug 21 02:38:52 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3541746384 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 250.prim_prince_test.3541746384 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/250.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/251.prim_prince_test.2006999332 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 1798285096 ps |
| CPU time | 30.45 seconds |
| Started | Aug 21 02:38:37 AM UTC 24 |
| Finished | Aug 21 02:39:16 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2006999332 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 251.prim_prince_test.2006999332 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/251.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/252.prim_prince_test.1429632952 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 3442554424 ps |
| CPU time | 58.48 seconds |
| Started | Aug 21 02:38:45 AM UTC 24 |
| Finished | Aug 21 02:40:00 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1429632952 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 252.prim_prince_test.1429632952 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/252.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/253.prim_prince_test.2641378286 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 2887434998 ps |
| CPU time | 49.58 seconds |
| Started | Aug 21 02:38:47 AM UTC 24 |
| Finished | Aug 21 02:39:51 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2641378286 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 253.prim_prince_test.2641378286 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/253.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/254.prim_prince_test.821411464 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 896167490 ps |
| CPU time | 15.47 seconds |
| Started | Aug 21 02:38:48 AM UTC 24 |
| Finished | Aug 21 02:39:09 AM UTC 24 |
| Peak memory | 154608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=821411464 -assert nopostproc +UVM_TES TNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pr im_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 254.prim_prince_test.821411464 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/254.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/255.prim_prince_test.2750835653 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 3581735040 ps |
| CPU time | 60.29 seconds |
| Started | Aug 21 02:38:48 AM UTC 24 |
| Finished | Aug 21 02:40:06 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2750835653 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 255.prim_prince_test.2750835653 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/255.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/256.prim_prince_test.2621496867 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 1891023933 ps |
| CPU time | 31.82 seconds |
| Started | Aug 21 02:38:50 AM UTC 24 |
| Finished | Aug 21 02:39:32 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2621496867 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 256.prim_prince_test.2621496867 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/256.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/257.prim_prince_test.1793199878 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 3374786825 ps |
| CPU time | 57.55 seconds |
| Started | Aug 21 02:38:53 AM UTC 24 |
| Finished | Aug 21 02:40:06 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1793199878 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 257.prim_prince_test.1793199878 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/257.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/258.prim_prince_test.1325418136 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 1171570344 ps |
| CPU time | 20.5 seconds |
| Started | Aug 21 02:38:53 AM UTC 24 |
| Finished | Aug 21 02:39:19 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1325418136 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 258.prim_prince_test.1325418136 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/258.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/259.prim_prince_test.833348071 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 2655950536 ps |
| CPU time | 45.29 seconds |
| Started | Aug 21 02:39:00 AM UTC 24 |
| Finished | Aug 21 02:39:58 AM UTC 24 |
| Peak memory | 154668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=833348071 -assert nopostproc +UVM_TES TNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pr im_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 259.prim_prince_test.833348071 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/259.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/26.prim_prince_test.825320701 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 1803633469 ps |
| CPU time | 31.31 seconds |
| Started | Aug 21 02:28:47 AM UTC 24 |
| Finished | Aug 21 02:29:27 AM UTC 24 |
| Peak memory | 154596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=825320701 -assert nopostproc +UVM_TES TNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pr im_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_prince_test.825320701 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/26.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/260.prim_prince_test.2477325777 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 2760552876 ps |
| CPU time | 46.34 seconds |
| Started | Aug 21 02:39:00 AM UTC 24 |
| Finished | Aug 21 02:40:00 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2477325777 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 260.prim_prince_test.2477325777 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/260.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/261.prim_prince_test.2749644489 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 813667047 ps |
| CPU time | 14.43 seconds |
| Started | Aug 21 02:39:06 AM UTC 24 |
| Finished | Aug 21 02:39:25 AM UTC 24 |
| Peak memory | 154604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2749644489 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 261.prim_prince_test.2749644489 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/261.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/262.prim_prince_test.1601259977 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 3663434170 ps |
| CPU time | 61.34 seconds |
| Started | Aug 21 02:39:08 AM UTC 24 |
| Finished | Aug 21 02:40:27 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1601259977 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 262.prim_prince_test.1601259977 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/262.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/263.prim_prince_test.1633800673 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 864941336 ps |
| CPU time | 14.94 seconds |
| Started | Aug 21 02:39:09 AM UTC 24 |
| Finished | Aug 21 02:39:29 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1633800673 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 263.prim_prince_test.1633800673 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/263.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/264.prim_prince_test.533309245 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 2450548334 ps |
| CPU time | 41.23 seconds |
| Started | Aug 21 02:39:10 AM UTC 24 |
| Finished | Aug 21 02:40:03 AM UTC 24 |
| Peak memory | 154668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=533309245 -assert nopostproc +UVM_TES TNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pr im_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 264.prim_prince_test.533309245 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/264.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/265.prim_prince_test.2030383927 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 898110820 ps |
| CPU time | 15.27 seconds |
| Started | Aug 21 02:39:14 AM UTC 24 |
| Finished | Aug 21 02:39:35 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2030383927 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 265.prim_prince_test.2030383927 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/265.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/266.prim_prince_test.2290422708 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 793321345 ps |
| CPU time | 13.89 seconds |
| Started | Aug 21 02:39:16 AM UTC 24 |
| Finished | Aug 21 02:39:34 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2290422708 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 266.prim_prince_test.2290422708 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/266.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/267.prim_prince_test.4142344737 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 1139171080 ps |
| CPU time | 19.38 seconds |
| Started | Aug 21 02:39:18 AM UTC 24 |
| Finished | Aug 21 02:39:43 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4142344737 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 267.prim_prince_test.4142344737 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/267.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/268.prim_prince_test.3083551333 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 2464420885 ps |
| CPU time | 41.53 seconds |
| Started | Aug 21 02:39:20 AM UTC 24 |
| Finished | Aug 21 02:40:14 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3083551333 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 268.prim_prince_test.3083551333 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/268.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/269.prim_prince_test.1531734460 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 792190096 ps |
| CPU time | 13.7 seconds |
| Started | Aug 21 02:39:24 AM UTC 24 |
| Finished | Aug 21 02:39:42 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1531734460 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 269.prim_prince_test.1531734460 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/269.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/27.prim_prince_test.3262131183 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 944862769 ps |
| CPU time | 16.38 seconds |
| Started | Aug 21 02:28:52 AM UTC 24 |
| Finished | Aug 21 02:29:14 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3262131183 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_prince_test.3262131183 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/27.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/270.prim_prince_test.293481030 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 2014996257 ps |
| CPU time | 34.49 seconds |
| Started | Aug 21 02:39:24 AM UTC 24 |
| Finished | Aug 21 02:40:08 AM UTC 24 |
| Peak memory | 154604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=293481030 -assert nopostproc +UVM_TES TNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pr im_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 270.prim_prince_test.293481030 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/270.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/271.prim_prince_test.2651825902 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 3414708782 ps |
| CPU time | 57.25 seconds |
| Started | Aug 21 02:39:26 AM UTC 24 |
| Finished | Aug 21 02:40:40 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2651825902 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 271.prim_prince_test.2651825902 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/271.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/272.prim_prince_test.2471775511 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 2300439945 ps |
| CPU time | 38.89 seconds |
| Started | Aug 21 02:39:26 AM UTC 24 |
| Finished | Aug 21 02:40:16 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2471775511 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 272.prim_prince_test.2471775511 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/272.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/273.prim_prince_test.2506249142 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 919271698 ps |
| CPU time | 15.96 seconds |
| Started | Aug 21 02:39:28 AM UTC 24 |
| Finished | Aug 21 02:39:50 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2506249142 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 273.prim_prince_test.2506249142 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/273.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/274.prim_prince_test.2128012953 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 2427337003 ps |
| CPU time | 41.08 seconds |
| Started | Aug 21 02:39:29 AM UTC 24 |
| Finished | Aug 21 02:40:22 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2128012953 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 274.prim_prince_test.2128012953 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/274.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/275.prim_prince_test.1126197498 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 2256175360 ps |
| CPU time | 38.03 seconds |
| Started | Aug 21 02:39:32 AM UTC 24 |
| Finished | Aug 21 02:40:22 AM UTC 24 |
| Peak memory | 154668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1126197498 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 275.prim_prince_test.1126197498 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/275.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/276.prim_prince_test.2222676941 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 3654844128 ps |
| CPU time | 60.71 seconds |
| Started | Aug 21 02:39:34 AM UTC 24 |
| Finished | Aug 21 02:40:52 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2222676941 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 276.prim_prince_test.2222676941 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/276.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/277.prim_prince_test.1210767177 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 1462322583 ps |
| CPU time | 25.19 seconds |
| Started | Aug 21 02:39:36 AM UTC 24 |
| Finished | Aug 21 02:40:09 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1210767177 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 277.prim_prince_test.1210767177 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/277.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/278.prim_prince_test.1610143102 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 1591905336 ps |
| CPU time | 26.98 seconds |
| Started | Aug 21 02:39:36 AM UTC 24 |
| Finished | Aug 21 02:40:11 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1610143102 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 278.prim_prince_test.1610143102 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/278.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/279.prim_prince_test.895563456 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 1789643071 ps |
| CPU time | 30.61 seconds |
| Started | Aug 21 02:39:43 AM UTC 24 |
| Finished | Aug 21 02:40:22 AM UTC 24 |
| Peak memory | 154604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=895563456 -assert nopostproc +UVM_TES TNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pr im_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 279.prim_prince_test.895563456 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/279.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/28.prim_prince_test.124113053 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 1339318234 ps |
| CPU time | 23.15 seconds |
| Started | Aug 21 02:28:56 AM UTC 24 |
| Finished | Aug 21 02:29:26 AM UTC 24 |
| Peak memory | 154596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=124113053 -assert nopostproc +UVM_TES TNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pr im_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_prince_test.124113053 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/28.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/280.prim_prince_test.501548026 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 2252301749 ps |
| CPU time | 38 seconds |
| Started | Aug 21 02:39:44 AM UTC 24 |
| Finished | Aug 21 02:40:33 AM UTC 24 |
| Peak memory | 154668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=501548026 -assert nopostproc +UVM_TES TNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pr im_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 280.prim_prince_test.501548026 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/280.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/281.prim_prince_test.2444992670 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 3140925578 ps |
| CPU time | 53.7 seconds |
| Started | Aug 21 02:39:50 AM UTC 24 |
| Finished | Aug 21 02:40:59 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2444992670 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 281.prim_prince_test.2444992670 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/281.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/282.prim_prince_test.681677780 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 1956022504 ps |
| CPU time | 32.88 seconds |
| Started | Aug 21 02:39:51 AM UTC 24 |
| Finished | Aug 21 02:40:34 AM UTC 24 |
| Peak memory | 154604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=681677780 -assert nopostproc +UVM_TES TNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pr im_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 282.prim_prince_test.681677780 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/282.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/283.prim_prince_test.289989027 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 3150623744 ps |
| CPU time | 53.85 seconds |
| Started | Aug 21 02:39:59 AM UTC 24 |
| Finished | Aug 21 02:41:09 AM UTC 24 |
| Peak memory | 154668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=289989027 -assert nopostproc +UVM_TES TNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pr im_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 283.prim_prince_test.289989027 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/283.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/284.prim_prince_test.3170925434 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 3631216020 ps |
| CPU time | 61.79 seconds |
| Started | Aug 21 02:40:01 AM UTC 24 |
| Finished | Aug 21 02:41:20 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3170925434 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 284.prim_prince_test.3170925434 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/284.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/285.prim_prince_test.94662 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 1002564506 ps |
| CPU time | 17.29 seconds |
| Started | Aug 21 02:40:01 AM UTC 24 |
| Finished | Aug 21 02:40:23 AM UTC 24 |
| Peak memory | 154604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=94662 -assert nopostproc +UVM_TESTNAM E= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_p rince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 285.prim_prince_test.94662 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/285.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/286.prim_prince_test.2773472066 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 2976748361 ps |
| CPU time | 49.73 seconds |
| Started | Aug 21 02:40:05 AM UTC 24 |
| Finished | Aug 21 02:41:09 AM UTC 24 |
| Peak memory | 154668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2773472066 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 286.prim_prince_test.2773472066 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/286.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/287.prim_prince_test.3780460735 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 3413587588 ps |
| CPU time | 57 seconds |
| Started | Aug 21 02:40:06 AM UTC 24 |
| Finished | Aug 21 02:41:19 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3780460735 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 287.prim_prince_test.3780460735 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/287.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/288.prim_prince_test.4010560978 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 2455402707 ps |
| CPU time | 40.88 seconds |
| Started | Aug 21 02:40:07 AM UTC 24 |
| Finished | Aug 21 02:41:00 AM UTC 24 |
| Peak memory | 154668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4010560978 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 288.prim_prince_test.4010560978 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/288.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/289.prim_prince_test.2823886794 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 3030426476 ps |
| CPU time | 51.68 seconds |
| Started | Aug 21 02:40:09 AM UTC 24 |
| Finished | Aug 21 02:41:15 AM UTC 24 |
| Peak memory | 154636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2823886794 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 289.prim_prince_test.2823886794 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/289.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/29.prim_prince_test.4128595461 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 2413842690 ps |
| CPU time | 41.6 seconds |
| Started | Aug 21 02:28:59 AM UTC 24 |
| Finished | Aug 21 02:29:52 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4128595461 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_prince_test.4128595461 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/29.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/290.prim_prince_test.535684050 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 1970795734 ps |
| CPU time | 34.04 seconds |
| Started | Aug 21 02:40:09 AM UTC 24 |
| Finished | Aug 21 02:40:53 AM UTC 24 |
| Peak memory | 154604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=535684050 -assert nopostproc +UVM_TES TNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pr im_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 290.prim_prince_test.535684050 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/290.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/291.prim_prince_test.903849078 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 3390763006 ps |
| CPU time | 57.53 seconds |
| Started | Aug 21 02:40:11 AM UTC 24 |
| Finished | Aug 21 02:41:25 AM UTC 24 |
| Peak memory | 154668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=903849078 -assert nopostproc +UVM_TES TNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pr im_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 291.prim_prince_test.903849078 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/291.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/292.prim_prince_test.366996238 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 1283072842 ps |
| CPU time | 21.62 seconds |
| Started | Aug 21 02:40:14 AM UTC 24 |
| Finished | Aug 21 02:40:43 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=366996238 -assert nopostproc +UVM_TES TNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pr im_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 292.prim_prince_test.366996238 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/292.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/293.prim_prince_test.761371328 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 827297969 ps |
| CPU time | 13.99 seconds |
| Started | Aug 21 02:40:17 AM UTC 24 |
| Finished | Aug 21 02:40:36 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=761371328 -assert nopostproc +UVM_TES TNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pr im_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 293.prim_prince_test.761371328 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/293.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/294.prim_prince_test.993570070 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 1090048488 ps |
| CPU time | 18.98 seconds |
| Started | Aug 21 02:40:23 AM UTC 24 |
| Finished | Aug 21 02:40:48 AM UTC 24 |
| Peak memory | 154604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=993570070 -assert nopostproc +UVM_TES TNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pr im_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 294.prim_prince_test.993570070 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/294.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/295.prim_prince_test.1526443896 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 1542783597 ps |
| CPU time | 25.81 seconds |
| Started | Aug 21 02:40:24 AM UTC 24 |
| Finished | Aug 21 02:40:58 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1526443896 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 295.prim_prince_test.1526443896 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/295.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/296.prim_prince_test.4023171009 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 2563518078 ps |
| CPU time | 42.58 seconds |
| Started | Aug 21 02:40:24 AM UTC 24 |
| Finished | Aug 21 02:41:19 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4023171009 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 296.prim_prince_test.4023171009 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/296.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/297.prim_prince_test.188192794 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 1985668882 ps |
| CPU time | 33.35 seconds |
| Started | Aug 21 02:40:24 AM UTC 24 |
| Finished | Aug 21 02:41:07 AM UTC 24 |
| Peak memory | 154604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=188192794 -assert nopostproc +UVM_TES TNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pr im_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 297.prim_prince_test.188192794 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/297.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/298.prim_prince_test.1150484213 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 3663540539 ps |
| CPU time | 61.29 seconds |
| Started | Aug 21 02:40:28 AM UTC 24 |
| Finished | Aug 21 02:41:47 AM UTC 24 |
| Peak memory | 154660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1150484213 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 298.prim_prince_test.1150484213 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/298.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/299.prim_prince_test.2961604965 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 3175449364 ps |
| CPU time | 53.1 seconds |
| Started | Aug 21 02:40:34 AM UTC 24 |
| Finished | Aug 21 02:41:42 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2961604965 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 299.prim_prince_test.2961604965 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/299.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/3.prim_prince_test.1258447271 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 2321672899 ps |
| CPU time | 39.97 seconds |
| Started | Aug 21 02:27:54 AM UTC 24 |
| Finished | Aug 21 02:28:45 AM UTC 24 |
| Peak memory | 154660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1258447271 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_prince_test.1258447271 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/3.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/30.prim_prince_test.1877820126 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 1160489750 ps |
| CPU time | 20.66 seconds |
| Started | Aug 21 02:29:01 AM UTC 24 |
| Finished | Aug 21 02:29:28 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1877820126 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_prince_test.1877820126 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/30.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/300.prim_prince_test.3701687243 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 1199355634 ps |
| CPU time | 20.4 seconds |
| Started | Aug 21 02:40:35 AM UTC 24 |
| Finished | Aug 21 02:41:02 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3701687243 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 300.prim_prince_test.3701687243 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/300.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/301.prim_prince_test.76752425 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 3191719529 ps |
| CPU time | 53.17 seconds |
| Started | Aug 21 02:40:37 AM UTC 24 |
| Finished | Aug 21 02:41:46 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=76752425 -assert nopostproc +UVM_TEST NAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pri m_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 301.prim_prince_test.76752425 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/301.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/302.prim_prince_test.2212858276 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 760049366 ps |
| CPU time | 13.07 seconds |
| Started | Aug 21 02:40:41 AM UTC 24 |
| Finished | Aug 21 02:40:58 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2212858276 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 302.prim_prince_test.2212858276 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/302.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/303.prim_prince_test.3746917802 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 2687942632 ps |
| CPU time | 45.43 seconds |
| Started | Aug 21 02:40:44 AM UTC 24 |
| Finished | Aug 21 02:41:42 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3746917802 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 303.prim_prince_test.3746917802 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/303.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/304.prim_prince_test.1005539825 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 2203306723 ps |
| CPU time | 37.62 seconds |
| Started | Aug 21 02:40:49 AM UTC 24 |
| Finished | Aug 21 02:41:37 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1005539825 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 304.prim_prince_test.1005539825 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/304.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/305.prim_prince_test.3271737796 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 1743813577 ps |
| CPU time | 29.73 seconds |
| Started | Aug 21 02:40:53 AM UTC 24 |
| Finished | Aug 21 02:41:32 AM UTC 24 |
| Peak memory | 154604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3271737796 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 305.prim_prince_test.3271737796 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/305.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/306.prim_prince_test.3863484510 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 2745757633 ps |
| CPU time | 46.77 seconds |
| Started | Aug 21 02:40:54 AM UTC 24 |
| Finished | Aug 21 02:41:54 AM UTC 24 |
| Peak memory | 154668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3863484510 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 306.prim_prince_test.3863484510 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/306.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/307.prim_prince_test.2838687131 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 3238435285 ps |
| CPU time | 54.61 seconds |
| Started | Aug 21 02:40:59 AM UTC 24 |
| Finished | Aug 21 02:42:10 AM UTC 24 |
| Peak memory | 154660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2838687131 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 307.prim_prince_test.2838687131 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/307.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/308.prim_prince_test.1363676216 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 3219793764 ps |
| CPU time | 55.06 seconds |
| Started | Aug 21 02:40:59 AM UTC 24 |
| Finished | Aug 21 02:42:10 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1363676216 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 308.prim_prince_test.1363676216 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/308.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/309.prim_prince_test.2012546767 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 2516758369 ps |
| CPU time | 42.62 seconds |
| Started | Aug 21 02:41:00 AM UTC 24 |
| Finished | Aug 21 02:41:56 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2012546767 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 309.prim_prince_test.2012546767 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/309.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/31.prim_prince_test.1865329429 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 1609276149 ps |
| CPU time | 27.4 seconds |
| Started | Aug 21 02:29:06 AM UTC 24 |
| Finished | Aug 21 02:29:42 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1865329429 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_prince_test.1865329429 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/31.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/310.prim_prince_test.553798118 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 3740860931 ps |
| CPU time | 62.97 seconds |
| Started | Aug 21 02:41:00 AM UTC 24 |
| Finished | Aug 21 02:42:22 AM UTC 24 |
| Peak memory | 154668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=553798118 -assert nopostproc +UVM_TES TNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pr im_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 310.prim_prince_test.553798118 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/310.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/311.prim_prince_test.3879297711 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 1159884596 ps |
| CPU time | 19.75 seconds |
| Started | Aug 21 02:41:03 AM UTC 24 |
| Finished | Aug 21 02:41:29 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3879297711 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 311.prim_prince_test.3879297711 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/311.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/312.prim_prince_test.938251645 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 3641798851 ps |
| CPU time | 61.26 seconds |
| Started | Aug 21 02:41:08 AM UTC 24 |
| Finished | Aug 21 02:42:27 AM UTC 24 |
| Peak memory | 154668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=938251645 -assert nopostproc +UVM_TES TNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pr im_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 312.prim_prince_test.938251645 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/312.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/313.prim_prince_test.2391699037 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 3258759140 ps |
| CPU time | 54.89 seconds |
| Started | Aug 21 02:41:10 AM UTC 24 |
| Finished | Aug 21 02:42:21 AM UTC 24 |
| Peak memory | 154288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2391699037 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 313.prim_prince_test.2391699037 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/313.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/314.prim_prince_test.3252270394 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 3488080422 ps |
| CPU time | 58.87 seconds |
| Started | Aug 21 02:41:10 AM UTC 24 |
| Finished | Aug 21 02:42:26 AM UTC 24 |
| Peak memory | 154368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3252270394 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 314.prim_prince_test.3252270394 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/314.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/315.prim_prince_test.1235847574 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 1230985655 ps |
| CPU time | 21.23 seconds |
| Started | Aug 21 02:41:16 AM UTC 24 |
| Finished | Aug 21 02:41:44 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1235847574 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 315.prim_prince_test.1235847574 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/315.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/316.prim_prince_test.1017384647 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 1892025717 ps |
| CPU time | 32.3 seconds |
| Started | Aug 21 02:41:20 AM UTC 24 |
| Finished | Aug 21 02:42:02 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1017384647 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 316.prim_prince_test.1017384647 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/316.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/317.prim_prince_test.2952106334 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 2098761992 ps |
| CPU time | 35.93 seconds |
| Started | Aug 21 02:41:20 AM UTC 24 |
| Finished | Aug 21 02:42:07 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2952106334 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 317.prim_prince_test.2952106334 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/317.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/318.prim_prince_test.205523116 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 2640400096 ps |
| CPU time | 44.71 seconds |
| Started | Aug 21 02:41:20 AM UTC 24 |
| Finished | Aug 21 02:42:18 AM UTC 24 |
| Peak memory | 154668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=205523116 -assert nopostproc +UVM_TES TNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pr im_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 318.prim_prince_test.205523116 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/318.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/319.prim_prince_test.3033369966 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 2094056051 ps |
| CPU time | 35.9 seconds |
| Started | Aug 21 02:41:25 AM UTC 24 |
| Finished | Aug 21 02:42:12 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3033369966 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 319.prim_prince_test.3033369966 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/319.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/32.prim_prince_test.2700348759 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 759178085 ps |
| CPU time | 13.37 seconds |
| Started | Aug 21 02:29:07 AM UTC 24 |
| Finished | Aug 21 02:29:25 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2700348759 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_prince_test.2700348759 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/32.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/320.prim_prince_test.2430533886 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 2752464374 ps |
| CPU time | 46 seconds |
| Started | Aug 21 02:41:30 AM UTC 24 |
| Finished | Aug 21 02:42:29 AM UTC 24 |
| Peak memory | 154668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2430533886 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 320.prim_prince_test.2430533886 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/320.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/321.prim_prince_test.3176058167 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 1682139198 ps |
| CPU time | 28.49 seconds |
| Started | Aug 21 02:41:33 AM UTC 24 |
| Finished | Aug 21 02:42:10 AM UTC 24 |
| Peak memory | 154604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3176058167 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 321.prim_prince_test.3176058167 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/321.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/322.prim_prince_test.3871508933 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 767581560 ps |
| CPU time | 13.24 seconds |
| Started | Aug 21 02:41:38 AM UTC 24 |
| Finished | Aug 21 02:41:55 AM UTC 24 |
| Peak memory | 154604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3871508933 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 322.prim_prince_test.3871508933 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/322.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/323.prim_prince_test.3497355417 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 2077157246 ps |
| CPU time | 35.44 seconds |
| Started | Aug 21 02:41:43 AM UTC 24 |
| Finished | Aug 21 02:42:29 AM UTC 24 |
| Peak memory | 154604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3497355417 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 323.prim_prince_test.3497355417 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/323.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/324.prim_prince_test.1904555595 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 1213472432 ps |
| CPU time | 20.87 seconds |
| Started | Aug 21 02:41:43 AM UTC 24 |
| Finished | Aug 21 02:42:11 AM UTC 24 |
| Peak memory | 154604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1904555595 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 324.prim_prince_test.1904555595 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/324.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/325.prim_prince_test.3175349769 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 2301285288 ps |
| CPU time | 39.6 seconds |
| Started | Aug 21 02:41:45 AM UTC 24 |
| Finished | Aug 21 02:42:36 AM UTC 24 |
| Peak memory | 154668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3175349769 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 325.prim_prince_test.3175349769 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/325.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/326.prim_prince_test.3027732174 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 3239880668 ps |
| CPU time | 54.45 seconds |
| Started | Aug 21 02:41:46 AM UTC 24 |
| Finished | Aug 21 02:42:56 AM UTC 24 |
| Peak memory | 154668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3027732174 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 326.prim_prince_test.3027732174 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/326.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/327.prim_prince_test.1141776433 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 1335107906 ps |
| CPU time | 22.67 seconds |
| Started | Aug 21 02:41:47 AM UTC 24 |
| Finished | Aug 21 02:42:17 AM UTC 24 |
| Peak memory | 154604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1141776433 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 327.prim_prince_test.1141776433 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/327.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/328.prim_prince_test.1905971786 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 3218490024 ps |
| CPU time | 54.41 seconds |
| Started | Aug 21 02:41:55 AM UTC 24 |
| Finished | Aug 21 02:43:05 AM UTC 24 |
| Peak memory | 154668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1905971786 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 328.prim_prince_test.1905971786 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/328.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/329.prim_prince_test.1798660374 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 3688334336 ps |
| CPU time | 61.94 seconds |
| Started | Aug 21 02:41:56 AM UTC 24 |
| Finished | Aug 21 02:43:15 AM UTC 24 |
| Peak memory | 154668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1798660374 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 329.prim_prince_test.1798660374 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/329.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/33.prim_prince_test.2962949395 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 1556566239 ps |
| CPU time | 26.6 seconds |
| Started | Aug 21 02:29:09 AM UTC 24 |
| Finished | Aug 21 02:29:44 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2962949395 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_prince_test.2962949395 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/33.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/330.prim_prince_test.1798009954 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 2851308731 ps |
| CPU time | 47.92 seconds |
| Started | Aug 21 02:41:57 AM UTC 24 |
| Finished | Aug 21 02:42:59 AM UTC 24 |
| Peak memory | 154668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1798009954 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 330.prim_prince_test.1798009954 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/330.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/331.prim_prince_test.3253413211 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 840205494 ps |
| CPU time | 14.56 seconds |
| Started | Aug 21 02:42:03 AM UTC 24 |
| Finished | Aug 21 02:42:23 AM UTC 24 |
| Peak memory | 154604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3253413211 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 331.prim_prince_test.3253413211 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/331.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/332.prim_prince_test.2011228016 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 2835613283 ps |
| CPU time | 47.64 seconds |
| Started | Aug 21 02:42:08 AM UTC 24 |
| Finished | Aug 21 02:43:09 AM UTC 24 |
| Peak memory | 154668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2011228016 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 332.prim_prince_test.2011228016 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/332.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/333.prim_prince_test.3652629694 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 1371273665 ps |
| CPU time | 23 seconds |
| Started | Aug 21 02:42:10 AM UTC 24 |
| Finished | Aug 21 02:42:40 AM UTC 24 |
| Peak memory | 154604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3652629694 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 333.prim_prince_test.3652629694 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/333.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/334.prim_prince_test.1152452896 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 1392628064 ps |
| CPU time | 24.05 seconds |
| Started | Aug 21 02:42:10 AM UTC 24 |
| Finished | Aug 21 02:42:42 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1152452896 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 334.prim_prince_test.1152452896 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/334.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/335.prim_prince_test.3164293825 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 1005035424 ps |
| CPU time | 17.37 seconds |
| Started | Aug 21 02:42:12 AM UTC 24 |
| Finished | Aug 21 02:42:34 AM UTC 24 |
| Peak memory | 154604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3164293825 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 335.prim_prince_test.3164293825 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/335.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/336.prim_prince_test.1525975227 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 2946546625 ps |
| CPU time | 49.58 seconds |
| Started | Aug 21 02:42:12 AM UTC 24 |
| Finished | Aug 21 02:43:15 AM UTC 24 |
| Peak memory | 154668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1525975227 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 336.prim_prince_test.1525975227 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/336.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/337.prim_prince_test.131492000 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 2881235178 ps |
| CPU time | 49.06 seconds |
| Started | Aug 21 02:42:13 AM UTC 24 |
| Finished | Aug 21 02:43:16 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=131492000 -assert nopostproc +UVM_TES TNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pr im_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 337.prim_prince_test.131492000 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/337.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/338.prim_prince_test.547504864 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 2065832685 ps |
| CPU time | 34.93 seconds |
| Started | Aug 21 02:42:18 AM UTC 24 |
| Finished | Aug 21 02:43:03 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=547504864 -assert nopostproc +UVM_TES TNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pr im_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 338.prim_prince_test.547504864 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/338.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/339.prim_prince_test.104451684 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 2893886566 ps |
| CPU time | 48.87 seconds |
| Started | Aug 21 02:42:19 AM UTC 24 |
| Finished | Aug 21 02:43:22 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=104451684 -assert nopostproc +UVM_TES TNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pr im_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 339.prim_prince_test.104451684 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/339.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/34.prim_prince_test.1426049941 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 3277305776 ps |
| CPU time | 56.24 seconds |
| Started | Aug 21 02:29:13 AM UTC 24 |
| Finished | Aug 21 02:30:25 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1426049941 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_prince_test.1426049941 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/34.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/340.prim_prince_test.3321627117 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 831471168 ps |
| CPU time | 14.02 seconds |
| Started | Aug 21 02:42:21 AM UTC 24 |
| Finished | Aug 21 02:42:40 AM UTC 24 |
| Peak memory | 154604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3321627117 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 340.prim_prince_test.3321627117 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/340.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/341.prim_prince_test.2121199891 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 2130768483 ps |
| CPU time | 36.29 seconds |
| Started | Aug 21 02:42:22 AM UTC 24 |
| Finished | Aug 21 02:43:09 AM UTC 24 |
| Peak memory | 154604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2121199891 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 341.prim_prince_test.2121199891 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/341.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/342.prim_prince_test.3207836956 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 2795244846 ps |
| CPU time | 47.35 seconds |
| Started | Aug 21 02:42:23 AM UTC 24 |
| Finished | Aug 21 02:43:24 AM UTC 24 |
| Peak memory | 154668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3207836956 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 342.prim_prince_test.3207836956 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/342.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/343.prim_prince_test.1840735189 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 1633640356 ps |
| CPU time | 27.88 seconds |
| Started | Aug 21 02:42:26 AM UTC 24 |
| Finished | Aug 21 02:43:03 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1840735189 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 343.prim_prince_test.1840735189 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/343.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/344.prim_prince_test.615836254 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 2331061346 ps |
| CPU time | 39.77 seconds |
| Started | Aug 21 02:42:28 AM UTC 24 |
| Finished | Aug 21 02:43:19 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=615836254 -assert nopostproc +UVM_TES TNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pr im_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 344.prim_prince_test.615836254 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/344.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/345.prim_prince_test.3100267916 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 1289609724 ps |
| CPU time | 21.94 seconds |
| Started | Aug 21 02:42:30 AM UTC 24 |
| Finished | Aug 21 02:42:59 AM UTC 24 |
| Peak memory | 154604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3100267916 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 345.prim_prince_test.3100267916 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/345.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/346.prim_prince_test.1470720597 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 986104174 ps |
| CPU time | 17.19 seconds |
| Started | Aug 21 02:42:30 AM UTC 24 |
| Finished | Aug 21 02:42:52 AM UTC 24 |
| Peak memory | 154604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1470720597 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 346.prim_prince_test.1470720597 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/346.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/347.prim_prince_test.1958719994 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 915243639 ps |
| CPU time | 15.92 seconds |
| Started | Aug 21 02:42:35 AM UTC 24 |
| Finished | Aug 21 02:42:56 AM UTC 24 |
| Peak memory | 154604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1958719994 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 347.prim_prince_test.1958719994 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/347.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/348.prim_prince_test.1170100003 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 3666092040 ps |
| CPU time | 62.61 seconds |
| Started | Aug 21 02:42:37 AM UTC 24 |
| Finished | Aug 21 02:43:57 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1170100003 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 348.prim_prince_test.1170100003 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/348.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/349.prim_prince_test.1195680039 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 1909918466 ps |
| CPU time | 32.72 seconds |
| Started | Aug 21 02:42:40 AM UTC 24 |
| Finished | Aug 21 02:43:22 AM UTC 24 |
| Peak memory | 154604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1195680039 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 349.prim_prince_test.1195680039 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/349.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/35.prim_prince_test.2522291973 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 2913759854 ps |
| CPU time | 48.94 seconds |
| Started | Aug 21 02:29:14 AM UTC 24 |
| Finished | Aug 21 02:30:17 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2522291973 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_prince_test.2522291973 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/35.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/350.prim_prince_test.3104894525 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 1516050369 ps |
| CPU time | 26.01 seconds |
| Started | Aug 21 02:42:41 AM UTC 24 |
| Finished | Aug 21 02:43:15 AM UTC 24 |
| Peak memory | 154604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3104894525 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 350.prim_prince_test.3104894525 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/350.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/351.prim_prince_test.3982630365 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 3098750526 ps |
| CPU time | 52.46 seconds |
| Started | Aug 21 02:42:42 AM UTC 24 |
| Finished | Aug 21 02:43:50 AM UTC 24 |
| Peak memory | 154668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3982630365 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 351.prim_prince_test.3982630365 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/351.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/352.prim_prince_test.2762528949 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 2047241053 ps |
| CPU time | 34.8 seconds |
| Started | Aug 21 02:42:54 AM UTC 24 |
| Finished | Aug 21 02:43:39 AM UTC 24 |
| Peak memory | 154604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2762528949 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 352.prim_prince_test.2762528949 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/352.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/353.prim_prince_test.1201727707 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 1344307086 ps |
| CPU time | 23 seconds |
| Started | Aug 21 02:42:57 AM UTC 24 |
| Finished | Aug 21 02:43:27 AM UTC 24 |
| Peak memory | 154604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1201727707 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 353.prim_prince_test.1201727707 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/353.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/354.prim_prince_test.1016975199 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 2837216829 ps |
| CPU time | 48.23 seconds |
| Started | Aug 21 02:42:58 AM UTC 24 |
| Finished | Aug 21 02:44:00 AM UTC 24 |
| Peak memory | 154668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1016975199 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 354.prim_prince_test.1016975199 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/354.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/355.prim_prince_test.2868000725 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 1124789600 ps |
| CPU time | 19.8 seconds |
| Started | Aug 21 02:42:59 AM UTC 24 |
| Finished | Aug 21 02:43:25 AM UTC 24 |
| Peak memory | 154604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2868000725 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 355.prim_prince_test.2868000725 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/355.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/356.prim_prince_test.3306001438 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 2352926860 ps |
| CPU time | 40.26 seconds |
| Started | Aug 21 02:42:59 AM UTC 24 |
| Finished | Aug 21 02:43:51 AM UTC 24 |
| Peak memory | 154668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3306001438 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 356.prim_prince_test.3306001438 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/356.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/357.prim_prince_test.1409410859 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 1759080277 ps |
| CPU time | 30.37 seconds |
| Started | Aug 21 02:43:03 AM UTC 24 |
| Finished | Aug 21 02:43:43 AM UTC 24 |
| Peak memory | 154604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1409410859 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 357.prim_prince_test.1409410859 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/357.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/358.prim_prince_test.75892391 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 3232713415 ps |
| CPU time | 54.81 seconds |
| Started | Aug 21 02:43:04 AM UTC 24 |
| Finished | Aug 21 02:44:15 AM UTC 24 |
| Peak memory | 154668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=75892391 -assert nopostproc +UVM_TEST NAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pri m_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 358.prim_prince_test.75892391 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/358.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/359.prim_prince_test.2778998559 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 3012974197 ps |
| CPU time | 50.83 seconds |
| Started | Aug 21 02:43:05 AM UTC 24 |
| Finished | Aug 21 02:44:11 AM UTC 24 |
| Peak memory | 154668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2778998559 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 359.prim_prince_test.2778998559 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/359.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/36.prim_prince_test.1949947134 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 1811531896 ps |
| CPU time | 31.16 seconds |
| Started | Aug 21 02:29:15 AM UTC 24 |
| Finished | Aug 21 02:29:56 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1949947134 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_prince_test.1949947134 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/36.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/360.prim_prince_test.3124661186 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 897950895 ps |
| CPU time | 15.41 seconds |
| Started | Aug 21 02:43:10 AM UTC 24 |
| Finished | Aug 21 02:43:30 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3124661186 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 360.prim_prince_test.3124661186 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/360.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/361.prim_prince_test.2070061446 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 3710840693 ps |
| CPU time | 63.09 seconds |
| Started | Aug 21 02:43:11 AM UTC 24 |
| Finished | Aug 21 02:44:32 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2070061446 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 361.prim_prince_test.2070061446 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/361.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/362.prim_prince_test.654721393 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 978096943 ps |
| CPU time | 16.99 seconds |
| Started | Aug 21 02:43:16 AM UTC 24 |
| Finished | Aug 21 02:43:38 AM UTC 24 |
| Peak memory | 154604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=654721393 -assert nopostproc +UVM_TES TNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pr im_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 362.prim_prince_test.654721393 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/362.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/363.prim_prince_test.3398352666 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 2889893069 ps |
| CPU time | 49.43 seconds |
| Started | Aug 21 02:43:16 AM UTC 24 |
| Finished | Aug 21 02:44:20 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3398352666 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 363.prim_prince_test.3398352666 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/363.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/364.prim_prince_test.848524375 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 3679481694 ps |
| CPU time | 62.61 seconds |
| Started | Aug 21 02:43:16 AM UTC 24 |
| Finished | Aug 21 02:44:36 AM UTC 24 |
| Peak memory | 154668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=848524375 -assert nopostproc +UVM_TES TNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pr im_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 364.prim_prince_test.848524375 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/364.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/365.prim_prince_test.380423317 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 3735266605 ps |
| CPU time | 63.65 seconds |
| Started | Aug 21 02:43:17 AM UTC 24 |
| Finished | Aug 21 02:44:39 AM UTC 24 |
| Peak memory | 154672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=380423317 -assert nopostproc +UVM_TES TNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pr im_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 365.prim_prince_test.380423317 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/365.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/366.prim_prince_test.3395480640 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 2822016170 ps |
| CPU time | 47.83 seconds |
| Started | Aug 21 02:43:19 AM UTC 24 |
| Finished | Aug 21 02:44:21 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3395480640 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 366.prim_prince_test.3395480640 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/366.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/367.prim_prince_test.2665576058 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 1625006040 ps |
| CPU time | 28.1 seconds |
| Started | Aug 21 02:43:23 AM UTC 24 |
| Finished | Aug 21 02:43:59 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2665576058 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 367.prim_prince_test.2665576058 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/367.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/368.prim_prince_test.2412613558 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 1789972970 ps |
| CPU time | 30.87 seconds |
| Started | Aug 21 02:43:24 AM UTC 24 |
| Finished | Aug 21 02:44:04 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2412613558 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 368.prim_prince_test.2412613558 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/368.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/369.prim_prince_test.3397419194 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 1991759850 ps |
| CPU time | 34.3 seconds |
| Started | Aug 21 02:43:25 AM UTC 24 |
| Finished | Aug 21 02:44:09 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3397419194 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 369.prim_prince_test.3397419194 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/369.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/37.prim_prince_test.3655666236 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 1964961334 ps |
| CPU time | 33.46 seconds |
| Started | Aug 21 02:29:18 AM UTC 24 |
| Finished | Aug 21 02:30:01 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3655666236 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_prince_test.3655666236 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/37.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/370.prim_prince_test.3240416658 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 2400602943 ps |
| CPU time | 41.06 seconds |
| Started | Aug 21 02:43:26 AM UTC 24 |
| Finished | Aug 21 02:44:19 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3240416658 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 370.prim_prince_test.3240416658 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/370.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/371.prim_prince_test.3127039831 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 3457703277 ps |
| CPU time | 59.07 seconds |
| Started | Aug 21 02:43:30 AM UTC 24 |
| Finished | Aug 21 02:44:46 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3127039831 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 371.prim_prince_test.3127039831 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/371.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/372.prim_prince_test.235241263 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 1799430057 ps |
| CPU time | 30.95 seconds |
| Started | Aug 21 02:43:32 AM UTC 24 |
| Finished | Aug 21 02:44:12 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=235241263 -assert nopostproc +UVM_TES TNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pr im_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 372.prim_prince_test.235241263 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/372.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/373.prim_prince_test.3908871829 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 2075140770 ps |
| CPU time | 35.6 seconds |
| Started | Aug 21 02:43:40 AM UTC 24 |
| Finished | Aug 21 02:44:26 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3908871829 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 373.prim_prince_test.3908871829 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/373.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/374.prim_prince_test.4075298483 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 877535887 ps |
| CPU time | 15.57 seconds |
| Started | Aug 21 02:43:40 AM UTC 24 |
| Finished | Aug 21 02:44:01 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4075298483 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 374.prim_prince_test.4075298483 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/374.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/375.prim_prince_test.1117079721 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 829312832 ps |
| CPU time | 14.54 seconds |
| Started | Aug 21 02:43:43 AM UTC 24 |
| Finished | Aug 21 02:44:03 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1117079721 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 375.prim_prince_test.1117079721 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/375.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/376.prim_prince_test.2960878288 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 2269575349 ps |
| CPU time | 38.38 seconds |
| Started | Aug 21 02:43:51 AM UTC 24 |
| Finished | Aug 21 02:44:40 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2960878288 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 376.prim_prince_test.2960878288 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/376.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/377.prim_prince_test.2120755513 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 2875681249 ps |
| CPU time | 48.72 seconds |
| Started | Aug 21 02:43:51 AM UTC 24 |
| Finished | Aug 21 02:44:53 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2120755513 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 377.prim_prince_test.2120755513 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/377.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/378.prim_prince_test.2848887833 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 824329650 ps |
| CPU time | 14.19 seconds |
| Started | Aug 21 02:43:52 AM UTC 24 |
| Finished | Aug 21 02:44:11 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2848887833 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 378.prim_prince_test.2848887833 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/378.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/379.prim_prince_test.2051851335 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 1077298479 ps |
| CPU time | 18.57 seconds |
| Started | Aug 21 02:43:58 AM UTC 24 |
| Finished | Aug 21 02:44:22 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2051851335 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 379.prim_prince_test.2051851335 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/379.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/38.prim_prince_test.3525431807 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 2010024118 ps |
| CPU time | 34.17 seconds |
| Started | Aug 21 02:29:22 AM UTC 24 |
| Finished | Aug 21 02:30:05 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3525431807 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_prince_test.3525431807 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/38.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/380.prim_prince_test.1879597831 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 1089934332 ps |
| CPU time | 18.63 seconds |
| Started | Aug 21 02:44:00 AM UTC 24 |
| Finished | Aug 21 02:44:25 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1879597831 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 380.prim_prince_test.1879597831 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/380.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/381.prim_prince_test.2295247438 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 1907620951 ps |
| CPU time | 32.43 seconds |
| Started | Aug 21 02:44:01 AM UTC 24 |
| Finished | Aug 21 02:44:43 AM UTC 24 |
| Peak memory | 154572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2295247438 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 381.prim_prince_test.2295247438 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/381.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/382.prim_prince_test.319627623 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 962925430 ps |
| CPU time | 16.65 seconds |
| Started | Aug 21 02:44:01 AM UTC 24 |
| Finished | Aug 21 02:44:23 AM UTC 24 |
| Peak memory | 154604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=319627623 -assert nopostproc +UVM_TES TNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pr im_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 382.prim_prince_test.319627623 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/382.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/383.prim_prince_test.696703890 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 3672423977 ps |
| CPU time | 61.81 seconds |
| Started | Aug 21 02:44:03 AM UTC 24 |
| Finished | Aug 21 02:45:23 AM UTC 24 |
| Peak memory | 154668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=696703890 -assert nopostproc +UVM_TES TNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pr im_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 383.prim_prince_test.696703890 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/383.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/384.prim_prince_test.4112092852 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 1432579759 ps |
| CPU time | 24.64 seconds |
| Started | Aug 21 02:44:05 AM UTC 24 |
| Finished | Aug 21 02:44:37 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4112092852 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 384.prim_prince_test.4112092852 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/384.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/385.prim_prince_test.1904298621 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 2442181140 ps |
| CPU time | 41.39 seconds |
| Started | Aug 21 02:44:10 AM UTC 24 |
| Finished | Aug 21 02:45:03 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1904298621 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 385.prim_prince_test.1904298621 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/385.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/386.prim_prince_test.552065110 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 3411012053 ps |
| CPU time | 57.22 seconds |
| Started | Aug 21 02:44:12 AM UTC 24 |
| Finished | Aug 21 02:45:26 AM UTC 24 |
| Peak memory | 154668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=552065110 -assert nopostproc +UVM_TES TNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pr im_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 386.prim_prince_test.552065110 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/386.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/387.prim_prince_test.1271865278 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 1244513243 ps |
| CPU time | 21.42 seconds |
| Started | Aug 21 02:44:12 AM UTC 24 |
| Finished | Aug 21 02:44:40 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1271865278 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 387.prim_prince_test.1271865278 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/387.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/388.prim_prince_test.2974357446 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 957019940 ps |
| CPU time | 16.44 seconds |
| Started | Aug 21 02:44:13 AM UTC 24 |
| Finished | Aug 21 02:44:35 AM UTC 24 |
| Peak memory | 154596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2974357446 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 388.prim_prince_test.2974357446 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/388.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/389.prim_prince_test.420635299 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 1455798837 ps |
| CPU time | 24.87 seconds |
| Started | Aug 21 02:44:15 AM UTC 24 |
| Finished | Aug 21 02:44:48 AM UTC 24 |
| Peak memory | 154604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=420635299 -assert nopostproc +UVM_TES TNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pr im_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 389.prim_prince_test.420635299 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/389.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/39.prim_prince_test.448029220 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 1905133504 ps |
| CPU time | 32.3 seconds |
| Started | Aug 21 02:29:25 AM UTC 24 |
| Finished | Aug 21 02:30:07 AM UTC 24 |
| Peak memory | 154596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=448029220 -assert nopostproc +UVM_TES TNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pr im_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_prince_test.448029220 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/39.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/390.prim_prince_test.3832557455 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 2230638031 ps |
| CPU time | 37.83 seconds |
| Started | Aug 21 02:44:19 AM UTC 24 |
| Finished | Aug 21 02:45:08 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3832557455 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 390.prim_prince_test.3832557455 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/390.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/391.prim_prince_test.4027675741 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 2831400510 ps |
| CPU time | 47.33 seconds |
| Started | Aug 21 02:44:21 AM UTC 24 |
| Finished | Aug 21 02:45:22 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4027675741 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 391.prim_prince_test.4027675741 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/391.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/392.prim_prince_test.1003447009 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 2201785201 ps |
| CPU time | 36.94 seconds |
| Started | Aug 21 02:44:22 AM UTC 24 |
| Finished | Aug 21 02:45:10 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1003447009 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 392.prim_prince_test.1003447009 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/392.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/393.prim_prince_test.2957958257 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 806025937 ps |
| CPU time | 14.04 seconds |
| Started | Aug 21 02:44:23 AM UTC 24 |
| Finished | Aug 21 02:44:42 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2957958257 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 393.prim_prince_test.2957958257 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/393.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/394.prim_prince_test.1767866938 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 3223041750 ps |
| CPU time | 53.85 seconds |
| Started | Aug 21 02:44:24 AM UTC 24 |
| Finished | Aug 21 02:45:34 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1767866938 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 394.prim_prince_test.1767866938 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/394.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/395.prim_prince_test.1797581375 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 3234229666 ps |
| CPU time | 54.95 seconds |
| Started | Aug 21 02:44:25 AM UTC 24 |
| Finished | Aug 21 02:45:36 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1797581375 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 395.prim_prince_test.1797581375 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/395.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/396.prim_prince_test.1354151263 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 2127903263 ps |
| CPU time | 36.51 seconds |
| Started | Aug 21 02:44:27 AM UTC 24 |
| Finished | Aug 21 02:45:15 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1354151263 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 396.prim_prince_test.1354151263 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/396.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/397.prim_prince_test.2720243082 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 2192386457 ps |
| CPU time | 36.79 seconds |
| Started | Aug 21 02:44:32 AM UTC 24 |
| Finished | Aug 21 02:45:20 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2720243082 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 397.prim_prince_test.2720243082 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/397.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/398.prim_prince_test.125164388 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 2289344877 ps |
| CPU time | 38.24 seconds |
| Started | Aug 21 02:44:36 AM UTC 24 |
| Finished | Aug 21 02:45:25 AM UTC 24 |
| Peak memory | 154668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=125164388 -assert nopostproc +UVM_TES TNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pr im_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 398.prim_prince_test.125164388 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/398.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/399.prim_prince_test.3162470608 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 1617325884 ps |
| CPU time | 27.35 seconds |
| Started | Aug 21 02:44:38 AM UTC 24 |
| Finished | Aug 21 02:45:14 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3162470608 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 399.prim_prince_test.3162470608 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/399.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/4.prim_prince_test.4055764516 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 1272680424 ps |
| CPU time | 22.11 seconds |
| Started | Aug 21 02:27:54 AM UTC 24 |
| Finished | Aug 21 02:28:22 AM UTC 24 |
| Peak memory | 154596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4055764516 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_prince_test.4055764516 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/4.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/40.prim_prince_test.3417224500 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 3061495229 ps |
| CPU time | 52.05 seconds |
| Started | Aug 21 02:29:25 AM UTC 24 |
| Finished | Aug 21 02:30:31 AM UTC 24 |
| Peak memory | 154660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3417224500 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_prince_test.3417224500 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/40.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/400.prim_prince_test.952872267 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 1048938079 ps |
| CPU time | 17.93 seconds |
| Started | Aug 21 02:44:38 AM UTC 24 |
| Finished | Aug 21 02:45:02 AM UTC 24 |
| Peak memory | 154604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=952872267 -assert nopostproc +UVM_TES TNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pr im_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 400.prim_prince_test.952872267 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/400.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/401.prim_prince_test.659695863 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 2184888128 ps |
| CPU time | 37.32 seconds |
| Started | Aug 21 02:44:40 AM UTC 24 |
| Finished | Aug 21 02:45:28 AM UTC 24 |
| Peak memory | 154672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=659695863 -assert nopostproc +UVM_TES TNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pr im_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 401.prim_prince_test.659695863 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/401.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/402.prim_prince_test.128823183 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 2365448271 ps |
| CPU time | 40.03 seconds |
| Started | Aug 21 02:44:41 AM UTC 24 |
| Finished | Aug 21 02:45:33 AM UTC 24 |
| Peak memory | 154196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=128823183 -assert nopostproc +UVM_TES TNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pr im_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 402.prim_prince_test.128823183 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/402.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/403.prim_prince_test.1111376253 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 1018821052 ps |
| CPU time | 17.44 seconds |
| Started | Aug 21 02:44:41 AM UTC 24 |
| Finished | Aug 21 02:45:04 AM UTC 24 |
| Peak memory | 153960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1111376253 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 403.prim_prince_test.1111376253 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/403.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/404.prim_prince_test.141839790 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 2908502597 ps |
| CPU time | 48.55 seconds |
| Started | Aug 21 02:44:42 AM UTC 24 |
| Finished | Aug 21 02:45:45 AM UTC 24 |
| Peak memory | 154668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=141839790 -assert nopostproc +UVM_TES TNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pr im_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 404.prim_prince_test.141839790 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/404.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/405.prim_prince_test.3554811111 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 3153686760 ps |
| CPU time | 53.07 seconds |
| Started | Aug 21 02:44:45 AM UTC 24 |
| Finished | Aug 21 02:45:53 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3554811111 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 405.prim_prince_test.3554811111 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/405.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/406.prim_prince_test.3592939903 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 3003292708 ps |
| CPU time | 50.22 seconds |
| Started | Aug 21 02:44:47 AM UTC 24 |
| Finished | Aug 21 02:45:51 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3592939903 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 406.prim_prince_test.3592939903 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/406.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/407.prim_prince_test.4040262971 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 2539806659 ps |
| CPU time | 42.99 seconds |
| Started | Aug 21 02:44:49 AM UTC 24 |
| Finished | Aug 21 02:45:44 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4040262971 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 407.prim_prince_test.4040262971 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/407.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/408.prim_prince_test.2322617604 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 1522261379 ps |
| CPU time | 26.17 seconds |
| Started | Aug 21 02:44:54 AM UTC 24 |
| Finished | Aug 21 02:45:28 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2322617604 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 408.prim_prince_test.2322617604 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/408.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/409.prim_prince_test.1022001951 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 2291368248 ps |
| CPU time | 39.1 seconds |
| Started | Aug 21 02:45:03 AM UTC 24 |
| Finished | Aug 21 02:45:54 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1022001951 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 409.prim_prince_test.1022001951 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/409.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/41.prim_prince_test.743233108 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 2299380463 ps |
| CPU time | 39.58 seconds |
| Started | Aug 21 02:29:26 AM UTC 24 |
| Finished | Aug 21 02:30:17 AM UTC 24 |
| Peak memory | 154660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=743233108 -assert nopostproc +UVM_TES TNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pr im_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_prince_test.743233108 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/41.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/410.prim_prince_test.272982784 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 3368936302 ps |
| CPU time | 56.67 seconds |
| Started | Aug 21 02:45:04 AM UTC 24 |
| Finished | Aug 21 02:46:17 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=272982784 -assert nopostproc +UVM_TES TNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pr im_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 410.prim_prince_test.272982784 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/410.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/411.prim_prince_test.4032643929 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 1423538257 ps |
| CPU time | 24.06 seconds |
| Started | Aug 21 02:45:05 AM UTC 24 |
| Finished | Aug 21 02:45:37 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4032643929 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 411.prim_prince_test.4032643929 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/411.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/412.prim_prince_test.1632188031 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 3512948691 ps |
| CPU time | 58.86 seconds |
| Started | Aug 21 02:45:10 AM UTC 24 |
| Finished | Aug 21 02:46:25 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1632188031 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 412.prim_prince_test.1632188031 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/412.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/413.prim_prince_test.1394086703 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 2672360497 ps |
| CPU time | 44.87 seconds |
| Started | Aug 21 02:45:11 AM UTC 24 |
| Finished | Aug 21 02:46:08 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1394086703 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 413.prim_prince_test.1394086703 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/413.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/414.prim_prince_test.1264144473 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 2837878786 ps |
| CPU time | 47.93 seconds |
| Started | Aug 21 02:45:15 AM UTC 24 |
| Finished | Aug 21 02:46:16 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1264144473 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 414.prim_prince_test.1264144473 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/414.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/415.prim_prince_test.3403299743 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 1345666228 ps |
| CPU time | 22.92 seconds |
| Started | Aug 21 02:45:16 AM UTC 24 |
| Finished | Aug 21 02:45:46 AM UTC 24 |
| Peak memory | 154596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3403299743 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 415.prim_prince_test.3403299743 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/415.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/416.prim_prince_test.3084817906 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 3539381258 ps |
| CPU time | 59.27 seconds |
| Started | Aug 21 02:45:21 AM UTC 24 |
| Finished | Aug 21 02:46:37 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3084817906 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 416.prim_prince_test.3084817906 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/416.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/417.prim_prince_test.3962646025 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 3272632338 ps |
| CPU time | 55 seconds |
| Started | Aug 21 02:45:23 AM UTC 24 |
| Finished | Aug 21 02:46:34 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3962646025 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 417.prim_prince_test.3962646025 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/417.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/418.prim_prince_test.2960768385 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 1342029677 ps |
| CPU time | 22.98 seconds |
| Started | Aug 21 02:45:23 AM UTC 24 |
| Finished | Aug 21 02:45:53 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2960768385 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 418.prim_prince_test.2960768385 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/418.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/419.prim_prince_test.1034556941 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 3266367623 ps |
| CPU time | 55.02 seconds |
| Started | Aug 21 02:45:26 AM UTC 24 |
| Finished | Aug 21 02:46:36 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1034556941 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 419.prim_prince_test.1034556941 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/419.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/42.prim_prince_test.242408018 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 2433421855 ps |
| CPU time | 41.42 seconds |
| Started | Aug 21 02:29:27 AM UTC 24 |
| Finished | Aug 21 02:30:20 AM UTC 24 |
| Peak memory | 154660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=242408018 -assert nopostproc +UVM_TES TNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pr im_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_prince_test.242408018 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/42.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/420.prim_prince_test.2365157521 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 869261726 ps |
| CPU time | 14.98 seconds |
| Started | Aug 21 02:45:27 AM UTC 24 |
| Finished | Aug 21 02:45:47 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2365157521 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 420.prim_prince_test.2365157521 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/420.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/421.prim_prince_test.717016195 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 3255020622 ps |
| CPU time | 54.97 seconds |
| Started | Aug 21 02:45:29 AM UTC 24 |
| Finished | Aug 21 02:46:40 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=717016195 -assert nopostproc +UVM_TES TNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pr im_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 421.prim_prince_test.717016195 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/421.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/422.prim_prince_test.61211684 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 2886800396 ps |
| CPU time | 48.72 seconds |
| Started | Aug 21 02:45:29 AM UTC 24 |
| Finished | Aug 21 02:46:32 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=61211684 -assert nopostproc +UVM_TEST NAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pri m_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 422.prim_prince_test.61211684 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/422.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/423.prim_prince_test.1010768876 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 877433200 ps |
| CPU time | 15.09 seconds |
| Started | Aug 21 02:45:34 AM UTC 24 |
| Finished | Aug 21 02:45:54 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1010768876 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 423.prim_prince_test.1010768876 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/423.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/424.prim_prince_test.3263309730 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 912646335 ps |
| CPU time | 15.77 seconds |
| Started | Aug 21 02:45:35 AM UTC 24 |
| Finished | Aug 21 02:45:56 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3263309730 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 424.prim_prince_test.3263309730 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/424.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/425.prim_prince_test.1639133790 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 3661666305 ps |
| CPU time | 61.27 seconds |
| Started | Aug 21 02:45:38 AM UTC 24 |
| Finished | Aug 21 02:46:56 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1639133790 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 425.prim_prince_test.1639133790 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/425.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/426.prim_prince_test.749848855 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 3029825035 ps |
| CPU time | 51.25 seconds |
| Started | Aug 21 02:45:38 AM UTC 24 |
| Finished | Aug 21 02:46:43 AM UTC 24 |
| Peak memory | 154668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=749848855 -assert nopostproc +UVM_TES TNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pr im_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 426.prim_prince_test.749848855 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/426.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/427.prim_prince_test.19251443 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 3438563040 ps |
| CPU time | 57.53 seconds |
| Started | Aug 21 02:45:45 AM UTC 24 |
| Finished | Aug 21 02:46:59 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=19251443 -assert nopostproc +UVM_TEST NAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pri m_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 427.prim_prince_test.19251443 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/427.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/428.prim_prince_test.2098899383 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 1011535721 ps |
| CPU time | 17.47 seconds |
| Started | Aug 21 02:45:46 AM UTC 24 |
| Finished | Aug 21 02:46:09 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2098899383 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 428.prim_prince_test.2098899383 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/428.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/429.prim_prince_test.1228852318 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 890143107 ps |
| CPU time | 15.43 seconds |
| Started | Aug 21 02:45:47 AM UTC 24 |
| Finished | Aug 21 02:46:08 AM UTC 24 |
| Peak memory | 154596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1228852318 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 429.prim_prince_test.1228852318 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/429.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/43.prim_prince_test.4139815970 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 2347686764 ps |
| CPU time | 39.87 seconds |
| Started | Aug 21 02:29:28 AM UTC 24 |
| Finished | Aug 21 02:30:19 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4139815970 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_prince_test.4139815970 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/43.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/430.prim_prince_test.2056475287 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 2577524784 ps |
| CPU time | 43.78 seconds |
| Started | Aug 21 02:45:47 AM UTC 24 |
| Finished | Aug 21 02:46:43 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2056475287 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 430.prim_prince_test.2056475287 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/430.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/431.prim_prince_test.3194012372 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 1752874724 ps |
| CPU time | 29.56 seconds |
| Started | Aug 21 02:45:52 AM UTC 24 |
| Finished | Aug 21 02:46:31 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3194012372 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 431.prim_prince_test.3194012372 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/431.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/432.prim_prince_test.1841896027 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 1329880001 ps |
| CPU time | 22.78 seconds |
| Started | Aug 21 02:45:53 AM UTC 24 |
| Finished | Aug 21 02:46:23 AM UTC 24 |
| Peak memory | 154604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1841896027 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 432.prim_prince_test.1841896027 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/432.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/433.prim_prince_test.3395255983 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 978981434 ps |
| CPU time | 16.67 seconds |
| Started | Aug 21 02:45:55 AM UTC 24 |
| Finished | Aug 21 02:46:17 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3395255983 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 433.prim_prince_test.3395255983 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/433.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/434.prim_prince_test.2121462111 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 1615508222 ps |
| CPU time | 27.54 seconds |
| Started | Aug 21 02:45:55 AM UTC 24 |
| Finished | Aug 21 02:46:31 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2121462111 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 434.prim_prince_test.2121462111 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/434.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/435.prim_prince_test.2009840682 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 2210660196 ps |
| CPU time | 37.75 seconds |
| Started | Aug 21 02:45:55 AM UTC 24 |
| Finished | Aug 21 02:46:44 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2009840682 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 435.prim_prince_test.2009840682 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/435.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/436.prim_prince_test.3140145059 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 2082128516 ps |
| CPU time | 35.03 seconds |
| Started | Aug 21 02:45:57 AM UTC 24 |
| Finished | Aug 21 02:46:43 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3140145059 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 436.prim_prince_test.3140145059 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/436.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/437.prim_prince_test.3553286610 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 1845421467 ps |
| CPU time | 31.11 seconds |
| Started | Aug 21 02:46:08 AM UTC 24 |
| Finished | Aug 21 02:46:49 AM UTC 24 |
| Peak memory | 154596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3553286610 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 437.prim_prince_test.3553286610 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/437.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/438.prim_prince_test.1158319243 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 2844414983 ps |
| CPU time | 48.43 seconds |
| Started | Aug 21 02:46:09 AM UTC 24 |
| Finished | Aug 21 02:47:12 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1158319243 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 438.prim_prince_test.1158319243 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/438.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/439.prim_prince_test.3673942003 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 2191148918 ps |
| CPU time | 37.11 seconds |
| Started | Aug 21 02:46:10 AM UTC 24 |
| Finished | Aug 21 02:46:58 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3673942003 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 439.prim_prince_test.3673942003 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/439.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/44.prim_prince_test.1776771016 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 1241978657 ps |
| CPU time | 21.29 seconds |
| Started | Aug 21 02:29:29 AM UTC 24 |
| Finished | Aug 21 02:29:57 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1776771016 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_prince_test.1776771016 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/44.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/440.prim_prince_test.1155859850 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 2535220448 ps |
| CPU time | 43.03 seconds |
| Started | Aug 21 02:46:18 AM UTC 24 |
| Finished | Aug 21 02:47:14 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1155859850 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 440.prim_prince_test.1155859850 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/440.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/441.prim_prince_test.1708111809 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 1367518237 ps |
| CPU time | 23.16 seconds |
| Started | Aug 21 02:46:18 AM UTC 24 |
| Finished | Aug 21 02:46:48 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1708111809 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 441.prim_prince_test.1708111809 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/441.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/442.prim_prince_test.1864019467 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 1151932063 ps |
| CPU time | 19.76 seconds |
| Started | Aug 21 02:46:18 AM UTC 24 |
| Finished | Aug 21 02:46:44 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1864019467 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 442.prim_prince_test.1864019467 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/442.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/443.prim_prince_test.3422100188 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 2708614836 ps |
| CPU time | 45.86 seconds |
| Started | Aug 21 02:46:24 AM UTC 24 |
| Finished | Aug 21 02:47:23 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3422100188 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 443.prim_prince_test.3422100188 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/443.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/444.prim_prince_test.1397027623 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 2688914614 ps |
| CPU time | 45.3 seconds |
| Started | Aug 21 02:46:26 AM UTC 24 |
| Finished | Aug 21 02:47:25 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1397027623 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 444.prim_prince_test.1397027623 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/444.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/445.prim_prince_test.2796396824 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 845339153 ps |
| CPU time | 14.75 seconds |
| Started | Aug 21 02:46:32 AM UTC 24 |
| Finished | Aug 21 02:46:51 AM UTC 24 |
| Peak memory | 154580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2796396824 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 445.prim_prince_test.2796396824 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/445.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/446.prim_prince_test.4080073429 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 1014815308 ps |
| CPU time | 17.59 seconds |
| Started | Aug 21 02:46:32 AM UTC 24 |
| Finished | Aug 21 02:46:55 AM UTC 24 |
| Peak memory | 154588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4080073429 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 446.prim_prince_test.4080073429 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/446.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/447.prim_prince_test.935286825 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 2175476869 ps |
| CPU time | 36.84 seconds |
| Started | Aug 21 02:46:33 AM UTC 24 |
| Finished | Aug 21 02:47:20 AM UTC 24 |
| Peak memory | 154668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=935286825 -assert nopostproc +UVM_TES TNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pr im_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 447.prim_prince_test.935286825 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/447.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/448.prim_prince_test.3487293279 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 2704416439 ps |
| CPU time | 45.39 seconds |
| Started | Aug 21 02:46:35 AM UTC 24 |
| Finished | Aug 21 02:47:33 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3487293279 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 448.prim_prince_test.3487293279 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/448.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/449.prim_prince_test.3410814217 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 3709642628 ps |
| CPU time | 62.12 seconds |
| Started | Aug 21 02:46:37 AM UTC 24 |
| Finished | Aug 21 02:47:57 AM UTC 24 |
| Peak memory | 156532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3410814217 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 449.prim_prince_test.3410814217 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/449.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/45.prim_prince_test.2499462815 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 3226393657 ps |
| CPU time | 54.81 seconds |
| Started | Aug 21 02:29:30 AM UTC 24 |
| Finished | Aug 21 02:30:40 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2499462815 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_prince_test.2499462815 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/45.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/450.prim_prince_test.41860187 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 3115702171 ps |
| CPU time | 52.33 seconds |
| Started | Aug 21 02:46:38 AM UTC 24 |
| Finished | Aug 21 02:47:46 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=41860187 -assert nopostproc +UVM_TEST NAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pri m_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 450.prim_prince_test.41860187 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/450.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/451.prim_prince_test.3133694349 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 2689955112 ps |
| CPU time | 45.4 seconds |
| Started | Aug 21 02:46:40 AM UTC 24 |
| Finished | Aug 21 02:47:39 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3133694349 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 451.prim_prince_test.3133694349 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/451.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/452.prim_prince_test.1197594389 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 949925035 ps |
| CPU time | 16.2 seconds |
| Started | Aug 21 02:46:43 AM UTC 24 |
| Finished | Aug 21 02:47:05 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1197594389 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 452.prim_prince_test.1197594389 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/452.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/453.prim_prince_test.2285398278 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 1471124670 ps |
| CPU time | 25.18 seconds |
| Started | Aug 21 02:46:45 AM UTC 24 |
| Finished | Aug 21 02:47:18 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2285398278 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 453.prim_prince_test.2285398278 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/453.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/454.prim_prince_test.1437836745 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 859580939 ps |
| CPU time | 14.83 seconds |
| Started | Aug 21 02:46:45 AM UTC 24 |
| Finished | Aug 21 02:47:05 AM UTC 24 |
| Peak memory | 154588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1437836745 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 454.prim_prince_test.1437836745 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/454.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/455.prim_prince_test.1447752429 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 1503012149 ps |
| CPU time | 25.56 seconds |
| Started | Aug 21 02:46:45 AM UTC 24 |
| Finished | Aug 21 02:47:18 AM UTC 24 |
| Peak memory | 154580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1447752429 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 455.prim_prince_test.1447752429 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/455.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/456.prim_prince_test.3787837646 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 2618356368 ps |
| CPU time | 44.21 seconds |
| Started | Aug 21 02:46:45 AM UTC 24 |
| Finished | Aug 21 02:47:42 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3787837646 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 456.prim_prince_test.3787837646 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/456.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/457.prim_prince_test.1713182148 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 2420073762 ps |
| CPU time | 40.68 seconds |
| Started | Aug 21 02:46:49 AM UTC 24 |
| Finished | Aug 21 02:47:42 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1713182148 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 457.prim_prince_test.1713182148 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/457.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/458.prim_prince_test.442074324 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 2772805475 ps |
| CPU time | 47.12 seconds |
| Started | Aug 21 02:46:49 AM UTC 24 |
| Finished | Aug 21 02:47:50 AM UTC 24 |
| Peak memory | 154668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=442074324 -assert nopostproc +UVM_TES TNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pr im_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 458.prim_prince_test.442074324 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/458.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/459.prim_prince_test.449690030 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 3019336568 ps |
| CPU time | 51.03 seconds |
| Started | Aug 21 02:46:51 AM UTC 24 |
| Finished | Aug 21 02:47:57 AM UTC 24 |
| Peak memory | 154672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=449690030 -assert nopostproc +UVM_TES TNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pr im_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 459.prim_prince_test.449690030 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/459.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/46.prim_prince_test.832716598 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 1831498130 ps |
| CPU time | 31.58 seconds |
| Started | Aug 21 02:29:32 AM UTC 24 |
| Finished | Aug 21 02:30:13 AM UTC 24 |
| Peak memory | 154596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=832716598 -assert nopostproc +UVM_TES TNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pr im_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_prince_test.832716598 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/46.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/460.prim_prince_test.2930872059 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 824240795 ps |
| CPU time | 14.6 seconds |
| Started | Aug 21 02:46:56 AM UTC 24 |
| Finished | Aug 21 02:47:15 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2930872059 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 460.prim_prince_test.2930872059 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/460.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/461.prim_prince_test.2632626873 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 3123509994 ps |
| CPU time | 52.6 seconds |
| Started | Aug 21 02:46:57 AM UTC 24 |
| Finished | Aug 21 02:48:04 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2632626873 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 461.prim_prince_test.2632626873 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/461.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/462.prim_prince_test.2662615623 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 860799036 ps |
| CPU time | 15.02 seconds |
| Started | Aug 21 02:46:58 AM UTC 24 |
| Finished | Aug 21 02:47:18 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2662615623 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 462.prim_prince_test.2662615623 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/462.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/463.prim_prince_test.651621084 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 2204143949 ps |
| CPU time | 37.22 seconds |
| Started | Aug 21 02:46:59 AM UTC 24 |
| Finished | Aug 21 02:47:47 AM UTC 24 |
| Peak memory | 154668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=651621084 -assert nopostproc +UVM_TES TNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pr im_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 463.prim_prince_test.651621084 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/463.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/464.prim_prince_test.3036334847 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 894969060 ps |
| CPU time | 15.56 seconds |
| Started | Aug 21 02:47:05 AM UTC 24 |
| Finished | Aug 21 02:47:26 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3036334847 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 464.prim_prince_test.3036334847 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/464.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/465.prim_prince_test.897424773 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 894695634 ps |
| CPU time | 15.58 seconds |
| Started | Aug 21 02:47:06 AM UTC 24 |
| Finished | Aug 21 02:47:27 AM UTC 24 |
| Peak memory | 154604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=897424773 -assert nopostproc +UVM_TES TNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pr im_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 465.prim_prince_test.897424773 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/465.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/466.prim_prince_test.3038542242 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 3038797243 ps |
| CPU time | 51.33 seconds |
| Started | Aug 21 02:47:13 AM UTC 24 |
| Finished | Aug 21 02:48:19 AM UTC 24 |
| Peak memory | 154668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3038542242 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 466.prim_prince_test.3038542242 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/466.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/467.prim_prince_test.1103555402 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 2523412325 ps |
| CPU time | 42.28 seconds |
| Started | Aug 21 02:47:15 AM UTC 24 |
| Finished | Aug 21 02:48:10 AM UTC 24 |
| Peak memory | 154668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1103555402 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 467.prim_prince_test.1103555402 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/467.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/468.prim_prince_test.2962226019 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 907421440 ps |
| CPU time | 15.46 seconds |
| Started | Aug 21 02:47:16 AM UTC 24 |
| Finished | Aug 21 02:47:36 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2962226019 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 468.prim_prince_test.2962226019 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/468.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/469.prim_prince_test.2966217681 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 3515142617 ps |
| CPU time | 58.92 seconds |
| Started | Aug 21 02:47:19 AM UTC 24 |
| Finished | Aug 21 02:48:35 AM UTC 24 |
| Peak memory | 156532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2966217681 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 469.prim_prince_test.2966217681 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/469.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/47.prim_prince_test.2972686481 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 2253125902 ps |
| CPU time | 38.5 seconds |
| Started | Aug 21 02:29:36 AM UTC 24 |
| Finished | Aug 21 02:30:25 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2972686481 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_prince_test.2972686481 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/47.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/470.prim_prince_test.2590826010 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 1310372893 ps |
| CPU time | 22.37 seconds |
| Started | Aug 21 02:47:19 AM UTC 24 |
| Finished | Aug 21 02:47:49 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2590826010 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 470.prim_prince_test.2590826010 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/470.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/471.prim_prince_test.398845675 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 2592948186 ps |
| CPU time | 43.61 seconds |
| Started | Aug 21 02:47:19 AM UTC 24 |
| Finished | Aug 21 02:48:16 AM UTC 24 |
| Peak memory | 154668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=398845675 -assert nopostproc +UVM_TES TNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pr im_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 471.prim_prince_test.398845675 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/471.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/472.prim_prince_test.2685550609 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 1647607078 ps |
| CPU time | 27.88 seconds |
| Started | Aug 21 02:47:22 AM UTC 24 |
| Finished | Aug 21 02:47:58 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2685550609 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 472.prim_prince_test.2685550609 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/472.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/473.prim_prince_test.3555847293 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 3105243075 ps |
| CPU time | 52.39 seconds |
| Started | Aug 21 02:47:24 AM UTC 24 |
| Finished | Aug 21 02:48:31 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3555847293 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 473.prim_prince_test.3555847293 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/473.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/474.prim_prince_test.2351449335 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 3173858091 ps |
| CPU time | 53.16 seconds |
| Started | Aug 21 02:47:26 AM UTC 24 |
| Finished | Aug 21 02:48:34 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2351449335 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 474.prim_prince_test.2351449335 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/474.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/475.prim_prince_test.1852954094 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 3726868034 ps |
| CPU time | 62.74 seconds |
| Started | Aug 21 02:47:27 AM UTC 24 |
| Finished | Aug 21 02:48:47 AM UTC 24 |
| Peak memory | 154668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1852954094 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 475.prim_prince_test.1852954094 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/475.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/476.prim_prince_test.4152464105 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 1450278264 ps |
| CPU time | 24.58 seconds |
| Started | Aug 21 02:47:28 AM UTC 24 |
| Finished | Aug 21 02:48:00 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4152464105 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 476.prim_prince_test.4152464105 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/476.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/477.prim_prince_test.379821375 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 1270951051 ps |
| CPU time | 21.72 seconds |
| Started | Aug 21 02:47:34 AM UTC 24 |
| Finished | Aug 21 02:48:03 AM UTC 24 |
| Peak memory | 154604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=379821375 -assert nopostproc +UVM_TES TNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pr im_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 477.prim_prince_test.379821375 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/477.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/478.prim_prince_test.728108969 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 1931487688 ps |
| CPU time | 32.56 seconds |
| Started | Aug 21 02:47:37 AM UTC 24 |
| Finished | Aug 21 02:48:20 AM UTC 24 |
| Peak memory | 154604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=728108969 -assert nopostproc +UVM_TES TNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pr im_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 478.prim_prince_test.728108969 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/478.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/479.prim_prince_test.2798143220 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 2022846373 ps |
| CPU time | 34.29 seconds |
| Started | Aug 21 02:47:40 AM UTC 24 |
| Finished | Aug 21 02:48:24 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2798143220 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 479.prim_prince_test.2798143220 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/479.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/48.prim_prince_test.2813242030 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 1696322510 ps |
| CPU time | 28.93 seconds |
| Started | Aug 21 02:29:42 AM UTC 24 |
| Finished | Aug 21 02:30:19 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2813242030 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_prince_test.2813242030 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/48.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/480.prim_prince_test.3120007903 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 3208043284 ps |
| CPU time | 54.05 seconds |
| Started | Aug 21 02:47:43 AM UTC 24 |
| Finished | Aug 21 02:48:52 AM UTC 24 |
| Peak memory | 154668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3120007903 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 480.prim_prince_test.3120007903 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/480.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/481.prim_prince_test.778738353 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 2777288642 ps |
| CPU time | 46.72 seconds |
| Started | Aug 21 02:47:43 AM UTC 24 |
| Finished | Aug 21 02:48:43 AM UTC 24 |
| Peak memory | 154668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=778738353 -assert nopostproc +UVM_TES TNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pr im_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 481.prim_prince_test.778738353 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/481.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/482.prim_prince_test.797772233 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 2886634467 ps |
| CPU time | 48.42 seconds |
| Started | Aug 21 02:47:46 AM UTC 24 |
| Finished | Aug 21 02:48:49 AM UTC 24 |
| Peak memory | 154672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=797772233 -assert nopostproc +UVM_TES TNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pr im_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 482.prim_prince_test.797772233 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/482.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/483.prim_prince_test.2247753821 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 3384452699 ps |
| CPU time | 56.75 seconds |
| Started | Aug 21 02:47:48 AM UTC 24 |
| Finished | Aug 21 02:49:02 AM UTC 24 |
| Peak memory | 154668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2247753821 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 483.prim_prince_test.2247753821 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/483.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/484.prim_prince_test.3489445809 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 1459284123 ps |
| CPU time | 24.83 seconds |
| Started | Aug 21 02:47:49 AM UTC 24 |
| Finished | Aug 21 02:48:22 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3489445809 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 484.prim_prince_test.3489445809 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/484.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/485.prim_prince_test.4203332875 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 3636267494 ps |
| CPU time | 61.31 seconds |
| Started | Aug 21 02:47:51 AM UTC 24 |
| Finished | Aug 21 02:49:10 AM UTC 24 |
| Peak memory | 154668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4203332875 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 485.prim_prince_test.4203332875 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/485.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/486.prim_prince_test.855565544 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 3300260605 ps |
| CPU time | 55.8 seconds |
| Started | Aug 21 02:47:58 AM UTC 24 |
| Finished | Aug 21 02:49:10 AM UTC 24 |
| Peak memory | 154668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=855565544 -assert nopostproc +UVM_TES TNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pr im_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 486.prim_prince_test.855565544 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/486.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/487.prim_prince_test.3360438504 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 1990755638 ps |
| CPU time | 33.63 seconds |
| Started | Aug 21 02:47:58 AM UTC 24 |
| Finished | Aug 21 02:48:42 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3360438504 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 487.prim_prince_test.3360438504 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/487.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/488.prim_prince_test.4036189885 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 3385189834 ps |
| CPU time | 56.67 seconds |
| Started | Aug 21 02:47:59 AM UTC 24 |
| Finished | Aug 21 02:49:13 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4036189885 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 488.prim_prince_test.4036189885 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/488.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/489.prim_prince_test.650030966 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 1907213597 ps |
| CPU time | 32.17 seconds |
| Started | Aug 21 02:48:01 AM UTC 24 |
| Finished | Aug 21 02:48:43 AM UTC 24 |
| Peak memory | 154604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=650030966 -assert nopostproc +UVM_TES TNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pr im_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 489.prim_prince_test.650030966 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/489.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/49.prim_prince_test.3328262411 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 3480067894 ps |
| CPU time | 58.94 seconds |
| Started | Aug 21 02:29:44 AM UTC 24 |
| Finished | Aug 21 02:31:00 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3328262411 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_prince_test.3328262411 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/49.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/490.prim_prince_test.2966646907 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 3431921177 ps |
| CPU time | 58.03 seconds |
| Started | Aug 21 02:48:03 AM UTC 24 |
| Finished | Aug 21 02:49:19 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2966646907 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 490.prim_prince_test.2966646907 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/490.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/491.prim_prince_test.405447487 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 3428148741 ps |
| CPU time | 58.28 seconds |
| Started | Aug 21 02:48:04 AM UTC 24 |
| Finished | Aug 21 02:49:20 AM UTC 24 |
| Peak memory | 154672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=405447487 -assert nopostproc +UVM_TES TNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pr im_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 491.prim_prince_test.405447487 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/491.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/492.prim_prince_test.640887474 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 1859158372 ps |
| CPU time | 31.25 seconds |
| Started | Aug 21 02:48:06 AM UTC 24 |
| Finished | Aug 21 02:48:46 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=640887474 -assert nopostproc +UVM_TES TNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pr im_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 492.prim_prince_test.640887474 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/492.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/493.prim_prince_test.2377074634 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 2380036733 ps |
| CPU time | 40.48 seconds |
| Started | Aug 21 02:48:11 AM UTC 24 |
| Finished | Aug 21 02:49:03 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2377074634 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 493.prim_prince_test.2377074634 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/493.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/494.prim_prince_test.47372639 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 1580486241 ps |
| CPU time | 27.04 seconds |
| Started | Aug 21 02:48:16 AM UTC 24 |
| Finished | Aug 21 02:48:51 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=47372639 -assert nopostproc +UVM_TEST NAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pri m_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 494.prim_prince_test.47372639 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/494.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/495.prim_prince_test.532092064 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 2400732829 ps |
| CPU time | 41.43 seconds |
| Started | Aug 21 02:48:19 AM UTC 24 |
| Finished | Aug 21 02:49:13 AM UTC 24 |
| Peak memory | 154668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=532092064 -assert nopostproc +UVM_TES TNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pr im_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 495.prim_prince_test.532092064 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/495.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/496.prim_prince_test.3400687353 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 2391472126 ps |
| CPU time | 40.71 seconds |
| Started | Aug 21 02:48:20 AM UTC 24 |
| Finished | Aug 21 02:49:13 AM UTC 24 |
| Peak memory | 154668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3400687353 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 496.prim_prince_test.3400687353 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/496.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/497.prim_prince_test.570352515 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 1638429389 ps |
| CPU time | 28.3 seconds |
| Started | Aug 21 02:48:23 AM UTC 24 |
| Finished | Aug 21 02:49:00 AM UTC 24 |
| Peak memory | 154604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=570352515 -assert nopostproc +UVM_TES TNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pr im_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 497.prim_prince_test.570352515 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/497.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/498.prim_prince_test.3508649103 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 817769274 ps |
| CPU time | 14 seconds |
| Started | Aug 21 02:48:25 AM UTC 24 |
| Finished | Aug 21 02:48:43 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3508649103 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 498.prim_prince_test.3508649103 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/498.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/499.prim_prince_test.583416343 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 1082503156 ps |
| CPU time | 18.4 seconds |
| Started | Aug 21 02:48:32 AM UTC 24 |
| Finished | Aug 21 02:48:56 AM UTC 24 |
| Peak memory | 154596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=583416343 -assert nopostproc +UVM_TES TNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pr im_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 499.prim_prince_test.583416343 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/499.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/5.prim_prince_test.1505850372 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 3636037148 ps |
| CPU time | 62.34 seconds |
| Started | Aug 21 02:27:54 AM UTC 24 |
| Finished | Aug 21 02:29:13 AM UTC 24 |
| Peak memory | 154660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1505850372 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_prince_test.1505850372 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/5.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/50.prim_prince_test.3087946591 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 2689331970 ps |
| CPU time | 45.93 seconds |
| Started | Aug 21 02:29:53 AM UTC 24 |
| Finished | Aug 21 02:30:52 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3087946591 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.prim_prince_test.3087946591 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/50.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/51.prim_prince_test.2514300372 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 2275069512 ps |
| CPU time | 38.86 seconds |
| Started | Aug 21 02:29:56 AM UTC 24 |
| Finished | Aug 21 02:30:46 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2514300372 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.prim_prince_test.2514300372 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/51.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/52.prim_prince_test.2915723824 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 2661546482 ps |
| CPU time | 45.42 seconds |
| Started | Aug 21 02:29:57 AM UTC 24 |
| Finished | Aug 21 02:30:56 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2915723824 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.prim_prince_test.2915723824 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/52.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/53.prim_prince_test.3264343651 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 1930000762 ps |
| CPU time | 33.21 seconds |
| Started | Aug 21 02:30:01 AM UTC 24 |
| Finished | Aug 21 02:30:44 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3264343651 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.prim_prince_test.3264343651 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/53.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/54.prim_prince_test.1274171358 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 1840514466 ps |
| CPU time | 31.26 seconds |
| Started | Aug 21 02:30:06 AM UTC 24 |
| Finished | Aug 21 02:30:47 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1274171358 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.prim_prince_test.1274171358 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/54.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/55.prim_prince_test.1360969689 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 1656341216 ps |
| CPU time | 28.24 seconds |
| Started | Aug 21 02:30:07 AM UTC 24 |
| Finished | Aug 21 02:30:44 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1360969689 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.prim_prince_test.1360969689 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/55.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/56.prim_prince_test.1779716936 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 2396292729 ps |
| CPU time | 40.79 seconds |
| Started | Aug 21 02:30:14 AM UTC 24 |
| Finished | Aug 21 02:31:06 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1779716936 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.prim_prince_test.1779716936 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/56.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/57.prim_prince_test.3988714183 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 2927267986 ps |
| CPU time | 49.6 seconds |
| Started | Aug 21 02:30:18 AM UTC 24 |
| Finished | Aug 21 02:31:21 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3988714183 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.prim_prince_test.3988714183 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/57.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/58.prim_prince_test.1240217468 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 3136715866 ps |
| CPU time | 53.36 seconds |
| Started | Aug 21 02:30:18 AM UTC 24 |
| Finished | Aug 21 02:31:26 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1240217468 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.prim_prince_test.1240217468 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/58.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/59.prim_prince_test.2919576745 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 2059673548 ps |
| CPU time | 34.92 seconds |
| Started | Aug 21 02:30:20 AM UTC 24 |
| Finished | Aug 21 02:31:05 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2919576745 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.prim_prince_test.2919576745 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/59.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/6.prim_prince_test.2188982575 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 2386203962 ps |
| CPU time | 41.48 seconds |
| Started | Aug 21 02:27:54 AM UTC 24 |
| Finished | Aug 21 02:28:47 AM UTC 24 |
| Peak memory | 154468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2188982575 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_prince_test.2188982575 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/6.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/60.prim_prince_test.4026472640 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 1769173762 ps |
| CPU time | 30.21 seconds |
| Started | Aug 21 02:30:21 AM UTC 24 |
| Finished | Aug 21 02:31:00 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4026472640 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.prim_prince_test.4026472640 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/60.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/61.prim_prince_test.2234208700 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 1421720438 ps |
| CPU time | 24.43 seconds |
| Started | Aug 21 02:30:21 AM UTC 24 |
| Finished | Aug 21 02:30:53 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2234208700 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.prim_prince_test.2234208700 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/61.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/62.prim_prince_test.2145879556 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 1196378817 ps |
| CPU time | 20.68 seconds |
| Started | Aug 21 02:30:26 AM UTC 24 |
| Finished | Aug 21 02:30:53 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2145879556 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.prim_prince_test.2145879556 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/62.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/63.prim_prince_test.91028095 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 1035360391 ps |
| CPU time | 18.11 seconds |
| Started | Aug 21 02:30:26 AM UTC 24 |
| Finished | Aug 21 02:30:50 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=91028095 -assert nopostproc +UVM_TEST NAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pri m_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.prim_prince_test.91028095 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/63.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/64.prim_prince_test.956508089 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 1807257313 ps |
| CPU time | 31.06 seconds |
| Started | Aug 21 02:30:32 AM UTC 24 |
| Finished | Aug 21 02:31:12 AM UTC 24 |
| Peak memory | 154596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=956508089 -assert nopostproc +UVM_TES TNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pr im_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.prim_prince_test.956508089 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/64.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/65.prim_prince_test.4133383147 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 2082740789 ps |
| CPU time | 35.44 seconds |
| Started | Aug 21 02:30:41 AM UTC 24 |
| Finished | Aug 21 02:31:27 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4133383147 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.prim_prince_test.4133383147 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/65.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/66.prim_prince_test.2377897379 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 3272853326 ps |
| CPU time | 55.77 seconds |
| Started | Aug 21 02:30:45 AM UTC 24 |
| Finished | Aug 21 02:31:57 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2377897379 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.prim_prince_test.2377897379 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/66.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/67.prim_prince_test.3771770912 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 3337237390 ps |
| CPU time | 56.59 seconds |
| Started | Aug 21 02:30:45 AM UTC 24 |
| Finished | Aug 21 02:31:58 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3771770912 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.prim_prince_test.3771770912 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/67.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/68.prim_prince_test.2088157948 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 3501588550 ps |
| CPU time | 59.27 seconds |
| Started | Aug 21 02:30:47 AM UTC 24 |
| Finished | Aug 21 02:32:03 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2088157948 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.prim_prince_test.2088157948 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/68.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/69.prim_prince_test.502567914 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 892952963 ps |
| CPU time | 15.59 seconds |
| Started | Aug 21 02:30:47 AM UTC 24 |
| Finished | Aug 21 02:31:08 AM UTC 24 |
| Peak memory | 154596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=502567914 -assert nopostproc +UVM_TES TNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pr im_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.prim_prince_test.502567914 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/69.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/7.prim_prince_test.1168621368 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 1912722616 ps |
| CPU time | 33.09 seconds |
| Started | Aug 21 02:27:54 AM UTC 24 |
| Finished | Aug 21 02:28:36 AM UTC 24 |
| Peak memory | 154596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1168621368 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_prince_test.1168621368 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/7.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/70.prim_prince_test.2520574672 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 2468974562 ps |
| CPU time | 42.13 seconds |
| Started | Aug 21 02:30:50 AM UTC 24 |
| Finished | Aug 21 02:31:45 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2520574672 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.prim_prince_test.2520574672 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/70.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/71.prim_prince_test.394016096 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 3457562381 ps |
| CPU time | 58.37 seconds |
| Started | Aug 21 02:30:52 AM UTC 24 |
| Finished | Aug 21 02:32:07 AM UTC 24 |
| Peak memory | 154660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=394016096 -assert nopostproc +UVM_TES TNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pr im_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.prim_prince_test.394016096 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/71.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/72.prim_prince_test.2672337519 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 2314414730 ps |
| CPU time | 39.55 seconds |
| Started | Aug 21 02:30:53 AM UTC 24 |
| Finished | Aug 21 02:31:44 AM UTC 24 |
| Peak memory | 154660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2672337519 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.prim_prince_test.2672337519 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/72.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/73.prim_prince_test.281329455 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 853562392 ps |
| CPU time | 15.07 seconds |
| Started | Aug 21 02:30:54 AM UTC 24 |
| Finished | Aug 21 02:31:13 AM UTC 24 |
| Peak memory | 154596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=281329455 -assert nopostproc +UVM_TES TNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pr im_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.prim_prince_test.281329455 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/73.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/74.prim_prince_test.507686635 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 1382839070 ps |
| CPU time | 23.96 seconds |
| Started | Aug 21 02:30:57 AM UTC 24 |
| Finished | Aug 21 02:31:28 AM UTC 24 |
| Peak memory | 154596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=507686635 -assert nopostproc +UVM_TES TNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pr im_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.prim_prince_test.507686635 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/74.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/75.prim_prince_test.3932525731 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 2895874833 ps |
| CPU time | 49.51 seconds |
| Started | Aug 21 02:31:01 AM UTC 24 |
| Finished | Aug 21 02:32:04 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3932525731 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.prim_prince_test.3932525731 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/75.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/76.prim_prince_test.3534479203 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 1420731643 ps |
| CPU time | 24.55 seconds |
| Started | Aug 21 02:31:01 AM UTC 24 |
| Finished | Aug 21 02:31:33 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3534479203 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.prim_prince_test.3534479203 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/76.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/77.prim_prince_test.4176392585 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 2370324341 ps |
| CPU time | 40.8 seconds |
| Started | Aug 21 02:31:06 AM UTC 24 |
| Finished | Aug 21 02:31:59 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4176392585 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.prim_prince_test.4176392585 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/77.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/78.prim_prince_test.2717459184 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 3091988110 ps |
| CPU time | 52.35 seconds |
| Started | Aug 21 02:31:07 AM UTC 24 |
| Finished | Aug 21 02:32:14 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2717459184 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.prim_prince_test.2717459184 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/78.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/79.prim_prince_test.762733163 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 1072053452 ps |
| CPU time | 18.61 seconds |
| Started | Aug 21 02:31:09 AM UTC 24 |
| Finished | Aug 21 02:31:33 AM UTC 24 |
| Peak memory | 154596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=762733163 -assert nopostproc +UVM_TES TNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pr im_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.prim_prince_test.762733163 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/79.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/8.prim_prince_test.3153059602 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 2881549057 ps |
| CPU time | 49.57 seconds |
| Started | Aug 21 02:27:55 AM UTC 24 |
| Finished | Aug 21 02:28:58 AM UTC 24 |
| Peak memory | 154660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3153059602 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_prince_test.3153059602 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/8.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/80.prim_prince_test.3146018034 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 2505389510 ps |
| CPU time | 42.35 seconds |
| Started | Aug 21 02:31:13 AM UTC 24 |
| Finished | Aug 21 02:32:07 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3146018034 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 80.prim_prince_test.3146018034 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/80.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/81.prim_prince_test.671176322 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 3031559336 ps |
| CPU time | 51.84 seconds |
| Started | Aug 21 02:31:14 AM UTC 24 |
| Finished | Aug 21 02:32:20 AM UTC 24 |
| Peak memory | 154660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=671176322 -assert nopostproc +UVM_TES TNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pr im_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 81.prim_prince_test.671176322 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/81.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/82.prim_prince_test.3965416704 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 3615169612 ps |
| CPU time | 61.24 seconds |
| Started | Aug 21 02:31:22 AM UTC 24 |
| Finished | Aug 21 02:32:41 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3965416704 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 82.prim_prince_test.3965416704 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/82.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/83.prim_prince_test.2455704661 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 1632341134 ps |
| CPU time | 28.1 seconds |
| Started | Aug 21 02:31:26 AM UTC 24 |
| Finished | Aug 21 02:32:03 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2455704661 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 83.prim_prince_test.2455704661 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/83.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/84.prim_prince_test.3251002849 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 1470259732 ps |
| CPU time | 25.2 seconds |
| Started | Aug 21 02:31:27 AM UTC 24 |
| Finished | Aug 21 02:32:00 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3251002849 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 84.prim_prince_test.3251002849 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/84.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/85.prim_prince_test.2101296603 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 1387449890 ps |
| CPU time | 23.99 seconds |
| Started | Aug 21 02:31:28 AM UTC 24 |
| Finished | Aug 21 02:32:00 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2101296603 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 85.prim_prince_test.2101296603 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/85.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/86.prim_prince_test.3876936197 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 1572852600 ps |
| CPU time | 27.18 seconds |
| Started | Aug 21 02:31:33 AM UTC 24 |
| Finished | Aug 21 02:32:08 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3876936197 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 86.prim_prince_test.3876936197 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/86.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/87.prim_prince_test.282349962 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 3155293873 ps |
| CPU time | 53.37 seconds |
| Started | Aug 21 02:31:34 AM UTC 24 |
| Finished | Aug 21 02:32:43 AM UTC 24 |
| Peak memory | 154660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=282349962 -assert nopostproc +UVM_TES TNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pr im_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 87.prim_prince_test.282349962 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/87.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/88.prim_prince_test.4224542239 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 2584110125 ps |
| CPU time | 44.39 seconds |
| Started | Aug 21 02:31:45 AM UTC 24 |
| Finished | Aug 21 02:32:42 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4224542239 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 88.prim_prince_test.4224542239 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/88.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/89.prim_prince_test.49731978 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 3068105755 ps |
| CPU time | 52.67 seconds |
| Started | Aug 21 02:31:46 AM UTC 24 |
| Finished | Aug 21 02:32:53 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=49731978 -assert nopostproc +UVM_TEST NAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pri m_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 89.prim_prince_test.49731978 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/89.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/9.prim_prince_test.3336862375 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 1838216657 ps |
| CPU time | 32 seconds |
| Started | Aug 21 02:27:55 AM UTC 24 |
| Finished | Aug 21 02:28:36 AM UTC 24 |
| Peak memory | 154596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3336862375 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_prince_test.3336862375 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/9.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/90.prim_prince_test.1794079002 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 1738988456 ps |
| CPU time | 29.61 seconds |
| Started | Aug 21 02:31:58 AM UTC 24 |
| Finished | Aug 21 02:32:36 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1794079002 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 90.prim_prince_test.1794079002 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/90.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/91.prim_prince_test.1222690671 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 2270296891 ps |
| CPU time | 38.45 seconds |
| Started | Aug 21 02:31:59 AM UTC 24 |
| Finished | Aug 21 02:32:48 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1222690671 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 91.prim_prince_test.1222690671 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/91.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/92.prim_prince_test.3154569557 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 3477522916 ps |
| CPU time | 58.79 seconds |
| Started | Aug 21 02:32:00 AM UTC 24 |
| Finished | Aug 21 02:33:15 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3154569557 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 92.prim_prince_test.3154569557 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/92.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/93.prim_prince_test.2936807757 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 2145653442 ps |
| CPU time | 36.58 seconds |
| Started | Aug 21 02:32:01 AM UTC 24 |
| Finished | Aug 21 02:32:48 AM UTC 24 |
| Peak memory | 153912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2936807757 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 93.prim_prince_test.2936807757 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/93.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/94.prim_prince_test.2253250123 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 2685009728 ps |
| CPU time | 46.07 seconds |
| Started | Aug 21 02:32:01 AM UTC 24 |
| Finished | Aug 21 02:33:00 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2253250123 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 94.prim_prince_test.2253250123 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/94.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/95.prim_prince_test.419771945 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 3263722219 ps |
| CPU time | 55.12 seconds |
| Started | Aug 21 02:32:01 AM UTC 24 |
| Finished | Aug 21 02:33:11 AM UTC 24 |
| Peak memory | 154660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=419771945 -assert nopostproc +UVM_TES TNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pr im_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 95.prim_prince_test.419771945 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/95.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/96.prim_prince_test.1728291825 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 2571838599 ps |
| CPU time | 43.76 seconds |
| Started | Aug 21 02:32:03 AM UTC 24 |
| Finished | Aug 21 02:32:59 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1728291825 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 96.prim_prince_test.1728291825 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/96.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/97.prim_prince_test.2304804834 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 2631285476 ps |
| CPU time | 44.6 seconds |
| Started | Aug 21 02:32:04 AM UTC 24 |
| Finished | Aug 21 02:33:01 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2304804834 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 97.prim_prince_test.2304804834 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/97.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/98.prim_prince_test.3868574472 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 2793251853 ps |
| CPU time | 47.83 seconds |
| Started | Aug 21 02:32:05 AM UTC 24 |
| Finished | Aug 21 02:33:06 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3868574472 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 98.prim_prince_test.3868574472 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/98.prim_prince_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/coverage/default/99.prim_prince_test.3739644127 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 2705894569 ps |
| CPU time | 46.58 seconds |
| Started | Aug 21 02:32:08 AM UTC 24 |
| Finished | Aug 21 02:33:08 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3739644127 -assert nopostproc +UVM_TE STNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/p rim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 99.prim_prince_test.3739644127 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/prim_prince-sim-vcs/99.prim_prince_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |