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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00 100.00


Total test records in report: 500
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html
T251 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/237.prim_prince_test.436656816 Aug 23 08:09:55 AM UTC 24 Aug 23 08:10:57 AM UTC 24 3349152777 ps
T252 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/265.prim_prince_test.184908599 Aug 23 08:10:40 AM UTC 24 Aug 23 08:10:57 AM UTC 24 909099928 ps
T253 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/266.prim_prince_test.1430496302 Aug 23 08:10:40 AM UTC 24 Aug 23 08:11:00 AM UTC 24 1033359874 ps
T254 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/251.prim_prince_test.315481608 Aug 23 08:10:20 AM UTC 24 Aug 23 08:11:02 AM UTC 24 2247354831 ps
T255 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/250.prim_prince_test.3482671392 Aug 23 08:10:15 AM UTC 24 Aug 23 08:11:03 AM UTC 24 2565021451 ps
T256 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/270.prim_prince_test.1441647647 Aug 23 08:10:43 AM UTC 24 Aug 23 08:11:05 AM UTC 24 1099835167 ps
T257 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/244.prim_prince_test.3284346746 Aug 23 08:10:07 AM UTC 24 Aug 23 08:11:06 AM UTC 24 3159932152 ps
T258 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/259.prim_prince_test.235126963 Aug 23 08:10:30 AM UTC 24 Aug 23 08:11:07 AM UTC 24 1941780067 ps
T259 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/241.prim_prince_test.161299323 Aug 23 08:10:00 AM UTC 24 Aug 23 08:11:09 AM UTC 24 3669900330 ps
T260 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/246.prim_prince_test.3353747756 Aug 23 08:10:10 AM UTC 24 Aug 23 08:11:10 AM UTC 24 3212234267 ps
T261 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/253.prim_prince_test.770914917 Aug 23 08:10:22 AM UTC 24 Aug 23 08:11:12 AM UTC 24 2663495825 ps
T262 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/273.prim_prince_test.3395237274 Aug 23 08:10:51 AM UTC 24 Aug 23 08:11:12 AM UTC 24 1111313887 ps
T263 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/254.prim_prince_test.3135437967 Aug 23 08:10:24 AM UTC 24 Aug 23 08:11:17 AM UTC 24 2848781945 ps
T264 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/248.prim_prince_test.776766405 Aug 23 08:10:12 AM UTC 24 Aug 23 08:11:19 AM UTC 24 3636579514 ps
T265 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/279.prim_prince_test.1596816840 Aug 23 08:11:01 AM UTC 24 Aug 23 08:11:19 AM UTC 24 945102531 ps
T266 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/278.prim_prince_test.518962577 Aug 23 08:10:58 AM UTC 24 Aug 23 08:11:21 AM UTC 24 1175334308 ps
T267 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/333.prim_prince_test.92031558 Aug 23 08:12:22 AM UTC 24 Aug 23 08:13:15 AM UTC 24 2820508217 ps
T268 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/263.prim_prince_test.3875797080 Aug 23 08:10:35 AM UTC 24 Aug 23 08:11:23 AM UTC 24 2541599417 ps
T269 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/258.prim_prince_test.1007013006 Aug 23 08:10:29 AM UTC 24 Aug 23 08:11:23 AM UTC 24 2918281160 ps
T270 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/280.prim_prince_test.690534153 Aug 23 08:11:03 AM UTC 24 Aug 23 08:11:25 AM UTC 24 1064737421 ps
T271 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/271.prim_prince_test.978369561 Aug 23 08:10:48 AM UTC 24 Aug 23 08:11:28 AM UTC 24 2111543380 ps
T272 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/284.prim_prince_test.3136713850 Aug 23 08:11:08 AM UTC 24 Aug 23 08:11:28 AM UTC 24 1084899160 ps
T273 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/264.prim_prince_test.3837621158 Aug 23 08:10:38 AM UTC 24 Aug 23 08:11:29 AM UTC 24 2695908036 ps
T274 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/282.prim_prince_test.112034567 Aug 23 08:11:05 AM UTC 24 Aug 23 08:11:29 AM UTC 24 1248960837 ps
T275 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/269.prim_prince_test.216069484 Aug 23 08:10:41 AM UTC 24 Aug 23 08:11:35 AM UTC 24 2912308760 ps
T276 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/277.prim_prince_test.1192951219 Aug 23 08:10:58 AM UTC 24 Aug 23 08:11:36 AM UTC 24 2010782312 ps
T277 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/288.prim_prince_test.693162447 Aug 23 08:11:13 AM UTC 24 Aug 23 08:11:36 AM UTC 24 1187155444 ps
T278 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/274.prim_prince_test.3290451009 Aug 23 08:10:56 AM UTC 24 Aug 23 08:11:38 AM UTC 24 2250353036 ps
T279 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/262.prim_prince_test.138675666 Aug 23 08:10:35 AM UTC 24 Aug 23 08:11:38 AM UTC 24 3353311049 ps
T280 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/260.prim_prince_test.909830957 Aug 23 08:10:31 AM UTC 24 Aug 23 08:11:40 AM UTC 24 3685314714 ps
T281 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/293.prim_prince_test.2470132028 Aug 23 08:11:24 AM UTC 24 Aug 23 08:11:43 AM UTC 24 954533346 ps
T282 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/276.prim_prince_test.1999113615 Aug 23 08:10:56 AM UTC 24 Aug 23 08:11:46 AM UTC 24 2673409711 ps
T283 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/285.prim_prince_test.3934424109 Aug 23 08:11:10 AM UTC 24 Aug 23 08:11:46 AM UTC 24 1910502374 ps
T284 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/267.prim_prince_test.432594031 Aug 23 08:10:40 AM UTC 24 Aug 23 08:11:47 AM UTC 24 3611743230 ps
T285 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/298.prim_prince_test.1303574966 Aug 23 08:11:30 AM UTC 24 Aug 23 08:11:48 AM UTC 24 922192865 ps
T286 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/283.prim_prince_test.2229314870 Aug 23 08:11:07 AM UTC 24 Aug 23 08:11:48 AM UTC 24 2217065390 ps
T287 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/268.prim_prince_test.2247780725 Aug 23 08:10:41 AM UTC 24 Aug 23 08:11:50 AM UTC 24 3682709387 ps
T288 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/272.prim_prince_test.3333812144 Aug 23 08:10:48 AM UTC 24 Aug 23 08:11:51 AM UTC 24 3378488239 ps
T289 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/290.prim_prince_test.4148611710 Aug 23 08:11:19 AM UTC 24 Aug 23 08:11:54 AM UTC 24 1857558561 ps
T290 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/286.prim_prince_test.3084219932 Aug 23 08:11:11 AM UTC 24 Aug 23 08:11:55 AM UTC 24 2342292275 ps
T291 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/287.prim_prince_test.1080814035 Aug 23 08:11:13 AM UTC 24 Aug 23 08:11:55 AM UTC 24 2258426326 ps
T292 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/302.prim_prince_test.4283421723 Aug 23 08:11:36 AM UTC 24 Aug 23 08:11:56 AM UTC 24 1011905101 ps
T293 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/275.prim_prince_test.1365384611 Aug 23 08:10:56 AM UTC 24 Aug 23 08:11:58 AM UTC 24 3343962707 ps
T294 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/306.prim_prince_test.937555783 Aug 23 08:11:44 AM UTC 24 Aug 23 08:12:00 AM UTC 24 804222894 ps
T295 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/295.prim_prince_test.1893876276 Aug 23 08:11:26 AM UTC 24 Aug 23 08:12:02 AM UTC 24 1907475575 ps
T296 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/305.prim_prince_test.1427224904 Aug 23 08:11:41 AM UTC 24 Aug 23 08:12:06 AM UTC 24 1303536899 ps
T297 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/304.prim_prince_test.906726228 Aug 23 08:11:39 AM UTC 24 Aug 23 08:12:06 AM UTC 24 1456452586 ps
T298 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/297.prim_prince_test.2754127964 Aug 23 08:11:29 AM UTC 24 Aug 23 08:12:12 AM UTC 24 2314617715 ps
T299 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/281.prim_prince_test.2898382943 Aug 23 08:11:04 AM UTC 24 Aug 23 08:12:13 AM UTC 24 3720473634 ps
T300 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/291.prim_prince_test.3741517808 Aug 23 08:11:20 AM UTC 24 Aug 23 08:12:14 AM UTC 24 2856321928 ps
T301 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/309.prim_prince_test.3162750469 Aug 23 08:11:47 AM UTC 24 Aug 23 08:12:15 AM UTC 24 1442515484 ps
T302 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/299.prim_prince_test.3092769041 Aug 23 08:11:30 AM UTC 24 Aug 23 08:12:16 AM UTC 24 2422938906 ps
T303 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/311.prim_prince_test.3433160122 Aug 23 08:11:49 AM UTC 24 Aug 23 08:12:16 AM UTC 24 1413675521 ps
T304 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/314.prim_prince_test.909368477 Aug 23 08:11:55 AM UTC 24 Aug 23 08:12:17 AM UTC 24 1157664005 ps
T305 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/303.prim_prince_test.4167329544 Aug 23 08:11:39 AM UTC 24 Aug 23 08:12:18 AM UTC 24 2126533623 ps
T306 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/300.prim_prince_test.4221752261 Aug 23 08:11:36 AM UTC 24 Aug 23 08:12:18 AM UTC 24 2203632019 ps
T307 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/316.prim_prince_test.601138668 Aug 23 08:11:56 AM UTC 24 Aug 23 08:12:20 AM UTC 24 1214193860 ps
T308 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/289.prim_prince_test.1641616806 Aug 23 08:11:18 AM UTC 24 Aug 23 08:12:21 AM UTC 24 3428465606 ps
T309 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/310.prim_prince_test.2288170749 Aug 23 08:11:49 AM UTC 24 Aug 23 08:12:24 AM UTC 24 1794498730 ps
T310 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/313.prim_prince_test.1417777083 Aug 23 08:11:52 AM UTC 24 Aug 23 08:12:24 AM UTC 24 1697735962 ps
T311 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/292.prim_prince_test.3521106018 Aug 23 08:11:21 AM UTC 24 Aug 23 08:12:31 AM UTC 24 3702169933 ps
T312 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/308.prim_prince_test.4061677372 Aug 23 08:11:47 AM UTC 24 Aug 23 08:12:31 AM UTC 24 2362458756 ps
T313 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/294.prim_prince_test.2102256149 Aug 23 08:11:24 AM UTC 24 Aug 23 08:12:32 AM UTC 24 3657688498 ps
T314 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/296.prim_prince_test.1797722668 Aug 23 08:11:29 AM UTC 24 Aug 23 08:12:35 AM UTC 24 3548438881 ps
T315 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/326.prim_prince_test.3473688001 Aug 23 08:12:15 AM UTC 24 Aug 23 08:12:36 AM UTC 24 1096947335 ps
T316 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/331.prim_prince_test.1163188678 Aug 23 08:12:20 AM UTC 24 Aug 23 08:12:40 AM UTC 24 1030714496 ps
T317 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/325.prim_prince_test.191311817 Aug 23 08:12:14 AM UTC 24 Aug 23 08:12:41 AM UTC 24 1410541638 ps
T318 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/301.prim_prince_test.2306228809 Aug 23 08:11:36 AM UTC 24 Aug 23 08:12:45 AM UTC 24 3744509706 ps
T319 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/315.prim_prince_test.1307246097 Aug 23 08:11:56 AM UTC 24 Aug 23 08:12:45 AM UTC 24 2578233964 ps
T320 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/317.prim_prince_test.101172493 Aug 23 08:11:57 AM UTC 24 Aug 23 08:12:47 AM UTC 24 2643658224 ps
T321 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/322.prim_prince_test.2536200297 Aug 23 08:12:08 AM UTC 24 Aug 23 08:12:47 AM UTC 24 2104833387 ps
T322 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/318.prim_prince_test.2804149182 Aug 23 08:11:59 AM UTC 24 Aug 23 08:12:49 AM UTC 24 2701577833 ps
T323 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/307.prim_prince_test.81473411 Aug 23 08:11:47 AM UTC 24 Aug 23 08:12:50 AM UTC 24 3370790604 ps
T324 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/324.prim_prince_test.2660686620 Aug 23 08:12:14 AM UTC 24 Aug 23 08:12:50 AM UTC 24 1901256867 ps
T325 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/339.prim_prince_test.2542758017 Aug 23 08:12:36 AM UTC 24 Aug 23 08:12:51 AM UTC 24 770125443 ps
T326 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/328.prim_prince_test.662833495 Aug 23 08:12:17 AM UTC 24 Aug 23 08:12:51 AM UTC 24 1802760733 ps
T327 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/312.prim_prince_test.1058151844 Aug 23 08:11:51 AM UTC 24 Aug 23 08:12:52 AM UTC 24 3302610233 ps
T328 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/320.prim_prince_test.1212649932 Aug 23 08:12:02 AM UTC 24 Aug 23 08:12:52 AM UTC 24 2608978560 ps
T329 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/338.prim_prince_test.4057183404 Aug 23 08:12:33 AM UTC 24 Aug 23 08:12:58 AM UTC 24 1335183834 ps
T330 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/329.prim_prince_test.3713380242 Aug 23 08:12:17 AM UTC 24 Aug 23 08:12:59 AM UTC 24 2198619150 ps
T331 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/319.prim_prince_test.3597666259 Aug 23 08:12:00 AM UTC 24 Aug 23 08:13:02 AM UTC 24 3321965523 ps
T332 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/330.prim_prince_test.3615685050 Aug 23 08:12:19 AM UTC 24 Aug 23 08:13:08 AM UTC 24 2591713896 ps
T333 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/348.prim_prince_test.661243238 Aug 23 08:12:51 AM UTC 24 Aug 23 08:13:08 AM UTC 24 862097177 ps
T334 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/327.prim_prince_test.402298964 Aug 23 08:12:17 AM UTC 24 Aug 23 08:13:11 AM UTC 24 2851889593 ps
T335 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/335.prim_prince_test.2867325382 Aug 23 08:12:25 AM UTC 24 Aug 23 08:13:12 AM UTC 24 2440787014 ps
T336 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/350.prim_prince_test.2793883542 Aug 23 08:12:52 AM UTC 24 Aug 23 08:13:14 AM UTC 24 1125159273 ps
T337 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/334.prim_prince_test.1951105836 Aug 23 08:12:24 AM UTC 24 Aug 23 08:13:15 AM UTC 24 2716136536 ps
T338 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/342.prim_prince_test.1806300505 Aug 23 08:12:42 AM UTC 24 Aug 23 08:13:16 AM UTC 24 1724866480 ps
T339 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/321.prim_prince_test.3085766183 Aug 23 08:12:07 AM UTC 24 Aug 23 08:13:17 AM UTC 24 3744586358 ps
T340 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/323.prim_prince_test.1883616763 Aug 23 08:12:13 AM UTC 24 Aug 23 08:13:18 AM UTC 24 3501201649 ps
T341 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/345.prim_prince_test.1197161670 Aug 23 08:12:49 AM UTC 24 Aug 23 08:13:19 AM UTC 24 1556366854 ps
T342 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/355.prim_prince_test.663478469 Aug 23 08:13:00 AM UTC 24 Aug 23 08:13:19 AM UTC 24 969491086 ps
T343 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/352.prim_prince_test.779609171 Aug 23 08:12:52 AM UTC 24 Aug 23 08:13:21 AM UTC 24 1443708487 ps
T344 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/347.prim_prince_test.1822026510 Aug 23 08:12:50 AM UTC 24 Aug 23 08:13:22 AM UTC 24 1641355156 ps
T345 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/340.prim_prince_test.535140575 Aug 23 08:12:37 AM UTC 24 Aug 23 08:13:23 AM UTC 24 2340810867 ps
T346 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/344.prim_prince_test.2783811735 Aug 23 08:12:46 AM UTC 24 Aug 23 08:13:24 AM UTC 24 1932937882 ps
T347 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/349.prim_prince_test.1445038236 Aug 23 08:12:51 AM UTC 24 Aug 23 08:13:24 AM UTC 24 1728898494 ps
T348 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/332.prim_prince_test.1139163515 Aug 23 08:12:21 AM UTC 24 Aug 23 08:13:28 AM UTC 24 3570645829 ps
T349 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/343.prim_prince_test.174207354 Aug 23 08:12:45 AM UTC 24 Aug 23 08:13:30 AM UTC 24 2400463797 ps
T350 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/361.prim_prince_test.2806564827 Aug 23 08:13:15 AM UTC 24 Aug 23 08:13:31 AM UTC 24 866413199 ps
T351 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/336.prim_prince_test.2917525682 Aug 23 08:12:31 AM UTC 24 Aug 23 08:13:33 AM UTC 24 3238684654 ps
T352 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/337.prim_prince_test.2422843014 Aug 23 08:12:31 AM UTC 24 Aug 23 08:13:36 AM UTC 24 3480917565 ps
T353 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/366.prim_prince_test.3362781641 Aug 23 08:13:19 AM UTC 24 Aug 23 08:13:36 AM UTC 24 884548140 ps
T354 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/356.prim_prince_test.2796071305 Aug 23 08:13:03 AM UTC 24 Aug 23 08:13:37 AM UTC 24 1814793211 ps
T355 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/359.prim_prince_test.3294168803 Aug 23 08:13:11 AM UTC 24 Aug 23 08:13:39 AM UTC 24 1428126128 ps
T356 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/357.prim_prince_test.1812221223 Aug 23 08:13:09 AM UTC 24 Aug 23 08:13:41 AM UTC 24 1636780200 ps
T357 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/373.prim_prince_test.2034061170 Aug 23 08:13:25 AM UTC 24 Aug 23 08:13:43 AM UTC 24 894623940 ps
T358 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/346.prim_prince_test.3327665238 Aug 23 08:12:49 AM UTC 24 Aug 23 08:13:46 AM UTC 24 3043974019 ps
T359 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/353.prim_prince_test.186991769 Aug 23 08:12:53 AM UTC 24 Aug 23 08:13:46 AM UTC 24 2794018827 ps
T360 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/372.prim_prince_test.241456864 Aug 23 08:13:25 AM UTC 24 Aug 23 08:13:46 AM UTC 24 1103001427 ps
T361 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/341.prim_prince_test.341991048 Aug 23 08:12:41 AM UTC 24 Aug 23 08:13:48 AM UTC 24 3614353192 ps
T362 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/351.prim_prince_test.996337545 Aug 23 08:12:52 AM UTC 24 Aug 23 08:13:49 AM UTC 24 3025418037 ps
T363 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/365.prim_prince_test.4269628408 Aug 23 08:13:18 AM UTC 24 Aug 23 08:13:49 AM UTC 24 1622308675 ps
T364 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/360.prim_prince_test.3135169900 Aug 23 08:13:13 AM UTC 24 Aug 23 08:13:52 AM UTC 24 2070630269 ps
T365 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/369.prim_prince_test.3581443707 Aug 23 08:13:22 AM UTC 24 Aug 23 08:13:56 AM UTC 24 1851376482 ps
T366 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/370.prim_prince_test.1846786075 Aug 23 08:13:23 AM UTC 24 Aug 23 08:14:05 AM UTC 24 2245703771 ps
T367 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/405.prim_prince_test.1314171835 Aug 23 08:14:16 AM UTC 24 Aug 23 08:15:25 AM UTC 24 3641258776 ps
T368 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/385.prim_prince_test.1451216808 Aug 23 08:13:47 AM UTC 24 Aug 23 08:14:05 AM UTC 24 948617543 ps
T369 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/368.prim_prince_test.171854498 Aug 23 08:13:19 AM UTC 24 Aug 23 08:14:05 AM UTC 24 2440391728 ps
T370 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/374.prim_prince_test.148573081 Aug 23 08:13:28 AM UTC 24 Aug 23 08:14:06 AM UTC 24 2031551467 ps
T371 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/354.prim_prince_test.99697450 Aug 23 08:13:00 AM UTC 24 Aug 23 08:14:06 AM UTC 24 3578468295 ps
T372 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/386.prim_prince_test.3163938949 Aug 23 08:13:48 AM UTC 24 Aug 23 08:14:06 AM UTC 24 928187138 ps
T373 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/358.prim_prince_test.2061001204 Aug 23 08:13:09 AM UTC 24 Aug 23 08:14:07 AM UTC 24 3142545256 ps
T374 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/377.prim_prince_test.2568554639 Aug 23 08:13:34 AM UTC 24 Aug 23 08:14:08 AM UTC 24 1806123461 ps
T375 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/364.prim_prince_test.2808652782 Aug 23 08:13:17 AM UTC 24 Aug 23 08:14:10 AM UTC 24 2853810565 ps
T376 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/363.prim_prince_test.1538722616 Aug 23 08:13:16 AM UTC 24 Aug 23 08:14:10 AM UTC 24 2914330787 ps
T377 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/375.prim_prince_test.2583423838 Aug 23 08:13:31 AM UTC 24 Aug 23 08:14:11 AM UTC 24 2114052816 ps
T378 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/376.prim_prince_test.2047184394 Aug 23 08:13:32 AM UTC 24 Aug 23 08:14:14 AM UTC 24 2245875257 ps
T379 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/382.prim_prince_test.1131109205 Aug 23 08:13:42 AM UTC 24 Aug 23 08:14:15 AM UTC 24 1752115142 ps
T380 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/388.prim_prince_test.2304808536 Aug 23 08:13:50 AM UTC 24 Aug 23 08:14:16 AM UTC 24 1331898270 ps
T381 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/362.prim_prince_test.97698047 Aug 23 08:13:16 AM UTC 24 Aug 23 08:14:17 AM UTC 24 3325984963 ps
T382 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/379.prim_prince_test.3755620909 Aug 23 08:13:37 AM UTC 24 Aug 23 08:14:18 AM UTC 24 2138699089 ps
T383 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/378.prim_prince_test.1822479905 Aug 23 08:13:37 AM UTC 24 Aug 23 08:14:18 AM UTC 24 2183791558 ps
T384 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/371.prim_prince_test.3900342567 Aug 23 08:13:24 AM UTC 24 Aug 23 08:14:23 AM UTC 24 3194674437 ps
T385 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/381.prim_prince_test.3427478901 Aug 23 08:13:39 AM UTC 24 Aug 23 08:14:23 AM UTC 24 2326944468 ps
T386 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/367.prim_prince_test.3120473380 Aug 23 08:13:19 AM UTC 24 Aug 23 08:14:26 AM UTC 24 3528317575 ps
T387 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/391.prim_prince_test.1993525797 Aug 23 08:13:56 AM UTC 24 Aug 23 08:14:31 AM UTC 24 1823450414 ps
T388 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/380.prim_prince_test.472536475 Aug 23 08:13:38 AM UTC 24 Aug 23 08:14:31 AM UTC 24 2811110077 ps
T389 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/387.prim_prince_test.4246290677 Aug 23 08:13:49 AM UTC 24 Aug 23 08:14:32 AM UTC 24 2253525099 ps
T390 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/401.prim_prince_test.1713130426 Aug 23 08:14:11 AM UTC 24 Aug 23 08:14:38 AM UTC 24 1431694899 ps
T391 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/407.prim_prince_test.1930356675 Aug 23 08:14:19 AM UTC 24 Aug 23 08:14:43 AM UTC 24 1255994871 ps
T392 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/402.prim_prince_test.2999873124 Aug 23 08:14:11 AM UTC 24 Aug 23 08:14:45 AM UTC 24 1813222898 ps
T393 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/393.prim_prince_test.975434330 Aug 23 08:14:06 AM UTC 24 Aug 23 08:14:45 AM UTC 24 2066506070 ps
T394 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/398.prim_prince_test.599837488 Aug 23 08:14:07 AM UTC 24 Aug 23 08:14:46 AM UTC 24 2025733810 ps
T395 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/399.prim_prince_test.3759505815 Aug 23 08:14:09 AM UTC 24 Aug 23 08:14:49 AM UTC 24 2133910530 ps
T396 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/384.prim_prince_test.3800427478 Aug 23 08:13:47 AM UTC 24 Aug 23 08:14:50 AM UTC 24 3438383730 ps
T397 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/383.prim_prince_test.2829899289 Aug 23 08:13:43 AM UTC 24 Aug 23 08:14:50 AM UTC 24 3619078515 ps
T398 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/390.prim_prince_test.417599803 Aug 23 08:13:53 AM UTC 24 Aug 23 08:14:52 AM UTC 24 3127648406 ps
T399 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/403.prim_prince_test.2500145604 Aug 23 08:14:12 AM UTC 24 Aug 23 08:14:56 AM UTC 24 2319716265 ps
T400 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/415.prim_prince_test.3392354792 Aug 23 08:14:33 AM UTC 24 Aug 23 08:14:57 AM UTC 24 1229907239 ps
T401 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/389.prim_prince_test.1588937286 Aug 23 08:13:50 AM UTC 24 Aug 23 08:14:57 AM UTC 24 3563946257 ps
T402 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/408.prim_prince_test.1036217454 Aug 23 08:14:19 AM UTC 24 Aug 23 08:14:58 AM UTC 24 2037978756 ps
T403 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/395.prim_prince_test.1116622916 Aug 23 08:14:06 AM UTC 24 Aug 23 08:14:59 AM UTC 24 2854649477 ps
T404 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/392.prim_prince_test.589858588 Aug 23 08:14:04 AM UTC 24 Aug 23 08:15:00 AM UTC 24 3001434471 ps
T405 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/397.prim_prince_test.2664507009 Aug 23 08:14:07 AM UTC 24 Aug 23 08:15:01 AM UTC 24 2847009054 ps
T406 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/411.prim_prince_test.113732312 Aug 23 08:14:24 AM UTC 24 Aug 23 08:15:02 AM UTC 24 2001214219 ps
T407 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/394.prim_prince_test.276703593 Aug 23 08:14:06 AM UTC 24 Aug 23 08:15:03 AM UTC 24 3027190860 ps
T408 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/410.prim_prince_test.1246327264 Aug 23 08:14:24 AM UTC 24 Aug 23 08:15:03 AM UTC 24 2097850803 ps
T409 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/417.prim_prince_test.3517859266 Aug 23 08:14:44 AM UTC 24 Aug 23 08:15:04 AM UTC 24 1024181639 ps
T410 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/413.prim_prince_test.329277785 Aug 23 08:14:32 AM UTC 24 Aug 23 08:15:05 AM UTC 24 1721441198 ps
T411 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/396.prim_prince_test.2545812860 Aug 23 08:14:07 AM UTC 24 Aug 23 08:15:08 AM UTC 24 3231898816 ps
T412 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/400.prim_prince_test.1575247246 Aug 23 08:14:09 AM UTC 24 Aug 23 08:15:08 AM UTC 24 3197098966 ps
T413 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/404.prim_prince_test.2134013189 Aug 23 08:14:15 AM UTC 24 Aug 23 08:15:11 AM UTC 24 2957926479 ps
T414 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/414.prim_prince_test.4163401358 Aug 23 08:14:32 AM UTC 24 Aug 23 08:15:15 AM UTC 24 2300397013 ps
T415 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/406.prim_prince_test.262322691 Aug 23 08:14:17 AM UTC 24 Aug 23 08:15:19 AM UTC 24 3363733950 ps
T416 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/424.prim_prince_test.1659572496 Aug 23 08:14:53 AM UTC 24 Aug 23 08:15:21 AM UTC 24 1459114990 ps
T417 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/419.prim_prince_test.2569389388 Aug 23 08:14:46 AM UTC 24 Aug 23 08:15:22 AM UTC 24 1842361517 ps
T418 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/435.prim_prince_test.3968738691 Aug 23 08:15:05 AM UTC 24 Aug 23 08:15:23 AM UTC 24 945750994 ps
T419 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/412.prim_prince_test.1805805369 Aug 23 08:14:26 AM UTC 24 Aug 23 08:15:25 AM UTC 24 3152152542 ps
T420 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/409.prim_prince_test.2534505665 Aug 23 08:14:19 AM UTC 24 Aug 23 08:15:27 AM UTC 24 3639299304 ps
T421 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/420.prim_prince_test.454913844 Aug 23 08:14:47 AM UTC 24 Aug 23 08:15:27 AM UTC 24 2150324395 ps
T422 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/421.prim_prince_test.4294939168 Aug 23 08:14:50 AM UTC 24 Aug 23 08:15:31 AM UTC 24 2214785897 ps
T423 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/433.prim_prince_test.4153429007 Aug 23 08:15:03 AM UTC 24 Aug 23 08:15:31 AM UTC 24 1438634977 ps
T424 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/416.prim_prince_test.4069353849 Aug 23 08:14:39 AM UTC 24 Aug 23 08:15:31 AM UTC 24 2787933141 ps
T425 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/425.prim_prince_test.3411836614 Aug 23 08:14:57 AM UTC 24 Aug 23 08:15:33 AM UTC 24 1879093826 ps
T426 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/429.prim_prince_test.2112446843 Aug 23 08:15:00 AM UTC 24 Aug 23 08:15:35 AM UTC 24 1852399974 ps
T427 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/426.prim_prince_test.2871089270 Aug 23 08:14:57 AM UTC 24 Aug 23 08:15:36 AM UTC 24 2025781126 ps
T428 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/430.prim_prince_test.530009326 Aug 23 08:15:01 AM UTC 24 Aug 23 08:15:36 AM UTC 24 1858243322 ps
T429 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/444.prim_prince_test.146419511 Aug 23 08:15:24 AM UTC 24 Aug 23 08:15:40 AM UTC 24 779676703 ps
T430 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/437.prim_prince_test.1571921999 Aug 23 08:15:09 AM UTC 24 Aug 23 08:15:41 AM UTC 24 1643181189 ps
T431 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/423.prim_prince_test.2539084287 Aug 23 08:14:51 AM UTC 24 Aug 23 08:15:42 AM UTC 24 2746889194 ps
T432 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/428.prim_prince_test.2603051822 Aug 23 08:14:59 AM UTC 24 Aug 23 08:15:45 AM UTC 24 2442010958 ps
T433 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/445.prim_prince_test.2106051654 Aug 23 08:15:26 AM UTC 24 Aug 23 08:15:48 AM UTC 24 1098277551 ps
T434 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/431.prim_prince_test.2652124485 Aug 23 08:15:02 AM UTC 24 Aug 23 08:15:49 AM UTC 24 2469496147 ps
T435 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/418.prim_prince_test.1040417574 Aug 23 08:14:46 AM UTC 24 Aug 23 08:15:49 AM UTC 24 3391195199 ps
T436 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/422.prim_prince_test.1438827806 Aug 23 08:14:51 AM UTC 24 Aug 23 08:15:51 AM UTC 24 3196668841 ps
T437 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/434.prim_prince_test.4164841382 Aug 23 08:15:05 AM UTC 24 Aug 23 08:15:57 AM UTC 24 2790909731 ps
T438 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/427.prim_prince_test.1015227153 Aug 23 08:14:59 AM UTC 24 Aug 23 08:15:57 AM UTC 24 3130383925 ps
T439 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/438.prim_prince_test.34422517 Aug 23 08:15:09 AM UTC 24 Aug 23 08:15:59 AM UTC 24 2630123129 ps
T440 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/446.prim_prince_test.1019196228 Aug 23 08:15:26 AM UTC 24 Aug 23 08:16:01 AM UTC 24 1808775024 ps
T441 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/436.prim_prince_test.2937581285 Aug 23 08:15:06 AM UTC 24 Aug 23 08:16:02 AM UTC 24 3036666264 ps
T442 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/439.prim_prince_test.2788823366 Aug 23 08:15:12 AM UTC 24 Aug 23 08:16:05 AM UTC 24 2814131988 ps
T443 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/448.prim_prince_test.64362565 Aug 23 08:15:29 AM UTC 24 Aug 23 08:16:05 AM UTC 24 1913193388 ps
T444 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/432.prim_prince_test.3863935120 Aug 23 08:15:03 AM UTC 24 Aug 23 08:16:05 AM UTC 24 3277336624 ps
T445 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/450.prim_prince_test.4137454625 Aug 23 08:15:32 AM UTC 24 Aug 23 08:16:07 AM UTC 24 1793389856 ps
T446 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/442.prim_prince_test.2216338932 Aug 23 08:15:22 AM UTC 24 Aug 23 08:16:07 AM UTC 24 2366090023 ps
T447 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/457.prim_prince_test.393939912 Aug 23 08:15:42 AM UTC 24 Aug 23 08:16:07 AM UTC 24 1316707208 ps
T448 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/453.prim_prince_test.1851847930 Aug 23 08:15:36 AM UTC 24 Aug 23 08:16:09 AM UTC 24 1678959669 ps
T449 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/449.prim_prince_test.2743244221 Aug 23 08:15:32 AM UTC 24 Aug 23 08:16:12 AM UTC 24 2160563150 ps
T450 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/458.prim_prince_test.3425019021 Aug 23 08:15:43 AM UTC 24 Aug 23 08:16:13 AM UTC 24 1544821210 ps
T451 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/464.prim_prince_test.3574791496 Aug 23 08:15:58 AM UTC 24 Aug 23 08:16:14 AM UTC 24 760220782 ps
T452 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/440.prim_prince_test.4127287929 Aug 23 08:15:15 AM UTC 24 Aug 23 08:16:16 AM UTC 24 3254221010 ps
T453 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/455.prim_prince_test.1459844965 Aug 23 08:15:37 AM UTC 24 Aug 23 08:16:20 AM UTC 24 2270023306 ps
T454 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/467.prim_prince_test.3780355409 Aug 23 08:16:02 AM UTC 24 Aug 23 08:16:20 AM UTC 24 950328178 ps
T455 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/468.prim_prince_test.2038383651 Aug 23 08:16:04 AM UTC 24 Aug 23 08:16:24 AM UTC 24 1018969266 ps
T456 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/441.prim_prince_test.8293177 Aug 23 08:15:21 AM UTC 24 Aug 23 08:16:24 AM UTC 24 3379226541 ps
T457 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/470.prim_prince_test.3469690726 Aug 23 08:16:06 AM UTC 24 Aug 23 08:16:27 AM UTC 24 1043997363 ps
T458 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/465.prim_prince_test.1887241085 Aug 23 08:15:58 AM UTC 24 Aug 23 08:16:28 AM UTC 24 1524354569 ps
T459 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/447.prim_prince_test.2500514990 Aug 23 08:15:28 AM UTC 24 Aug 23 08:16:28 AM UTC 24 3162839884 ps
T460 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/451.prim_prince_test.4055434449 Aug 23 08:15:33 AM UTC 24 Aug 23 08:16:28 AM UTC 24 2947767572 ps
T461 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/443.prim_prince_test.3535524655 Aug 23 08:15:23 AM UTC 24 Aug 23 08:16:29 AM UTC 24 3534873532 ps
T462 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/452.prim_prince_test.604332061 Aug 23 08:15:34 AM UTC 24 Aug 23 08:16:32 AM UTC 24 3034439189 ps
T463 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/462.prim_prince_test.194754893 Aug 23 08:15:51 AM UTC 24 Aug 23 08:16:38 AM UTC 24 2497005554 ps
T464 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/472.prim_prince_test.1762848440 Aug 23 08:16:08 AM UTC 24 Aug 23 08:16:38 AM UTC 24 1589615937 ps
T465 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/469.prim_prince_test.4050331595 Aug 23 08:16:06 AM UTC 24 Aug 23 08:16:39 AM UTC 24 1728547415 ps
T466 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/461.prim_prince_test.570270101 Aug 23 08:15:50 AM UTC 24 Aug 23 08:16:44 AM UTC 24 2913081218 ps
T467 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/454.prim_prince_test.4199489631 Aug 23 08:15:36 AM UTC 24 Aug 23 08:16:45 AM UTC 24 3724589190 ps
T468 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/456.prim_prince_test.1559149825 Aug 23 08:15:41 AM UTC 24 Aug 23 08:16:45 AM UTC 24 3434450071 ps
T469 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/463.prim_prince_test.160242160 Aug 23 08:15:52 AM UTC 24 Aug 23 08:16:48 AM UTC 24 2966718050 ps
T470 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/485.prim_prince_test.999350822 Aug 23 08:16:28 AM UTC 24 Aug 23 08:16:51 AM UTC 24 1121536900 ps
T471 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/460.prim_prince_test.650282779 Aug 23 08:15:48 AM UTC 24 Aug 23 08:16:51 AM UTC 24 3347162664 ps
T472 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/459.prim_prince_test.3601015120 Aug 23 08:15:45 AM UTC 24 Aug 23 08:16:53 AM UTC 24 3659297170 ps
T473 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/488.prim_prince_test.2665867891 Aug 23 08:16:30 AM UTC 24 Aug 23 08:16:55 AM UTC 24 1300657731 ps
T474 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/492.prim_prince_test.3707458875 Aug 23 08:16:39 AM UTC 24 Aug 23 08:16:55 AM UTC 24 760788024 ps
T475 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/479.prim_prince_test.2634551927 Aug 23 08:16:16 AM UTC 24 Aug 23 08:16:55 AM UTC 24 2015189080 ps
T476 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/474.prim_prince_test.4172212625 Aug 23 08:16:08 AM UTC 24 Aug 23 08:16:57 AM UTC 24 2648907674 ps
T477 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/473.prim_prince_test.956399876 Aug 23 08:16:08 AM UTC 24 Aug 23 08:16:58 AM UTC 24 2617810601 ps
T478 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/483.prim_prince_test.3734146872 Aug 23 08:16:25 AM UTC 24 Aug 23 08:16:59 AM UTC 24 1758676049 ps
T479 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/481.prim_prince_test.4025664031 Aug 23 08:16:22 AM UTC 24 Aug 23 08:17:01 AM UTC 24 2040481902 ps
T480 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/475.prim_prince_test.3047121362 Aug 23 08:16:10 AM UTC 24 Aug 23 08:17:03 AM UTC 24 2810546835 ps
T481 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/476.prim_prince_test.3550924016 Aug 23 08:16:13 AM UTC 24 Aug 23 08:17:03 AM UTC 24 2627412873 ps
T482 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/466.prim_prince_test.2564041207 Aug 23 08:16:00 AM UTC 24 Aug 23 08:17:08 AM UTC 24 3598881626 ps
T483 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/487.prim_prince_test.487349946 Aug 23 08:16:30 AM UTC 24 Aug 23 08:17:11 AM UTC 24 2163794928 ps
T484 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/471.prim_prince_test.448514835 Aug 23 08:16:06 AM UTC 24 Aug 23 08:17:11 AM UTC 24 3443231400 ps
T485 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/490.prim_prince_test.4279523876 Aug 23 08:16:39 AM UTC 24 Aug 23 08:17:12 AM UTC 24 1708495865 ps
T486 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/482.prim_prince_test.3716874273 Aug 23 08:16:25 AM UTC 24 Aug 23 08:17:15 AM UTC 24 2639860727 ps
T487 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/491.prim_prince_test.3764497882 Aug 23 08:16:39 AM UTC 24 Aug 23 08:17:15 AM UTC 24 1860728527 ps
T488 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/493.prim_prince_test.2732392656 Aug 23 08:16:45 AM UTC 24 Aug 23 08:17:16 AM UTC 24 1651653217 ps
T489 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/480.prim_prince_test.4067890094 Aug 23 08:16:21 AM UTC 24 Aug 23 08:17:19 AM UTC 24 3089447278 ps
T490 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/496.prim_prince_test.384563322 Aug 23 08:16:48 AM UTC 24 Aug 23 08:17:20 AM UTC 24 1716115249 ps
T491 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/477.prim_prince_test.2502944235 Aug 23 08:16:13 AM UTC 24 Aug 23 08:17:21 AM UTC 24 3631860956 ps
T492 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/489.prim_prince_test.2672061138 Aug 23 08:16:33 AM UTC 24 Aug 23 08:17:21 AM UTC 24 2545260870 ps
T493 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/484.prim_prince_test.1568723034 Aug 23 08:16:27 AM UTC 24 Aug 23 08:17:22 AM UTC 24 2907048275 ps
T494 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/478.prim_prince_test.3252339308 Aug 23 08:16:14 AM UTC 24 Aug 23 08:17:22 AM UTC 24 3622279412 ps
T495 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/495.prim_prince_test.2891330344 Aug 23 08:16:46 AM UTC 24 Aug 23 08:17:23 AM UTC 24 1939199241 ps
T496 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/486.prim_prince_test.4160641718 Aug 23 08:16:30 AM UTC 24 Aug 23 08:17:24 AM UTC 24 2880278529 ps
T497 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/497.prim_prince_test.2316745284 Aug 23 08:16:51 AM UTC 24 Aug 23 08:17:26 AM UTC 24 1820165299 ps
T498 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/494.prim_prince_test.3973281743 Aug 23 08:16:46 AM UTC 24 Aug 23 08:17:35 AM UTC 24 2657174390 ps
T499 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/498.prim_prince_test.4040287395 Aug 23 08:16:52 AM UTC 24 Aug 23 08:17:44 AM UTC 24 2783230212 ps
T500 /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/499.prim_prince_test.76762628 Aug 23 08:16:55 AM UTC 24 Aug 23 08:17:44 AM UTC 24 2669213521 ps

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/1.prim_prince_test.105376643
Short name T1
Test name
Test status
Simulation time 1028867443 ps
CPU time 14.69 seconds
Started Aug 23 08:01:07 AM UTC 24
Finished Aug 23 08:01:27 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=105376643 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 1.prim_prince_test.105376643
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/1.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/0.prim_prince_test.826561869
Short name T11
Test name
Test status
Simulation time 3150127457 ps
CPU time 46.06 seconds
Started Aug 23 08:01:07 AM UTC 24
Finished Aug 23 08:02:08 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=826561869 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 0.prim_prince_test.826561869
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/0.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/10.prim_prince_test.3658808619
Short name T4
Test name
Test status
Simulation time 1856320679 ps
CPU time 26.33 seconds
Started Aug 23 08:01:09 AM UTC 24
Finished Aug 23 08:01:44 AM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3658808619 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 10.prim_prince_test.3658808619
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/10.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/100.prim_prince_test.2665138903
Short name T95
Test name
Test status
Simulation time 1275352739 ps
CPU time 19.14 seconds
Started Aug 23 08:05:15 AM UTC 24
Finished Aug 23 08:05:40 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2665138903 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 100.prim_prince_test.2665138903
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/100.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/101.prim_prince_test.389054277
Short name T104
Test name
Test status
Simulation time 2408610629 ps
CPU time 35.37 seconds
Started Aug 23 08:05:16 AM UTC 24
Finished Aug 23 08:06:02 AM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=389054277 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 101.prim_prince_test.389054277
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/101.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/102.prim_prince_test.2163800983
Short name T91
Test name
Test status
Simulation time 826966877 ps
CPU time 12.45 seconds
Started Aug 23 08:05:16 AM UTC 24
Finished Aug 23 08:05:33 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2163800983 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 102.prim_prince_test.2163800983
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/102.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/103.prim_prince_test.2303720983
Short name T96
Test name
Test status
Simulation time 791108950 ps
CPU time 11.72 seconds
Started Aug 23 08:05:25 AM UTC 24
Finished Aug 23 08:05:41 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2303720983 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 103.prim_prince_test.2303720983
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/103.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/104.prim_prince_test.23005476
Short name T97
Test name
Test status
Simulation time 1087860515 ps
CPU time 16.32 seconds
Started Aug 23 08:05:26 AM UTC 24
Finished Aug 23 08:05:48 AM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23005476 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 104.prim_prince_test.23005476
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/104.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/105.prim_prince_test.3013931213
Short name T99
Test name
Test status
Simulation time 1066665612 ps
CPU time 16.23 seconds
Started Aug 23 08:05:29 AM UTC 24
Finished Aug 23 08:05:51 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3013931213 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 105.prim_prince_test.3013931213
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/105.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/106.prim_prince_test.2503522387
Short name T110
Test name
Test status
Simulation time 2628862468 ps
CPU time 39.02 seconds
Started Aug 23 08:05:29 AM UTC 24
Finished Aug 23 08:06:19 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2503522387 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 106.prim_prince_test.2503522387
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/106.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/107.prim_prince_test.2235970329
Short name T113
Test name
Test status
Simulation time 3000043895 ps
CPU time 44.36 seconds
Started Aug 23 08:05:32 AM UTC 24
Finished Aug 23 08:06:29 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2235970329 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 107.prim_prince_test.2235970329
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/107.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/108.prim_prince_test.3929361219
Short name T111
Test name
Test status
Simulation time 2659714378 ps
CPU time 39.08 seconds
Started Aug 23 08:05:33 AM UTC 24
Finished Aug 23 08:06:24 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3929361219 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 108.prim_prince_test.3929361219
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/108.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/109.prim_prince_test.547155759
Short name T118
Test name
Test status
Simulation time 3413214261 ps
CPU time 50.25 seconds
Started Aug 23 08:05:35 AM UTC 24
Finished Aug 23 08:06:40 AM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=547155759 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 109.prim_prince_test.547155759
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/109.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/11.prim_prince_test.78186514
Short name T9
Test name
Test status
Simulation time 2599872111 ps
CPU time 36.76 seconds
Started Aug 23 08:01:09 AM UTC 24
Finished Aug 23 08:01:58 AM UTC 24
Peak memory 154632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=78186514 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 11.prim_prince_test.78186514
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/11.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/110.prim_prince_test.2689146314
Short name T119
Test name
Test status
Simulation time 3361029744 ps
CPU time 48.89 seconds
Started Aug 23 08:05:39 AM UTC 24
Finished Aug 23 08:06:42 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2689146314 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 110.prim_prince_test.2689146314
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/110.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/111.prim_prince_test.3395629761
Short name T112
Test name
Test status
Simulation time 2582417613 ps
CPU time 37.45 seconds
Started Aug 23 08:05:40 AM UTC 24
Finished Aug 23 08:06:29 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3395629761 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 111.prim_prince_test.3395629761
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/111.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/112.prim_prince_test.943193960
Short name T120
Test name
Test status
Simulation time 3473875620 ps
CPU time 50.5 seconds
Started Aug 23 08:05:41 AM UTC 24
Finished Aug 23 08:06:46 AM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=943193960 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 112.prim_prince_test.943193960
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/112.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/113.prim_prince_test.1045137662
Short name T109
Test name
Test status
Simulation time 1901917257 ps
CPU time 28.19 seconds
Started Aug 23 08:05:42 AM UTC 24
Finished Aug 23 08:06:18 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1045137662 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 113.prim_prince_test.1045137662
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/113.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/114.prim_prince_test.346982966
Short name T105
Test name
Test status
Simulation time 1142267610 ps
CPU time 16.84 seconds
Started Aug 23 08:05:48 AM UTC 24
Finished Aug 23 08:06:10 AM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=346982966 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 114.prim_prince_test.346982966
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/114.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/115.prim_prince_test.4211011769
Short name T114
Test name
Test status
Simulation time 2187483589 ps
CPU time 31.99 seconds
Started Aug 23 08:05:49 AM UTC 24
Finished Aug 23 08:06:31 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4211011769 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 115.prim_prince_test.4211011769
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/115.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/116.prim_prince_test.3270777842
Short name T125
Test name
Test status
Simulation time 3519228332 ps
CPU time 51.08 seconds
Started Aug 23 08:05:51 AM UTC 24
Finished Aug 23 08:06:57 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3270777842 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 116.prim_prince_test.3270777842
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/116.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/117.prim_prince_test.3103586045
Short name T106
Test name
Test status
Simulation time 783429994 ps
CPU time 11.55 seconds
Started Aug 23 08:05:55 AM UTC 24
Finished Aug 23 08:06:11 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3103586045 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 117.prim_prince_test.3103586045
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/117.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/118.prim_prince_test.3747549856
Short name T116
Test name
Test status
Simulation time 2273689120 ps
CPU time 33.14 seconds
Started Aug 23 08:05:55 AM UTC 24
Finished Aug 23 08:06:39 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3747549856 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 118.prim_prince_test.3747549856
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/118.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/119.prim_prince_test.77799514
Short name T115
Test name
Test status
Simulation time 1678014993 ps
CPU time 25.04 seconds
Started Aug 23 08:05:58 AM UTC 24
Finished Aug 23 08:06:31 AM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=77799514 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 119.prim_prince_test.77799514
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/119.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/12.prim_prince_test.3318985757
Short name T7
Test name
Test status
Simulation time 2124372671 ps
CPU time 30.49 seconds
Started Aug 23 08:01:09 AM UTC 24
Finished Aug 23 08:01:49 AM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3318985757 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 12.prim_prince_test.3318985757
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/12.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/120.prim_prince_test.2987380316
Short name T133
Test name
Test status
Simulation time 3527487372 ps
CPU time 51.48 seconds
Started Aug 23 08:06:02 AM UTC 24
Finished Aug 23 08:07:09 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2987380316 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 120.prim_prince_test.2987380316
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/120.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/121.prim_prince_test.2981458552
Short name T124
Test name
Test status
Simulation time 2799652979 ps
CPU time 40.66 seconds
Started Aug 23 08:06:02 AM UTC 24
Finished Aug 23 08:06:55 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2981458552 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 121.prim_prince_test.2981458552
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/121.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/122.prim_prince_test.2639608884
Short name T121
Test name
Test status
Simulation time 2122073931 ps
CPU time 31.03 seconds
Started Aug 23 08:06:06 AM UTC 24
Finished Aug 23 08:06:46 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2639608884 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 122.prim_prince_test.2639608884
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/122.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/123.prim_prince_test.4251510747
Short name T132
Test name
Test status
Simulation time 3039771824 ps
CPU time 44.73 seconds
Started Aug 23 08:06:11 AM UTC 24
Finished Aug 23 08:07:09 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4251510747 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 123.prim_prince_test.4251510747
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/123.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/124.prim_prince_test.3378044643
Short name T123
Test name
Test status
Simulation time 2012228611 ps
CPU time 30.32 seconds
Started Aug 23 08:06:12 AM UTC 24
Finished Aug 23 08:06:51 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3378044643 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 124.prim_prince_test.3378044643
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/124.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/125.prim_prince_test.1393257122
Short name T117
Test name
Test status
Simulation time 1351555538 ps
CPU time 20.07 seconds
Started Aug 23 08:06:13 AM UTC 24
Finished Aug 23 08:06:40 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1393257122 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 125.prim_prince_test.1393257122
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/125.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/126.prim_prince_test.1651901726
Short name T137
Test name
Test status
Simulation time 3116497104 ps
CPU time 45.82 seconds
Started Aug 23 08:06:16 AM UTC 24
Finished Aug 23 08:07:15 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1651901726 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 126.prim_prince_test.1651901726
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/126.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/127.prim_prince_test.89955136
Short name T138
Test name
Test status
Simulation time 3089854261 ps
CPU time 45.14 seconds
Started Aug 23 08:06:19 AM UTC 24
Finished Aug 23 08:07:17 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=89955136 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 127.prim_prince_test.89955136
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/127.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/128.prim_prince_test.673035764
Short name T129
Test name
Test status
Simulation time 2152992896 ps
CPU time 31.72 seconds
Started Aug 23 08:06:20 AM UTC 24
Finished Aug 23 08:07:02 AM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=673035764 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 128.prim_prince_test.673035764
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/128.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/129.prim_prince_test.2110922526
Short name T122
Test name
Test status
Simulation time 1225812013 ps
CPU time 18.48 seconds
Started Aug 23 08:06:23 AM UTC 24
Finished Aug 23 08:06:48 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2110922526 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 129.prim_prince_test.2110922526
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/129.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/13.prim_prince_test.4187945402
Short name T5
Test name
Test status
Simulation time 931186929 ps
CPU time 13.44 seconds
Started Aug 23 08:01:28 AM UTC 24
Finished Aug 23 08:01:46 AM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4187945402 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 13.prim_prince_test.4187945402
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/13.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/130.prim_prince_test.3688099970
Short name T128
Test name
Test status
Simulation time 1916348677 ps
CPU time 27.82 seconds
Started Aug 23 08:06:24 AM UTC 24
Finished Aug 23 08:07:01 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3688099970 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 130.prim_prince_test.3688099970
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/130.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/131.prim_prince_test.3234478214
Short name T135
Test name
Test status
Simulation time 2178642743 ps
CPU time 32.03 seconds
Started Aug 23 08:06:30 AM UTC 24
Finished Aug 23 08:07:11 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3234478214 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 131.prim_prince_test.3234478214
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/131.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/132.prim_prince_test.3757485541
Short name T134
Test name
Test status
Simulation time 2031459345 ps
CPU time 30.25 seconds
Started Aug 23 08:06:30 AM UTC 24
Finished Aug 23 08:07:09 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3757485541 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 132.prim_prince_test.3757485541
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/132.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/133.prim_prince_test.3350297394
Short name T130
Test name
Test status
Simulation time 1662490487 ps
CPU time 24.6 seconds
Started Aug 23 08:06:32 AM UTC 24
Finished Aug 23 08:07:04 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3350297394 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 133.prim_prince_test.3350297394
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/133.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/134.prim_prince_test.1100647488
Short name T126
Test name
Test status
Simulation time 1358500190 ps
CPU time 20.04 seconds
Started Aug 23 08:06:32 AM UTC 24
Finished Aug 23 08:06:58 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1100647488 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 134.prim_prince_test.1100647488
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/134.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/135.prim_prince_test.2235728477
Short name T140
Test name
Test status
Simulation time 2403038641 ps
CPU time 35.51 seconds
Started Aug 23 08:06:40 AM UTC 24
Finished Aug 23 08:07:26 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2235728477 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 135.prim_prince_test.2235728477
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/135.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/136.prim_prince_test.2461022533
Short name T127
Test name
Test status
Simulation time 973806814 ps
CPU time 14.32 seconds
Started Aug 23 08:06:41 AM UTC 24
Finished Aug 23 08:07:00 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2461022533 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 136.prim_prince_test.2461022533
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/136.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/137.prim_prince_test.484128552
Short name T144
Test name
Test status
Simulation time 3051234036 ps
CPU time 44.57 seconds
Started Aug 23 08:06:41 AM UTC 24
Finished Aug 23 08:07:39 AM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=484128552 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 137.prim_prince_test.484128552
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/137.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/138.prim_prince_test.2949604912
Short name T142
Test name
Test status
Simulation time 2572407451 ps
CPU time 37.55 seconds
Started Aug 23 08:06:43 AM UTC 24
Finished Aug 23 08:07:31 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2949604912 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 138.prim_prince_test.2949604912
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/138.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/139.prim_prince_test.234728788
Short name T136
Test name
Test status
Simulation time 1316237482 ps
CPU time 19.52 seconds
Started Aug 23 08:06:46 AM UTC 24
Finished Aug 23 08:07:12 AM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=234728788 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 139.prim_prince_test.234728788
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/139.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/14.prim_prince_test.828743934
Short name T21
Test name
Test status
Simulation time 3384049756 ps
CPU time 49.31 seconds
Started Aug 23 08:01:35 AM UTC 24
Finished Aug 23 08:02:39 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=828743934 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 14.prim_prince_test.828743934
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/14.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/140.prim_prince_test.1473282978
Short name T152
Test name
Test status
Simulation time 3445538243 ps
CPU time 50.61 seconds
Started Aug 23 08:06:47 AM UTC 24
Finished Aug 23 08:07:53 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1473282978 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 140.prim_prince_test.1473282978
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/140.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/141.prim_prince_test.3358099317
Short name T131
Test name
Test status
Simulation time 966266498 ps
CPU time 14.39 seconds
Started Aug 23 08:06:48 AM UTC 24
Finished Aug 23 08:07:08 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3358099317 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 141.prim_prince_test.3358099317
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/141.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/142.prim_prince_test.2968732937
Short name T146
Test name
Test status
Simulation time 2535319333 ps
CPU time 37.34 seconds
Started Aug 23 08:06:52 AM UTC 24
Finished Aug 23 08:07:40 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2968732937 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 142.prim_prince_test.2968732937
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/142.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/143.prim_prince_test.3938540392
Short name T139
Test name
Test status
Simulation time 1436079717 ps
CPU time 21.14 seconds
Started Aug 23 08:06:55 AM UTC 24
Finished Aug 23 08:07:23 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3938540392 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 143.prim_prince_test.3938540392
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/143.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/144.prim_prince_test.3275708464
Short name T151
Test name
Test status
Simulation time 2878487440 ps
CPU time 41.79 seconds
Started Aug 23 08:06:57 AM UTC 24
Finished Aug 23 08:07:52 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3275708464 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 144.prim_prince_test.3275708464
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/144.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/145.prim_prince_test.51162595
Short name T154
Test name
Test status
Simulation time 3002255142 ps
CPU time 44.21 seconds
Started Aug 23 08:07:00 AM UTC 24
Finished Aug 23 08:07:56 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=51162595 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 145.prim_prince_test.51162595
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/145.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/146.prim_prince_test.3044904219
Short name T147
Test name
Test status
Simulation time 2087032019 ps
CPU time 31.21 seconds
Started Aug 23 08:07:01 AM UTC 24
Finished Aug 23 08:07:41 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3044904219 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 146.prim_prince_test.3044904219
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/146.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/147.prim_prince_test.82027095
Short name T143
Test name
Test status
Simulation time 1599705590 ps
CPU time 23.29 seconds
Started Aug 23 08:07:02 AM UTC 24
Finished Aug 23 08:07:32 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=82027095 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 147.prim_prince_test.82027095
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/147.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/148.prim_prince_test.83342082
Short name T149
Test name
Test status
Simulation time 2274656621 ps
CPU time 33.03 seconds
Started Aug 23 08:07:03 AM UTC 24
Finished Aug 23 08:07:46 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=83342082 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 148.prim_prince_test.83342082
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/148.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/149.prim_prince_test.3717116448
Short name T161
Test name
Test status
Simulation time 3550819136 ps
CPU time 51.47 seconds
Started Aug 23 08:07:05 AM UTC 24
Finished Aug 23 08:08:11 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3717116448 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 149.prim_prince_test.3717116448
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/149.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/15.prim_prince_test.218103592
Short name T10
Test name
Test status
Simulation time 1064652862 ps
CPU time 15.11 seconds
Started Aug 23 08:01:43 AM UTC 24
Finished Aug 23 08:02:03 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=218103592 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 15.prim_prince_test.218103592
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/15.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/150.prim_prince_test.2344000449
Short name T153
Test name
Test status
Simulation time 2461272889 ps
CPU time 36.51 seconds
Started Aug 23 08:07:08 AM UTC 24
Finished Aug 23 08:07:55 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2344000449 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 150.prim_prince_test.2344000449
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/150.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/151.prim_prince_test.1303492728
Short name T150
Test name
Test status
Simulation time 2038189774 ps
CPU time 30.04 seconds
Started Aug 23 08:07:10 AM UTC 24
Finished Aug 23 08:07:49 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1303492728 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 151.prim_prince_test.1303492728
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/151.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/152.prim_prince_test.3784504359
Short name T141
Test name
Test status
Simulation time 880067719 ps
CPU time 13.27 seconds
Started Aug 23 08:07:10 AM UTC 24
Finished Aug 23 08:07:28 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3784504359 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 152.prim_prince_test.3784504359
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/152.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/153.prim_prince_test.793253901
Short name T148
Test name
Test status
Simulation time 1621153782 ps
CPU time 23.81 seconds
Started Aug 23 08:07:10 AM UTC 24
Finished Aug 23 08:07:41 AM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=793253901 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 153.prim_prince_test.793253901
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/153.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/154.prim_prince_test.725031463
Short name T163
Test name
Test status
Simulation time 3402625988 ps
CPU time 49.74 seconds
Started Aug 23 08:07:12 AM UTC 24
Finished Aug 23 08:08:16 AM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=725031463 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 154.prim_prince_test.725031463
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/154.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/155.prim_prince_test.3093481307
Short name T145
Test name
Test status
Simulation time 1486638846 ps
CPU time 21.35 seconds
Started Aug 23 08:07:12 AM UTC 24
Finished Aug 23 08:07:40 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3093481307 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 155.prim_prince_test.3093481307
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/155.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/156.prim_prince_test.684620376
Short name T158
Test name
Test status
Simulation time 2430615365 ps
CPU time 35.66 seconds
Started Aug 23 08:07:15 AM UTC 24
Finished Aug 23 08:08:02 AM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=684620376 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 156.prim_prince_test.684620376
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/156.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/157.prim_prince_test.3650082296
Short name T156
Test name
Test status
Simulation time 2123388962 ps
CPU time 31.08 seconds
Started Aug 23 08:07:18 AM UTC 24
Finished Aug 23 08:07:58 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3650082296 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 157.prim_prince_test.3650082296
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/157.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/158.prim_prince_test.2617311677
Short name T155
Test name
Test status
Simulation time 1832812747 ps
CPU time 26.75 seconds
Started Aug 23 08:07:24 AM UTC 24
Finished Aug 23 08:07:58 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2617311677 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 158.prim_prince_test.2617311677
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/158.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/159.prim_prince_test.2049269922
Short name T159
Test name
Test status
Simulation time 2211061202 ps
CPU time 32.59 seconds
Started Aug 23 08:07:27 AM UTC 24
Finished Aug 23 08:08:09 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2049269922 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 159.prim_prince_test.2049269922
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/159.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/16.prim_prince_test.2082215570
Short name T25
Test name
Test status
Simulation time 3618377909 ps
CPU time 51.3 seconds
Started Aug 23 08:01:45 AM UTC 24
Finished Aug 23 08:02:52 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2082215570 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 16.prim_prince_test.2082215570
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/16.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/160.prim_prince_test.3280431287
Short name T160
Test name
Test status
Simulation time 2226811694 ps
CPU time 32.64 seconds
Started Aug 23 08:07:27 AM UTC 24
Finished Aug 23 08:08:10 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3280431287 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 160.prim_prince_test.3280431287
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/160.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/161.prim_prince_test.2410441265
Short name T166
Test name
Test status
Simulation time 3076928949 ps
CPU time 44.91 seconds
Started Aug 23 08:07:28 AM UTC 24
Finished Aug 23 08:08:26 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2410441265 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 161.prim_prince_test.2410441265
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/161.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/162.prim_prince_test.3120659944
Short name T165
Test name
Test status
Simulation time 2364372388 ps
CPU time 35.05 seconds
Started Aug 23 08:07:32 AM UTC 24
Finished Aug 23 08:08:17 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3120659944 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 162.prim_prince_test.3120659944
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/162.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/163.prim_prince_test.438217172
Short name T157
Test name
Test status
Simulation time 1453051937 ps
CPU time 21.36 seconds
Started Aug 23 08:07:32 AM UTC 24
Finished Aug 23 08:08:00 AM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=438217172 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 163.prim_prince_test.438217172
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/163.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/164.prim_prince_test.3900293568
Short name T162
Test name
Test status
Simulation time 1704327684 ps
CPU time 25.21 seconds
Started Aug 23 08:07:39 AM UTC 24
Finished Aug 23 08:08:12 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3900293568 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 164.prim_prince_test.3900293568
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/164.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/165.prim_prince_test.875902968
Short name T177
Test name
Test status
Simulation time 3711232146 ps
CPU time 54.4 seconds
Started Aug 23 08:07:40 AM UTC 24
Finished Aug 23 08:08:50 AM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=875902968 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 165.prim_prince_test.875902968
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/165.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/166.prim_prince_test.2078129615
Short name T167
Test name
Test status
Simulation time 2453785166 ps
CPU time 36.41 seconds
Started Aug 23 08:07:42 AM UTC 24
Finished Aug 23 08:08:29 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2078129615 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 166.prim_prince_test.2078129615
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/166.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/167.prim_prince_test.4276132203
Short name T170
Test name
Test status
Simulation time 3005312962 ps
CPU time 44.14 seconds
Started Aug 23 08:07:42 AM UTC 24
Finished Aug 23 08:08:39 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4276132203 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 167.prim_prince_test.4276132203
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/167.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/168.prim_prince_test.4058655814
Short name T174
Test name
Test status
Simulation time 3381275516 ps
CPU time 50.03 seconds
Started Aug 23 08:07:42 AM UTC 24
Finished Aug 23 08:08:46 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4058655814 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 168.prim_prince_test.4058655814
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/168.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/169.prim_prince_test.964479011
Short name T183
Test name
Test status
Simulation time 3679441112 ps
CPU time 54.25 seconds
Started Aug 23 08:07:47 AM UTC 24
Finished Aug 23 08:08:56 AM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=964479011 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 169.prim_prince_test.964479011
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/169.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/17.prim_prince_test.740303219
Short name T20
Test name
Test status
Simulation time 2713915573 ps
CPU time 39.15 seconds
Started Aug 23 08:01:47 AM UTC 24
Finished Aug 23 08:02:38 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=740303219 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 17.prim_prince_test.740303219
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/17.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/170.prim_prince_test.4268489393
Short name T164
Test name
Test status
Simulation time 1378848626 ps
CPU time 20.38 seconds
Started Aug 23 08:07:50 AM UTC 24
Finished Aug 23 08:08:16 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4268489393 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 170.prim_prince_test.4268489393
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/170.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/171.prim_prince_test.157498059
Short name T168
Test name
Test status
Simulation time 2146541983 ps
CPU time 31.72 seconds
Started Aug 23 08:07:53 AM UTC 24
Finished Aug 23 08:08:34 AM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=157498059 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 171.prim_prince_test.157498059
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/171.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/172.prim_prince_test.4094627710
Short name T179
Test name
Test status
Simulation time 2994603187 ps
CPU time 43.53 seconds
Started Aug 23 08:07:54 AM UTC 24
Finished Aug 23 08:08:51 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4094627710 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 172.prim_prince_test.4094627710
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/172.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/173.prim_prince_test.3288340604
Short name T169
Test name
Test status
Simulation time 2094080659 ps
CPU time 31.4 seconds
Started Aug 23 08:07:56 AM UTC 24
Finished Aug 23 08:08:36 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3288340604 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 173.prim_prince_test.3288340604
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/173.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/174.prim_prince_test.3281356145
Short name T186
Test name
Test status
Simulation time 3472933511 ps
CPU time 51.01 seconds
Started Aug 23 08:07:57 AM UTC 24
Finished Aug 23 08:09:03 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3281356145 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 174.prim_prince_test.3281356145
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/174.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/175.prim_prince_test.1395981706
Short name T176
Test name
Test status
Simulation time 2582900584 ps
CPU time 38.46 seconds
Started Aug 23 08:07:59 AM UTC 24
Finished Aug 23 08:08:48 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1395981706 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 175.prim_prince_test.1395981706
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/175.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/176.prim_prince_test.3797794063
Short name T180
Test name
Test status
Simulation time 2712253101 ps
CPU time 40.25 seconds
Started Aug 23 08:07:59 AM UTC 24
Finished Aug 23 08:08:51 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3797794063 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 176.prim_prince_test.3797794063
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/176.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/177.prim_prince_test.3827283993
Short name T175
Test name
Test status
Simulation time 2459053299 ps
CPU time 36.09 seconds
Started Aug 23 08:08:01 AM UTC 24
Finished Aug 23 08:08:48 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3827283993 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 177.prim_prince_test.3827283993
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/177.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/178.prim_prince_test.776659080
Short name T182
Test name
Test status
Simulation time 2737586273 ps
CPU time 40.48 seconds
Started Aug 23 08:08:02 AM UTC 24
Finished Aug 23 08:08:55 AM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=776659080 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 178.prim_prince_test.776659080
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/178.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/179.prim_prince_test.48225634
Short name T171
Test name
Test status
Simulation time 1751528137 ps
CPU time 26.31 seconds
Started Aug 23 08:08:10 AM UTC 24
Finished Aug 23 08:08:43 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=48225634 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 179.prim_prince_test.48225634
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/179.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/18.prim_prince_test.3137644058
Short name T17
Test name
Test status
Simulation time 2414753964 ps
CPU time 35.4 seconds
Started Aug 23 08:01:48 AM UTC 24
Finished Aug 23 08:02:34 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3137644058 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 18.prim_prince_test.3137644058
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/18.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/180.prim_prince_test.2599750794
Short name T172
Test name
Test status
Simulation time 1703901068 ps
CPU time 25.34 seconds
Started Aug 23 08:08:11 AM UTC 24
Finished Aug 23 08:08:43 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2599750794 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 180.prim_prince_test.2599750794
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/180.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/181.prim_prince_test.2814915192
Short name T193
Test name
Test status
Simulation time 3686381429 ps
CPU time 54.92 seconds
Started Aug 23 08:08:12 AM UTC 24
Finished Aug 23 08:09:22 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2814915192 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 181.prim_prince_test.2814915192
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/181.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/182.prim_prince_test.4100406551
Short name T189
Test name
Test status
Simulation time 3031403511 ps
CPU time 44.76 seconds
Started Aug 23 08:08:13 AM UTC 24
Finished Aug 23 08:09:11 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4100406551 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 182.prim_prince_test.4100406551
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/182.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/183.prim_prince_test.3724343406
Short name T191
Test name
Test status
Simulation time 3596716783 ps
CPU time 52.89 seconds
Started Aug 23 08:08:13 AM UTC 24
Finished Aug 23 08:09:20 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3724343406 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 183.prim_prince_test.3724343406
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/183.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/184.prim_prince_test.3327469697
Short name T196
Test name
Test status
Simulation time 3695057333 ps
CPU time 53.96 seconds
Started Aug 23 08:08:17 AM UTC 24
Finished Aug 23 08:09:26 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3327469697 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 184.prim_prince_test.3327469697
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/184.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/185.prim_prince_test.2335673529
Short name T181
Test name
Test status
Simulation time 1873648205 ps
CPU time 27.76 seconds
Started Aug 23 08:08:17 AM UTC 24
Finished Aug 23 08:08:54 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2335673529 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 185.prim_prince_test.2335673529
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/185.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/186.prim_prince_test.673156593
Short name T173
Test name
Test status
Simulation time 1395330764 ps
CPU time 20.47 seconds
Started Aug 23 08:08:18 AM UTC 24
Finished Aug 23 08:08:45 AM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=673156593 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 186.prim_prince_test.673156593
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/186.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/187.prim_prince_test.2984856257
Short name T178
Test name
Test status
Simulation time 1233093308 ps
CPU time 18.4 seconds
Started Aug 23 08:08:26 AM UTC 24
Finished Aug 23 08:08:51 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2984856257 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 187.prim_prince_test.2984856257
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/187.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/188.prim_prince_test.2246402270
Short name T188
Test name
Test status
Simulation time 2022624468 ps
CPU time 30.04 seconds
Started Aug 23 08:08:30 AM UTC 24
Finished Aug 23 08:09:08 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2246402270 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 188.prim_prince_test.2246402270
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/188.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/189.prim_prince_test.270153079
Short name T187
Test name
Test status
Simulation time 1564226103 ps
CPU time 23.39 seconds
Started Aug 23 08:08:35 AM UTC 24
Finished Aug 23 08:09:05 AM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=270153079 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 189.prim_prince_test.270153079
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/189.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/19.prim_prince_test.2954168643
Short name T23
Test name
Test status
Simulation time 2747890496 ps
CPU time 39.22 seconds
Started Aug 23 08:01:50 AM UTC 24
Finished Aug 23 08:02:41 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2954168643 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 19.prim_prince_test.2954168643
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/19.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/190.prim_prince_test.3733722437
Short name T184
Test name
Test status
Simulation time 1070981440 ps
CPU time 15.83 seconds
Started Aug 23 08:08:37 AM UTC 24
Finished Aug 23 08:08:58 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3733722437 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 190.prim_prince_test.3733722437
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/190.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/191.prim_prince_test.1025713845
Short name T185
Test name
Test status
Simulation time 1010087833 ps
CPU time 14.73 seconds
Started Aug 23 08:08:40 AM UTC 24
Finished Aug 23 08:08:59 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1025713845 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 191.prim_prince_test.1025713845
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/191.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/192.prim_prince_test.4081495665
Short name T208
Test name
Test status
Simulation time 3172269649 ps
CPU time 46.45 seconds
Started Aug 23 08:08:44 AM UTC 24
Finished Aug 23 08:09:44 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4081495665 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 192.prim_prince_test.4081495665
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/192.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/193.prim_prince_test.3381901750
Short name T203
Test name
Test status
Simulation time 2980597637 ps
CPU time 43.66 seconds
Started Aug 23 08:08:44 AM UTC 24
Finished Aug 23 08:09:40 AM UTC 24
Peak memory 156120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3381901750 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 193.prim_prince_test.3381901750
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/193.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/194.prim_prince_test.1179633402
Short name T206
Test name
Test status
Simulation time 3090685918 ps
CPU time 45.24 seconds
Started Aug 23 08:08:45 AM UTC 24
Finished Aug 23 08:09:43 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1179633402 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 194.prim_prince_test.1179633402
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/194.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/195.prim_prince_test.2628705180
Short name T194
Test name
Test status
Simulation time 1891857714 ps
CPU time 28.54 seconds
Started Aug 23 08:08:46 AM UTC 24
Finished Aug 23 08:09:23 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2628705180 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 195.prim_prince_test.2628705180
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/195.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/196.prim_prince_test.2674337780
Short name T197
Test name
Test status
Simulation time 2248364425 ps
CPU time 32.86 seconds
Started Aug 23 08:08:46 AM UTC 24
Finished Aug 23 08:09:29 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2674337780 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 196.prim_prince_test.2674337780
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/196.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/197.prim_prince_test.3440242560
Short name T192
Test name
Test status
Simulation time 1688175809 ps
CPU time 24.86 seconds
Started Aug 23 08:08:49 AM UTC 24
Finished Aug 23 08:09:21 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3440242560 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 197.prim_prince_test.3440242560
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/197.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/198.prim_prince_test.898656081
Short name T198
Test name
Test status
Simulation time 2130705348 ps
CPU time 31.32 seconds
Started Aug 23 08:08:50 AM UTC 24
Finished Aug 23 08:09:30 AM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=898656081 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 198.prim_prince_test.898656081
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/198.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/199.prim_prince_test.4285269391
Short name T201
Test name
Test status
Simulation time 2233403348 ps
CPU time 33.02 seconds
Started Aug 23 08:08:51 AM UTC 24
Finished Aug 23 08:09:33 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4285269391 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 199.prim_prince_test.4285269391
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/199.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/2.prim_prince_test.551110328
Short name T2
Test name
Test status
Simulation time 1383455972 ps
CPU time 20.3 seconds
Started Aug 23 08:01:07 AM UTC 24
Finished Aug 23 08:01:35 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=551110328 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 2.prim_prince_test.551110328
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/2.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/20.prim_prince_test.471028336
Short name T19
Test name
Test status
Simulation time 2140615977 ps
CPU time 30.86 seconds
Started Aug 23 08:01:55 AM UTC 24
Finished Aug 23 08:02:36 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=471028336 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 20.prim_prince_test.471028336
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/20.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/200.prim_prince_test.1484603344
Short name T202
Test name
Test status
Simulation time 2504576817 ps
CPU time 36.06 seconds
Started Aug 23 08:08:52 AM UTC 24
Finished Aug 23 08:09:39 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1484603344 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 200.prim_prince_test.1484603344
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/200.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/201.prim_prince_test.186330732
Short name T195
Test name
Test status
Simulation time 1687707530 ps
CPU time 24.91 seconds
Started Aug 23 08:08:52 AM UTC 24
Finished Aug 23 08:09:24 AM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=186330732 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 201.prim_prince_test.186330732
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/201.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/202.prim_prince_test.1426124744
Short name T216
Test name
Test status
Simulation time 3563685769 ps
CPU time 51.84 seconds
Started Aug 23 08:08:52 AM UTC 24
Finished Aug 23 08:09:58 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1426124744 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 202.prim_prince_test.1426124744
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/202.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/203.prim_prince_test.3583629584
Short name T199
Test name
Test status
Simulation time 1920625701 ps
CPU time 28.84 seconds
Started Aug 23 08:08:54 AM UTC 24
Finished Aug 23 08:09:31 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3583629584 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 203.prim_prince_test.3583629584
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/203.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/204.prim_prince_test.2191693037
Short name T190
Test name
Test status
Simulation time 869935480 ps
CPU time 12.81 seconds
Started Aug 23 08:08:55 AM UTC 24
Finished Aug 23 08:09:12 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2191693037 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 204.prim_prince_test.2191693037
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/204.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/205.prim_prince_test.3247354850
Short name T204
Test name
Test status
Simulation time 2371231850 ps
CPU time 34.84 seconds
Started Aug 23 08:08:56 AM UTC 24
Finished Aug 23 08:09:41 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3247354850 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 205.prim_prince_test.3247354850
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/205.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/206.prim_prince_test.1705664472
Short name T207
Test name
Test status
Simulation time 2389359558 ps
CPU time 34.78 seconds
Started Aug 23 08:08:58 AM UTC 24
Finished Aug 23 08:09:43 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1705664472 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 206.prim_prince_test.1705664472
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/206.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/207.prim_prince_test.2651609439
Short name T215
Test name
Test status
Simulation time 2859664259 ps
CPU time 42.87 seconds
Started Aug 23 08:09:01 AM UTC 24
Finished Aug 23 08:09:55 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2651609439 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 207.prim_prince_test.2651609439
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/207.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/208.prim_prince_test.2063616347
Short name T205
Test name
Test status
Simulation time 2136227666 ps
CPU time 31.58 seconds
Started Aug 23 08:09:01 AM UTC 24
Finished Aug 23 08:09:41 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2063616347 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 208.prim_prince_test.2063616347
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/208.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/209.prim_prince_test.2562964542
Short name T225
Test name
Test status
Simulation time 3701248501 ps
CPU time 53.25 seconds
Started Aug 23 08:09:04 AM UTC 24
Finished Aug 23 08:10:11 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2562964542 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 209.prim_prince_test.2562964542
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/209.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/21.prim_prince_test.2141389158
Short name T16
Test name
Test status
Simulation time 1382618917 ps
CPU time 20.24 seconds
Started Aug 23 08:01:58 AM UTC 24
Finished Aug 23 08:02:25 AM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2141389158 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 21.prim_prince_test.2141389158
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/21.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/210.prim_prince_test.691339146
Short name T200
Test name
Test status
Simulation time 1369657007 ps
CPU time 20.24 seconds
Started Aug 23 08:09:06 AM UTC 24
Finished Aug 23 08:09:32 AM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=691339146 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 210.prim_prince_test.691339146
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/210.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/211.prim_prince_test.1044022830
Short name T209
Test name
Test status
Simulation time 1841091440 ps
CPU time 27.15 seconds
Started Aug 23 08:09:09 AM UTC 24
Finished Aug 23 08:09:44 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1044022830 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 211.prim_prince_test.1044022830
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/211.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/212.prim_prince_test.3242031670
Short name T212
Test name
Test status
Simulation time 2041831154 ps
CPU time 29.94 seconds
Started Aug 23 08:09:12 AM UTC 24
Finished Aug 23 08:09:51 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3242031670 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 212.prim_prince_test.3242031670
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/212.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/213.prim_prince_test.3869893106
Short name T217
Test name
Test status
Simulation time 2462505674 ps
CPU time 35.82 seconds
Started Aug 23 08:09:13 AM UTC 24
Finished Aug 23 08:09:59 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3869893106 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 213.prim_prince_test.3869893106
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/213.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/214.prim_prince_test.513560134
Short name T229
Test name
Test status
Simulation time 3363798281 ps
CPU time 49.25 seconds
Started Aug 23 08:09:21 AM UTC 24
Finished Aug 23 08:10:24 AM UTC 24
Peak memory 154344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=513560134 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 214.prim_prince_test.513560134
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/214.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/215.prim_prince_test.1427916110
Short name T231
Test name
Test status
Simulation time 3467718330 ps
CPU time 51.01 seconds
Started Aug 23 08:09:21 AM UTC 24
Finished Aug 23 08:10:26 AM UTC 24
Peak memory 154460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1427916110 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 215.prim_prince_test.1427916110
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/215.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/216.prim_prince_test.2855392380
Short name T222
Test name
Test status
Simulation time 2413477813 ps
CPU time 36.11 seconds
Started Aug 23 08:09:23 AM UTC 24
Finished Aug 23 08:10:09 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2855392380 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 216.prim_prince_test.2855392380
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/216.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/217.prim_prince_test.2592401604
Short name T210
Test name
Test status
Simulation time 1182699741 ps
CPU time 17.51 seconds
Started Aug 23 08:09:24 AM UTC 24
Finished Aug 23 08:09:46 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2592401604 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 217.prim_prince_test.2592401604
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/217.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/218.prim_prince_test.820622635
Short name T218
Test name
Test status
Simulation time 1868251428 ps
CPU time 27.2 seconds
Started Aug 23 08:09:26 AM UTC 24
Finished Aug 23 08:10:01 AM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=820622635 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 218.prim_prince_test.820622635
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/218.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/219.prim_prince_test.4198587900
Short name T219
Test name
Test status
Simulation time 1992747450 ps
CPU time 29.21 seconds
Started Aug 23 08:09:27 AM UTC 24
Finished Aug 23 08:10:04 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4198587900 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 219.prim_prince_test.4198587900
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/219.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/22.prim_prince_test.616627425
Short name T24
Test name
Test status
Simulation time 2172871348 ps
CPU time 31.81 seconds
Started Aug 23 08:02:04 AM UTC 24
Finished Aug 23 08:02:46 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=616627425 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 22.prim_prince_test.616627425
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/22.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/220.prim_prince_test.1938244349
Short name T228
Test name
Test status
Simulation time 2722086911 ps
CPU time 40.66 seconds
Started Aug 23 08:09:30 AM UTC 24
Finished Aug 23 08:10:22 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1938244349 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 220.prim_prince_test.1938244349
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/220.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/221.prim_prince_test.663557425
Short name T241
Test name
Test status
Simulation time 3731804814 ps
CPU time 53.27 seconds
Started Aug 23 08:09:31 AM UTC 24
Finished Aug 23 08:10:39 AM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=663557425 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 221.prim_prince_test.663557425
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/221.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/222.prim_prince_test.2074832867
Short name T211
Test name
Test status
Simulation time 826946753 ps
CPU time 12.29 seconds
Started Aug 23 08:09:32 AM UTC 24
Finished Aug 23 08:09:48 AM UTC 24
Peak memory 154348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2074832867 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 222.prim_prince_test.2074832867
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/222.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/223.prim_prince_test.3143167192
Short name T213
Test name
Test status
Simulation time 1055532600 ps
CPU time 15.99 seconds
Started Aug 23 08:09:33 AM UTC 24
Finished Aug 23 08:09:54 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3143167192 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 223.prim_prince_test.3143167192
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/223.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/224.prim_prince_test.2789413585
Short name T242
Test name
Test status
Simulation time 3498910003 ps
CPU time 50.97 seconds
Started Aug 23 08:09:34 AM UTC 24
Finished Aug 23 08:10:39 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2789413585 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 224.prim_prince_test.2789413585
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/224.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/225.prim_prince_test.99251625
Short name T214
Test name
Test status
Simulation time 795033900 ps
CPU time 11.67 seconds
Started Aug 23 08:09:39 AM UTC 24
Finished Aug 23 08:09:55 AM UTC 24
Peak memory 154352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=99251625 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 225.prim_prince_test.99251625
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/225.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/226.prim_prince_test.298358722
Short name T223
Test name
Test status
Simulation time 1515607796 ps
CPU time 22.45 seconds
Started Aug 23 08:09:41 AM UTC 24
Finished Aug 23 08:10:10 AM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=298358722 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 226.prim_prince_test.298358722
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/226.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/227.prim_prince_test.3254571293
Short name T244
Test name
Test status
Simulation time 3220262648 ps
CPU time 46.59 seconds
Started Aug 23 08:09:43 AM UTC 24
Finished Aug 23 08:10:42 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3254571293 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 227.prim_prince_test.3254571293
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/227.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/228.prim_prince_test.1083029244
Short name T226
Test name
Test status
Simulation time 1643408484 ps
CPU time 24.31 seconds
Started Aug 23 08:09:43 AM UTC 24
Finished Aug 23 08:10:14 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1083029244 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 228.prim_prince_test.1083029244
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/228.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/229.prim_prince_test.4016415862
Short name T220
Test name
Test status
Simulation time 1193391602 ps
CPU time 17.41 seconds
Started Aug 23 08:09:44 AM UTC 24
Finished Aug 23 08:10:07 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4016415862 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 229.prim_prince_test.4016415862
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/229.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/23.prim_prince_test.279213082
Short name T33
Test name
Test status
Simulation time 3515451680 ps
CPU time 50.08 seconds
Started Aug 23 08:02:08 AM UTC 24
Finished Aug 23 08:03:13 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=279213082 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 23.prim_prince_test.279213082
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/23.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/230.prim_prince_test.373522290
Short name T227
Test name
Test status
Simulation time 1882151445 ps
CPU time 27.55 seconds
Started Aug 23 08:09:44 AM UTC 24
Finished Aug 23 08:10:20 AM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=373522290 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 230.prim_prince_test.373522290
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/230.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/231.prim_prince_test.3307043275
Short name T243
Test name
Test status
Simulation time 2943874311 ps
CPU time 42.82 seconds
Started Aug 23 08:09:45 AM UTC 24
Finished Aug 23 08:10:40 AM UTC 24
Peak memory 154512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3307043275 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 231.prim_prince_test.3307043275
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/231.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/232.prim_prince_test.3823385829
Short name T221
Test name
Test status
Simulation time 1280318409 ps
CPU time 18.36 seconds
Started Aug 23 08:09:45 AM UTC 24
Finished Aug 23 08:10:09 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3823385829 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 232.prim_prince_test.3823385829
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/232.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/233.prim_prince_test.1302357458
Short name T236
Test name
Test status
Simulation time 2280220345 ps
CPU time 33.52 seconds
Started Aug 23 08:09:47 AM UTC 24
Finished Aug 23 08:10:30 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1302357458 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 233.prim_prince_test.1302357458
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/233.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/234.prim_prince_test.3565795111
Short name T238
Test name
Test status
Simulation time 2425193373 ps
CPU time 35.44 seconds
Started Aug 23 08:09:49 AM UTC 24
Finished Aug 23 08:10:35 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3565795111 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 234.prim_prince_test.3565795111
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/234.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/235.prim_prince_test.494881766
Short name T232
Test name
Test status
Simulation time 1917680731 ps
CPU time 28.22 seconds
Started Aug 23 08:09:51 AM UTC 24
Finished Aug 23 08:10:28 AM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=494881766 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 235.prim_prince_test.494881766
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/235.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/236.prim_prince_test.1422276041
Short name T240
Test name
Test status
Simulation time 2342148714 ps
CPU time 34.16 seconds
Started Aug 23 08:09:55 AM UTC 24
Finished Aug 23 08:10:38 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1422276041 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 236.prim_prince_test.1422276041
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/236.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/237.prim_prince_test.436656816
Short name T251
Test name
Test status
Simulation time 3349152777 ps
CPU time 48.83 seconds
Started Aug 23 08:09:55 AM UTC 24
Finished Aug 23 08:10:57 AM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=436656816 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 237.prim_prince_test.436656816
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/237.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/238.prim_prince_test.1523587043
Short name T239
Test name
Test status
Simulation time 2194564213 ps
CPU time 32.47 seconds
Started Aug 23 08:09:56 AM UTC 24
Finished Aug 23 08:10:37 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1523587043 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 238.prim_prince_test.1523587043
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/238.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/239.prim_prince_test.993181759
Short name T224
Test name
Test status
Simulation time 765066911 ps
CPU time 11.58 seconds
Started Aug 23 08:09:56 AM UTC 24
Finished Aug 23 08:10:11 AM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=993181759 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 239.prim_prince_test.993181759
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/239.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/24.prim_prince_test.60365433
Short name T27
Test name
Test status
Simulation time 2440377248 ps
CPU time 35.75 seconds
Started Aug 23 08:02:08 AM UTC 24
Finished Aug 23 08:02:56 AM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=60365433 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 24.prim_prince_test.60365433
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/24.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/240.prim_prince_test.2921296325
Short name T233
Test name
Test status
Simulation time 1542500345 ps
CPU time 22.7 seconds
Started Aug 23 08:09:59 AM UTC 24
Finished Aug 23 08:10:28 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2921296325 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 240.prim_prince_test.2921296325
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/240.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/241.prim_prince_test.161299323
Short name T259
Test name
Test status
Simulation time 3669900330 ps
CPU time 54.23 seconds
Started Aug 23 08:10:00 AM UTC 24
Finished Aug 23 08:11:09 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=161299323 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 241.prim_prince_test.161299323
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/241.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/242.prim_prince_test.456426356
Short name T235
Test name
Test status
Simulation time 1491708467 ps
CPU time 22.17 seconds
Started Aug 23 08:10:01 AM UTC 24
Finished Aug 23 08:10:30 AM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=456426356 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 242.prim_prince_test.456426356
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/242.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/243.prim_prince_test.1607357763
Short name T230
Test name
Test status
Simulation time 973371369 ps
CPU time 14.81 seconds
Started Aug 23 08:10:05 AM UTC 24
Finished Aug 23 08:10:25 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1607357763 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 243.prim_prince_test.1607357763
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/243.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/244.prim_prince_test.3284346746
Short name T257
Test name
Test status
Simulation time 3159932152 ps
CPU time 45.8 seconds
Started Aug 23 08:10:07 AM UTC 24
Finished Aug 23 08:11:06 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3284346746 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 244.prim_prince_test.3284346746
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/244.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/245.prim_prince_test.1421079868
Short name T237
Test name
Test status
Simulation time 1230887529 ps
CPU time 18.3 seconds
Started Aug 23 08:10:10 AM UTC 24
Finished Aug 23 08:10:34 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1421079868 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 245.prim_prince_test.1421079868
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/245.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/246.prim_prince_test.3353747756
Short name T260
Test name
Test status
Simulation time 3212234267 ps
CPU time 46.99 seconds
Started Aug 23 08:10:10 AM UTC 24
Finished Aug 23 08:11:10 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3353747756 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 246.prim_prince_test.3353747756
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/246.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/247.prim_prince_test.974539411
Short name T234
Test name
Test status
Simulation time 846875261 ps
CPU time 12.85 seconds
Started Aug 23 08:10:12 AM UTC 24
Finished Aug 23 08:10:29 AM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=974539411 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 247.prim_prince_test.974539411
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/247.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/248.prim_prince_test.776766405
Short name T264
Test name
Test status
Simulation time 3636579514 ps
CPU time 52.56 seconds
Started Aug 23 08:10:12 AM UTC 24
Finished Aug 23 08:11:19 AM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=776766405 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 248.prim_prince_test.776766405
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/248.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/249.prim_prince_test.967952844
Short name T249
Test name
Test status
Simulation time 2258830894 ps
CPU time 32.9 seconds
Started Aug 23 08:10:13 AM UTC 24
Finished Aug 23 08:10:55 AM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=967952844 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 249.prim_prince_test.967952844
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/249.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/25.prim_prince_test.4110591694
Short name T30
Test name
Test status
Simulation time 2712922811 ps
CPU time 40.15 seconds
Started Aug 23 08:02:10 AM UTC 24
Finished Aug 23 08:03:03 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4110591694 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 25.prim_prince_test.4110591694
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/25.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/250.prim_prince_test.3482671392
Short name T255
Test name
Test status
Simulation time 2565021451 ps
CPU time 37.92 seconds
Started Aug 23 08:10:15 AM UTC 24
Finished Aug 23 08:11:03 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3482671392 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 250.prim_prince_test.3482671392
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/250.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/251.prim_prince_test.315481608
Short name T254
Test name
Test status
Simulation time 2247354831 ps
CPU time 33.03 seconds
Started Aug 23 08:10:20 AM UTC 24
Finished Aug 23 08:11:02 AM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=315481608 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 251.prim_prince_test.315481608
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/251.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/252.prim_prince_test.3191928797
Short name T250
Test name
Test status
Simulation time 1745835600 ps
CPU time 25.82 seconds
Started Aug 23 08:10:22 AM UTC 24
Finished Aug 23 08:10:55 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3191928797 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 252.prim_prince_test.3191928797
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/252.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/253.prim_prince_test.770914917
Short name T261
Test name
Test status
Simulation time 2663495825 ps
CPU time 39.03 seconds
Started Aug 23 08:10:22 AM UTC 24
Finished Aug 23 08:11:12 AM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=770914917 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 253.prim_prince_test.770914917
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/253.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/254.prim_prince_test.3135437967
Short name T263
Test name
Test status
Simulation time 2848781945 ps
CPU time 41.47 seconds
Started Aug 23 08:10:24 AM UTC 24
Finished Aug 23 08:11:17 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3135437967 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 254.prim_prince_test.3135437967
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/254.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/255.prim_prince_test.745554769
Short name T245
Test name
Test status
Simulation time 1145184578 ps
CPU time 16.66 seconds
Started Aug 23 08:10:26 AM UTC 24
Finished Aug 23 08:10:48 AM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=745554769 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 255.prim_prince_test.745554769
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/255.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/256.prim_prince_test.77957187
Short name T247
Test name
Test status
Simulation time 1227916877 ps
CPU time 17.67 seconds
Started Aug 23 08:10:27 AM UTC 24
Finished Aug 23 08:10:50 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=77957187 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 256.prim_prince_test.77957187
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/256.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/257.prim_prince_test.3108930479
Short name T248
Test name
Test status
Simulation time 1349168824 ps
CPU time 19.64 seconds
Started Aug 23 08:10:29 AM UTC 24
Finished Aug 23 08:10:54 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3108930479 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 257.prim_prince_test.3108930479
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/257.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/258.prim_prince_test.1007013006
Short name T269
Test name
Test status
Simulation time 2918281160 ps
CPU time 42.56 seconds
Started Aug 23 08:10:29 AM UTC 24
Finished Aug 23 08:11:23 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1007013006 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 258.prim_prince_test.1007013006
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/258.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/259.prim_prince_test.235126963
Short name T258
Test name
Test status
Simulation time 1941780067 ps
CPU time 28.37 seconds
Started Aug 23 08:10:30 AM UTC 24
Finished Aug 23 08:11:07 AM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=235126963 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 259.prim_prince_test.235126963
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/259.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/26.prim_prince_test.590416058
Short name T22
Test name
Test status
Simulation time 1349470635 ps
CPU time 19.58 seconds
Started Aug 23 08:02:15 AM UTC 24
Finished Aug 23 08:02:41 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=590416058 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 26.prim_prince_test.590416058
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/26.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/260.prim_prince_test.909830957
Short name T280
Test name
Test status
Simulation time 3685314714 ps
CPU time 54.19 seconds
Started Aug 23 08:10:31 AM UTC 24
Finished Aug 23 08:11:40 AM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=909830957 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 260.prim_prince_test.909830957
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/260.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/261.prim_prince_test.194257836
Short name T246
Test name
Test status
Simulation time 811308974 ps
CPU time 12.55 seconds
Started Aug 23 08:10:31 AM UTC 24
Finished Aug 23 08:10:48 AM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=194257836 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 261.prim_prince_test.194257836
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/261.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/262.prim_prince_test.138675666
Short name T279
Test name
Test status
Simulation time 3353311049 ps
CPU time 49.5 seconds
Started Aug 23 08:10:35 AM UTC 24
Finished Aug 23 08:11:38 AM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=138675666 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 262.prim_prince_test.138675666
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/262.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/263.prim_prince_test.3875797080
Short name T268
Test name
Test status
Simulation time 2541599417 ps
CPU time 37.15 seconds
Started Aug 23 08:10:35 AM UTC 24
Finished Aug 23 08:11:23 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3875797080 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 263.prim_prince_test.3875797080
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/263.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/264.prim_prince_test.3837621158
Short name T273
Test name
Test status
Simulation time 2695908036 ps
CPU time 39.53 seconds
Started Aug 23 08:10:38 AM UTC 24
Finished Aug 23 08:11:29 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3837621158 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 264.prim_prince_test.3837621158
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/264.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/265.prim_prince_test.184908599
Short name T252
Test name
Test status
Simulation time 909099928 ps
CPU time 13.31 seconds
Started Aug 23 08:10:40 AM UTC 24
Finished Aug 23 08:10:57 AM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=184908599 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 265.prim_prince_test.184908599
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/265.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/266.prim_prince_test.1430496302
Short name T253
Test name
Test status
Simulation time 1033359874 ps
CPU time 15.85 seconds
Started Aug 23 08:10:40 AM UTC 24
Finished Aug 23 08:11:00 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1430496302 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 266.prim_prince_test.1430496302
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/266.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/267.prim_prince_test.432594031
Short name T284
Test name
Test status
Simulation time 3611743230 ps
CPU time 52.98 seconds
Started Aug 23 08:10:40 AM UTC 24
Finished Aug 23 08:11:47 AM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=432594031 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 267.prim_prince_test.432594031
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/267.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/268.prim_prince_test.2247780725
Short name T287
Test name
Test status
Simulation time 3682709387 ps
CPU time 54.55 seconds
Started Aug 23 08:10:41 AM UTC 24
Finished Aug 23 08:11:50 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2247780725 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 268.prim_prince_test.2247780725
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/268.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/269.prim_prince_test.216069484
Short name T275
Test name
Test status
Simulation time 2912308760 ps
CPU time 42.56 seconds
Started Aug 23 08:10:41 AM UTC 24
Finished Aug 23 08:11:35 AM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=216069484 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 269.prim_prince_test.216069484
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/269.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/27.prim_prince_test.1269608809
Short name T18
Test name
Test status
Simulation time 875267344 ps
CPU time 13.41 seconds
Started Aug 23 08:02:18 AM UTC 24
Finished Aug 23 08:02:36 AM UTC 24
Peak memory 154348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1269608809 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 27.prim_prince_test.1269608809
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/27.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/270.prim_prince_test.1441647647
Short name T256
Test name
Test status
Simulation time 1099835167 ps
CPU time 16.35 seconds
Started Aug 23 08:10:43 AM UTC 24
Finished Aug 23 08:11:05 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1441647647 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 270.prim_prince_test.1441647647
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/270.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/271.prim_prince_test.978369561
Short name T271
Test name
Test status
Simulation time 2111543380 ps
CPU time 30.71 seconds
Started Aug 23 08:10:48 AM UTC 24
Finished Aug 23 08:11:28 AM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=978369561 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 271.prim_prince_test.978369561
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/271.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/272.prim_prince_test.3333812144
Short name T288
Test name
Test status
Simulation time 3378488239 ps
CPU time 49.36 seconds
Started Aug 23 08:10:48 AM UTC 24
Finished Aug 23 08:11:51 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3333812144 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 272.prim_prince_test.3333812144
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/272.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/273.prim_prince_test.3395237274
Short name T262
Test name
Test status
Simulation time 1111313887 ps
CPU time 16.7 seconds
Started Aug 23 08:10:51 AM UTC 24
Finished Aug 23 08:11:12 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3395237274 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 273.prim_prince_test.3395237274
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/273.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/274.prim_prince_test.3290451009
Short name T278
Test name
Test status
Simulation time 2250353036 ps
CPU time 33.06 seconds
Started Aug 23 08:10:56 AM UTC 24
Finished Aug 23 08:11:38 AM UTC 24
Peak memory 154532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3290451009 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 274.prim_prince_test.3290451009
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/274.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/275.prim_prince_test.1365384611
Short name T293
Test name
Test status
Simulation time 3343962707 ps
CPU time 49.46 seconds
Started Aug 23 08:10:56 AM UTC 24
Finished Aug 23 08:11:58 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1365384611 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 275.prim_prince_test.1365384611
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/275.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/276.prim_prince_test.1999113615
Short name T282
Test name
Test status
Simulation time 2673409711 ps
CPU time 39.52 seconds
Started Aug 23 08:10:56 AM UTC 24
Finished Aug 23 08:11:46 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1999113615 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 276.prim_prince_test.1999113615
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/276.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/277.prim_prince_test.1192951219
Short name T276
Test name
Test status
Simulation time 2010782312 ps
CPU time 29.69 seconds
Started Aug 23 08:10:58 AM UTC 24
Finished Aug 23 08:11:36 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1192951219 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 277.prim_prince_test.1192951219
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/277.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/278.prim_prince_test.518962577
Short name T266
Test name
Test status
Simulation time 1175334308 ps
CPU time 17.28 seconds
Started Aug 23 08:10:58 AM UTC 24
Finished Aug 23 08:11:21 AM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=518962577 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 278.prim_prince_test.518962577
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/278.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/279.prim_prince_test.1596816840
Short name T265
Test name
Test status
Simulation time 945102531 ps
CPU time 14.07 seconds
Started Aug 23 08:11:01 AM UTC 24
Finished Aug 23 08:11:19 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1596816840 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 279.prim_prince_test.1596816840
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/279.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/28.prim_prince_test.4184121740
Short name T26
Test name
Test status
Simulation time 1627041503 ps
CPU time 23.71 seconds
Started Aug 23 08:02:22 AM UTC 24
Finished Aug 23 08:02:53 AM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4184121740 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 28.prim_prince_test.4184121740
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/28.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/280.prim_prince_test.690534153
Short name T270
Test name
Test status
Simulation time 1064737421 ps
CPU time 16.19 seconds
Started Aug 23 08:11:03 AM UTC 24
Finished Aug 23 08:11:25 AM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=690534153 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 280.prim_prince_test.690534153
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/280.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/281.prim_prince_test.2898382943
Short name T299
Test name
Test status
Simulation time 3720473634 ps
CPU time 53.85 seconds
Started Aug 23 08:11:04 AM UTC 24
Finished Aug 23 08:12:13 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2898382943 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 281.prim_prince_test.2898382943
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/281.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/282.prim_prince_test.112034567
Short name T274
Test name
Test status
Simulation time 1248960837 ps
CPU time 18.39 seconds
Started Aug 23 08:11:05 AM UTC 24
Finished Aug 23 08:11:29 AM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=112034567 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 282.prim_prince_test.112034567
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/282.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/283.prim_prince_test.2229314870
Short name T286
Test name
Test status
Simulation time 2217065390 ps
CPU time 32.68 seconds
Started Aug 23 08:11:07 AM UTC 24
Finished Aug 23 08:11:48 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2229314870 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 283.prim_prince_test.2229314870
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/283.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/284.prim_prince_test.3136713850
Short name T272
Test name
Test status
Simulation time 1084899160 ps
CPU time 16.12 seconds
Started Aug 23 08:11:08 AM UTC 24
Finished Aug 23 08:11:28 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3136713850 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 284.prim_prince_test.3136713850
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/284.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/285.prim_prince_test.3934424109
Short name T283
Test name
Test status
Simulation time 1910502374 ps
CPU time 28.15 seconds
Started Aug 23 08:11:10 AM UTC 24
Finished Aug 23 08:11:46 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3934424109 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 285.prim_prince_test.3934424109
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/285.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/286.prim_prince_test.3084219932
Short name T290
Test name
Test status
Simulation time 2342292275 ps
CPU time 35.02 seconds
Started Aug 23 08:11:11 AM UTC 24
Finished Aug 23 08:11:55 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3084219932 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 286.prim_prince_test.3084219932
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/286.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/287.prim_prince_test.1080814035
Short name T291
Test name
Test status
Simulation time 2258426326 ps
CPU time 33.56 seconds
Started Aug 23 08:11:13 AM UTC 24
Finished Aug 23 08:11:55 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1080814035 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 287.prim_prince_test.1080814035
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/287.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/288.prim_prince_test.693162447
Short name T277
Test name
Test status
Simulation time 1187155444 ps
CPU time 17.8 seconds
Started Aug 23 08:11:13 AM UTC 24
Finished Aug 23 08:11:36 AM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=693162447 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 288.prim_prince_test.693162447
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/288.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/289.prim_prince_test.1641616806
Short name T308
Test name
Test status
Simulation time 3428465606 ps
CPU time 49.63 seconds
Started Aug 23 08:11:18 AM UTC 24
Finished Aug 23 08:12:21 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1641616806 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 289.prim_prince_test.1641616806
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/289.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/29.prim_prince_test.739075395
Short name T35
Test name
Test status
Simulation time 2987333641 ps
CPU time 44.45 seconds
Started Aug 23 08:02:23 AM UTC 24
Finished Aug 23 08:03:21 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=739075395 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 29.prim_prince_test.739075395
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/29.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/290.prim_prince_test.4148611710
Short name T289
Test name
Test status
Simulation time 1857558561 ps
CPU time 26.92 seconds
Started Aug 23 08:11:19 AM UTC 24
Finished Aug 23 08:11:54 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4148611710 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 290.prim_prince_test.4148611710
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/290.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/291.prim_prince_test.3741517808
Short name T300
Test name
Test status
Simulation time 2856321928 ps
CPU time 41.83 seconds
Started Aug 23 08:11:20 AM UTC 24
Finished Aug 23 08:12:14 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3741517808 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 291.prim_prince_test.3741517808
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/291.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/292.prim_prince_test.3521106018
Short name T311
Test name
Test status
Simulation time 3702169933 ps
CPU time 55.15 seconds
Started Aug 23 08:11:21 AM UTC 24
Finished Aug 23 08:12:31 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3521106018 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 292.prim_prince_test.3521106018
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/292.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/293.prim_prince_test.2470132028
Short name T281
Test name
Test status
Simulation time 954533346 ps
CPU time 14.6 seconds
Started Aug 23 08:11:24 AM UTC 24
Finished Aug 23 08:11:43 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2470132028 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 293.prim_prince_test.2470132028
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/293.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/294.prim_prince_test.2102256149
Short name T313
Test name
Test status
Simulation time 3657688498 ps
CPU time 54.21 seconds
Started Aug 23 08:11:24 AM UTC 24
Finished Aug 23 08:12:32 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2102256149 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 294.prim_prince_test.2102256149
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/294.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/295.prim_prince_test.1893876276
Short name T295
Test name
Test status
Simulation time 1907475575 ps
CPU time 28.24 seconds
Started Aug 23 08:11:26 AM UTC 24
Finished Aug 23 08:12:02 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1893876276 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 295.prim_prince_test.1893876276
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/295.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/296.prim_prince_test.1797722668
Short name T314
Test name
Test status
Simulation time 3548438881 ps
CPU time 52.01 seconds
Started Aug 23 08:11:29 AM UTC 24
Finished Aug 23 08:12:35 AM UTC 24
Peak memory 154440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1797722668 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 296.prim_prince_test.1797722668
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/296.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/297.prim_prince_test.2754127964
Short name T298
Test name
Test status
Simulation time 2314617715 ps
CPU time 33.93 seconds
Started Aug 23 08:11:29 AM UTC 24
Finished Aug 23 08:12:12 AM UTC 24
Peak memory 154412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2754127964 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 297.prim_prince_test.2754127964
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/297.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/298.prim_prince_test.1303574966
Short name T285
Test name
Test status
Simulation time 922192865 ps
CPU time 13.57 seconds
Started Aug 23 08:11:30 AM UTC 24
Finished Aug 23 08:11:48 AM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1303574966 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 298.prim_prince_test.1303574966
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/298.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/299.prim_prince_test.3092769041
Short name T302
Test name
Test status
Simulation time 2422938906 ps
CPU time 36.57 seconds
Started Aug 23 08:11:30 AM UTC 24
Finished Aug 23 08:12:16 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3092769041 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 299.prim_prince_test.3092769041
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/299.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/3.prim_prince_test.1428927664
Short name T8
Test name
Test status
Simulation time 2484564721 ps
CPU time 35.49 seconds
Started Aug 23 08:01:08 AM UTC 24
Finished Aug 23 08:01:55 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1428927664 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 3.prim_prince_test.1428927664
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/3.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/30.prim_prince_test.489539485
Short name T32
Test name
Test status
Simulation time 2139880701 ps
CPU time 31.62 seconds
Started Aug 23 08:02:23 AM UTC 24
Finished Aug 23 08:03:05 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=489539485 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 30.prim_prince_test.489539485
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/30.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/300.prim_prince_test.4221752261
Short name T306
Test name
Test status
Simulation time 2203632019 ps
CPU time 33.13 seconds
Started Aug 23 08:11:36 AM UTC 24
Finished Aug 23 08:12:18 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4221752261 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 300.prim_prince_test.4221752261
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/300.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/301.prim_prince_test.2306228809
Short name T318
Test name
Test status
Simulation time 3744509706 ps
CPU time 53.52 seconds
Started Aug 23 08:11:36 AM UTC 24
Finished Aug 23 08:12:45 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2306228809 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 301.prim_prince_test.2306228809
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/301.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/302.prim_prince_test.4283421723
Short name T292
Test name
Test status
Simulation time 1011905101 ps
CPU time 15.27 seconds
Started Aug 23 08:11:36 AM UTC 24
Finished Aug 23 08:11:56 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4283421723 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 302.prim_prince_test.4283421723
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/302.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/303.prim_prince_test.4167329544
Short name T305
Test name
Test status
Simulation time 2126533623 ps
CPU time 30.92 seconds
Started Aug 23 08:11:39 AM UTC 24
Finished Aug 23 08:12:18 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4167329544 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 303.prim_prince_test.4167329544
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/303.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/304.prim_prince_test.906726228
Short name T297
Test name
Test status
Simulation time 1456452586 ps
CPU time 21.44 seconds
Started Aug 23 08:11:39 AM UTC 24
Finished Aug 23 08:12:06 AM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=906726228 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 304.prim_prince_test.906726228
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/304.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/305.prim_prince_test.1427224904
Short name T296
Test name
Test status
Simulation time 1303536899 ps
CPU time 19.08 seconds
Started Aug 23 08:11:41 AM UTC 24
Finished Aug 23 08:12:06 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1427224904 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 305.prim_prince_test.1427224904
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/305.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/306.prim_prince_test.937555783
Short name T294
Test name
Test status
Simulation time 804222894 ps
CPU time 12.19 seconds
Started Aug 23 08:11:44 AM UTC 24
Finished Aug 23 08:12:00 AM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=937555783 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 306.prim_prince_test.937555783
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/306.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/307.prim_prince_test.81473411
Short name T323
Test name
Test status
Simulation time 3370790604 ps
CPU time 49.61 seconds
Started Aug 23 08:11:47 AM UTC 24
Finished Aug 23 08:12:50 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=81473411 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 307.prim_prince_test.81473411
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/307.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/308.prim_prince_test.4061677372
Short name T312
Test name
Test status
Simulation time 2362458756 ps
CPU time 34.15 seconds
Started Aug 23 08:11:47 AM UTC 24
Finished Aug 23 08:12:31 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4061677372 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 308.prim_prince_test.4061677372
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/308.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/309.prim_prince_test.3162750469
Short name T301
Test name
Test status
Simulation time 1442515484 ps
CPU time 21.25 seconds
Started Aug 23 08:11:47 AM UTC 24
Finished Aug 23 08:12:15 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3162750469 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 309.prim_prince_test.3162750469
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/309.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/31.prim_prince_test.1656683023
Short name T29
Test name
Test status
Simulation time 1899035770 ps
CPU time 27.53 seconds
Started Aug 23 08:02:26 AM UTC 24
Finished Aug 23 08:03:02 AM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1656683023 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 31.prim_prince_test.1656683023
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/31.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/310.prim_prince_test.2288170749
Short name T309
Test name
Test status
Simulation time 1794498730 ps
CPU time 26.78 seconds
Started Aug 23 08:11:49 AM UTC 24
Finished Aug 23 08:12:24 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2288170749 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 310.prim_prince_test.2288170749
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/310.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/311.prim_prince_test.3433160122
Short name T303
Test name
Test status
Simulation time 1413675521 ps
CPU time 20.91 seconds
Started Aug 23 08:11:49 AM UTC 24
Finished Aug 23 08:12:16 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3433160122 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 311.prim_prince_test.3433160122
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/311.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/312.prim_prince_test.1058151844
Short name T327
Test name
Test status
Simulation time 3302610233 ps
CPU time 47.97 seconds
Started Aug 23 08:11:51 AM UTC 24
Finished Aug 23 08:12:52 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1058151844 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 312.prim_prince_test.1058151844
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/312.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/313.prim_prince_test.1417777083
Short name T310
Test name
Test status
Simulation time 1697735962 ps
CPU time 25.33 seconds
Started Aug 23 08:11:52 AM UTC 24
Finished Aug 23 08:12:24 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1417777083 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 313.prim_prince_test.1417777083
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/313.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/314.prim_prince_test.909368477
Short name T304
Test name
Test status
Simulation time 1157664005 ps
CPU time 16.98 seconds
Started Aug 23 08:11:55 AM UTC 24
Finished Aug 23 08:12:17 AM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=909368477 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 314.prim_prince_test.909368477
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/314.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/315.prim_prince_test.1307246097
Short name T319
Test name
Test status
Simulation time 2578233964 ps
CPU time 38.91 seconds
Started Aug 23 08:11:56 AM UTC 24
Finished Aug 23 08:12:45 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1307246097 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 315.prim_prince_test.1307246097
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/315.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/316.prim_prince_test.601138668
Short name T307
Test name
Test status
Simulation time 1214193860 ps
CPU time 18.27 seconds
Started Aug 23 08:11:56 AM UTC 24
Finished Aug 23 08:12:20 AM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=601138668 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 316.prim_prince_test.601138668
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/316.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/317.prim_prince_test.101172493
Short name T320
Test name
Test status
Simulation time 2643658224 ps
CPU time 39.67 seconds
Started Aug 23 08:11:57 AM UTC 24
Finished Aug 23 08:12:47 AM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=101172493 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 317.prim_prince_test.101172493
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/317.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/318.prim_prince_test.2804149182
Short name T322
Test name
Test status
Simulation time 2701577833 ps
CPU time 39.09 seconds
Started Aug 23 08:11:59 AM UTC 24
Finished Aug 23 08:12:49 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2804149182 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 318.prim_prince_test.2804149182
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/318.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/319.prim_prince_test.3597666259
Short name T331
Test name
Test status
Simulation time 3321965523 ps
CPU time 48.9 seconds
Started Aug 23 08:12:00 AM UTC 24
Finished Aug 23 08:13:02 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3597666259 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 319.prim_prince_test.3597666259
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/319.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/32.prim_prince_test.2956750418
Short name T40
Test name
Test status
Simulation time 2834878983 ps
CPU time 41.67 seconds
Started Aug 23 08:02:35 AM UTC 24
Finished Aug 23 08:03:30 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2956750418 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 32.prim_prince_test.2956750418
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/32.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/320.prim_prince_test.1212649932
Short name T328
Test name
Test status
Simulation time 2608978560 ps
CPU time 38.81 seconds
Started Aug 23 08:12:02 AM UTC 24
Finished Aug 23 08:12:52 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1212649932 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 320.prim_prince_test.1212649932
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/320.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/321.prim_prince_test.3085766183
Short name T339
Test name
Test status
Simulation time 3744586358 ps
CPU time 55.16 seconds
Started Aug 23 08:12:07 AM UTC 24
Finished Aug 23 08:13:17 AM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3085766183 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 321.prim_prince_test.3085766183
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/321.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/322.prim_prince_test.2536200297
Short name T321
Test name
Test status
Simulation time 2104833387 ps
CPU time 30.55 seconds
Started Aug 23 08:12:08 AM UTC 24
Finished Aug 23 08:12:47 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2536200297 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 322.prim_prince_test.2536200297
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/322.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/323.prim_prince_test.1883616763
Short name T340
Test name
Test status
Simulation time 3501201649 ps
CPU time 51.18 seconds
Started Aug 23 08:12:13 AM UTC 24
Finished Aug 23 08:13:18 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1883616763 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 323.prim_prince_test.1883616763
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/323.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/324.prim_prince_test.2660686620
Short name T324
Test name
Test status
Simulation time 1901256867 ps
CPU time 28.43 seconds
Started Aug 23 08:12:14 AM UTC 24
Finished Aug 23 08:12:50 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2660686620 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 324.prim_prince_test.2660686620
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/324.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/325.prim_prince_test.191311817
Short name T317
Test name
Test status
Simulation time 1410541638 ps
CPU time 21.18 seconds
Started Aug 23 08:12:14 AM UTC 24
Finished Aug 23 08:12:41 AM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=191311817 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 325.prim_prince_test.191311817
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/325.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/326.prim_prince_test.3473688001
Short name T315
Test name
Test status
Simulation time 1096947335 ps
CPU time 16.14 seconds
Started Aug 23 08:12:15 AM UTC 24
Finished Aug 23 08:12:36 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3473688001 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 326.prim_prince_test.3473688001
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/326.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/327.prim_prince_test.402298964
Short name T334
Test name
Test status
Simulation time 2851889593 ps
CPU time 42 seconds
Started Aug 23 08:12:17 AM UTC 24
Finished Aug 23 08:13:11 AM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=402298964 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 327.prim_prince_test.402298964
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/327.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/328.prim_prince_test.662833495
Short name T326
Test name
Test status
Simulation time 1802760733 ps
CPU time 26.52 seconds
Started Aug 23 08:12:17 AM UTC 24
Finished Aug 23 08:12:51 AM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=662833495 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 328.prim_prince_test.662833495
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/328.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/329.prim_prince_test.3713380242
Short name T330
Test name
Test status
Simulation time 2198619150 ps
CPU time 32.12 seconds
Started Aug 23 08:12:17 AM UTC 24
Finished Aug 23 08:12:59 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3713380242 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 329.prim_prince_test.3713380242
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/329.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/33.prim_prince_test.3167184586
Short name T39
Test name
Test status
Simulation time 2757884786 ps
CPU time 40.12 seconds
Started Aug 23 08:02:37 AM UTC 24
Finished Aug 23 08:03:29 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3167184586 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 33.prim_prince_test.3167184586
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/33.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/330.prim_prince_test.3615685050
Short name T332
Test name
Test status
Simulation time 2591713896 ps
CPU time 38.4 seconds
Started Aug 23 08:12:19 AM UTC 24
Finished Aug 23 08:13:08 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3615685050 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 330.prim_prince_test.3615685050
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/330.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/331.prim_prince_test.1163188678
Short name T316
Test name
Test status
Simulation time 1030714496 ps
CPU time 15.26 seconds
Started Aug 23 08:12:20 AM UTC 24
Finished Aug 23 08:12:40 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1163188678 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 331.prim_prince_test.1163188678
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/331.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/332.prim_prince_test.1139163515
Short name T348
Test name
Test status
Simulation time 3570645829 ps
CPU time 52.58 seconds
Started Aug 23 08:12:21 AM UTC 24
Finished Aug 23 08:13:28 AM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1139163515 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 332.prim_prince_test.1139163515
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/332.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/333.prim_prince_test.92031558
Short name T267
Test name
Test status
Simulation time 2820508217 ps
CPU time 41.11 seconds
Started Aug 23 08:12:22 AM UTC 24
Finished Aug 23 08:13:15 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=92031558 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 333.prim_prince_test.92031558
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/333.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/334.prim_prince_test.1951105836
Short name T337
Test name
Test status
Simulation time 2716136536 ps
CPU time 40.17 seconds
Started Aug 23 08:12:24 AM UTC 24
Finished Aug 23 08:13:15 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1951105836 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 334.prim_prince_test.1951105836
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/334.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/335.prim_prince_test.2867325382
Short name T335
Test name
Test status
Simulation time 2440787014 ps
CPU time 36.44 seconds
Started Aug 23 08:12:25 AM UTC 24
Finished Aug 23 08:13:12 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2867325382 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 335.prim_prince_test.2867325382
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/335.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/336.prim_prince_test.2917525682
Short name T351
Test name
Test status
Simulation time 3238684654 ps
CPU time 47.93 seconds
Started Aug 23 08:12:31 AM UTC 24
Finished Aug 23 08:13:33 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2917525682 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 336.prim_prince_test.2917525682
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/336.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/337.prim_prince_test.2422843014
Short name T352
Test name
Test status
Simulation time 3480917565 ps
CPU time 50.91 seconds
Started Aug 23 08:12:31 AM UTC 24
Finished Aug 23 08:13:36 AM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2422843014 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 337.prim_prince_test.2422843014
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/337.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/338.prim_prince_test.4057183404
Short name T329
Test name
Test status
Simulation time 1335183834 ps
CPU time 19.91 seconds
Started Aug 23 08:12:33 AM UTC 24
Finished Aug 23 08:12:58 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4057183404 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 338.prim_prince_test.4057183404
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/338.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/339.prim_prince_test.2542758017
Short name T325
Test name
Test status
Simulation time 770125443 ps
CPU time 11.13 seconds
Started Aug 23 08:12:36 AM UTC 24
Finished Aug 23 08:12:51 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2542758017 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 339.prim_prince_test.2542758017
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/339.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/34.prim_prince_test.3537633720
Short name T42
Test name
Test status
Simulation time 2922074035 ps
CPU time 42.17 seconds
Started Aug 23 08:02:37 AM UTC 24
Finished Aug 23 08:03:32 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3537633720 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 34.prim_prince_test.3537633720
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/34.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/340.prim_prince_test.535140575
Short name T345
Test name
Test status
Simulation time 2340810867 ps
CPU time 35.07 seconds
Started Aug 23 08:12:37 AM UTC 24
Finished Aug 23 08:13:23 AM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=535140575 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 340.prim_prince_test.535140575
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/340.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/341.prim_prince_test.341991048
Short name T361
Test name
Test status
Simulation time 3614353192 ps
CPU time 52.59 seconds
Started Aug 23 08:12:41 AM UTC 24
Finished Aug 23 08:13:48 AM UTC 24
Peak memory 154676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=341991048 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 341.prim_prince_test.341991048
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/341.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/342.prim_prince_test.1806300505
Short name T338
Test name
Test status
Simulation time 1724866480 ps
CPU time 25.99 seconds
Started Aug 23 08:12:42 AM UTC 24
Finished Aug 23 08:13:16 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1806300505 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 342.prim_prince_test.1806300505
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/342.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/343.prim_prince_test.174207354
Short name T349
Test name
Test status
Simulation time 2400463797 ps
CPU time 35.46 seconds
Started Aug 23 08:12:45 AM UTC 24
Finished Aug 23 08:13:30 AM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=174207354 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 343.prim_prince_test.174207354
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/343.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/344.prim_prince_test.2783811735
Short name T346
Test name
Test status
Simulation time 1932937882 ps
CPU time 29.24 seconds
Started Aug 23 08:12:46 AM UTC 24
Finished Aug 23 08:13:24 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2783811735 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 344.prim_prince_test.2783811735
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/344.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/345.prim_prince_test.1197161670
Short name T341
Test name
Test status
Simulation time 1556366854 ps
CPU time 23.02 seconds
Started Aug 23 08:12:49 AM UTC 24
Finished Aug 23 08:13:19 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1197161670 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 345.prim_prince_test.1197161670
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/345.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/346.prim_prince_test.3327665238
Short name T358
Test name
Test status
Simulation time 3043974019 ps
CPU time 44.49 seconds
Started Aug 23 08:12:49 AM UTC 24
Finished Aug 23 08:13:46 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3327665238 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 346.prim_prince_test.3327665238
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/346.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/347.prim_prince_test.1822026510
Short name T344
Test name
Test status
Simulation time 1641355156 ps
CPU time 24.58 seconds
Started Aug 23 08:12:50 AM UTC 24
Finished Aug 23 08:13:22 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1822026510 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 347.prim_prince_test.1822026510
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/347.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/348.prim_prince_test.661243238
Short name T333
Test name
Test status
Simulation time 862097177 ps
CPU time 13.22 seconds
Started Aug 23 08:12:51 AM UTC 24
Finished Aug 23 08:13:08 AM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=661243238 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 348.prim_prince_test.661243238
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/348.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/349.prim_prince_test.1445038236
Short name T347
Test name
Test status
Simulation time 1728898494 ps
CPU time 26.17 seconds
Started Aug 23 08:12:51 AM UTC 24
Finished Aug 23 08:13:24 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1445038236 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 349.prim_prince_test.1445038236
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/349.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/35.prim_prince_test.4153944245
Short name T34
Test name
Test status
Simulation time 1789819793 ps
CPU time 26.06 seconds
Started Aug 23 08:02:39 AM UTC 24
Finished Aug 23 08:03:13 AM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4153944245 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 35.prim_prince_test.4153944245
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/35.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/350.prim_prince_test.2793883542
Short name T336
Test name
Test status
Simulation time 1125159273 ps
CPU time 16.57 seconds
Started Aug 23 08:12:52 AM UTC 24
Finished Aug 23 08:13:14 AM UTC 24
Peak memory 154536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2793883542 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 350.prim_prince_test.2793883542
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/350.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/351.prim_prince_test.996337545
Short name T362
Test name
Test status
Simulation time 3025418037 ps
CPU time 44.65 seconds
Started Aug 23 08:12:52 AM UTC 24
Finished Aug 23 08:13:49 AM UTC 24
Peak memory 154624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=996337545 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 351.prim_prince_test.996337545
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/351.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/352.prim_prince_test.779609171
Short name T343
Test name
Test status
Simulation time 1443708487 ps
CPU time 21.89 seconds
Started Aug 23 08:12:52 AM UTC 24
Finished Aug 23 08:13:21 AM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=779609171 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 352.prim_prince_test.779609171
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/352.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/353.prim_prince_test.186991769
Short name T359
Test name
Test status
Simulation time 2794018827 ps
CPU time 40.79 seconds
Started Aug 23 08:12:53 AM UTC 24
Finished Aug 23 08:13:46 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=186991769 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 353.prim_prince_test.186991769
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/353.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/354.prim_prince_test.99697450
Short name T371
Test name
Test status
Simulation time 3578468295 ps
CPU time 52.17 seconds
Started Aug 23 08:13:00 AM UTC 24
Finished Aug 23 08:14:06 AM UTC 24
Peak memory 156532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=99697450 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 354.prim_prince_test.99697450
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/354.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/355.prim_prince_test.663478469
Short name T342
Test name
Test status
Simulation time 969491086 ps
CPU time 14.6 seconds
Started Aug 23 08:13:00 AM UTC 24
Finished Aug 23 08:13:19 AM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=663478469 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 355.prim_prince_test.663478469
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/355.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/356.prim_prince_test.2796071305
Short name T354
Test name
Test status
Simulation time 1814793211 ps
CPU time 26.62 seconds
Started Aug 23 08:13:03 AM UTC 24
Finished Aug 23 08:13:37 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2796071305 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 356.prim_prince_test.2796071305
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/356.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/357.prim_prince_test.1812221223
Short name T356
Test name
Test status
Simulation time 1636780200 ps
CPU time 24.87 seconds
Started Aug 23 08:13:09 AM UTC 24
Finished Aug 23 08:13:41 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1812221223 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 357.prim_prince_test.1812221223
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/357.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/358.prim_prince_test.2061001204
Short name T373
Test name
Test status
Simulation time 3142545256 ps
CPU time 45.26 seconds
Started Aug 23 08:13:09 AM UTC 24
Finished Aug 23 08:14:07 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2061001204 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 358.prim_prince_test.2061001204
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/358.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/359.prim_prince_test.3294168803
Short name T355
Test name
Test status
Simulation time 1428126128 ps
CPU time 21.08 seconds
Started Aug 23 08:13:11 AM UTC 24
Finished Aug 23 08:13:39 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3294168803 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 359.prim_prince_test.3294168803
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/359.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/36.prim_prince_test.1362091165
Short name T44
Test name
Test status
Simulation time 3184279748 ps
CPU time 45.44 seconds
Started Aug 23 08:02:40 AM UTC 24
Finished Aug 23 08:03:39 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1362091165 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 36.prim_prince_test.1362091165
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/36.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/360.prim_prince_test.3135169900
Short name T364
Test name
Test status
Simulation time 2070630269 ps
CPU time 30.51 seconds
Started Aug 23 08:13:13 AM UTC 24
Finished Aug 23 08:13:52 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3135169900 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 360.prim_prince_test.3135169900
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/360.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/361.prim_prince_test.2806564827
Short name T350
Test name
Test status
Simulation time 866413199 ps
CPU time 12.79 seconds
Started Aug 23 08:13:15 AM UTC 24
Finished Aug 23 08:13:31 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2806564827 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 361.prim_prince_test.2806564827
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/361.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/362.prim_prince_test.97698047
Short name T381
Test name
Test status
Simulation time 3325984963 ps
CPU time 48.79 seconds
Started Aug 23 08:13:16 AM UTC 24
Finished Aug 23 08:14:17 AM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=97698047 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 362.prim_prince_test.97698047
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/362.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/363.prim_prince_test.1538722616
Short name T376
Test name
Test status
Simulation time 2914330787 ps
CPU time 42.82 seconds
Started Aug 23 08:13:16 AM UTC 24
Finished Aug 23 08:14:10 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1538722616 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 363.prim_prince_test.1538722616
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/363.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/364.prim_prince_test.2808652782
Short name T375
Test name
Test status
Simulation time 2853810565 ps
CPU time 41.73 seconds
Started Aug 23 08:13:17 AM UTC 24
Finished Aug 23 08:14:10 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2808652782 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 364.prim_prince_test.2808652782
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/364.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/365.prim_prince_test.4269628408
Short name T363
Test name
Test status
Simulation time 1622308675 ps
CPU time 23.96 seconds
Started Aug 23 08:13:18 AM UTC 24
Finished Aug 23 08:13:49 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4269628408 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 365.prim_prince_test.4269628408
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/365.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/366.prim_prince_test.3362781641
Short name T353
Test name
Test status
Simulation time 884548140 ps
CPU time 12.99 seconds
Started Aug 23 08:13:19 AM UTC 24
Finished Aug 23 08:13:36 AM UTC 24
Peak memory 154228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3362781641 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 366.prim_prince_test.3362781641
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/366.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/367.prim_prince_test.3120473380
Short name T386
Test name
Test status
Simulation time 3528317575 ps
CPU time 52.34 seconds
Started Aug 23 08:13:19 AM UTC 24
Finished Aug 23 08:14:26 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3120473380 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 367.prim_prince_test.3120473380
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/367.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/368.prim_prince_test.171854498
Short name T369
Test name
Test status
Simulation time 2440391728 ps
CPU time 35.99 seconds
Started Aug 23 08:13:19 AM UTC 24
Finished Aug 23 08:14:05 AM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=171854498 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 368.prim_prince_test.171854498
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/368.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/369.prim_prince_test.3581443707
Short name T365
Test name
Test status
Simulation time 1851376482 ps
CPU time 26.85 seconds
Started Aug 23 08:13:22 AM UTC 24
Finished Aug 23 08:13:56 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3581443707 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 369.prim_prince_test.3581443707
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/369.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/37.prim_prince_test.378164321
Short name T28
Test name
Test status
Simulation time 936779328 ps
CPU time 14.73 seconds
Started Aug 23 08:02:42 AM UTC 24
Finished Aug 23 08:03:01 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=378164321 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 37.prim_prince_test.378164321
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/37.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/370.prim_prince_test.1846786075
Short name T366
Test name
Test status
Simulation time 2245703771 ps
CPU time 32.84 seconds
Started Aug 23 08:13:23 AM UTC 24
Finished Aug 23 08:14:05 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1846786075 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 370.prim_prince_test.1846786075
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/370.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/371.prim_prince_test.3900342567
Short name T384
Test name
Test status
Simulation time 3194674437 ps
CPU time 46.51 seconds
Started Aug 23 08:13:24 AM UTC 24
Finished Aug 23 08:14:23 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3900342567 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 371.prim_prince_test.3900342567
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/371.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/372.prim_prince_test.241456864
Short name T360
Test name
Test status
Simulation time 1103001427 ps
CPU time 16.38 seconds
Started Aug 23 08:13:25 AM UTC 24
Finished Aug 23 08:13:46 AM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=241456864 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 372.prim_prince_test.241456864
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/372.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/373.prim_prince_test.2034061170
Short name T357
Test name
Test status
Simulation time 894623940 ps
CPU time 13.33 seconds
Started Aug 23 08:13:25 AM UTC 24
Finished Aug 23 08:13:43 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2034061170 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 373.prim_prince_test.2034061170
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/373.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/374.prim_prince_test.148573081
Short name T370
Test name
Test status
Simulation time 2031551467 ps
CPU time 29.44 seconds
Started Aug 23 08:13:28 AM UTC 24
Finished Aug 23 08:14:06 AM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=148573081 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 374.prim_prince_test.148573081
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/374.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/375.prim_prince_test.2583423838
Short name T377
Test name
Test status
Simulation time 2114052816 ps
CPU time 31.09 seconds
Started Aug 23 08:13:31 AM UTC 24
Finished Aug 23 08:14:11 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2583423838 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 375.prim_prince_test.2583423838
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/375.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/376.prim_prince_test.2047184394
Short name T378
Test name
Test status
Simulation time 2245875257 ps
CPU time 32.49 seconds
Started Aug 23 08:13:32 AM UTC 24
Finished Aug 23 08:14:14 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2047184394 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 376.prim_prince_test.2047184394
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/376.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/377.prim_prince_test.2568554639
Short name T374
Test name
Test status
Simulation time 1806123461 ps
CPU time 27.07 seconds
Started Aug 23 08:13:34 AM UTC 24
Finished Aug 23 08:14:08 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2568554639 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 377.prim_prince_test.2568554639
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/377.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/378.prim_prince_test.1822479905
Short name T383
Test name
Test status
Simulation time 2183791558 ps
CPU time 32.35 seconds
Started Aug 23 08:13:37 AM UTC 24
Finished Aug 23 08:14:18 AM UTC 24
Peak memory 154648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1822479905 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 378.prim_prince_test.1822479905
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/378.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/379.prim_prince_test.3755620909
Short name T382
Test name
Test status
Simulation time 2138699089 ps
CPU time 32.08 seconds
Started Aug 23 08:13:37 AM UTC 24
Finished Aug 23 08:14:18 AM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3755620909 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 379.prim_prince_test.3755620909
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/379.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/38.prim_prince_test.1896071710
Short name T31
Test name
Test status
Simulation time 1111210740 ps
CPU time 16.74 seconds
Started Aug 23 08:02:42 AM UTC 24
Finished Aug 23 08:03:04 AM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1896071710 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 38.prim_prince_test.1896071710
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/38.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/380.prim_prince_test.472536475
Short name T388
Test name
Test status
Simulation time 2811110077 ps
CPU time 41.81 seconds
Started Aug 23 08:13:38 AM UTC 24
Finished Aug 23 08:14:31 AM UTC 24
Peak memory 154676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=472536475 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 380.prim_prince_test.472536475
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/380.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/381.prim_prince_test.3427478901
Short name T385
Test name
Test status
Simulation time 2326944468 ps
CPU time 34.48 seconds
Started Aug 23 08:13:39 AM UTC 24
Finished Aug 23 08:14:23 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3427478901 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 381.prim_prince_test.3427478901
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/381.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/382.prim_prince_test.1131109205
Short name T379
Test name
Test status
Simulation time 1752115142 ps
CPU time 25.52 seconds
Started Aug 23 08:13:42 AM UTC 24
Finished Aug 23 08:14:15 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1131109205 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 382.prim_prince_test.1131109205
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/382.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/383.prim_prince_test.2829899289
Short name T397
Test name
Test status
Simulation time 3619078515 ps
CPU time 52.85 seconds
Started Aug 23 08:13:43 AM UTC 24
Finished Aug 23 08:14:50 AM UTC 24
Peak memory 156532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2829899289 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 383.prim_prince_test.2829899289
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/383.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/384.prim_prince_test.3800427478
Short name T396
Test name
Test status
Simulation time 3438383730 ps
CPU time 49.82 seconds
Started Aug 23 08:13:47 AM UTC 24
Finished Aug 23 08:14:50 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3800427478 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 384.prim_prince_test.3800427478
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/384.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/385.prim_prince_test.1451216808
Short name T368
Test name
Test status
Simulation time 948617543 ps
CPU time 13.93 seconds
Started Aug 23 08:13:47 AM UTC 24
Finished Aug 23 08:14:05 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1451216808 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 385.prim_prince_test.1451216808
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/385.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/386.prim_prince_test.3163938949
Short name T372
Test name
Test status
Simulation time 928187138 ps
CPU time 14.27 seconds
Started Aug 23 08:13:48 AM UTC 24
Finished Aug 23 08:14:06 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3163938949 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 386.prim_prince_test.3163938949
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/386.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/387.prim_prince_test.4246290677
Short name T389
Test name
Test status
Simulation time 2253525099 ps
CPU time 33.57 seconds
Started Aug 23 08:13:49 AM UTC 24
Finished Aug 23 08:14:32 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4246290677 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 387.prim_prince_test.4246290677
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/387.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/388.prim_prince_test.2304808536
Short name T380
Test name
Test status
Simulation time 1331898270 ps
CPU time 19.99 seconds
Started Aug 23 08:13:50 AM UTC 24
Finished Aug 23 08:14:16 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2304808536 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 388.prim_prince_test.2304808536
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/388.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/389.prim_prince_test.1588937286
Short name T401
Test name
Test status
Simulation time 3563946257 ps
CPU time 53.09 seconds
Started Aug 23 08:13:50 AM UTC 24
Finished Aug 23 08:14:57 AM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1588937286 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 389.prim_prince_test.1588937286
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/389.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/39.prim_prince_test.2012680035
Short name T48
Test name
Test status
Simulation time 3328468323 ps
CPU time 48.56 seconds
Started Aug 23 08:02:47 AM UTC 24
Finished Aug 23 08:03:50 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2012680035 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 39.prim_prince_test.2012680035
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/39.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/390.prim_prince_test.417599803
Short name T398
Test name
Test status
Simulation time 3127648406 ps
CPU time 46.33 seconds
Started Aug 23 08:13:53 AM UTC 24
Finished Aug 23 08:14:52 AM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=417599803 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 390.prim_prince_test.417599803
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/390.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/391.prim_prince_test.1993525797
Short name T387
Test name
Test status
Simulation time 1823450414 ps
CPU time 26.66 seconds
Started Aug 23 08:13:56 AM UTC 24
Finished Aug 23 08:14:31 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1993525797 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 391.prim_prince_test.1993525797
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/391.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/392.prim_prince_test.589858588
Short name T404
Test name
Test status
Simulation time 3001434471 ps
CPU time 44.28 seconds
Started Aug 23 08:14:04 AM UTC 24
Finished Aug 23 08:15:00 AM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=589858588 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 392.prim_prince_test.589858588
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/392.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/393.prim_prince_test.975434330
Short name T393
Test name
Test status
Simulation time 2066506070 ps
CPU time 30.81 seconds
Started Aug 23 08:14:06 AM UTC 24
Finished Aug 23 08:14:45 AM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=975434330 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 393.prim_prince_test.975434330
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/393.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/394.prim_prince_test.276703593
Short name T407
Test name
Test status
Simulation time 3027190860 ps
CPU time 44.44 seconds
Started Aug 23 08:14:06 AM UTC 24
Finished Aug 23 08:15:03 AM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=276703593 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 394.prim_prince_test.276703593
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/394.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/395.prim_prince_test.1116622916
Short name T403
Test name
Test status
Simulation time 2854649477 ps
CPU time 41.69 seconds
Started Aug 23 08:14:06 AM UTC 24
Finished Aug 23 08:14:59 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1116622916 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 395.prim_prince_test.1116622916
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/395.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/396.prim_prince_test.2545812860
Short name T411
Test name
Test status
Simulation time 3231898816 ps
CPU time 47.43 seconds
Started Aug 23 08:14:07 AM UTC 24
Finished Aug 23 08:15:08 AM UTC 24
Peak memory 156124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2545812860 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 396.prim_prince_test.2545812860
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/396.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/397.prim_prince_test.2664507009
Short name T405
Test name
Test status
Simulation time 2847009054 ps
CPU time 42.01 seconds
Started Aug 23 08:14:07 AM UTC 24
Finished Aug 23 08:15:01 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2664507009 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 397.prim_prince_test.2664507009
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/397.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/398.prim_prince_test.599837488
Short name T394
Test name
Test status
Simulation time 2025733810 ps
CPU time 30.06 seconds
Started Aug 23 08:14:07 AM UTC 24
Finished Aug 23 08:14:46 AM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=599837488 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 398.prim_prince_test.599837488
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/398.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/399.prim_prince_test.3759505815
Short name T395
Test name
Test status
Simulation time 2133910530 ps
CPU time 31.58 seconds
Started Aug 23 08:14:09 AM UTC 24
Finished Aug 23 08:14:49 AM UTC 24
Peak memory 154456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3759505815 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 399.prim_prince_test.3759505815
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/399.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/4.prim_prince_test.3622448589
Short name T12
Test name
Test status
Simulation time 3212139245 ps
CPU time 45.93 seconds
Started Aug 23 08:01:08 AM UTC 24
Finished Aug 23 08:02:08 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3622448589 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 4.prim_prince_test.3622448589
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/4.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/40.prim_prince_test.395773033
Short name T37
Test name
Test status
Simulation time 1681797716 ps
CPU time 24.64 seconds
Started Aug 23 08:02:53 AM UTC 24
Finished Aug 23 08:03:25 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=395773033 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 40.prim_prince_test.395773033
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/40.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/400.prim_prince_test.1575247246
Short name T412
Test name
Test status
Simulation time 3197098966 ps
CPU time 47.14 seconds
Started Aug 23 08:14:09 AM UTC 24
Finished Aug 23 08:15:08 AM UTC 24
Peak memory 154464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1575247246 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 400.prim_prince_test.1575247246
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/400.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/401.prim_prince_test.1713130426
Short name T390
Test name
Test status
Simulation time 1431694899 ps
CPU time 21.08 seconds
Started Aug 23 08:14:11 AM UTC 24
Finished Aug 23 08:14:38 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1713130426 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 401.prim_prince_test.1713130426
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/401.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/402.prim_prince_test.2999873124
Short name T392
Test name
Test status
Simulation time 1813222898 ps
CPU time 26.36 seconds
Started Aug 23 08:14:11 AM UTC 24
Finished Aug 23 08:14:45 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2999873124 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 402.prim_prince_test.2999873124
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/402.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/403.prim_prince_test.2500145604
Short name T399
Test name
Test status
Simulation time 2319716265 ps
CPU time 34.45 seconds
Started Aug 23 08:14:12 AM UTC 24
Finished Aug 23 08:14:56 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2500145604 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 403.prim_prince_test.2500145604
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/403.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/404.prim_prince_test.2134013189
Short name T413
Test name
Test status
Simulation time 2957926479 ps
CPU time 44.02 seconds
Started Aug 23 08:14:15 AM UTC 24
Finished Aug 23 08:15:11 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2134013189 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 404.prim_prince_test.2134013189
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/404.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/405.prim_prince_test.1314171835
Short name T367
Test name
Test status
Simulation time 3641258776 ps
CPU time 53.91 seconds
Started Aug 23 08:14:16 AM UTC 24
Finished Aug 23 08:15:25 AM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1314171835 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 405.prim_prince_test.1314171835
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/405.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/406.prim_prince_test.262322691
Short name T415
Test name
Test status
Simulation time 3363733950 ps
CPU time 49.31 seconds
Started Aug 23 08:14:17 AM UTC 24
Finished Aug 23 08:15:19 AM UTC 24
Peak memory 154676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=262322691 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 406.prim_prince_test.262322691
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/406.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/407.prim_prince_test.1930356675
Short name T391
Test name
Test status
Simulation time 1255994871 ps
CPU time 18.59 seconds
Started Aug 23 08:14:19 AM UTC 24
Finished Aug 23 08:14:43 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1930356675 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 407.prim_prince_test.1930356675
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/407.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/408.prim_prince_test.1036217454
Short name T402
Test name
Test status
Simulation time 2037978756 ps
CPU time 30.09 seconds
Started Aug 23 08:14:19 AM UTC 24
Finished Aug 23 08:14:58 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1036217454 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 408.prim_prince_test.1036217454
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/408.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/409.prim_prince_test.2534505665
Short name T420
Test name
Test status
Simulation time 3639299304 ps
CPU time 53.73 seconds
Started Aug 23 08:14:19 AM UTC 24
Finished Aug 23 08:15:27 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2534505665 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 409.prim_prince_test.2534505665
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/409.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/41.prim_prince_test.2052603902
Short name T36
Test name
Test status
Simulation time 1503402873 ps
CPU time 22.12 seconds
Started Aug 23 08:02:54 AM UTC 24
Finished Aug 23 08:03:24 AM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2052603902 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 41.prim_prince_test.2052603902
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/41.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/410.prim_prince_test.1246327264
Short name T408
Test name
Test status
Simulation time 2097850803 ps
CPU time 30.57 seconds
Started Aug 23 08:14:24 AM UTC 24
Finished Aug 23 08:15:03 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1246327264 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 410.prim_prince_test.1246327264
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/410.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/411.prim_prince_test.113732312
Short name T406
Test name
Test status
Simulation time 2001214219 ps
CPU time 29.57 seconds
Started Aug 23 08:14:24 AM UTC 24
Finished Aug 23 08:15:02 AM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=113732312 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 411.prim_prince_test.113732312
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/411.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/412.prim_prince_test.1805805369
Short name T419
Test name
Test status
Simulation time 3152152542 ps
CPU time 46.02 seconds
Started Aug 23 08:14:26 AM UTC 24
Finished Aug 23 08:15:25 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1805805369 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 412.prim_prince_test.1805805369
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/412.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/413.prim_prince_test.329277785
Short name T410
Test name
Test status
Simulation time 1721441198 ps
CPU time 25.86 seconds
Started Aug 23 08:14:32 AM UTC 24
Finished Aug 23 08:15:05 AM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=329277785 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 413.prim_prince_test.329277785
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/413.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/414.prim_prince_test.4163401358
Short name T414
Test name
Test status
Simulation time 2300397013 ps
CPU time 33.79 seconds
Started Aug 23 08:14:32 AM UTC 24
Finished Aug 23 08:15:15 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4163401358 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 414.prim_prince_test.4163401358
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/414.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/415.prim_prince_test.3392354792
Short name T400
Test name
Test status
Simulation time 1229907239 ps
CPU time 18.47 seconds
Started Aug 23 08:14:33 AM UTC 24
Finished Aug 23 08:14:57 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3392354792 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 415.prim_prince_test.3392354792
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/415.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/416.prim_prince_test.4069353849
Short name T424
Test name
Test status
Simulation time 2787933141 ps
CPU time 40.97 seconds
Started Aug 23 08:14:39 AM UTC 24
Finished Aug 23 08:15:31 AM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4069353849 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 416.prim_prince_test.4069353849
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/416.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/417.prim_prince_test.3517859266
Short name T409
Test name
Test status
Simulation time 1024181639 ps
CPU time 15.28 seconds
Started Aug 23 08:14:44 AM UTC 24
Finished Aug 23 08:15:04 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3517859266 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 417.prim_prince_test.3517859266
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/417.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/418.prim_prince_test.1040417574
Short name T435
Test name
Test status
Simulation time 3391195199 ps
CPU time 49.24 seconds
Started Aug 23 08:14:46 AM UTC 24
Finished Aug 23 08:15:49 AM UTC 24
Peak memory 157988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1040417574 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 418.prim_prince_test.1040417574
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/418.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/419.prim_prince_test.2569389388
Short name T417
Test name
Test status
Simulation time 1842361517 ps
CPU time 27.23 seconds
Started Aug 23 08:14:46 AM UTC 24
Finished Aug 23 08:15:22 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2569389388 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 419.prim_prince_test.2569389388
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/419.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/42.prim_prince_test.3796752899
Short name T54
Test name
Test status
Simulation time 3637671383 ps
CPU time 52.67 seconds
Started Aug 23 08:02:56 AM UTC 24
Finished Aug 23 08:04:04 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3796752899 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 42.prim_prince_test.3796752899
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/42.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/420.prim_prince_test.454913844
Short name T421
Test name
Test status
Simulation time 2150324395 ps
CPU time 31.95 seconds
Started Aug 23 08:14:47 AM UTC 24
Finished Aug 23 08:15:27 AM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=454913844 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 420.prim_prince_test.454913844
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/420.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/421.prim_prince_test.4294939168
Short name T422
Test name
Test status
Simulation time 2214785897 ps
CPU time 32.13 seconds
Started Aug 23 08:14:50 AM UTC 24
Finished Aug 23 08:15:31 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4294939168 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 421.prim_prince_test.4294939168
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/421.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/422.prim_prince_test.1438827806
Short name T436
Test name
Test status
Simulation time 3196668841 ps
CPU time 47.42 seconds
Started Aug 23 08:14:51 AM UTC 24
Finished Aug 23 08:15:51 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1438827806 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 422.prim_prince_test.1438827806
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/422.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/423.prim_prince_test.2539084287
Short name T431
Test name
Test status
Simulation time 2746889194 ps
CPU time 40.51 seconds
Started Aug 23 08:14:51 AM UTC 24
Finished Aug 23 08:15:42 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2539084287 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 423.prim_prince_test.2539084287
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/423.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/424.prim_prince_test.1659572496
Short name T416
Test name
Test status
Simulation time 1459114990 ps
CPU time 21.95 seconds
Started Aug 23 08:14:53 AM UTC 24
Finished Aug 23 08:15:21 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1659572496 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 424.prim_prince_test.1659572496
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/424.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/425.prim_prince_test.3411836614
Short name T425
Test name
Test status
Simulation time 1879093826 ps
CPU time 27.78 seconds
Started Aug 23 08:14:57 AM UTC 24
Finished Aug 23 08:15:33 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3411836614 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 425.prim_prince_test.3411836614
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/425.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/426.prim_prince_test.2871089270
Short name T427
Test name
Test status
Simulation time 2025781126 ps
CPU time 29.89 seconds
Started Aug 23 08:14:57 AM UTC 24
Finished Aug 23 08:15:36 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2871089270 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 426.prim_prince_test.2871089270
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/426.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/427.prim_prince_test.1015227153
Short name T438
Test name
Test status
Simulation time 3130383925 ps
CPU time 46.01 seconds
Started Aug 23 08:14:59 AM UTC 24
Finished Aug 23 08:15:57 AM UTC 24
Peak memory 154056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1015227153 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 427.prim_prince_test.1015227153
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/427.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/428.prim_prince_test.2603051822
Short name T432
Test name
Test status
Simulation time 2442010958 ps
CPU time 36.25 seconds
Started Aug 23 08:14:59 AM UTC 24
Finished Aug 23 08:15:45 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2603051822 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 428.prim_prince_test.2603051822
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/428.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/429.prim_prince_test.2112446843
Short name T426
Test name
Test status
Simulation time 1852399974 ps
CPU time 27.52 seconds
Started Aug 23 08:15:00 AM UTC 24
Finished Aug 23 08:15:35 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2112446843 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 429.prim_prince_test.2112446843
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/429.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/43.prim_prince_test.2253271759
Short name T51
Test name
Test status
Simulation time 3062580492 ps
CPU time 44.31 seconds
Started Aug 23 08:03:02 AM UTC 24
Finished Aug 23 08:03:59 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2253271759 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 43.prim_prince_test.2253271759
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/43.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/430.prim_prince_test.530009326
Short name T428
Test name
Test status
Simulation time 1858243322 ps
CPU time 27.4 seconds
Started Aug 23 08:15:01 AM UTC 24
Finished Aug 23 08:15:36 AM UTC 24
Peak memory 156124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=530009326 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 430.prim_prince_test.530009326
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/430.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/431.prim_prince_test.2652124485
Short name T434
Test name
Test status
Simulation time 2469496147 ps
CPU time 36.63 seconds
Started Aug 23 08:15:02 AM UTC 24
Finished Aug 23 08:15:49 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2652124485 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 431.prim_prince_test.2652124485
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/431.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/432.prim_prince_test.3863935120
Short name T444
Test name
Test status
Simulation time 3277336624 ps
CPU time 48.9 seconds
Started Aug 23 08:15:03 AM UTC 24
Finished Aug 23 08:16:05 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3863935120 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 432.prim_prince_test.3863935120
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/432.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/433.prim_prince_test.4153429007
Short name T423
Test name
Test status
Simulation time 1438634977 ps
CPU time 21.82 seconds
Started Aug 23 08:15:03 AM UTC 24
Finished Aug 23 08:15:31 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4153429007 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 433.prim_prince_test.4153429007
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/433.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/434.prim_prince_test.4164841382
Short name T437
Test name
Test status
Simulation time 2790909731 ps
CPU time 41.27 seconds
Started Aug 23 08:15:05 AM UTC 24
Finished Aug 23 08:15:57 AM UTC 24
Peak memory 154412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4164841382 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 434.prim_prince_test.4164841382
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/434.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/435.prim_prince_test.3968738691
Short name T418
Test name
Test status
Simulation time 945750994 ps
CPU time 14.2 seconds
Started Aug 23 08:15:05 AM UTC 24
Finished Aug 23 08:15:23 AM UTC 24
Peak memory 154324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3968738691 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 435.prim_prince_test.3968738691
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/435.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/436.prim_prince_test.2937581285
Short name T441
Test name
Test status
Simulation time 3036666264 ps
CPU time 44.77 seconds
Started Aug 23 08:15:06 AM UTC 24
Finished Aug 23 08:16:02 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2937581285 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 436.prim_prince_test.2937581285
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/436.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/437.prim_prince_test.1571921999
Short name T430
Test name
Test status
Simulation time 1643181189 ps
CPU time 24.55 seconds
Started Aug 23 08:15:09 AM UTC 24
Finished Aug 23 08:15:41 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1571921999 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 437.prim_prince_test.1571921999
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/437.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/438.prim_prince_test.34422517
Short name T439
Test name
Test status
Simulation time 2630123129 ps
CPU time 39.49 seconds
Started Aug 23 08:15:09 AM UTC 24
Finished Aug 23 08:15:59 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34422517 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 438.prim_prince_test.34422517
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/438.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/439.prim_prince_test.2788823366
Short name T442
Test name
Test status
Simulation time 2814131988 ps
CPU time 41.47 seconds
Started Aug 23 08:15:12 AM UTC 24
Finished Aug 23 08:16:05 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2788823366 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 439.prim_prince_test.2788823366
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/439.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/44.prim_prince_test.1993955581
Short name T38
Test name
Test status
Simulation time 1231763021 ps
CPU time 18.08 seconds
Started Aug 23 08:03:02 AM UTC 24
Finished Aug 23 08:03:26 AM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1993955581 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 44.prim_prince_test.1993955581
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/44.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/440.prim_prince_test.4127287929
Short name T452
Test name
Test status
Simulation time 3254221010 ps
CPU time 47.52 seconds
Started Aug 23 08:15:15 AM UTC 24
Finished Aug 23 08:16:16 AM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4127287929 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 440.prim_prince_test.4127287929
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/440.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/441.prim_prince_test.8293177
Short name T456
Test name
Test status
Simulation time 3379226541 ps
CPU time 49.72 seconds
Started Aug 23 08:15:21 AM UTC 24
Finished Aug 23 08:16:24 AM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8293177 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 441.prim_prince_test.8293177
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/441.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/442.prim_prince_test.2216338932
Short name T446
Test name
Test status
Simulation time 2366090023 ps
CPU time 35.28 seconds
Started Aug 23 08:15:22 AM UTC 24
Finished Aug 23 08:16:07 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2216338932 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 442.prim_prince_test.2216338932
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/442.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/443.prim_prince_test.3535524655
Short name T461
Test name
Test status
Simulation time 3534873532 ps
CPU time 51.95 seconds
Started Aug 23 08:15:23 AM UTC 24
Finished Aug 23 08:16:29 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3535524655 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 443.prim_prince_test.3535524655
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/443.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/444.prim_prince_test.146419511
Short name T429
Test name
Test status
Simulation time 779676703 ps
CPU time 11.99 seconds
Started Aug 23 08:15:24 AM UTC 24
Finished Aug 23 08:15:40 AM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=146419511 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 444.prim_prince_test.146419511
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/444.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/445.prim_prince_test.2106051654
Short name T433
Test name
Test status
Simulation time 1098277551 ps
CPU time 16.62 seconds
Started Aug 23 08:15:26 AM UTC 24
Finished Aug 23 08:15:48 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2106051654 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 445.prim_prince_test.2106051654
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/445.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/446.prim_prince_test.1019196228
Short name T440
Test name
Test status
Simulation time 1808775024 ps
CPU time 26.62 seconds
Started Aug 23 08:15:26 AM UTC 24
Finished Aug 23 08:16:01 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1019196228 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 446.prim_prince_test.1019196228
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/446.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/447.prim_prince_test.2500514990
Short name T459
Test name
Test status
Simulation time 3162839884 ps
CPU time 47.03 seconds
Started Aug 23 08:15:28 AM UTC 24
Finished Aug 23 08:16:28 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2500514990 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 447.prim_prince_test.2500514990
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/447.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/448.prim_prince_test.64362565
Short name T443
Test name
Test status
Simulation time 1913193388 ps
CPU time 28.34 seconds
Started Aug 23 08:15:29 AM UTC 24
Finished Aug 23 08:16:05 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=64362565 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 448.prim_prince_test.64362565
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/448.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/449.prim_prince_test.2743244221
Short name T449
Test name
Test status
Simulation time 2160563150 ps
CPU time 31.77 seconds
Started Aug 23 08:15:32 AM UTC 24
Finished Aug 23 08:16:12 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2743244221 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 449.prim_prince_test.2743244221
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/449.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/45.prim_prince_test.3638359669
Short name T55
Test name
Test status
Simulation time 3426257684 ps
CPU time 50.11 seconds
Started Aug 23 08:03:03 AM UTC 24
Finished Aug 23 08:04:08 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3638359669 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 45.prim_prince_test.3638359669
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/45.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/450.prim_prince_test.4137454625
Short name T445
Test name
Test status
Simulation time 1793389856 ps
CPU time 27.07 seconds
Started Aug 23 08:15:32 AM UTC 24
Finished Aug 23 08:16:07 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4137454625 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 450.prim_prince_test.4137454625
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/450.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/451.prim_prince_test.4055434449
Short name T460
Test name
Test status
Simulation time 2947767572 ps
CPU time 43.33 seconds
Started Aug 23 08:15:33 AM UTC 24
Finished Aug 23 08:16:28 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4055434449 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 451.prim_prince_test.4055434449
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/451.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/452.prim_prince_test.604332061
Short name T462
Test name
Test status
Simulation time 3034439189 ps
CPU time 45.52 seconds
Started Aug 23 08:15:34 AM UTC 24
Finished Aug 23 08:16:32 AM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=604332061 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 452.prim_prince_test.604332061
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/452.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/453.prim_prince_test.1851847930
Short name T448
Test name
Test status
Simulation time 1678959669 ps
CPU time 25.14 seconds
Started Aug 23 08:15:36 AM UTC 24
Finished Aug 23 08:16:09 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1851847930 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 453.prim_prince_test.1851847930
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/453.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/454.prim_prince_test.4199489631
Short name T467
Test name
Test status
Simulation time 3724589190 ps
CPU time 53.96 seconds
Started Aug 23 08:15:36 AM UTC 24
Finished Aug 23 08:16:45 AM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4199489631 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 454.prim_prince_test.4199489631
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/454.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/455.prim_prince_test.1459844965
Short name T453
Test name
Test status
Simulation time 2270023306 ps
CPU time 34.19 seconds
Started Aug 23 08:15:37 AM UTC 24
Finished Aug 23 08:16:20 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1459844965 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 455.prim_prince_test.1459844965
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/455.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/456.prim_prince_test.1559149825
Short name T468
Test name
Test status
Simulation time 3434450071 ps
CPU time 50.55 seconds
Started Aug 23 08:15:41 AM UTC 24
Finished Aug 23 08:16:45 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1559149825 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 456.prim_prince_test.1559149825
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/456.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/457.prim_prince_test.393939912
Short name T447
Test name
Test status
Simulation time 1316707208 ps
CPU time 19.29 seconds
Started Aug 23 08:15:42 AM UTC 24
Finished Aug 23 08:16:07 AM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=393939912 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 457.prim_prince_test.393939912
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/457.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/458.prim_prince_test.3425019021
Short name T450
Test name
Test status
Simulation time 1544821210 ps
CPU time 23.07 seconds
Started Aug 23 08:15:43 AM UTC 24
Finished Aug 23 08:16:13 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3425019021 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 458.prim_prince_test.3425019021
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/458.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/459.prim_prince_test.3601015120
Short name T472
Test name
Test status
Simulation time 3659297170 ps
CPU time 53.66 seconds
Started Aug 23 08:15:45 AM UTC 24
Finished Aug 23 08:16:53 AM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3601015120 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 459.prim_prince_test.3601015120
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/459.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/46.prim_prince_test.683771789
Short name T41
Test name
Test status
Simulation time 1258757252 ps
CPU time 18.89 seconds
Started Aug 23 08:03:05 AM UTC 24
Finished Aug 23 08:03:30 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=683771789 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 46.prim_prince_test.683771789
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/46.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/460.prim_prince_test.650282779
Short name T471
Test name
Test status
Simulation time 3347162664 ps
CPU time 49.1 seconds
Started Aug 23 08:15:48 AM UTC 24
Finished Aug 23 08:16:51 AM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=650282779 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 460.prim_prince_test.650282779
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/460.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/461.prim_prince_test.570270101
Short name T466
Test name
Test status
Simulation time 2913081218 ps
CPU time 42.8 seconds
Started Aug 23 08:15:50 AM UTC 24
Finished Aug 23 08:16:44 AM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=570270101 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 461.prim_prince_test.570270101
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/461.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/462.prim_prince_test.194754893
Short name T463
Test name
Test status
Simulation time 2497005554 ps
CPU time 37.01 seconds
Started Aug 23 08:15:51 AM UTC 24
Finished Aug 23 08:16:38 AM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=194754893 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 462.prim_prince_test.194754893
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/462.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/463.prim_prince_test.160242160
Short name T469
Test name
Test status
Simulation time 2966718050 ps
CPU time 43.7 seconds
Started Aug 23 08:15:52 AM UTC 24
Finished Aug 23 08:16:48 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=160242160 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 463.prim_prince_test.160242160
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/463.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/464.prim_prince_test.3574791496
Short name T451
Test name
Test status
Simulation time 760220782 ps
CPU time 11.64 seconds
Started Aug 23 08:15:58 AM UTC 24
Finished Aug 23 08:16:14 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3574791496 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 464.prim_prince_test.3574791496
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/464.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/465.prim_prince_test.1887241085
Short name T458
Test name
Test status
Simulation time 1524354569 ps
CPU time 22.79 seconds
Started Aug 23 08:15:58 AM UTC 24
Finished Aug 23 08:16:28 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1887241085 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 465.prim_prince_test.1887241085
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/465.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/466.prim_prince_test.2564041207
Short name T482
Test name
Test status
Simulation time 3598881626 ps
CPU time 53.16 seconds
Started Aug 23 08:16:00 AM UTC 24
Finished Aug 23 08:17:08 AM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2564041207 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 466.prim_prince_test.2564041207
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/466.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/467.prim_prince_test.3780355409
Short name T454
Test name
Test status
Simulation time 950328178 ps
CPU time 14.4 seconds
Started Aug 23 08:16:02 AM UTC 24
Finished Aug 23 08:16:20 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3780355409 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 467.prim_prince_test.3780355409
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/467.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/468.prim_prince_test.2038383651
Short name T455
Test name
Test status
Simulation time 1018969266 ps
CPU time 15.24 seconds
Started Aug 23 08:16:04 AM UTC 24
Finished Aug 23 08:16:24 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2038383651 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 468.prim_prince_test.2038383651
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/468.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/469.prim_prince_test.4050331595
Short name T465
Test name
Test status
Simulation time 1728547415 ps
CPU time 25.46 seconds
Started Aug 23 08:16:06 AM UTC 24
Finished Aug 23 08:16:39 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4050331595 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 469.prim_prince_test.4050331595
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/469.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/47.prim_prince_test.4259589426
Short name T61
Test name
Test status
Simulation time 3703773672 ps
CPU time 54.27 seconds
Started Aug 23 08:03:05 AM UTC 24
Finished Aug 23 08:04:16 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4259589426 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 47.prim_prince_test.4259589426
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/47.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/470.prim_prince_test.3469690726
Short name T457
Test name
Test status
Simulation time 1043997363 ps
CPU time 15.75 seconds
Started Aug 23 08:16:06 AM UTC 24
Finished Aug 23 08:16:27 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3469690726 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 470.prim_prince_test.3469690726
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/470.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/471.prim_prince_test.448514835
Short name T484
Test name
Test status
Simulation time 3443231400 ps
CPU time 50.83 seconds
Started Aug 23 08:16:06 AM UTC 24
Finished Aug 23 08:17:11 AM UTC 24
Peak memory 154676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=448514835 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 471.prim_prince_test.448514835
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/471.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/472.prim_prince_test.1762848440
Short name T464
Test name
Test status
Simulation time 1589615937 ps
CPU time 23.92 seconds
Started Aug 23 08:16:08 AM UTC 24
Finished Aug 23 08:16:38 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1762848440 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 472.prim_prince_test.1762848440
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/472.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/473.prim_prince_test.956399876
Short name T477
Test name
Test status
Simulation time 2617810601 ps
CPU time 39.62 seconds
Started Aug 23 08:16:08 AM UTC 24
Finished Aug 23 08:16:58 AM UTC 24
Peak memory 154392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=956399876 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 473.prim_prince_test.956399876
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/473.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/474.prim_prince_test.4172212625
Short name T476
Test name
Test status
Simulation time 2648907674 ps
CPU time 38.83 seconds
Started Aug 23 08:16:08 AM UTC 24
Finished Aug 23 08:16:57 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4172212625 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 474.prim_prince_test.4172212625
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/474.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/475.prim_prince_test.3047121362
Short name T480
Test name
Test status
Simulation time 2810546835 ps
CPU time 41.64 seconds
Started Aug 23 08:16:10 AM UTC 24
Finished Aug 23 08:17:03 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3047121362 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 475.prim_prince_test.3047121362
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/475.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/476.prim_prince_test.3550924016
Short name T481
Test name
Test status
Simulation time 2627412873 ps
CPU time 39.26 seconds
Started Aug 23 08:16:13 AM UTC 24
Finished Aug 23 08:17:03 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3550924016 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 476.prim_prince_test.3550924016
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/476.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/477.prim_prince_test.2502944235
Short name T491
Test name
Test status
Simulation time 3631860956 ps
CPU time 53.03 seconds
Started Aug 23 08:16:13 AM UTC 24
Finished Aug 23 08:17:21 AM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2502944235 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 477.prim_prince_test.2502944235
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/477.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/478.prim_prince_test.3252339308
Short name T494
Test name
Test status
Simulation time 3622279412 ps
CPU time 53.07 seconds
Started Aug 23 08:16:14 AM UTC 24
Finished Aug 23 08:17:22 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3252339308 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 478.prim_prince_test.3252339308
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/478.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/479.prim_prince_test.2634551927
Short name T475
Test name
Test status
Simulation time 2015189080 ps
CPU time 30.1 seconds
Started Aug 23 08:16:16 AM UTC 24
Finished Aug 23 08:16:55 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2634551927 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 479.prim_prince_test.2634551927
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/479.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/48.prim_prince_test.2630795510
Short name T52
Test name
Test status
Simulation time 2487707828 ps
CPU time 36.16 seconds
Started Aug 23 08:03:14 AM UTC 24
Finished Aug 23 08:04:01 AM UTC 24
Peak memory 154560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2630795510 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 48.prim_prince_test.2630795510
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/48.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/480.prim_prince_test.4067890094
Short name T489
Test name
Test status
Simulation time 3089447278 ps
CPU time 45.57 seconds
Started Aug 23 08:16:21 AM UTC 24
Finished Aug 23 08:17:19 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4067890094 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 480.prim_prince_test.4067890094
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/480.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/481.prim_prince_test.4025664031
Short name T479
Test name
Test status
Simulation time 2040481902 ps
CPU time 30.3 seconds
Started Aug 23 08:16:22 AM UTC 24
Finished Aug 23 08:17:01 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4025664031 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 481.prim_prince_test.4025664031
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/481.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/482.prim_prince_test.3716874273
Short name T486
Test name
Test status
Simulation time 2639860727 ps
CPU time 38.52 seconds
Started Aug 23 08:16:25 AM UTC 24
Finished Aug 23 08:17:15 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3716874273 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 482.prim_prince_test.3716874273
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/482.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/483.prim_prince_test.3734146872
Short name T478
Test name
Test status
Simulation time 1758676049 ps
CPU time 26.43 seconds
Started Aug 23 08:16:25 AM UTC 24
Finished Aug 23 08:16:59 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3734146872 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 483.prim_prince_test.3734146872
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/483.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/484.prim_prince_test.1568723034
Short name T493
Test name
Test status
Simulation time 2907048275 ps
CPU time 42.77 seconds
Started Aug 23 08:16:27 AM UTC 24
Finished Aug 23 08:17:22 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1568723034 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 484.prim_prince_test.1568723034
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/484.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/485.prim_prince_test.999350822
Short name T470
Test name
Test status
Simulation time 1121536900 ps
CPU time 17.17 seconds
Started Aug 23 08:16:28 AM UTC 24
Finished Aug 23 08:16:51 AM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=999350822 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 485.prim_prince_test.999350822
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/485.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/486.prim_prince_test.4160641718
Short name T496
Test name
Test status
Simulation time 2880278529 ps
CPU time 42.4 seconds
Started Aug 23 08:16:30 AM UTC 24
Finished Aug 23 08:17:24 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4160641718 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 486.prim_prince_test.4160641718
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/486.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/487.prim_prince_test.487349946
Short name T483
Test name
Test status
Simulation time 2163794928 ps
CPU time 31.85 seconds
Started Aug 23 08:16:30 AM UTC 24
Finished Aug 23 08:17:11 AM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=487349946 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 487.prim_prince_test.487349946
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/487.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/488.prim_prince_test.2665867891
Short name T473
Test name
Test status
Simulation time 1300657731 ps
CPU time 19.29 seconds
Started Aug 23 08:16:30 AM UTC 24
Finished Aug 23 08:16:55 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2665867891 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 488.prim_prince_test.2665867891
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/488.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/489.prim_prince_test.2672061138
Short name T492
Test name
Test status
Simulation time 2545260870 ps
CPU time 37.23 seconds
Started Aug 23 08:16:33 AM UTC 24
Finished Aug 23 08:17:21 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2672061138 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 489.prim_prince_test.2672061138
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/489.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/49.prim_prince_test.1657409258
Short name T53
Test name
Test status
Simulation time 2495615680 ps
CPU time 36.42 seconds
Started Aug 23 08:03:15 AM UTC 24
Finished Aug 23 08:04:02 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1657409258 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 49.prim_prince_test.1657409258
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/49.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/490.prim_prince_test.4279523876
Short name T485
Test name
Test status
Simulation time 1708495865 ps
CPU time 24.82 seconds
Started Aug 23 08:16:39 AM UTC 24
Finished Aug 23 08:17:12 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4279523876 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 490.prim_prince_test.4279523876
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/490.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/491.prim_prince_test.3764497882
Short name T487
Test name
Test status
Simulation time 1860728527 ps
CPU time 27.57 seconds
Started Aug 23 08:16:39 AM UTC 24
Finished Aug 23 08:17:15 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3764497882 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 491.prim_prince_test.3764497882
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/491.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/492.prim_prince_test.3707458875
Short name T474
Test name
Test status
Simulation time 760788024 ps
CPU time 11.77 seconds
Started Aug 23 08:16:39 AM UTC 24
Finished Aug 23 08:16:55 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3707458875 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 492.prim_prince_test.3707458875
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/492.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/493.prim_prince_test.2732392656
Short name T488
Test name
Test status
Simulation time 1651653217 ps
CPU time 24.06 seconds
Started Aug 23 08:16:45 AM UTC 24
Finished Aug 23 08:17:16 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2732392656 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 493.prim_prince_test.2732392656
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/493.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/494.prim_prince_test.3973281743
Short name T498
Test name
Test status
Simulation time 2657174390 ps
CPU time 37.72 seconds
Started Aug 23 08:16:46 AM UTC 24
Finished Aug 23 08:17:35 AM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3973281743 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 494.prim_prince_test.3973281743
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/494.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/495.prim_prince_test.2891330344
Short name T495
Test name
Test status
Simulation time 1939199241 ps
CPU time 28.66 seconds
Started Aug 23 08:16:46 AM UTC 24
Finished Aug 23 08:17:23 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2891330344 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 495.prim_prince_test.2891330344
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/495.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/496.prim_prince_test.384563322
Short name T490
Test name
Test status
Simulation time 1716115249 ps
CPU time 24.65 seconds
Started Aug 23 08:16:48 AM UTC 24
Finished Aug 23 08:17:20 AM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=384563322 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 496.prim_prince_test.384563322
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/496.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/497.prim_prince_test.2316745284
Short name T497
Test name
Test status
Simulation time 1820165299 ps
CPU time 26.47 seconds
Started Aug 23 08:16:51 AM UTC 24
Finished Aug 23 08:17:26 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2316745284 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 497.prim_prince_test.2316745284
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/497.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/498.prim_prince_test.4040287395
Short name T499
Test name
Test status
Simulation time 2783230212 ps
CPU time 39.51 seconds
Started Aug 23 08:16:52 AM UTC 24
Finished Aug 23 08:17:44 AM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4040287395 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 498.prim_prince_test.4040287395
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/498.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/499.prim_prince_test.76762628
Short name T500
Test name
Test status
Simulation time 2669213521 ps
CPU time 37.24 seconds
Started Aug 23 08:16:55 AM UTC 24
Finished Aug 23 08:17:44 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=76762628 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 499.prim_prince_test.76762628
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/499.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/5.prim_prince_test.3298493536
Short name T13
Test name
Test status
Simulation time 3287569916 ps
CPU time 47.42 seconds
Started Aug 23 08:01:08 AM UTC 24
Finished Aug 23 08:02:10 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3298493536 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 5.prim_prince_test.3298493536
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/5.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/50.prim_prince_test.4213052814
Short name T43
Test name
Test status
Simulation time 787310701 ps
CPU time 11.86 seconds
Started Aug 23 08:03:18 AM UTC 24
Finished Aug 23 08:03:34 AM UTC 24
Peak memory 154348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4213052814 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 50.prim_prince_test.4213052814
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/50.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/51.prim_prince_test.1951942910
Short name T46
Test name
Test status
Simulation time 1419625096 ps
CPU time 20.85 seconds
Started Aug 23 08:03:22 AM UTC 24
Finished Aug 23 08:03:49 AM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1951942910 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 51.prim_prince_test.1951942910
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/51.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/52.prim_prince_test.1003989966
Short name T45
Test name
Test status
Simulation time 1253470374 ps
CPU time 18.61 seconds
Started Aug 23 08:03:25 AM UTC 24
Finished Aug 23 08:03:49 AM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1003989966 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 52.prim_prince_test.1003989966
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/52.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/53.prim_prince_test.2990627523
Short name T49
Test name
Test status
Simulation time 1308773565 ps
CPU time 18.9 seconds
Started Aug 23 08:03:26 AM UTC 24
Finished Aug 23 08:03:51 AM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2990627523 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 53.prim_prince_test.2990627523
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/53.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/54.prim_prince_test.1962189545
Short name T69
Test name
Test status
Simulation time 3490788801 ps
CPU time 50.7 seconds
Started Aug 23 08:03:27 AM UTC 24
Finished Aug 23 08:04:33 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1962189545 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 54.prim_prince_test.1962189545
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/54.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/55.prim_prince_test.3110113264
Short name T47
Test name
Test status
Simulation time 1014282915 ps
CPU time 15.02 seconds
Started Aug 23 08:03:30 AM UTC 24
Finished Aug 23 08:03:50 AM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3110113264 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 55.prim_prince_test.3110113264
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/55.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/56.prim_prince_test.3771953287
Short name T50
Test name
Test status
Simulation time 1174345650 ps
CPU time 17.27 seconds
Started Aug 23 08:03:30 AM UTC 24
Finished Aug 23 08:03:53 AM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3771953287 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 56.prim_prince_test.3771953287
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/56.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/57.prim_prince_test.1767161212
Short name T63
Test name
Test status
Simulation time 2876949070 ps
CPU time 41.68 seconds
Started Aug 23 08:03:31 AM UTC 24
Finished Aug 23 08:04:26 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1767161212 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 57.prim_prince_test.1767161212
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/57.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/58.prim_prince_test.1710979670
Short name T57
Test name
Test status
Simulation time 1823980180 ps
CPU time 26.87 seconds
Started Aug 23 08:03:33 AM UTC 24
Finished Aug 23 08:04:08 AM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1710979670 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 58.prim_prince_test.1710979670
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/58.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/59.prim_prince_test.3822157518
Short name T59
Test name
Test status
Simulation time 2033637771 ps
CPU time 29.64 seconds
Started Aug 23 08:03:34 AM UTC 24
Finished Aug 23 08:04:13 AM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3822157518 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 59.prim_prince_test.3822157518
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/59.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/6.prim_prince_test.1952461589
Short name T14
Test name
Test status
Simulation time 3593681851 ps
CPU time 51.77 seconds
Started Aug 23 08:01:08 AM UTC 24
Finished Aug 23 08:02:15 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1952461589 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 6.prim_prince_test.1952461589
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/6.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/60.prim_prince_test.656293128
Short name T56
Test name
Test status
Simulation time 1499758596 ps
CPU time 21.8 seconds
Started Aug 23 08:03:39 AM UTC 24
Finished Aug 23 08:04:08 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=656293128 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 60.prim_prince_test.656293128
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/60.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/61.prim_prince_test.3972665834
Short name T62
Test name
Test status
Simulation time 1681566094 ps
CPU time 24.32 seconds
Started Aug 23 08:03:48 AM UTC 24
Finished Aug 23 08:04:20 AM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3972665834 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 61.prim_prince_test.3972665834
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/61.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/62.prim_prince_test.1180682546
Short name T76
Test name
Test status
Simulation time 3686572494 ps
CPU time 52.95 seconds
Started Aug 23 08:03:50 AM UTC 24
Finished Aug 23 08:04:58 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1180682546 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 62.prim_prince_test.1180682546
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/62.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/63.prim_prince_test.2324092978
Short name T60
Test name
Test status
Simulation time 1280923114 ps
CPU time 19.23 seconds
Started Aug 23 08:03:50 AM UTC 24
Finished Aug 23 08:04:15 AM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2324092978 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 63.prim_prince_test.2324092978
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/63.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/64.prim_prince_test.1103880231
Short name T58
Test name
Test status
Simulation time 998776308 ps
CPU time 15.11 seconds
Started Aug 23 08:03:51 AM UTC 24
Finished Aug 23 08:04:11 AM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1103880231 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 64.prim_prince_test.1103880231
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/64.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/65.prim_prince_test.4028665005
Short name T70
Test name
Test status
Simulation time 2513156679 ps
CPU time 35.63 seconds
Started Aug 23 08:03:51 AM UTC 24
Finished Aug 23 08:04:37 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4028665005 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 65.prim_prince_test.4028665005
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/65.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/66.prim_prince_test.1140021932
Short name T64
Test name
Test status
Simulation time 1737387801 ps
CPU time 25.91 seconds
Started Aug 23 08:03:52 AM UTC 24
Finished Aug 23 08:04:26 AM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1140021932 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 66.prim_prince_test.1140021932
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/66.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/67.prim_prince_test.1526468822
Short name T66
Test name
Test status
Simulation time 1805208869 ps
CPU time 26.66 seconds
Started Aug 23 08:03:54 AM UTC 24
Finished Aug 23 08:04:29 AM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1526468822 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 67.prim_prince_test.1526468822
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/67.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/68.prim_prince_test.2032621532
Short name T71
Test name
Test status
Simulation time 2176108607 ps
CPU time 31.64 seconds
Started Aug 23 08:04:00 AM UTC 24
Finished Aug 23 08:04:41 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2032621532 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 68.prim_prince_test.2032621532
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/68.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/69.prim_prince_test.2641121037
Short name T75
Test name
Test status
Simulation time 2997082035 ps
CPU time 43.23 seconds
Started Aug 23 08:04:02 AM UTC 24
Finished Aug 23 08:04:58 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2641121037 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 69.prim_prince_test.2641121037
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/69.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/7.prim_prince_test.1752766203
Short name T15
Test name
Test status
Simulation time 3707683491 ps
CPU time 52.51 seconds
Started Aug 23 08:01:08 AM UTC 24
Finished Aug 23 08:02:16 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1752766203 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 7.prim_prince_test.1752766203
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/7.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/70.prim_prince_test.3818393992
Short name T77
Test name
Test status
Simulation time 3070081321 ps
CPU time 44.79 seconds
Started Aug 23 08:04:02 AM UTC 24
Finished Aug 23 08:05:00 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3818393992 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 70.prim_prince_test.3818393992
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/70.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/71.prim_prince_test.2869333739
Short name T65
Test name
Test status
Simulation time 1108584230 ps
CPU time 16.23 seconds
Started Aug 23 08:04:04 AM UTC 24
Finished Aug 23 08:04:26 AM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2869333739 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 71.prim_prince_test.2869333739
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/71.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/72.prim_prince_test.1709566908
Short name T68
Test name
Test status
Simulation time 1256770872 ps
CPU time 18.53 seconds
Started Aug 23 08:04:08 AM UTC 24
Finished Aug 23 08:04:33 AM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1709566908 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 72.prim_prince_test.1709566908
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/72.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/73.prim_prince_test.3726311941
Short name T72
Test name
Test status
Simulation time 2202051003 ps
CPU time 32.75 seconds
Started Aug 23 08:04:08 AM UTC 24
Finished Aug 23 08:04:50 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3726311941 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 73.prim_prince_test.3726311941
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/73.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/74.prim_prince_test.1211076319
Short name T67
Test name
Test status
Simulation time 1174280358 ps
CPU time 17.63 seconds
Started Aug 23 08:04:09 AM UTC 24
Finished Aug 23 08:04:32 AM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1211076319 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 74.prim_prince_test.1211076319
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/74.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/75.prim_prince_test.2161208811
Short name T80
Test name
Test status
Simulation time 2919878815 ps
CPU time 42.51 seconds
Started Aug 23 08:04:11 AM UTC 24
Finished Aug 23 08:05:06 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2161208811 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 75.prim_prince_test.2161208811
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/75.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/76.prim_prince_test.3947055767
Short name T73
Test name
Test status
Simulation time 2150212803 ps
CPU time 31.58 seconds
Started Aug 23 08:04:13 AM UTC 24
Finished Aug 23 08:04:54 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3947055767 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 76.prim_prince_test.3947055767
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/76.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/77.prim_prince_test.3302470095
Short name T74
Test name
Test status
Simulation time 2177182076 ps
CPU time 31.71 seconds
Started Aug 23 08:04:15 AM UTC 24
Finished Aug 23 08:04:57 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3302470095 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 77.prim_prince_test.3302470095
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/77.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/78.prim_prince_test.72905176
Short name T82
Test name
Test status
Simulation time 3002679772 ps
CPU time 42.96 seconds
Started Aug 23 08:04:17 AM UTC 24
Finished Aug 23 08:05:12 AM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=72905176 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 78.prim_prince_test.72905176
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/78.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/79.prim_prince_test.1181427732
Short name T85
Test name
Test status
Simulation time 2908011402 ps
CPU time 42.35 seconds
Started Aug 23 08:04:21 AM UTC 24
Finished Aug 23 08:05:15 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1181427732 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 79.prim_prince_test.1181427732
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/79.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/8.prim_prince_test.3411913305
Short name T6
Test name
Test status
Simulation time 2077966894 ps
CPU time 29.52 seconds
Started Aug 23 08:01:08 AM UTC 24
Finished Aug 23 08:01:47 AM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3411913305 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 8.prim_prince_test.3411913305
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/8.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/80.prim_prince_test.3259867621
Short name T89
Test name
Test status
Simulation time 3330005185 ps
CPU time 48.24 seconds
Started Aug 23 08:04:27 AM UTC 24
Finished Aug 23 08:05:29 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3259867621 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 80.prim_prince_test.3259867621
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/80.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/81.prim_prince_test.2728074359
Short name T87
Test name
Test status
Simulation time 3154601664 ps
CPU time 45.5 seconds
Started Aug 23 08:04:27 AM UTC 24
Finished Aug 23 08:05:26 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2728074359 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 81.prim_prince_test.2728074359
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/81.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/82.prim_prince_test.2095202374
Short name T84
Test name
Test status
Simulation time 2600326243 ps
CPU time 37.33 seconds
Started Aug 23 08:04:27 AM UTC 24
Finished Aug 23 08:05:15 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2095202374 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 82.prim_prince_test.2095202374
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/82.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/83.prim_prince_test.2054951083
Short name T78
Test name
Test status
Simulation time 1755892862 ps
CPU time 25.88 seconds
Started Aug 23 08:04:30 AM UTC 24
Finished Aug 23 08:05:04 AM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2054951083 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 83.prim_prince_test.2054951083
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/83.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/84.prim_prince_test.797966592
Short name T90
Test name
Test status
Simulation time 3160300496 ps
CPU time 45.4 seconds
Started Aug 23 08:04:33 AM UTC 24
Finished Aug 23 08:05:32 AM UTC 24
Peak memory 154652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=797966592 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 84.prim_prince_test.797966592
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/84.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/85.prim_prince_test.2547748665
Short name T79
Test name
Test status
Simulation time 1662937205 ps
CPU time 24.17 seconds
Started Aug 23 08:04:33 AM UTC 24
Finished Aug 23 08:05:05 AM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2547748665 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 85.prim_prince_test.2547748665
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/85.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/86.prim_prince_test.1285147072
Short name T93
Test name
Test status
Simulation time 3410277670 ps
CPU time 49.3 seconds
Started Aug 23 08:04:34 AM UTC 24
Finished Aug 23 08:05:37 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1285147072 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 86.prim_prince_test.1285147072
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/86.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/87.prim_prince_test.4005014305
Short name T81
Test name
Test status
Simulation time 1502460312 ps
CPU time 22.09 seconds
Started Aug 23 08:04:38 AM UTC 24
Finished Aug 23 08:05:07 AM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4005014305 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 87.prim_prince_test.4005014305
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/87.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/88.prim_prince_test.554455363
Short name T98
Test name
Test status
Simulation time 3546191749 ps
CPU time 51.59 seconds
Started Aug 23 08:04:41 AM UTC 24
Finished Aug 23 08:05:48 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=554455363 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 88.prim_prince_test.554455363
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/88.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/89.prim_prince_test.1486257584
Short name T92
Test name
Test status
Simulation time 2297855057 ps
CPU time 33.46 seconds
Started Aug 23 08:04:51 AM UTC 24
Finished Aug 23 08:05:34 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1486257584 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 89.prim_prince_test.1486257584
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/89.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/9.prim_prince_test.4034146516
Short name T3
Test name
Test status
Simulation time 1770539190 ps
CPU time 25.77 seconds
Started Aug 23 08:01:08 AM UTC 24
Finished Aug 23 08:01:42 AM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4034146516 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 9.prim_prince_test.4034146516
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/9.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/90.prim_prince_test.4082296035
Short name T101
Test name
Test status
Simulation time 3165148472 ps
CPU time 46.12 seconds
Started Aug 23 08:04:55 AM UTC 24
Finished Aug 23 08:05:55 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4082296035 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 90.prim_prince_test.4082296035
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/90.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/91.prim_prince_test.1223939585
Short name T83
Test name
Test status
Simulation time 861448784 ps
CPU time 12.55 seconds
Started Aug 23 08:04:57 AM UTC 24
Finished Aug 23 08:05:14 AM UTC 24
Peak memory 154348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1223939585 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 91.prim_prince_test.1223939585
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/91.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/92.prim_prince_test.3324517212
Short name T102
Test name
Test status
Simulation time 3112485936 ps
CPU time 45.43 seconds
Started Aug 23 08:04:58 AM UTC 24
Finished Aug 23 08:05:58 AM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3324517212 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 92.prim_prince_test.3324517212
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/92.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/93.prim_prince_test.2051210342
Short name T103
Test name
Test status
Simulation time 3268334991 ps
CPU time 48.3 seconds
Started Aug 23 08:04:58 AM UTC 24
Finished Aug 23 08:06:01 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2051210342 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 93.prim_prince_test.2051210342
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/93.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/94.prim_prince_test.1893825078
Short name T88
Test name
Test status
Simulation time 1429397548 ps
CPU time 21.17 seconds
Started Aug 23 08:05:00 AM UTC 24
Finished Aug 23 08:05:28 AM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1893825078 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 94.prim_prince_test.1893825078
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/94.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/95.prim_prince_test.3666890503
Short name T107
Test name
Test status
Simulation time 3571302540 ps
CPU time 51.7 seconds
Started Aug 23 08:05:05 AM UTC 24
Finished Aug 23 08:06:12 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3666890503 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 95.prim_prince_test.3666890503
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/95.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/96.prim_prince_test.2665083216
Short name T86
Test name
Test status
Simulation time 964852052 ps
CPU time 14.18 seconds
Started Aug 23 08:05:06 AM UTC 24
Finished Aug 23 08:05:25 AM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2665083216 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 96.prim_prince_test.2665083216
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/96.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/97.prim_prince_test.3501381450
Short name T94
Test name
Test status
Simulation time 1682217572 ps
CPU time 24.23 seconds
Started Aug 23 08:05:07 AM UTC 24
Finished Aug 23 08:05:39 AM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3501381450 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 97.prim_prince_test.3501381450
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/97.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/98.prim_prince_test.1487109214
Short name T108
Test name
Test status
Simulation time 3581731946 ps
CPU time 52.54 seconds
Started Aug 23 08:05:08 AM UTC 24
Finished Aug 23 08:06:15 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1487109214 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 98.prim_prince_test.1487109214
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/98.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default/99.prim_prince_test.848137946
Short name T100
Test name
Test status
Simulation time 2143392734 ps
CPU time 31.47 seconds
Started Aug 23 08:05:13 AM UTC 24
Finished Aug 23 08:05:54 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=848137946 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 99.prim_prince_test.848137946
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_prince-sim-vcs/99.prim_prince_test/latest
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