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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00 100.00


Total test records in report: 500
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html
T251 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/252.prim_prince_test.298690866 Aug 25 12:18:40 AM UTC 24 Aug 25 12:19:44 AM UTC 24 2428925441 ps
T252 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/286.prim_prince_test.2016103361 Aug 25 12:19:15 AM UTC 24 Aug 25 12:19:44 AM UTC 24 1106943224 ps
T253 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/274.prim_prince_test.1658147185 Aug 25 12:19:02 AM UTC 24 Aug 25 12:19:45 AM UTC 24 1619170983 ps
T254 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/245.prim_prince_test.4167486776 Aug 25 12:18:34 AM UTC 24 Aug 25 12:19:46 AM UTC 24 2734798552 ps
T255 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/285.prim_prince_test.2792434608 Aug 25 12:19:15 AM UTC 24 Aug 25 12:19:46 AM UTC 24 1168436501 ps
T256 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/239.prim_prince_test.3254924335 Aug 25 12:18:29 AM UTC 24 Aug 25 12:19:49 AM UTC 24 3064516750 ps
T257 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/256.prim_prince_test.2407804555 Aug 25 12:18:41 AM UTC 24 Aug 25 12:19:51 AM UTC 24 2649558947 ps
T258 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/255.prim_prince_test.688824422 Aug 25 12:18:40 AM UTC 24 Aug 25 12:19:52 AM UTC 24 2712392013 ps
T259 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/275.prim_prince_test.3086324878 Aug 25 12:19:02 AM UTC 24 Aug 25 12:19:52 AM UTC 24 1871519401 ps
T260 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/257.prim_prince_test.2743965157 Aug 25 12:18:41 AM UTC 24 Aug 25 12:19:52 AM UTC 24 2710284333 ps
T261 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/262.prim_prince_test.2893209356 Aug 25 12:18:44 AM UTC 24 Aug 25 12:19:53 AM UTC 24 2635083570 ps
T262 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/298.prim_prince_test.2482639199 Aug 25 12:19:24 AM UTC 24 Aug 25 12:19:53 AM UTC 24 1051228373 ps
T263 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/277.prim_prince_test.432908822 Aug 25 12:19:06 AM UTC 24 Aug 25 12:19:53 AM UTC 24 1779587945 ps
T264 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/230.prim_prince_test.1220229641 Aug 25 12:18:21 AM UTC 24 Aug 25 12:19:54 AM UTC 24 3514016185 ps
T265 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/241.prim_prince_test.3589517972 Aug 25 12:18:30 AM UTC 24 Aug 25 12:19:54 AM UTC 24 3232876414 ps
T266 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/250.prim_prince_test.1754451258 Aug 25 12:18:39 AM UTC 24 Aug 25 12:19:55 AM UTC 24 2930292601 ps
T267 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/234.prim_prince_test.3087409569 Aug 25 12:18:25 AM UTC 24 Aug 25 12:19:55 AM UTC 24 3455020086 ps
T268 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/243.prim_prince_test.428360022 Aug 25 12:18:32 AM UTC 24 Aug 25 12:19:56 AM UTC 24 3225003533 ps
T269 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/249.prim_prince_test.1330736854 Aug 25 12:18:36 AM UTC 24 Aug 25 12:19:56 AM UTC 24 3014366706 ps
T270 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/238.prim_prince_test.2777294863 Aug 25 12:18:29 AM UTC 24 Aug 25 12:19:57 AM UTC 24 3361963298 ps
T271 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/283.prim_prince_test.1993580210 Aug 25 12:19:10 AM UTC 24 Aug 25 12:19:57 AM UTC 24 1815674716 ps
T272 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/244.prim_prince_test.2557491355 Aug 25 12:18:32 AM UTC 24 Aug 25 12:19:57 AM UTC 24 3286888328 ps
T273 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/246.prim_prince_test.728218748 Aug 25 12:18:35 AM UTC 24 Aug 25 12:19:59 AM UTC 24 3198862229 ps
T274 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/254.prim_prince_test.3435601662 Aug 25 12:18:40 AM UTC 24 Aug 25 12:19:59 AM UTC 24 3026234345 ps
T275 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/267.prim_prince_test.1707543562 Aug 25 12:18:48 AM UTC 24 Aug 25 12:20:01 AM UTC 24 2757157020 ps
T276 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/370.prim_prince_test.2938205429 Aug 25 12:20:21 AM UTC 24 Aug 25 12:20:52 AM UTC 24 1180485768 ps
T277 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/242.prim_prince_test.3346234504 Aug 25 12:18:32 AM UTC 24 Aug 25 12:20:01 AM UTC 24 3418593090 ps
T278 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/260.prim_prince_test.3242525059 Aug 25 12:18:43 AM UTC 24 Aug 25 12:20:04 AM UTC 24 3151084588 ps
T279 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/253.prim_prince_test.2791316676 Aug 25 12:18:40 AM UTC 24 Aug 25 12:20:05 AM UTC 24 3249855103 ps
T280 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/279.prim_prince_test.329703672 Aug 25 12:19:09 AM UTC 24 Aug 25 12:20:07 AM UTC 24 2205186988 ps
T281 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/320.prim_prince_test.1024525795 Aug 25 12:19:45 AM UTC 24 Aug 25 12:20:08 AM UTC 24 830287406 ps
T282 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/321.prim_prince_test.780397842 Aug 25 12:19:47 AM UTC 24 Aug 25 12:20:08 AM UTC 24 772875920 ps
T283 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/306.prim_prince_test.1077793306 Aug 25 12:19:31 AM UTC 24 Aug 25 12:20:10 AM UTC 24 1450355922 ps
T284 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/270.prim_prince_test.4289566467 Aug 25 12:18:51 AM UTC 24 Aug 25 12:20:11 AM UTC 24 3095919144 ps
T285 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/299.prim_prince_test.3546282570 Aug 25 12:19:24 AM UTC 24 Aug 25 12:20:12 AM UTC 24 1789014482 ps
T286 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/293.prim_prince_test.2564704594 Aug 25 12:19:22 AM UTC 24 Aug 25 12:20:12 AM UTC 24 1936553396 ps
T287 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/258.prim_prince_test.2632153579 Aug 25 12:18:43 AM UTC 24 Aug 25 12:20:13 AM UTC 24 3477789313 ps
T288 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/308.prim_prince_test.3239490159 Aug 25 12:19:35 AM UTC 24 Aug 25 12:20:13 AM UTC 24 1449048521 ps
T289 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/325.prim_prince_test.2577837720 Aug 25 12:19:50 AM UTC 24 Aug 25 12:20:15 AM UTC 24 917632560 ps
T290 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/273.prim_prince_test.702791465 Aug 25 12:18:54 AM UTC 24 Aug 25 12:20:16 AM UTC 24 3141780640 ps
T291 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/282.prim_prince_test.506750051 Aug 25 12:19:09 AM UTC 24 Aug 25 12:20:17 AM UTC 24 2603860094 ps
T292 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/269.prim_prince_test.3834905292 Aug 25 12:18:51 AM UTC 24 Aug 25 12:20:19 AM UTC 24 3414319107 ps
T293 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/302.prim_prince_test.1398232127 Aug 25 12:19:27 AM UTC 24 Aug 25 12:20:19 AM UTC 24 1977764450 ps
T294 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/290.prim_prince_test.1280017642 Aug 25 12:19:17 AM UTC 24 Aug 25 12:20:19 AM UTC 24 2357538910 ps
T295 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/329.prim_prince_test.1132845050 Aug 25 12:19:54 AM UTC 24 Aug 25 12:20:19 AM UTC 24 927224672 ps
T296 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/268.prim_prince_test.645280900 Aug 25 12:18:49 AM UTC 24 Aug 25 12:20:19 AM UTC 24 3469399723 ps
T297 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/265.prim_prince_test.3322202617 Aug 25 12:18:46 AM UTC 24 Aug 25 12:20:19 AM UTC 24 3586797830 ps
T298 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/319.prim_prince_test.3904662075 Aug 25 12:19:45 AM UTC 24 Aug 25 12:20:20 AM UTC 24 1325337592 ps
T299 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/280.prim_prince_test.3621569143 Aug 25 12:19:09 AM UTC 24 Aug 25 12:20:21 AM UTC 24 2755775212 ps
T300 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/304.prim_prince_test.1763416495 Aug 25 12:19:29 AM UTC 24 Aug 25 12:20:21 AM UTC 24 2014136883 ps
T301 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/284.prim_prince_test.4189216456 Aug 25 12:19:10 AM UTC 24 Aug 25 12:20:25 AM UTC 24 2950251831 ps
T302 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/332.prim_prince_test.3459305241 Aug 25 12:19:54 AM UTC 24 Aug 25 12:20:27 AM UTC 24 1245920758 ps
T303 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/297.prim_prince_test.3134799805 Aug 25 12:19:24 AM UTC 24 Aug 25 12:20:27 AM UTC 24 2435251280 ps
T304 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/317.prim_prince_test.1100168004 Aug 25 12:19:44 AM UTC 24 Aug 25 12:20:27 AM UTC 24 1668243073 ps
T305 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/291.prim_prince_test.3924588271 Aug 25 12:19:20 AM UTC 24 Aug 25 12:20:28 AM UTC 24 2595800615 ps
T306 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/289.prim_prince_test.2832383695 Aug 25 12:19:17 AM UTC 24 Aug 25 12:20:29 AM UTC 24 2796243688 ps
T307 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/303.prim_prince_test.3123822089 Aug 25 12:19:28 AM UTC 24 Aug 25 12:20:29 AM UTC 24 2378819319 ps
T308 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/349.prim_prince_test.2569594791 Aug 25 12:20:05 AM UTC 24 Aug 25 12:20:30 AM UTC 24 912469533 ps
T309 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/288.prim_prince_test.2667833768 Aug 25 12:19:16 AM UTC 24 Aug 25 12:20:30 AM UTC 24 2873346377 ps
T310 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/305.prim_prince_test.3368075035 Aug 25 12:19:29 AM UTC 24 Aug 25 12:20:32 AM UTC 24 2435643242 ps
T311 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/356.prim_prince_test.3323738810 Aug 25 12:20:12 AM UTC 24 Aug 25 12:20:34 AM UTC 24 758672102 ps
T312 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/287.prim_prince_test.1110672443 Aug 25 12:19:16 AM UTC 24 Aug 25 12:20:34 AM UTC 24 3008842463 ps
T313 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/292.prim_prince_test.985941816 Aug 25 12:19:22 AM UTC 24 Aug 25 12:20:34 AM UTC 24 2797244255 ps
T314 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/328.prim_prince_test.1572199084 Aug 25 12:19:52 AM UTC 24 Aug 25 12:20:35 AM UTC 24 1608351677 ps
T315 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/354.prim_prince_test.2151922170 Aug 25 12:20:09 AM UTC 24 Aug 25 12:20:35 AM UTC 24 965848093 ps
T316 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/278.prim_prince_test.3144587060 Aug 25 12:19:08 AM UTC 24 Aug 25 12:20:35 AM UTC 24 3361329744 ps
T317 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/307.prim_prince_test.2770455071 Aug 25 12:19:32 AM UTC 24 Aug 25 12:20:35 AM UTC 24 2414266311 ps
T318 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/341.prim_prince_test.2441151895 Aug 25 12:19:58 AM UTC 24 Aug 25 12:20:35 AM UTC 24 1382955997 ps
T319 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/346.prim_prince_test.528832698 Aug 25 12:20:02 AM UTC 24 Aug 25 12:20:36 AM UTC 24 1251279515 ps
T320 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/330.prim_prince_test.299477757 Aug 25 12:19:54 AM UTC 24 Aug 25 12:20:38 AM UTC 24 1680376983 ps
T321 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/309.prim_prince_test.4178358205 Aug 25 12:19:36 AM UTC 24 Aug 25 12:20:38 AM UTC 24 2414141510 ps
T322 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/323.prim_prince_test.2629007023 Aug 25 12:19:47 AM UTC 24 Aug 25 12:20:40 AM UTC 24 2079146281 ps
T323 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/301.prim_prince_test.3438770136 Aug 25 12:19:26 AM UTC 24 Aug 25 12:20:43 AM UTC 24 2960351304 ps
T324 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/326.prim_prince_test.1676393920 Aug 25 12:19:51 AM UTC 24 Aug 25 12:20:43 AM UTC 24 1997853984 ps
T325 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/296.prim_prince_test.745140798 Aug 25 12:19:24 AM UTC 24 Aug 25 12:20:44 AM UTC 24 3078484801 ps
T326 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/335.prim_prince_test.353671787 Aug 25 12:19:57 AM UTC 24 Aug 25 12:20:46 AM UTC 24 1898482307 ps
T327 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/363.prim_prince_test.76954287 Aug 25 12:20:18 AM UTC 24 Aug 25 12:20:47 AM UTC 24 1074206007 ps
T328 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/353.prim_prince_test.3065379190 Aug 25 12:20:09 AM UTC 24 Aug 25 12:20:47 AM UTC 24 1438718527 ps
T329 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/312.prim_prince_test.1596303983 Aug 25 12:19:38 AM UTC 24 Aug 25 12:20:48 AM UTC 24 2685142372 ps
T330 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/316.prim_prince_test.240112523 Aug 25 12:19:42 AM UTC 24 Aug 25 12:20:49 AM UTC 24 2608952065 ps
T331 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/342.prim_prince_test.1050581479 Aug 25 12:19:59 AM UTC 24 Aug 25 12:20:49 AM UTC 24 1893186402 ps
T332 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/333.prim_prince_test.1176616942 Aug 25 12:19:55 AM UTC 24 Aug 25 12:20:49 AM UTC 24 2068194530 ps
T333 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/336.prim_prince_test.538110813 Aug 25 12:19:57 AM UTC 24 Aug 25 12:20:50 AM UTC 24 2031142258 ps
T334 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/322.prim_prince_test.3587678175 Aug 25 12:19:47 AM UTC 24 Aug 25 12:20:50 AM UTC 24 2423947934 ps
T335 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/348.prim_prince_test.1032933388 Aug 25 12:20:05 AM UTC 24 Aug 25 12:20:50 AM UTC 24 1726303964 ps
T336 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/339.prim_prince_test.1277716556 Aug 25 12:19:58 AM UTC 24 Aug 25 12:20:53 AM UTC 24 2099294574 ps
T337 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/300.prim_prince_test.4208036261 Aug 25 12:19:26 AM UTC 24 Aug 25 12:20:53 AM UTC 24 3369992176 ps
T338 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/368.prim_prince_test.3066915839 Aug 25 12:20:20 AM UTC 24 Aug 25 12:20:53 AM UTC 24 1249703296 ps
T339 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/366.prim_prince_test.2712087069 Aug 25 12:20:20 AM UTC 24 Aug 25 12:20:54 AM UTC 24 1262448217 ps
T340 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/351.prim_prince_test.3633362049 Aug 25 12:20:08 AM UTC 24 Aug 25 12:20:54 AM UTC 24 1773593725 ps
T341 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/294.prim_prince_test.213342143 Aug 25 12:19:23 AM UTC 24 Aug 25 12:20:56 AM UTC 24 3632679858 ps
T342 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/391.prim_prince_test.494889535 Aug 25 12:20:37 AM UTC 24 Aug 25 12:20:58 AM UTC 24 784122302 ps
T343 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/352.prim_prince_test.2336359032 Aug 25 12:20:08 AM UTC 24 Aug 25 12:20:58 AM UTC 24 1934109974 ps
T344 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/313.prim_prince_test.4044780853 Aug 25 12:19:38 AM UTC 24 Aug 25 12:21:01 AM UTC 24 3219216568 ps
T345 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/350.prim_prince_test.4012187497 Aug 25 12:20:06 AM UTC 24 Aug 25 12:21:02 AM UTC 24 2143058531 ps
T346 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/343.prim_prince_test.3303778674 Aug 25 12:20:00 AM UTC 24 Aug 25 12:21:03 AM UTC 24 2407910344 ps
T347 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/340.prim_prince_test.3994053725 Aug 25 12:19:58 AM UTC 24 Aug 25 12:21:03 AM UTC 24 2482772021 ps
T348 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/338.prim_prince_test.4079995684 Aug 25 12:19:57 AM UTC 24 Aug 25 12:21:05 AM UTC 24 2595003932 ps
T349 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/381.prim_prince_test.2651506888 Aug 25 12:20:30 AM UTC 24 Aug 25 12:21:06 AM UTC 24 1378229198 ps
T350 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/365.prim_prince_test.1624004077 Aug 25 12:20:20 AM UTC 24 Aug 25 12:21:08 AM UTC 24 1834212633 ps
T351 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/382.prim_prince_test.833376508 Aug 25 12:20:30 AM UTC 24 Aug 25 12:21:08 AM UTC 24 1457674030 ps
T352 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/324.prim_prince_test.3713235079 Aug 25 12:19:48 AM UTC 24 Aug 25 12:21:09 AM UTC 24 3139608802 ps
T353 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/311.prim_prince_test.35597279 Aug 25 12:19:37 AM UTC 24 Aug 25 12:21:10 AM UTC 24 3614669523 ps
T354 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/364.prim_prince_test.533782205 Aug 25 12:20:18 AM UTC 24 Aug 25 12:21:12 AM UTC 24 2050049032 ps
T355 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/394.prim_prince_test.4233309494 Aug 25 12:20:39 AM UTC 24 Aug 25 12:21:12 AM UTC 24 1235518011 ps
T356 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/374.prim_prince_test.1157320061 Aug 25 12:20:22 AM UTC 24 Aug 25 12:21:12 AM UTC 24 1901343638 ps
T357 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/310.prim_prince_test.1590609279 Aug 25 12:19:37 AM UTC 24 Aug 25 12:21:12 AM UTC 24 3690724401 ps
T358 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/331.prim_prince_test.3067419568 Aug 25 12:19:54 AM UTC 24 Aug 25 12:21:14 AM UTC 24 3104705149 ps
T359 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/314.prim_prince_test.3062747490 Aug 25 12:19:42 AM UTC 24 Aug 25 12:21:14 AM UTC 24 3599754791 ps
T360 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/388.prim_prince_test.3767592927 Aug 25 12:20:37 AM UTC 24 Aug 25 12:21:14 AM UTC 24 1436239474 ps
T361 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/318.prim_prince_test.1950678850 Aug 25 12:19:45 AM UTC 24 Aug 25 12:21:14 AM UTC 24 3465081341 ps
T362 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/393.prim_prince_test.139631997 Aug 25 12:20:37 AM UTC 24 Aug 25 12:21:14 AM UTC 24 1434981104 ps
T363 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/347.prim_prince_test.3969659012 Aug 25 12:20:04 AM UTC 24 Aug 25 12:21:16 AM UTC 24 2799352011 ps
T364 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/315.prim_prince_test.3745983597 Aug 25 12:19:42 AM UTC 24 Aug 25 12:21:16 AM UTC 24 3691659924 ps
T365 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/396.prim_prince_test.250963356 Aug 25 12:20:41 AM UTC 24 Aug 25 12:21:17 AM UTC 24 1399201428 ps
T366 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/389.prim_prince_test.2455192416 Aug 25 12:20:37 AM UTC 24 Aug 25 12:21:18 AM UTC 24 1599213144 ps
T367 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/361.prim_prince_test.385335974 Aug 25 12:20:16 AM UTC 24 Aug 25 12:21:19 AM UTC 24 2427140979 ps
T368 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/400.prim_prince_test.72695149 Aug 25 12:20:47 AM UTC 24 Aug 25 12:21:21 AM UTC 24 1311817141 ps
T369 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/357.prim_prince_test.2216956261 Aug 25 12:20:12 AM UTC 24 Aug 25 12:21:22 AM UTC 24 2679621032 ps
T370 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/376.prim_prince_test.3041089960 Aug 25 12:20:29 AM UTC 24 Aug 25 12:21:22 AM UTC 24 2052569519 ps
T371 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/390.prim_prince_test.702866566 Aug 25 12:20:37 AM UTC 24 Aug 25 12:21:22 AM UTC 24 1751649694 ps
T372 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/402.prim_prince_test.10951330 Aug 25 12:20:48 AM UTC 24 Aug 25 12:21:23 AM UTC 24 1339930869 ps
T373 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/359.prim_prince_test.3154045088 Aug 25 12:20:14 AM UTC 24 Aug 25 12:21:23 AM UTC 24 2713445410 ps
T374 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/355.prim_prince_test.4143097597 Aug 25 12:20:10 AM UTC 24 Aug 25 12:21:24 AM UTC 24 2862045662 ps
T375 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/345.prim_prince_test.2824583969 Aug 25 12:20:02 AM UTC 24 Aug 25 12:21:24 AM UTC 24 3186323056 ps
T376 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/375.prim_prince_test.3434335976 Aug 25 12:20:26 AM UTC 24 Aug 25 12:21:25 AM UTC 24 2265385171 ps
T377 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/417.prim_prince_test.2349771808 Aug 25 12:20:56 AM UTC 24 Aug 25 12:21:25 AM UTC 24 1128061451 ps
T378 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/327.prim_prince_test.937310079 Aug 25 12:19:52 AM UTC 24 Aug 25 12:21:26 AM UTC 24 3614844557 ps
T379 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/453.prim_prince_test.160272117 Aug 25 12:21:25 AM UTC 24 Aug 25 12:21:51 AM UTC 24 1014027525 ps
T380 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/384.prim_prince_test.669674540 Aug 25 12:20:33 AM UTC 24 Aug 25 12:21:55 AM UTC 24 3212415035 ps
T381 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/383.prim_prince_test.2833320521 Aug 25 12:20:31 AM UTC 24 Aug 25 12:21:26 AM UTC 24 2130973263 ps
T382 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/386.prim_prince_test.365599627 Aug 25 12:20:35 AM UTC 24 Aug 25 12:21:26 AM UTC 24 2000682066 ps
T383 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/398.prim_prince_test.3740711005 Aug 25 12:20:45 AM UTC 24 Aug 25 12:21:28 AM UTC 24 1675121937 ps
T384 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/404.prim_prince_test.936947674 Aug 25 12:20:50 AM UTC 24 Aug 25 12:21:28 AM UTC 24 1457793371 ps
T385 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/379.prim_prince_test.2935801545 Aug 25 12:20:29 AM UTC 24 Aug 25 12:21:28 AM UTC 24 2330855151 ps
T386 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/337.prim_prince_test.3656149201 Aug 25 12:19:57 AM UTC 24 Aug 25 12:21:29 AM UTC 24 3613754032 ps
T387 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/421.prim_prince_test.3371506501 Aug 25 12:21:01 AM UTC 24 Aug 25 12:21:55 AM UTC 24 2082829586 ps
T388 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/344.prim_prince_test.2934906944 Aug 25 12:20:02 AM UTC 24 Aug 25 12:21:29 AM UTC 24 3420959626 ps
T389 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/334.prim_prince_test.2345662228 Aug 25 12:19:55 AM UTC 24 Aug 25 12:21:30 AM UTC 24 3690452489 ps
T390 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/395.prim_prince_test.4257966271 Aug 25 12:20:39 AM UTC 24 Aug 25 12:21:31 AM UTC 24 2028884878 ps
T391 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/410.prim_prince_test.885999599 Aug 25 12:20:51 AM UTC 24 Aug 25 12:21:31 AM UTC 24 1531210551 ps
T392 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/428.prim_prince_test.4229269564 Aug 25 12:21:10 AM UTC 24 Aug 25 12:21:32 AM UTC 24 830668523 ps
T393 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/360.prim_prince_test.2650518494 Aug 25 12:20:14 AM UTC 24 Aug 25 12:21:32 AM UTC 24 3064166173 ps
T394 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/369.prim_prince_test.924065632 Aug 25 12:20:20 AM UTC 24 Aug 25 12:21:32 AM UTC 24 2815904894 ps
T395 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/406.prim_prince_test.1454668199 Aug 25 12:20:50 AM UTC 24 Aug 25 12:21:33 AM UTC 24 1679371334 ps
T396 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/418.prim_prince_test.1216398366 Aug 25 12:20:57 AM UTC 24 Aug 25 12:21:35 AM UTC 24 1488411805 ps
T397 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/358.prim_prince_test.2690777052 Aug 25 12:20:14 AM UTC 24 Aug 25 12:21:37 AM UTC 24 3284409225 ps
T398 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/372.prim_prince_test.3996746716 Aug 25 12:20:22 AM UTC 24 Aug 25 12:21:41 AM UTC 24 3077292096 ps
T399 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/380.prim_prince_test.3310150447 Aug 25 12:20:30 AM UTC 24 Aug 25 12:21:42 AM UTC 24 2834112725 ps
T400 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/414.prim_prince_test.2846261027 Aug 25 12:20:54 AM UTC 24 Aug 25 12:21:43 AM UTC 24 1894649006 ps
T401 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/413.prim_prince_test.3492999839 Aug 25 12:20:54 AM UTC 24 Aug 25 12:21:43 AM UTC 24 1902173804 ps
T402 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/424.prim_prince_test.2223026909 Aug 25 12:21:04 AM UTC 24 Aug 25 12:21:43 AM UTC 24 1515153415 ps
T403 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/439.prim_prince_test.305957244 Aug 25 12:21:15 AM UTC 24 Aug 25 12:21:43 AM UTC 24 1070224083 ps
T404 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/378.prim_prince_test.557594085 Aug 25 12:20:29 AM UTC 24 Aug 25 12:21:44 AM UTC 24 2930321639 ps
T405 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/420.prim_prince_test.3455473117 Aug 25 12:20:59 AM UTC 24 Aug 25 12:21:45 AM UTC 24 1777095008 ps
T406 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/454.prim_prince_test.2839406640 Aug 25 12:21:25 AM UTC 24 Aug 25 12:21:45 AM UTC 24 755155429 ps
T407 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/367.prim_prince_test.2736554498 Aug 25 12:20:20 AM UTC 24 Aug 25 12:21:46 AM UTC 24 3379188676 ps
T408 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/401.prim_prince_test.3010065639 Aug 25 12:20:48 AM UTC 24 Aug 25 12:21:47 AM UTC 24 2299268598 ps
T409 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/377.prim_prince_test.2113775584 Aug 25 12:20:29 AM UTC 24 Aug 25 12:21:48 AM UTC 24 3117822525 ps
T410 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/451.prim_prince_test.3393483058 Aug 25 12:21:25 AM UTC 24 Aug 25 12:21:48 AM UTC 24 894083793 ps
T411 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/429.prim_prince_test.1219147954 Aug 25 12:21:10 AM UTC 24 Aug 25 12:21:49 AM UTC 24 1534182970 ps
T412 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/422.prim_prince_test.1539379316 Aug 25 12:21:02 AM UTC 24 Aug 25 12:21:49 AM UTC 24 1820673946 ps
T413 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/409.prim_prince_test.3832462836 Aug 25 12:20:51 AM UTC 24 Aug 25 12:21:50 AM UTC 24 2294197415 ps
T414 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/415.prim_prince_test.3935280524 Aug 25 12:20:54 AM UTC 24 Aug 25 12:21:50 AM UTC 24 2178105048 ps
T415 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/436.prim_prince_test.2408771462 Aug 25 12:21:15 AM UTC 24 Aug 25 12:21:50 AM UTC 24 1379202077 ps
T416 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/373.prim_prince_test.1868685388 Aug 25 12:20:22 AM UTC 24 Aug 25 12:21:51 AM UTC 24 3497697032 ps
T417 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/387.prim_prince_test.1586661206 Aug 25 12:20:35 AM UTC 24 Aug 25 12:21:51 AM UTC 24 2982813629 ps
T418 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/362.prim_prince_test.1779771554 Aug 25 12:20:16 AM UTC 24 Aug 25 12:21:51 AM UTC 24 3755770851 ps
T419 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/442.prim_prince_test.3480143110 Aug 25 12:21:18 AM UTC 24 Aug 25 12:21:53 AM UTC 24 1382098079 ps
T420 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/371.prim_prince_test.1147586613 Aug 25 12:20:22 AM UTC 24 Aug 25 12:21:56 AM UTC 24 3706824567 ps
T421 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/433.prim_prince_test.1388760563 Aug 25 12:21:13 AM UTC 24 Aug 25 12:21:57 AM UTC 24 1696535909 ps
T422 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/468.prim_prince_test.4206193093 Aug 25 12:21:32 AM UTC 24 Aug 25 12:21:58 AM UTC 24 977288419 ps
T423 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/399.prim_prince_test.4089467524 Aug 25 12:20:45 AM UTC 24 Aug 25 12:21:58 AM UTC 24 2895833142 ps
T424 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/423.prim_prince_test.1133070348 Aug 25 12:21:04 AM UTC 24 Aug 25 12:21:59 AM UTC 24 2167805306 ps
T425 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/412.prim_prince_test.2127284245 Aug 25 12:20:54 AM UTC 24 Aug 25 12:22:00 AM UTC 24 2592205130 ps
T426 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/385.prim_prince_test.372394120 Aug 25 12:20:35 AM UTC 24 Aug 25 12:22:02 AM UTC 24 3418551161 ps
T427 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/435.prim_prince_test.1400759905 Aug 25 12:21:15 AM UTC 24 Aug 25 12:22:03 AM UTC 24 1873331567 ps
T428 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/457.prim_prince_test.2933459878 Aug 25 12:21:26 AM UTC 24 Aug 25 12:22:03 AM UTC 24 1424991962 ps
T429 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/455.prim_prince_test.4161116997 Aug 25 12:21:26 AM UTC 24 Aug 25 12:22:04 AM UTC 24 1450686164 ps
T430 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/460.prim_prince_test.855274555 Aug 25 12:21:28 AM UTC 24 Aug 25 12:22:05 AM UTC 24 1427016297 ps
T431 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/471.prim_prince_test.3190658680 Aug 25 12:21:34 AM UTC 24 Aug 25 12:22:05 AM UTC 24 1180133464 ps
T432 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/441.prim_prince_test.1630752728 Aug 25 12:21:18 AM UTC 24 Aug 25 12:22:05 AM UTC 24 1848113981 ps
T433 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/434.prim_prince_test.4175887126 Aug 25 12:21:13 AM UTC 24 Aug 25 12:22:06 AM UTC 24 2084794660 ps
T434 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/449.prim_prince_test.2345168504 Aug 25 12:21:23 AM UTC 24 Aug 25 12:22:07 AM UTC 24 1725097731 ps
T435 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/416.prim_prince_test.4138177522 Aug 25 12:20:56 AM UTC 24 Aug 25 12:22:09 AM UTC 24 2900446188 ps
T436 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/463.prim_prince_test.4291118858 Aug 25 12:21:29 AM UTC 24 Aug 25 12:22:10 AM UTC 24 1597223554 ps
T437 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/392.prim_prince_test.3289684193 Aug 25 12:20:37 AM UTC 24 Aug 25 12:22:10 AM UTC 24 3696803930 ps
T438 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/437.prim_prince_test.842200455 Aug 25 12:21:15 AM UTC 24 Aug 25 12:22:11 AM UTC 24 2210255463 ps
T439 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/469.prim_prince_test.4193458920 Aug 25 12:21:32 AM UTC 24 Aug 25 12:22:12 AM UTC 24 1522683560 ps
T440 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/430.prim_prince_test.627827797 Aug 25 12:21:11 AM UTC 24 Aug 25 12:22:13 AM UTC 24 2448410067 ps
T441 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/473.prim_prince_test.3315688812 Aug 25 12:21:34 AM UTC 24 Aug 25 12:22:13 AM UTC 24 1502320038 ps
T442 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/458.prim_prince_test.3775991265 Aug 25 12:21:27 AM UTC 24 Aug 25 12:22:14 AM UTC 24 1889110756 ps
T443 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/397.prim_prince_test.4246353419 Aug 25 12:20:43 AM UTC 24 Aug 25 12:22:15 AM UTC 24 3652098666 ps
T444 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/408.prim_prince_test.1019741577 Aug 25 12:20:51 AM UTC 24 Aug 25 12:22:16 AM UTC 24 3356588913 ps
T445 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/485.prim_prince_test.160137613 Aug 25 12:21:46 AM UTC 24 Aug 25 12:22:16 AM UTC 24 1144852263 ps
T446 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/403.prim_prince_test.421670986 Aug 25 12:20:50 AM UTC 24 Aug 25 12:22:16 AM UTC 24 3399211158 ps
T447 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/464.prim_prince_test.3936661630 Aug 25 12:21:29 AM UTC 24 Aug 25 12:22:17 AM UTC 24 1872336952 ps
T448 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/492.prim_prince_test.365256631 Aug 25 12:21:51 AM UTC 24 Aug 25 12:22:18 AM UTC 24 1033015200 ps
T449 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/438.prim_prince_test.3932350832 Aug 25 12:21:15 AM UTC 24 Aug 25 12:22:19 AM UTC 24 2524416925 ps
T450 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/495.prim_prince_test.931727998 Aug 25 12:21:53 AM UTC 24 Aug 25 12:22:20 AM UTC 24 1045970911 ps
T451 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/479.prim_prince_test.3245803219 Aug 25 12:21:44 AM UTC 24 Aug 25 12:22:21 AM UTC 24 1432140252 ps
T452 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/405.prim_prince_test.4242013341 Aug 25 12:20:50 AM UTC 24 Aug 25 12:22:23 AM UTC 24 3705368771 ps
T453 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/461.prim_prince_test.3659380921 Aug 25 12:21:28 AM UTC 24 Aug 25 12:22:23 AM UTC 24 2198463531 ps
T454 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/407.prim_prince_test.478472225 Aug 25 12:20:51 AM UTC 24 Aug 25 12:22:23 AM UTC 24 3654266327 ps
T455 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/497.prim_prince_test.1066752447 Aug 25 12:21:53 AM UTC 24 Aug 25 12:22:23 AM UTC 24 1184658151 ps
T456 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/466.prim_prince_test.4227147997 Aug 25 12:21:31 AM UTC 24 Aug 25 12:22:24 AM UTC 24 2078669219 ps
T457 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/459.prim_prince_test.3202842235 Aug 25 12:21:28 AM UTC 24 Aug 25 12:22:24 AM UTC 24 2234831302 ps
T458 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/444.prim_prince_test.1282662845 Aug 25 12:21:19 AM UTC 24 Aug 25 12:22:24 AM UTC 24 2608048410 ps
T459 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/445.prim_prince_test.2410945279 Aug 25 12:21:20 AM UTC 24 Aug 25 12:22:25 AM UTC 24 2601847317 ps
T460 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/411.prim_prince_test.3231203799 Aug 25 12:20:53 AM UTC 24 Aug 25 12:22:25 AM UTC 24 3687543022 ps
T461 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/475.prim_prince_test.1383300307 Aug 25 12:21:38 AM UTC 24 Aug 25 12:22:25 AM UTC 24 1878958321 ps
T462 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/425.prim_prince_test.4273565541 Aug 25 12:21:05 AM UTC 24 Aug 25 12:22:26 AM UTC 24 3251375544 ps
T463 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/470.prim_prince_test.3782929223 Aug 25 12:21:32 AM UTC 24 Aug 25 12:22:26 AM UTC 24 2151855466 ps
T464 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/432.prim_prince_test.1366712899 Aug 25 12:21:13 AM UTC 24 Aug 25 12:22:29 AM UTC 24 3023173687 ps
T465 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/419.prim_prince_test.2975420246 Aug 25 12:20:59 AM UTC 24 Aug 25 12:22:29 AM UTC 24 3610382478 ps
T466 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/496.prim_prince_test.3898349105 Aug 25 12:21:53 AM UTC 24 Aug 25 12:22:29 AM UTC 24 1433196657 ps
T467 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/427.prim_prince_test.814915414 Aug 25 12:21:08 AM UTC 24 Aug 25 12:22:30 AM UTC 24 3270050132 ps
T468 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/452.prim_prince_test.3938597120 Aug 25 12:21:25 AM UTC 24 Aug 25 12:22:32 AM UTC 24 2710041411 ps
T469 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/472.prim_prince_test.234030374 Aug 25 12:21:34 AM UTC 24 Aug 25 12:22:34 AM UTC 24 2411765962 ps
T470 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/481.prim_prince_test.3478774278 Aug 25 12:21:44 AM UTC 24 Aug 25 12:22:34 AM UTC 24 2019075499 ps
T471 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/426.prim_prince_test.624754413 Aug 25 12:21:07 AM UTC 24 Aug 25 12:22:35 AM UTC 24 3535706108 ps
T472 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/446.prim_prince_test.2024845772 Aug 25 12:21:20 AM UTC 24 Aug 25 12:22:35 AM UTC 24 3015776824 ps
T473 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/447.prim_prince_test.1605998302 Aug 25 12:21:22 AM UTC 24 Aug 25 12:22:35 AM UTC 24 2929158747 ps
T474 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/456.prim_prince_test.457685585 Aug 25 12:21:26 AM UTC 24 Aug 25 12:22:36 AM UTC 24 2800224404 ps
T475 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/431.prim_prince_test.2299963182 Aug 25 12:21:13 AM UTC 24 Aug 25 12:22:36 AM UTC 24 3361148071 ps
T476 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/477.prim_prince_test.1213658125 Aug 25 12:21:44 AM UTC 24 Aug 25 12:22:37 AM UTC 24 2130156719 ps
T477 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/493.prim_prince_test.3124019090 Aug 25 12:21:51 AM UTC 24 Aug 25 12:22:37 AM UTC 24 1854177349 ps
T478 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/486.prim_prince_test.152916481 Aug 25 12:21:47 AM UTC 24 Aug 25 12:22:37 AM UTC 24 2052868169 ps
T479 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/465.prim_prince_test.1798920223 Aug 25 12:21:31 AM UTC 24 Aug 25 12:22:37 AM UTC 24 2709289717 ps
T480 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/498.prim_prince_test.2251903199 Aug 25 12:21:53 AM UTC 24 Aug 25 12:22:37 AM UTC 24 1795536903 ps
T481 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/443.prim_prince_test.1855030512 Aug 25 12:21:19 AM UTC 24 Aug 25 12:22:37 AM UTC 24 3185633291 ps
T482 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/448.prim_prince_test.2688866913 Aug 25 12:21:23 AM UTC 24 Aug 25 12:22:39 AM UTC 24 3112032321 ps
T483 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/462.prim_prince_test.1461753866 Aug 25 12:21:29 AM UTC 24 Aug 25 12:22:40 AM UTC 24 2879587923 ps
T484 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/440.prim_prince_test.1813585848 Aug 25 12:21:18 AM UTC 24 Aug 25 12:22:41 AM UTC 24 3400541707 ps
T485 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/476.prim_prince_test.4290606457 Aug 25 12:21:41 AM UTC 24 Aug 25 12:22:43 AM UTC 24 2487777366 ps
T486 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/482.prim_prince_test.1173219125 Aug 25 12:21:44 AM UTC 24 Aug 25 12:22:43 AM UTC 24 2346865320 ps
T487 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/499.prim_prince_test.4049257961 Aug 25 12:21:53 AM UTC 24 Aug 25 12:22:43 AM UTC 24 2051617739 ps
T488 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/488.prim_prince_test.590433299 Aug 25 12:21:49 AM UTC 24 Aug 25 12:22:45 AM UTC 24 2231238038 ps
T489 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/483.prim_prince_test.2829887662 Aug 25 12:21:46 AM UTC 24 Aug 25 12:22:47 AM UTC 24 2445754799 ps
T490 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/494.prim_prince_test.2139482277 Aug 25 12:21:51 AM UTC 24 Aug 25 12:22:48 AM UTC 24 2271527586 ps
T491 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/480.prim_prince_test.1299204238 Aug 25 12:21:44 AM UTC 24 Aug 25 12:22:50 AM UTC 24 2667741976 ps
T492 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/450.prim_prince_test.1150924185 Aug 25 12:21:23 AM UTC 24 Aug 25 12:22:50 AM UTC 24 3530952226 ps
T493 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/484.prim_prince_test.1399413892 Aug 25 12:21:46 AM UTC 24 Aug 25 12:22:52 AM UTC 24 2684273913 ps
T494 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/474.prim_prince_test.2855141452 Aug 25 12:21:36 AM UTC 24 Aug 25 12:22:53 AM UTC 24 3109714570 ps
T495 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/467.prim_prince_test.473423895 Aug 25 12:21:31 AM UTC 24 Aug 25 12:23:00 AM UTC 24 3598408843 ps
T496 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/487.prim_prince_test.3746080465 Aug 25 12:21:48 AM UTC 24 Aug 25 12:23:01 AM UTC 24 2911924128 ps
T497 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/478.prim_prince_test.3780446258 Aug 25 12:21:44 AM UTC 24 Aug 25 12:23:06 AM UTC 24 3317595725 ps
T498 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/489.prim_prince_test.3077462827 Aug 25 12:21:49 AM UTC 24 Aug 25 12:23:06 AM UTC 24 3155878110 ps
T499 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/490.prim_prince_test.2659375343 Aug 25 12:21:51 AM UTC 24 Aug 25 12:23:07 AM UTC 24 3074828816 ps
T500 /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/491.prim_prince_test.4072109633 Aug 25 12:21:51 AM UTC 24 Aug 25 12:23:10 AM UTC 24 3278087891 ps

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/0.prim_prince_test.3205376223
Short name T1
Test name
Test status
Simulation time 824838622 ps
CPU time 18.66 seconds
Started Aug 25 12:14:22 AM UTC 24
Finished Aug 25 12:14:47 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3205376223 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 0.prim_prince_test.3205376223
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/0.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/1.prim_prince_test.2343397803
Short name T18
Test name
Test status
Simulation time 2151663297 ps
CPU time 45.27 seconds
Started Aug 25 12:14:23 AM UTC 24
Finished Aug 25 12:15:24 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2343397803 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 1.prim_prince_test.2343397803
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/1.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/10.prim_prince_test.767238798
Short name T3
Test name
Test status
Simulation time 855629559 ps
CPU time 18.58 seconds
Started Aug 25 12:14:30 AM UTC 24
Finished Aug 25 12:14:55 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=767238798 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 10.prim_prince_test.767238798
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/10.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/100.prim_prince_test.3921886009
Short name T56
Test name
Test status
Simulation time 975886185 ps
CPU time 20.31 seconds
Started Aug 25 12:16:05 AM UTC 24
Finished Aug 25 12:16:33 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3921886009 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 100.prim_prince_test.3921886009
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/100.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/101.prim_prince_test.2415670630
Short name T77
Test name
Test status
Simulation time 1395128729 ps
CPU time 29.42 seconds
Started Aug 25 12:16:08 AM UTC 24
Finished Aug 25 12:16:46 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2415670630 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 101.prim_prince_test.2415670630
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/101.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/102.prim_prince_test.2317386674
Short name T100
Test name
Test status
Simulation time 2292667981 ps
CPU time 48.03 seconds
Started Aug 25 12:16:09 AM UTC 24
Finished Aug 25 12:17:12 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2317386674 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 102.prim_prince_test.2317386674
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/102.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/103.prim_prince_test.2410101697
Short name T120
Test name
Test status
Simulation time 2847795020 ps
CPU time 58.53 seconds
Started Aug 25 12:16:10 AM UTC 24
Finished Aug 25 12:17:26 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2410101697 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 103.prim_prince_test.2410101697
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/103.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/104.prim_prince_test.460733197
Short name T74
Test name
Test status
Simulation time 1155528533 ps
CPU time 24.25 seconds
Started Aug 25 12:16:10 AM UTC 24
Finished Aug 25 12:16:42 AM UTC 24
Peak memory 154580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=460733197 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 104.prim_prince_test.460733197
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/104.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/105.prim_prince_test.2613884368
Short name T118
Test name
Test status
Simulation time 2778588658 ps
CPU time 57.61 seconds
Started Aug 25 12:16:10 AM UTC 24
Finished Aug 25 12:17:25 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2613884368 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 105.prim_prince_test.2613884368
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/105.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/106.prim_prince_test.2606634957
Short name T89
Test name
Test status
Simulation time 1581917184 ps
CPU time 33.29 seconds
Started Aug 25 12:16:11 AM UTC 24
Finished Aug 25 12:16:55 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2606634957 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 106.prim_prince_test.2606634957
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/106.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/107.prim_prince_test.352597974
Short name T110
Test name
Test status
Simulation time 2482763401 ps
CPU time 51.41 seconds
Started Aug 25 12:16:12 AM UTC 24
Finished Aug 25 12:17:19 AM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=352597974 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 107.prim_prince_test.352597974
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/107.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/108.prim_prince_test.1863764588
Short name T103
Test name
Test status
Simulation time 2282058208 ps
CPU time 47.17 seconds
Started Aug 25 12:16:12 AM UTC 24
Finished Aug 25 12:17:14 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1863764588 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 108.prim_prince_test.1863764588
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/108.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/109.prim_prince_test.3229971999
Short name T109
Test name
Test status
Simulation time 2459395063 ps
CPU time 50.52 seconds
Started Aug 25 12:16:13 AM UTC 24
Finished Aug 25 12:17:19 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3229971999 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 109.prim_prince_test.3229971999
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/109.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/11.prim_prince_test.681079739
Short name T4
Test name
Test status
Simulation time 1114064221 ps
CPU time 23.73 seconds
Started Aug 25 12:14:30 AM UTC 24
Finished Aug 25 12:15:02 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=681079739 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 11.prim_prince_test.681079739
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/11.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/110.prim_prince_test.2737599520
Short name T92
Test name
Test status
Simulation time 1571717838 ps
CPU time 33.29 seconds
Started Aug 25 12:16:17 AM UTC 24
Finished Aug 25 12:17:01 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2737599520 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 110.prim_prince_test.2737599520
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/110.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/111.prim_prince_test.591961346
Short name T139
Test name
Test status
Simulation time 3527844545 ps
CPU time 72.58 seconds
Started Aug 25 12:16:17 AM UTC 24
Finished Aug 25 12:17:51 AM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=591961346 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 111.prim_prince_test.591961346
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/111.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/112.prim_prince_test.634288784
Short name T135
Test name
Test status
Simulation time 3295266356 ps
CPU time 68.43 seconds
Started Aug 25 12:16:18 AM UTC 24
Finished Aug 25 12:17:47 AM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=634288784 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 112.prim_prince_test.634288784
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/112.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/113.prim_prince_test.707658237
Short name T85
Test name
Test status
Simulation time 1095268601 ps
CPU time 22.98 seconds
Started Aug 25 12:16:19 AM UTC 24
Finished Aug 25 12:16:50 AM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=707658237 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 113.prim_prince_test.707658237
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/113.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/114.prim_prince_test.2821221043
Short name T115
Test name
Test status
Simulation time 2177399051 ps
CPU time 45.01 seconds
Started Aug 25 12:16:23 AM UTC 24
Finished Aug 25 12:17:21 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2821221043 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 114.prim_prince_test.2821221043
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/114.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/115.prim_prince_test.3466333041
Short name T132
Test name
Test status
Simulation time 3059664611 ps
CPU time 63.48 seconds
Started Aug 25 12:16:24 AM UTC 24
Finished Aug 25 12:17:46 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3466333041 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 115.prim_prince_test.3466333041
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/115.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/116.prim_prince_test.2680752616
Short name T93
Test name
Test status
Simulation time 1365399463 ps
CPU time 28.62 seconds
Started Aug 25 12:16:25 AM UTC 24
Finished Aug 25 12:17:03 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2680752616 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 116.prim_prince_test.2680752616
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/116.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/117.prim_prince_test.3001539255
Short name T145
Test name
Test status
Simulation time 3417012459 ps
CPU time 70.45 seconds
Started Aug 25 12:16:28 AM UTC 24
Finished Aug 25 12:17:59 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3001539255 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 117.prim_prince_test.3001539255
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/117.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/118.prim_prince_test.3181404088
Short name T117
Test name
Test status
Simulation time 2034110009 ps
CPU time 42.28 seconds
Started Aug 25 12:16:28 AM UTC 24
Finished Aug 25 12:17:23 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3181404088 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 118.prim_prince_test.3181404088
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/118.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/119.prim_prince_test.1310719248
Short name T111
Test name
Test status
Simulation time 1886820046 ps
CPU time 39.06 seconds
Started Aug 25 12:16:28 AM UTC 24
Finished Aug 25 12:17:19 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1310719248 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 119.prim_prince_test.1310719248
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/119.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/12.prim_prince_test.2270962057
Short name T48
Test name
Test status
Simulation time 3439568298 ps
CPU time 71.48 seconds
Started Aug 25 12:14:30 AM UTC 24
Finished Aug 25 12:16:05 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2270962057 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 12.prim_prince_test.2270962057
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/12.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/120.prim_prince_test.170938602
Short name T129
Test name
Test status
Simulation time 2643597410 ps
CPU time 54.79 seconds
Started Aug 25 12:16:30 AM UTC 24
Finished Aug 25 12:17:41 AM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=170938602 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 120.prim_prince_test.170938602
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/120.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/121.prim_prince_test.2613762441
Short name T136
Test name
Test status
Simulation time 2928363171 ps
CPU time 60.83 seconds
Started Aug 25 12:16:30 AM UTC 24
Finished Aug 25 12:17:49 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2613762441 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 121.prim_prince_test.2613762441
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/121.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/122.prim_prince_test.4007915431
Short name T131
Test name
Test status
Simulation time 2683765272 ps
CPU time 54.84 seconds
Started Aug 25 12:16:33 AM UTC 24
Finished Aug 25 12:17:45 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4007915431 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 122.prim_prince_test.4007915431
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/122.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/123.prim_prince_test.4177568952
Short name T95
Test name
Test status
Simulation time 1100313014 ps
CPU time 23.14 seconds
Started Aug 25 12:16:33 AM UTC 24
Finished Aug 25 12:17:04 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4177568952 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 123.prim_prince_test.4177568952
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/123.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/124.prim_prince_test.740448128
Short name T119
Test name
Test status
Simulation time 1636406616 ps
CPU time 33.71 seconds
Started Aug 25 12:16:42 AM UTC 24
Finished Aug 25 12:17:26 AM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=740448128 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 124.prim_prince_test.740448128
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/124.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/125.prim_prince_test.1406041610
Short name T101
Test name
Test status
Simulation time 1080599482 ps
CPU time 22.49 seconds
Started Aug 25 12:16:43 AM UTC 24
Finished Aug 25 12:17:13 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1406041610 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 125.prim_prince_test.1406041610
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/125.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/126.prim_prince_test.198710630
Short name T98
Test name
Test status
Simulation time 862333252 ps
CPU time 18.08 seconds
Started Aug 25 12:16:43 AM UTC 24
Finished Aug 25 12:17:07 AM UTC 24
Peak memory 156060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=198710630 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 126.prim_prince_test.198710630
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/126.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/127.prim_prince_test.1935089684
Short name T97
Test name
Test status
Simulation time 838167952 ps
CPU time 18.04 seconds
Started Aug 25 12:16:43 AM UTC 24
Finished Aug 25 12:17:07 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1935089684 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 127.prim_prince_test.1935089684
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/127.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/128.prim_prince_test.99032251
Short name T147
Test name
Test status
Simulation time 2921515041 ps
CPU time 60.19 seconds
Started Aug 25 12:16:43 AM UTC 24
Finished Aug 25 12:18:01 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=99032251 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 128.prim_prince_test.99032251
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/128.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/129.prim_prince_test.3254476329
Short name T102
Test name
Test status
Simulation time 1022772886 ps
CPU time 21.57 seconds
Started Aug 25 12:16:44 AM UTC 24
Finished Aug 25 12:17:13 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3254476329 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 129.prim_prince_test.3254476329
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/129.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/13.prim_prince_test.1555046018
Short name T57
Test name
Test status
Simulation time 3665749996 ps
CPU time 76.67 seconds
Started Aug 25 12:14:30 AM UTC 24
Finished Aug 25 12:16:11 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1555046018 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 13.prim_prince_test.1555046018
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/13.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/130.prim_prince_test.644502853
Short name T150
Test name
Test status
Simulation time 3000812717 ps
CPU time 61.98 seconds
Started Aug 25 12:16:44 AM UTC 24
Finished Aug 25 12:18:05 AM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=644502853 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 130.prim_prince_test.644502853
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/130.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/131.prim_prince_test.3623817535
Short name T128
Test name
Test status
Simulation time 1938185836 ps
CPU time 40.24 seconds
Started Aug 25 12:16:48 AM UTC 24
Finished Aug 25 12:17:40 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3623817535 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 131.prim_prince_test.3623817535
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/131.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/132.prim_prince_test.4280877098
Short name T165
Test name
Test status
Simulation time 3349130660 ps
CPU time 68.24 seconds
Started Aug 25 12:16:48 AM UTC 24
Finished Aug 25 12:18:16 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4280877098 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 132.prim_prince_test.4280877098
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/132.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/133.prim_prince_test.2258078892
Short name T144
Test name
Test status
Simulation time 2667001599 ps
CPU time 54.64 seconds
Started Aug 25 12:16:48 AM UTC 24
Finished Aug 25 12:17:59 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2258078892 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 133.prim_prince_test.2258078892
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/133.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/134.prim_prince_test.653231797
Short name T133
Test name
Test status
Simulation time 2130721876 ps
CPU time 43.92 seconds
Started Aug 25 12:16:49 AM UTC 24
Finished Aug 25 12:17:46 AM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=653231797 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 134.prim_prince_test.653231797
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/134.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/135.prim_prince_test.276022841
Short name T123
Test name
Test status
Simulation time 1608049070 ps
CPU time 33.08 seconds
Started Aug 25 12:16:49 AM UTC 24
Finished Aug 25 12:17:32 AM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=276022841 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 135.prim_prince_test.276022841
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/135.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/136.prim_prince_test.1866596207
Short name T126
Test name
Test status
Simulation time 1680982236 ps
CPU time 35 seconds
Started Aug 25 12:16:49 AM UTC 24
Finished Aug 25 12:17:35 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1866596207 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 136.prim_prince_test.1866596207
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/136.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/137.prim_prince_test.330172712
Short name T155
Test name
Test status
Simulation time 2848987799 ps
CPU time 58.18 seconds
Started Aug 25 12:16:50 AM UTC 24
Finished Aug 25 12:18:06 AM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=330172712 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 137.prim_prince_test.330172712
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/137.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/138.prim_prince_test.2531612318
Short name T164
Test name
Test status
Simulation time 3166744029 ps
CPU time 64.9 seconds
Started Aug 25 12:16:50 AM UTC 24
Finished Aug 25 12:18:14 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2531612318 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 138.prim_prince_test.2531612318
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/138.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/139.prim_prince_test.3388332861
Short name T172
Test name
Test status
Simulation time 3560108077 ps
CPU time 72.9 seconds
Started Aug 25 12:16:50 AM UTC 24
Finished Aug 25 12:18:24 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3388332861 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 139.prim_prince_test.3388332861
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/139.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/14.prim_prince_test.2503689818
Short name T14
Test name
Test status
Simulation time 1792898951 ps
CPU time 38.03 seconds
Started Aug 25 12:14:30 AM UTC 24
Finished Aug 25 12:15:21 AM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2503689818 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 14.prim_prince_test.2503689818
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/14.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/140.prim_prince_test.1859148198
Short name T169
Test name
Test status
Simulation time 3405977048 ps
CPU time 69.5 seconds
Started Aug 25 12:16:51 AM UTC 24
Finished Aug 25 12:18:21 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1859148198 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 140.prim_prince_test.1859148198
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/140.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/141.prim_prince_test.2826736377
Short name T170
Test name
Test status
Simulation time 3418202314 ps
CPU time 70.17 seconds
Started Aug 25 12:16:53 AM UTC 24
Finished Aug 25 12:18:23 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2826736377 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 141.prim_prince_test.2826736377
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/141.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/142.prim_prince_test.4251711525
Short name T124
Test name
Test status
Simulation time 1428599638 ps
CPU time 29.59 seconds
Started Aug 25 12:16:54 AM UTC 24
Finished Aug 25 12:17:33 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4251711525 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 142.prim_prince_test.4251711525
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/142.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/143.prim_prince_test.3862084997
Short name T179
Test name
Test status
Simulation time 3642113291 ps
CPU time 74.8 seconds
Started Aug 25 12:16:54 AM UTC 24
Finished Aug 25 12:18:30 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3862084997 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 143.prim_prince_test.3862084997
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/143.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/144.prim_prince_test.2030401043
Short name T122
Test name
Test status
Simulation time 1324320289 ps
CPU time 27.47 seconds
Started Aug 25 12:16:55 AM UTC 24
Finished Aug 25 12:17:31 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2030401043 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 144.prim_prince_test.2030401043
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/144.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/145.prim_prince_test.3710464189
Short name T137
Test name
Test status
Simulation time 1982281248 ps
CPU time 40.99 seconds
Started Aug 25 12:16:56 AM UTC 24
Finished Aug 25 12:17:49 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3710464189 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 145.prim_prince_test.3710464189
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/145.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/146.prim_prince_test.3875879935
Short name T125
Test name
Test status
Simulation time 1333637278 ps
CPU time 27.72 seconds
Started Aug 25 12:16:58 AM UTC 24
Finished Aug 25 12:17:35 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3875879935 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 146.prim_prince_test.3875879935
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/146.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/147.prim_prince_test.1585197489
Short name T183
Test name
Test status
Simulation time 3602765824 ps
CPU time 73.85 seconds
Started Aug 25 12:16:59 AM UTC 24
Finished Aug 25 12:18:34 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1585197489 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 147.prim_prince_test.1585197489
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/147.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/148.prim_prince_test.3368836158
Short name T151
Test name
Test status
Simulation time 2380126986 ps
CPU time 49.01 seconds
Started Aug 25 12:17:01 AM UTC 24
Finished Aug 25 12:18:05 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3368836158 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 148.prim_prince_test.3368836158
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/148.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/149.prim_prince_test.548444365
Short name T130
Test name
Test status
Simulation time 1502685786 ps
CPU time 31.22 seconds
Started Aug 25 12:17:03 AM UTC 24
Finished Aug 25 12:17:44 AM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=548444365 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 149.prim_prince_test.548444365
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/149.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/15.prim_prince_test.4256661256
Short name T22
Test name
Test status
Simulation time 2182838175 ps
CPU time 45.94 seconds
Started Aug 25 12:14:30 AM UTC 24
Finished Aug 25 12:15:32 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4256661256 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 15.prim_prince_test.4256661256
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/15.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/150.prim_prince_test.892497642
Short name T178
Test name
Test status
Simulation time 3277364567 ps
CPU time 67.15 seconds
Started Aug 25 12:17:04 AM UTC 24
Finished Aug 25 12:18:30 AM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=892497642 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 150.prim_prince_test.892497642
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/150.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/151.prim_prince_test.1766418898
Short name T175
Test name
Test status
Simulation time 3128252257 ps
CPU time 63.99 seconds
Started Aug 25 12:17:05 AM UTC 24
Finished Aug 25 12:18:28 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1766418898 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 151.prim_prince_test.1766418898
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/151.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/152.prim_prince_test.1110176483
Short name T171
Test name
Test status
Simulation time 2994642896 ps
CPU time 61.12 seconds
Started Aug 25 12:17:05 AM UTC 24
Finished Aug 25 12:18:24 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1110176483 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 152.prim_prince_test.1110176483
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/152.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/153.prim_prince_test.3386858930
Short name T160
Test name
Test status
Simulation time 2442746395 ps
CPU time 50.65 seconds
Started Aug 25 12:17:06 AM UTC 24
Finished Aug 25 12:18:11 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3386858930 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 153.prim_prince_test.3386858930
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/153.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/154.prim_prince_test.1356215008
Short name T182
Test name
Test status
Simulation time 3265003593 ps
CPU time 66.4 seconds
Started Aug 25 12:17:08 AM UTC 24
Finished Aug 25 12:18:34 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1356215008 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 154.prim_prince_test.1356215008
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/154.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/155.prim_prince_test.3471299000
Short name T188
Test name
Test status
Simulation time 3422776409 ps
CPU time 70.39 seconds
Started Aug 25 12:17:08 AM UTC 24
Finished Aug 25 12:18:39 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3471299000 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 155.prim_prince_test.3471299000
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/155.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/156.prim_prince_test.591395815
Short name T138
Test name
Test status
Simulation time 1491663101 ps
CPU time 30.99 seconds
Started Aug 25 12:17:11 AM UTC 24
Finished Aug 25 12:17:51 AM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=591395815 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 156.prim_prince_test.591395815
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/156.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/157.prim_prince_test.2777556374
Short name T142
Test name
Test status
Simulation time 1589693776 ps
CPU time 33.16 seconds
Started Aug 25 12:17:13 AM UTC 24
Finished Aug 25 12:17:56 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2777556374 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 157.prim_prince_test.2777556374
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/157.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/158.prim_prince_test.2767968074
Short name T153
Test name
Test status
Simulation time 1967831328 ps
CPU time 40.74 seconds
Started Aug 25 12:17:13 AM UTC 24
Finished Aug 25 12:18:05 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2767968074 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 158.prim_prince_test.2767968074
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/158.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/159.prim_prince_test.86905290
Short name T187
Test name
Test status
Simulation time 3237634518 ps
CPU time 65.92 seconds
Started Aug 25 12:17:14 AM UTC 24
Finished Aug 25 12:18:39 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=86905290 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 159.prim_prince_test.86905290
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/159.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/16.prim_prince_test.1853955282
Short name T35
Test name
Test status
Simulation time 2893322572 ps
CPU time 60.83 seconds
Started Aug 25 12:14:30 AM UTC 24
Finished Aug 25 12:15:51 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1853955282 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 16.prim_prince_test.1853955282
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/16.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/160.prim_prince_test.853928926
Short name T191
Test name
Test status
Simulation time 3298122336 ps
CPU time 67.58 seconds
Started Aug 25 12:17:14 AM UTC 24
Finished Aug 25 12:18:41 AM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=853928926 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 160.prim_prince_test.853928926
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/160.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/161.prim_prince_test.734918476
Short name T152
Test name
Test status
Simulation time 1874669966 ps
CPU time 38.68 seconds
Started Aug 25 12:17:15 AM UTC 24
Finished Aug 25 12:18:05 AM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=734918476 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 161.prim_prince_test.734918476
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/161.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/162.prim_prince_test.2412160634
Short name T148
Test name
Test status
Simulation time 1728055038 ps
CPU time 35.44 seconds
Started Aug 25 12:17:16 AM UTC 24
Finished Aug 25 12:18:02 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2412160634 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 162.prim_prince_test.2412160634
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/162.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/163.prim_prince_test.2727553442
Short name T197
Test name
Test status
Simulation time 3265251684 ps
CPU time 66.8 seconds
Started Aug 25 12:17:17 AM UTC 24
Finished Aug 25 12:18:43 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2727553442 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 163.prim_prince_test.2727553442
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/163.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/164.prim_prince_test.129272807
Short name T143
Test name
Test status
Simulation time 1538227495 ps
CPU time 32.05 seconds
Started Aug 25 12:17:17 AM UTC 24
Finished Aug 25 12:17:59 AM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=129272807 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 164.prim_prince_test.129272807
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/164.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/165.prim_prince_test.860629193
Short name T163
Test name
Test status
Simulation time 2096057141 ps
CPU time 43.48 seconds
Started Aug 25 12:17:18 AM UTC 24
Finished Aug 25 12:18:14 AM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=860629193 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 165.prim_prince_test.860629193
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/165.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/166.prim_prince_test.2528115222
Short name T186
Test name
Test status
Simulation time 2973976490 ps
CPU time 61.08 seconds
Started Aug 25 12:17:19 AM UTC 24
Finished Aug 25 12:18:38 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2528115222 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 166.prim_prince_test.2528115222
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/166.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/167.prim_prince_test.602206263
Short name T203
Test name
Test status
Simulation time 3383912391 ps
CPU time 69.04 seconds
Started Aug 25 12:17:20 AM UTC 24
Finished Aug 25 12:18:48 AM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=602206263 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 167.prim_prince_test.602206263
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/167.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/168.prim_prince_test.2114882811
Short name T154
Test name
Test status
Simulation time 1701504772 ps
CPU time 35.36 seconds
Started Aug 25 12:17:20 AM UTC 24
Finished Aug 25 12:18:06 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2114882811 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 168.prim_prince_test.2114882811
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/168.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/169.prim_prince_test.3572292117
Short name T166
Test name
Test status
Simulation time 2251989158 ps
CPU time 46.03 seconds
Started Aug 25 12:17:20 AM UTC 24
Finished Aug 25 12:18:19 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3572292117 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 169.prim_prince_test.3572292117
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/169.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/17.prim_prince_test.2643641423
Short name T37
Test name
Test status
Simulation time 2909627793 ps
CPU time 61.09 seconds
Started Aug 25 12:14:31 AM UTC 24
Finished Aug 25 12:15:53 AM UTC 24
Peak memory 154552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2643641423 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 17.prim_prince_test.2643641423
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/17.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/170.prim_prince_test.2737391607
Short name T140
Test name
Test status
Simulation time 1257858871 ps
CPU time 26.08 seconds
Started Aug 25 12:17:21 AM UTC 24
Finished Aug 25 12:17:55 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2737391607 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 170.prim_prince_test.2737391607
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/170.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/171.prim_prince_test.4075308272
Short name T134
Test name
Test status
Simulation time 935518769 ps
CPU time 19.58 seconds
Started Aug 25 12:17:21 AM UTC 24
Finished Aug 25 12:17:47 AM UTC 24
Peak memory 156056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4075308272 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 171.prim_prince_test.4075308272
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/171.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/172.prim_prince_test.1838902409
Short name T159
Test name
Test status
Simulation time 1874938725 ps
CPU time 38.59 seconds
Started Aug 25 12:17:21 AM UTC 24
Finished Aug 25 12:18:11 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1838902409 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 172.prim_prince_test.1838902409
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/172.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/173.prim_prince_test.2465632368
Short name T181
Test name
Test status
Simulation time 2730571905 ps
CPU time 55.46 seconds
Started Aug 25 12:17:22 AM UTC 24
Finished Aug 25 12:18:34 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2465632368 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 173.prim_prince_test.2465632368
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/173.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/174.prim_prince_test.4002056604
Short name T206
Test name
Test status
Simulation time 3332026602 ps
CPU time 68.89 seconds
Started Aug 25 12:17:23 AM UTC 24
Finished Aug 25 12:18:52 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4002056604 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 174.prim_prince_test.4002056604
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/174.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/175.prim_prince_test.1491528310
Short name T194
Test name
Test status
Simulation time 2917673315 ps
CPU time 60.34 seconds
Started Aug 25 12:17:24 AM UTC 24
Finished Aug 25 12:18:42 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1491528310 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 175.prim_prince_test.1491528310
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/175.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/176.prim_prince_test.1681602142
Short name T156
Test name
Test status
Simulation time 1625180708 ps
CPU time 33.89 seconds
Started Aug 25 12:17:25 AM UTC 24
Finished Aug 25 12:18:09 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1681602142 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 176.prim_prince_test.1681602142
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/176.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/177.prim_prince_test.3482557262
Short name T168
Test name
Test status
Simulation time 2040057474 ps
CPU time 42.21 seconds
Started Aug 25 12:17:26 AM UTC 24
Finished Aug 25 12:18:21 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3482557262 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 177.prim_prince_test.3482557262
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/177.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/178.prim_prince_test.2754882724
Short name T149
Test name
Test status
Simulation time 1394964897 ps
CPU time 28.91 seconds
Started Aug 25 12:17:27 AM UTC 24
Finished Aug 25 12:18:04 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2754882724 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 178.prim_prince_test.2754882724
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/178.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/179.prim_prince_test.641682685
Short name T146
Test name
Test status
Simulation time 1116928809 ps
CPU time 23.12 seconds
Started Aug 25 12:17:31 AM UTC 24
Finished Aug 25 12:18:01 AM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=641682685 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 179.prim_prince_test.641682685
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/179.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/18.prim_prince_test.3041966630
Short name T31
Test name
Test status
Simulation time 2622335318 ps
CPU time 54.63 seconds
Started Aug 25 12:14:31 AM UTC 24
Finished Aug 25 12:15:45 AM UTC 24
Peak memory 154520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3041966630 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 18.prim_prince_test.3041966630
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/18.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/180.prim_prince_test.2899744831
Short name T141
Test name
Test status
Simulation time 855941732 ps
CPU time 18.23 seconds
Started Aug 25 12:17:32 AM UTC 24
Finished Aug 25 12:17:56 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2899744831 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 180.prim_prince_test.2899744831
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/180.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/181.prim_prince_test.2131217261
Short name T158
Test name
Test status
Simulation time 1389303856 ps
CPU time 28.67 seconds
Started Aug 25 12:17:33 AM UTC 24
Finished Aug 25 12:18:10 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2131217261 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 181.prim_prince_test.2131217261
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/181.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/182.prim_prince_test.3679077899
Short name T207
Test name
Test status
Simulation time 2976122744 ps
CPU time 61.38 seconds
Started Aug 25 12:17:34 AM UTC 24
Finished Aug 25 12:18:53 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3679077899 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 182.prim_prince_test.3679077899
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/182.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/183.prim_prince_test.3924221657
Short name T161
Test name
Test status
Simulation time 1416970465 ps
CPU time 29.22 seconds
Started Aug 25 12:17:35 AM UTC 24
Finished Aug 25 12:18:13 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3924221657 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 183.prim_prince_test.3924221657
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/183.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/184.prim_prince_test.2968851522
Short name T157
Test name
Test status
Simulation time 1235208032 ps
CPU time 25.83 seconds
Started Aug 25 12:17:36 AM UTC 24
Finished Aug 25 12:18:10 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2968851522 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 184.prim_prince_test.2968851522
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/184.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/185.prim_prince_test.3980386391
Short name T213
Test name
Test status
Simulation time 3418439101 ps
CPU time 70.34 seconds
Started Aug 25 12:17:37 AM UTC 24
Finished Aug 25 12:19:08 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3980386391 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 185.prim_prince_test.3980386391
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/185.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/186.prim_prince_test.4041712240
Short name T173
Test name
Test status
Simulation time 1814464050 ps
CPU time 37.12 seconds
Started Aug 25 12:17:38 AM UTC 24
Finished Aug 25 12:18:26 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4041712240 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 186.prim_prince_test.4041712240
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/186.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/187.prim_prince_test.1267073948
Short name T167
Test name
Test status
Simulation time 1441286091 ps
CPU time 29.75 seconds
Started Aug 25 12:17:42 AM UTC 24
Finished Aug 25 12:18:20 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1267073948 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 187.prim_prince_test.1267073948
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/187.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/188.prim_prince_test.188106601
Short name T185
Test name
Test status
Simulation time 2066345213 ps
CPU time 42.67 seconds
Started Aug 25 12:17:43 AM UTC 24
Finished Aug 25 12:18:38 AM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=188106601 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 188.prim_prince_test.188106601
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/188.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/189.prim_prince_test.2709948422
Short name T216
Test name
Test status
Simulation time 3184987303 ps
CPU time 65.14 seconds
Started Aug 25 12:17:45 AM UTC 24
Finished Aug 25 12:19:08 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2709948422 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 189.prim_prince_test.2709948422
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/189.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/19.prim_prince_test.2430792481
Short name T10
Test name
Test status
Simulation time 1511383399 ps
CPU time 32.07 seconds
Started Aug 25 12:14:31 AM UTC 24
Finished Aug 25 12:15:15 AM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2430792481 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 19.prim_prince_test.2430792481
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/19.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/190.prim_prince_test.737259185
Short name T177
Test name
Test status
Simulation time 1625181292 ps
CPU time 33.49 seconds
Started Aug 25 12:17:46 AM UTC 24
Finished Aug 25 12:18:29 AM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=737259185 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 190.prim_prince_test.737259185
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/190.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/191.prim_prince_test.2151882286
Short name T231
Test name
Test status
Simulation time 3679349940 ps
CPU time 74.97 seconds
Started Aug 25 12:17:47 AM UTC 24
Finished Aug 25 12:19:23 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2151882286 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 191.prim_prince_test.2151882286
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/191.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/192.prim_prince_test.514241063
Short name T235
Test name
Test status
Simulation time 3707833290 ps
CPU time 75.98 seconds
Started Aug 25 12:17:47 AM UTC 24
Finished Aug 25 12:19:25 AM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=514241063 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 192.prim_prince_test.514241063
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/192.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/193.prim_prince_test.1365522594
Short name T195
Test name
Test status
Simulation time 2053582675 ps
CPU time 42.39 seconds
Started Aug 25 12:17:47 AM UTC 24
Finished Aug 25 12:18:42 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1365522594 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 193.prim_prince_test.1365522594
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/193.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/194.prim_prince_test.1066688553
Short name T200
Test name
Test status
Simulation time 2152464849 ps
CPU time 43.88 seconds
Started Aug 25 12:17:49 AM UTC 24
Finished Aug 25 12:18:45 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1066688553 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 194.prim_prince_test.1066688553
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/194.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/195.prim_prince_test.575563957
Short name T226
Test name
Test status
Simulation time 3511946850 ps
CPU time 71.77 seconds
Started Aug 25 12:17:49 AM UTC 24
Finished Aug 25 12:19:21 AM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=575563957 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 195.prim_prince_test.575563957
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/195.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/196.prim_prince_test.3963118787
Short name T162
Test name
Test status
Simulation time 876724895 ps
CPU time 18.38 seconds
Started Aug 25 12:17:50 AM UTC 24
Finished Aug 25 12:18:14 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3963118787 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 196.prim_prince_test.3963118787
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/196.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/197.prim_prince_test.1757170948
Short name T217
Test name
Test status
Simulation time 3001966666 ps
CPU time 61.13 seconds
Started Aug 25 12:17:50 AM UTC 24
Finished Aug 25 12:19:08 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1757170948 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 197.prim_prince_test.1757170948
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/197.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/198.prim_prince_test.141243500
Short name T193
Test name
Test status
Simulation time 1934878662 ps
CPU time 39.75 seconds
Started Aug 25 12:17:50 AM UTC 24
Finished Aug 25 12:18:41 AM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=141243500 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 198.prim_prince_test.141243500
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/198.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/199.prim_prince_test.3919616980
Short name T228
Test name
Test status
Simulation time 3394181087 ps
CPU time 69.64 seconds
Started Aug 25 12:17:52 AM UTC 24
Finished Aug 25 12:19:22 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3919616980 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 199.prim_prince_test.3919616980
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/199.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/2.prim_prince_test.2384687454
Short name T19
Test name
Test status
Simulation time 2169500238 ps
CPU time 45.84 seconds
Started Aug 25 12:14:23 AM UTC 24
Finished Aug 25 12:15:25 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2384687454 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 2.prim_prince_test.2384687454
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/2.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/20.prim_prince_test.2921548796
Short name T15
Test name
Test status
Simulation time 1779087656 ps
CPU time 37.68 seconds
Started Aug 25 12:14:31 AM UTC 24
Finished Aug 25 12:15:22 AM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2921548796 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 20.prim_prince_test.2921548796
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/20.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/200.prim_prince_test.2207411175
Short name T184
Test name
Test status
Simulation time 1684415022 ps
CPU time 34.73 seconds
Started Aug 25 12:17:52 AM UTC 24
Finished Aug 25 12:18:37 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2207411175 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 200.prim_prince_test.2207411175
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/200.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/201.prim_prince_test.578051028
Short name T174
Test name
Test status
Simulation time 1189699253 ps
CPU time 24.69 seconds
Started Aug 25 12:17:55 AM UTC 24
Finished Aug 25 12:18:28 AM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=578051028 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 201.prim_prince_test.578051028
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/201.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/202.prim_prince_test.109091544
Short name T236
Test name
Test status
Simulation time 3430200017 ps
CPU time 69.91 seconds
Started Aug 25 12:17:57 AM UTC 24
Finished Aug 25 12:19:26 AM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=109091544 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 202.prim_prince_test.109091544
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/202.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/203.prim_prince_test.2239000828
Short name T208
Test name
Test status
Simulation time 2107036621 ps
CPU time 43.66 seconds
Started Aug 25 12:17:57 AM UTC 24
Finished Aug 25 12:18:53 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2239000828 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 203.prim_prince_test.2239000828
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/203.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/204.prim_prince_test.1370595528
Short name T192
Test name
Test status
Simulation time 1546921071 ps
CPU time 32.12 seconds
Started Aug 25 12:18:00 AM UTC 24
Finished Aug 25 12:18:41 AM UTC 24
Peak memory 156056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1370595528 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 204.prim_prince_test.1370595528
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/204.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/205.prim_prince_test.3466376217
Short name T205
Test name
Test status
Simulation time 1877680372 ps
CPU time 38.69 seconds
Started Aug 25 12:18:00 AM UTC 24
Finished Aug 25 12:18:50 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3466376217 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 205.prim_prince_test.3466376217
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/205.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/206.prim_prince_test.2110299261
Short name T176
Test name
Test status
Simulation time 1010828177 ps
CPU time 21.19 seconds
Started Aug 25 12:18:00 AM UTC 24
Finished Aug 25 12:18:28 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2110299261 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 206.prim_prince_test.2110299261
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/206.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/207.prim_prince_test.276394696
Short name T232
Test name
Test status
Simulation time 3086615134 ps
CPU time 63.52 seconds
Started Aug 25 12:18:02 AM UTC 24
Finished Aug 25 12:19:24 AM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=276394696 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 207.prim_prince_test.276394696
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/207.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/208.prim_prince_test.2991454304
Short name T202
Test name
Test status
Simulation time 1670484286 ps
CPU time 34.52 seconds
Started Aug 25 12:18:02 AM UTC 24
Finished Aug 25 12:18:47 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2991454304 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 208.prim_prince_test.2991454304
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/208.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/209.prim_prince_test.2528360597
Short name T249
Test name
Test status
Simulation time 3724270952 ps
CPU time 76.28 seconds
Started Aug 25 12:18:03 AM UTC 24
Finished Aug 25 12:19:41 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2528360597 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 209.prim_prince_test.2528360597
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/209.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/21.prim_prince_test.608676898
Short name T11
Test name
Test status
Simulation time 1507716204 ps
CPU time 32.16 seconds
Started Aug 25 12:14:31 AM UTC 24
Finished Aug 25 12:15:15 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=608676898 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 21.prim_prince_test.608676898
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/21.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/210.prim_prince_test.411132127
Short name T246
Test name
Test status
Simulation time 3618431864 ps
CPU time 73.77 seconds
Started Aug 25 12:18:04 AM UTC 24
Finished Aug 25 12:19:38 AM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=411132127 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 210.prim_prince_test.411132127
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/210.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/211.prim_prince_test.3687493278
Short name T241
Test name
Test status
Simulation time 3260338664 ps
CPU time 66.56 seconds
Started Aug 25 12:18:06 AM UTC 24
Finished Aug 25 12:19:31 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3687493278 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 211.prim_prince_test.3687493278
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/211.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/212.prim_prince_test.291331084
Short name T247
Test name
Test status
Simulation time 3626712480 ps
CPU time 73.87 seconds
Started Aug 25 12:18:06 AM UTC 24
Finished Aug 25 12:19:40 AM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=291331084 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 212.prim_prince_test.291331084
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/212.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/213.prim_prince_test.3757204054
Short name T189
Test name
Test status
Simulation time 1251280143 ps
CPU time 25.85 seconds
Started Aug 25 12:18:06 AM UTC 24
Finished Aug 25 12:18:40 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3757204054 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 213.prim_prince_test.3757204054
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/213.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/214.prim_prince_test.1350794108
Short name T214
Test name
Test status
Simulation time 2347739595 ps
CPU time 48.05 seconds
Started Aug 25 12:18:06 AM UTC 24
Finished Aug 25 12:19:08 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1350794108 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 214.prim_prince_test.1350794108
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/214.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/215.prim_prince_test.4106270571
Short name T243
Test name
Test status
Simulation time 3399230303 ps
CPU time 69.45 seconds
Started Aug 25 12:18:07 AM UTC 24
Finished Aug 25 12:19:36 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4106270571 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 215.prim_prince_test.4106270571
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/215.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/216.prim_prince_test.3895404483
Short name T199
Test name
Test status
Simulation time 1327725610 ps
CPU time 27.69 seconds
Started Aug 25 12:18:07 AM UTC 24
Finished Aug 25 12:18:43 AM UTC 24
Peak memory 154088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3895404483 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 216.prim_prince_test.3895404483
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/216.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/217.prim_prince_test.2769124373
Short name T180
Test name
Test status
Simulation time 940231106 ps
CPU time 19.66 seconds
Started Aug 25 12:18:07 AM UTC 24
Finished Aug 25 12:18:33 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2769124373 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 217.prim_prince_test.2769124373
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/217.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/218.prim_prince_test.3703843890
Short name T198
Test name
Test status
Simulation time 1210943916 ps
CPU time 25.01 seconds
Started Aug 25 12:18:10 AM UTC 24
Finished Aug 25 12:18:43 AM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3703843890 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 218.prim_prince_test.3703843890
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/218.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/219.prim_prince_test.818794332
Short name T190
Test name
Test status
Simulation time 1095078942 ps
CPU time 22.82 seconds
Started Aug 25 12:18:10 AM UTC 24
Finished Aug 25 12:18:40 AM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=818794332 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 219.prim_prince_test.818794332
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/219.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/22.prim_prince_test.2917613716
Short name T58
Test name
Test status
Simulation time 3612686642 ps
CPU time 75.36 seconds
Started Aug 25 12:14:32 AM UTC 24
Finished Aug 25 12:16:12 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2917613716 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 22.prim_prince_test.2917613716
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/22.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/220.prim_prince_test.1636289881
Short name T211
Test name
Test status
Simulation time 1973928478 ps
CPU time 40.85 seconds
Started Aug 25 12:18:12 AM UTC 24
Finished Aug 25 12:19:04 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1636289881 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 220.prim_prince_test.1636289881
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/220.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/221.prim_prince_test.792370991
Short name T250
Test name
Test status
Simulation time 3514190855 ps
CPU time 71.57 seconds
Started Aug 25 12:18:12 AM UTC 24
Finished Aug 25 12:19:43 AM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=792370991 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 221.prim_prince_test.792370991
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/221.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/222.prim_prince_test.1288244263
Short name T209
Test name
Test status
Simulation time 1817616334 ps
CPU time 37.29 seconds
Started Aug 25 12:18:13 AM UTC 24
Finished Aug 25 12:19:01 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1288244263 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 222.prim_prince_test.1288244263
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/222.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/223.prim_prince_test.3641120317
Short name T218
Test name
Test status
Simulation time 2083867990 ps
CPU time 43.06 seconds
Started Aug 25 12:18:13 AM UTC 24
Finished Aug 25 12:19:09 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3641120317 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 223.prim_prince_test.3641120317
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/223.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/224.prim_prince_test.4119628793
Short name T230
Test name
Test status
Simulation time 2598047388 ps
CPU time 53.12 seconds
Started Aug 25 12:18:14 AM UTC 24
Finished Aug 25 12:19:23 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4119628793 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 224.prim_prince_test.4119628793
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/224.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/225.prim_prince_test.3803347761
Short name T225
Test name
Test status
Simulation time 2431567806 ps
CPU time 49.46 seconds
Started Aug 25 12:18:15 AM UTC 24
Finished Aug 25 12:19:19 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3803347761 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 225.prim_prince_test.3803347761
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/225.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/226.prim_prince_test.3644321111
Short name T221
Test name
Test status
Simulation time 2235041402 ps
CPU time 45.74 seconds
Started Aug 25 12:18:15 AM UTC 24
Finished Aug 25 12:19:15 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3644321111 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 226.prim_prince_test.3644321111
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/226.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/227.prim_prince_test.670065206
Short name T220
Test name
Test status
Simulation time 2202466488 ps
CPU time 45.15 seconds
Started Aug 25 12:18:15 AM UTC 24
Finished Aug 25 12:19:14 AM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=670065206 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 227.prim_prince_test.670065206
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/227.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/228.prim_prince_test.2257470530
Short name T244
Test name
Test status
Simulation time 3053044731 ps
CPU time 62.39 seconds
Started Aug 25 12:18:17 AM UTC 24
Finished Aug 25 12:19:36 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2257470530 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 228.prim_prince_test.2257470530
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/228.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/229.prim_prince_test.1957602685
Short name T201
Test name
Test status
Simulation time 954171454 ps
CPU time 19.73 seconds
Started Aug 25 12:18:20 AM UTC 24
Finished Aug 25 12:18:46 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1957602685 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 229.prim_prince_test.1957602685
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/229.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/23.prim_prince_test.600074256
Short name T5
Test name
Test status
Simulation time 1090113267 ps
CPU time 23.75 seconds
Started Aug 25 12:14:32 AM UTC 24
Finished Aug 25 12:15:04 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=600074256 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 23.prim_prince_test.600074256
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/23.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/230.prim_prince_test.1220229641
Short name T264
Test name
Test status
Simulation time 3514016185 ps
CPU time 72.56 seconds
Started Aug 25 12:18:21 AM UTC 24
Finished Aug 25 12:19:54 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1220229641 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 230.prim_prince_test.1220229641
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/230.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/231.prim_prince_test.3207830148
Short name T222
Test name
Test status
Simulation time 1982434912 ps
CPU time 40.74 seconds
Started Aug 25 12:18:22 AM UTC 24
Finished Aug 25 12:19:15 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3207830148 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 231.prim_prince_test.3207830148
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/231.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/232.prim_prince_test.2595564341
Short name T215
Test name
Test status
Simulation time 1719560499 ps
CPU time 35.22 seconds
Started Aug 25 12:18:22 AM UTC 24
Finished Aug 25 12:19:08 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2595564341 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 232.prim_prince_test.2595564341
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/232.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/233.prim_prince_test.1660909500
Short name T210
Test name
Test status
Simulation time 1474880721 ps
CPU time 30.44 seconds
Started Aug 25 12:18:24 AM UTC 24
Finished Aug 25 12:19:04 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1660909500 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 233.prim_prince_test.1660909500
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/233.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/234.prim_prince_test.3087409569
Short name T267
Test name
Test status
Simulation time 3455020086 ps
CPU time 70.37 seconds
Started Aug 25 12:18:25 AM UTC 24
Finished Aug 25 12:19:55 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3087409569 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 234.prim_prince_test.3087409569
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/234.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/235.prim_prince_test.2307588267
Short name T204
Test name
Test status
Simulation time 875991604 ps
CPU time 18.18 seconds
Started Aug 25 12:18:26 AM UTC 24
Finished Aug 25 12:18:50 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2307588267 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 235.prim_prince_test.2307588267
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/235.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/236.prim_prince_test.1925325583
Short name T248
Test name
Test status
Simulation time 2827276938 ps
CPU time 57.8 seconds
Started Aug 25 12:18:27 AM UTC 24
Finished Aug 25 12:19:41 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1925325583 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 236.prim_prince_test.1925325583
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/236.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/237.prim_prince_test.1008645821
Short name T234
Test name
Test status
Simulation time 2103494438 ps
CPU time 43.11 seconds
Started Aug 25 12:18:29 AM UTC 24
Finished Aug 25 12:19:24 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1008645821 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 237.prim_prince_test.1008645821
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/237.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/238.prim_prince_test.2777294863
Short name T270
Test name
Test status
Simulation time 3361963298 ps
CPU time 68.77 seconds
Started Aug 25 12:18:29 AM UTC 24
Finished Aug 25 12:19:57 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2777294863 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 238.prim_prince_test.2777294863
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/238.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/239.prim_prince_test.3254924335
Short name T256
Test name
Test status
Simulation time 3064516750 ps
CPU time 62.46 seconds
Started Aug 25 12:18:29 AM UTC 24
Finished Aug 25 12:19:49 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3254924335 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 239.prim_prince_test.3254924335
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/239.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/24.prim_prince_test.565212873
Short name T54
Test name
Test status
Simulation time 3460891222 ps
CPU time 72.37 seconds
Started Aug 25 12:14:34 AM UTC 24
Finished Aug 25 12:16:10 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=565212873 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 24.prim_prince_test.565212873
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/24.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/240.prim_prince_test.2148781232
Short name T224
Test name
Test status
Simulation time 1742352858 ps
CPU time 35.73 seconds
Started Aug 25 12:18:30 AM UTC 24
Finished Aug 25 12:19:16 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2148781232 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 240.prim_prince_test.2148781232
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/240.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/241.prim_prince_test.3589517972
Short name T265
Test name
Test status
Simulation time 3232876414 ps
CPU time 65.76 seconds
Started Aug 25 12:18:30 AM UTC 24
Finished Aug 25 12:19:54 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3589517972 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 241.prim_prince_test.3589517972
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/241.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/242.prim_prince_test.3346234504
Short name T277
Test name
Test status
Simulation time 3418593090 ps
CPU time 69.92 seconds
Started Aug 25 12:18:32 AM UTC 24
Finished Aug 25 12:20:01 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3346234504 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 242.prim_prince_test.3346234504
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/242.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/243.prim_prince_test.428360022
Short name T268
Test name
Test status
Simulation time 3225003533 ps
CPU time 65.78 seconds
Started Aug 25 12:18:32 AM UTC 24
Finished Aug 25 12:19:56 AM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=428360022 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 243.prim_prince_test.428360022
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/243.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/244.prim_prince_test.2557491355
Short name T272
Test name
Test status
Simulation time 3286888328 ps
CPU time 67.04 seconds
Started Aug 25 12:18:32 AM UTC 24
Finished Aug 25 12:19:57 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2557491355 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 244.prim_prince_test.2557491355
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/244.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/245.prim_prince_test.4167486776
Short name T254
Test name
Test status
Simulation time 2734798552 ps
CPU time 55.84 seconds
Started Aug 25 12:18:34 AM UTC 24
Finished Aug 25 12:19:46 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4167486776 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 245.prim_prince_test.4167486776
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/245.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/246.prim_prince_test.728218748
Short name T273
Test name
Test status
Simulation time 3198862229 ps
CPU time 64.97 seconds
Started Aug 25 12:18:35 AM UTC 24
Finished Aug 25 12:19:59 AM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=728218748 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 246.prim_prince_test.728218748
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/246.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/247.prim_prince_test.2467424956
Short name T212
Test name
Test status
Simulation time 1144419729 ps
CPU time 23.93 seconds
Started Aug 25 12:18:35 AM UTC 24
Finished Aug 25 12:19:07 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2467424956 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 247.prim_prince_test.2467424956
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/247.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/248.prim_prince_test.1750702782
Short name T229
Test name
Test status
Simulation time 1759250578 ps
CPU time 36.02 seconds
Started Aug 25 12:18:35 AM UTC 24
Finished Aug 25 12:19:22 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1750702782 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 248.prim_prince_test.1750702782
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/248.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/249.prim_prince_test.1330736854
Short name T269
Test name
Test status
Simulation time 3014366706 ps
CPU time 61.68 seconds
Started Aug 25 12:18:36 AM UTC 24
Finished Aug 25 12:19:56 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1330736854 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 249.prim_prince_test.1330736854
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/249.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/25.prim_prince_test.395725930
Short name T20
Test name
Test status
Simulation time 1803917543 ps
CPU time 38.06 seconds
Started Aug 25 12:14:35 AM UTC 24
Finished Aug 25 12:15:26 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=395725930 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 25.prim_prince_test.395725930
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/25.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/250.prim_prince_test.1754451258
Short name T266
Test name
Test status
Simulation time 2930292601 ps
CPU time 59.45 seconds
Started Aug 25 12:18:39 AM UTC 24
Finished Aug 25 12:19:55 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1754451258 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 250.prim_prince_test.1754451258
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/250.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/251.prim_prince_test.2548093495
Short name T233
Test name
Test status
Simulation time 1684129316 ps
CPU time 34.77 seconds
Started Aug 25 12:18:39 AM UTC 24
Finished Aug 25 12:19:24 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2548093495 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 251.prim_prince_test.2548093495
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/251.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/252.prim_prince_test.298690866
Short name T251
Test name
Test status
Simulation time 2428925441 ps
CPU time 49.86 seconds
Started Aug 25 12:18:40 AM UTC 24
Finished Aug 25 12:19:44 AM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=298690866 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 252.prim_prince_test.298690866
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/252.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/253.prim_prince_test.2791316676
Short name T279
Test name
Test status
Simulation time 3249855103 ps
CPU time 66.37 seconds
Started Aug 25 12:18:40 AM UTC 24
Finished Aug 25 12:20:05 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2791316676 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 253.prim_prince_test.2791316676
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/253.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/254.prim_prince_test.3435601662
Short name T274
Test name
Test status
Simulation time 3026234345 ps
CPU time 61.74 seconds
Started Aug 25 12:18:40 AM UTC 24
Finished Aug 25 12:19:59 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3435601662 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 254.prim_prince_test.3435601662
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/254.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/255.prim_prince_test.688824422
Short name T258
Test name
Test status
Simulation time 2712392013 ps
CPU time 55.66 seconds
Started Aug 25 12:18:40 AM UTC 24
Finished Aug 25 12:19:52 AM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=688824422 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 255.prim_prince_test.688824422
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/255.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/256.prim_prince_test.2407804555
Short name T257
Test name
Test status
Simulation time 2649558947 ps
CPU time 54.24 seconds
Started Aug 25 12:18:41 AM UTC 24
Finished Aug 25 12:19:51 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2407804555 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 256.prim_prince_test.2407804555
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/256.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/257.prim_prince_test.2743965157
Short name T260
Test name
Test status
Simulation time 2710284333 ps
CPU time 55.66 seconds
Started Aug 25 12:18:41 AM UTC 24
Finished Aug 25 12:19:52 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2743965157 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 257.prim_prince_test.2743965157
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/257.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/258.prim_prince_test.2632153579
Short name T287
Test name
Test status
Simulation time 3477789313 ps
CPU time 70.63 seconds
Started Aug 25 12:18:43 AM UTC 24
Finished Aug 25 12:20:13 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2632153579 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 258.prim_prince_test.2632153579
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/258.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/259.prim_prince_test.4200371397
Short name T223
Test name
Test status
Simulation time 1241100214 ps
CPU time 25.6 seconds
Started Aug 25 12:18:43 AM UTC 24
Finished Aug 25 12:19:16 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4200371397 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 259.prim_prince_test.4200371397
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/259.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/26.prim_prince_test.2967263258
Short name T44
Test name
Test status
Simulation time 2997856965 ps
CPU time 62.8 seconds
Started Aug 25 12:14:37 AM UTC 24
Finished Aug 25 12:16:01 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2967263258 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 26.prim_prince_test.2967263258
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/26.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/260.prim_prince_test.3242525059
Short name T278
Test name
Test status
Simulation time 3151084588 ps
CPU time 63.93 seconds
Started Aug 25 12:18:43 AM UTC 24
Finished Aug 25 12:20:04 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3242525059 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 260.prim_prince_test.3242525059
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/260.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/261.prim_prince_test.4026435369
Short name T239
Test name
Test status
Simulation time 1731460840 ps
CPU time 35.51 seconds
Started Aug 25 12:18:43 AM UTC 24
Finished Aug 25 12:19:29 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4026435369 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 261.prim_prince_test.4026435369
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/261.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/262.prim_prince_test.2893209356
Short name T261
Test name
Test status
Simulation time 2635083570 ps
CPU time 53.64 seconds
Started Aug 25 12:18:44 AM UTC 24
Finished Aug 25 12:19:53 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2893209356 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 262.prim_prince_test.2893209356
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/262.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/263.prim_prince_test.212886841
Short name T219
Test name
Test status
Simulation time 1091400423 ps
CPU time 22.71 seconds
Started Aug 25 12:18:44 AM UTC 24
Finished Aug 25 12:19:14 AM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=212886841 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 263.prim_prince_test.212886841
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/263.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/264.prim_prince_test.2235907679
Short name T240
Test name
Test status
Simulation time 1757455051 ps
CPU time 36.1 seconds
Started Aug 25 12:18:44 AM UTC 24
Finished Aug 25 12:19:31 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2235907679 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 264.prim_prince_test.2235907679
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/264.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/265.prim_prince_test.3322202617
Short name T297
Test name
Test status
Simulation time 3586797830 ps
CPU time 72.81 seconds
Started Aug 25 12:18:46 AM UTC 24
Finished Aug 25 12:20:19 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3322202617 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 265.prim_prince_test.3322202617
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/265.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/266.prim_prince_test.1737087643
Short name T237
Test name
Test status
Simulation time 1467577984 ps
CPU time 30.51 seconds
Started Aug 25 12:18:47 AM UTC 24
Finished Aug 25 12:19:27 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1737087643 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 266.prim_prince_test.1737087643
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/266.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/267.prim_prince_test.1707543562
Short name T275
Test name
Test status
Simulation time 2757157020 ps
CPU time 56.51 seconds
Started Aug 25 12:18:48 AM UTC 24
Finished Aug 25 12:20:01 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1707543562 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 267.prim_prince_test.1707543562
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/267.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/268.prim_prince_test.645280900
Short name T296
Test name
Test status
Simulation time 3469399723 ps
CPU time 70.23 seconds
Started Aug 25 12:18:49 AM UTC 24
Finished Aug 25 12:20:19 AM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=645280900 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 268.prim_prince_test.645280900
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/268.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/269.prim_prince_test.3834905292
Short name T292
Test name
Test status
Simulation time 3414319107 ps
CPU time 68.9 seconds
Started Aug 25 12:18:51 AM UTC 24
Finished Aug 25 12:20:19 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3834905292 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 269.prim_prince_test.3834905292
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/269.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/27.prim_prince_test.3524800683
Short name T55
Test name
Test status
Simulation time 3396347454 ps
CPU time 70.36 seconds
Started Aug 25 12:14:37 AM UTC 24
Finished Aug 25 12:16:11 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3524800683 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 27.prim_prince_test.3524800683
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/27.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/270.prim_prince_test.4289566467
Short name T284
Test name
Test status
Simulation time 3095919144 ps
CPU time 63 seconds
Started Aug 25 12:18:51 AM UTC 24
Finished Aug 25 12:20:11 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4289566467 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 270.prim_prince_test.4289566467
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/270.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/271.prim_prince_test.1812566351
Short name T227
Test name
Test status
Simulation time 1034426500 ps
CPU time 21.53 seconds
Started Aug 25 12:18:53 AM UTC 24
Finished Aug 25 12:19:21 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1812566351 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 271.prim_prince_test.1812566351
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/271.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/272.prim_prince_test.1797647551
Short name T242
Test name
Test status
Simulation time 1539913897 ps
CPU time 31.68 seconds
Started Aug 25 12:18:54 AM UTC 24
Finished Aug 25 12:19:35 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1797647551 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 272.prim_prince_test.1797647551
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/272.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/273.prim_prince_test.702791465
Short name T290
Test name
Test status
Simulation time 3141780640 ps
CPU time 63.91 seconds
Started Aug 25 12:18:54 AM UTC 24
Finished Aug 25 12:20:16 AM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=702791465 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 273.prim_prince_test.702791465
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/273.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/274.prim_prince_test.1658147185
Short name T253
Test name
Test status
Simulation time 1619170983 ps
CPU time 33.13 seconds
Started Aug 25 12:19:02 AM UTC 24
Finished Aug 25 12:19:45 AM UTC 24
Peak memory 154504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1658147185 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 274.prim_prince_test.1658147185
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/274.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/275.prim_prince_test.3086324878
Short name T259
Test name
Test status
Simulation time 1871519401 ps
CPU time 38.59 seconds
Started Aug 25 12:19:02 AM UTC 24
Finished Aug 25 12:19:52 AM UTC 24
Peak memory 154484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3086324878 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 275.prim_prince_test.3086324878
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/275.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/276.prim_prince_test.867034410
Short name T238
Test name
Test status
Simulation time 843954231 ps
CPU time 17.75 seconds
Started Aug 25 12:19:05 AM UTC 24
Finished Aug 25 12:19:28 AM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=867034410 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 276.prim_prince_test.867034410
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/276.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/277.prim_prince_test.432908822
Short name T263
Test name
Test status
Simulation time 1779587945 ps
CPU time 36.74 seconds
Started Aug 25 12:19:06 AM UTC 24
Finished Aug 25 12:19:53 AM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=432908822 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 277.prim_prince_test.432908822
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/277.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/278.prim_prince_test.3144587060
Short name T316
Test name
Test status
Simulation time 3361329744 ps
CPU time 68.44 seconds
Started Aug 25 12:19:08 AM UTC 24
Finished Aug 25 12:20:35 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3144587060 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 278.prim_prince_test.3144587060
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/278.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/279.prim_prince_test.329703672
Short name T280
Test name
Test status
Simulation time 2205186988 ps
CPU time 45.06 seconds
Started Aug 25 12:19:09 AM UTC 24
Finished Aug 25 12:20:07 AM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=329703672 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 279.prim_prince_test.329703672
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/279.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/28.prim_prince_test.3563791177
Short name T13
Test name
Test status
Simulation time 1522294313 ps
CPU time 32.02 seconds
Started Aug 25 12:14:37 AM UTC 24
Finished Aug 25 12:15:21 AM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3563791177 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 28.prim_prince_test.3563791177
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/28.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/280.prim_prince_test.3621569143
Short name T299
Test name
Test status
Simulation time 2755775212 ps
CPU time 56.31 seconds
Started Aug 25 12:19:09 AM UTC 24
Finished Aug 25 12:20:21 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3621569143 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 280.prim_prince_test.3621569143
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/280.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/281.prim_prince_test.432448407
Short name T245
Test name
Test status
Simulation time 1035897211 ps
CPU time 21.63 seconds
Started Aug 25 12:19:09 AM UTC 24
Finished Aug 25 12:19:38 AM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=432448407 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 281.prim_prince_test.432448407
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/281.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/282.prim_prince_test.506750051
Short name T291
Test name
Test status
Simulation time 2603860094 ps
CPU time 52.96 seconds
Started Aug 25 12:19:09 AM UTC 24
Finished Aug 25 12:20:17 AM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=506750051 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 282.prim_prince_test.506750051
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/282.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/283.prim_prince_test.1993580210
Short name T271
Test name
Test status
Simulation time 1815674716 ps
CPU time 37.16 seconds
Started Aug 25 12:19:10 AM UTC 24
Finished Aug 25 12:19:57 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1993580210 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 283.prim_prince_test.1993580210
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/283.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/284.prim_prince_test.4189216456
Short name T301
Test name
Test status
Simulation time 2950251831 ps
CPU time 59.35 seconds
Started Aug 25 12:19:10 AM UTC 24
Finished Aug 25 12:20:25 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4189216456 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 284.prim_prince_test.4189216456
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/284.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/285.prim_prince_test.2792434608
Short name T255
Test name
Test status
Simulation time 1168436501 ps
CPU time 24.17 seconds
Started Aug 25 12:19:15 AM UTC 24
Finished Aug 25 12:19:46 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2792434608 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 285.prim_prince_test.2792434608
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/285.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/286.prim_prince_test.2016103361
Short name T252
Test name
Test status
Simulation time 1106943224 ps
CPU time 22.76 seconds
Started Aug 25 12:19:15 AM UTC 24
Finished Aug 25 12:19:44 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2016103361 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 286.prim_prince_test.2016103361
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/286.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/287.prim_prince_test.1110672443
Short name T312
Test name
Test status
Simulation time 3008842463 ps
CPU time 60.63 seconds
Started Aug 25 12:19:16 AM UTC 24
Finished Aug 25 12:20:34 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1110672443 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 287.prim_prince_test.1110672443
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/287.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/288.prim_prince_test.2667833768
Short name T309
Test name
Test status
Simulation time 2873346377 ps
CPU time 58.07 seconds
Started Aug 25 12:19:16 AM UTC 24
Finished Aug 25 12:20:30 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2667833768 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 288.prim_prince_test.2667833768
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/288.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/289.prim_prince_test.2832383695
Short name T306
Test name
Test status
Simulation time 2796243688 ps
CPU time 56.53 seconds
Started Aug 25 12:19:17 AM UTC 24
Finished Aug 25 12:20:29 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2832383695 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 289.prim_prince_test.2832383695
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/289.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/29.prim_prince_test.3920110489
Short name T32
Test name
Test status
Simulation time 2447709994 ps
CPU time 51.1 seconds
Started Aug 25 12:14:37 AM UTC 24
Finished Aug 25 12:15:46 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3920110489 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 29.prim_prince_test.3920110489
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/29.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/290.prim_prince_test.1280017642
Short name T294
Test name
Test status
Simulation time 2357538910 ps
CPU time 48.26 seconds
Started Aug 25 12:19:17 AM UTC 24
Finished Aug 25 12:20:19 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1280017642 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 290.prim_prince_test.1280017642
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/290.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/291.prim_prince_test.3924588271
Short name T305
Test name
Test status
Simulation time 2595800615 ps
CPU time 52.69 seconds
Started Aug 25 12:19:20 AM UTC 24
Finished Aug 25 12:20:28 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3924588271 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 291.prim_prince_test.3924588271
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/291.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/292.prim_prince_test.985941816
Short name T313
Test name
Test status
Simulation time 2797244255 ps
CPU time 56.69 seconds
Started Aug 25 12:19:22 AM UTC 24
Finished Aug 25 12:20:34 AM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=985941816 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 292.prim_prince_test.985941816
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/292.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/293.prim_prince_test.2564704594
Short name T286
Test name
Test status
Simulation time 1936553396 ps
CPU time 39.51 seconds
Started Aug 25 12:19:22 AM UTC 24
Finished Aug 25 12:20:12 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2564704594 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 293.prim_prince_test.2564704594
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/293.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/294.prim_prince_test.213342143
Short name T341
Test name
Test status
Simulation time 3632679858 ps
CPU time 73.26 seconds
Started Aug 25 12:19:23 AM UTC 24
Finished Aug 25 12:20:56 AM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=213342143 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 294.prim_prince_test.213342143
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/294.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/295.prim_prince_test.4101800004
Short name T196
Test name
Test status
Simulation time 782934383 ps
CPU time 16.36 seconds
Started Aug 25 12:19:23 AM UTC 24
Finished Aug 25 12:19:44 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4101800004 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 295.prim_prince_test.4101800004
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/295.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/296.prim_prince_test.745140798
Short name T325
Test name
Test status
Simulation time 3078484801 ps
CPU time 62.19 seconds
Started Aug 25 12:19:24 AM UTC 24
Finished Aug 25 12:20:44 AM UTC 24
Peak memory 154524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=745140798 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 296.prim_prince_test.745140798
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/296.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/297.prim_prince_test.3134799805
Short name T303
Test name
Test status
Simulation time 2435251280 ps
CPU time 49.32 seconds
Started Aug 25 12:19:24 AM UTC 24
Finished Aug 25 12:20:27 AM UTC 24
Peak memory 154440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3134799805 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 297.prim_prince_test.3134799805
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/297.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/298.prim_prince_test.2482639199
Short name T262
Test name
Test status
Simulation time 1051228373 ps
CPU time 21.68 seconds
Started Aug 25 12:19:24 AM UTC 24
Finished Aug 25 12:19:53 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2482639199 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 298.prim_prince_test.2482639199
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/298.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/299.prim_prince_test.3546282570
Short name T285
Test name
Test status
Simulation time 1789014482 ps
CPU time 36.87 seconds
Started Aug 25 12:19:24 AM UTC 24
Finished Aug 25 12:20:12 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3546282570 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 299.prim_prince_test.3546282570
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/299.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/3.prim_prince_test.243329605
Short name T21
Test name
Test status
Simulation time 2337265443 ps
CPU time 49.36 seconds
Started Aug 25 12:14:23 AM UTC 24
Finished Aug 25 12:15:30 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=243329605 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 3.prim_prince_test.243329605
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/3.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/30.prim_prince_test.152506219
Short name T8
Test name
Test status
Simulation time 990411701 ps
CPU time 21.06 seconds
Started Aug 25 12:14:37 AM UTC 24
Finished Aug 25 12:15:06 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=152506219 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 30.prim_prince_test.152506219
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/30.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/300.prim_prince_test.4208036261
Short name T337
Test name
Test status
Simulation time 3369992176 ps
CPU time 68.46 seconds
Started Aug 25 12:19:26 AM UTC 24
Finished Aug 25 12:20:53 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4208036261 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 300.prim_prince_test.4208036261
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/300.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/301.prim_prince_test.3438770136
Short name T323
Test name
Test status
Simulation time 2960351304 ps
CPU time 60.07 seconds
Started Aug 25 12:19:26 AM UTC 24
Finished Aug 25 12:20:43 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3438770136 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 301.prim_prince_test.3438770136
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/301.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/302.prim_prince_test.1398232127
Short name T293
Test name
Test status
Simulation time 1977764450 ps
CPU time 40.38 seconds
Started Aug 25 12:19:27 AM UTC 24
Finished Aug 25 12:20:19 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1398232127 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 302.prim_prince_test.1398232127
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/302.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/303.prim_prince_test.3123822089
Short name T307
Test name
Test status
Simulation time 2378819319 ps
CPU time 47.99 seconds
Started Aug 25 12:19:28 AM UTC 24
Finished Aug 25 12:20:29 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3123822089 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 303.prim_prince_test.3123822089
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/303.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/304.prim_prince_test.1763416495
Short name T300
Test name
Test status
Simulation time 2014136883 ps
CPU time 40.82 seconds
Started Aug 25 12:19:29 AM UTC 24
Finished Aug 25 12:20:21 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1763416495 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 304.prim_prince_test.1763416495
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/304.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/305.prim_prince_test.3368075035
Short name T310
Test name
Test status
Simulation time 2435643242 ps
CPU time 49.22 seconds
Started Aug 25 12:19:29 AM UTC 24
Finished Aug 25 12:20:32 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3368075035 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 305.prim_prince_test.3368075035
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/305.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/306.prim_prince_test.1077793306
Short name T283
Test name
Test status
Simulation time 1450355922 ps
CPU time 29.65 seconds
Started Aug 25 12:19:31 AM UTC 24
Finished Aug 25 12:20:10 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1077793306 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 306.prim_prince_test.1077793306
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/306.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/307.prim_prince_test.2770455071
Short name T317
Test name
Test status
Simulation time 2414266311 ps
CPU time 48.85 seconds
Started Aug 25 12:19:32 AM UTC 24
Finished Aug 25 12:20:35 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2770455071 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 307.prim_prince_test.2770455071
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/307.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/308.prim_prince_test.3239490159
Short name T288
Test name
Test status
Simulation time 1449048521 ps
CPU time 29.64 seconds
Started Aug 25 12:19:35 AM UTC 24
Finished Aug 25 12:20:13 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3239490159 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 308.prim_prince_test.3239490159
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/308.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/309.prim_prince_test.4178358205
Short name T321
Test name
Test status
Simulation time 2414141510 ps
CPU time 48.78 seconds
Started Aug 25 12:19:36 AM UTC 24
Finished Aug 25 12:20:38 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4178358205 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 309.prim_prince_test.4178358205
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/309.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/31.prim_prince_test.2333620059
Short name T33
Test name
Test status
Simulation time 2568102044 ps
CPU time 53.73 seconds
Started Aug 25 12:14:37 AM UTC 24
Finished Aug 25 12:15:49 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2333620059 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 31.prim_prince_test.2333620059
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/31.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/310.prim_prince_test.1590609279
Short name T357
Test name
Test status
Simulation time 3690724401 ps
CPU time 74.6 seconds
Started Aug 25 12:19:37 AM UTC 24
Finished Aug 25 12:21:12 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1590609279 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 310.prim_prince_test.1590609279
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/310.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/311.prim_prince_test.35597279
Short name T353
Test name
Test status
Simulation time 3614669523 ps
CPU time 72.73 seconds
Started Aug 25 12:19:37 AM UTC 24
Finished Aug 25 12:21:10 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=35597279 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 311.prim_prince_test.35597279
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/311.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/312.prim_prince_test.1596303983
Short name T329
Test name
Test status
Simulation time 2685142372 ps
CPU time 54.84 seconds
Started Aug 25 12:19:38 AM UTC 24
Finished Aug 25 12:20:48 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1596303983 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 312.prim_prince_test.1596303983
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/312.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/313.prim_prince_test.4044780853
Short name T344
Test name
Test status
Simulation time 3219216568 ps
CPU time 64.85 seconds
Started Aug 25 12:19:38 AM UTC 24
Finished Aug 25 12:21:01 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4044780853 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 313.prim_prince_test.4044780853
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/313.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/314.prim_prince_test.3062747490
Short name T359
Test name
Test status
Simulation time 3599754791 ps
CPU time 72.56 seconds
Started Aug 25 12:19:42 AM UTC 24
Finished Aug 25 12:21:14 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3062747490 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 314.prim_prince_test.3062747490
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/314.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/315.prim_prince_test.3745983597
Short name T364
Test name
Test status
Simulation time 3691659924 ps
CPU time 74.59 seconds
Started Aug 25 12:19:42 AM UTC 24
Finished Aug 25 12:21:16 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3745983597 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 315.prim_prince_test.3745983597
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/315.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/316.prim_prince_test.240112523
Short name T330
Test name
Test status
Simulation time 2608952065 ps
CPU time 52.66 seconds
Started Aug 25 12:19:42 AM UTC 24
Finished Aug 25 12:20:49 AM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=240112523 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 316.prim_prince_test.240112523
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/316.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/317.prim_prince_test.1100168004
Short name T304
Test name
Test status
Simulation time 1668243073 ps
CPU time 34.06 seconds
Started Aug 25 12:19:44 AM UTC 24
Finished Aug 25 12:20:27 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1100168004 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 317.prim_prince_test.1100168004
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/317.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/318.prim_prince_test.1950678850
Short name T361
Test name
Test status
Simulation time 3465081341 ps
CPU time 69.86 seconds
Started Aug 25 12:19:45 AM UTC 24
Finished Aug 25 12:21:14 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1950678850 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 318.prim_prince_test.1950678850
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/318.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/319.prim_prince_test.3904662075
Short name T298
Test name
Test status
Simulation time 1325337592 ps
CPU time 27.32 seconds
Started Aug 25 12:19:45 AM UTC 24
Finished Aug 25 12:20:20 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3904662075 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 319.prim_prince_test.3904662075
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/319.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/32.prim_prince_test.4196901614
Short name T52
Test name
Test status
Simulation time 3343298894 ps
CPU time 69.56 seconds
Started Aug 25 12:14:37 AM UTC 24
Finished Aug 25 12:16:09 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4196901614 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 32.prim_prince_test.4196901614
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/32.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/320.prim_prince_test.1024525795
Short name T281
Test name
Test status
Simulation time 830287406 ps
CPU time 17.12 seconds
Started Aug 25 12:19:45 AM UTC 24
Finished Aug 25 12:20:08 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1024525795 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 320.prim_prince_test.1024525795
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/320.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/321.prim_prince_test.780397842
Short name T282
Test name
Test status
Simulation time 772875920 ps
CPU time 16.07 seconds
Started Aug 25 12:19:47 AM UTC 24
Finished Aug 25 12:20:08 AM UTC 24
Peak memory 154156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=780397842 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 321.prim_prince_test.780397842
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/321.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/322.prim_prince_test.3587678175
Short name T334
Test name
Test status
Simulation time 2423947934 ps
CPU time 49.03 seconds
Started Aug 25 12:19:47 AM UTC 24
Finished Aug 25 12:20:50 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3587678175 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 322.prim_prince_test.3587678175
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/322.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/323.prim_prince_test.2629007023
Short name T322
Test name
Test status
Simulation time 2079146281 ps
CPU time 41.84 seconds
Started Aug 25 12:19:47 AM UTC 24
Finished Aug 25 12:20:40 AM UTC 24
Peak memory 154248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2629007023 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 323.prim_prince_test.2629007023
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/323.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/324.prim_prince_test.3713235079
Short name T352
Test name
Test status
Simulation time 3139608802 ps
CPU time 63.01 seconds
Started Aug 25 12:19:48 AM UTC 24
Finished Aug 25 12:21:09 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3713235079 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 324.prim_prince_test.3713235079
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/324.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/325.prim_prince_test.2577837720
Short name T289
Test name
Test status
Simulation time 917632560 ps
CPU time 18.9 seconds
Started Aug 25 12:19:50 AM UTC 24
Finished Aug 25 12:20:15 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2577837720 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 325.prim_prince_test.2577837720
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/325.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/326.prim_prince_test.1676393920
Short name T324
Test name
Test status
Simulation time 1997853984 ps
CPU time 40.71 seconds
Started Aug 25 12:19:51 AM UTC 24
Finished Aug 25 12:20:43 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1676393920 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 326.prim_prince_test.1676393920
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/326.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/327.prim_prince_test.937310079
Short name T378
Test name
Test status
Simulation time 3614844557 ps
CPU time 72.8 seconds
Started Aug 25 12:19:52 AM UTC 24
Finished Aug 25 12:21:26 AM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=937310079 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 327.prim_prince_test.937310079
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/327.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/328.prim_prince_test.1572199084
Short name T314
Test name
Test status
Simulation time 1608351677 ps
CPU time 32.74 seconds
Started Aug 25 12:19:52 AM UTC 24
Finished Aug 25 12:20:35 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1572199084 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 328.prim_prince_test.1572199084
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/328.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/329.prim_prince_test.1132845050
Short name T295
Test name
Test status
Simulation time 927224672 ps
CPU time 19.1 seconds
Started Aug 25 12:19:54 AM UTC 24
Finished Aug 25 12:20:19 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1132845050 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 329.prim_prince_test.1132845050
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/329.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/33.prim_prince_test.2759845345
Short name T60
Test name
Test status
Simulation time 3561737003 ps
CPU time 74.06 seconds
Started Aug 25 12:14:38 AM UTC 24
Finished Aug 25 12:16:17 AM UTC 24
Peak memory 154588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2759845345 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 33.prim_prince_test.2759845345
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/33.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/330.prim_prince_test.299477757
Short name T320
Test name
Test status
Simulation time 1680376983 ps
CPU time 34.15 seconds
Started Aug 25 12:19:54 AM UTC 24
Finished Aug 25 12:20:38 AM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=299477757 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 330.prim_prince_test.299477757
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/330.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/331.prim_prince_test.3067419568
Short name T358
Test name
Test status
Simulation time 3104705149 ps
CPU time 62.39 seconds
Started Aug 25 12:19:54 AM UTC 24
Finished Aug 25 12:21:14 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3067419568 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 331.prim_prince_test.3067419568
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/331.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/332.prim_prince_test.3459305241
Short name T302
Test name
Test status
Simulation time 1245920758 ps
CPU time 25.38 seconds
Started Aug 25 12:19:54 AM UTC 24
Finished Aug 25 12:20:27 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3459305241 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 332.prim_prince_test.3459305241
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/332.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/333.prim_prince_test.1176616942
Short name T332
Test name
Test status
Simulation time 2068194530 ps
CPU time 41.77 seconds
Started Aug 25 12:19:55 AM UTC 24
Finished Aug 25 12:20:49 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1176616942 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 333.prim_prince_test.1176616942
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/333.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/334.prim_prince_test.2345662228
Short name T389
Test name
Test status
Simulation time 3690452489 ps
CPU time 73.95 seconds
Started Aug 25 12:19:55 AM UTC 24
Finished Aug 25 12:21:30 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2345662228 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 334.prim_prince_test.2345662228
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/334.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/335.prim_prince_test.353671787
Short name T326
Test name
Test status
Simulation time 1898482307 ps
CPU time 38.28 seconds
Started Aug 25 12:19:57 AM UTC 24
Finished Aug 25 12:20:46 AM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=353671787 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 335.prim_prince_test.353671787
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/335.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/336.prim_prince_test.538110813
Short name T333
Test name
Test status
Simulation time 2031142258 ps
CPU time 41.18 seconds
Started Aug 25 12:19:57 AM UTC 24
Finished Aug 25 12:20:50 AM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=538110813 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 336.prim_prince_test.538110813
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/336.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/337.prim_prince_test.3656149201
Short name T386
Test name
Test status
Simulation time 3613754032 ps
CPU time 72.55 seconds
Started Aug 25 12:19:57 AM UTC 24
Finished Aug 25 12:21:29 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3656149201 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 337.prim_prince_test.3656149201
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/337.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/338.prim_prince_test.4079995684
Short name T348
Test name
Test status
Simulation time 2595003932 ps
CPU time 52.66 seconds
Started Aug 25 12:19:57 AM UTC 24
Finished Aug 25 12:21:05 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4079995684 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 338.prim_prince_test.4079995684
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/338.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/339.prim_prince_test.1277716556
Short name T336
Test name
Test status
Simulation time 2099294574 ps
CPU time 42.8 seconds
Started Aug 25 12:19:58 AM UTC 24
Finished Aug 25 12:20:53 AM UTC 24
Peak memory 154376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1277716556 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 339.prim_prince_test.1277716556
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/339.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/34.prim_prince_test.1811961427
Short name T45
Test name
Test status
Simulation time 2979406824 ps
CPU time 62.04 seconds
Started Aug 25 12:14:38 AM UTC 24
Finished Aug 25 12:16:01 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1811961427 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 34.prim_prince_test.1811961427
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/34.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/340.prim_prince_test.3994053725
Short name T347
Test name
Test status
Simulation time 2482772021 ps
CPU time 50.44 seconds
Started Aug 25 12:19:58 AM UTC 24
Finished Aug 25 12:21:03 AM UTC 24
Peak memory 154536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3994053725 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 340.prim_prince_test.3994053725
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/340.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/341.prim_prince_test.2441151895
Short name T318
Test name
Test status
Simulation time 1382955997 ps
CPU time 28.35 seconds
Started Aug 25 12:19:58 AM UTC 24
Finished Aug 25 12:20:35 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2441151895 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 341.prim_prince_test.2441151895
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/341.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/342.prim_prince_test.1050581479
Short name T331
Test name
Test status
Simulation time 1893186402 ps
CPU time 38.69 seconds
Started Aug 25 12:19:59 AM UTC 24
Finished Aug 25 12:20:49 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1050581479 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 342.prim_prince_test.1050581479
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/342.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/343.prim_prince_test.3303778674
Short name T346
Test name
Test status
Simulation time 2407910344 ps
CPU time 48.76 seconds
Started Aug 25 12:20:00 AM UTC 24
Finished Aug 25 12:21:03 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3303778674 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 343.prim_prince_test.3303778674
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/343.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/344.prim_prince_test.2934906944
Short name T388
Test name
Test status
Simulation time 3420959626 ps
CPU time 68.52 seconds
Started Aug 25 12:20:02 AM UTC 24
Finished Aug 25 12:21:29 AM UTC 24
Peak memory 154440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2934906944 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 344.prim_prince_test.2934906944
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/344.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/345.prim_prince_test.2824583969
Short name T375
Test name
Test status
Simulation time 3186323056 ps
CPU time 64.34 seconds
Started Aug 25 12:20:02 AM UTC 24
Finished Aug 25 12:21:24 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2824583969 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 345.prim_prince_test.2824583969
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/345.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/346.prim_prince_test.528832698
Short name T319
Test name
Test status
Simulation time 1251279515 ps
CPU time 25.75 seconds
Started Aug 25 12:20:02 AM UTC 24
Finished Aug 25 12:20:36 AM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=528832698 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 346.prim_prince_test.528832698
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/346.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/347.prim_prince_test.3969659012
Short name T363
Test name
Test status
Simulation time 2799352011 ps
CPU time 56.61 seconds
Started Aug 25 12:20:04 AM UTC 24
Finished Aug 25 12:21:16 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3969659012 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 347.prim_prince_test.3969659012
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/347.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/348.prim_prince_test.1032933388
Short name T335
Test name
Test status
Simulation time 1726303964 ps
CPU time 35.05 seconds
Started Aug 25 12:20:05 AM UTC 24
Finished Aug 25 12:20:50 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1032933388 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 348.prim_prince_test.1032933388
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/348.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/349.prim_prince_test.2569594791
Short name T308
Test name
Test status
Simulation time 912469533 ps
CPU time 18.77 seconds
Started Aug 25 12:20:05 AM UTC 24
Finished Aug 25 12:20:30 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2569594791 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 349.prim_prince_test.2569594791
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/349.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/35.prim_prince_test.3825911027
Short name T24
Test name
Test status
Simulation time 2045804298 ps
CPU time 42.94 seconds
Started Aug 25 12:14:38 AM UTC 24
Finished Aug 25 12:15:37 AM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3825911027 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 35.prim_prince_test.3825911027
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/35.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/350.prim_prince_test.4012187497
Short name T345
Test name
Test status
Simulation time 2143058531 ps
CPU time 43.39 seconds
Started Aug 25 12:20:06 AM UTC 24
Finished Aug 25 12:21:02 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4012187497 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 350.prim_prince_test.4012187497
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/350.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/351.prim_prince_test.3633362049
Short name T340
Test name
Test status
Simulation time 1773593725 ps
CPU time 35.88 seconds
Started Aug 25 12:20:08 AM UTC 24
Finished Aug 25 12:20:54 AM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3633362049 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 351.prim_prince_test.3633362049
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/351.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/352.prim_prince_test.2336359032
Short name T343
Test name
Test status
Simulation time 1934109974 ps
CPU time 39.16 seconds
Started Aug 25 12:20:08 AM UTC 24
Finished Aug 25 12:20:58 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2336359032 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 352.prim_prince_test.2336359032
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/352.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/353.prim_prince_test.3065379190
Short name T328
Test name
Test status
Simulation time 1438718527 ps
CPU time 29.36 seconds
Started Aug 25 12:20:09 AM UTC 24
Finished Aug 25 12:20:47 AM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3065379190 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 353.prim_prince_test.3065379190
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/353.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/354.prim_prince_test.2151922170
Short name T315
Test name
Test status
Simulation time 965848093 ps
CPU time 19.79 seconds
Started Aug 25 12:20:09 AM UTC 24
Finished Aug 25 12:20:35 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2151922170 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 354.prim_prince_test.2151922170
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/354.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/355.prim_prince_test.4143097597
Short name T374
Test name
Test status
Simulation time 2862045662 ps
CPU time 57.65 seconds
Started Aug 25 12:20:10 AM UTC 24
Finished Aug 25 12:21:24 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4143097597 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 355.prim_prince_test.4143097597
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/355.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/356.prim_prince_test.3323738810
Short name T311
Test name
Test status
Simulation time 758672102 ps
CPU time 15.96 seconds
Started Aug 25 12:20:12 AM UTC 24
Finished Aug 25 12:20:34 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3323738810 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 356.prim_prince_test.3323738810
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/356.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/357.prim_prince_test.2216956261
Short name T369
Test name
Test status
Simulation time 2679621032 ps
CPU time 54.11 seconds
Started Aug 25 12:20:12 AM UTC 24
Finished Aug 25 12:21:22 AM UTC 24
Peak memory 156120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2216956261 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 357.prim_prince_test.2216956261
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/357.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/358.prim_prince_test.2690777052
Short name T397
Test name
Test status
Simulation time 3284409225 ps
CPU time 65.67 seconds
Started Aug 25 12:20:14 AM UTC 24
Finished Aug 25 12:21:37 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2690777052 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 358.prim_prince_test.2690777052
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/358.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/359.prim_prince_test.3154045088
Short name T373
Test name
Test status
Simulation time 2713445410 ps
CPU time 54.45 seconds
Started Aug 25 12:20:14 AM UTC 24
Finished Aug 25 12:21:23 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3154045088 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 359.prim_prince_test.3154045088
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/359.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/36.prim_prince_test.3419330593
Short name T34
Test name
Test status
Simulation time 2509362270 ps
CPU time 52.89 seconds
Started Aug 25 12:14:38 AM UTC 24
Finished Aug 25 12:15:50 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3419330593 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 36.prim_prince_test.3419330593
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/36.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/360.prim_prince_test.2650518494
Short name T393
Test name
Test status
Simulation time 3064166173 ps
CPU time 61.64 seconds
Started Aug 25 12:20:14 AM UTC 24
Finished Aug 25 12:21:32 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2650518494 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 360.prim_prince_test.2650518494
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/360.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/361.prim_prince_test.385335974
Short name T367
Test name
Test status
Simulation time 2427140979 ps
CPU time 48.72 seconds
Started Aug 25 12:20:16 AM UTC 24
Finished Aug 25 12:21:19 AM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=385335974 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 361.prim_prince_test.385335974
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/361.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/362.prim_prince_test.1779771554
Short name T418
Test name
Test status
Simulation time 3755770851 ps
CPU time 75.15 seconds
Started Aug 25 12:20:16 AM UTC 24
Finished Aug 25 12:21:51 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1779771554 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 362.prim_prince_test.1779771554
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/362.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/363.prim_prince_test.76954287
Short name T327
Test name
Test status
Simulation time 1074206007 ps
CPU time 22.05 seconds
Started Aug 25 12:20:18 AM UTC 24
Finished Aug 25 12:20:47 AM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=76954287 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 363.prim_prince_test.76954287
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/363.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/364.prim_prince_test.533782205
Short name T354
Test name
Test status
Simulation time 2050049032 ps
CPU time 41.45 seconds
Started Aug 25 12:20:18 AM UTC 24
Finished Aug 25 12:21:12 AM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=533782205 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 364.prim_prince_test.533782205
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/364.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/365.prim_prince_test.1624004077
Short name T350
Test name
Test status
Simulation time 1834212633 ps
CPU time 37.09 seconds
Started Aug 25 12:20:20 AM UTC 24
Finished Aug 25 12:21:08 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1624004077 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 365.prim_prince_test.1624004077
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/365.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/366.prim_prince_test.2712087069
Short name T339
Test name
Test status
Simulation time 1262448217 ps
CPU time 25.93 seconds
Started Aug 25 12:20:20 AM UTC 24
Finished Aug 25 12:20:54 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2712087069 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 366.prim_prince_test.2712087069
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/366.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/367.prim_prince_test.2736554498
Short name T407
Test name
Test status
Simulation time 3379188676 ps
CPU time 67.87 seconds
Started Aug 25 12:20:20 AM UTC 24
Finished Aug 25 12:21:46 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2736554498 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 367.prim_prince_test.2736554498
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/367.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/368.prim_prince_test.3066915839
Short name T338
Test name
Test status
Simulation time 1249703296 ps
CPU time 25.43 seconds
Started Aug 25 12:20:20 AM UTC 24
Finished Aug 25 12:20:53 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3066915839 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 368.prim_prince_test.3066915839
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/368.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/369.prim_prince_test.924065632
Short name T394
Test name
Test status
Simulation time 2815904894 ps
CPU time 56.29 seconds
Started Aug 25 12:20:20 AM UTC 24
Finished Aug 25 12:21:32 AM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=924065632 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 369.prim_prince_test.924065632
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/369.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/37.prim_prince_test.1956882322
Short name T28
Test name
Test status
Simulation time 2271607070 ps
CPU time 47.76 seconds
Started Aug 25 12:14:39 AM UTC 24
Finished Aug 25 12:15:43 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1956882322 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 37.prim_prince_test.1956882322
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/37.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/370.prim_prince_test.2938205429
Short name T276
Test name
Test status
Simulation time 1180485768 ps
CPU time 24.14 seconds
Started Aug 25 12:20:21 AM UTC 24
Finished Aug 25 12:20:52 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2938205429 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 370.prim_prince_test.2938205429
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/370.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/371.prim_prince_test.1147586613
Short name T420
Test name
Test status
Simulation time 3706824567 ps
CPU time 74 seconds
Started Aug 25 12:20:22 AM UTC 24
Finished Aug 25 12:21:56 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1147586613 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 371.prim_prince_test.1147586613
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/371.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/372.prim_prince_test.3996746716
Short name T398
Test name
Test status
Simulation time 3077292096 ps
CPU time 61.91 seconds
Started Aug 25 12:20:22 AM UTC 24
Finished Aug 25 12:21:41 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3996746716 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 372.prim_prince_test.3996746716
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/372.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/373.prim_prince_test.1868685388
Short name T416
Test name
Test status
Simulation time 3497697032 ps
CPU time 69.89 seconds
Started Aug 25 12:20:22 AM UTC 24
Finished Aug 25 12:21:51 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1868685388 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 373.prim_prince_test.1868685388
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/373.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/374.prim_prince_test.1157320061
Short name T356
Test name
Test status
Simulation time 1901343638 ps
CPU time 38.77 seconds
Started Aug 25 12:20:22 AM UTC 24
Finished Aug 25 12:21:12 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1157320061 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 374.prim_prince_test.1157320061
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/374.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/375.prim_prince_test.3434335976
Short name T376
Test name
Test status
Simulation time 2265385171 ps
CPU time 45.84 seconds
Started Aug 25 12:20:26 AM UTC 24
Finished Aug 25 12:21:25 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3434335976 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 375.prim_prince_test.3434335976
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/375.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/376.prim_prince_test.3041089960
Short name T370
Test name
Test status
Simulation time 2052569519 ps
CPU time 41.4 seconds
Started Aug 25 12:20:29 AM UTC 24
Finished Aug 25 12:21:22 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3041089960 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 376.prim_prince_test.3041089960
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/376.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/377.prim_prince_test.2113775584
Short name T409
Test name
Test status
Simulation time 3117822525 ps
CPU time 62.63 seconds
Started Aug 25 12:20:29 AM UTC 24
Finished Aug 25 12:21:48 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2113775584 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 377.prim_prince_test.2113775584
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/377.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/378.prim_prince_test.557594085
Short name T404
Test name
Test status
Simulation time 2930321639 ps
CPU time 58.69 seconds
Started Aug 25 12:20:29 AM UTC 24
Finished Aug 25 12:21:44 AM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=557594085 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 378.prim_prince_test.557594085
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/378.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/379.prim_prince_test.2935801545
Short name T385
Test name
Test status
Simulation time 2330855151 ps
CPU time 46.5 seconds
Started Aug 25 12:20:29 AM UTC 24
Finished Aug 25 12:21:28 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2935801545 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 379.prim_prince_test.2935801545
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/379.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/38.prim_prince_test.1015890637
Short name T6
Test name
Test status
Simulation time 839409944 ps
CPU time 17.99 seconds
Started Aug 25 12:14:40 AM UTC 24
Finished Aug 25 12:15:05 AM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1015890637 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 38.prim_prince_test.1015890637
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/38.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/380.prim_prince_test.3310150447
Short name T399
Test name
Test status
Simulation time 2834112725 ps
CPU time 56.74 seconds
Started Aug 25 12:20:30 AM UTC 24
Finished Aug 25 12:21:42 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3310150447 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 380.prim_prince_test.3310150447
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/380.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/381.prim_prince_test.2651506888
Short name T349
Test name
Test status
Simulation time 1378229198 ps
CPU time 28.16 seconds
Started Aug 25 12:20:30 AM UTC 24
Finished Aug 25 12:21:06 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2651506888 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 381.prim_prince_test.2651506888
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/381.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/382.prim_prince_test.833376508
Short name T351
Test name
Test status
Simulation time 1457674030 ps
CPU time 29.45 seconds
Started Aug 25 12:20:30 AM UTC 24
Finished Aug 25 12:21:08 AM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=833376508 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 382.prim_prince_test.833376508
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/382.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/383.prim_prince_test.2833320521
Short name T381
Test name
Test status
Simulation time 2130973263 ps
CPU time 43.2 seconds
Started Aug 25 12:20:31 AM UTC 24
Finished Aug 25 12:21:26 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2833320521 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 383.prim_prince_test.2833320521
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/383.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/384.prim_prince_test.669674540
Short name T380
Test name
Test status
Simulation time 3212415035 ps
CPU time 63.88 seconds
Started Aug 25 12:20:33 AM UTC 24
Finished Aug 25 12:21:55 AM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=669674540 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 384.prim_prince_test.669674540
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/384.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/385.prim_prince_test.372394120
Short name T426
Test name
Test status
Simulation time 3418551161 ps
CPU time 68.38 seconds
Started Aug 25 12:20:35 AM UTC 24
Finished Aug 25 12:22:02 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=372394120 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 385.prim_prince_test.372394120
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/385.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/386.prim_prince_test.365599627
Short name T382
Test name
Test status
Simulation time 2000682066 ps
CPU time 40.26 seconds
Started Aug 25 12:20:35 AM UTC 24
Finished Aug 25 12:21:26 AM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=365599627 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 386.prim_prince_test.365599627
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/386.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/387.prim_prince_test.1586661206
Short name T417
Test name
Test status
Simulation time 2982813629 ps
CPU time 60.03 seconds
Started Aug 25 12:20:35 AM UTC 24
Finished Aug 25 12:21:51 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1586661206 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 387.prim_prince_test.1586661206
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/387.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/388.prim_prince_test.3767592927
Short name T360
Test name
Test status
Simulation time 1436239474 ps
CPU time 29.03 seconds
Started Aug 25 12:20:37 AM UTC 24
Finished Aug 25 12:21:14 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3767592927 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 388.prim_prince_test.3767592927
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/388.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/389.prim_prince_test.2455192416
Short name T366
Test name
Test status
Simulation time 1599213144 ps
CPU time 32.45 seconds
Started Aug 25 12:20:37 AM UTC 24
Finished Aug 25 12:21:18 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2455192416 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 389.prim_prince_test.2455192416
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/389.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/39.prim_prince_test.3397161801
Short name T17
Test name
Test status
Simulation time 1510532577 ps
CPU time 31.75 seconds
Started Aug 25 12:14:41 AM UTC 24
Finished Aug 25 12:15:24 AM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3397161801 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 39.prim_prince_test.3397161801
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/39.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/390.prim_prince_test.702866566
Short name T371
Test name
Test status
Simulation time 1751649694 ps
CPU time 35.52 seconds
Started Aug 25 12:20:37 AM UTC 24
Finished Aug 25 12:21:22 AM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=702866566 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 390.prim_prince_test.702866566
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/390.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/391.prim_prince_test.494889535
Short name T342
Test name
Test status
Simulation time 784122302 ps
CPU time 16.35 seconds
Started Aug 25 12:20:37 AM UTC 24
Finished Aug 25 12:20:58 AM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=494889535 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 391.prim_prince_test.494889535
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/391.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/392.prim_prince_test.3289684193
Short name T437
Test name
Test status
Simulation time 3696803930 ps
CPU time 73.79 seconds
Started Aug 25 12:20:37 AM UTC 24
Finished Aug 25 12:22:10 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3289684193 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 392.prim_prince_test.3289684193
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/392.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/393.prim_prince_test.139631997
Short name T362
Test name
Test status
Simulation time 1434981104 ps
CPU time 29.12 seconds
Started Aug 25 12:20:37 AM UTC 24
Finished Aug 25 12:21:14 AM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=139631997 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 393.prim_prince_test.139631997
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/393.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/394.prim_prince_test.4233309494
Short name T355
Test name
Test status
Simulation time 1235518011 ps
CPU time 25.36 seconds
Started Aug 25 12:20:39 AM UTC 24
Finished Aug 25 12:21:12 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4233309494 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 394.prim_prince_test.4233309494
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/394.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/395.prim_prince_test.4257966271
Short name T390
Test name
Test status
Simulation time 2028884878 ps
CPU time 40.68 seconds
Started Aug 25 12:20:39 AM UTC 24
Finished Aug 25 12:21:31 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4257966271 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 395.prim_prince_test.4257966271
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/395.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/396.prim_prince_test.250963356
Short name T365
Test name
Test status
Simulation time 1399201428 ps
CPU time 28.04 seconds
Started Aug 25 12:20:41 AM UTC 24
Finished Aug 25 12:21:17 AM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=250963356 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 396.prim_prince_test.250963356
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/396.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/397.prim_prince_test.4246353419
Short name T443
Test name
Test status
Simulation time 3652098666 ps
CPU time 72.07 seconds
Started Aug 25 12:20:43 AM UTC 24
Finished Aug 25 12:22:15 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4246353419 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 397.prim_prince_test.4246353419
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/397.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/398.prim_prince_test.3740711005
Short name T383
Test name
Test status
Simulation time 1675121937 ps
CPU time 33.59 seconds
Started Aug 25 12:20:45 AM UTC 24
Finished Aug 25 12:21:28 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3740711005 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 398.prim_prince_test.3740711005
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/398.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/399.prim_prince_test.4089467524
Short name T423
Test name
Test status
Simulation time 2895833142 ps
CPU time 57.89 seconds
Started Aug 25 12:20:45 AM UTC 24
Finished Aug 25 12:21:58 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4089467524 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 399.prim_prince_test.4089467524
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/399.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/4.prim_prince_test.106088973
Short name T7
Test name
Test status
Simulation time 1259327946 ps
CPU time 26.84 seconds
Started Aug 25 12:14:28 AM UTC 24
Finished Aug 25 12:15:05 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=106088973 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 4.prim_prince_test.106088973
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/4.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/40.prim_prince_test.1471176016
Short name T43
Test name
Test status
Simulation time 2887422088 ps
CPU time 59.82 seconds
Started Aug 25 12:14:41 AM UTC 24
Finished Aug 25 12:16:01 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1471176016 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 40.prim_prince_test.1471176016
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/40.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/400.prim_prince_test.72695149
Short name T368
Test name
Test status
Simulation time 1311817141 ps
CPU time 26.44 seconds
Started Aug 25 12:20:47 AM UTC 24
Finished Aug 25 12:21:21 AM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=72695149 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 400.prim_prince_test.72695149
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/400.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/401.prim_prince_test.3010065639
Short name T408
Test name
Test status
Simulation time 2299268598 ps
CPU time 46.27 seconds
Started Aug 25 12:20:48 AM UTC 24
Finished Aug 25 12:21:47 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3010065639 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 401.prim_prince_test.3010065639
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/401.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/402.prim_prince_test.10951330
Short name T372
Test name
Test status
Simulation time 1339930869 ps
CPU time 27.21 seconds
Started Aug 25 12:20:48 AM UTC 24
Finished Aug 25 12:21:23 AM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10951330 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 402.prim_prince_test.10951330
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/402.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/403.prim_prince_test.421670986
Short name T446
Test name
Test status
Simulation time 3399211158 ps
CPU time 68.1 seconds
Started Aug 25 12:20:50 AM UTC 24
Finished Aug 25 12:22:16 AM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=421670986 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 403.prim_prince_test.421670986
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/403.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/404.prim_prince_test.936947674
Short name T384
Test name
Test status
Simulation time 1457793371 ps
CPU time 29.53 seconds
Started Aug 25 12:20:50 AM UTC 24
Finished Aug 25 12:21:28 AM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=936947674 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 404.prim_prince_test.936947674
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/404.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/405.prim_prince_test.4242013341
Short name T452
Test name
Test status
Simulation time 3705368771 ps
CPU time 73.39 seconds
Started Aug 25 12:20:50 AM UTC 24
Finished Aug 25 12:22:23 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4242013341 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 405.prim_prince_test.4242013341
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/405.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/406.prim_prince_test.1454668199
Short name T395
Test name
Test status
Simulation time 1679371334 ps
CPU time 33.7 seconds
Started Aug 25 12:20:50 AM UTC 24
Finished Aug 25 12:21:33 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1454668199 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 406.prim_prince_test.1454668199
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/406.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/407.prim_prince_test.478472225
Short name T454
Test name
Test status
Simulation time 3654266327 ps
CPU time 72.4 seconds
Started Aug 25 12:20:51 AM UTC 24
Finished Aug 25 12:22:23 AM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=478472225 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 407.prim_prince_test.478472225
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/407.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/408.prim_prince_test.1019741577
Short name T444
Test name
Test status
Simulation time 3356588913 ps
CPU time 66.74 seconds
Started Aug 25 12:20:51 AM UTC 24
Finished Aug 25 12:22:16 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1019741577 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 408.prim_prince_test.1019741577
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/408.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/409.prim_prince_test.3832462836
Short name T413
Test name
Test status
Simulation time 2294197415 ps
CPU time 46.1 seconds
Started Aug 25 12:20:51 AM UTC 24
Finished Aug 25 12:21:50 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3832462836 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 409.prim_prince_test.3832462836
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/409.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/41.prim_prince_test.1920277484
Short name T47
Test name
Test status
Simulation time 2845811780 ps
CPU time 59.2 seconds
Started Aug 25 12:14:44 AM UTC 24
Finished Aug 25 12:16:03 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1920277484 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 41.prim_prince_test.1920277484
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/41.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/410.prim_prince_test.885999599
Short name T391
Test name
Test status
Simulation time 1531210551 ps
CPU time 30.96 seconds
Started Aug 25 12:20:51 AM UTC 24
Finished Aug 25 12:21:31 AM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=885999599 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 410.prim_prince_test.885999599
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/410.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/411.prim_prince_test.3231203799
Short name T460
Test name
Test status
Simulation time 3687543022 ps
CPU time 73.11 seconds
Started Aug 25 12:20:53 AM UTC 24
Finished Aug 25 12:22:25 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3231203799 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 411.prim_prince_test.3231203799
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/411.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/412.prim_prince_test.2127284245
Short name T425
Test name
Test status
Simulation time 2592205130 ps
CPU time 52.04 seconds
Started Aug 25 12:20:54 AM UTC 24
Finished Aug 25 12:22:00 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2127284245 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 412.prim_prince_test.2127284245
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/412.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/413.prim_prince_test.3492999839
Short name T401
Test name
Test status
Simulation time 1902173804 ps
CPU time 38.08 seconds
Started Aug 25 12:20:54 AM UTC 24
Finished Aug 25 12:21:43 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3492999839 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 413.prim_prince_test.3492999839
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/413.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/414.prim_prince_test.2846261027
Short name T400
Test name
Test status
Simulation time 1894649006 ps
CPU time 37.92 seconds
Started Aug 25 12:20:54 AM UTC 24
Finished Aug 25 12:21:43 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2846261027 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 414.prim_prince_test.2846261027
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/414.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/415.prim_prince_test.3935280524
Short name T414
Test name
Test status
Simulation time 2178105048 ps
CPU time 43.6 seconds
Started Aug 25 12:20:54 AM UTC 24
Finished Aug 25 12:21:50 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3935280524 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 415.prim_prince_test.3935280524
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/415.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/416.prim_prince_test.4138177522
Short name T435
Test name
Test status
Simulation time 2900446188 ps
CPU time 57.71 seconds
Started Aug 25 12:20:56 AM UTC 24
Finished Aug 25 12:22:09 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4138177522 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 416.prim_prince_test.4138177522
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/416.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/417.prim_prince_test.2349771808
Short name T377
Test name
Test status
Simulation time 1128061451 ps
CPU time 22.91 seconds
Started Aug 25 12:20:56 AM UTC 24
Finished Aug 25 12:21:25 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2349771808 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 417.prim_prince_test.2349771808
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/417.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/418.prim_prince_test.1216398366
Short name T396
Test name
Test status
Simulation time 1488411805 ps
CPU time 29.86 seconds
Started Aug 25 12:20:57 AM UTC 24
Finished Aug 25 12:21:35 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1216398366 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 418.prim_prince_test.1216398366
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/418.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/419.prim_prince_test.2975420246
Short name T465
Test name
Test status
Simulation time 3610382478 ps
CPU time 71.14 seconds
Started Aug 25 12:20:59 AM UTC 24
Finished Aug 25 12:22:29 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2975420246 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 419.prim_prince_test.2975420246
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/419.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/42.prim_prince_test.1576327061
Short name T16
Test name
Test status
Simulation time 1212805489 ps
CPU time 25.53 seconds
Started Aug 25 12:14:48 AM UTC 24
Finished Aug 25 12:15:23 AM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1576327061 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 42.prim_prince_test.1576327061
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/42.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/420.prim_prince_test.3455473117
Short name T405
Test name
Test status
Simulation time 1777095008 ps
CPU time 35.83 seconds
Started Aug 25 12:20:59 AM UTC 24
Finished Aug 25 12:21:45 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3455473117 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 420.prim_prince_test.3455473117
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/420.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/421.prim_prince_test.3371506501
Short name T387
Test name
Test status
Simulation time 2082829586 ps
CPU time 42 seconds
Started Aug 25 12:21:01 AM UTC 24
Finished Aug 25 12:21:55 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3371506501 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 421.prim_prince_test.3371506501
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/421.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/422.prim_prince_test.1539379316
Short name T412
Test name
Test status
Simulation time 1820673946 ps
CPU time 36.7 seconds
Started Aug 25 12:21:02 AM UTC 24
Finished Aug 25 12:21:49 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1539379316 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 422.prim_prince_test.1539379316
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/422.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/423.prim_prince_test.1133070348
Short name T424
Test name
Test status
Simulation time 2167805306 ps
CPU time 43.17 seconds
Started Aug 25 12:21:04 AM UTC 24
Finished Aug 25 12:21:59 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1133070348 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 423.prim_prince_test.1133070348
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/423.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/424.prim_prince_test.2223026909
Short name T402
Test name
Test status
Simulation time 1515153415 ps
CPU time 30.52 seconds
Started Aug 25 12:21:04 AM UTC 24
Finished Aug 25 12:21:43 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2223026909 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 424.prim_prince_test.2223026909
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/424.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/425.prim_prince_test.4273565541
Short name T462
Test name
Test status
Simulation time 3251375544 ps
CPU time 64.09 seconds
Started Aug 25 12:21:05 AM UTC 24
Finished Aug 25 12:22:26 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4273565541 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 425.prim_prince_test.4273565541
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/425.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/426.prim_prince_test.624754413
Short name T471
Test name
Test status
Simulation time 3535706108 ps
CPU time 69.36 seconds
Started Aug 25 12:21:07 AM UTC 24
Finished Aug 25 12:22:35 AM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=624754413 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 426.prim_prince_test.624754413
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/426.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/427.prim_prince_test.814915414
Short name T467
Test name
Test status
Simulation time 3270050132 ps
CPU time 64.77 seconds
Started Aug 25 12:21:08 AM UTC 24
Finished Aug 25 12:22:30 AM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=814915414 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 427.prim_prince_test.814915414
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/427.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/428.prim_prince_test.4229269564
Short name T392
Test name
Test status
Simulation time 830668523 ps
CPU time 16.89 seconds
Started Aug 25 12:21:10 AM UTC 24
Finished Aug 25 12:21:32 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4229269564 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 428.prim_prince_test.4229269564
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/428.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/429.prim_prince_test.1219147954
Short name T411
Test name
Test status
Simulation time 1534182970 ps
CPU time 30.95 seconds
Started Aug 25 12:21:10 AM UTC 24
Finished Aug 25 12:21:49 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1219147954 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 429.prim_prince_test.1219147954
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/429.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/43.prim_prince_test.1692034649
Short name T12
Test name
Test status
Simulation time 843445227 ps
CPU time 18.09 seconds
Started Aug 25 12:14:52 AM UTC 24
Finished Aug 25 12:15:18 AM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1692034649 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 43.prim_prince_test.1692034649
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/43.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/430.prim_prince_test.627827797
Short name T440
Test name
Test status
Simulation time 2448410067 ps
CPU time 48.73 seconds
Started Aug 25 12:21:11 AM UTC 24
Finished Aug 25 12:22:13 AM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=627827797 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 430.prim_prince_test.627827797
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/430.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/431.prim_prince_test.2299963182
Short name T475
Test name
Test status
Simulation time 3361148071 ps
CPU time 65.9 seconds
Started Aug 25 12:21:13 AM UTC 24
Finished Aug 25 12:22:36 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2299963182 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 431.prim_prince_test.2299963182
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/431.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/432.prim_prince_test.1366712899
Short name T464
Test name
Test status
Simulation time 3023173687 ps
CPU time 59.44 seconds
Started Aug 25 12:21:13 AM UTC 24
Finished Aug 25 12:22:29 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1366712899 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 432.prim_prince_test.1366712899
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/432.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/433.prim_prince_test.1388760563
Short name T421
Test name
Test status
Simulation time 1696535909 ps
CPU time 33.86 seconds
Started Aug 25 12:21:13 AM UTC 24
Finished Aug 25 12:21:57 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1388760563 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 433.prim_prince_test.1388760563
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/433.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/434.prim_prince_test.4175887126
Short name T433
Test name
Test status
Simulation time 2084794660 ps
CPU time 41.56 seconds
Started Aug 25 12:21:13 AM UTC 24
Finished Aug 25 12:22:06 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4175887126 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 434.prim_prince_test.4175887126
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/434.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/435.prim_prince_test.1400759905
Short name T427
Test name
Test status
Simulation time 1873331567 ps
CPU time 37.51 seconds
Started Aug 25 12:21:15 AM UTC 24
Finished Aug 25 12:22:03 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1400759905 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 435.prim_prince_test.1400759905
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/435.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/436.prim_prince_test.2408771462
Short name T415
Test name
Test status
Simulation time 1379202077 ps
CPU time 27.63 seconds
Started Aug 25 12:21:15 AM UTC 24
Finished Aug 25 12:21:50 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2408771462 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 436.prim_prince_test.2408771462
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/436.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/437.prim_prince_test.842200455
Short name T438
Test name
Test status
Simulation time 2210255463 ps
CPU time 44.22 seconds
Started Aug 25 12:21:15 AM UTC 24
Finished Aug 25 12:22:11 AM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=842200455 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 437.prim_prince_test.842200455
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/437.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/438.prim_prince_test.3932350832
Short name T449
Test name
Test status
Simulation time 2524416925 ps
CPU time 50.17 seconds
Started Aug 25 12:21:15 AM UTC 24
Finished Aug 25 12:22:19 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3932350832 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 438.prim_prince_test.3932350832
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/438.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/439.prim_prince_test.305957244
Short name T403
Test name
Test status
Simulation time 1070224083 ps
CPU time 21.68 seconds
Started Aug 25 12:21:15 AM UTC 24
Finished Aug 25 12:21:43 AM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=305957244 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 439.prim_prince_test.305957244
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/439.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/44.prim_prince_test.1524743883
Short name T63
Test name
Test status
Simulation time 3121598162 ps
CPU time 64.37 seconds
Started Aug 25 12:14:57 AM UTC 24
Finished Aug 25 12:16:22 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1524743883 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 44.prim_prince_test.1524743883
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/44.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/440.prim_prince_test.1813585848
Short name T484
Test name
Test status
Simulation time 3400541707 ps
CPU time 66.14 seconds
Started Aug 25 12:21:18 AM UTC 24
Finished Aug 25 12:22:41 AM UTC 24
Peak memory 154252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1813585848 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 440.prim_prince_test.1813585848
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/440.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/441.prim_prince_test.1630752728
Short name T432
Test name
Test status
Simulation time 1848113981 ps
CPU time 37.05 seconds
Started Aug 25 12:21:18 AM UTC 24
Finished Aug 25 12:22:05 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1630752728 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 441.prim_prince_test.1630752728
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/441.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/442.prim_prince_test.3480143110
Short name T419
Test name
Test status
Simulation time 1382098079 ps
CPU time 27.66 seconds
Started Aug 25 12:21:18 AM UTC 24
Finished Aug 25 12:21:53 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3480143110 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 442.prim_prince_test.3480143110
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/442.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/443.prim_prince_test.1855030512
Short name T481
Test name
Test status
Simulation time 3185633291 ps
CPU time 62.48 seconds
Started Aug 25 12:21:19 AM UTC 24
Finished Aug 25 12:22:37 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1855030512 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 443.prim_prince_test.1855030512
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/443.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/444.prim_prince_test.1282662845
Short name T458
Test name
Test status
Simulation time 2608048410 ps
CPU time 51.62 seconds
Started Aug 25 12:21:19 AM UTC 24
Finished Aug 25 12:22:24 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1282662845 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 444.prim_prince_test.1282662845
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/444.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/445.prim_prince_test.2410945279
Short name T459
Test name
Test status
Simulation time 2601847317 ps
CPU time 51.25 seconds
Started Aug 25 12:21:20 AM UTC 24
Finished Aug 25 12:22:25 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2410945279 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 445.prim_prince_test.2410945279
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/445.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/446.prim_prince_test.2024845772
Short name T472
Test name
Test status
Simulation time 3015776824 ps
CPU time 58.92 seconds
Started Aug 25 12:21:20 AM UTC 24
Finished Aug 25 12:22:35 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2024845772 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 446.prim_prince_test.2024845772
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/446.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/447.prim_prince_test.1605998302
Short name T473
Test name
Test status
Simulation time 2929158747 ps
CPU time 57.76 seconds
Started Aug 25 12:21:22 AM UTC 24
Finished Aug 25 12:22:35 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1605998302 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 447.prim_prince_test.1605998302
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/447.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/448.prim_prince_test.2688866913
Short name T482
Test name
Test status
Simulation time 3112032321 ps
CPU time 60.61 seconds
Started Aug 25 12:21:23 AM UTC 24
Finished Aug 25 12:22:39 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2688866913 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 448.prim_prince_test.2688866913
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/448.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/449.prim_prince_test.2345168504
Short name T434
Test name
Test status
Simulation time 1725097731 ps
CPU time 34.44 seconds
Started Aug 25 12:21:23 AM UTC 24
Finished Aug 25 12:22:07 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2345168504 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 449.prim_prince_test.2345168504
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/449.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/45.prim_prince_test.4016955503
Short name T67
Test name
Test status
Simulation time 3303191498 ps
CPU time 68.77 seconds
Started Aug 25 12:14:57 AM UTC 24
Finished Aug 25 12:16:27 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4016955503 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 45.prim_prince_test.4016955503
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/45.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/450.prim_prince_test.1150924185
Short name T492
Test name
Test status
Simulation time 3530952226 ps
CPU time 68.77 seconds
Started Aug 25 12:21:23 AM UTC 24
Finished Aug 25 12:22:50 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1150924185 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 450.prim_prince_test.1150924185
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/450.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/451.prim_prince_test.3393483058
Short name T410
Test name
Test status
Simulation time 894083793 ps
CPU time 18.19 seconds
Started Aug 25 12:21:25 AM UTC 24
Finished Aug 25 12:21:48 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3393483058 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 451.prim_prince_test.3393483058
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/451.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/452.prim_prince_test.3938597120
Short name T468
Test name
Test status
Simulation time 2710041411 ps
CPU time 53.08 seconds
Started Aug 25 12:21:25 AM UTC 24
Finished Aug 25 12:22:32 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3938597120 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 452.prim_prince_test.3938597120
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/452.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/453.prim_prince_test.160272117
Short name T379
Test name
Test status
Simulation time 1014027525 ps
CPU time 20.56 seconds
Started Aug 25 12:21:25 AM UTC 24
Finished Aug 25 12:21:51 AM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=160272117 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 453.prim_prince_test.160272117
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/453.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/454.prim_prince_test.2839406640
Short name T406
Test name
Test status
Simulation time 755155429 ps
CPU time 15.55 seconds
Started Aug 25 12:21:25 AM UTC 24
Finished Aug 25 12:21:45 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2839406640 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 454.prim_prince_test.2839406640
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/454.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/455.prim_prince_test.4161116997
Short name T429
Test name
Test status
Simulation time 1450686164 ps
CPU time 29.13 seconds
Started Aug 25 12:21:26 AM UTC 24
Finished Aug 25 12:22:04 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4161116997 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 455.prim_prince_test.4161116997
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/455.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/456.prim_prince_test.457685585
Short name T474
Test name
Test status
Simulation time 2800224404 ps
CPU time 54.99 seconds
Started Aug 25 12:21:26 AM UTC 24
Finished Aug 25 12:22:36 AM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=457685585 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 456.prim_prince_test.457685585
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/456.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/457.prim_prince_test.2933459878
Short name T428
Test name
Test status
Simulation time 1424991962 ps
CPU time 28.65 seconds
Started Aug 25 12:21:26 AM UTC 24
Finished Aug 25 12:22:03 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2933459878 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 457.prim_prince_test.2933459878
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/457.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/458.prim_prince_test.3775991265
Short name T442
Test name
Test status
Simulation time 1889110756 ps
CPU time 37.56 seconds
Started Aug 25 12:21:27 AM UTC 24
Finished Aug 25 12:22:14 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3775991265 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 458.prim_prince_test.3775991265
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/458.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/459.prim_prince_test.3202842235
Short name T457
Test name
Test status
Simulation time 2234831302 ps
CPU time 44.35 seconds
Started Aug 25 12:21:28 AM UTC 24
Finished Aug 25 12:22:24 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3202842235 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 459.prim_prince_test.3202842235
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/459.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/46.prim_prince_test.1905822940
Short name T30
Test name
Test status
Simulation time 1477516153 ps
CPU time 30.71 seconds
Started Aug 25 12:15:03 AM UTC 24
Finished Aug 25 12:15:44 AM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1905822940 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 46.prim_prince_test.1905822940
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/46.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/460.prim_prince_test.855274555
Short name T430
Test name
Test status
Simulation time 1427016297 ps
CPU time 28.64 seconds
Started Aug 25 12:21:28 AM UTC 24
Finished Aug 25 12:22:05 AM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=855274555 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 460.prim_prince_test.855274555
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/460.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/461.prim_prince_test.3659380921
Short name T453
Test name
Test status
Simulation time 2198463531 ps
CPU time 43.2 seconds
Started Aug 25 12:21:28 AM UTC 24
Finished Aug 25 12:22:23 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3659380921 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 461.prim_prince_test.3659380921
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/461.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/462.prim_prince_test.1461753866
Short name T483
Test name
Test status
Simulation time 2879587923 ps
CPU time 56.13 seconds
Started Aug 25 12:21:29 AM UTC 24
Finished Aug 25 12:22:40 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1461753866 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 462.prim_prince_test.1461753866
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/462.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/463.prim_prince_test.4291118858
Short name T436
Test name
Test status
Simulation time 1597223554 ps
CPU time 31.83 seconds
Started Aug 25 12:21:29 AM UTC 24
Finished Aug 25 12:22:10 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4291118858 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 463.prim_prince_test.4291118858
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/463.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/464.prim_prince_test.3936661630
Short name T447
Test name
Test status
Simulation time 1872336952 ps
CPU time 37.56 seconds
Started Aug 25 12:21:29 AM UTC 24
Finished Aug 25 12:22:17 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3936661630 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 464.prim_prince_test.3936661630
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/464.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/465.prim_prince_test.1798920223
Short name T479
Test name
Test status
Simulation time 2709289717 ps
CPU time 52.51 seconds
Started Aug 25 12:21:31 AM UTC 24
Finished Aug 25 12:22:37 AM UTC 24
Peak memory 154280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1798920223 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 465.prim_prince_test.1798920223
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/465.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/466.prim_prince_test.4227147997
Short name T456
Test name
Test status
Simulation time 2078669219 ps
CPU time 41.42 seconds
Started Aug 25 12:21:31 AM UTC 24
Finished Aug 25 12:22:24 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4227147997 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 466.prim_prince_test.4227147997
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/466.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/467.prim_prince_test.473423895
Short name T495
Test name
Test status
Simulation time 3598408843 ps
CPU time 70.56 seconds
Started Aug 25 12:21:31 AM UTC 24
Finished Aug 25 12:23:00 AM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=473423895 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 467.prim_prince_test.473423895
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/467.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/468.prim_prince_test.4206193093
Short name T422
Test name
Test status
Simulation time 977288419 ps
CPU time 19.66 seconds
Started Aug 25 12:21:32 AM UTC 24
Finished Aug 25 12:21:58 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4206193093 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 468.prim_prince_test.4206193093
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/468.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/469.prim_prince_test.4193458920
Short name T439
Test name
Test status
Simulation time 1522683560 ps
CPU time 30.84 seconds
Started Aug 25 12:21:32 AM UTC 24
Finished Aug 25 12:22:12 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4193458920 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 469.prim_prince_test.4193458920
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/469.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/47.prim_prince_test.3328307134
Short name T59
Test name
Test status
Simulation time 2574702708 ps
CPU time 53.67 seconds
Started Aug 25 12:15:05 AM UTC 24
Finished Aug 25 12:16:16 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3328307134 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 47.prim_prince_test.3328307134
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/47.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/470.prim_prince_test.3782929223
Short name T463
Test name
Test status
Simulation time 2151855466 ps
CPU time 42.58 seconds
Started Aug 25 12:21:32 AM UTC 24
Finished Aug 25 12:22:26 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3782929223 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 470.prim_prince_test.3782929223
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/470.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/471.prim_prince_test.3190658680
Short name T431
Test name
Test status
Simulation time 1180133464 ps
CPU time 24.04 seconds
Started Aug 25 12:21:34 AM UTC 24
Finished Aug 25 12:22:05 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3190658680 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 471.prim_prince_test.3190658680
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/471.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/472.prim_prince_test.234030374
Short name T469
Test name
Test status
Simulation time 2411765962 ps
CPU time 47.36 seconds
Started Aug 25 12:21:34 AM UTC 24
Finished Aug 25 12:22:34 AM UTC 24
Peak memory 154276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=234030374 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 472.prim_prince_test.234030374
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/472.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/473.prim_prince_test.3315688812
Short name T441
Test name
Test status
Simulation time 1502320038 ps
CPU time 30.13 seconds
Started Aug 25 12:21:34 AM UTC 24
Finished Aug 25 12:22:13 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3315688812 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 473.prim_prince_test.3315688812
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/473.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/474.prim_prince_test.2855141452
Short name T494
Test name
Test status
Simulation time 3109714570 ps
CPU time 60.21 seconds
Started Aug 25 12:21:36 AM UTC 24
Finished Aug 25 12:22:53 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2855141452 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 474.prim_prince_test.2855141452
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/474.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/475.prim_prince_test.1383300307
Short name T461
Test name
Test status
Simulation time 1878958321 ps
CPU time 37.16 seconds
Started Aug 25 12:21:38 AM UTC 24
Finished Aug 25 12:22:25 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1383300307 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 475.prim_prince_test.1383300307
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/475.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/476.prim_prince_test.4290606457
Short name T485
Test name
Test status
Simulation time 2487777366 ps
CPU time 48.25 seconds
Started Aug 25 12:21:41 AM UTC 24
Finished Aug 25 12:22:43 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4290606457 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 476.prim_prince_test.4290606457
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/476.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/477.prim_prince_test.1213658125
Short name T476
Test name
Test status
Simulation time 2130156719 ps
CPU time 41.39 seconds
Started Aug 25 12:21:44 AM UTC 24
Finished Aug 25 12:22:37 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1213658125 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 477.prim_prince_test.1213658125
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/477.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/478.prim_prince_test.3780446258
Short name T497
Test name
Test status
Simulation time 3317595725 ps
CPU time 63.79 seconds
Started Aug 25 12:21:44 AM UTC 24
Finished Aug 25 12:23:06 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3780446258 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 478.prim_prince_test.3780446258
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/478.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/479.prim_prince_test.3245803219
Short name T451
Test name
Test status
Simulation time 1432140252 ps
CPU time 28.59 seconds
Started Aug 25 12:21:44 AM UTC 24
Finished Aug 25 12:22:21 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3245803219 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 479.prim_prince_test.3245803219
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/479.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/48.prim_prince_test.2255091417
Short name T50
Test name
Test status
Simulation time 2278882034 ps
CPU time 47.34 seconds
Started Aug 25 12:15:05 AM UTC 24
Finished Aug 25 12:16:08 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2255091417 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 48.prim_prince_test.2255091417
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/48.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/480.prim_prince_test.1299204238
Short name T491
Test name
Test status
Simulation time 2667741976 ps
CPU time 51.73 seconds
Started Aug 25 12:21:44 AM UTC 24
Finished Aug 25 12:22:50 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1299204238 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 480.prim_prince_test.1299204238
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/480.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/481.prim_prince_test.3478774278
Short name T470
Test name
Test status
Simulation time 2019075499 ps
CPU time 39.03 seconds
Started Aug 25 12:21:44 AM UTC 24
Finished Aug 25 12:22:34 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3478774278 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 481.prim_prince_test.3478774278
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/481.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/482.prim_prince_test.1173219125
Short name T486
Test name
Test status
Simulation time 2346865320 ps
CPU time 46.11 seconds
Started Aug 25 12:21:44 AM UTC 24
Finished Aug 25 12:22:43 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1173219125 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 482.prim_prince_test.1173219125
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/482.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/483.prim_prince_test.2829887662
Short name T489
Test name
Test status
Simulation time 2445754799 ps
CPU time 47.58 seconds
Started Aug 25 12:21:46 AM UTC 24
Finished Aug 25 12:22:47 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2829887662 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 483.prim_prince_test.2829887662
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/483.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/484.prim_prince_test.1399413892
Short name T493
Test name
Test status
Simulation time 2684273913 ps
CPU time 52.69 seconds
Started Aug 25 12:21:46 AM UTC 24
Finished Aug 25 12:22:52 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1399413892 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 484.prim_prince_test.1399413892
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/484.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/485.prim_prince_test.160137613
Short name T445
Test name
Test status
Simulation time 1144852263 ps
CPU time 23.09 seconds
Started Aug 25 12:21:46 AM UTC 24
Finished Aug 25 12:22:16 AM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=160137613 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 485.prim_prince_test.160137613
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/485.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/486.prim_prince_test.152916481
Short name T478
Test name
Test status
Simulation time 2052868169 ps
CPU time 39.55 seconds
Started Aug 25 12:21:47 AM UTC 24
Finished Aug 25 12:22:37 AM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=152916481 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 486.prim_prince_test.152916481
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/486.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/487.prim_prince_test.3746080465
Short name T496
Test name
Test status
Simulation time 2911924128 ps
CPU time 57.51 seconds
Started Aug 25 12:21:48 AM UTC 24
Finished Aug 25 12:23:01 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3746080465 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 487.prim_prince_test.3746080465
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/487.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/488.prim_prince_test.590433299
Short name T488
Test name
Test status
Simulation time 2231238038 ps
CPU time 43.47 seconds
Started Aug 25 12:21:49 AM UTC 24
Finished Aug 25 12:22:45 AM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=590433299 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 488.prim_prince_test.590433299
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/488.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/489.prim_prince_test.3077462827
Short name T498
Test name
Test status
Simulation time 3155878110 ps
CPU time 60.27 seconds
Started Aug 25 12:21:49 AM UTC 24
Finished Aug 25 12:23:06 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3077462827 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 489.prim_prince_test.3077462827
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/489.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/49.prim_prince_test.2590413144
Short name T81
Test name
Test status
Simulation time 3720346754 ps
CPU time 77.16 seconds
Started Aug 25 12:15:07 AM UTC 24
Finished Aug 25 12:16:49 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2590413144 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 49.prim_prince_test.2590413144
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/49.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/490.prim_prince_test.2659375343
Short name T499
Test name
Test status
Simulation time 3074828816 ps
CPU time 59.22 seconds
Started Aug 25 12:21:51 AM UTC 24
Finished Aug 25 12:23:07 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2659375343 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 490.prim_prince_test.2659375343
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/490.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/491.prim_prince_test.4072109633
Short name T500
Test name
Test status
Simulation time 3278087891 ps
CPU time 61.67 seconds
Started Aug 25 12:21:51 AM UTC 24
Finished Aug 25 12:23:10 AM UTC 24
Peak memory 154504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4072109633 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 491.prim_prince_test.4072109633
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/491.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/492.prim_prince_test.365256631
Short name T448
Test name
Test status
Simulation time 1033015200 ps
CPU time 20.84 seconds
Started Aug 25 12:21:51 AM UTC 24
Finished Aug 25 12:22:18 AM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=365256631 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 492.prim_prince_test.365256631
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/492.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/493.prim_prince_test.3124019090
Short name T477
Test name
Test status
Simulation time 1854177349 ps
CPU time 35.74 seconds
Started Aug 25 12:21:51 AM UTC 24
Finished Aug 25 12:22:37 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3124019090 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 493.prim_prince_test.3124019090
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/493.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/494.prim_prince_test.2139482277
Short name T490
Test name
Test status
Simulation time 2271527586 ps
CPU time 44.32 seconds
Started Aug 25 12:21:51 AM UTC 24
Finished Aug 25 12:22:48 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2139482277 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 494.prim_prince_test.2139482277
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/494.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/495.prim_prince_test.931727998
Short name T450
Test name
Test status
Simulation time 1045970911 ps
CPU time 20.94 seconds
Started Aug 25 12:21:53 AM UTC 24
Finished Aug 25 12:22:20 AM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=931727998 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 495.prim_prince_test.931727998
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/495.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/496.prim_prince_test.3898349105
Short name T466
Test name
Test status
Simulation time 1433196657 ps
CPU time 28.2 seconds
Started Aug 25 12:21:53 AM UTC 24
Finished Aug 25 12:22:29 AM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3898349105 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 496.prim_prince_test.3898349105
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/496.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/497.prim_prince_test.1066752447
Short name T455
Test name
Test status
Simulation time 1184658151 ps
CPU time 23.23 seconds
Started Aug 25 12:21:53 AM UTC 24
Finished Aug 25 12:22:23 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1066752447 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 497.prim_prince_test.1066752447
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/497.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/498.prim_prince_test.2251903199
Short name T480
Test name
Test status
Simulation time 1795536903 ps
CPU time 34.78 seconds
Started Aug 25 12:21:53 AM UTC 24
Finished Aug 25 12:22:37 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2251903199 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 498.prim_prince_test.2251903199
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/498.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/499.prim_prince_test.4049257961
Short name T487
Test name
Test status
Simulation time 2051617739 ps
CPU time 39.55 seconds
Started Aug 25 12:21:53 AM UTC 24
Finished Aug 25 12:22:43 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4049257961 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 499.prim_prince_test.4049257961
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/499.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/5.prim_prince_test.4216541820
Short name T2
Test name
Test status
Simulation time 784201609 ps
CPU time 16.84 seconds
Started Aug 25 12:14:28 AM UTC 24
Finished Aug 25 12:14:51 AM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4216541820 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 5.prim_prince_test.4216541820
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/5.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/50.prim_prince_test.1495001662
Short name T41
Test name
Test status
Simulation time 1786373687 ps
CPU time 37.48 seconds
Started Aug 25 12:15:08 AM UTC 24
Finished Aug 25 12:15:59 AM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1495001662 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 50.prim_prince_test.1495001662
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/50.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/51.prim_prince_test.2225619347
Short name T26
Test name
Test status
Simulation time 955703445 ps
CPU time 20.28 seconds
Started Aug 25 12:15:14 AM UTC 24
Finished Aug 25 12:15:42 AM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2225619347 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 51.prim_prince_test.2225619347
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/51.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/52.prim_prince_test.697800379
Short name T25
Test name
Test status
Simulation time 849005026 ps
CPU time 18.08 seconds
Started Aug 25 12:15:16 AM UTC 24
Finished Aug 25 12:15:41 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=697800379 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 52.prim_prince_test.697800379
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/52.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/53.prim_prince_test.923964698
Short name T27
Test name
Test status
Simulation time 893150169 ps
CPU time 19.11 seconds
Started Aug 25 12:15:16 AM UTC 24
Finished Aug 25 12:15:42 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=923964698 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 53.prim_prince_test.923964698
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/53.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/54.prim_prince_test.1097898232
Short name T64
Test name
Test status
Simulation time 2316776355 ps
CPU time 48.54 seconds
Started Aug 25 12:15:19 AM UTC 24
Finished Aug 25 12:16:22 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1097898232 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 54.prim_prince_test.1097898232
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/54.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/55.prim_prince_test.2309952186
Short name T69
Test name
Test status
Simulation time 2549673367 ps
CPU time 53.3 seconds
Started Aug 25 12:15:19 AM UTC 24
Finished Aug 25 12:16:29 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2309952186 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 55.prim_prince_test.2309952186
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/55.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/56.prim_prince_test.2846160148
Short name T36
Test name
Test status
Simulation time 1103296457 ps
CPU time 23.13 seconds
Started Aug 25 12:15:21 AM UTC 24
Finished Aug 25 12:15:52 AM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2846160148 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 56.prim_prince_test.2846160148
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/56.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/57.prim_prince_test.36662135
Short name T84
Test name
Test status
Simulation time 3590596856 ps
CPU time 73.25 seconds
Started Aug 25 12:15:23 AM UTC 24
Finished Aug 25 12:16:59 AM UTC 24
Peak memory 154632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=36662135 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 57.prim_prince_test.36662135
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/57.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/58.prim_prince_test.738614813
Short name T40
Test name
Test status
Simulation time 1184191662 ps
CPU time 24.98 seconds
Started Aug 25 12:15:23 AM UTC 24
Finished Aug 25 12:15:57 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=738614813 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 58.prim_prince_test.738614813
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/58.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/59.prim_prince_test.2543528742
Short name T38
Test name
Test status
Simulation time 1054902900 ps
CPU time 22.18 seconds
Started Aug 25 12:15:23 AM UTC 24
Finished Aug 25 12:15:53 AM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2543528742 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 59.prim_prince_test.2543528742
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/59.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/6.prim_prince_test.3949723234
Short name T9
Test name
Test status
Simulation time 1515068085 ps
CPU time 32.21 seconds
Started Aug 25 12:14:28 AM UTC 24
Finished Aug 25 12:15:12 AM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3949723234 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 6.prim_prince_test.3949723234
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/6.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/60.prim_prince_test.3908298601
Short name T49
Test name
Test status
Simulation time 1502373700 ps
CPU time 31.31 seconds
Started Aug 25 12:15:25 AM UTC 24
Finished Aug 25 12:16:07 AM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3908298601 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 60.prim_prince_test.3908298601
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/60.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/61.prim_prince_test.1100302723
Short name T66
Test name
Test status
Simulation time 2261875753 ps
CPU time 47.11 seconds
Started Aug 25 12:15:25 AM UTC 24
Finished Aug 25 12:16:27 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1100302723 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 61.prim_prince_test.1100302723
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/61.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/62.prim_prince_test.2715702966
Short name T91
Test name
Test status
Simulation time 3404527953 ps
CPU time 70.46 seconds
Started Aug 25 12:15:25 AM UTC 24
Finished Aug 25 12:16:57 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2715702966 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 62.prim_prince_test.2715702966
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/62.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/63.prim_prince_test.1502729033
Short name T46
Test name
Test status
Simulation time 1214376021 ps
CPU time 25.55 seconds
Started Aug 25 12:15:28 AM UTC 24
Finished Aug 25 12:16:02 AM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1502729033 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 63.prim_prince_test.1502729033
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/63.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/64.prim_prince_test.2074958599
Short name T78
Test name
Test status
Simulation time 2937095436 ps
CPU time 60.69 seconds
Started Aug 25 12:15:28 AM UTC 24
Finished Aug 25 12:16:47 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2074958599 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 64.prim_prince_test.2074958599
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/64.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/65.prim_prince_test.1447494281
Short name T42
Test name
Test status
Simulation time 1003766497 ps
CPU time 21.13 seconds
Started Aug 25 12:15:31 AM UTC 24
Finished Aug 25 12:15:59 AM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1447494281 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 65.prim_prince_test.1447494281
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/65.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/66.prim_prince_test.2440057343
Short name T53
Test name
Test status
Simulation time 1391231517 ps
CPU time 29.04 seconds
Started Aug 25 12:15:31 AM UTC 24
Finished Aug 25 12:16:09 AM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2440057343 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 66.prim_prince_test.2440057343
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/66.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/67.prim_prince_test.102464010
Short name T62
Test name
Test status
Simulation time 1680799013 ps
CPU time 34.98 seconds
Started Aug 25 12:15:33 AM UTC 24
Finished Aug 25 12:16:19 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=102464010 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 67.prim_prince_test.102464010
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/67.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/68.prim_prince_test.791509619
Short name T87
Test name
Test status
Simulation time 2911770352 ps
CPU time 60.75 seconds
Started Aug 25 12:15:33 AM UTC 24
Finished Aug 25 12:16:52 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=791509619 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 68.prim_prince_test.791509619
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/68.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/69.prim_prince_test.1740029197
Short name T76
Test name
Test status
Simulation time 2414080453 ps
CPU time 50.39 seconds
Started Aug 25 12:15:38 AM UTC 24
Finished Aug 25 12:16:44 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1740029197 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 69.prim_prince_test.1740029197
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/69.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/7.prim_prince_test.302441498
Short name T39
Test name
Test status
Simulation time 3104250363 ps
CPU time 64.54 seconds
Started Aug 25 12:14:28 AM UTC 24
Finished Aug 25 12:15:54 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=302441498 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 7.prim_prince_test.302441498
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/7.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/70.prim_prince_test.1011985391
Short name T73
Test name
Test status
Simulation time 2266035043 ps
CPU time 47.17 seconds
Started Aug 25 12:15:40 AM UTC 24
Finished Aug 25 12:16:41 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1011985391 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 70.prim_prince_test.1011985391
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/70.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/71.prim_prince_test.4053455931
Short name T71
Test name
Test status
Simulation time 1926369014 ps
CPU time 40 seconds
Started Aug 25 12:15:40 AM UTC 24
Finished Aug 25 12:16:32 AM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4053455931 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 71.prim_prince_test.4053455931
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/71.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/72.prim_prince_test.1874768469
Short name T68
Test name
Test status
Simulation time 1739476020 ps
CPU time 36.5 seconds
Started Aug 25 12:15:40 AM UTC 24
Finished Aug 25 12:16:27 AM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1874768469 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 72.prim_prince_test.1874768469
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/72.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/73.prim_prince_test.1517526957
Short name T65
Test name
Test status
Simulation time 1569986461 ps
CPU time 32.87 seconds
Started Aug 25 12:15:41 AM UTC 24
Finished Aug 25 12:16:24 AM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1517526957 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 73.prim_prince_test.1517526957
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/73.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/74.prim_prince_test.3940858289
Short name T51
Test name
Test status
Simulation time 951092835 ps
CPU time 20.18 seconds
Started Aug 25 12:15:42 AM UTC 24
Finished Aug 25 12:16:09 AM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3940858289 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 74.prim_prince_test.3940858289
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/74.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/75.prim_prince_test.3894860233
Short name T96
Test name
Test status
Simulation time 3038072539 ps
CPU time 63.07 seconds
Started Aug 25 12:15:42 AM UTC 24
Finished Aug 25 12:17:05 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3894860233 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 75.prim_prince_test.3894860233
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/75.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/76.prim_prince_test.2601159196
Short name T61
Test name
Test status
Simulation time 1257934928 ps
CPU time 26.52 seconds
Started Aug 25 12:15:42 AM UTC 24
Finished Aug 25 12:16:17 AM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2601159196 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 76.prim_prince_test.2601159196
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/76.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/77.prim_prince_test.860177120
Short name T86
Test name
Test status
Simulation time 2487461237 ps
CPU time 51.63 seconds
Started Aug 25 12:15:44 AM UTC 24
Finished Aug 25 12:16:51 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=860177120 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 77.prim_prince_test.860177120
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/77.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/78.prim_prince_test.3537841985
Short name T105
Test name
Test status
Simulation time 3445599330 ps
CPU time 70.85 seconds
Started Aug 25 12:15:44 AM UTC 24
Finished Aug 25 12:17:16 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3537841985 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 78.prim_prince_test.3537841985
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/78.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/79.prim_prince_test.4052509025
Short name T112
Test name
Test status
Simulation time 3560476935 ps
CPU time 73.33 seconds
Started Aug 25 12:15:45 AM UTC 24
Finished Aug 25 12:17:20 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4052509025 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 79.prim_prince_test.4052509025
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/79.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/8.prim_prince_test.3370650603
Short name T23
Test name
Test status
Simulation time 2214445861 ps
CPU time 46.92 seconds
Started Aug 25 12:14:28 AM UTC 24
Finished Aug 25 12:15:32 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3370650603 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 8.prim_prince_test.3370650603
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/8.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/80.prim_prince_test.2849626070
Short name T107
Test name
Test status
Simulation time 3451994634 ps
CPU time 70.68 seconds
Started Aug 25 12:15:45 AM UTC 24
Finished Aug 25 12:17:17 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2849626070 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 80.prim_prince_test.2849626070
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/80.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/81.prim_prince_test.2990551062
Short name T108
Test name
Test status
Simulation time 3498454149 ps
CPU time 72.01 seconds
Started Aug 25 12:15:45 AM UTC 24
Finished Aug 25 12:17:19 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2990551062 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 81.prim_prince_test.2990551062
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/81.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/82.prim_prince_test.1922840704
Short name T80
Test name
Test status
Simulation time 2295115751 ps
CPU time 47.69 seconds
Started Aug 25 12:15:46 AM UTC 24
Finished Aug 25 12:16:49 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1922840704 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 82.prim_prince_test.1922840704
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/82.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/83.prim_prince_test.1127551879
Short name T72
Test name
Test status
Simulation time 1982736516 ps
CPU time 41.52 seconds
Started Aug 25 12:15:46 AM UTC 24
Finished Aug 25 12:16:41 AM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1127551879 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 83.prim_prince_test.1127551879
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/83.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/84.prim_prince_test.3372160900
Short name T88
Test name
Test status
Simulation time 2486524175 ps
CPU time 51.36 seconds
Started Aug 25 12:15:46 AM UTC 24
Finished Aug 25 12:16:53 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3372160900 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 84.prim_prince_test.3372160900
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/84.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/85.prim_prince_test.2976978025
Short name T99
Test name
Test status
Simulation time 3008994074 ps
CPU time 62.22 seconds
Started Aug 25 12:15:50 AM UTC 24
Finished Aug 25 12:17:11 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2976978025 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 85.prim_prince_test.2976978025
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/85.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/86.prim_prince_test.26220076
Short name T116
Test name
Test status
Simulation time 3427531296 ps
CPU time 70.96 seconds
Started Aug 25 12:15:50 AM UTC 24
Finished Aug 25 12:17:23 AM UTC 24
Peak memory 154632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26220076 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 86.prim_prince_test.26220076
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/86.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/87.prim_prince_test.1946694951
Short name T121
Test name
Test status
Simulation time 3599050978 ps
CPU time 74.86 seconds
Started Aug 25 12:15:53 AM UTC 24
Finished Aug 25 12:17:30 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1946694951 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 87.prim_prince_test.1946694951
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/87.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/88.prim_prince_test.1025811581
Short name T75
Test name
Test status
Simulation time 1850183840 ps
CPU time 38.34 seconds
Started Aug 25 12:15:53 AM UTC 24
Finished Aug 25 12:16:43 AM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1025811581 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 88.prim_prince_test.1025811581
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/88.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/89.prim_prince_test.2273901887
Short name T70
Test name
Test status
Simulation time 1300356546 ps
CPU time 27.26 seconds
Started Aug 25 12:15:54 AM UTC 24
Finished Aug 25 12:16:30 AM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2273901887 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 89.prim_prince_test.2273901887
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/89.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/9.prim_prince_test.3773767777
Short name T29
Test name
Test status
Simulation time 2681513530 ps
CPU time 56.23 seconds
Started Aug 25 12:14:28 AM UTC 24
Finished Aug 25 12:15:44 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3773767777 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 9.prim_prince_test.3773767777
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/9.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/90.prim_prince_test.1052406877
Short name T79
Test name
Test status
Simulation time 2022047130 ps
CPU time 41.97 seconds
Started Aug 25 12:15:54 AM UTC 24
Finished Aug 25 12:16:49 AM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1052406877 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 90.prim_prince_test.1052406877
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/90.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/91.prim_prince_test.1980735937
Short name T106
Test name
Test status
Simulation time 3051945417 ps
CPU time 63.05 seconds
Started Aug 25 12:15:55 AM UTC 24
Finished Aug 25 12:17:17 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1980735937 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 91.prim_prince_test.1980735937
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/91.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/92.prim_prince_test.3814665331
Short name T83
Test name
Test status
Simulation time 1938197274 ps
CPU time 39.7 seconds
Started Aug 25 12:15:58 AM UTC 24
Finished Aug 25 12:16:50 AM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3814665331 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 92.prim_prince_test.3814665331
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/92.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/93.prim_prince_test.4189254077
Short name T90
Test name
Test status
Simulation time 2099983836 ps
CPU time 43.29 seconds
Started Aug 25 12:15:59 AM UTC 24
Finished Aug 25 12:16:56 AM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4189254077 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 93.prim_prince_test.4189254077
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/93.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/94.prim_prince_test.815199794
Short name T113
Test name
Test status
Simulation time 3011790443 ps
CPU time 61.86 seconds
Started Aug 25 12:16:00 AM UTC 24
Finished Aug 25 12:17:20 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=815199794 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 94.prim_prince_test.815199794
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/94.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/95.prim_prince_test.2884701587
Short name T104
Test name
Test status
Simulation time 2728891990 ps
CPU time 56.45 seconds
Started Aug 25 12:16:01 AM UTC 24
Finished Aug 25 12:17:15 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2884701587 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 95.prim_prince_test.2884701587
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/95.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/96.prim_prince_test.945711956
Short name T114
Test name
Test status
Simulation time 2900103518 ps
CPU time 60.16 seconds
Started Aug 25 12:16:02 AM UTC 24
Finished Aug 25 12:17:20 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=945711956 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 96.prim_prince_test.945711956
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/96.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/97.prim_prince_test.1071851562
Short name T94
Test name
Test status
Simulation time 2269582911 ps
CPU time 47.07 seconds
Started Aug 25 12:16:02 AM UTC 24
Finished Aug 25 12:17:04 AM UTC 24
Peak memory 154552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1071851562 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 97.prim_prince_test.1071851562
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/97.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/98.prim_prince_test.1832618504
Short name T82
Test name
Test status
Simulation time 1739861243 ps
CPU time 36.09 seconds
Started Aug 25 12:16:02 AM UTC 24
Finished Aug 25 12:16:50 AM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1832618504 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 98.prim_prince_test.1832618504
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/98.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default/99.prim_prince_test.3400042466
Short name T127
Test name
Test status
Simulation time 3461666543 ps
CPU time 70.98 seconds
Started Aug 25 12:16:04 AM UTC 24
Finished Aug 25 12:17:37 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3400042466 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 99.prim_prince_test.3400042466
Directory /workspaces/repo/scratch/os_regression_2024_08_24/prim_prince-sim-vcs/99.prim_prince_test/latest
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