SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 | 100.00 | 100.00 |
T251 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/248.prim_prince_test.3885268278 | Aug 27 12:52:22 AM UTC 24 | Aug 27 12:53:22 AM UTC 24 | 2733923083 ps | ||
T252 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/242.prim_prince_test.1388660221 | Aug 27 12:52:08 AM UTC 24 | Aug 27 12:53:28 AM UTC 24 | 3664177106 ps | ||
T253 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/247.prim_prince_test.2961781178 | Aug 27 12:52:20 AM UTC 24 | Aug 27 12:53:28 AM UTC 24 | 3176728001 ps | ||
T254 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/246.prim_prince_test.1853340926 | Aug 27 12:52:18 AM UTC 24 | Aug 27 12:53:32 AM UTC 24 | 3382091528 ps | ||
T255 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/250.prim_prince_test.3519201598 | Aug 27 12:52:23 AM UTC 24 | Aug 27 12:53:35 AM UTC 24 | 3297630379 ps | ||
T256 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/249.prim_prince_test.332749229 | Aug 27 12:52:22 AM UTC 24 | Aug 27 12:53:37 AM UTC 24 | 3443728350 ps | ||
T257 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/253.prim_prince_test.3458484839 | Aug 27 12:52:39 AM UTC 24 | Aug 27 12:53:37 AM UTC 24 | 2623385548 ps | ||
T258 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/254.prim_prince_test.29200099 | Aug 27 12:52:39 AM UTC 24 | Aug 27 12:53:42 AM UTC 24 | 2874448610 ps | ||
T259 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/261.prim_prince_test.3336508581 | Aug 27 12:52:56 AM UTC 24 | Aug 27 12:53:44 AM UTC 24 | 2170616866 ps | ||
T260 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/260.prim_prince_test.4273841077 | Aug 27 12:52:53 AM UTC 24 | Aug 27 12:53:48 AM UTC 24 | 2515848757 ps | ||
T261 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/257.prim_prince_test.3225648313 | Aug 27 12:52:44 AM UTC 24 | Aug 27 12:53:52 AM UTC 24 | 3146860546 ps | ||
T262 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/269.prim_prince_test.3364788966 | Aug 27 12:53:29 AM UTC 24 | Aug 27 12:53:54 AM UTC 24 | 1114506748 ps | ||
T263 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/265.prim_prince_test.745319503 | Aug 27 12:53:17 AM UTC 24 | Aug 27 12:53:57 AM UTC 24 | 1831155887 ps | ||
T264 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/273.prim_prince_test.4293733350 | Aug 27 12:53:38 AM UTC 24 | Aug 27 12:53:58 AM UTC 24 | 884887077 ps | ||
T265 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/263.prim_prince_test.2129959775 | Aug 27 12:53:12 AM UTC 24 | Aug 27 12:54:00 AM UTC 24 | 2176392196 ps | ||
T266 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/259.prim_prince_test.1897812857 | Aug 27 12:52:53 AM UTC 24 | Aug 27 12:54:01 AM UTC 24 | 3124667387 ps | ||
T267 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/268.prim_prince_test.538733526 | Aug 27 12:53:23 AM UTC 24 | Aug 27 12:54:04 AM UTC 24 | 1886466934 ps | ||
T268 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/267.prim_prince_test.1457217490 | Aug 27 12:53:20 AM UTC 24 | Aug 27 12:54:06 AM UTC 24 | 2098624782 ps | ||
T269 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/264.prim_prince_test.2431154817 | Aug 27 12:53:14 AM UTC 24 | Aug 27 12:54:11 AM UTC 24 | 2635281575 ps | ||
T270 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/274.prim_prince_test.2122501883 | Aug 27 12:53:38 AM UTC 24 | Aug 27 12:54:16 AM UTC 24 | 1741068023 ps | ||
T271 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/275.prim_prince_test.2802174576 | Aug 27 12:53:42 AM UTC 24 | Aug 27 12:54:20 AM UTC 24 | 1723900802 ps | ||
T272 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/266.prim_prince_test.285673691 | Aug 27 12:53:19 AM UTC 24 | Aug 27 12:54:23 AM UTC 24 | 2929915635 ps | ||
T273 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/272.prim_prince_test.2752266090 | Aug 27 12:53:36 AM UTC 24 | Aug 27 12:54:27 AM UTC 24 | 2351466975 ps | ||
T274 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/279.prim_prince_test.226258167 | Aug 27 12:53:55 AM UTC 24 | Aug 27 12:54:27 AM UTC 24 | 1442458188 ps | ||
T275 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/285.prim_prince_test.3674569272 | Aug 27 12:54:08 AM UTC 24 | Aug 27 12:54:29 AM UTC 24 | 945447867 ps | ||
T276 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/271.prim_prince_test.3334595762 | Aug 27 12:53:32 AM UTC 24 | Aug 27 12:54:32 AM UTC 24 | 2748727555 ps | ||
T277 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/262.prim_prince_test.398262611 | Aug 27 12:53:11 AM UTC 24 | Aug 27 12:54:32 AM UTC 24 | 3748792115 ps | ||
T278 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/283.prim_prince_test.4208240037 | Aug 27 12:54:02 AM UTC 24 | Aug 27 12:54:36 AM UTC 24 | 1531526943 ps | ||
T279 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/282.prim_prince_test.148533261 | Aug 27 12:54:01 AM UTC 24 | Aug 27 12:54:39 AM UTC 24 | 1728880791 ps | ||
T280 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/276.prim_prince_test.2200951992 | Aug 27 12:53:45 AM UTC 24 | Aug 27 12:54:44 AM UTC 24 | 2728955070 ps | ||
T281 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/286.prim_prince_test.307996903 | Aug 27 12:54:12 AM UTC 24 | Aug 27 12:54:44 AM UTC 24 | 1434091283 ps | ||
T282 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/278.prim_prince_test.3515134279 | Aug 27 12:53:53 AM UTC 24 | Aug 27 12:54:46 AM UTC 24 | 2434836700 ps | ||
T283 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/270.prim_prince_test.3683233858 | Aug 27 12:53:29 AM UTC 24 | Aug 27 12:54:47 AM UTC 24 | 3628206494 ps | ||
T284 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/287.prim_prince_test.1134947033 | Aug 27 12:54:17 AM UTC 24 | Aug 27 12:54:47 AM UTC 24 | 1348980495 ps | ||
T285 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/284.prim_prince_test.758948335 | Aug 27 12:54:05 AM UTC 24 | Aug 27 12:54:58 AM UTC 24 | 2442542150 ps | ||
T286 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/277.prim_prince_test.2096328994 | Aug 27 12:53:49 AM UTC 24 | Aug 27 12:55:01 AM UTC 24 | 3313954109 ps | ||
T287 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/280.prim_prince_test.349304806 | Aug 27 12:53:59 AM UTC 24 | Aug 27 12:55:07 AM UTC 24 | 3118940598 ps | ||
T288 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/290.prim_prince_test.2060450489 | Aug 27 12:54:27 AM UTC 24 | Aug 27 12:55:09 AM UTC 24 | 1872659530 ps | ||
T289 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/289.prim_prince_test.604351442 | Aug 27 12:54:24 AM UTC 24 | Aug 27 12:55:10 AM UTC 24 | 2065770154 ps | ||
T290 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/292.prim_prince_test.1411549232 | Aug 27 12:54:31 AM UTC 24 | Aug 27 12:55:10 AM UTC 24 | 1760278347 ps | ||
T291 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/288.prim_prince_test.2060651567 | Aug 27 12:54:21 AM UTC 24 | Aug 27 12:55:13 AM UTC 24 | 2398144190 ps | ||
T292 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/297.prim_prince_test.552130534 | Aug 27 12:54:44 AM UTC 24 | Aug 27 12:55:18 AM UTC 24 | 1504089243 ps | ||
T293 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/281.prim_prince_test.2238205388 | Aug 27 12:53:59 AM UTC 24 | Aug 27 12:55:19 AM UTC 24 | 3668227124 ps | ||
T294 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/295.prim_prince_test.3213159962 | Aug 27 12:54:38 AM UTC 24 | Aug 27 12:55:19 AM UTC 24 | 1872656291 ps | ||
T295 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/294.prim_prince_test.3207167923 | Aug 27 12:54:33 AM UTC 24 | Aug 27 12:55:28 AM UTC 24 | 2490059890 ps | ||
T296 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/293.prim_prince_test.2998591834 | Aug 27 12:54:33 AM UTC 24 | Aug 27 12:55:29 AM UTC 24 | 2526482050 ps | ||
T297 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/299.prim_prince_test.3942019424 | Aug 27 12:54:48 AM UTC 24 | Aug 27 12:55:32 AM UTC 24 | 1978642219 ps | ||
T298 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/301.prim_prince_test.349893984 | Aug 27 12:54:48 AM UTC 24 | Aug 27 12:55:33 AM UTC 24 | 2046167366 ps | ||
T299 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/302.prim_prince_test.3488113143 | Aug 27 12:54:58 AM UTC 24 | Aug 27 12:55:39 AM UTC 24 | 1824042599 ps | ||
T300 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/300.prim_prince_test.1131135066 | Aug 27 12:54:48 AM UTC 24 | Aug 27 12:55:40 AM UTC 24 | 2372218615 ps | ||
T301 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/291.prim_prince_test.1215021954 | Aug 27 12:54:28 AM UTC 24 | Aug 27 12:55:41 AM UTC 24 | 3349389987 ps | ||
T302 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/309.prim_prince_test.1173419770 | Aug 27 12:55:20 AM UTC 24 | Aug 27 12:55:43 AM UTC 24 | 1017692430 ps | ||
T303 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/308.prim_prince_test.2756676878 | Aug 27 12:55:15 AM UTC 24 | Aug 27 12:55:50 AM UTC 24 | 1556770488 ps | ||
T304 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/304.prim_prince_test.1362303489 | Aug 27 12:55:09 AM UTC 24 | Aug 27 12:55:53 AM UTC 24 | 1954774110 ps | ||
T305 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/298.prim_prince_test.3474441145 | Aug 27 12:54:45 AM UTC 24 | Aug 27 12:55:54 AM UTC 24 | 3122358488 ps | ||
T306 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/312.prim_prince_test.3907517319 | Aug 27 12:55:23 AM UTC 24 | Aug 27 12:55:54 AM UTC 24 | 1359667758 ps | ||
T307 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/296.prim_prince_test.3659502381 | Aug 27 12:54:40 AM UTC 24 | Aug 27 12:55:55 AM UTC 24 | 3466143949 ps | ||
T308 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/311.prim_prince_test.3505799502 | Aug 27 12:55:20 AM UTC 24 | Aug 27 12:55:58 AM UTC 24 | 1735136948 ps | ||
T309 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/310.prim_prince_test.806706500 | Aug 27 12:55:20 AM UTC 24 | Aug 27 12:56:02 AM UTC 24 | 1939719649 ps | ||
T310 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/315.prim_prince_test.3436851811 | Aug 27 12:55:33 AM UTC 24 | Aug 27 12:56:09 AM UTC 24 | 1673355181 ps | ||
T311 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/316.prim_prince_test.3864554857 | Aug 27 12:55:34 AM UTC 24 | Aug 27 12:56:13 AM UTC 24 | 1757507926 ps | ||
T312 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/306.prim_prince_test.3817835749 | Aug 27 12:55:12 AM UTC 24 | Aug 27 12:56:14 AM UTC 24 | 2888201775 ps | ||
T313 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/313.prim_prince_test.4074570957 | Aug 27 12:55:28 AM UTC 24 | Aug 27 12:56:16 AM UTC 24 | 2161881621 ps | ||
T314 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/305.prim_prince_test.1971110975 | Aug 27 12:55:12 AM UTC 24 | Aug 27 12:56:19 AM UTC 24 | 3077848671 ps | ||
T315 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/303.prim_prince_test.2920253472 | Aug 27 12:55:03 AM UTC 24 | Aug 27 12:56:19 AM UTC 24 | 3511321627 ps | ||
T316 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/319.prim_prince_test.136200003 | Aug 27 12:55:42 AM UTC 24 | Aug 27 12:56:30 AM UTC 24 | 2154662029 ps | ||
T317 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/307.prim_prince_test.1345990484 | Aug 27 12:55:12 AM UTC 24 | Aug 27 12:56:30 AM UTC 24 | 3608195985 ps | ||
T318 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/317.prim_prince_test.220874298 | Aug 27 12:55:40 AM UTC 24 | Aug 27 12:56:31 AM UTC 24 | 2341586373 ps | ||
T319 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/323.prim_prince_test.3425709036 | Aug 27 12:55:55 AM UTC 24 | Aug 27 12:56:32 AM UTC 24 | 1650749220 ps | ||
T320 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/328.prim_prince_test.3477948382 | Aug 27 12:56:10 AM UTC 24 | Aug 27 12:56:33 AM UTC 24 | 1009746386 ps | ||
T321 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/321.prim_prince_test.3574092186 | Aug 27 12:55:51 AM UTC 24 | Aug 27 12:56:34 AM UTC 24 | 1959368554 ps | ||
T322 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/314.prim_prince_test.2660639958 | Aug 27 12:55:30 AM UTC 24 | Aug 27 12:56:43 AM UTC 24 | 3390722560 ps | ||
T323 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/322.prim_prince_test.2328910615 | Aug 27 12:55:53 AM UTC 24 | Aug 27 12:56:49 AM UTC 24 | 2558340004 ps | ||
T324 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/324.prim_prince_test.1098143883 | Aug 27 12:55:55 AM UTC 24 | Aug 27 12:56:50 AM UTC 24 | 2519774723 ps | ||
T325 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/318.prim_prince_test.493145134 | Aug 27 12:55:41 AM UTC 24 | Aug 27 12:56:51 AM UTC 24 | 3234058334 ps | ||
T326 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/332.prim_prince_test.3656799987 | Aug 27 12:56:20 AM UTC 24 | Aug 27 12:56:51 AM UTC 24 | 1359091436 ps | ||
T327 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/325.prim_prince_test.1634549933 | Aug 27 12:55:56 AM UTC 24 | Aug 27 12:56:51 AM UTC 24 | 2543241079 ps | ||
T328 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/327.prim_prince_test.2218356265 | Aug 27 12:56:04 AM UTC 24 | Aug 27 12:56:52 AM UTC 24 | 2193177194 ps | ||
T329 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/336.prim_prince_test.4173393864 | Aug 27 12:56:33 AM UTC 24 | Aug 27 12:56:52 AM UTC 24 | 841874986 ps | ||
T330 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/330.prim_prince_test.2543422493 | Aug 27 12:56:15 AM UTC 24 | Aug 27 12:56:56 AM UTC 24 | 1857650709 ps | ||
T331 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/320.prim_prince_test.237834187 | Aug 27 12:55:44 AM UTC 24 | Aug 27 12:56:57 AM UTC 24 | 3383734676 ps | ||
T332 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/338.prim_prince_test.3107987210 | Aug 27 12:56:34 AM UTC 24 | Aug 27 12:56:59 AM UTC 24 | 1147100721 ps | ||
T333 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/335.prim_prince_test.1901806793 | Aug 27 12:56:31 AM UTC 24 | Aug 27 12:57:00 AM UTC 24 | 1287490689 ps | ||
T334 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/326.prim_prince_test.3334858932 | Aug 27 12:55:59 AM UTC 24 | Aug 27 12:57:15 AM UTC 24 | 3509196175 ps | ||
T335 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/329.prim_prince_test.1516463280 | Aug 27 12:56:14 AM UTC 24 | Aug 27 12:57:21 AM UTC 24 | 3072826435 ps | ||
T336 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/333.prim_prince_test.756095340 | Aug 27 12:56:20 AM UTC 24 | Aug 27 12:57:21 AM UTC 24 | 2805644119 ps | ||
T337 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/341.prim_prince_test.2218346206 | Aug 27 12:56:50 AM UTC 24 | Aug 27 12:57:26 AM UTC 24 | 1631716891 ps | ||
T338 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/351.prim_prince_test.1381012499 | Aug 27 12:57:01 AM UTC 24 | Aug 27 12:57:26 AM UTC 24 | 1116533440 ps | ||
T339 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/340.prim_prince_test.87713502 | Aug 27 12:56:45 AM UTC 24 | Aug 27 12:57:27 AM UTC 24 | 1931020588 ps | ||
T340 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/348.prim_prince_test.3334762335 | Aug 27 12:56:57 AM UTC 24 | Aug 27 12:57:28 AM UTC 24 | 1415047432 ps | ||
T341 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/339.prim_prince_test.3629328798 | Aug 27 12:56:35 AM UTC 24 | Aug 27 12:57:29 AM UTC 24 | 2465733705 ps | ||
T342 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/342.prim_prince_test.4024542564 | Aug 27 12:56:52 AM UTC 24 | Aug 27 12:57:30 AM UTC 24 | 1738750673 ps | ||
T343 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/337.prim_prince_test.1894810809 | Aug 27 12:56:33 AM UTC 24 | Aug 27 12:57:31 AM UTC 24 | 2667777657 ps | ||
T344 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/331.prim_prince_test.3020660756 | Aug 27 12:56:17 AM UTC 24 | Aug 27 12:57:31 AM UTC 24 | 3462093668 ps | ||
T345 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/346.prim_prince_test.146608380 | Aug 27 12:56:54 AM UTC 24 | Aug 27 12:57:43 AM UTC 24 | 2287739655 ps | ||
T346 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/345.prim_prince_test.3084530485 | Aug 27 12:56:54 AM UTC 24 | Aug 27 12:57:45 AM UTC 24 | 2398577635 ps | ||
T347 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/349.prim_prince_test.989549789 | Aug 27 12:56:58 AM UTC 24 | Aug 27 12:57:45 AM UTC 24 | 2173007199 ps | ||
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T349 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/350.prim_prince_test.1373703406 | Aug 27 12:57:01 AM UTC 24 | Aug 27 12:57:51 AM UTC 24 | 2341033824 ps | ||
T350 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/347.prim_prince_test.3687080079 | Aug 27 12:56:54 AM UTC 24 | Aug 27 12:57:54 AM UTC 24 | 2794322826 ps | ||
T351 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/360.prim_prince_test.100435399 | Aug 27 12:57:31 AM UTC 24 | Aug 27 12:57:56 AM UTC 24 | 1127540982 ps | ||
T352 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/355.prim_prince_test.4032133730 | Aug 27 12:57:26 AM UTC 24 | Aug 27 12:58:00 AM UTC 24 | 1532961678 ps | ||
T353 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/358.prim_prince_test.2883034954 | Aug 27 12:57:29 AM UTC 24 | Aug 27 12:58:05 AM UTC 24 | 1656989057 ps | ||
T354 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/354.prim_prince_test.445142278 | Aug 27 12:57:23 AM UTC 24 | Aug 27 12:58:08 AM UTC 24 | 2042990697 ps | ||
T355 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/344.prim_prince_test.1543424240 | Aug 27 12:56:52 AM UTC 24 | Aug 27 12:58:09 AM UTC 24 | 3600362272 ps | ||
T356 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/352.prim_prince_test.176742488 | Aug 27 12:57:16 AM UTC 24 | Aug 27 12:58:10 AM UTC 24 | 2484693811 ps | ||
T357 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/343.prim_prince_test.742238141 | Aug 27 12:56:52 AM UTC 24 | Aug 27 12:58:12 AM UTC 24 | 3732299743 ps | ||
T358 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/364.prim_prince_test.1339719561 | Aug 27 12:57:46 AM UTC 24 | Aug 27 12:58:24 AM UTC 24 | 1720123040 ps | ||
T359 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/367.prim_prince_test.1724378543 | Aug 27 12:57:52 AM UTC 24 | Aug 27 12:58:24 AM UTC 24 | 1455707523 ps | ||
T360 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/353.prim_prince_test.2551169528 | Aug 27 12:57:23 AM UTC 24 | Aug 27 12:58:24 AM UTC 24 | 2814593630 ps | ||
T361 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/369.prim_prince_test.5238307 | Aug 27 12:57:58 AM UTC 24 | Aug 27 12:58:28 AM UTC 24 | 1373639206 ps | ||
T362 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/359.prim_prince_test.919104420 | Aug 27 12:57:31 AM UTC 24 | Aug 27 12:58:28 AM UTC 24 | 2602943906 ps | ||
T363 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/368.prim_prince_test.706942285 | Aug 27 12:57:55 AM UTC 24 | Aug 27 12:58:34 AM UTC 24 | 1769983717 ps | ||
T364 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/375.prim_prince_test.569085242 | Aug 27 12:58:13 AM UTC 24 | Aug 27 12:58:36 AM UTC 24 | 1037494154 ps | ||
T365 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/357.prim_prince_test.2044157682 | Aug 27 12:57:28 AM UTC 24 | Aug 27 12:58:39 AM UTC 24 | 3290538102 ps | ||
T366 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/366.prim_prince_test.732408050 | Aug 27 12:57:52 AM UTC 24 | Aug 27 12:58:41 AM UTC 24 | 2276463247 ps | ||
T367 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/361.prim_prince_test.3534145351 | Aug 27 12:57:32 AM UTC 24 | Aug 27 12:58:43 AM UTC 24 | 3234273750 ps | ||
T368 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/356.prim_prince_test.2375440300 | Aug 27 12:57:28 AM UTC 24 | Aug 27 12:58:44 AM UTC 24 | 3565293451 ps | ||
T369 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/362.prim_prince_test.2495704597 | Aug 27 12:57:32 AM UTC 24 | Aug 27 12:58:51 AM UTC 24 | 3654857304 ps | ||
T370 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/381.prim_prince_test.1852364051 | Aug 27 12:58:35 AM UTC 24 | Aug 27 12:58:53 AM UTC 24 | 810151697 ps | ||
T371 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/376.prim_prince_test.3076034239 | Aug 27 12:58:26 AM UTC 24 | Aug 27 12:58:53 AM UTC 24 | 1244777059 ps | ||
T372 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/372.prim_prince_test.880771507 | Aug 27 12:58:09 AM UTC 24 | Aug 27 12:58:56 AM UTC 24 | 2150549254 ps | ||
T373 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/363.prim_prince_test.4132657872 | Aug 27 12:57:45 AM UTC 24 | Aug 27 12:58:59 AM UTC 24 | 3428667374 ps | ||
T374 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/370.prim_prince_test.4187380434 | Aug 27 12:58:01 AM UTC 24 | Aug 27 12:59:01 AM UTC 24 | 2731053786 ps | ||
T375 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/365.prim_prince_test.3633173573 | Aug 27 12:57:46 AM UTC 24 | Aug 27 12:59:01 AM UTC 24 | 3454274665 ps | ||
T376 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/374.prim_prince_test.1232687923 | Aug 27 12:58:11 AM UTC 24 | Aug 27 12:59:04 AM UTC 24 | 2450534606 ps | ||
T377 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/380.prim_prince_test.1553369878 | Aug 27 12:58:29 AM UTC 24 | Aug 27 12:59:06 AM UTC 24 | 1657083834 ps | ||
T378 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/385.prim_prince_test.2424984139 | Aug 27 12:58:43 AM UTC 24 | Aug 27 12:59:11 AM UTC 24 | 1254570415 ps | ||
T379 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/382.prim_prince_test.2115286922 | Aug 27 12:58:37 AM UTC 24 | Aug 27 12:59:13 AM UTC 24 | 1632509303 ps | ||
T380 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/384.prim_prince_test.3115611121 | Aug 27 12:58:42 AM UTC 24 | Aug 27 12:59:14 AM UTC 24 | 1477954924 ps | ||
T381 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/371.prim_prince_test.3461031649 | Aug 27 12:58:06 AM UTC 24 | Aug 27 12:59:19 AM UTC 24 | 3363480502 ps | ||
T382 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/373.prim_prince_test.1077065894 | Aug 27 12:58:10 AM UTC 24 | Aug 27 12:59:20 AM UTC 24 | 3260108782 ps | ||
T383 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/391.prim_prince_test.1197658561 | Aug 27 12:59:00 AM UTC 24 | Aug 27 12:59:23 AM UTC 24 | 992379094 ps | ||
T384 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/377.prim_prince_test.3060936457 | Aug 27 12:58:26 AM UTC 24 | Aug 27 12:59:25 AM UTC 24 | 2731503723 ps | ||
T385 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/388.prim_prince_test.207821665 | Aug 27 12:58:54 AM UTC 24 | Aug 27 12:59:30 AM UTC 24 | 1596406378 ps | ||
T386 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/389.prim_prince_test.2401939207 | Aug 27 12:58:54 AM UTC 24 | Aug 27 12:59:34 AM UTC 24 | 1823653488 ps | ||
T387 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/383.prim_prince_test.695596252 | Aug 27 12:58:39 AM UTC 24 | Aug 27 12:59:36 AM UTC 24 | 2623002425 ps | ||
T388 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/378.prim_prince_test.3685466857 | Aug 27 12:58:26 AM UTC 24 | Aug 27 12:59:38 AM UTC 24 | 3340990388 ps | ||
T389 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/379.prim_prince_test.3714180216 | Aug 27 12:58:29 AM UTC 24 | Aug 27 12:59:45 AM UTC 24 | 3487349775 ps | ||
T390 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/390.prim_prince_test.2443666090 | Aug 27 12:58:57 AM UTC 24 | Aug 27 12:59:51 AM UTC 24 | 2489886170 ps | ||
T391 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/386.prim_prince_test.745924589 | Aug 27 12:58:45 AM UTC 24 | Aug 27 12:59:56 AM UTC 24 | 3279824284 ps | ||
T392 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/398.prim_prince_test.1508046842 | Aug 27 12:59:16 AM UTC 24 | Aug 27 12:59:58 AM UTC 24 | 1941292783 ps | ||
T393 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/393.prim_prince_test.3383480120 | Aug 27 12:59:03 AM UTC 24 | Aug 27 01:00:00 AM UTC 24 | 2637012036 ps | ||
T394 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/419.prim_prince_test.3546737957 | Aug 27 01:00:23 AM UTC 24 | Aug 27 01:01:10 AM UTC 24 | 2115304991 ps | ||
T395 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/401.prim_prince_test.131502142 | Aug 27 12:59:24 AM UTC 24 | Aug 27 01:00:00 AM UTC 24 | 1663766832 ps | ||
T396 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/399.prim_prince_test.2495969262 | Aug 27 12:59:20 AM UTC 24 | Aug 27 01:00:02 AM UTC 24 | 1923202277 ps | ||
T397 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/396.prim_prince_test.526393603 | Aug 27 12:59:12 AM UTC 24 | Aug 27 01:00:09 AM UTC 24 | 2614435394 ps | ||
T398 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/387.prim_prince_test.3289994823 | Aug 27 12:58:52 AM UTC 24 | Aug 27 01:00:10 AM UTC 24 | 3639507245 ps | ||
T399 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/392.prim_prince_test.3166432629 | Aug 27 12:59:02 AM UTC 24 | Aug 27 01:00:11 AM UTC 24 | 3193963649 ps | ||
T400 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/397.prim_prince_test.3370350279 | Aug 27 12:59:14 AM UTC 24 | Aug 27 01:00:19 AM UTC 24 | 2977708912 ps | ||
T401 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/394.prim_prince_test.760890324 | Aug 27 12:59:05 AM UTC 24 | Aug 27 01:00:21 AM UTC 24 | 3519652136 ps | ||
T402 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/407.prim_prince_test.928338440 | Aug 27 12:59:46 AM UTC 24 | Aug 27 01:00:22 AM UTC 24 | 1631249393 ps | ||
T403 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/405.prim_prince_test.25610944 | Aug 27 12:59:37 AM UTC 24 | Aug 27 01:00:25 AM UTC 24 | 2197155192 ps | ||
T404 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/400.prim_prince_test.3120683322 | Aug 27 12:59:21 AM UTC 24 | Aug 27 01:00:27 AM UTC 24 | 3010694839 ps | ||
T405 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/395.prim_prince_test.2109224867 | Aug 27 12:59:08 AM UTC 24 | Aug 27 01:00:28 AM UTC 24 | 3711465781 ps | ||
T406 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/412.prim_prince_test.268540236 | Aug 27 01:00:02 AM UTC 24 | Aug 27 01:00:28 AM UTC 24 | 1041601985 ps | ||
T407 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/411.prim_prince_test.1379048325 | Aug 27 01:00:00 AM UTC 24 | Aug 27 01:00:33 AM UTC 24 | 1284195110 ps | ||
T408 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/406.prim_prince_test.515534374 | Aug 27 12:59:38 AM UTC 24 | Aug 27 01:00:36 AM UTC 24 | 2630233556 ps | ||
T409 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/402.prim_prince_test.2605995018 | Aug 27 12:59:26 AM UTC 24 | Aug 27 01:00:42 AM UTC 24 | 3517538743 ps | ||
T410 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/403.prim_prince_test.2449416130 | Aug 27 12:59:31 AM UTC 24 | Aug 27 01:00:42 AM UTC 24 | 3269020042 ps | ||
T411 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/410.prim_prince_test.806959801 | Aug 27 12:59:59 AM UTC 24 | Aug 27 01:00:43 AM UTC 24 | 1983799132 ps | ||
T412 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/417.prim_prince_test.1284417458 | Aug 27 01:00:20 AM UTC 24 | Aug 27 01:00:44 AM UTC 24 | 1086214333 ps | ||
T413 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/418.prim_prince_test.1147482510 | Aug 27 01:00:22 AM UTC 24 | Aug 27 01:00:45 AM UTC 24 | 1010610391 ps | ||
T414 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/414.prim_prince_test.542407568 | Aug 27 01:00:09 AM UTC 24 | Aug 27 01:00:47 AM UTC 24 | 1691923348 ps | ||
T415 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/404.prim_prince_test.515997000 | Aug 27 12:59:36 AM UTC 24 | Aug 27 01:00:48 AM UTC 24 | 3342477889 ps | ||
T416 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/408.prim_prince_test.1773171501 | Aug 27 12:59:52 AM UTC 24 | Aug 27 01:00:52 AM UTC 24 | 2754181190 ps | ||
T417 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/420.prim_prince_test.3102152568 | Aug 27 01:00:27 AM UTC 24 | Aug 27 01:00:52 AM UTC 24 | 1111575404 ps | ||
T418 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/423.prim_prince_test.477677303 | Aug 27 01:00:30 AM UTC 24 | Aug 27 01:00:59 AM UTC 24 | 1286305524 ps | ||
T419 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/421.prim_prince_test.671838433 | Aug 27 01:00:28 AM UTC 24 | Aug 27 01:01:07 AM UTC 24 | 1744351572 ps | ||
T420 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/409.prim_prince_test.682175862 | Aug 27 12:59:58 AM UTC 24 | Aug 27 01:01:08 AM UTC 24 | 3249582451 ps | ||
T421 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/430.prim_prince_test.3789258773 | Aug 27 01:00:46 AM UTC 24 | Aug 27 01:01:14 AM UTC 24 | 1226117774 ps | ||
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T423 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/415.prim_prince_test.873209812 | Aug 27 01:00:12 AM UTC 24 | Aug 27 01:01:17 AM UTC 24 | 2960363647 ps | ||
T424 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/429.prim_prince_test.918047059 | Aug 27 01:00:46 AM UTC 24 | Aug 27 01:01:17 AM UTC 24 | 1399201437 ps | ||
T425 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/427.prim_prince_test.2956644764 | Aug 27 01:00:44 AM UTC 24 | Aug 27 01:01:19 AM UTC 24 | 1585981174 ps | ||
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T427 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/416.prim_prince_test.2126990786 | Aug 27 01:00:12 AM UTC 24 | Aug 27 01:01:22 AM UTC 24 | 3233580135 ps | ||
T428 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/432.prim_prince_test.974049895 | Aug 27 01:00:49 AM UTC 24 | Aug 27 01:01:24 AM UTC 24 | 1583479829 ps | ||
T429 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/413.prim_prince_test.3957020679 | Aug 27 01:00:06 AM UTC 24 | Aug 27 01:01:25 AM UTC 24 | 3683339827 ps | ||
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T431 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/438.prim_prince_test.115413430 | Aug 27 01:01:11 AM UTC 24 | Aug 27 01:01:37 AM UTC 24 | 1156037467 ps | ||
T432 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/440.prim_prince_test.2267697138 | Aug 27 01:01:17 AM UTC 24 | Aug 27 01:01:38 AM UTC 24 | 887428000 ps | ||
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T440 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/439.prim_prince_test.1689385881 | Aug 27 01:01:15 AM UTC 24 | Aug 27 01:01:49 AM UTC 24 | 1516323088 ps | ||
T441 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/422.prim_prince_test.2040025562 | Aug 27 01:00:30 AM UTC 24 | Aug 27 01:01:49 AM UTC 24 | 3641216886 ps | ||
T442 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/447.prim_prince_test.3948611217 | Aug 27 01:01:23 AM UTC 24 | Aug 27 01:01:51 AM UTC 24 | 1219705135 ps | ||
T443 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/435.prim_prince_test.2257816834 | Aug 27 01:01:00 AM UTC 24 | Aug 27 01:01:58 AM UTC 24 | 2647913822 ps | ||
T444 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/443.prim_prince_test.4245226975 | Aug 27 01:01:19 AM UTC 24 | Aug 27 01:02:03 AM UTC 24 | 2015041452 ps | ||
T445 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/433.prim_prince_test.3684106720 | Aug 27 01:00:53 AM UTC 24 | Aug 27 01:02:05 AM UTC 24 | 3341790522 ps | ||
T446 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/441.prim_prince_test.3600472545 | Aug 27 01:01:17 AM UTC 24 | Aug 27 01:02:06 AM UTC 24 | 2203707772 ps | ||
T447 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/451.prim_prince_test.311484181 | Aug 27 01:01:38 AM UTC 24 | Aug 27 01:02:09 AM UTC 24 | 1383073164 ps | ||
T448 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/448.prim_prince_test.331687304 | Aug 27 01:01:26 AM UTC 24 | Aug 27 01:02:11 AM UTC 24 | 2068286708 ps | ||
T449 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/457.prim_prince_test.2069510226 | Aug 27 01:01:48 AM UTC 24 | Aug 27 01:02:12 AM UTC 24 | 1089074955 ps | ||
T450 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/434.prim_prince_test.1346291633 | Aug 27 01:00:53 AM UTC 24 | Aug 27 01:02:13 AM UTC 24 | 3701143552 ps | ||
T451 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/455.prim_prince_test.1210477760 | Aug 27 01:01:43 AM UTC 24 | Aug 27 01:02:16 AM UTC 24 | 1467633045 ps | ||
T452 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/463.prim_prince_test.312015016 | Aug 27 01:01:59 AM UTC 24 | Aug 27 01:02:20 AM UTC 24 | 951425537 ps | ||
T453 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/450.prim_prince_test.611069983 | Aug 27 01:01:37 AM UTC 24 | Aug 27 01:02:23 AM UTC 24 | 2124284269 ps | ||
T454 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/442.prim_prince_test.3122879270 | Aug 27 01:01:19 AM UTC 24 | Aug 27 01:02:23 AM UTC 24 | 2969224118 ps | ||
T455 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/462.prim_prince_test.2393106675 | Aug 27 01:01:52 AM UTC 24 | Aug 27 01:02:29 AM UTC 24 | 1676420710 ps | ||
T456 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/458.prim_prince_test.1971168229 | Aug 27 01:01:48 AM UTC 24 | Aug 27 01:02:30 AM UTC 24 | 1948132979 ps | ||
T457 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/452.prim_prince_test.1096358802 | Aug 27 01:01:38 AM UTC 24 | Aug 27 01:02:33 AM UTC 24 | 2531423856 ps | ||
T458 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/445.prim_prince_test.3467849130 | Aug 27 01:01:21 AM UTC 24 | Aug 27 01:02:35 AM UTC 24 | 3443196677 ps | ||
T459 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/454.prim_prince_test.3847935741 | Aug 27 01:01:43 AM UTC 24 | Aug 27 01:02:36 AM UTC 24 | 2410026794 ps | ||
T460 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/461.prim_prince_test.2242988653 | Aug 27 01:01:51 AM UTC 24 | Aug 27 01:02:36 AM UTC 24 | 2079737944 ps | ||
T461 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/468.prim_prince_test.3059234852 | Aug 27 01:02:12 AM UTC 24 | Aug 27 01:02:37 AM UTC 24 | 1119499476 ps | ||
T462 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/460.prim_prince_test.2159296626 | Aug 27 01:01:49 AM UTC 24 | Aug 27 01:02:39 AM UTC 24 | 2264609915 ps | ||
T463 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/465.prim_prince_test.2526931247 | Aug 27 01:02:06 AM UTC 24 | Aug 27 01:02:42 AM UTC 24 | 1661014607 ps | ||
T464 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/456.prim_prince_test.1814152461 | Aug 27 01:01:45 AM UTC 24 | Aug 27 01:02:47 AM UTC 24 | 2847788861 ps | ||
T465 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/469.prim_prince_test.415213696 | Aug 27 01:02:13 AM UTC 24 | Aug 27 01:02:47 AM UTC 24 | 1541312537 ps | ||
T466 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/471.prim_prince_test.882387865 | Aug 27 01:02:17 AM UTC 24 | Aug 27 01:02:51 AM UTC 24 | 1483307374 ps | ||
T467 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/453.prim_prince_test.3368436545 | Aug 27 01:01:42 AM UTC 24 | Aug 27 01:02:53 AM UTC 24 | 3270580466 ps | ||
T468 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/475.prim_prince_test.1949479405 | Aug 27 01:02:31 AM UTC 24 | Aug 27 01:02:59 AM UTC 24 | 1236778085 ps | ||
T469 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/482.prim_prince_test.1921986172 | Aug 27 01:02:40 AM UTC 24 | Aug 27 01:03:05 AM UTC 24 | 1082976612 ps | ||
T470 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/470.prim_prince_test.274293178 | Aug 27 01:02:15 AM UTC 24 | Aug 27 01:03:05 AM UTC 24 | 2311229818 ps | ||
T471 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/459.prim_prince_test.663329935 | Aug 27 01:01:49 AM UTC 24 | Aug 27 01:03:06 AM UTC 24 | 3557753814 ps | ||
T472 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/479.prim_prince_test.2929200241 | Aug 27 01:02:38 AM UTC 24 | Aug 27 01:03:09 AM UTC 24 | 1389829548 ps | ||
T473 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/464.prim_prince_test.3627384529 | Aug 27 01:02:04 AM UTC 24 | Aug 27 01:03:10 AM UTC 24 | 3045001095 ps | ||
T474 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/466.prim_prince_test.2870311066 | Aug 27 01:02:07 AM UTC 24 | Aug 27 01:03:12 AM UTC 24 | 2976016947 ps | ||
T475 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/473.prim_prince_test.1900734860 | Aug 27 01:02:24 AM UTC 24 | Aug 27 01:03:13 AM UTC 24 | 2252982918 ps | ||
T476 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/488.prim_prince_test.418448908 | Aug 27 01:02:54 AM UTC 24 | Aug 27 01:03:19 AM UTC 24 | 1106716885 ps | ||
T477 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/476.prim_prince_test.2809741661 | Aug 27 01:02:32 AM UTC 24 | Aug 27 01:03:20 AM UTC 24 | 2192612046 ps | ||
T478 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/485.prim_prince_test.1693389250 | Aug 27 01:02:47 AM UTC 24 | Aug 27 01:03:25 AM UTC 24 | 1732181459 ps | ||
T479 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/477.prim_prince_test.1351980369 | Aug 27 01:02:34 AM UTC 24 | Aug 27 01:03:27 AM UTC 24 | 2384176821 ps | ||
T480 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/494.prim_prince_test.3701510974 | Aug 27 01:03:10 AM UTC 24 | Aug 27 01:03:30 AM UTC 24 | 890544594 ps | ||
T481 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/467.prim_prince_test.172660785 | Aug 27 01:02:10 AM UTC 24 | Aug 27 01:03:31 AM UTC 24 | 3760052821 ps | ||
T482 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/478.prim_prince_test.1416500689 | Aug 27 01:02:38 AM UTC 24 | Aug 27 01:03:32 AM UTC 24 | 2505768004 ps | ||
T483 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/472.prim_prince_test.2155456680 | Aug 27 01:02:21 AM UTC 24 | Aug 27 01:03:34 AM UTC 24 | 3359436856 ps | ||
T484 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/487.prim_prince_test.1110772579 | Aug 27 01:02:51 AM UTC 24 | Aug 27 01:03:38 AM UTC 24 | 2131089622 ps | ||
T485 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/496.prim_prince_test.4097246545 | Aug 27 01:03:13 AM UTC 24 | Aug 27 01:03:38 AM UTC 24 | 1122027402 ps | ||
T486 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/474.prim_prince_test.2553382917 | Aug 27 01:02:25 AM UTC 24 | Aug 27 01:03:44 AM UTC 24 | 3605864178 ps | ||
T487 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/480.prim_prince_test.3942891605 | Aug 27 01:02:38 AM UTC 24 | Aug 27 01:03:45 AM UTC 24 | 3105230441 ps | ||
T488 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/483.prim_prince_test.1781406906 | Aug 27 01:02:42 AM UTC 24 | Aug 27 01:03:46 AM UTC 24 | 2920199080 ps | ||
T489 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/481.prim_prince_test.4208482667 | Aug 27 01:02:39 AM UTC 24 | Aug 27 01:03:55 AM UTC 24 | 3485024928 ps | ||
T490 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/484.prim_prince_test.1218404663 | Aug 27 01:02:43 AM UTC 24 | Aug 27 01:04:00 AM UTC 24 | 3508523157 ps | ||
T491 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/486.prim_prince_test.4085655295 | Aug 27 01:02:49 AM UTC 24 | Aug 27 01:04:09 AM UTC 24 | 3654673383 ps | ||
T492 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/489.prim_prince_test.1942890308 | Aug 27 01:02:57 AM UTC 24 | Aug 27 01:04:10 AM UTC 24 | 3317961607 ps | ||
T493 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/493.prim_prince_test.1663341964 | Aug 27 01:03:08 AM UTC 24 | Aug 27 01:04:11 AM UTC 24 | 2881851038 ps | ||
T494 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/497.prim_prince_test.1167959211 | Aug 27 01:03:14 AM UTC 24 | Aug 27 01:04:17 AM UTC 24 | 2819547405 ps | ||
T495 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/495.prim_prince_test.1449059604 | Aug 27 01:03:11 AM UTC 24 | Aug 27 01:04:17 AM UTC 24 | 2977328188 ps | ||
T496 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/490.prim_prince_test.681762549 | Aug 27 01:03:00 AM UTC 24 | Aug 27 01:04:17 AM UTC 24 | 3543539087 ps | ||
T497 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/492.prim_prince_test.1815687753 | Aug 27 01:03:07 AM UTC 24 | Aug 27 01:04:20 AM UTC 24 | 3348355644 ps | ||
T498 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/491.prim_prince_test.2026939936 | Aug 27 01:03:07 AM UTC 24 | Aug 27 01:04:24 AM UTC 24 | 3493621060 ps | ||
T499 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/499.prim_prince_test.1781641391 | Aug 27 01:03:22 AM UTC 24 | Aug 27 01:04:28 AM UTC 24 | 2978603088 ps | ||
T500 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/498.prim_prince_test.690426252 | Aug 27 01:03:21 AM UTC 24 | Aug 27 01:04:34 AM UTC 24 | 3297303064 ps |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/0.prim_prince_test.446012424 |
Short name | T1 |
Test name | |
Test status | |
Simulation time | 1100954635 ps |
CPU time | 19.74 seconds |
Started | Aug 27 12:37:36 AM UTC 24 |
Finished | Aug 27 12:38:01 AM UTC 24 |
Peak memory | 154612 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=446012424 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 0.prim_prince_test.446012424 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/0.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/1.prim_prince_test.2962448283 |
Short name | T2 |
Test name | |
Test status | |
Simulation time | 1617609039 ps |
CPU time | 28.06 seconds |
Started | Aug 27 12:37:38 AM UTC 24 |
Finished | Aug 27 12:38:14 AM UTC 24 |
Peak memory | 154600 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2962448283 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 1.prim_prince_test.2962448283 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/1.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/10.prim_prince_test.3689843334 |
Short name | T14 |
Test name | |
Test status | |
Simulation time | 2640491004 ps |
CPU time | 45.47 seconds |
Started | Aug 27 12:38:32 AM UTC 24 |
Finished | Aug 27 12:39:29 AM UTC 24 |
Peak memory | 154664 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3689843334 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 10.prim_prince_test.3689843334 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/10.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/100.prim_prince_test.376133510 |
Short name | T94 |
Test name | |
Test status | |
Simulation time | 1592373407 ps |
CPU time | 27.51 seconds |
Started | Aug 27 12:44:58 AM UTC 24 |
Finished | Aug 27 12:45:35 AM UTC 24 |
Peak memory | 154596 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=376133510 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 100.prim_prince_test.376133510 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/100.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/101.prim_prince_test.3166023476 |
Short name | T108 |
Test name | |
Test status | |
Simulation time | 3159872352 ps |
CPU time | 53.3 seconds |
Started | Aug 27 12:45:00 AM UTC 24 |
Finished | Aug 27 12:46:10 AM UTC 24 |
Peak memory | 154652 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3166023476 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 101.prim_prince_test.3166023476 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/101.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/102.prim_prince_test.2731075038 |
Short name | T101 |
Test name | |
Test status | |
Simulation time | 1948850897 ps |
CPU time | 32.94 seconds |
Started | Aug 27 12:45:05 AM UTC 24 |
Finished | Aug 27 12:45:48 AM UTC 24 |
Peak memory | 154592 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2731075038 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 102.prim_prince_test.2731075038 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/102.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/103.prim_prince_test.2563829726 |
Short name | T110 |
Test name | |
Test status | |
Simulation time | 3279885299 ps |
CPU time | 54.95 seconds |
Started | Aug 27 12:45:06 AM UTC 24 |
Finished | Aug 27 12:46:17 AM UTC 24 |
Peak memory | 154656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2563829726 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 103.prim_prince_test.2563829726 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/103.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/104.prim_prince_test.4136892688 |
Short name | T100 |
Test name | |
Test status | |
Simulation time | 1750305355 ps |
CPU time | 29.52 seconds |
Started | Aug 27 12:45:08 AM UTC 24 |
Finished | Aug 27 12:45:47 AM UTC 24 |
Peak memory | 154592 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4136892688 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 104.prim_prince_test.4136892688 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/104.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/105.prim_prince_test.3822764421 |
Short name | T99 |
Test name | |
Test status | |
Simulation time | 1137126915 ps |
CPU time | 19.67 seconds |
Started | Aug 27 12:45:20 AM UTC 24 |
Finished | Aug 27 12:45:46 AM UTC 24 |
Peak memory | 154592 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3822764421 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 105.prim_prince_test.3822764421 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/105.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/106.prim_prince_test.1987671395 |
Short name | T106 |
Test name | |
Test status | |
Simulation time | 2099464817 ps |
CPU time | 36.02 seconds |
Started | Aug 27 12:45:21 AM UTC 24 |
Finished | Aug 27 12:46:08 AM UTC 24 |
Peak memory | 154588 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1987671395 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 106.prim_prince_test.1987671395 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/106.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/107.prim_prince_test.457361760 |
Short name | T115 |
Test name | |
Test status | |
Simulation time | 2775713768 ps |
CPU time | 47.06 seconds |
Started | Aug 27 12:45:30 AM UTC 24 |
Finished | Aug 27 12:46:31 AM UTC 24 |
Peak memory | 154664 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=457361760 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 107.prim_prince_test.457361760 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/107.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/108.prim_prince_test.1052505315 |
Short name | T103 |
Test name | |
Test status | |
Simulation time | 1478305170 ps |
CPU time | 25.75 seconds |
Started | Aug 27 12:45:30 AM UTC 24 |
Finished | Aug 27 12:46:04 AM UTC 24 |
Peak memory | 154592 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1052505315 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 108.prim_prince_test.1052505315 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/108.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/109.prim_prince_test.1194844374 |
Short name | T111 |
Test name | |
Test status | |
Simulation time | 1895585017 ps |
CPU time | 32.57 seconds |
Started | Aug 27 12:45:35 AM UTC 24 |
Finished | Aug 27 12:46:18 AM UTC 24 |
Peak memory | 154592 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1194844374 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 109.prim_prince_test.1194844374 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/109.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/11.prim_prince_test.2991663687 |
Short name | T7 |
Test name | |
Test status | |
Simulation time | 1385747244 ps |
CPU time | 24.46 seconds |
Started | Aug 27 12:38:35 AM UTC 24 |
Finished | Aug 27 12:39:06 AM UTC 24 |
Peak memory | 154600 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2991663687 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 11.prim_prince_test.2991663687 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/11.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/110.prim_prince_test.1106000389 |
Short name | T113 |
Test name | |
Test status | |
Simulation time | 2324297950 ps |
CPU time | 39.71 seconds |
Started | Aug 27 12:45:36 AM UTC 24 |
Finished | Aug 27 12:46:27 AM UTC 24 |
Peak memory | 154656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1106000389 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 110.prim_prince_test.1106000389 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/110.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/111.prim_prince_test.3483776875 |
Short name | T112 |
Test name | |
Test status | |
Simulation time | 1829841464 ps |
CPU time | 30.44 seconds |
Started | Aug 27 12:45:44 AM UTC 24 |
Finished | Aug 27 12:46:24 AM UTC 24 |
Peak memory | 154592 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3483776875 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 111.prim_prince_test.3483776875 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/111.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/112.prim_prince_test.954683133 |
Short name | T118 |
Test name | |
Test status | |
Simulation time | 2870418305 ps |
CPU time | 48.27 seconds |
Started | Aug 27 12:45:45 AM UTC 24 |
Finished | Aug 27 12:46:47 AM UTC 24 |
Peak memory | 154664 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=954683133 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 112.prim_prince_test.954683133 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/112.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/113.prim_prince_test.827023509 |
Short name | T125 |
Test name | |
Test status | |
Simulation time | 3545911841 ps |
CPU time | 60.24 seconds |
Started | Aug 27 12:45:47 AM UTC 24 |
Finished | Aug 27 12:47:05 AM UTC 24 |
Peak memory | 154664 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=827023509 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 113.prim_prince_test.827023509 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/113.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/114.prim_prince_test.716244117 |
Short name | T109 |
Test name | |
Test status | |
Simulation time | 1123175323 ps |
CPU time | 18.8 seconds |
Started | Aug 27 12:45:47 AM UTC 24 |
Finished | Aug 27 12:46:12 AM UTC 24 |
Peak memory | 154600 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=716244117 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 114.prim_prince_test.716244117 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/114.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/115.prim_prince_test.3597515759 |
Short name | T121 |
Test name | |
Test status | |
Simulation time | 3105256850 ps |
CPU time | 52.72 seconds |
Started | Aug 27 12:45:47 AM UTC 24 |
Finished | Aug 27 12:46:55 AM UTC 24 |
Peak memory | 154656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3597515759 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 115.prim_prince_test.3597515759 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/115.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/116.prim_prince_test.1921557347 |
Short name | T104 |
Test name | |
Test status | |
Simulation time | 756135740 ps |
CPU time | 13.24 seconds |
Started | Aug 27 12:45:48 AM UTC 24 |
Finished | Aug 27 12:46:06 AM UTC 24 |
Peak memory | 154348 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1921557347 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 116.prim_prince_test.1921557347 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/116.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/117.prim_prince_test.1703692149 |
Short name | T117 |
Test name | |
Test status | |
Simulation time | 2228850061 ps |
CPU time | 37.11 seconds |
Started | Aug 27 12:45:56 AM UTC 24 |
Finished | Aug 27 12:46:45 AM UTC 24 |
Peak memory | 154656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1703692149 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 117.prim_prince_test.1703692149 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/117.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/118.prim_prince_test.3104990470 |
Short name | T128 |
Test name | |
Test status | |
Simulation time | 3525654569 ps |
CPU time | 60.14 seconds |
Started | Aug 27 12:46:05 AM UTC 24 |
Finished | Aug 27 12:47:22 AM UTC 24 |
Peak memory | 154656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3104990470 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 118.prim_prince_test.3104990470 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/118.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/119.prim_prince_test.1897861975 |
Short name | T116 |
Test name | |
Test status | |
Simulation time | 1443014217 ps |
CPU time | 24.74 seconds |
Started | Aug 27 12:46:07 AM UTC 24 |
Finished | Aug 27 12:46:39 AM UTC 24 |
Peak memory | 154592 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1897861975 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 119.prim_prince_test.1897861975 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/119.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/12.prim_prince_test.1488585852 |
Short name | T17 |
Test name | |
Test status | |
Simulation time | 2897361442 ps |
CPU time | 50.2 seconds |
Started | Aug 27 12:38:37 AM UTC 24 |
Finished | Aug 27 12:39:40 AM UTC 24 |
Peak memory | 154664 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1488585852 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 12.prim_prince_test.1488585852 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/12.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/120.prim_prince_test.796458532 |
Short name | T114 |
Test name | |
Test status | |
Simulation time | 1010043204 ps |
CPU time | 17.41 seconds |
Started | Aug 27 12:46:08 AM UTC 24 |
Finished | Aug 27 12:46:31 AM UTC 24 |
Peak memory | 154600 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=796458532 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 120.prim_prince_test.796458532 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/120.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/121.prim_prince_test.2164691889 |
Short name | T124 |
Test name | |
Test status | |
Simulation time | 2428019997 ps |
CPU time | 40.86 seconds |
Started | Aug 27 12:46:09 AM UTC 24 |
Finished | Aug 27 12:47:02 AM UTC 24 |
Peak memory | 154656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2164691889 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 121.prim_prince_test.2164691889 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/121.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/122.prim_prince_test.1863105684 |
Short name | T119 |
Test name | |
Test status | |
Simulation time | 1772283252 ps |
CPU time | 29.79 seconds |
Started | Aug 27 12:46:09 AM UTC 24 |
Finished | Aug 27 12:46:48 AM UTC 24 |
Peak memory | 154592 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1863105684 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 122.prim_prince_test.1863105684 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/122.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/123.prim_prince_test.1478433196 |
Short name | T123 |
Test name | |
Test status | |
Simulation time | 2191507050 ps |
CPU time | 37.04 seconds |
Started | Aug 27 12:46:10 AM UTC 24 |
Finished | Aug 27 12:46:59 AM UTC 24 |
Peak memory | 154656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1478433196 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 123.prim_prince_test.1478433196 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/123.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/124.prim_prince_test.3090867949 |
Short name | T130 |
Test name | |
Test status | |
Simulation time | 3548885999 ps |
CPU time | 59.91 seconds |
Started | Aug 27 12:46:13 AM UTC 24 |
Finished | Aug 27 12:47:31 AM UTC 24 |
Peak memory | 154656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3090867949 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 124.prim_prince_test.3090867949 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/124.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/125.prim_prince_test.4201247851 |
Short name | T122 |
Test name | |
Test status | |
Simulation time | 1793532156 ps |
CPU time | 30.49 seconds |
Started | Aug 27 12:46:17 AM UTC 24 |
Finished | Aug 27 12:46:57 AM UTC 24 |
Peak memory | 154592 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4201247851 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 125.prim_prince_test.4201247851 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/125.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/126.prim_prince_test.2123930690 |
Short name | T129 |
Test name | |
Test status | |
Simulation time | 3230109760 ps |
CPU time | 54.92 seconds |
Started | Aug 27 12:46:19 AM UTC 24 |
Finished | Aug 27 12:47:29 AM UTC 24 |
Peak memory | 154656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2123930690 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 126.prim_prince_test.2123930690 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/126.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/127.prim_prince_test.2846991155 |
Short name | T137 |
Test name | |
Test status | |
Simulation time | 3533990437 ps |
CPU time | 60.73 seconds |
Started | Aug 27 12:46:25 AM UTC 24 |
Finished | Aug 27 12:47:43 AM UTC 24 |
Peak memory | 154656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2846991155 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 127.prim_prince_test.2846991155 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/127.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/128.prim_prince_test.2325944563 |
Short name | T133 |
Test name | |
Test status | |
Simulation time | 3169597945 ps |
CPU time | 53.38 seconds |
Started | Aug 27 12:46:28 AM UTC 24 |
Finished | Aug 27 12:47:37 AM UTC 24 |
Peak memory | 154656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2325944563 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 128.prim_prince_test.2325944563 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/128.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/129.prim_prince_test.2309124064 |
Short name | T120 |
Test name | |
Test status | |
Simulation time | 778519614 ps |
CPU time | 13.59 seconds |
Started | Aug 27 12:46:32 AM UTC 24 |
Finished | Aug 27 12:46:50 AM UTC 24 |
Peak memory | 154348 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2309124064 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 129.prim_prince_test.2309124064 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/129.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/13.prim_prince_test.1723221565 |
Short name | T11 |
Test name | |
Test status | |
Simulation time | 910912002 ps |
CPU time | 16.27 seconds |
Started | Aug 27 12:39:00 AM UTC 24 |
Finished | Aug 27 12:39:21 AM UTC 24 |
Peak memory | 154600 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1723221565 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 13.prim_prince_test.1723221565 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/13.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/130.prim_prince_test.2140688424 |
Short name | T126 |
Test name | |
Test status | |
Simulation time | 1955924313 ps |
CPU time | 33.19 seconds |
Started | Aug 27 12:46:32 AM UTC 24 |
Finished | Aug 27 12:47:15 AM UTC 24 |
Peak memory | 154592 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2140688424 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 130.prim_prince_test.2140688424 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/130.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/131.prim_prince_test.1993965830 |
Short name | T132 |
Test name | |
Test status | |
Simulation time | 2371250398 ps |
CPU time | 40.46 seconds |
Started | Aug 27 12:46:40 AM UTC 24 |
Finished | Aug 27 12:47:33 AM UTC 24 |
Peak memory | 154656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1993965830 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 131.prim_prince_test.1993965830 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/131.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/132.prim_prince_test.329248882 |
Short name | T136 |
Test name | |
Test status | |
Simulation time | 2594977083 ps |
CPU time | 43.94 seconds |
Started | Aug 27 12:46:45 AM UTC 24 |
Finished | Aug 27 12:47:42 AM UTC 24 |
Peak memory | 154664 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=329248882 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 132.prim_prince_test.329248882 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/132.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/133.prim_prince_test.4045097539 |
Short name | T127 |
Test name | |
Test status | |
Simulation time | 1302057689 ps |
CPU time | 22.25 seconds |
Started | Aug 27 12:46:49 AM UTC 24 |
Finished | Aug 27 12:47:18 AM UTC 24 |
Peak memory | 154592 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4045097539 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 133.prim_prince_test.4045097539 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/133.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/134.prim_prince_test.2705613044 |
Short name | T139 |
Test name | |
Test status | |
Simulation time | 2820823184 ps |
CPU time | 48.59 seconds |
Started | Aug 27 12:46:49 AM UTC 24 |
Finished | Aug 27 12:47:51 AM UTC 24 |
Peak memory | 154656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2705613044 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 134.prim_prince_test.2705613044 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/134.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/135.prim_prince_test.587165321 |
Short name | T134 |
Test name | |
Test status | |
Simulation time | 2260150520 ps |
CPU time | 38.77 seconds |
Started | Aug 27 12:46:51 AM UTC 24 |
Finished | Aug 27 12:47:41 AM UTC 24 |
Peak memory | 154664 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=587165321 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 135.prim_prince_test.587165321 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/135.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/136.prim_prince_test.2121430366 |
Short name | T131 |
Test name | |
Test status | |
Simulation time | 1645964334 ps |
CPU time | 28.01 seconds |
Started | Aug 27 12:46:56 AM UTC 24 |
Finished | Aug 27 12:47:33 AM UTC 24 |
Peak memory | 154588 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2121430366 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 136.prim_prince_test.2121430366 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/136.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/137.prim_prince_test.1210935084 |
Short name | T141 |
Test name | |
Test status | |
Simulation time | 2795249952 ps |
CPU time | 47.15 seconds |
Started | Aug 27 12:46:58 AM UTC 24 |
Finished | Aug 27 12:47:59 AM UTC 24 |
Peak memory | 154656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1210935084 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 137.prim_prince_test.1210935084 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/137.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/138.prim_prince_test.1685230643 |
Short name | T147 |
Test name | |
Test status | |
Simulation time | 3459732730 ps |
CPU time | 58.66 seconds |
Started | Aug 27 12:46:59 AM UTC 24 |
Finished | Aug 27 12:48:15 AM UTC 24 |
Peak memory | 154656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1685230643 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 138.prim_prince_test.1685230643 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/138.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/139.prim_prince_test.447657192 |
Short name | T145 |
Test name | |
Test status | |
Simulation time | 2984510921 ps |
CPU time | 50.7 seconds |
Started | Aug 27 12:47:03 AM UTC 24 |
Finished | Aug 27 12:48:09 AM UTC 24 |
Peak memory | 154656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=447657192 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 139.prim_prince_test.447657192 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/139.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/14.prim_prince_test.2027844668 |
Short name | T13 |
Test name | |
Test status | |
Simulation time | 775763584 ps |
CPU time | 13.92 seconds |
Started | Aug 27 12:39:07 AM UTC 24 |
Finished | Aug 27 12:39:25 AM UTC 24 |
Peak memory | 154600 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2027844668 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 14.prim_prince_test.2027844668 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/14.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/140.prim_prince_test.4010942197 |
Short name | T142 |
Test name | |
Test status | |
Simulation time | 2603925599 ps |
CPU time | 44.75 seconds |
Started | Aug 27 12:47:06 AM UTC 24 |
Finished | Aug 27 12:48:03 AM UTC 24 |
Peak memory | 154656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4010942197 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 140.prim_prince_test.4010942197 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/140.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/141.prim_prince_test.2736454289 |
Short name | T135 |
Test name | |
Test status | |
Simulation time | 1117333769 ps |
CPU time | 19.26 seconds |
Started | Aug 27 12:47:16 AM UTC 24 |
Finished | Aug 27 12:47:41 AM UTC 24 |
Peak memory | 154592 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2736454289 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 141.prim_prince_test.2736454289 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/141.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/142.prim_prince_test.2490312717 |
Short name | T144 |
Test name | |
Test status | |
Simulation time | 2141618786 ps |
CPU time | 36.87 seconds |
Started | Aug 27 12:47:19 AM UTC 24 |
Finished | Aug 27 12:48:07 AM UTC 24 |
Peak memory | 154592 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2490312717 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 142.prim_prince_test.2490312717 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/142.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/143.prim_prince_test.2497964867 |
Short name | T143 |
Test name | |
Test status | |
Simulation time | 1825560360 ps |
CPU time | 31.1 seconds |
Started | Aug 27 12:47:23 AM UTC 24 |
Finished | Aug 27 12:48:03 AM UTC 24 |
Peak memory | 154592 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2497964867 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 143.prim_prince_test.2497964867 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/143.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/144.prim_prince_test.2753725265 |
Short name | T140 |
Test name | |
Test status | |
Simulation time | 1080542944 ps |
CPU time | 18.86 seconds |
Started | Aug 27 12:47:30 AM UTC 24 |
Finished | Aug 27 12:47:55 AM UTC 24 |
Peak memory | 154592 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2753725265 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 144.prim_prince_test.2753725265 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/144.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/145.prim_prince_test.1708454117 |
Short name | T155 |
Test name | |
Test status | |
Simulation time | 3543308038 ps |
CPU time | 60.06 seconds |
Started | Aug 27 12:47:31 AM UTC 24 |
Finished | Aug 27 12:48:49 AM UTC 24 |
Peak memory | 154656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1708454117 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 145.prim_prince_test.1708454117 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/145.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/146.prim_prince_test.1284383942 |
Short name | T152 |
Test name | |
Test status | |
Simulation time | 3040308466 ps |
CPU time | 51.25 seconds |
Started | Aug 27 12:47:34 AM UTC 24 |
Finished | Aug 27 12:48:40 AM UTC 24 |
Peak memory | 154656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1284383942 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 146.prim_prince_test.1284383942 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/146.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/147.prim_prince_test.3592154569 |
Short name | T138 |
Test name | |
Test status | |
Simulation time | 768408163 ps |
CPU time | 13.25 seconds |
Started | Aug 27 12:47:34 AM UTC 24 |
Finished | Aug 27 12:47:51 AM UTC 24 |
Peak memory | 154592 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3592154569 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 147.prim_prince_test.3592154569 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/147.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/148.prim_prince_test.3267247910 |
Short name | T146 |
Test name | |
Test status | |
Simulation time | 1513728412 ps |
CPU time | 26.07 seconds |
Started | Aug 27 12:47:38 AM UTC 24 |
Finished | Aug 27 12:48:12 AM UTC 24 |
Peak memory | 154588 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3267247910 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 148.prim_prince_test.3267247910 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/148.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/149.prim_prince_test.2264793329 |
Short name | T158 |
Test name | |
Test status | |
Simulation time | 3462867238 ps |
CPU time | 58.98 seconds |
Started | Aug 27 12:47:42 AM UTC 24 |
Finished | Aug 27 12:48:58 AM UTC 24 |
Peak memory | 154656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2264793329 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 149.prim_prince_test.2264793329 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/149.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/15.prim_prince_test.2026199773 |
Short name | T16 |
Test name | |
Test status | |
Simulation time | 990269093 ps |
CPU time | 17.33 seconds |
Started | Aug 27 12:39:13 AM UTC 24 |
Finished | Aug 27 12:39:36 AM UTC 24 |
Peak memory | 154600 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2026199773 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 15.prim_prince_test.2026199773 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/15.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/150.prim_prince_test.1377355052 |
Short name | T148 |
Test name | |
Test status | |
Simulation time | 1903399339 ps |
CPU time | 32.81 seconds |
Started | Aug 27 12:47:42 AM UTC 24 |
Finished | Aug 27 12:48:25 AM UTC 24 |
Peak memory | 154592 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1377355052 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 150.prim_prince_test.1377355052 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/150.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/151.prim_prince_test.3940172581 |
Short name | T156 |
Test name | |
Test status | |
Simulation time | 3044047631 ps |
CPU time | 51.64 seconds |
Started | Aug 27 12:47:43 AM UTC 24 |
Finished | Aug 27 12:48:50 AM UTC 24 |
Peak memory | 154656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3940172581 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 151.prim_prince_test.3940172581 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/151.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/152.prim_prince_test.3619786533 |
Short name | T153 |
Test name | |
Test status | |
Simulation time | 2721848874 ps |
CPU time | 46.62 seconds |
Started | Aug 27 12:47:44 AM UTC 24 |
Finished | Aug 27 12:48:45 AM UTC 24 |
Peak memory | 154656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3619786533 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 152.prim_prince_test.3619786533 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/152.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/153.prim_prince_test.94026627 |
Short name | T149 |
Test name | |
Test status | |
Simulation time | 1715774697 ps |
CPU time | 29.33 seconds |
Started | Aug 27 12:47:53 AM UTC 24 |
Finished | Aug 27 12:48:31 AM UTC 24 |
Peak memory | 154600 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=94026627 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 153.prim_prince_test.94026627 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/153.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/154.prim_prince_test.183079034 |
Short name | T154 |
Test name | |
Test status | |
Simulation time | 2370369656 ps |
CPU time | 40.68 seconds |
Started | Aug 27 12:47:53 AM UTC 24 |
Finished | Aug 27 12:48:45 AM UTC 24 |
Peak memory | 154664 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=183079034 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 154.prim_prince_test.183079034 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/154.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/155.prim_prince_test.2977449931 |
Short name | T150 |
Test name | |
Test status | |
Simulation time | 1716007824 ps |
CPU time | 29.33 seconds |
Started | Aug 27 12:47:56 AM UTC 24 |
Finished | Aug 27 12:48:34 AM UTC 24 |
Peak memory | 154592 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2977449931 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 155.prim_prince_test.2977449931 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/155.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/156.prim_prince_test.474452518 |
Short name | T168 |
Test name | |
Test status | |
Simulation time | 3694374623 ps |
CPU time | 62.52 seconds |
Started | Aug 27 12:48:00 AM UTC 24 |
Finished | Aug 27 12:49:21 AM UTC 24 |
Peak memory | 156184 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=474452518 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 156.prim_prince_test.474452518 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/156.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/157.prim_prince_test.1918047285 |
Short name | T164 |
Test name | |
Test status | |
Simulation time | 3371111980 ps |
CPU time | 57.45 seconds |
Started | Aug 27 12:48:01 AM UTC 24 |
Finished | Aug 27 12:49:15 AM UTC 24 |
Peak memory | 154656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1918047285 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 157.prim_prince_test.1918047285 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/157.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/158.prim_prince_test.2987827723 |
Short name | T151 |
Test name | |
Test status | |
Simulation time | 1507710674 ps |
CPU time | 25.94 seconds |
Started | Aug 27 12:48:04 AM UTC 24 |
Finished | Aug 27 12:48:38 AM UTC 24 |
Peak memory | 154592 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2987827723 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 158.prim_prince_test.2987827723 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/158.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/159.prim_prince_test.4173721977 |
Short name | T169 |
Test name | |
Test status | |
Simulation time | 3578395100 ps |
CPU time | 60.31 seconds |
Started | Aug 27 12:48:04 AM UTC 24 |
Finished | Aug 27 12:49:22 AM UTC 24 |
Peak memory | 154656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4173721977 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 159.prim_prince_test.4173721977 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/159.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/16.prim_prince_test.695516180 |
Short name | T18 |
Test name | |
Test status | |
Simulation time | 1193954171 ps |
CPU time | 20.84 seconds |
Started | Aug 27 12:39:15 AM UTC 24 |
Finished | Aug 27 12:39:42 AM UTC 24 |
Peak memory | 154600 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=695516180 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 16.prim_prince_test.695516180 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/16.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/160.prim_prince_test.1898518337 |
Short name | T163 |
Test name | |
Test status | |
Simulation time | 3066305024 ps |
CPU time | 51.9 seconds |
Started | Aug 27 12:48:08 AM UTC 24 |
Finished | Aug 27 12:49:15 AM UTC 24 |
Peak memory | 154656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1898518337 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 160.prim_prince_test.1898518337 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/160.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/161.prim_prince_test.2075531534 |
Short name | T161 |
Test name | |
Test status | |
Simulation time | 2575415266 ps |
CPU time | 44.51 seconds |
Started | Aug 27 12:48:10 AM UTC 24 |
Finished | Aug 27 12:49:08 AM UTC 24 |
Peak memory | 154656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2075531534 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 161.prim_prince_test.2075531534 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/161.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/162.prim_prince_test.1842717940 |
Short name | T166 |
Test name | |
Test status | |
Simulation time | 2957606439 ps |
CPU time | 50.08 seconds |
Started | Aug 27 12:48:13 AM UTC 24 |
Finished | Aug 27 12:49:18 AM UTC 24 |
Peak memory | 154656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1842717940 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 162.prim_prince_test.1842717940 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/162.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/163.prim_prince_test.3982274477 |
Short name | T159 |
Test name | |
Test status | |
Simulation time | 1946474310 ps |
CPU time | 33.1 seconds |
Started | Aug 27 12:48:16 AM UTC 24 |
Finished | Aug 27 12:49:00 AM UTC 24 |
Peak memory | 154580 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3982274477 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 163.prim_prince_test.3982274477 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/163.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/164.prim_prince_test.1965846769 |
Short name | T162 |
Test name | |
Test status | |
Simulation time | 2044432194 ps |
CPU time | 34.6 seconds |
Started | Aug 27 12:48:25 AM UTC 24 |
Finished | Aug 27 12:49:10 AM UTC 24 |
Peak memory | 154592 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1965846769 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 164.prim_prince_test.1965846769 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/164.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/165.prim_prince_test.3673567245 |
Short name | T160 |
Test name | |
Test status | |
Simulation time | 1261495535 ps |
CPU time | 21.78 seconds |
Started | Aug 27 12:48:31 AM UTC 24 |
Finished | Aug 27 12:49:00 AM UTC 24 |
Peak memory | 154592 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3673567245 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 165.prim_prince_test.3673567245 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/165.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/166.prim_prince_test.2772439098 |
Short name | T174 |
Test name | |
Test status | |
Simulation time | 3602673908 ps |
CPU time | 61.14 seconds |
Started | Aug 27 12:48:35 AM UTC 24 |
Finished | Aug 27 12:49:53 AM UTC 24 |
Peak memory | 154656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2772439098 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 166.prim_prince_test.2772439098 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/166.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/167.prim_prince_test.2442124656 |
Short name | T157 |
Test name | |
Test status | |
Simulation time | 790620031 ps |
CPU time | 13.77 seconds |
Started | Aug 27 12:48:39 AM UTC 24 |
Finished | Aug 27 12:48:57 AM UTC 24 |
Peak memory | 154588 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2442124656 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 167.prim_prince_test.2442124656 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/167.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/168.prim_prince_test.3850889538 |
Short name | T167 |
Test name | |
Test status | |
Simulation time | 1713944741 ps |
CPU time | 28.99 seconds |
Started | Aug 27 12:48:41 AM UTC 24 |
Finished | Aug 27 12:49:19 AM UTC 24 |
Peak memory | 154592 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3850889538 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 168.prim_prince_test.3850889538 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/168.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/169.prim_prince_test.2289589551 |
Short name | T165 |
Test name | |
Test status | |
Simulation time | 1366997487 ps |
CPU time | 23.15 seconds |
Started | Aug 27 12:48:45 AM UTC 24 |
Finished | Aug 27 12:49:16 AM UTC 24 |
Peak memory | 154592 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2289589551 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 169.prim_prince_test.2289589551 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/169.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/17.prim_prince_test.821931083 |
Short name | T23 |
Test name | |
Test status | |
Simulation time | 3226817419 ps |
CPU time | 55.55 seconds |
Started | Aug 27 12:39:16 AM UTC 24 |
Finished | Aug 27 12:40:27 AM UTC 24 |
Peak memory | 154664 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=821931083 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 17.prim_prince_test.821931083 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/17.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/170.prim_prince_test.1584737848 |
Short name | T175 |
Test name | |
Test status | |
Simulation time | 3081825450 ps |
CPU time | 52.16 seconds |
Started | Aug 27 12:48:46 AM UTC 24 |
Finished | Aug 27 12:49:54 AM UTC 24 |
Peak memory | 154656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1584737848 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 170.prim_prince_test.1584737848 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/170.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/171.prim_prince_test.4116801901 |
Short name | T170 |
Test name | |
Test status | |
Simulation time | 2036152680 ps |
CPU time | 34.9 seconds |
Started | Aug 27 12:48:49 AM UTC 24 |
Finished | Aug 27 12:49:35 AM UTC 24 |
Peak memory | 154592 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4116801901 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 171.prim_prince_test.4116801901 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/171.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/172.prim_prince_test.2997989731 |
Short name | T180 |
Test name | |
Test status | |
Simulation time | 3369548035 ps |
CPU time | 57.3 seconds |
Started | Aug 27 12:48:51 AM UTC 24 |
Finished | Aug 27 12:50:05 AM UTC 24 |
Peak memory | 154648 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2997989731 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 172.prim_prince_test.2997989731 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/172.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/173.prim_prince_test.3548652710 |
Short name | T173 |
Test name | |
Test status | |
Simulation time | 2339431778 ps |
CPU time | 39.86 seconds |
Started | Aug 27 12:48:58 AM UTC 24 |
Finished | Aug 27 12:49:49 AM UTC 24 |
Peak memory | 154652 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3548652710 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 173.prim_prince_test.3548652710 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/173.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/174.prim_prince_test.3265065572 |
Short name | T177 |
Test name | |
Test status | |
Simulation time | 2940890136 ps |
CPU time | 49.8 seconds |
Started | Aug 27 12:48:59 AM UTC 24 |
Finished | Aug 27 12:50:03 AM UTC 24 |
Peak memory | 154656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3265065572 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 174.prim_prince_test.3265065572 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/174.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/175.prim_prince_test.248837425 |
Short name | T184 |
Test name | |
Test status | |
Simulation time | 3608607754 ps |
CPU time | 60.45 seconds |
Started | Aug 27 12:49:00 AM UTC 24 |
Finished | Aug 27 12:50:18 AM UTC 24 |
Peak memory | 154664 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=248837425 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 175.prim_prince_test.248837425 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/175.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/176.prim_prince_test.705901166 |
Short name | T171 |
Test name | |
Test status | |
Simulation time | 1897515257 ps |
CPU time | 32.44 seconds |
Started | Aug 27 12:49:01 AM UTC 24 |
Finished | Aug 27 12:49:44 AM UTC 24 |
Peak memory | 154600 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=705901166 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 176.prim_prince_test.705901166 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/176.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/177.prim_prince_test.866635190 |
Short name | T176 |
Test name | |
Test status | |
Simulation time | 2180100411 ps |
CPU time | 37.1 seconds |
Started | Aug 27 12:49:09 AM UTC 24 |
Finished | Aug 27 12:49:57 AM UTC 24 |
Peak memory | 154664 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=866635190 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 177.prim_prince_test.866635190 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/177.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/178.prim_prince_test.3344059933 |
Short name | T181 |
Test name | |
Test status | |
Simulation time | 2767599759 ps |
CPU time | 46.57 seconds |
Started | Aug 27 12:49:11 AM UTC 24 |
Finished | Aug 27 12:50:11 AM UTC 24 |
Peak memory | 154656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3344059933 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 178.prim_prince_test.3344059933 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/178.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/179.prim_prince_test.1375338516 |
Short name | T188 |
Test name | |
Test status | |
Simulation time | 3287366332 ps |
CPU time | 55.47 seconds |
Started | Aug 27 12:49:16 AM UTC 24 |
Finished | Aug 27 12:50:28 AM UTC 24 |
Peak memory | 154652 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1375338516 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 179.prim_prince_test.1375338516 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/179.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/18.prim_prince_test.3812139666 |
Short name | T25 |
Test name | |
Test status | |
Simulation time | 3162054185 ps |
CPU time | 54.58 seconds |
Started | Aug 27 12:39:22 AM UTC 24 |
Finished | Aug 27 12:40:32 AM UTC 24 |
Peak memory | 154660 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3812139666 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 18.prim_prince_test.3812139666 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/18.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/180.prim_prince_test.639499882 |
Short name | T189 |
Test name | |
Test status | |
Simulation time | 3367542464 ps |
CPU time | 56.67 seconds |
Started | Aug 27 12:49:16 AM UTC 24 |
Finished | Aug 27 12:50:29 AM UTC 24 |
Peak memory | 154664 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=639499882 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 180.prim_prince_test.639499882 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/180.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/181.prim_prince_test.3751176673 |
Short name | T183 |
Test name | |
Test status | |
Simulation time | 2739506639 ps |
CPU time | 46.06 seconds |
Started | Aug 27 12:49:16 AM UTC 24 |
Finished | Aug 27 12:50:16 AM UTC 24 |
Peak memory | 154656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3751176673 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 181.prim_prince_test.3751176673 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/181.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/182.prim_prince_test.3640955907 |
Short name | T178 |
Test name | |
Test status | |
Simulation time | 2071787203 ps |
CPU time | 35.01 seconds |
Started | Aug 27 12:49:18 AM UTC 24 |
Finished | Aug 27 12:50:04 AM UTC 24 |
Peak memory | 154592 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3640955907 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 182.prim_prince_test.3640955907 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/182.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/183.prim_prince_test.3861275298 |
Short name | T193 |
Test name | |
Test status | |
Simulation time | 3695467653 ps |
CPU time | 61.89 seconds |
Started | Aug 27 12:49:20 AM UTC 24 |
Finished | Aug 27 12:50:39 AM UTC 24 |
Peak memory | 154656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3861275298 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 183.prim_prince_test.3861275298 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/183.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/184.prim_prince_test.2562222969 |
Short name | T172 |
Test name | |
Test status | |
Simulation time | 1003280290 ps |
CPU time | 17.17 seconds |
Started | Aug 27 12:49:22 AM UTC 24 |
Finished | Aug 27 12:49:45 AM UTC 24 |
Peak memory | 154348 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2562222969 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 184.prim_prince_test.2562222969 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/184.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/185.prim_prince_test.813911507 |
Short name | T179 |
Test name | |
Test status | |
Simulation time | 1848457121 ps |
CPU time | 31.45 seconds |
Started | Aug 27 12:49:23 AM UTC 24 |
Finished | Aug 27 12:50:04 AM UTC 24 |
Peak memory | 154600 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=813911507 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 185.prim_prince_test.813911507 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/185.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/186.prim_prince_test.16664883 |
Short name | T186 |
Test name | |
Test status | |
Simulation time | 2238296510 ps |
CPU time | 37.55 seconds |
Started | Aug 27 12:49:36 AM UTC 24 |
Finished | Aug 27 12:50:25 AM UTC 24 |
Peak memory | 154664 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16664883 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 186.prim_prince_test.16664883 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/186.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/187.prim_prince_test.2635893834 |
Short name | T182 |
Test name | |
Test status | |
Simulation time | 1333991176 ps |
CPU time | 22.77 seconds |
Started | Aug 27 12:49:44 AM UTC 24 |
Finished | Aug 27 12:50:14 AM UTC 24 |
Peak memory | 154592 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2635893834 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 187.prim_prince_test.2635893834 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/187.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/188.prim_prince_test.316291003 |
Short name | T185 |
Test name | |
Test status | |
Simulation time | 1558089253 ps |
CPU time | 26.55 seconds |
Started | Aug 27 12:49:46 AM UTC 24 |
Finished | Aug 27 12:50:20 AM UTC 24 |
Peak memory | 154600 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=316291003 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 188.prim_prince_test.316291003 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/188.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/189.prim_prince_test.131291316 |
Short name | T197 |
Test name | |
Test status | |
Simulation time | 2813356811 ps |
CPU time | 47.36 seconds |
Started | Aug 27 12:49:51 AM UTC 24 |
Finished | Aug 27 12:50:52 AM UTC 24 |
Peak memory | 154664 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=131291316 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 189.prim_prince_test.131291316 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/189.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/19.prim_prince_test.2248848720 |
Short name | T24 |
Test name | |
Test status | |
Simulation time | 3022137048 ps |
CPU time | 51.46 seconds |
Started | Aug 27 12:39:25 AM UTC 24 |
Finished | Aug 27 12:40:31 AM UTC 24 |
Peak memory | 154664 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2248848720 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 19.prim_prince_test.2248848720 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/19.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/190.prim_prince_test.3343269437 |
Short name | T194 |
Test name | |
Test status | |
Simulation time | 2153789709 ps |
CPU time | 36.74 seconds |
Started | Aug 27 12:49:54 AM UTC 24 |
Finished | Aug 27 12:50:42 AM UTC 24 |
Peak memory | 154656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3343269437 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 190.prim_prince_test.3343269437 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/190.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/191.prim_prince_test.3275766349 |
Short name | T187 |
Test name | |
Test status | |
Simulation time | 1436002733 ps |
CPU time | 24.48 seconds |
Started | Aug 27 12:49:54 AM UTC 24 |
Finished | Aug 27 12:50:26 AM UTC 24 |
Peak memory | 154592 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3275766349 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 191.prim_prince_test.3275766349 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/191.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/192.prim_prince_test.1933403901 |
Short name | T190 |
Test name | |
Test status | |
Simulation time | 1538497459 ps |
CPU time | 25.92 seconds |
Started | Aug 27 12:49:57 AM UTC 24 |
Finished | Aug 27 12:50:32 AM UTC 24 |
Peak memory | 154592 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1933403901 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 192.prim_prince_test.1933403901 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/192.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/193.prim_prince_test.2377967528 |
Short name | T191 |
Test name | |
Test status | |
Simulation time | 1234482234 ps |
CPU time | 21.25 seconds |
Started | Aug 27 12:50:05 AM UTC 24 |
Finished | Aug 27 12:50:33 AM UTC 24 |
Peak memory | 154592 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2377967528 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 193.prim_prince_test.2377967528 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/193.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/194.prim_prince_test.23848398 |
Short name | T205 |
Test name | |
Test status | |
Simulation time | 3240574815 ps |
CPU time | 54.52 seconds |
Started | Aug 27 12:50:05 AM UTC 24 |
Finished | Aug 27 12:51:15 AM UTC 24 |
Peak memory | 154664 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23848398 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 194.prim_prince_test.23848398 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/194.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/195.prim_prince_test.3722153867 |
Short name | T195 |
Test name | |
Test status | |
Simulation time | 1820897383 ps |
CPU time | 30.74 seconds |
Started | Aug 27 12:50:05 AM UTC 24 |
Finished | Aug 27 12:50:45 AM UTC 24 |
Peak memory | 154592 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3722153867 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 195.prim_prince_test.3722153867 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/195.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/196.prim_prince_test.879614249 |
Short name | T208 |
Test name | |
Test status | |
Simulation time | 3645575576 ps |
CPU time | 61.48 seconds |
Started | Aug 27 12:50:06 AM UTC 24 |
Finished | Aug 27 12:51:26 AM UTC 24 |
Peak memory | 154664 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=879614249 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 196.prim_prince_test.879614249 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/196.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/197.prim_prince_test.3434842466 |
Short name | T198 |
Test name | |
Test status | |
Simulation time | 2093868260 ps |
CPU time | 35.29 seconds |
Started | Aug 27 12:50:12 AM UTC 24 |
Finished | Aug 27 12:50:58 AM UTC 24 |
Peak memory | 154592 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3434842466 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 197.prim_prince_test.3434842466 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/197.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/198.prim_prince_test.2220013944 |
Short name | T211 |
Test name | |
Test status | |
Simulation time | 3548421523 ps |
CPU time | 59.73 seconds |
Started | Aug 27 12:50:15 AM UTC 24 |
Finished | Aug 27 12:51:33 AM UTC 24 |
Peak memory | 154656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2220013944 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 198.prim_prince_test.2220013944 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/198.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/199.prim_prince_test.1513834672 |
Short name | T196 |
Test name | |
Test status | |
Simulation time | 1265158106 ps |
CPU time | 21.65 seconds |
Started | Aug 27 12:50:17 AM UTC 24 |
Finished | Aug 27 12:50:45 AM UTC 24 |
Peak memory | 154592 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1513834672 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 199.prim_prince_test.1513834672 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/199.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/2.prim_prince_test.1242706132 |
Short name | T4 |
Test name | |
Test status | |
Simulation time | 2128079577 ps |
CPU time | 37.5 seconds |
Started | Aug 27 12:37:42 AM UTC 24 |
Finished | Aug 27 12:38:29 AM UTC 24 |
Peak memory | 154600 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1242706132 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 2.prim_prince_test.1242706132 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/2.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/20.prim_prince_test.2153019624 |
Short name | T20 |
Test name | |
Test status | |
Simulation time | 1685298148 ps |
CPU time | 29.08 seconds |
Started | Aug 27 12:39:26 AM UTC 24 |
Finished | Aug 27 12:40:04 AM UTC 24 |
Peak memory | 154600 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2153019624 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 20.prim_prince_test.2153019624 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/20.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/200.prim_prince_test.3282421643 |
Short name | T192 |
Test name | |
Test status | |
Simulation time | 873238549 ps |
CPU time | 14.94 seconds |
Started | Aug 27 12:50:19 AM UTC 24 |
Finished | Aug 27 12:50:39 AM UTC 24 |
Peak memory | 154348 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3282421643 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 200.prim_prince_test.3282421643 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/200.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/201.prim_prince_test.3465998918 |
Short name | T213 |
Test name | |
Test status | |
Simulation time | 3463065030 ps |
CPU time | 58.45 seconds |
Started | Aug 27 12:50:21 AM UTC 24 |
Finished | Aug 27 12:51:36 AM UTC 24 |
Peak memory | 154656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3465998918 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 201.prim_prince_test.3465998918 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/201.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/202.prim_prince_test.2315458151 |
Short name | T206 |
Test name | |
Test status | |
Simulation time | 2495068792 ps |
CPU time | 42.34 seconds |
Started | Aug 27 12:50:26 AM UTC 24 |
Finished | Aug 27 12:51:21 AM UTC 24 |
Peak memory | 154656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2315458151 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 202.prim_prince_test.2315458151 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/202.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/203.prim_prince_test.3427012354 |
Short name | T201 |
Test name | |
Test status | |
Simulation time | 1638867611 ps |
CPU time | 27.9 seconds |
Started | Aug 27 12:50:27 AM UTC 24 |
Finished | Aug 27 12:51:04 AM UTC 24 |
Peak memory | 154592 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3427012354 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 203.prim_prince_test.3427012354 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/203.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/204.prim_prince_test.3136748338 |
Short name | T199 |
Test name | |
Test status | |
Simulation time | 1368112191 ps |
CPU time | 23.12 seconds |
Started | Aug 27 12:50:29 AM UTC 24 |
Finished | Aug 27 12:50:59 AM UTC 24 |
Peak memory | 154592 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3136748338 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 204.prim_prince_test.3136748338 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/204.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/205.prim_prince_test.1893135515 |
Short name | T200 |
Test name | |
Test status | |
Simulation time | 1344457673 ps |
CPU time | 22.81 seconds |
Started | Aug 27 12:50:31 AM UTC 24 |
Finished | Aug 27 12:51:01 AM UTC 24 |
Peak memory | 154596 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1893135515 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 205.prim_prince_test.1893135515 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/205.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/206.prim_prince_test.3332451030 |
Short name | T203 |
Test name | |
Test status | |
Simulation time | 1578763640 ps |
CPU time | 26.68 seconds |
Started | Aug 27 12:50:32 AM UTC 24 |
Finished | Aug 27 12:51:07 AM UTC 24 |
Peak memory | 154592 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3332451030 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 206.prim_prince_test.3332451030 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/206.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/207.prim_prince_test.2918469460 |
Short name | T204 |
Test name | |
Test status | |
Simulation time | 1614377255 ps |
CPU time | 27.27 seconds |
Started | Aug 27 12:50:33 AM UTC 24 |
Finished | Aug 27 12:51:09 AM UTC 24 |
Peak memory | 154592 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2918469460 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 207.prim_prince_test.2918469460 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/207.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/208.prim_prince_test.2508253053 |
Short name | T202 |
Test name | |
Test status | |
Simulation time | 1179569115 ps |
CPU time | 20.33 seconds |
Started | Aug 27 12:50:39 AM UTC 24 |
Finished | Aug 27 12:51:06 AM UTC 24 |
Peak memory | 154592 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2508253053 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 208.prim_prince_test.2508253053 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/208.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/209.prim_prince_test.1605849942 |
Short name | T212 |
Test name | |
Test status | |
Simulation time | 2447501198 ps |
CPU time | 40.9 seconds |
Started | Aug 27 12:50:41 AM UTC 24 |
Finished | Aug 27 12:51:34 AM UTC 24 |
Peak memory | 154664 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1605849942 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 209.prim_prince_test.1605849942 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/209.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/21.prim_prince_test.2619273673 |
Short name | T19 |
Test name | |
Test status | |
Simulation time | 1612504357 ps |
CPU time | 27.6 seconds |
Started | Aug 27 12:39:27 AM UTC 24 |
Finished | Aug 27 12:40:03 AM UTC 24 |
Peak memory | 154596 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2619273673 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 21.prim_prince_test.2619273673 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/21.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/210.prim_prince_test.282265142 |
Short name | T215 |
Test name | |
Test status | |
Simulation time | 2596019680 ps |
CPU time | 44 seconds |
Started | Aug 27 12:50:43 AM UTC 24 |
Finished | Aug 27 12:51:40 AM UTC 24 |
Peak memory | 154656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=282265142 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 210.prim_prince_test.282265142 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/210.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/211.prim_prince_test.770203416 |
Short name | T222 |
Test name | |
Test status | |
Simulation time | 3541561903 ps |
CPU time | 59.53 seconds |
Started | Aug 27 12:50:46 AM UTC 24 |
Finished | Aug 27 12:52:03 AM UTC 24 |
Peak memory | 154664 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=770203416 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 211.prim_prince_test.770203416 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/211.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/212.prim_prince_test.3421121539 |
Short name | T207 |
Test name | |
Test status | |
Simulation time | 1599706873 ps |
CPU time | 27.33 seconds |
Started | Aug 27 12:50:46 AM UTC 24 |
Finished | Aug 27 12:51:22 AM UTC 24 |
Peak memory | 154600 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3421121539 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 212.prim_prince_test.3421121539 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/212.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/213.prim_prince_test.3223758903 |
Short name | T210 |
Test name | |
Test status | |
Simulation time | 1553874660 ps |
CPU time | 26.64 seconds |
Started | Aug 27 12:50:53 AM UTC 24 |
Finished | Aug 27 12:51:28 AM UTC 24 |
Peak memory | 154608 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3223758903 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 213.prim_prince_test.3223758903 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/213.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/214.prim_prince_test.12261395 |
Short name | T216 |
Test name | |
Test status | |
Simulation time | 2054596258 ps |
CPU time | 34.4 seconds |
Started | Aug 27 12:51:00 AM UTC 24 |
Finished | Aug 27 12:51:45 AM UTC 24 |
Peak memory | 154608 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=12261395 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 214.prim_prince_test.12261395 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/214.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/215.prim_prince_test.3833139410 |
Short name | T218 |
Test name | |
Test status | |
Simulation time | 2222974308 ps |
CPU time | 37.59 seconds |
Started | Aug 27 12:51:00 AM UTC 24 |
Finished | Aug 27 12:51:49 AM UTC 24 |
Peak memory | 154664 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3833139410 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 215.prim_prince_test.3833139410 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/215.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/216.prim_prince_test.3129908665 |
Short name | T209 |
Test name | |
Test status | |
Simulation time | 1106042534 ps |
CPU time | 18.84 seconds |
Started | Aug 27 12:51:02 AM UTC 24 |
Finished | Aug 27 12:51:27 AM UTC 24 |
Peak memory | 154600 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3129908665 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 216.prim_prince_test.3129908665 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/216.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/217.prim_prince_test.410923749 |
Short name | T217 |
Test name | |
Test status | |
Simulation time | 1908255952 ps |
CPU time | 32.37 seconds |
Started | Aug 27 12:51:04 AM UTC 24 |
Finished | Aug 27 12:51:47 AM UTC 24 |
Peak memory | 154600 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=410923749 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 217.prim_prince_test.410923749 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/217.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/218.prim_prince_test.3254289330 |
Short name | T232 |
Test name | |
Test status | |
Simulation time | 3399458689 ps |
CPU time | 56.92 seconds |
Started | Aug 27 12:51:08 AM UTC 24 |
Finished | Aug 27 12:52:21 AM UTC 24 |
Peak memory | 154664 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3254289330 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 218.prim_prince_test.3254289330 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/218.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/219.prim_prince_test.1283993240 |
Short name | T214 |
Test name | |
Test status | |
Simulation time | 1337705285 ps |
CPU time | 22.89 seconds |
Started | Aug 27 12:51:08 AM UTC 24 |
Finished | Aug 27 12:51:38 AM UTC 24 |
Peak memory | 154600 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1283993240 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 219.prim_prince_test.1283993240 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/219.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/22.prim_prince_test.3560069336 |
Short name | T22 |
Test name | |
Test status | |
Simulation time | 1925876708 ps |
CPU time | 33.5 seconds |
Started | Aug 27 12:39:30 AM UTC 24 |
Finished | Aug 27 12:40:14 AM UTC 24 |
Peak memory | 154488 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3560069336 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 22.prim_prince_test.3560069336 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/22.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/220.prim_prince_test.2890139776 |
Short name | T226 |
Test name | |
Test status | |
Simulation time | 2672840625 ps |
CPU time | 45.44 seconds |
Started | Aug 27 12:51:10 AM UTC 24 |
Finished | Aug 27 12:52:09 AM UTC 24 |
Peak memory | 154664 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2890139776 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 220.prim_prince_test.2890139776 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/220.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/221.prim_prince_test.1494839101 |
Short name | T219 |
Test name | |
Test status | |
Simulation time | 1504451699 ps |
CPU time | 25.62 seconds |
Started | Aug 27 12:51:16 AM UTC 24 |
Finished | Aug 27 12:51:50 AM UTC 24 |
Peak memory | 154600 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1494839101 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 221.prim_prince_test.1494839101 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/221.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/222.prim_prince_test.4227499829 |
Short name | T233 |
Test name | |
Test status | |
Simulation time | 2779891442 ps |
CPU time | 46.5 seconds |
Started | Aug 27 12:51:22 AM UTC 24 |
Finished | Aug 27 12:52:23 AM UTC 24 |
Peak memory | 154672 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4227499829 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 222.prim_prince_test.4227499829 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/222.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/223.prim_prince_test.1802823341 |
Short name | T225 |
Test name | |
Test status | |
Simulation time | 2052955109 ps |
CPU time | 34.59 seconds |
Started | Aug 27 12:51:22 AM UTC 24 |
Finished | Aug 27 12:52:07 AM UTC 24 |
Peak memory | 154600 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1802823341 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 223.prim_prince_test.1802823341 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/223.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/224.prim_prince_test.1491389287 |
Short name | T227 |
Test name | |
Test status | |
Simulation time | 2131927565 ps |
CPU time | 36.07 seconds |
Started | Aug 27 12:51:27 AM UTC 24 |
Finished | Aug 27 12:52:14 AM UTC 24 |
Peak memory | 154584 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1491389287 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 224.prim_prince_test.1491389287 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/224.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/225.prim_prince_test.1894660455 |
Short name | T221 |
Test name | |
Test status | |
Simulation time | 1355877063 ps |
CPU time | 23.26 seconds |
Started | Aug 27 12:51:28 AM UTC 24 |
Finished | Aug 27 12:51:59 AM UTC 24 |
Peak memory | 154600 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1894660455 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 225.prim_prince_test.1894660455 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/225.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/226.prim_prince_test.2242853734 |
Short name | T230 |
Test name | |
Test status | |
Simulation time | 2217384035 ps |
CPU time | 37.65 seconds |
Started | Aug 27 12:51:29 AM UTC 24 |
Finished | Aug 27 12:52:18 AM UTC 24 |
Peak memory | 154660 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2242853734 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 226.prim_prince_test.2242853734 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/226.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/227.prim_prince_test.3042741590 |
Short name | T220 |
Test name | |
Test status | |
Simulation time | 1006955936 ps |
CPU time | 17.33 seconds |
Started | Aug 27 12:51:33 AM UTC 24 |
Finished | Aug 27 12:51:56 AM UTC 24 |
Peak memory | 154600 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3042741590 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 227.prim_prince_test.3042741590 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/227.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/228.prim_prince_test.3265787958 |
Short name | T223 |
Test name | |
Test status | |
Simulation time | 1310672506 ps |
CPU time | 22.02 seconds |
Started | Aug 27 12:51:35 AM UTC 24 |
Finished | Aug 27 12:52:04 AM UTC 24 |
Peak memory | 154600 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3265787958 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 228.prim_prince_test.3265787958 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/228.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/229.prim_prince_test.3583627412 |
Short name | T242 |
Test name | |
Test status | |
Simulation time | 3380102730 ps |
CPU time | 56.76 seconds |
Started | Aug 27 12:51:38 AM UTC 24 |
Finished | Aug 27 12:52:51 AM UTC 24 |
Peak memory | 154660 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3583627412 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 229.prim_prince_test.3583627412 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/229.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/23.prim_prince_test.2616567119 |
Short name | T29 |
Test name | |
Test status | |
Simulation time | 3342835452 ps |
CPU time | 56.75 seconds |
Started | Aug 27 12:39:30 AM UTC 24 |
Finished | Aug 27 12:40:43 AM UTC 24 |
Peak memory | 154576 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2616567119 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 23.prim_prince_test.2616567119 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/23.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/230.prim_prince_test.4224146202 |
Short name | T224 |
Test name | |
Test status | |
Simulation time | 1190753701 ps |
CPU time | 20.39 seconds |
Started | Aug 27 12:51:38 AM UTC 24 |
Finished | Aug 27 12:52:05 AM UTC 24 |
Peak memory | 154600 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4224146202 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 230.prim_prince_test.4224146202 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/230.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/231.prim_prince_test.1151504995 |
Short name | T237 |
Test name | |
Test status | |
Simulation time | 2704161841 ps |
CPU time | 45.69 seconds |
Started | Aug 27 12:51:39 AM UTC 24 |
Finished | Aug 27 12:52:38 AM UTC 24 |
Peak memory | 154664 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1151504995 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 231.prim_prince_test.1151504995 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/231.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/232.prim_prince_test.1831217356 |
Short name | T235 |
Test name | |
Test status | |
Simulation time | 2550376934 ps |
CPU time | 42.76 seconds |
Started | Aug 27 12:51:41 AM UTC 24 |
Finished | Aug 27 12:52:37 AM UTC 24 |
Peak memory | 154664 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1831217356 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 232.prim_prince_test.1831217356 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/232.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/233.prim_prince_test.885017143 |
Short name | T228 |
Test name | |
Test status | |
Simulation time | 1342938532 ps |
CPU time | 22.86 seconds |
Started | Aug 27 12:51:45 AM UTC 24 |
Finished | Aug 27 12:52:16 AM UTC 24 |
Peak memory | 154600 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=885017143 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 233.prim_prince_test.885017143 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/233.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/234.prim_prince_test.3623634806 |
Short name | T229 |
Test name | |
Test status | |
Simulation time | 1318523023 ps |
CPU time | 22.2 seconds |
Started | Aug 27 12:51:48 AM UTC 24 |
Finished | Aug 27 12:52:17 AM UTC 24 |
Peak memory | 154600 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3623634806 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 234.prim_prince_test.3623634806 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/234.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/235.prim_prince_test.1622068107 |
Short name | T243 |
Test name | |
Test status | |
Simulation time | 2852933018 ps |
CPU time | 47.61 seconds |
Started | Aug 27 12:51:50 AM UTC 24 |
Finished | Aug 27 12:52:52 AM UTC 24 |
Peak memory | 154664 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1622068107 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 235.prim_prince_test.1622068107 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/235.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/236.prim_prince_test.3192001495 |
Short name | T234 |
Test name | |
Test status | |
Simulation time | 1485901562 ps |
CPU time | 25.23 seconds |
Started | Aug 27 12:51:50 AM UTC 24 |
Finished | Aug 27 12:52:23 AM UTC 24 |
Peak memory | 154600 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3192001495 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 236.prim_prince_test.3192001495 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/236.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/237.prim_prince_test.2764630676 |
Short name | T231 |
Test name | |
Test status | |
Simulation time | 1039590827 ps |
CPU time | 17.82 seconds |
Started | Aug 27 12:51:57 AM UTC 24 |
Finished | Aug 27 12:52:21 AM UTC 24 |
Peak memory | 154600 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2764630676 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 237.prim_prince_test.2764630676 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/237.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/238.prim_prince_test.438943998 |
Short name | T236 |
Test name | |
Test status | |
Simulation time | 1715315928 ps |
CPU time | 29.02 seconds |
Started | Aug 27 12:52:00 AM UTC 24 |
Finished | Aug 27 12:52:38 AM UTC 24 |
Peak memory | 154600 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=438943998 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 238.prim_prince_test.438943998 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/238.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/239.prim_prince_test.1682201245 |
Short name | T247 |
Test name | |
Test status | |
Simulation time | 3167245226 ps |
CPU time | 53.48 seconds |
Started | Aug 27 12:52:04 AM UTC 24 |
Finished | Aug 27 12:53:13 AM UTC 24 |
Peak memory | 154636 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1682201245 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 239.prim_prince_test.1682201245 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/239.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/24.prim_prince_test.4002854236 |
Short name | T28 |
Test name | |
Test status | |
Simulation time | 2905703989 ps |
CPU time | 49.81 seconds |
Started | Aug 27 12:39:36 AM UTC 24 |
Finished | Aug 27 12:40:41 AM UTC 24 |
Peak memory | 154664 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4002854236 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 24.prim_prince_test.4002854236 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/24.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/240.prim_prince_test.3542908693 |
Short name | T245 |
Test name | |
Test status | |
Simulation time | 3072963415 ps |
CPU time | 51.34 seconds |
Started | Aug 27 12:52:04 AM UTC 24 |
Finished | Aug 27 12:53:10 AM UTC 24 |
Peak memory | 154676 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3542908693 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 240.prim_prince_test.3542908693 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/240.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/241.prim_prince_test.3987993912 |
Short name | T239 |
Test name | |
Test status | |
Simulation time | 1648087407 ps |
CPU time | 27.99 seconds |
Started | Aug 27 12:52:05 AM UTC 24 |
Finished | Aug 27 12:52:42 AM UTC 24 |
Peak memory | 154600 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3987993912 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 241.prim_prince_test.3987993912 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/241.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/242.prim_prince_test.1388660221 |
Short name | T252 |
Test name | |
Test status | |
Simulation time | 3664177106 ps |
CPU time | 61.28 seconds |
Started | Aug 27 12:52:08 AM UTC 24 |
Finished | Aug 27 12:53:28 AM UTC 24 |
Peak memory | 154672 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1388660221 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 242.prim_prince_test.1388660221 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/242.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/243.prim_prince_test.2442963240 |
Short name | T241 |
Test name | |
Test status | |
Simulation time | 1621202792 ps |
CPU time | 27.08 seconds |
Started | Aug 27 12:52:10 AM UTC 24 |
Finished | Aug 27 12:52:46 AM UTC 24 |
Peak memory | 154600 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2442963240 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 243.prim_prince_test.2442963240 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/243.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/244.prim_prince_test.1825739477 |
Short name | T238 |
Test name | |
Test status | |
Simulation time | 1042933455 ps |
CPU time | 17.84 seconds |
Started | Aug 27 12:52:15 AM UTC 24 |
Finished | Aug 27 12:52:38 AM UTC 24 |
Peak memory | 154592 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1825739477 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 244.prim_prince_test.1825739477 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/244.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/245.prim_prince_test.4101001770 |
Short name | T246 |
Test name | |
Test status | |
Simulation time | 2543199868 ps |
CPU time | 42.76 seconds |
Started | Aug 27 12:52:16 AM UTC 24 |
Finished | Aug 27 12:53:12 AM UTC 24 |
Peak memory | 154656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4101001770 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 245.prim_prince_test.4101001770 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/245.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/246.prim_prince_test.1853340926 |
Short name | T254 |
Test name | |
Test status | |
Simulation time | 3382091528 ps |
CPU time | 56.73 seconds |
Started | Aug 27 12:52:18 AM UTC 24 |
Finished | Aug 27 12:53:32 AM UTC 24 |
Peak memory | 154656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1853340926 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 246.prim_prince_test.1853340926 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/246.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/247.prim_prince_test.2961781178 |
Short name | T253 |
Test name | |
Test status | |
Simulation time | 3176728001 ps |
CPU time | 53.37 seconds |
Started | Aug 27 12:52:20 AM UTC 24 |
Finished | Aug 27 12:53:28 AM UTC 24 |
Peak memory | 154656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2961781178 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 247.prim_prince_test.2961781178 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/247.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/248.prim_prince_test.3885268278 |
Short name | T251 |
Test name | |
Test status | |
Simulation time | 2733923083 ps |
CPU time | 45.99 seconds |
Started | Aug 27 12:52:22 AM UTC 24 |
Finished | Aug 27 12:53:22 AM UTC 24 |
Peak memory | 154656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3885268278 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 248.prim_prince_test.3885268278 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/248.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/249.prim_prince_test.332749229 |
Short name | T256 |
Test name | |
Test status | |
Simulation time | 3443728350 ps |
CPU time | 57.56 seconds |
Started | Aug 27 12:52:22 AM UTC 24 |
Finished | Aug 27 12:53:37 AM UTC 24 |
Peak memory | 156100 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=332749229 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 249.prim_prince_test.332749229 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/249.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/25.prim_prince_test.4167348624 |
Short name | T31 |
Test name | |
Test status | |
Simulation time | 3497169440 ps |
CPU time | 59.65 seconds |
Started | Aug 27 12:39:39 AM UTC 24 |
Finished | Aug 27 12:40:56 AM UTC 24 |
Peak memory | 154664 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4167348624 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 25.prim_prince_test.4167348624 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/25.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/250.prim_prince_test.3519201598 |
Short name | T255 |
Test name | |
Test status | |
Simulation time | 3297630379 ps |
CPU time | 55.19 seconds |
Started | Aug 27 12:52:23 AM UTC 24 |
Finished | Aug 27 12:53:35 AM UTC 24 |
Peak memory | 154656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3519201598 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 250.prim_prince_test.3519201598 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/250.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/251.prim_prince_test.3218063479 |
Short name | T240 |
Test name | |
Test status | |
Simulation time | 783803784 ps |
CPU time | 13.69 seconds |
Started | Aug 27 12:52:25 AM UTC 24 |
Finished | Aug 27 12:52:43 AM UTC 24 |
Peak memory | 154592 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3218063479 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 251.prim_prince_test.3218063479 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/251.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/252.prim_prince_test.19748469 |
Short name | T244 |
Test name | |
Test status | |
Simulation time | 768517283 ps |
CPU time | 13.12 seconds |
Started | Aug 27 12:52:38 AM UTC 24 |
Finished | Aug 27 12:52:55 AM UTC 24 |
Peak memory | 154600 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19748469 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 252.prim_prince_test.19748469 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/252.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/253.prim_prince_test.3458484839 |
Short name | T257 |
Test name | |
Test status | |
Simulation time | 2623385548 ps |
CPU time | 44.51 seconds |
Started | Aug 27 12:52:39 AM UTC 24 |
Finished | Aug 27 12:53:37 AM UTC 24 |
Peak memory | 154656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3458484839 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 253.prim_prince_test.3458484839 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/253.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/254.prim_prince_test.29200099 |
Short name | T258 |
Test name | |
Test status | |
Simulation time | 2874448610 ps |
CPU time | 48.32 seconds |
Started | Aug 27 12:52:39 AM UTC 24 |
Finished | Aug 27 12:53:42 AM UTC 24 |
Peak memory | 154664 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29200099 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 254.prim_prince_test.29200099 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/254.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/255.prim_prince_test.3579892863 |
Short name | T249 |
Test name | |
Test status | |
Simulation time | 1765867999 ps |
CPU time | 29.82 seconds |
Started | Aug 27 12:52:39 AM UTC 24 |
Finished | Aug 27 12:53:18 AM UTC 24 |
Peak memory | 154592 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3579892863 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 255.prim_prince_test.3579892863 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/255.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/256.prim_prince_test.1698666786 |
Short name | T250 |
Test name | |
Test status | |
Simulation time | 1642005463 ps |
CPU time | 27.81 seconds |
Started | Aug 27 12:52:43 AM UTC 24 |
Finished | Aug 27 12:53:19 AM UTC 24 |
Peak memory | 154592 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1698666786 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 256.prim_prince_test.1698666786 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/256.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/257.prim_prince_test.3225648313 |
Short name | T261 |
Test name | |
Test status | |
Simulation time | 3146860546 ps |
CPU time | 52.72 seconds |
Started | Aug 27 12:52:44 AM UTC 24 |
Finished | Aug 27 12:53:52 AM UTC 24 |
Peak memory | 154656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3225648313 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 257.prim_prince_test.3225648313 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/257.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/258.prim_prince_test.2273120969 |
Short name | T248 |
Test name | |
Test status | |
Simulation time | 1317066272 ps |
CPU time | 22.24 seconds |
Started | Aug 27 12:52:46 AM UTC 24 |
Finished | Aug 27 12:53:15 AM UTC 24 |
Peak memory | 154592 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2273120969 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 258.prim_prince_test.2273120969 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/258.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/259.prim_prince_test.1897812857 |
Short name | T266 |
Test name | |
Test status | |
Simulation time | 3124667387 ps |
CPU time | 52.57 seconds |
Started | Aug 27 12:52:53 AM UTC 24 |
Finished | Aug 27 12:54:01 AM UTC 24 |
Peak memory | 154656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1897812857 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 259.prim_prince_test.1897812857 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/259.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/26.prim_prince_test.431689152 |
Short name | T27 |
Test name | |
Test status | |
Simulation time | 2468186406 ps |
CPU time | 42.04 seconds |
Started | Aug 27 12:39:42 AM UTC 24 |
Finished | Aug 27 12:40:36 AM UTC 24 |
Peak memory | 154664 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=431689152 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 26.prim_prince_test.431689152 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/26.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/260.prim_prince_test.4273841077 |
Short name | T260 |
Test name | |
Test status | |
Simulation time | 2515848757 ps |
CPU time | 42.19 seconds |
Started | Aug 27 12:52:53 AM UTC 24 |
Finished | Aug 27 12:53:48 AM UTC 24 |
Peak memory | 154656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4273841077 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 260.prim_prince_test.4273841077 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/260.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/261.prim_prince_test.3336508581 |
Short name | T259 |
Test name | |
Test status | |
Simulation time | 2170616866 ps |
CPU time | 36.55 seconds |
Started | Aug 27 12:52:56 AM UTC 24 |
Finished | Aug 27 12:53:44 AM UTC 24 |
Peak memory | 154656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3336508581 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 261.prim_prince_test.3336508581 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/261.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/262.prim_prince_test.398262611 |
Short name | T277 |
Test name | |
Test status | |
Simulation time | 3748792115 ps |
CPU time | 62.89 seconds |
Started | Aug 27 12:53:11 AM UTC 24 |
Finished | Aug 27 12:54:32 AM UTC 24 |
Peak memory | 154664 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=398262611 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 262.prim_prince_test.398262611 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/262.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/263.prim_prince_test.2129959775 |
Short name | T265 |
Test name | |
Test status | |
Simulation time | 2176392196 ps |
CPU time | 36.5 seconds |
Started | Aug 27 12:53:12 AM UTC 24 |
Finished | Aug 27 12:54:00 AM UTC 24 |
Peak memory | 154656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2129959775 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 263.prim_prince_test.2129959775 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/263.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/264.prim_prince_test.2431154817 |
Short name | T269 |
Test name | |
Test status | |
Simulation time | 2635281575 ps |
CPU time | 44.24 seconds |
Started | Aug 27 12:53:14 AM UTC 24 |
Finished | Aug 27 12:54:11 AM UTC 24 |
Peak memory | 154652 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2431154817 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 264.prim_prince_test.2431154817 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/264.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/265.prim_prince_test.745319503 |
Short name | T263 |
Test name | |
Test status | |
Simulation time | 1831155887 ps |
CPU time | 31.14 seconds |
Started | Aug 27 12:53:17 AM UTC 24 |
Finished | Aug 27 12:53:57 AM UTC 24 |
Peak memory | 154600 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=745319503 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 265.prim_prince_test.745319503 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/265.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/266.prim_prince_test.285673691 |
Short name | T272 |
Test name | |
Test status | |
Simulation time | 2929915635 ps |
CPU time | 49.57 seconds |
Started | Aug 27 12:53:19 AM UTC 24 |
Finished | Aug 27 12:54:23 AM UTC 24 |
Peak memory | 154664 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=285673691 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 266.prim_prince_test.285673691 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/266.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/267.prim_prince_test.1457217490 |
Short name | T268 |
Test name | |
Test status | |
Simulation time | 2098624782 ps |
CPU time | 35.6 seconds |
Started | Aug 27 12:53:20 AM UTC 24 |
Finished | Aug 27 12:54:06 AM UTC 24 |
Peak memory | 154592 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1457217490 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 267.prim_prince_test.1457217490 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/267.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/268.prim_prince_test.538733526 |
Short name | T267 |
Test name | |
Test status | |
Simulation time | 1886466934 ps |
CPU time | 31.7 seconds |
Started | Aug 27 12:53:23 AM UTC 24 |
Finished | Aug 27 12:54:04 AM UTC 24 |
Peak memory | 154600 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=538733526 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 268.prim_prince_test.538733526 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/268.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/269.prim_prince_test.3364788966 |
Short name | T262 |
Test name | |
Test status | |
Simulation time | 1114506748 ps |
CPU time | 19.01 seconds |
Started | Aug 27 12:53:29 AM UTC 24 |
Finished | Aug 27 12:53:54 AM UTC 24 |
Peak memory | 154588 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3364788966 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 269.prim_prince_test.3364788966 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/269.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/27.prim_prince_test.1233522908 |
Short name | T21 |
Test name | |
Test status | |
Simulation time | 1128096421 ps |
CPU time | 19.64 seconds |
Started | Aug 27 12:39:43 AM UTC 24 |
Finished | Aug 27 12:40:08 AM UTC 24 |
Peak memory | 154600 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1233522908 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 27.prim_prince_test.1233522908 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/27.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/270.prim_prince_test.3683233858 |
Short name | T283 |
Test name | |
Test status | |
Simulation time | 3628206494 ps |
CPU time | 60.55 seconds |
Started | Aug 27 12:53:29 AM UTC 24 |
Finished | Aug 27 12:54:47 AM UTC 24 |
Peak memory | 154656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3683233858 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 270.prim_prince_test.3683233858 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/270.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/271.prim_prince_test.3334595762 |
Short name | T276 |
Test name | |
Test status | |
Simulation time | 2748727555 ps |
CPU time | 46.13 seconds |
Started | Aug 27 12:53:32 AM UTC 24 |
Finished | Aug 27 12:54:32 AM UTC 24 |
Peak memory | 154656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3334595762 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 271.prim_prince_test.3334595762 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/271.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/272.prim_prince_test.2752266090 |
Short name | T273 |
Test name | |
Test status | |
Simulation time | 2351466975 ps |
CPU time | 39.37 seconds |
Started | Aug 27 12:53:36 AM UTC 24 |
Finished | Aug 27 12:54:27 AM UTC 24 |
Peak memory | 154656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2752266090 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 272.prim_prince_test.2752266090 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/272.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/273.prim_prince_test.4293733350 |
Short name | T264 |
Test name | |
Test status | |
Simulation time | 884887077 ps |
CPU time | 15.3 seconds |
Started | Aug 27 12:53:38 AM UTC 24 |
Finished | Aug 27 12:53:58 AM UTC 24 |
Peak memory | 154592 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4293733350 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 273.prim_prince_test.4293733350 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/273.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/274.prim_prince_test.2122501883 |
Short name | T270 |
Test name | |
Test status | |
Simulation time | 1741068023 ps |
CPU time | 29.34 seconds |
Started | Aug 27 12:53:38 AM UTC 24 |
Finished | Aug 27 12:54:16 AM UTC 24 |
Peak memory | 154588 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2122501883 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 274.prim_prince_test.2122501883 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/274.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/275.prim_prince_test.2802174576 |
Short name | T271 |
Test name | |
Test status | |
Simulation time | 1723900802 ps |
CPU time | 29.02 seconds |
Started | Aug 27 12:53:42 AM UTC 24 |
Finished | Aug 27 12:54:20 AM UTC 24 |
Peak memory | 154592 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2802174576 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 275.prim_prince_test.2802174576 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/275.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/276.prim_prince_test.2200951992 |
Short name | T280 |
Test name | |
Test status | |
Simulation time | 2728955070 ps |
CPU time | 45.55 seconds |
Started | Aug 27 12:53:45 AM UTC 24 |
Finished | Aug 27 12:54:44 AM UTC 24 |
Peak memory | 154656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2200951992 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 276.prim_prince_test.2200951992 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/276.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/277.prim_prince_test.2096328994 |
Short name | T286 |
Test name | |
Test status | |
Simulation time | 3313954109 ps |
CPU time | 55.63 seconds |
Started | Aug 27 12:53:49 AM UTC 24 |
Finished | Aug 27 12:55:01 AM UTC 24 |
Peak memory | 154656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2096328994 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 277.prim_prince_test.2096328994 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/277.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/278.prim_prince_test.3515134279 |
Short name | T282 |
Test name | |
Test status | |
Simulation time | 2434836700 ps |
CPU time | 41.04 seconds |
Started | Aug 27 12:53:53 AM UTC 24 |
Finished | Aug 27 12:54:46 AM UTC 24 |
Peak memory | 154656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3515134279 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 278.prim_prince_test.3515134279 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/278.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/279.prim_prince_test.226258167 |
Short name | T274 |
Test name | |
Test status | |
Simulation time | 1442458188 ps |
CPU time | 24.38 seconds |
Started | Aug 27 12:53:55 AM UTC 24 |
Finished | Aug 27 12:54:27 AM UTC 24 |
Peak memory | 154600 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=226258167 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 279.prim_prince_test.226258167 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/279.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/28.prim_prince_test.1892134859 |
Short name | T32 |
Test name | |
Test status | |
Simulation time | 2977560283 ps |
CPU time | 50.84 seconds |
Started | Aug 27 12:40:04 AM UTC 24 |
Finished | Aug 27 12:41:09 AM UTC 24 |
Peak memory | 154664 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1892134859 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 28.prim_prince_test.1892134859 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/28.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/280.prim_prince_test.349304806 |
Short name | T287 |
Test name | |
Test status | |
Simulation time | 3118940598 ps |
CPU time | 52.59 seconds |
Started | Aug 27 12:53:59 AM UTC 24 |
Finished | Aug 27 12:55:07 AM UTC 24 |
Peak memory | 154664 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=349304806 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 280.prim_prince_test.349304806 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/280.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/281.prim_prince_test.2238205388 |
Short name | T293 |
Test name | |
Test status | |
Simulation time | 3668227124 ps |
CPU time | 61.91 seconds |
Started | Aug 27 12:53:59 AM UTC 24 |
Finished | Aug 27 12:55:19 AM UTC 24 |
Peak memory | 156112 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2238205388 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 281.prim_prince_test.2238205388 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/281.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/282.prim_prince_test.148533261 |
Short name | T279 |
Test name | |
Test status | |
Simulation time | 1728880791 ps |
CPU time | 29.09 seconds |
Started | Aug 27 12:54:01 AM UTC 24 |
Finished | Aug 27 12:54:39 AM UTC 24 |
Peak memory | 154596 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=148533261 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 282.prim_prince_test.148533261 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/282.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/283.prim_prince_test.4208240037 |
Short name | T278 |
Test name | |
Test status | |
Simulation time | 1531526943 ps |
CPU time | 26.04 seconds |
Started | Aug 27 12:54:02 AM UTC 24 |
Finished | Aug 27 12:54:36 AM UTC 24 |
Peak memory | 154592 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4208240037 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 283.prim_prince_test.4208240037 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/283.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/284.prim_prince_test.758948335 |
Short name | T285 |
Test name | |
Test status | |
Simulation time | 2442542150 ps |
CPU time | 41.1 seconds |
Started | Aug 27 12:54:05 AM UTC 24 |
Finished | Aug 27 12:54:58 AM UTC 24 |
Peak memory | 154664 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=758948335 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 284.prim_prince_test.758948335 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/284.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/285.prim_prince_test.3674569272 |
Short name | T275 |
Test name | |
Test status | |
Simulation time | 945447867 ps |
CPU time | 16.15 seconds |
Started | Aug 27 12:54:08 AM UTC 24 |
Finished | Aug 27 12:54:29 AM UTC 24 |
Peak memory | 154588 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3674569272 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 285.prim_prince_test.3674569272 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/285.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/286.prim_prince_test.307996903 |
Short name | T281 |
Test name | |
Test status | |
Simulation time | 1434091283 ps |
CPU time | 24.4 seconds |
Started | Aug 27 12:54:12 AM UTC 24 |
Finished | Aug 27 12:54:44 AM UTC 24 |
Peak memory | 154600 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=307996903 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 286.prim_prince_test.307996903 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/286.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/287.prim_prince_test.1134947033 |
Short name | T284 |
Test name | |
Test status | |
Simulation time | 1348980495 ps |
CPU time | 22.9 seconds |
Started | Aug 27 12:54:17 AM UTC 24 |
Finished | Aug 27 12:54:47 AM UTC 24 |
Peak memory | 154592 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1134947033 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 287.prim_prince_test.1134947033 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/287.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/288.prim_prince_test.2060651567 |
Short name | T291 |
Test name | |
Test status | |
Simulation time | 2398144190 ps |
CPU time | 40.41 seconds |
Started | Aug 27 12:54:21 AM UTC 24 |
Finished | Aug 27 12:55:13 AM UTC 24 |
Peak memory | 154656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2060651567 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 288.prim_prince_test.2060651567 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/288.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/289.prim_prince_test.604351442 |
Short name | T289 |
Test name | |
Test status | |
Simulation time | 2065770154 ps |
CPU time | 35.12 seconds |
Started | Aug 27 12:54:24 AM UTC 24 |
Finished | Aug 27 12:55:10 AM UTC 24 |
Peak memory | 154600 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=604351442 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 289.prim_prince_test.604351442 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/289.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/29.prim_prince_test.3849594233 |
Short name | T26 |
Test name | |
Test status | |
Simulation time | 1377551630 ps |
CPU time | 23.8 seconds |
Started | Aug 27 12:40:05 AM UTC 24 |
Finished | Aug 27 12:40:36 AM UTC 24 |
Peak memory | 154600 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3849594233 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 29.prim_prince_test.3849594233 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/29.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/290.prim_prince_test.2060450489 |
Short name | T288 |
Test name | |
Test status | |
Simulation time | 1872659530 ps |
CPU time | 31.92 seconds |
Started | Aug 27 12:54:27 AM UTC 24 |
Finished | Aug 27 12:55:09 AM UTC 24 |
Peak memory | 154592 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2060450489 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 290.prim_prince_test.2060450489 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/290.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/291.prim_prince_test.1215021954 |
Short name | T301 |
Test name | |
Test status | |
Simulation time | 3349389987 ps |
CPU time | 56.34 seconds |
Started | Aug 27 12:54:28 AM UTC 24 |
Finished | Aug 27 12:55:41 AM UTC 24 |
Peak memory | 154660 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1215021954 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 291.prim_prince_test.1215021954 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/291.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/292.prim_prince_test.1411549232 |
Short name | T290 |
Test name | |
Test status | |
Simulation time | 1760278347 ps |
CPU time | 30.01 seconds |
Started | Aug 27 12:54:31 AM UTC 24 |
Finished | Aug 27 12:55:10 AM UTC 24 |
Peak memory | 154592 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1411549232 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 292.prim_prince_test.1411549232 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/292.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/293.prim_prince_test.2998591834 |
Short name | T296 |
Test name | |
Test status | |
Simulation time | 2526482050 ps |
CPU time | 42.56 seconds |
Started | Aug 27 12:54:33 AM UTC 24 |
Finished | Aug 27 12:55:29 AM UTC 24 |
Peak memory | 154656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2998591834 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 293.prim_prince_test.2998591834 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/293.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/294.prim_prince_test.3207167923 |
Short name | T295 |
Test name | |
Test status | |
Simulation time | 2490059890 ps |
CPU time | 42.12 seconds |
Started | Aug 27 12:54:33 AM UTC 24 |
Finished | Aug 27 12:55:28 AM UTC 24 |
Peak memory | 154656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3207167923 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 294.prim_prince_test.3207167923 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/294.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/295.prim_prince_test.3213159962 |
Short name | T294 |
Test name | |
Test status | |
Simulation time | 1872656291 ps |
CPU time | 31.65 seconds |
Started | Aug 27 12:54:38 AM UTC 24 |
Finished | Aug 27 12:55:19 AM UTC 24 |
Peak memory | 154592 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3213159962 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 295.prim_prince_test.3213159962 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/295.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/296.prim_prince_test.3659502381 |
Short name | T307 |
Test name | |
Test status | |
Simulation time | 3466143949 ps |
CPU time | 58.13 seconds |
Started | Aug 27 12:54:40 AM UTC 24 |
Finished | Aug 27 12:55:55 AM UTC 24 |
Peak memory | 154660 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3659502381 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 296.prim_prince_test.3659502381 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/296.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/297.prim_prince_test.552130534 |
Short name | T292 |
Test name | |
Test status | |
Simulation time | 1504089243 ps |
CPU time | 25.64 seconds |
Started | Aug 27 12:54:44 AM UTC 24 |
Finished | Aug 27 12:55:18 AM UTC 24 |
Peak memory | 154596 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=552130534 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 297.prim_prince_test.552130534 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/297.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/298.prim_prince_test.3474441145 |
Short name | T305 |
Test name | |
Test status | |
Simulation time | 3122358488 ps |
CPU time | 52.63 seconds |
Started | Aug 27 12:54:45 AM UTC 24 |
Finished | Aug 27 12:55:54 AM UTC 24 |
Peak memory | 154656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3474441145 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 298.prim_prince_test.3474441145 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/298.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/299.prim_prince_test.3942019424 |
Short name | T297 |
Test name | |
Test status | |
Simulation time | 1978642219 ps |
CPU time | 33.7 seconds |
Started | Aug 27 12:54:48 AM UTC 24 |
Finished | Aug 27 12:55:32 AM UTC 24 |
Peak memory | 154352 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3942019424 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 299.prim_prince_test.3942019424 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/299.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/3.prim_prince_test.2350061341 |
Short name | T3 |
Test name | |
Test status | |
Simulation time | 1582241567 ps |
CPU time | 27.89 seconds |
Started | Aug 27 12:37:48 AM UTC 24 |
Finished | Aug 27 12:38:24 AM UTC 24 |
Peak memory | 154600 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2350061341 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 3.prim_prince_test.2350061341 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/3.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/30.prim_prince_test.4287509670 |
Short name | T30 |
Test name | |
Test status | |
Simulation time | 1784504103 ps |
CPU time | 30.53 seconds |
Started | Aug 27 12:40:09 AM UTC 24 |
Finished | Aug 27 12:40:49 AM UTC 24 |
Peak memory | 154600 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4287509670 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 30.prim_prince_test.4287509670 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/30.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/300.prim_prince_test.1131135066 |
Short name | T300 |
Test name | |
Test status | |
Simulation time | 2372218615 ps |
CPU time | 40.34 seconds |
Started | Aug 27 12:54:48 AM UTC 24 |
Finished | Aug 27 12:55:40 AM UTC 24 |
Peak memory | 154400 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1131135066 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 300.prim_prince_test.1131135066 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/300.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/301.prim_prince_test.349893984 |
Short name | T298 |
Test name | |
Test status | |
Simulation time | 2046167366 ps |
CPU time | 34.82 seconds |
Started | Aug 27 12:54:48 AM UTC 24 |
Finished | Aug 27 12:55:33 AM UTC 24 |
Peak memory | 154600 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=349893984 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 301.prim_prince_test.349893984 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/301.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/302.prim_prince_test.3488113143 |
Short name | T299 |
Test name | |
Test status | |
Simulation time | 1824042599 ps |
CPU time | 31.01 seconds |
Started | Aug 27 12:54:58 AM UTC 24 |
Finished | Aug 27 12:55:39 AM UTC 24 |
Peak memory | 154592 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3488113143 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 302.prim_prince_test.3488113143 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/302.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/303.prim_prince_test.2920253472 |
Short name | T315 |
Test name | |
Test status | |
Simulation time | 3511321627 ps |
CPU time | 59.11 seconds |
Started | Aug 27 12:55:03 AM UTC 24 |
Finished | Aug 27 12:56:19 AM UTC 24 |
Peak memory | 156524 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2920253472 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 303.prim_prince_test.2920253472 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/303.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/304.prim_prince_test.1362303489 |
Short name | T304 |
Test name | |
Test status | |
Simulation time | 1954774110 ps |
CPU time | 33.18 seconds |
Started | Aug 27 12:55:09 AM UTC 24 |
Finished | Aug 27 12:55:53 AM UTC 24 |
Peak memory | 154572 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1362303489 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 304.prim_prince_test.1362303489 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/304.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/305.prim_prince_test.1971110975 |
Short name | T314 |
Test name | |
Test status | |
Simulation time | 3077848671 ps |
CPU time | 52.01 seconds |
Started | Aug 27 12:55:12 AM UTC 24 |
Finished | Aug 27 12:56:19 AM UTC 24 |
Peak memory | 154640 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1971110975 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 305.prim_prince_test.1971110975 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/305.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/306.prim_prince_test.3817835749 |
Short name | T312 |
Test name | |
Test status | |
Simulation time | 2888201775 ps |
CPU time | 48.26 seconds |
Started | Aug 27 12:55:12 AM UTC 24 |
Finished | Aug 27 12:56:14 AM UTC 24 |
Peak memory | 154656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3817835749 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 306.prim_prince_test.3817835749 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/306.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/307.prim_prince_test.1345990484 |
Short name | T317 |
Test name | |
Test status | |
Simulation time | 3608195985 ps |
CPU time | 60.69 seconds |
Started | Aug 27 12:55:12 AM UTC 24 |
Finished | Aug 27 12:56:30 AM UTC 24 |
Peak memory | 154652 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1345990484 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 307.prim_prince_test.1345990484 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/307.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/308.prim_prince_test.2756676878 |
Short name | T303 |
Test name | |
Test status | |
Simulation time | 1556770488 ps |
CPU time | 26.43 seconds |
Started | Aug 27 12:55:15 AM UTC 24 |
Finished | Aug 27 12:55:50 AM UTC 24 |
Peak memory | 154592 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2756676878 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 308.prim_prince_test.2756676878 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/308.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/309.prim_prince_test.1173419770 |
Short name | T302 |
Test name | |
Test status | |
Simulation time | 1017692430 ps |
CPU time | 17.55 seconds |
Started | Aug 27 12:55:20 AM UTC 24 |
Finished | Aug 27 12:55:43 AM UTC 24 |
Peak memory | 154592 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1173419770 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 309.prim_prince_test.1173419770 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/309.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/31.prim_prince_test.1095330606 |
Short name | T33 |
Test name | |
Test status | |
Simulation time | 2528269617 ps |
CPU time | 43.85 seconds |
Started | Aug 27 12:40:14 AM UTC 24 |
Finished | Aug 27 12:41:10 AM UTC 24 |
Peak memory | 154664 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1095330606 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 31.prim_prince_test.1095330606 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/31.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/310.prim_prince_test.806706500 |
Short name | T309 |
Test name | |
Test status | |
Simulation time | 1939719649 ps |
CPU time | 32.59 seconds |
Started | Aug 27 12:55:20 AM UTC 24 |
Finished | Aug 27 12:56:02 AM UTC 24 |
Peak memory | 154596 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=806706500 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 310.prim_prince_test.806706500 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/310.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/311.prim_prince_test.3505799502 |
Short name | T308 |
Test name | |
Test status | |
Simulation time | 1735136948 ps |
CPU time | 29.26 seconds |
Started | Aug 27 12:55:20 AM UTC 24 |
Finished | Aug 27 12:55:58 AM UTC 24 |
Peak memory | 154572 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3505799502 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 311.prim_prince_test.3505799502 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/311.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/312.prim_prince_test.3907517319 |
Short name | T306 |
Test name | |
Test status | |
Simulation time | 1359667758 ps |
CPU time | 23.21 seconds |
Started | Aug 27 12:55:23 AM UTC 24 |
Finished | Aug 27 12:55:54 AM UTC 24 |
Peak memory | 154592 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3907517319 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 312.prim_prince_test.3907517319 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/312.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/313.prim_prince_test.4074570957 |
Short name | T313 |
Test name | |
Test status | |
Simulation time | 2161881621 ps |
CPU time | 36.29 seconds |
Started | Aug 27 12:55:28 AM UTC 24 |
Finished | Aug 27 12:56:16 AM UTC 24 |
Peak memory | 154656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4074570957 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 313.prim_prince_test.4074570957 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/313.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/314.prim_prince_test.2660639958 |
Short name | T322 |
Test name | |
Test status | |
Simulation time | 3390722560 ps |
CPU time | 56.77 seconds |
Started | Aug 27 12:55:30 AM UTC 24 |
Finished | Aug 27 12:56:43 AM UTC 24 |
Peak memory | 154660 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2660639958 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 314.prim_prince_test.2660639958 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/314.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/315.prim_prince_test.3436851811 |
Short name | T310 |
Test name | |
Test status | |
Simulation time | 1673355181 ps |
CPU time | 27.9 seconds |
Started | Aug 27 12:55:33 AM UTC 24 |
Finished | Aug 27 12:56:09 AM UTC 24 |
Peak memory | 154592 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3436851811 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 315.prim_prince_test.3436851811 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/315.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/316.prim_prince_test.3864554857 |
Short name | T311 |
Test name | |
Test status | |
Simulation time | 1757507926 ps |
CPU time | 29.87 seconds |
Started | Aug 27 12:55:34 AM UTC 24 |
Finished | Aug 27 12:56:13 AM UTC 24 |
Peak memory | 154592 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3864554857 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 316.prim_prince_test.3864554857 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/316.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/317.prim_prince_test.220874298 |
Short name | T318 |
Test name | |
Test status | |
Simulation time | 2341586373 ps |
CPU time | 39.53 seconds |
Started | Aug 27 12:55:40 AM UTC 24 |
Finished | Aug 27 12:56:31 AM UTC 24 |
Peak memory | 154664 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=220874298 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 317.prim_prince_test.220874298 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/317.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/318.prim_prince_test.493145134 |
Short name | T325 |
Test name | |
Test status | |
Simulation time | 3234058334 ps |
CPU time | 53.96 seconds |
Started | Aug 27 12:55:41 AM UTC 24 |
Finished | Aug 27 12:56:51 AM UTC 24 |
Peak memory | 154664 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=493145134 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 318.prim_prince_test.493145134 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/318.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/319.prim_prince_test.136200003 |
Short name | T316 |
Test name | |
Test status | |
Simulation time | 2154662029 ps |
CPU time | 36.63 seconds |
Started | Aug 27 12:55:42 AM UTC 24 |
Finished | Aug 27 12:56:30 AM UTC 24 |
Peak memory | 154664 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=136200003 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 319.prim_prince_test.136200003 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/319.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/32.prim_prince_test.587658009 |
Short name | T36 |
Test name | |
Test status | |
Simulation time | 2588733802 ps |
CPU time | 44.52 seconds |
Started | Aug 27 12:40:26 AM UTC 24 |
Finished | Aug 27 12:41:24 AM UTC 24 |
Peak memory | 154664 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=587658009 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 32.prim_prince_test.587658009 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/32.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/320.prim_prince_test.237834187 |
Short name | T331 |
Test name | |
Test status | |
Simulation time | 3383734676 ps |
CPU time | 56.54 seconds |
Started | Aug 27 12:55:44 AM UTC 24 |
Finished | Aug 27 12:56:57 AM UTC 24 |
Peak memory | 154664 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=237834187 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 320.prim_prince_test.237834187 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/320.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/321.prim_prince_test.3574092186 |
Short name | T321 |
Test name | |
Test status | |
Simulation time | 1959368554 ps |
CPU time | 32.88 seconds |
Started | Aug 27 12:55:51 AM UTC 24 |
Finished | Aug 27 12:56:34 AM UTC 24 |
Peak memory | 154584 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3574092186 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 321.prim_prince_test.3574092186 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/321.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/322.prim_prince_test.2328910615 |
Short name | T323 |
Test name | |
Test status | |
Simulation time | 2558340004 ps |
CPU time | 43.09 seconds |
Started | Aug 27 12:55:53 AM UTC 24 |
Finished | Aug 27 12:56:49 AM UTC 24 |
Peak memory | 154652 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2328910615 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 322.prim_prince_test.2328910615 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/322.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/323.prim_prince_test.3425709036 |
Short name | T319 |
Test name | |
Test status | |
Simulation time | 1650749220 ps |
CPU time | 28.25 seconds |
Started | Aug 27 12:55:55 AM UTC 24 |
Finished | Aug 27 12:56:32 AM UTC 24 |
Peak memory | 154592 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3425709036 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 323.prim_prince_test.3425709036 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/323.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/324.prim_prince_test.1098143883 |
Short name | T324 |
Test name | |
Test status | |
Simulation time | 2519774723 ps |
CPU time | 42.5 seconds |
Started | Aug 27 12:55:55 AM UTC 24 |
Finished | Aug 27 12:56:50 AM UTC 24 |
Peak memory | 154656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1098143883 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 324.prim_prince_test.1098143883 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/324.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/325.prim_prince_test.1634549933 |
Short name | T327 |
Test name | |
Test status | |
Simulation time | 2543241079 ps |
CPU time | 42.55 seconds |
Started | Aug 27 12:55:56 AM UTC 24 |
Finished | Aug 27 12:56:51 AM UTC 24 |
Peak memory | 154656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1634549933 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 325.prim_prince_test.1634549933 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/325.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/326.prim_prince_test.3334858932 |
Short name | T334 |
Test name | |
Test status | |
Simulation time | 3509196175 ps |
CPU time | 58.8 seconds |
Started | Aug 27 12:55:59 AM UTC 24 |
Finished | Aug 27 12:57:15 AM UTC 24 |
Peak memory | 157980 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3334858932 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 326.prim_prince_test.3334858932 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/326.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/327.prim_prince_test.2218356265 |
Short name | T328 |
Test name | |
Test status | |
Simulation time | 2193177194 ps |
CPU time | 37.15 seconds |
Started | Aug 27 12:56:04 AM UTC 24 |
Finished | Aug 27 12:56:52 AM UTC 24 |
Peak memory | 154656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2218356265 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 327.prim_prince_test.2218356265 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/327.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/328.prim_prince_test.3477948382 |
Short name | T320 |
Test name | |
Test status | |
Simulation time | 1009746386 ps |
CPU time | 17.39 seconds |
Started | Aug 27 12:56:10 AM UTC 24 |
Finished | Aug 27 12:56:33 AM UTC 24 |
Peak memory | 154592 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3477948382 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 328.prim_prince_test.3477948382 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/328.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/329.prim_prince_test.1516463280 |
Short name | T335 |
Test name | |
Test status | |
Simulation time | 3072826435 ps |
CPU time | 51.82 seconds |
Started | Aug 27 12:56:14 AM UTC 24 |
Finished | Aug 27 12:57:21 AM UTC 24 |
Peak memory | 154644 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1516463280 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 329.prim_prince_test.1516463280 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/329.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/33.prim_prince_test.3831142836 |
Short name | T37 |
Test name | |
Test status | |
Simulation time | 2544921092 ps |
CPU time | 43.52 seconds |
Started | Aug 27 12:40:28 AM UTC 24 |
Finished | Aug 27 12:41:25 AM UTC 24 |
Peak memory | 154664 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3831142836 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 33.prim_prince_test.3831142836 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/33.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/330.prim_prince_test.2543422493 |
Short name | T330 |
Test name | |
Test status | |
Simulation time | 1857650709 ps |
CPU time | 31.42 seconds |
Started | Aug 27 12:56:15 AM UTC 24 |
Finished | Aug 27 12:56:56 AM UTC 24 |
Peak memory | 154592 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2543422493 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 330.prim_prince_test.2543422493 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/330.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/331.prim_prince_test.3020660756 |
Short name | T344 |
Test name | |
Test status | |
Simulation time | 3462093668 ps |
CPU time | 57.84 seconds |
Started | Aug 27 12:56:17 AM UTC 24 |
Finished | Aug 27 12:57:31 AM UTC 24 |
Peak memory | 154660 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3020660756 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 331.prim_prince_test.3020660756 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/331.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/332.prim_prince_test.3656799987 |
Short name | T326 |
Test name | |
Test status | |
Simulation time | 1359091436 ps |
CPU time | 23.3 seconds |
Started | Aug 27 12:56:20 AM UTC 24 |
Finished | Aug 27 12:56:51 AM UTC 24 |
Peak memory | 154588 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3656799987 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 332.prim_prince_test.3656799987 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/332.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/333.prim_prince_test.756095340 |
Short name | T336 |
Test name | |
Test status | |
Simulation time | 2805644119 ps |
CPU time | 47.22 seconds |
Started | Aug 27 12:56:20 AM UTC 24 |
Finished | Aug 27 12:57:21 AM UTC 24 |
Peak memory | 154664 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=756095340 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 333.prim_prince_test.756095340 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/333.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/334.prim_prince_test.1314511512 |
Short name | T348 |
Test name | |
Test status | |
Simulation time | 3690451203 ps |
CPU time | 61.86 seconds |
Started | Aug 27 12:56:31 AM UTC 24 |
Finished | Aug 27 12:57:51 AM UTC 24 |
Peak memory | 156524 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1314511512 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 334.prim_prince_test.1314511512 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/334.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/335.prim_prince_test.1901806793 |
Short name | T333 |
Test name | |
Test status | |
Simulation time | 1287490689 ps |
CPU time | 21.71 seconds |
Started | Aug 27 12:56:31 AM UTC 24 |
Finished | Aug 27 12:57:00 AM UTC 24 |
Peak memory | 154592 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1901806793 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 335.prim_prince_test.1901806793 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/335.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/336.prim_prince_test.4173393864 |
Short name | T329 |
Test name | |
Test status | |
Simulation time | 841874986 ps |
CPU time | 14.6 seconds |
Started | Aug 27 12:56:33 AM UTC 24 |
Finished | Aug 27 12:56:52 AM UTC 24 |
Peak memory | 154344 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4173393864 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 336.prim_prince_test.4173393864 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/336.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/337.prim_prince_test.1894810809 |
Short name | T343 |
Test name | |
Test status | |
Simulation time | 2667777657 ps |
CPU time | 45.12 seconds |
Started | Aug 27 12:56:33 AM UTC 24 |
Finished | Aug 27 12:57:31 AM UTC 24 |
Peak memory | 154656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1894810809 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 337.prim_prince_test.1894810809 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/337.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/338.prim_prince_test.3107987210 |
Short name | T332 |
Test name | |
Test status | |
Simulation time | 1147100721 ps |
CPU time | 19.31 seconds |
Started | Aug 27 12:56:34 AM UTC 24 |
Finished | Aug 27 12:56:59 AM UTC 24 |
Peak memory | 156048 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3107987210 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 338.prim_prince_test.3107987210 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/338.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/339.prim_prince_test.3629328798 |
Short name | T341 |
Test name | |
Test status | |
Simulation time | 2465733705 ps |
CPU time | 41.44 seconds |
Started | Aug 27 12:56:35 AM UTC 24 |
Finished | Aug 27 12:57:29 AM UTC 24 |
Peak memory | 154656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3629328798 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 339.prim_prince_test.3629328798 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/339.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/34.prim_prince_test.2651412635 |
Short name | T34 |
Test name | |
Test status | |
Simulation time | 1867180391 ps |
CPU time | 32.09 seconds |
Started | Aug 27 12:40:32 AM UTC 24 |
Finished | Aug 27 12:41:14 AM UTC 24 |
Peak memory | 154600 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2651412635 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 34.prim_prince_test.2651412635 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/34.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/340.prim_prince_test.87713502 |
Short name | T339 |
Test name | |
Test status | |
Simulation time | 1931020588 ps |
CPU time | 32.29 seconds |
Started | Aug 27 12:56:45 AM UTC 24 |
Finished | Aug 27 12:57:27 AM UTC 24 |
Peak memory | 154592 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=87713502 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 340.prim_prince_test.87713502 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/340.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/341.prim_prince_test.2218346206 |
Short name | T337 |
Test name | |
Test status | |
Simulation time | 1631716891 ps |
CPU time | 27.34 seconds |
Started | Aug 27 12:56:50 AM UTC 24 |
Finished | Aug 27 12:57:26 AM UTC 24 |
Peak memory | 154592 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2218346206 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 341.prim_prince_test.2218346206 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/341.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/342.prim_prince_test.4024542564 |
Short name | T342 |
Test name | |
Test status | |
Simulation time | 1738750673 ps |
CPU time | 29.19 seconds |
Started | Aug 27 12:56:52 AM UTC 24 |
Finished | Aug 27 12:57:30 AM UTC 24 |
Peak memory | 154592 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4024542564 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 342.prim_prince_test.4024542564 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/342.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/343.prim_prince_test.742238141 |
Short name | T357 |
Test name | |
Test status | |
Simulation time | 3732299743 ps |
CPU time | 62.08 seconds |
Started | Aug 27 12:56:52 AM UTC 24 |
Finished | Aug 27 12:58:12 AM UTC 24 |
Peak memory | 156532 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=742238141 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 343.prim_prince_test.742238141 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/343.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/344.prim_prince_test.1543424240 |
Short name | T355 |
Test name | |
Test status | |
Simulation time | 3600362272 ps |
CPU time | 59.95 seconds |
Started | Aug 27 12:56:52 AM UTC 24 |
Finished | Aug 27 12:58:09 AM UTC 24 |
Peak memory | 154656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1543424240 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 344.prim_prince_test.1543424240 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/344.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/345.prim_prince_test.3084530485 |
Short name | T346 |
Test name | |
Test status | |
Simulation time | 2398577635 ps |
CPU time | 39.99 seconds |
Started | Aug 27 12:56:54 AM UTC 24 |
Finished | Aug 27 12:57:45 AM UTC 24 |
Peak memory | 154656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3084530485 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 345.prim_prince_test.3084530485 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/345.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/346.prim_prince_test.146608380 |
Short name | T345 |
Test name | |
Test status | |
Simulation time | 2287739655 ps |
CPU time | 38.46 seconds |
Started | Aug 27 12:56:54 AM UTC 24 |
Finished | Aug 27 12:57:43 AM UTC 24 |
Peak memory | 154660 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=146608380 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 346.prim_prince_test.146608380 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/346.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/347.prim_prince_test.3687080079 |
Short name | T350 |
Test name | |
Test status | |
Simulation time | 2794322826 ps |
CPU time | 46.53 seconds |
Started | Aug 27 12:56:54 AM UTC 24 |
Finished | Aug 27 12:57:54 AM UTC 24 |
Peak memory | 154656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3687080079 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 347.prim_prince_test.3687080079 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/347.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/348.prim_prince_test.3334762335 |
Short name | T340 |
Test name | |
Test status | |
Simulation time | 1415047432 ps |
CPU time | 24.02 seconds |
Started | Aug 27 12:56:57 AM UTC 24 |
Finished | Aug 27 12:57:28 AM UTC 24 |
Peak memory | 154592 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3334762335 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 348.prim_prince_test.3334762335 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/348.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/349.prim_prince_test.989549789 |
Short name | T347 |
Test name | |
Test status | |
Simulation time | 2173007199 ps |
CPU time | 36.47 seconds |
Started | Aug 27 12:56:58 AM UTC 24 |
Finished | Aug 27 12:57:45 AM UTC 24 |
Peak memory | 154664 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=989549789 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 349.prim_prince_test.989549789 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/349.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/35.prim_prince_test.3334041539 |
Short name | T38 |
Test name | |
Test status | |
Simulation time | 2513156395 ps |
CPU time | 42.88 seconds |
Started | Aug 27 12:40:33 AM UTC 24 |
Finished | Aug 27 12:41:29 AM UTC 24 |
Peak memory | 154664 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3334041539 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 35.prim_prince_test.3334041539 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/35.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/350.prim_prince_test.1373703406 |
Short name | T349 |
Test name | |
Test status | |
Simulation time | 2341033824 ps |
CPU time | 38.97 seconds |
Started | Aug 27 12:57:01 AM UTC 24 |
Finished | Aug 27 12:57:51 AM UTC 24 |
Peak memory | 154656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1373703406 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 350.prim_prince_test.1373703406 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/350.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/351.prim_prince_test.1381012499 |
Short name | T338 |
Test name | |
Test status | |
Simulation time | 1116533440 ps |
CPU time | 19 seconds |
Started | Aug 27 12:57:01 AM UTC 24 |
Finished | Aug 27 12:57:26 AM UTC 24 |
Peak memory | 154592 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1381012499 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 351.prim_prince_test.1381012499 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/351.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/352.prim_prince_test.176742488 |
Short name | T356 |
Test name | |
Test status | |
Simulation time | 2484693811 ps |
CPU time | 41.61 seconds |
Started | Aug 27 12:57:16 AM UTC 24 |
Finished | Aug 27 12:58:10 AM UTC 24 |
Peak memory | 154664 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=176742488 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 352.prim_prince_test.176742488 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/352.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/353.prim_prince_test.2551169528 |
Short name | T360 |
Test name | |
Test status | |
Simulation time | 2814593630 ps |
CPU time | 47.38 seconds |
Started | Aug 27 12:57:23 AM UTC 24 |
Finished | Aug 27 12:58:24 AM UTC 24 |
Peak memory | 156524 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2551169528 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 353.prim_prince_test.2551169528 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/353.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/354.prim_prince_test.445142278 |
Short name | T354 |
Test name | |
Test status | |
Simulation time | 2042990697 ps |
CPU time | 34.05 seconds |
Started | Aug 27 12:57:23 AM UTC 24 |
Finished | Aug 27 12:58:08 AM UTC 24 |
Peak memory | 154600 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=445142278 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 354.prim_prince_test.445142278 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/354.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/355.prim_prince_test.4032133730 |
Short name | T352 |
Test name | |
Test status | |
Simulation time | 1532961678 ps |
CPU time | 26.02 seconds |
Started | Aug 27 12:57:26 AM UTC 24 |
Finished | Aug 27 12:58:00 AM UTC 24 |
Peak memory | 154592 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4032133730 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 355.prim_prince_test.4032133730 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/355.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/356.prim_prince_test.2375440300 |
Short name | T368 |
Test name | |
Test status | |
Simulation time | 3565293451 ps |
CPU time | 59.37 seconds |
Started | Aug 27 12:57:28 AM UTC 24 |
Finished | Aug 27 12:58:44 AM UTC 24 |
Peak memory | 156524 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2375440300 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 356.prim_prince_test.2375440300 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/356.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/357.prim_prince_test.2044157682 |
Short name | T365 |
Test name | |
Test status | |
Simulation time | 3290538102 ps |
CPU time | 54.74 seconds |
Started | Aug 27 12:57:28 AM UTC 24 |
Finished | Aug 27 12:58:39 AM UTC 24 |
Peak memory | 154656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2044157682 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 357.prim_prince_test.2044157682 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/357.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/358.prim_prince_test.2883034954 |
Short name | T353 |
Test name | |
Test status | |
Simulation time | 1656989057 ps |
CPU time | 27.91 seconds |
Started | Aug 27 12:57:29 AM UTC 24 |
Finished | Aug 27 12:58:05 AM UTC 24 |
Peak memory | 154588 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2883034954 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 358.prim_prince_test.2883034954 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/358.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/359.prim_prince_test.919104420 |
Short name | T362 |
Test name | |
Test status | |
Simulation time | 2602943906 ps |
CPU time | 44.12 seconds |
Started | Aug 27 12:57:31 AM UTC 24 |
Finished | Aug 27 12:58:28 AM UTC 24 |
Peak memory | 154664 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=919104420 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 359.prim_prince_test.919104420 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/359.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/36.prim_prince_test.4026804831 |
Short name | T40 |
Test name | |
Test status | |
Simulation time | 2899233976 ps |
CPU time | 50.16 seconds |
Started | Aug 27 12:40:36 AM UTC 24 |
Finished | Aug 27 12:41:41 AM UTC 24 |
Peak memory | 154664 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4026804831 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 36.prim_prince_test.4026804831 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/36.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/360.prim_prince_test.100435399 |
Short name | T351 |
Test name | |
Test status | |
Simulation time | 1127540982 ps |
CPU time | 19.33 seconds |
Started | Aug 27 12:57:31 AM UTC 24 |
Finished | Aug 27 12:57:56 AM UTC 24 |
Peak memory | 154600 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=100435399 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 360.prim_prince_test.100435399 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/360.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/361.prim_prince_test.3534145351 |
Short name | T367 |
Test name | |
Test status | |
Simulation time | 3234273750 ps |
CPU time | 54.16 seconds |
Started | Aug 27 12:57:32 AM UTC 24 |
Finished | Aug 27 12:58:43 AM UTC 24 |
Peak memory | 154656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3534145351 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 361.prim_prince_test.3534145351 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/361.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/362.prim_prince_test.2495704597 |
Short name | T369 |
Test name | |
Test status | |
Simulation time | 3654857304 ps |
CPU time | 60.85 seconds |
Started | Aug 27 12:57:32 AM UTC 24 |
Finished | Aug 27 12:58:51 AM UTC 24 |
Peak memory | 154656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2495704597 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 362.prim_prince_test.2495704597 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/362.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/363.prim_prince_test.4132657872 |
Short name | T373 |
Test name | |
Test status | |
Simulation time | 3428667374 ps |
CPU time | 57.73 seconds |
Started | Aug 27 12:57:45 AM UTC 24 |
Finished | Aug 27 12:58:59 AM UTC 24 |
Peak memory | 154660 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4132657872 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 363.prim_prince_test.4132657872 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/363.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/364.prim_prince_test.1339719561 |
Short name | T358 |
Test name | |
Test status | |
Simulation time | 1720123040 ps |
CPU time | 28.65 seconds |
Started | Aug 27 12:57:46 AM UTC 24 |
Finished | Aug 27 12:58:24 AM UTC 24 |
Peak memory | 154396 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1339719561 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 364.prim_prince_test.1339719561 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/364.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/365.prim_prince_test.3633173573 |
Short name | T375 |
Test name | |
Test status | |
Simulation time | 3454274665 ps |
CPU time | 58.07 seconds |
Started | Aug 27 12:57:46 AM UTC 24 |
Finished | Aug 27 12:59:01 AM UTC 24 |
Peak memory | 154512 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3633173573 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 365.prim_prince_test.3633173573 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/365.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/366.prim_prince_test.732408050 |
Short name | T366 |
Test name | |
Test status | |
Simulation time | 2276463247 ps |
CPU time | 37.9 seconds |
Started | Aug 27 12:57:52 AM UTC 24 |
Finished | Aug 27 12:58:41 AM UTC 24 |
Peak memory | 154632 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=732408050 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 366.prim_prince_test.732408050 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/366.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/367.prim_prince_test.1724378543 |
Short name | T359 |
Test name | |
Test status | |
Simulation time | 1455707523 ps |
CPU time | 24.59 seconds |
Started | Aug 27 12:57:52 AM UTC 24 |
Finished | Aug 27 12:58:24 AM UTC 24 |
Peak memory | 154596 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1724378543 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 367.prim_prince_test.1724378543 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/367.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/368.prim_prince_test.706942285 |
Short name | T363 |
Test name | |
Test status | |
Simulation time | 1769983717 ps |
CPU time | 29.58 seconds |
Started | Aug 27 12:57:55 AM UTC 24 |
Finished | Aug 27 12:58:34 AM UTC 24 |
Peak memory | 154600 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=706942285 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 368.prim_prince_test.706942285 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/368.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/369.prim_prince_test.5238307 |
Short name | T361 |
Test name | |
Test status | |
Simulation time | 1373639206 ps |
CPU time | 22.98 seconds |
Started | Aug 27 12:57:58 AM UTC 24 |
Finished | Aug 27 12:58:28 AM UTC 24 |
Peak memory | 154604 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5238307 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 369.prim_prince_test.5238307 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/369.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/37.prim_prince_test.3113142214 |
Short name | T44 |
Test name | |
Test status | |
Simulation time | 3579055028 ps |
CPU time | 60.73 seconds |
Started | Aug 27 12:40:37 AM UTC 24 |
Finished | Aug 27 12:41:56 AM UTC 24 |
Peak memory | 154664 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3113142214 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 37.prim_prince_test.3113142214 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/37.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/370.prim_prince_test.4187380434 |
Short name | T374 |
Test name | |
Test status | |
Simulation time | 2731053786 ps |
CPU time | 46.19 seconds |
Started | Aug 27 12:58:01 AM UTC 24 |
Finished | Aug 27 12:59:01 AM UTC 24 |
Peak memory | 154664 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4187380434 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 370.prim_prince_test.4187380434 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/370.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/371.prim_prince_test.3461031649 |
Short name | T381 |
Test name | |
Test status | |
Simulation time | 3363480502 ps |
CPU time | 56.2 seconds |
Started | Aug 27 12:58:06 AM UTC 24 |
Finished | Aug 27 12:59:19 AM UTC 24 |
Peak memory | 156532 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3461031649 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 371.prim_prince_test.3461031649 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/371.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/372.prim_prince_test.880771507 |
Short name | T372 |
Test name | |
Test status | |
Simulation time | 2150549254 ps |
CPU time | 36.07 seconds |
Started | Aug 27 12:58:09 AM UTC 24 |
Finished | Aug 27 12:58:56 AM UTC 24 |
Peak memory | 156120 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=880771507 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 372.prim_prince_test.880771507 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/372.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/373.prim_prince_test.1077065894 |
Short name | T382 |
Test name | |
Test status | |
Simulation time | 3260108782 ps |
CPU time | 54.14 seconds |
Started | Aug 27 12:58:10 AM UTC 24 |
Finished | Aug 27 12:59:20 AM UTC 24 |
Peak memory | 154664 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1077065894 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 373.prim_prince_test.1077065894 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/373.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/374.prim_prince_test.1232687923 |
Short name | T376 |
Test name | |
Test status | |
Simulation time | 2450534606 ps |
CPU time | 40.76 seconds |
Started | Aug 27 12:58:11 AM UTC 24 |
Finished | Aug 27 12:59:04 AM UTC 24 |
Peak memory | 154660 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1232687923 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 374.prim_prince_test.1232687923 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/374.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/375.prim_prince_test.569085242 |
Short name | T364 |
Test name | |
Test status | |
Simulation time | 1037494154 ps |
CPU time | 17.56 seconds |
Started | Aug 27 12:58:13 AM UTC 24 |
Finished | Aug 27 12:58:36 AM UTC 24 |
Peak memory | 154596 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=569085242 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 375.prim_prince_test.569085242 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/375.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/376.prim_prince_test.3076034239 |
Short name | T371 |
Test name | |
Test status | |
Simulation time | 1244777059 ps |
CPU time | 21.12 seconds |
Started | Aug 27 12:58:26 AM UTC 24 |
Finished | Aug 27 12:58:53 AM UTC 24 |
Peak memory | 154600 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3076034239 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 376.prim_prince_test.3076034239 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/376.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/377.prim_prince_test.3060936457 |
Short name | T384 |
Test name | |
Test status | |
Simulation time | 2731503723 ps |
CPU time | 45.77 seconds |
Started | Aug 27 12:58:26 AM UTC 24 |
Finished | Aug 27 12:59:25 AM UTC 24 |
Peak memory | 154676 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3060936457 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 377.prim_prince_test.3060936457 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/377.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/378.prim_prince_test.3685466857 |
Short name | T388 |
Test name | |
Test status | |
Simulation time | 3340990388 ps |
CPU time | 55.72 seconds |
Started | Aug 27 12:58:26 AM UTC 24 |
Finished | Aug 27 12:59:38 AM UTC 24 |
Peak memory | 154668 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3685466857 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 378.prim_prince_test.3685466857 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/378.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/379.prim_prince_test.3714180216 |
Short name | T389 |
Test name | |
Test status | |
Simulation time | 3487349775 ps |
CPU time | 58.28 seconds |
Started | Aug 27 12:58:29 AM UTC 24 |
Finished | Aug 27 12:59:45 AM UTC 24 |
Peak memory | 154660 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3714180216 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 379.prim_prince_test.3714180216 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/379.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/38.prim_prince_test.2989158810 |
Short name | T35 |
Test name | |
Test status | |
Simulation time | 1879074231 ps |
CPU time | 31.87 seconds |
Started | Aug 27 12:40:41 AM UTC 24 |
Finished | Aug 27 12:41:23 AM UTC 24 |
Peak memory | 154600 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2989158810 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 38.prim_prince_test.2989158810 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/38.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/380.prim_prince_test.1553369878 |
Short name | T377 |
Test name | |
Test status | |
Simulation time | 1657083834 ps |
CPU time | 28.46 seconds |
Started | Aug 27 12:58:29 AM UTC 24 |
Finished | Aug 27 12:59:06 AM UTC 24 |
Peak memory | 154600 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1553369878 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 380.prim_prince_test.1553369878 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/380.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/381.prim_prince_test.1852364051 |
Short name | T370 |
Test name | |
Test status | |
Simulation time | 810151697 ps |
CPU time | 13.81 seconds |
Started | Aug 27 12:58:35 AM UTC 24 |
Finished | Aug 27 12:58:53 AM UTC 24 |
Peak memory | 154600 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1852364051 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 381.prim_prince_test.1852364051 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/381.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/382.prim_prince_test.2115286922 |
Short name | T379 |
Test name | |
Test status | |
Simulation time | 1632509303 ps |
CPU time | 27.76 seconds |
Started | Aug 27 12:58:37 AM UTC 24 |
Finished | Aug 27 12:59:13 AM UTC 24 |
Peak memory | 154600 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2115286922 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 382.prim_prince_test.2115286922 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/382.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/383.prim_prince_test.695596252 |
Short name | T387 |
Test name | |
Test status | |
Simulation time | 2623002425 ps |
CPU time | 43.9 seconds |
Started | Aug 27 12:58:39 AM UTC 24 |
Finished | Aug 27 12:59:36 AM UTC 24 |
Peak memory | 154664 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=695596252 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 383.prim_prince_test.695596252 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/383.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/384.prim_prince_test.3115611121 |
Short name | T380 |
Test name | |
Test status | |
Simulation time | 1477954924 ps |
CPU time | 24.96 seconds |
Started | Aug 27 12:58:42 AM UTC 24 |
Finished | Aug 27 12:59:14 AM UTC 24 |
Peak memory | 154600 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3115611121 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 384.prim_prince_test.3115611121 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/384.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/385.prim_prince_test.2424984139 |
Short name | T378 |
Test name | |
Test status | |
Simulation time | 1254570415 ps |
CPU time | 21.29 seconds |
Started | Aug 27 12:58:43 AM UTC 24 |
Finished | Aug 27 12:59:11 AM UTC 24 |
Peak memory | 154600 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2424984139 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 385.prim_prince_test.2424984139 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/385.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/386.prim_prince_test.745924589 |
Short name | T391 |
Test name | |
Test status | |
Simulation time | 3279824284 ps |
CPU time | 54.9 seconds |
Started | Aug 27 12:58:45 AM UTC 24 |
Finished | Aug 27 12:59:56 AM UTC 24 |
Peak memory | 156532 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=745924589 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 386.prim_prince_test.745924589 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/386.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/387.prim_prince_test.3289994823 |
Short name | T398 |
Test name | |
Test status | |
Simulation time | 3639507245 ps |
CPU time | 60.8 seconds |
Started | Aug 27 12:58:52 AM UTC 24 |
Finished | Aug 27 01:00:10 AM UTC 24 |
Peak memory | 154668 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3289994823 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 387.prim_prince_test.3289994823 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/387.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/388.prim_prince_test.207821665 |
Short name | T385 |
Test name | |
Test status | |
Simulation time | 1596406378 ps |
CPU time | 26.92 seconds |
Started | Aug 27 12:58:54 AM UTC 24 |
Finished | Aug 27 12:59:30 AM UTC 24 |
Peak memory | 154600 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=207821665 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 388.prim_prince_test.207821665 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/388.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/389.prim_prince_test.2401939207 |
Short name | T386 |
Test name | |
Test status | |
Simulation time | 1823653488 ps |
CPU time | 30.4 seconds |
Started | Aug 27 12:58:54 AM UTC 24 |
Finished | Aug 27 12:59:34 AM UTC 24 |
Peak memory | 154596 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2401939207 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 389.prim_prince_test.2401939207 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/389.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/39.prim_prince_test.3758821186 |
Short name | T42 |
Test name | |
Test status | |
Simulation time | 2996786370 ps |
CPU time | 51.59 seconds |
Started | Aug 27 12:40:44 AM UTC 24 |
Finished | Aug 27 12:41:51 AM UTC 24 |
Peak memory | 154664 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3758821186 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 39.prim_prince_test.3758821186 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/39.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/390.prim_prince_test.2443666090 |
Short name | T390 |
Test name | |
Test status | |
Simulation time | 2489886170 ps |
CPU time | 41.75 seconds |
Started | Aug 27 12:58:57 AM UTC 24 |
Finished | Aug 27 12:59:51 AM UTC 24 |
Peak memory | 154664 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2443666090 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 390.prim_prince_test.2443666090 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/390.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/391.prim_prince_test.1197658561 |
Short name | T383 |
Test name | |
Test status | |
Simulation time | 992379094 ps |
CPU time | 16.93 seconds |
Started | Aug 27 12:59:00 AM UTC 24 |
Finished | Aug 27 12:59:23 AM UTC 24 |
Peak memory | 154600 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1197658561 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 391.prim_prince_test.1197658561 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/391.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/392.prim_prince_test.3166432629 |
Short name | T399 |
Test name | |
Test status | |
Simulation time | 3193963649 ps |
CPU time | 53.89 seconds |
Started | Aug 27 12:59:02 AM UTC 24 |
Finished | Aug 27 01:00:11 AM UTC 24 |
Peak memory | 154672 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3166432629 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 392.prim_prince_test.3166432629 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/392.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/393.prim_prince_test.3383480120 |
Short name | T393 |
Test name | |
Test status | |
Simulation time | 2637012036 ps |
CPU time | 43.89 seconds |
Started | Aug 27 12:59:03 AM UTC 24 |
Finished | Aug 27 01:00:00 AM UTC 24 |
Peak memory | 154664 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3383480120 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 393.prim_prince_test.3383480120 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/393.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/394.prim_prince_test.760890324 |
Short name | T401 |
Test name | |
Test status | |
Simulation time | 3519652136 ps |
CPU time | 58.55 seconds |
Started | Aug 27 12:59:05 AM UTC 24 |
Finished | Aug 27 01:00:21 AM UTC 24 |
Peak memory | 154668 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=760890324 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 394.prim_prince_test.760890324 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/394.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/395.prim_prince_test.2109224867 |
Short name | T405 |
Test name | |
Test status | |
Simulation time | 3711465781 ps |
CPU time | 61.94 seconds |
Started | Aug 27 12:59:08 AM UTC 24 |
Finished | Aug 27 01:00:28 AM UTC 24 |
Peak memory | 154668 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2109224867 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 395.prim_prince_test.2109224867 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/395.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/396.prim_prince_test.526393603 |
Short name | T397 |
Test name | |
Test status | |
Simulation time | 2614435394 ps |
CPU time | 44.03 seconds |
Started | Aug 27 12:59:12 AM UTC 24 |
Finished | Aug 27 01:00:09 AM UTC 24 |
Peak memory | 154664 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=526393603 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 396.prim_prince_test.526393603 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/396.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/397.prim_prince_test.3370350279 |
Short name | T400 |
Test name | |
Test status | |
Simulation time | 2977708912 ps |
CPU time | 49.98 seconds |
Started | Aug 27 12:59:14 AM UTC 24 |
Finished | Aug 27 01:00:19 AM UTC 24 |
Peak memory | 154664 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3370350279 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 397.prim_prince_test.3370350279 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/397.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/398.prim_prince_test.1508046842 |
Short name | T392 |
Test name | |
Test status | |
Simulation time | 1941292783 ps |
CPU time | 32.86 seconds |
Started | Aug 27 12:59:16 AM UTC 24 |
Finished | Aug 27 12:59:58 AM UTC 24 |
Peak memory | 154592 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1508046842 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 398.prim_prince_test.1508046842 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/398.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/399.prim_prince_test.2495969262 |
Short name | T396 |
Test name | |
Test status | |
Simulation time | 1923202277 ps |
CPU time | 32.37 seconds |
Started | Aug 27 12:59:20 AM UTC 24 |
Finished | Aug 27 01:00:02 AM UTC 24 |
Peak memory | 154592 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2495969262 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 399.prim_prince_test.2495969262 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/399.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/4.prim_prince_test.1306440523 |
Short name | T5 |
Test name | |
Test status | |
Simulation time | 1607957620 ps |
CPU time | 28.16 seconds |
Started | Aug 27 12:37:58 AM UTC 24 |
Finished | Aug 27 12:38:34 AM UTC 24 |
Peak memory | 154600 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1306440523 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 4.prim_prince_test.1306440523 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/4.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/40.prim_prince_test.2777720120 |
Short name | T45 |
Test name | |
Test status | |
Simulation time | 3113107635 ps |
CPU time | 53.5 seconds |
Started | Aug 27 12:40:50 AM UTC 24 |
Finished | Aug 27 12:41:59 AM UTC 24 |
Peak memory | 154664 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2777720120 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 40.prim_prince_test.2777720120 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/40.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/400.prim_prince_test.3120683322 |
Short name | T404 |
Test name | |
Test status | |
Simulation time | 3010694839 ps |
CPU time | 50.71 seconds |
Started | Aug 27 12:59:21 AM UTC 24 |
Finished | Aug 27 01:00:27 AM UTC 24 |
Peak memory | 154656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3120683322 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 400.prim_prince_test.3120683322 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/400.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/401.prim_prince_test.131502142 |
Short name | T395 |
Test name | |
Test status | |
Simulation time | 1663766832 ps |
CPU time | 28.14 seconds |
Started | Aug 27 12:59:24 AM UTC 24 |
Finished | Aug 27 01:00:00 AM UTC 24 |
Peak memory | 154600 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=131502142 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 401.prim_prince_test.131502142 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/401.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/402.prim_prince_test.2605995018 |
Short name | T409 |
Test name | |
Test status | |
Simulation time | 3517538743 ps |
CPU time | 58.96 seconds |
Started | Aug 27 12:59:26 AM UTC 24 |
Finished | Aug 27 01:00:42 AM UTC 24 |
Peak memory | 154660 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2605995018 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 402.prim_prince_test.2605995018 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/402.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/403.prim_prince_test.2449416130 |
Short name | T410 |
Test name | |
Test status | |
Simulation time | 3269020042 ps |
CPU time | 54.95 seconds |
Started | Aug 27 12:59:31 AM UTC 24 |
Finished | Aug 27 01:00:42 AM UTC 24 |
Peak memory | 154656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2449416130 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 403.prim_prince_test.2449416130 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/403.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/404.prim_prince_test.515997000 |
Short name | T415 |
Test name | |
Test status | |
Simulation time | 3342477889 ps |
CPU time | 56.01 seconds |
Started | Aug 27 12:59:36 AM UTC 24 |
Finished | Aug 27 01:00:48 AM UTC 24 |
Peak memory | 154668 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=515997000 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 404.prim_prince_test.515997000 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/404.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/405.prim_prince_test.25610944 |
Short name | T403 |
Test name | |
Test status | |
Simulation time | 2197155192 ps |
CPU time | 37.15 seconds |
Started | Aug 27 12:59:37 AM UTC 24 |
Finished | Aug 27 01:00:25 AM UTC 24 |
Peak memory | 154664 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25610944 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 405.prim_prince_test.25610944 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/405.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/406.prim_prince_test.515534374 |
Short name | T408 |
Test name | |
Test status | |
Simulation time | 2630233556 ps |
CPU time | 44.21 seconds |
Started | Aug 27 12:59:38 AM UTC 24 |
Finished | Aug 27 01:00:36 AM UTC 24 |
Peak memory | 154664 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=515534374 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 406.prim_prince_test.515534374 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/406.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/407.prim_prince_test.928338440 |
Short name | T402 |
Test name | |
Test status | |
Simulation time | 1631249393 ps |
CPU time | 27.59 seconds |
Started | Aug 27 12:59:46 AM UTC 24 |
Finished | Aug 27 01:00:22 AM UTC 24 |
Peak memory | 154600 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=928338440 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 407.prim_prince_test.928338440 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/407.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/408.prim_prince_test.1773171501 |
Short name | T416 |
Test name | |
Test status | |
Simulation time | 2754181190 ps |
CPU time | 45.92 seconds |
Started | Aug 27 12:59:52 AM UTC 24 |
Finished | Aug 27 01:00:52 AM UTC 24 |
Peak memory | 154656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1773171501 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 408.prim_prince_test.1773171501 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/408.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/409.prim_prince_test.682175862 |
Short name | T420 |
Test name | |
Test status | |
Simulation time | 3249582451 ps |
CPU time | 54.15 seconds |
Started | Aug 27 12:59:58 AM UTC 24 |
Finished | Aug 27 01:01:08 AM UTC 24 |
Peak memory | 156532 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=682175862 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 409.prim_prince_test.682175862 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/409.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/41.prim_prince_test.1690876304 |
Short name | T39 |
Test name | |
Test status | |
Simulation time | 1840316220 ps |
CPU time | 31.72 seconds |
Started | Aug 27 12:40:57 AM UTC 24 |
Finished | Aug 27 12:41:38 AM UTC 24 |
Peak memory | 154600 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1690876304 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 41.prim_prince_test.1690876304 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/41.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/410.prim_prince_test.806959801 |
Short name | T411 |
Test name | |
Test status | |
Simulation time | 1983799132 ps |
CPU time | 33.56 seconds |
Started | Aug 27 12:59:59 AM UTC 24 |
Finished | Aug 27 01:00:43 AM UTC 24 |
Peak memory | 154600 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=806959801 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 410.prim_prince_test.806959801 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/410.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/411.prim_prince_test.1379048325 |
Short name | T407 |
Test name | |
Test status | |
Simulation time | 1284195110 ps |
CPU time | 21.92 seconds |
Started | Aug 27 01:00:00 AM UTC 24 |
Finished | Aug 27 01:00:33 AM UTC 24 |
Peak memory | 154592 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1379048325 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 411.prim_prince_test.1379048325 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/411.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/412.prim_prince_test.268540236 |
Short name | T406 |
Test name | |
Test status | |
Simulation time | 1041601985 ps |
CPU time | 17.74 seconds |
Started | Aug 27 01:00:02 AM UTC 24 |
Finished | Aug 27 01:00:28 AM UTC 24 |
Peak memory | 156056 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=268540236 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 412.prim_prince_test.268540236 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/412.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/413.prim_prince_test.3957020679 |
Short name | T429 |
Test name | |
Test status | |
Simulation time | 3683339827 ps |
CPU time | 61.54 seconds |
Started | Aug 27 01:00:06 AM UTC 24 |
Finished | Aug 27 01:01:25 AM UTC 24 |
Peak memory | 154656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3957020679 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 413.prim_prince_test.3957020679 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/413.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/414.prim_prince_test.542407568 |
Short name | T414 |
Test name | |
Test status | |
Simulation time | 1691923348 ps |
CPU time | 28.76 seconds |
Started | Aug 27 01:00:09 AM UTC 24 |
Finished | Aug 27 01:00:47 AM UTC 24 |
Peak memory | 154600 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=542407568 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 414.prim_prince_test.542407568 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/414.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/415.prim_prince_test.873209812 |
Short name | T423 |
Test name | |
Test status | |
Simulation time | 2960363647 ps |
CPU time | 49.86 seconds |
Started | Aug 27 01:00:12 AM UTC 24 |
Finished | Aug 27 01:01:17 AM UTC 24 |
Peak memory | 154664 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=873209812 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 415.prim_prince_test.873209812 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/415.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/416.prim_prince_test.2126990786 |
Short name | T427 |
Test name | |
Test status | |
Simulation time | 3233580135 ps |
CPU time | 54.14 seconds |
Started | Aug 27 01:00:12 AM UTC 24 |
Finished | Aug 27 01:01:22 AM UTC 24 |
Peak memory | 154656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2126990786 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 416.prim_prince_test.2126990786 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/416.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/417.prim_prince_test.1284417458 |
Short name | T412 |
Test name | |
Test status | |
Simulation time | 1086214333 ps |
CPU time | 18.46 seconds |
Started | Aug 27 01:00:20 AM UTC 24 |
Finished | Aug 27 01:00:44 AM UTC 24 |
Peak memory | 154588 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1284417458 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 417.prim_prince_test.1284417458 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/417.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/418.prim_prince_test.1147482510 |
Short name | T413 |
Test name | |
Test status | |
Simulation time | 1010610391 ps |
CPU time | 17.16 seconds |
Started | Aug 27 01:00:22 AM UTC 24 |
Finished | Aug 27 01:00:45 AM UTC 24 |
Peak memory | 154592 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1147482510 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 418.prim_prince_test.1147482510 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/418.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/419.prim_prince_test.3546737957 |
Short name | T394 |
Test name | |
Test status | |
Simulation time | 2115304991 ps |
CPU time | 35.41 seconds |
Started | Aug 27 01:00:23 AM UTC 24 |
Finished | Aug 27 01:01:10 AM UTC 24 |
Peak memory | 154592 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3546737957 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 419.prim_prince_test.3546737957 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/419.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/42.prim_prince_test.3689959304 |
Short name | T43 |
Test name | |
Test status | |
Simulation time | 2041215865 ps |
CPU time | 34.85 seconds |
Started | Aug 27 12:41:10 AM UTC 24 |
Finished | Aug 27 12:41:55 AM UTC 24 |
Peak memory | 154600 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3689959304 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 42.prim_prince_test.3689959304 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/42.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/420.prim_prince_test.3102152568 |
Short name | T417 |
Test name | |
Test status | |
Simulation time | 1111575404 ps |
CPU time | 18.65 seconds |
Started | Aug 27 01:00:27 AM UTC 24 |
Finished | Aug 27 01:00:52 AM UTC 24 |
Peak memory | 154592 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3102152568 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 420.prim_prince_test.3102152568 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/420.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/421.prim_prince_test.671838433 |
Short name | T419 |
Test name | |
Test status | |
Simulation time | 1744351572 ps |
CPU time | 29.45 seconds |
Started | Aug 27 01:00:28 AM UTC 24 |
Finished | Aug 27 01:01:07 AM UTC 24 |
Peak memory | 154600 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=671838433 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 421.prim_prince_test.671838433 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/421.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/422.prim_prince_test.2040025562 |
Short name | T441 |
Test name | |
Test status | |
Simulation time | 3641216886 ps |
CPU time | 61.2 seconds |
Started | Aug 27 01:00:30 AM UTC 24 |
Finished | Aug 27 01:01:49 AM UTC 24 |
Peak memory | 154660 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2040025562 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 422.prim_prince_test.2040025562 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/422.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/423.prim_prince_test.477677303 |
Short name | T418 |
Test name | |
Test status | |
Simulation time | 1286305524 ps |
CPU time | 22.05 seconds |
Started | Aug 27 01:00:30 AM UTC 24 |
Finished | Aug 27 01:00:59 AM UTC 24 |
Peak memory | 154600 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=477677303 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 423.prim_prince_test.477677303 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/423.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/424.prim_prince_test.1628932721 |
Short name | T426 |
Test name | |
Test status | |
Simulation time | 2047392450 ps |
CPU time | 34.48 seconds |
Started | Aug 27 01:00:34 AM UTC 24 |
Finished | Aug 27 01:01:19 AM UTC 24 |
Peak memory | 154592 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1628932721 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 424.prim_prince_test.1628932721 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/424.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/425.prim_prince_test.3090851189 |
Short name | T430 |
Test name | |
Test status | |
Simulation time | 2688226661 ps |
CPU time | 45.46 seconds |
Started | Aug 27 01:00:36 AM UTC 24 |
Finished | Aug 27 01:01:35 AM UTC 24 |
Peak memory | 154660 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3090851189 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 425.prim_prince_test.3090851189 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/425.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/426.prim_prince_test.2165334744 |
Short name | T433 |
Test name | |
Test status | |
Simulation time | 2587264252 ps |
CPU time | 43.59 seconds |
Started | Aug 27 01:00:44 AM UTC 24 |
Finished | Aug 27 01:01:40 AM UTC 24 |
Peak memory | 154660 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2165334744 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 426.prim_prince_test.2165334744 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/426.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/427.prim_prince_test.2956644764 |
Short name | T425 |
Test name | |
Test status | |
Simulation time | 1585981174 ps |
CPU time | 26.86 seconds |
Started | Aug 27 01:00:44 AM UTC 24 |
Finished | Aug 27 01:01:19 AM UTC 24 |
Peak memory | 154588 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2956644764 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 427.prim_prince_test.2956644764 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/427.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/428.prim_prince_test.3842750869 |
Short name | T437 |
Test name | |
Test status | |
Simulation time | 2893450949 ps |
CPU time | 48.03 seconds |
Started | Aug 27 01:00:44 AM UTC 24 |
Finished | Aug 27 01:01:46 AM UTC 24 |
Peak memory | 154656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3842750869 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 428.prim_prince_test.3842750869 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/428.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/429.prim_prince_test.918047059 |
Short name | T424 |
Test name | |
Test status | |
Simulation time | 1399201437 ps |
CPU time | 23.5 seconds |
Started | Aug 27 01:00:46 AM UTC 24 |
Finished | Aug 27 01:01:17 AM UTC 24 |
Peak memory | 154596 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=918047059 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 429.prim_prince_test.918047059 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/429.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/43.prim_prince_test.2514918428 |
Short name | T46 |
Test name | |
Test status | |
Simulation time | 2357407459 ps |
CPU time | 40.41 seconds |
Started | Aug 27 12:41:11 AM UTC 24 |
Finished | Aug 27 12:42:03 AM UTC 24 |
Peak memory | 154664 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2514918428 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 43.prim_prince_test.2514918428 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/43.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/430.prim_prince_test.3789258773 |
Short name | T421 |
Test name | |
Test status | |
Simulation time | 1226117774 ps |
CPU time | 20.81 seconds |
Started | Aug 27 01:00:46 AM UTC 24 |
Finished | Aug 27 01:01:14 AM UTC 24 |
Peak memory | 154592 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3789258773 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 430.prim_prince_test.3789258773 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/430.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/431.prim_prince_test.237508942 |
Short name | T422 |
Test name | |
Test status | |
Simulation time | 1246017053 ps |
CPU time | 21.19 seconds |
Started | Aug 27 01:00:48 AM UTC 24 |
Finished | Aug 27 01:01:16 AM UTC 24 |
Peak memory | 154600 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=237508942 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 431.prim_prince_test.237508942 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/431.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/432.prim_prince_test.974049895 |
Short name | T428 |
Test name | |
Test status | |
Simulation time | 1583479829 ps |
CPU time | 26.71 seconds |
Started | Aug 27 01:00:49 AM UTC 24 |
Finished | Aug 27 01:01:24 AM UTC 24 |
Peak memory | 154600 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=974049895 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 432.prim_prince_test.974049895 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/432.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/433.prim_prince_test.3684106720 |
Short name | T445 |
Test name | |
Test status | |
Simulation time | 3341790522 ps |
CPU time | 55.82 seconds |
Started | Aug 27 01:00:53 AM UTC 24 |
Finished | Aug 27 01:02:05 AM UTC 24 |
Peak memory | 156516 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3684106720 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 433.prim_prince_test.3684106720 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/433.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/434.prim_prince_test.1346291633 |
Short name | T450 |
Test name | |
Test status | |
Simulation time | 3701143552 ps |
CPU time | 61.94 seconds |
Started | Aug 27 01:00:53 AM UTC 24 |
Finished | Aug 27 01:02:13 AM UTC 24 |
Peak memory | 154660 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1346291633 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 434.prim_prince_test.1346291633 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/434.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/435.prim_prince_test.2257816834 |
Short name | T443 |
Test name | |
Test status | |
Simulation time | 2647913822 ps |
CPU time | 44.47 seconds |
Started | Aug 27 01:01:00 AM UTC 24 |
Finished | Aug 27 01:01:58 AM UTC 24 |
Peak memory | 154656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2257816834 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 435.prim_prince_test.2257816834 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/435.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/436.prim_prince_test.3572969846 |
Short name | T439 |
Test name | |
Test status | |
Simulation time | 1799775260 ps |
CPU time | 30.31 seconds |
Started | Aug 27 01:01:08 AM UTC 24 |
Finished | Aug 27 01:01:47 AM UTC 24 |
Peak memory | 154592 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3572969846 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 436.prim_prince_test.3572969846 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/436.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/437.prim_prince_test.1566380237 |
Short name | T436 |
Test name | |
Test status | |
Simulation time | 1540582800 ps |
CPU time | 25.96 seconds |
Started | Aug 27 01:01:09 AM UTC 24 |
Finished | Aug 27 01:01:43 AM UTC 24 |
Peak memory | 154592 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1566380237 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 437.prim_prince_test.1566380237 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/437.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/438.prim_prince_test.115413430 |
Short name | T431 |
Test name | |
Test status | |
Simulation time | 1156037467 ps |
CPU time | 19.91 seconds |
Started | Aug 27 01:01:11 AM UTC 24 |
Finished | Aug 27 01:01:37 AM UTC 24 |
Peak memory | 156056 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=115413430 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 438.prim_prince_test.115413430 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/438.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/439.prim_prince_test.1689385881 |
Short name | T440 |
Test name | |
Test status | |
Simulation time | 1516323088 ps |
CPU time | 25.86 seconds |
Started | Aug 27 01:01:15 AM UTC 24 |
Finished | Aug 27 01:01:49 AM UTC 24 |
Peak memory | 154592 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1689385881 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 439.prim_prince_test.1689385881 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/439.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/44.prim_prince_test.2983775078 |
Short name | T51 |
Test name | |
Test status | |
Simulation time | 3579495989 ps |
CPU time | 60.65 seconds |
Started | Aug 27 12:41:15 AM UTC 24 |
Finished | Aug 27 12:42:33 AM UTC 24 |
Peak memory | 154660 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2983775078 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 44.prim_prince_test.2983775078 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/44.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/440.prim_prince_test.2267697138 |
Short name | T432 |
Test name | |
Test status | |
Simulation time | 887428000 ps |
CPU time | 15.3 seconds |
Started | Aug 27 01:01:17 AM UTC 24 |
Finished | Aug 27 01:01:38 AM UTC 24 |
Peak memory | 154592 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2267697138 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 440.prim_prince_test.2267697138 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/440.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/441.prim_prince_test.3600472545 |
Short name | T446 |
Test name | |
Test status | |
Simulation time | 2203707772 ps |
CPU time | 37.32 seconds |
Started | Aug 27 01:01:17 AM UTC 24 |
Finished | Aug 27 01:02:06 AM UTC 24 |
Peak memory | 154656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3600472545 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 441.prim_prince_test.3600472545 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/441.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/442.prim_prince_test.3122879270 |
Short name | T454 |
Test name | |
Test status | |
Simulation time | 2969224118 ps |
CPU time | 49.8 seconds |
Started | Aug 27 01:01:19 AM UTC 24 |
Finished | Aug 27 01:02:23 AM UTC 24 |
Peak memory | 154660 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3122879270 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 442.prim_prince_test.3122879270 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/442.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/443.prim_prince_test.4245226975 |
Short name | T444 |
Test name | |
Test status | |
Simulation time | 2015041452 ps |
CPU time | 33.74 seconds |
Started | Aug 27 01:01:19 AM UTC 24 |
Finished | Aug 27 01:02:03 AM UTC 24 |
Peak memory | 154592 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4245226975 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 443.prim_prince_test.4245226975 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/443.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/444.prim_prince_test.689087813 |
Short name | T434 |
Test name | |
Test status | |
Simulation time | 1011095927 ps |
CPU time | 17.25 seconds |
Started | Aug 27 01:01:19 AM UTC 24 |
Finished | Aug 27 01:01:42 AM UTC 24 |
Peak memory | 154600 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=689087813 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 444.prim_prince_test.689087813 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/444.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/445.prim_prince_test.3467849130 |
Short name | T458 |
Test name | |
Test status | |
Simulation time | 3443196677 ps |
CPU time | 58 seconds |
Started | Aug 27 01:01:21 AM UTC 24 |
Finished | Aug 27 01:02:35 AM UTC 24 |
Peak memory | 154660 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3467849130 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 445.prim_prince_test.3467849130 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/445.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/446.prim_prince_test.1375781065 |
Short name | T435 |
Test name | |
Test status | |
Simulation time | 931678443 ps |
CPU time | 16.05 seconds |
Started | Aug 27 01:01:21 AM UTC 24 |
Finished | Aug 27 01:01:42 AM UTC 24 |
Peak memory | 154592 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1375781065 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 446.prim_prince_test.1375781065 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/446.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/447.prim_prince_test.3948611217 |
Short name | T442 |
Test name | |
Test status | |
Simulation time | 1219705135 ps |
CPU time | 20.74 seconds |
Started | Aug 27 01:01:23 AM UTC 24 |
Finished | Aug 27 01:01:51 AM UTC 24 |
Peak memory | 154592 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3948611217 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 447.prim_prince_test.3948611217 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/447.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/448.prim_prince_test.331687304 |
Short name | T448 |
Test name | |
Test status | |
Simulation time | 2068286708 ps |
CPU time | 34.61 seconds |
Started | Aug 27 01:01:26 AM UTC 24 |
Finished | Aug 27 01:02:11 AM UTC 24 |
Peak memory | 154600 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=331687304 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 448.prim_prince_test.331687304 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/448.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/449.prim_prince_test.418616226 |
Short name | T438 |
Test name | |
Test status | |
Simulation time | 843597546 ps |
CPU time | 14.58 seconds |
Started | Aug 27 01:01:27 AM UTC 24 |
Finished | Aug 27 01:01:47 AM UTC 24 |
Peak memory | 154600 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=418616226 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 449.prim_prince_test.418616226 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/449.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/45.prim_prince_test.941402206 |
Short name | T41 |
Test name | |
Test status | |
Simulation time | 1004223833 ps |
CPU time | 17.52 seconds |
Started | Aug 27 12:41:24 AM UTC 24 |
Finished | Aug 27 12:41:47 AM UTC 24 |
Peak memory | 154600 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=941402206 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 45.prim_prince_test.941402206 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/45.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/450.prim_prince_test.611069983 |
Short name | T453 |
Test name | |
Test status | |
Simulation time | 2124284269 ps |
CPU time | 35.73 seconds |
Started | Aug 27 01:01:37 AM UTC 24 |
Finished | Aug 27 01:02:23 AM UTC 24 |
Peak memory | 154600 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=611069983 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 450.prim_prince_test.611069983 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/450.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/451.prim_prince_test.311484181 |
Short name | T447 |
Test name | |
Test status | |
Simulation time | 1383073164 ps |
CPU time | 23.53 seconds |
Started | Aug 27 01:01:38 AM UTC 24 |
Finished | Aug 27 01:02:09 AM UTC 24 |
Peak memory | 154600 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=311484181 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 451.prim_prince_test.311484181 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/451.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/452.prim_prince_test.1096358802 |
Short name | T457 |
Test name | |
Test status | |
Simulation time | 2531423856 ps |
CPU time | 42.58 seconds |
Started | Aug 27 01:01:38 AM UTC 24 |
Finished | Aug 27 01:02:33 AM UTC 24 |
Peak memory | 154656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1096358802 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 452.prim_prince_test.1096358802 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/452.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/453.prim_prince_test.3368436545 |
Short name | T467 |
Test name | |
Test status | |
Simulation time | 3270580466 ps |
CPU time | 55.16 seconds |
Started | Aug 27 01:01:42 AM UTC 24 |
Finished | Aug 27 01:02:53 AM UTC 24 |
Peak memory | 156524 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3368436545 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 453.prim_prince_test.3368436545 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/453.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/454.prim_prince_test.3847935741 |
Short name | T459 |
Test name | |
Test status | |
Simulation time | 2410026794 ps |
CPU time | 40.79 seconds |
Started | Aug 27 01:01:43 AM UTC 24 |
Finished | Aug 27 01:02:36 AM UTC 24 |
Peak memory | 154656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3847935741 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 454.prim_prince_test.3847935741 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/454.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/455.prim_prince_test.1210477760 |
Short name | T451 |
Test name | |
Test status | |
Simulation time | 1467633045 ps |
CPU time | 24.9 seconds |
Started | Aug 27 01:01:43 AM UTC 24 |
Finished | Aug 27 01:02:16 AM UTC 24 |
Peak memory | 154592 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1210477760 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 455.prim_prince_test.1210477760 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/455.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/456.prim_prince_test.1814152461 |
Short name | T464 |
Test name | |
Test status | |
Simulation time | 2847788861 ps |
CPU time | 47.75 seconds |
Started | Aug 27 01:01:45 AM UTC 24 |
Finished | Aug 27 01:02:47 AM UTC 24 |
Peak memory | 154656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1814152461 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 456.prim_prince_test.1814152461 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/456.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/457.prim_prince_test.2069510226 |
Short name | T449 |
Test name | |
Test status | |
Simulation time | 1089074955 ps |
CPU time | 18.56 seconds |
Started | Aug 27 01:01:48 AM UTC 24 |
Finished | Aug 27 01:02:12 AM UTC 24 |
Peak memory | 154592 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2069510226 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 457.prim_prince_test.2069510226 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/457.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/458.prim_prince_test.1971168229 |
Short name | T456 |
Test name | |
Test status | |
Simulation time | 1948132979 ps |
CPU time | 32.93 seconds |
Started | Aug 27 01:01:48 AM UTC 24 |
Finished | Aug 27 01:02:30 AM UTC 24 |
Peak memory | 154592 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1971168229 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 458.prim_prince_test.1971168229 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/458.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/459.prim_prince_test.663329935 |
Short name | T471 |
Test name | |
Test status | |
Simulation time | 3557753814 ps |
CPU time | 59.72 seconds |
Started | Aug 27 01:01:49 AM UTC 24 |
Finished | Aug 27 01:03:06 AM UTC 24 |
Peak memory | 154668 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=663329935 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 459.prim_prince_test.663329935 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/459.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/46.prim_prince_test.2402724491 |
Short name | T47 |
Test name | |
Test status | |
Simulation time | 2101673496 ps |
CPU time | 35.5 seconds |
Started | Aug 27 12:41:25 AM UTC 24 |
Finished | Aug 27 12:42:11 AM UTC 24 |
Peak memory | 154600 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2402724491 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 46.prim_prince_test.2402724491 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/46.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/460.prim_prince_test.2159296626 |
Short name | T462 |
Test name | |
Test status | |
Simulation time | 2264609915 ps |
CPU time | 37.86 seconds |
Started | Aug 27 01:01:49 AM UTC 24 |
Finished | Aug 27 01:02:39 AM UTC 24 |
Peak memory | 154656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2159296626 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 460.prim_prince_test.2159296626 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/460.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/461.prim_prince_test.2242988653 |
Short name | T460 |
Test name | |
Test status | |
Simulation time | 2079737944 ps |
CPU time | 35.17 seconds |
Started | Aug 27 01:01:51 AM UTC 24 |
Finished | Aug 27 01:02:36 AM UTC 24 |
Peak memory | 154592 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2242988653 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 461.prim_prince_test.2242988653 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/461.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/462.prim_prince_test.2393106675 |
Short name | T455 |
Test name | |
Test status | |
Simulation time | 1676420710 ps |
CPU time | 28.35 seconds |
Started | Aug 27 01:01:52 AM UTC 24 |
Finished | Aug 27 01:02:29 AM UTC 24 |
Peak memory | 154592 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2393106675 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 462.prim_prince_test.2393106675 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/462.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/463.prim_prince_test.312015016 |
Short name | T452 |
Test name | |
Test status | |
Simulation time | 951425537 ps |
CPU time | 16.27 seconds |
Started | Aug 27 01:01:59 AM UTC 24 |
Finished | Aug 27 01:02:20 AM UTC 24 |
Peak memory | 154600 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=312015016 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 463.prim_prince_test.312015016 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/463.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/464.prim_prince_test.3627384529 |
Short name | T473 |
Test name | |
Test status | |
Simulation time | 3045001095 ps |
CPU time | 51.26 seconds |
Started | Aug 27 01:02:04 AM UTC 24 |
Finished | Aug 27 01:03:10 AM UTC 24 |
Peak memory | 154660 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3627384529 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 464.prim_prince_test.3627384529 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/464.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/465.prim_prince_test.2526931247 |
Short name | T463 |
Test name | |
Test status | |
Simulation time | 1661014607 ps |
CPU time | 28.03 seconds |
Started | Aug 27 01:02:06 AM UTC 24 |
Finished | Aug 27 01:02:42 AM UTC 24 |
Peak memory | 154592 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2526931247 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 465.prim_prince_test.2526931247 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/465.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/466.prim_prince_test.2870311066 |
Short name | T474 |
Test name | |
Test status | |
Simulation time | 2976016947 ps |
CPU time | 50.28 seconds |
Started | Aug 27 01:02:07 AM UTC 24 |
Finished | Aug 27 01:03:12 AM UTC 24 |
Peak memory | 154656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2870311066 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 466.prim_prince_test.2870311066 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/466.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/467.prim_prince_test.172660785 |
Short name | T481 |
Test name | |
Test status | |
Simulation time | 3760052821 ps |
CPU time | 63.16 seconds |
Started | Aug 27 01:02:10 AM UTC 24 |
Finished | Aug 27 01:03:31 AM UTC 24 |
Peak memory | 156532 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=172660785 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 467.prim_prince_test.172660785 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/467.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/468.prim_prince_test.3059234852 |
Short name | T461 |
Test name | |
Test status | |
Simulation time | 1119499476 ps |
CPU time | 19.29 seconds |
Started | Aug 27 01:02:12 AM UTC 24 |
Finished | Aug 27 01:02:37 AM UTC 24 |
Peak memory | 154592 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3059234852 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 468.prim_prince_test.3059234852 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/468.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/469.prim_prince_test.415213696 |
Short name | T465 |
Test name | |
Test status | |
Simulation time | 1541312537 ps |
CPU time | 26.17 seconds |
Started | Aug 27 01:02:13 AM UTC 24 |
Finished | Aug 27 01:02:47 AM UTC 24 |
Peak memory | 154600 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=415213696 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 469.prim_prince_test.415213696 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/469.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/47.prim_prince_test.641526940 |
Short name | T53 |
Test name | |
Test status | |
Simulation time | 3406439061 ps |
CPU time | 58.06 seconds |
Started | Aug 27 12:41:26 AM UTC 24 |
Finished | Aug 27 12:42:41 AM UTC 24 |
Peak memory | 154664 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=641526940 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 47.prim_prince_test.641526940 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/47.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/470.prim_prince_test.274293178 |
Short name | T470 |
Test name | |
Test status | |
Simulation time | 2311229818 ps |
CPU time | 39.01 seconds |
Started | Aug 27 01:02:15 AM UTC 24 |
Finished | Aug 27 01:03:05 AM UTC 24 |
Peak memory | 154664 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=274293178 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 470.prim_prince_test.274293178 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/470.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/471.prim_prince_test.882387865 |
Short name | T466 |
Test name | |
Test status | |
Simulation time | 1483307374 ps |
CPU time | 25.58 seconds |
Started | Aug 27 01:02:17 AM UTC 24 |
Finished | Aug 27 01:02:51 AM UTC 24 |
Peak memory | 154600 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=882387865 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 471.prim_prince_test.882387865 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/471.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/472.prim_prince_test.2155456680 |
Short name | T483 |
Test name | |
Test status | |
Simulation time | 3359436856 ps |
CPU time | 56.57 seconds |
Started | Aug 27 01:02:21 AM UTC 24 |
Finished | Aug 27 01:03:34 AM UTC 24 |
Peak memory | 154656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2155456680 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 472.prim_prince_test.2155456680 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/472.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/473.prim_prince_test.1900734860 |
Short name | T475 |
Test name | |
Test status | |
Simulation time | 2252982918 ps |
CPU time | 38.04 seconds |
Started | Aug 27 01:02:24 AM UTC 24 |
Finished | Aug 27 01:03:13 AM UTC 24 |
Peak memory | 154656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1900734860 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 473.prim_prince_test.1900734860 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/473.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/474.prim_prince_test.2553382917 |
Short name | T486 |
Test name | |
Test status | |
Simulation time | 3605864178 ps |
CPU time | 60.99 seconds |
Started | Aug 27 01:02:25 AM UTC 24 |
Finished | Aug 27 01:03:44 AM UTC 24 |
Peak memory | 154656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2553382917 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 474.prim_prince_test.2553382917 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/474.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/475.prim_prince_test.1949479405 |
Short name | T468 |
Test name | |
Test status | |
Simulation time | 1236778085 ps |
CPU time | 21.08 seconds |
Started | Aug 27 01:02:31 AM UTC 24 |
Finished | Aug 27 01:02:59 AM UTC 24 |
Peak memory | 154592 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1949479405 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 475.prim_prince_test.1949479405 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/475.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/476.prim_prince_test.2809741661 |
Short name | T477 |
Test name | |
Test status | |
Simulation time | 2192612046 ps |
CPU time | 37.04 seconds |
Started | Aug 27 01:02:32 AM UTC 24 |
Finished | Aug 27 01:03:20 AM UTC 24 |
Peak memory | 154656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2809741661 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 476.prim_prince_test.2809741661 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/476.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/477.prim_prince_test.1351980369 |
Short name | T479 |
Test name | |
Test status | |
Simulation time | 2384176821 ps |
CPU time | 40.55 seconds |
Started | Aug 27 01:02:34 AM UTC 24 |
Finished | Aug 27 01:03:27 AM UTC 24 |
Peak memory | 154656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1351980369 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 477.prim_prince_test.1351980369 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/477.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/478.prim_prince_test.1416500689 |
Short name | T482 |
Test name | |
Test status | |
Simulation time | 2505768004 ps |
CPU time | 42.45 seconds |
Started | Aug 27 01:02:38 AM UTC 24 |
Finished | Aug 27 01:03:32 AM UTC 24 |
Peak memory | 154656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1416500689 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 478.prim_prince_test.1416500689 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/478.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/479.prim_prince_test.2929200241 |
Short name | T472 |
Test name | |
Test status | |
Simulation time | 1389829548 ps |
CPU time | 23.64 seconds |
Started | Aug 27 01:02:38 AM UTC 24 |
Finished | Aug 27 01:03:09 AM UTC 24 |
Peak memory | 154584 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2929200241 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 479.prim_prince_test.2929200241 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/479.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/48.prim_prince_test.2413412500 |
Short name | T56 |
Test name | |
Test status | |
Simulation time | 3738489521 ps |
CPU time | 63.67 seconds |
Started | Aug 27 12:41:30 AM UTC 24 |
Finished | Aug 27 12:42:52 AM UTC 24 |
Peak memory | 154664 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2413412500 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 48.prim_prince_test.2413412500 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/48.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/480.prim_prince_test.3942891605 |
Short name | T487 |
Test name | |
Test status | |
Simulation time | 3105230441 ps |
CPU time | 52.51 seconds |
Started | Aug 27 01:02:38 AM UTC 24 |
Finished | Aug 27 01:03:45 AM UTC 24 |
Peak memory | 154656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3942891605 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 480.prim_prince_test.3942891605 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/480.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/481.prim_prince_test.4208482667 |
Short name | T489 |
Test name | |
Test status | |
Simulation time | 3485024928 ps |
CPU time | 58.79 seconds |
Started | Aug 27 01:02:39 AM UTC 24 |
Finished | Aug 27 01:03:55 AM UTC 24 |
Peak memory | 154656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4208482667 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 481.prim_prince_test.4208482667 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/481.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/482.prim_prince_test.1921986172 |
Short name | T469 |
Test name | |
Test status | |
Simulation time | 1082976612 ps |
CPU time | 18.72 seconds |
Started | Aug 27 01:02:40 AM UTC 24 |
Finished | Aug 27 01:03:05 AM UTC 24 |
Peak memory | 154588 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1921986172 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 482.prim_prince_test.1921986172 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/482.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/483.prim_prince_test.1781406906 |
Short name | T488 |
Test name | |
Test status | |
Simulation time | 2920199080 ps |
CPU time | 49.94 seconds |
Started | Aug 27 01:02:42 AM UTC 24 |
Finished | Aug 27 01:03:46 AM UTC 24 |
Peak memory | 154656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1781406906 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 483.prim_prince_test.1781406906 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/483.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/484.prim_prince_test.1218404663 |
Short name | T490 |
Test name | |
Test status | |
Simulation time | 3508523157 ps |
CPU time | 59.66 seconds |
Started | Aug 27 01:02:43 AM UTC 24 |
Finished | Aug 27 01:04:00 AM UTC 24 |
Peak memory | 154656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1218404663 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 484.prim_prince_test.1218404663 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/484.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/485.prim_prince_test.1693389250 |
Short name | T478 |
Test name | |
Test status | |
Simulation time | 1732181459 ps |
CPU time | 29.32 seconds |
Started | Aug 27 01:02:47 AM UTC 24 |
Finished | Aug 27 01:03:25 AM UTC 24 |
Peak memory | 154592 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1693389250 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 485.prim_prince_test.1693389250 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/485.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/486.prim_prince_test.4085655295 |
Short name | T491 |
Test name | |
Test status | |
Simulation time | 3654673383 ps |
CPU time | 62.22 seconds |
Started | Aug 27 01:02:49 AM UTC 24 |
Finished | Aug 27 01:04:09 AM UTC 24 |
Peak memory | 154656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4085655295 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 486.prim_prince_test.4085655295 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/486.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/487.prim_prince_test.1110772579 |
Short name | T484 |
Test name | |
Test status | |
Simulation time | 2131089622 ps |
CPU time | 36.01 seconds |
Started | Aug 27 01:02:51 AM UTC 24 |
Finished | Aug 27 01:03:38 AM UTC 24 |
Peak memory | 154592 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1110772579 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 487.prim_prince_test.1110772579 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/487.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/488.prim_prince_test.418448908 |
Short name | T476 |
Test name | |
Test status | |
Simulation time | 1106716885 ps |
CPU time | 19.37 seconds |
Started | Aug 27 01:02:54 AM UTC 24 |
Finished | Aug 27 01:03:19 AM UTC 24 |
Peak memory | 154600 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=418448908 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 488.prim_prince_test.418448908 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/488.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/489.prim_prince_test.1942890308 |
Short name | T492 |
Test name | |
Test status | |
Simulation time | 3317961607 ps |
CPU time | 57.12 seconds |
Started | Aug 27 01:02:57 AM UTC 24 |
Finished | Aug 27 01:04:10 AM UTC 24 |
Peak memory | 154656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1942890308 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 489.prim_prince_test.1942890308 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/489.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/49.prim_prince_test.2155122712 |
Short name | T55 |
Test name | |
Test status | |
Simulation time | 3198542999 ps |
CPU time | 54.44 seconds |
Started | Aug 27 12:41:39 AM UTC 24 |
Finished | Aug 27 12:42:49 AM UTC 24 |
Peak memory | 154664 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2155122712 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 49.prim_prince_test.2155122712 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/49.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/490.prim_prince_test.681762549 |
Short name | T496 |
Test name | |
Test status | |
Simulation time | 3543539087 ps |
CPU time | 59.97 seconds |
Started | Aug 27 01:03:00 AM UTC 24 |
Finished | Aug 27 01:04:17 AM UTC 24 |
Peak memory | 154664 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=681762549 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 490.prim_prince_test.681762549 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/490.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/491.prim_prince_test.2026939936 |
Short name | T498 |
Test name | |
Test status | |
Simulation time | 3493621060 ps |
CPU time | 59.89 seconds |
Started | Aug 27 01:03:07 AM UTC 24 |
Finished | Aug 27 01:04:24 AM UTC 24 |
Peak memory | 154660 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2026939936 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 491.prim_prince_test.2026939936 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/491.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/492.prim_prince_test.1815687753 |
Short name | T497 |
Test name | |
Test status | |
Simulation time | 3348355644 ps |
CPU time | 56.7 seconds |
Started | Aug 27 01:03:07 AM UTC 24 |
Finished | Aug 27 01:04:20 AM UTC 24 |
Peak memory | 154656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1815687753 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 492.prim_prince_test.1815687753 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/492.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/493.prim_prince_test.1663341964 |
Short name | T493 |
Test name | |
Test status | |
Simulation time | 2881851038 ps |
CPU time | 48.6 seconds |
Started | Aug 27 01:03:08 AM UTC 24 |
Finished | Aug 27 01:04:11 AM UTC 24 |
Peak memory | 154656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1663341964 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 493.prim_prince_test.1663341964 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/493.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/494.prim_prince_test.3701510974 |
Short name | T480 |
Test name | |
Test status | |
Simulation time | 890544594 ps |
CPU time | 15.52 seconds |
Started | Aug 27 01:03:10 AM UTC 24 |
Finished | Aug 27 01:03:30 AM UTC 24 |
Peak memory | 154588 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3701510974 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 494.prim_prince_test.3701510974 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/494.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/495.prim_prince_test.1449059604 |
Short name | T495 |
Test name | |
Test status | |
Simulation time | 2977328188 ps |
CPU time | 51.1 seconds |
Started | Aug 27 01:03:11 AM UTC 24 |
Finished | Aug 27 01:04:17 AM UTC 24 |
Peak memory | 154652 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1449059604 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 495.prim_prince_test.1449059604 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/495.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/496.prim_prince_test.4097246545 |
Short name | T485 |
Test name | |
Test status | |
Simulation time | 1122027402 ps |
CPU time | 19.54 seconds |
Started | Aug 27 01:03:13 AM UTC 24 |
Finished | Aug 27 01:03:38 AM UTC 24 |
Peak memory | 154592 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4097246545 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 496.prim_prince_test.4097246545 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/496.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/497.prim_prince_test.1167959211 |
Short name | T494 |
Test name | |
Test status | |
Simulation time | 2819547405 ps |
CPU time | 48.39 seconds |
Started | Aug 27 01:03:14 AM UTC 24 |
Finished | Aug 27 01:04:17 AM UTC 24 |
Peak memory | 154656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1167959211 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 497.prim_prince_test.1167959211 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/497.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/498.prim_prince_test.690426252 |
Short name | T500 |
Test name | |
Test status | |
Simulation time | 3297303064 ps |
CPU time | 57.14 seconds |
Started | Aug 27 01:03:21 AM UTC 24 |
Finished | Aug 27 01:04:34 AM UTC 24 |
Peak memory | 154668 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=690426252 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 498.prim_prince_test.690426252 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/498.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/499.prim_prince_test.1781641391 |
Short name | T499 |
Test name | |
Test status | |
Simulation time | 2978603088 ps |
CPU time | 51.45 seconds |
Started | Aug 27 01:03:22 AM UTC 24 |
Finished | Aug 27 01:04:28 AM UTC 24 |
Peak memory | 154656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1781641391 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 499.prim_prince_test.1781641391 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/499.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/5.prim_prince_test.603168684 |
Short name | T12 |
Test name | |
Test status | |
Simulation time | 3738749878 ps |
CPU time | 64.94 seconds |
Started | Aug 27 12:38:02 AM UTC 24 |
Finished | Aug 27 12:39:24 AM UTC 24 |
Peak memory | 154660 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=603168684 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 5.prim_prince_test.603168684 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/5.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/50.prim_prince_test.379564583 |
Short name | T54 |
Test name | |
Test status | |
Simulation time | 2985559042 ps |
CPU time | 51.42 seconds |
Started | Aug 27 12:41:41 AM UTC 24 |
Finished | Aug 27 12:42:48 AM UTC 24 |
Peak memory | 154664 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=379564583 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 50.prim_prince_test.379564583 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/50.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/51.prim_prince_test.994947812 |
Short name | T50 |
Test name | |
Test status | |
Simulation time | 1903654047 ps |
CPU time | 32.71 seconds |
Started | Aug 27 12:41:46 AM UTC 24 |
Finished | Aug 27 12:42:29 AM UTC 24 |
Peak memory | 154600 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=994947812 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 51.prim_prince_test.994947812 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/51.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/52.prim_prince_test.3988496109 |
Short name | T58 |
Test name | |
Test status | |
Simulation time | 3071804695 ps |
CPU time | 52.86 seconds |
Started | Aug 27 12:41:48 AM UTC 24 |
Finished | Aug 27 12:42:56 AM UTC 24 |
Peak memory | 154656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3988496109 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 52.prim_prince_test.3988496109 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/52.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/53.prim_prince_test.516345386 |
Short name | T60 |
Test name | |
Test status | |
Simulation time | 3321422465 ps |
CPU time | 56.44 seconds |
Started | Aug 27 12:41:52 AM UTC 24 |
Finished | Aug 27 12:43:05 AM UTC 24 |
Peak memory | 154664 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=516345386 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 53.prim_prince_test.516345386 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/53.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/54.prim_prince_test.3933893927 |
Short name | T57 |
Test name | |
Test status | |
Simulation time | 2618950294 ps |
CPU time | 44.89 seconds |
Started | Aug 27 12:41:57 AM UTC 24 |
Finished | Aug 27 12:42:55 AM UTC 24 |
Peak memory | 154664 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3933893927 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 54.prim_prince_test.3933893927 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/54.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/55.prim_prince_test.575234945 |
Short name | T48 |
Test name | |
Test status | |
Simulation time | 1120385147 ps |
CPU time | 19.39 seconds |
Started | Aug 27 12:41:57 AM UTC 24 |
Finished | Aug 27 12:42:22 AM UTC 24 |
Peak memory | 154600 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=575234945 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 55.prim_prince_test.575234945 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/55.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/56.prim_prince_test.1004376974 |
Short name | T49 |
Test name | |
Test status | |
Simulation time | 1178180727 ps |
CPU time | 20.5 seconds |
Started | Aug 27 12:42:00 AM UTC 24 |
Finished | Aug 27 12:42:27 AM UTC 24 |
Peak memory | 154600 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1004376974 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 56.prim_prince_test.1004376974 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/56.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/57.prim_prince_test.3945254821 |
Short name | T52 |
Test name | |
Test status | |
Simulation time | 1387506374 ps |
CPU time | 23.8 seconds |
Started | Aug 27 12:42:04 AM UTC 24 |
Finished | Aug 27 12:42:35 AM UTC 24 |
Peak memory | 154600 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3945254821 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 57.prim_prince_test.3945254821 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/57.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/58.prim_prince_test.2544124975 |
Short name | T59 |
Test name | |
Test status | |
Simulation time | 1968628317 ps |
CPU time | 34.12 seconds |
Started | Aug 27 12:42:12 AM UTC 24 |
Finished | Aug 27 12:42:56 AM UTC 24 |
Peak memory | 154600 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2544124975 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 58.prim_prince_test.2544124975 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/58.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/59.prim_prince_test.2295704993 |
Short name | T64 |
Test name | |
Test status | |
Simulation time | 2387752976 ps |
CPU time | 40.67 seconds |
Started | Aug 27 12:42:23 AM UTC 24 |
Finished | Aug 27 12:43:16 AM UTC 24 |
Peak memory | 154664 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2295704993 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 59.prim_prince_test.2295704993 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/59.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/6.prim_prince_test.3343708532 |
Short name | T15 |
Test name | |
Test status | |
Simulation time | 3452639741 ps |
CPU time | 59.38 seconds |
Started | Aug 27 12:38:14 AM UTC 24 |
Finished | Aug 27 12:39:29 AM UTC 24 |
Peak memory | 154664 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3343708532 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 6.prim_prince_test.3343708532 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/6.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/60.prim_prince_test.2390191085 |
Short name | T62 |
Test name | |
Test status | |
Simulation time | 2143669647 ps |
CPU time | 36.98 seconds |
Started | Aug 27 12:42:27 AM UTC 24 |
Finished | Aug 27 12:43:15 AM UTC 24 |
Peak memory | 154600 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2390191085 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 60.prim_prince_test.2390191085 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/60.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/61.prim_prince_test.1878024984 |
Short name | T61 |
Test name | |
Test status | |
Simulation time | 1898909369 ps |
CPU time | 32.2 seconds |
Started | Aug 27 12:42:30 AM UTC 24 |
Finished | Aug 27 12:43:12 AM UTC 24 |
Peak memory | 154600 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1878024984 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 61.prim_prince_test.1878024984 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/61.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/62.prim_prince_test.1797873112 |
Short name | T65 |
Test name | |
Test status | |
Simulation time | 3051975013 ps |
CPU time | 52.04 seconds |
Started | Aug 27 12:42:34 AM UTC 24 |
Finished | Aug 27 12:43:42 AM UTC 24 |
Peak memory | 154664 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1797873112 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 62.prim_prince_test.1797873112 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/62.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/63.prim_prince_test.2309890061 |
Short name | T69 |
Test name | |
Test status | |
Simulation time | 3428583971 ps |
CPU time | 58.12 seconds |
Started | Aug 27 12:42:36 AM UTC 24 |
Finished | Aug 27 12:43:51 AM UTC 24 |
Peak memory | 154664 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2309890061 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 63.prim_prince_test.2309890061 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/63.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/64.prim_prince_test.2107373633 |
Short name | T63 |
Test name | |
Test status | |
Simulation time | 1494810990 ps |
CPU time | 25.85 seconds |
Started | Aug 27 12:42:42 AM UTC 24 |
Finished | Aug 27 12:43:15 AM UTC 24 |
Peak memory | 154600 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2107373633 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 64.prim_prince_test.2107373633 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/64.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/65.prim_prince_test.399108546 |
Short name | T72 |
Test name | |
Test status | |
Simulation time | 3332225927 ps |
CPU time | 57.2 seconds |
Started | Aug 27 12:42:49 AM UTC 24 |
Finished | Aug 27 12:44:02 AM UTC 24 |
Peak memory | 154664 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=399108546 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 65.prim_prince_test.399108546 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/65.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/66.prim_prince_test.665373997 |
Short name | T68 |
Test name | |
Test status | |
Simulation time | 2746596307 ps |
CPU time | 46.65 seconds |
Started | Aug 27 12:42:51 AM UTC 24 |
Finished | Aug 27 12:43:51 AM UTC 24 |
Peak memory | 154664 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=665373997 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 66.prim_prince_test.665373997 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/66.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/67.prim_prince_test.786851871 |
Short name | T71 |
Test name | |
Test status | |
Simulation time | 3008387664 ps |
CPU time | 51.42 seconds |
Started | Aug 27 12:42:53 AM UTC 24 |
Finished | Aug 27 12:43:59 AM UTC 24 |
Peak memory | 154660 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=786851871 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 67.prim_prince_test.786851871 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/67.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/68.prim_prince_test.4208230697 |
Short name | T74 |
Test name | |
Test status | |
Simulation time | 3355028220 ps |
CPU time | 57.25 seconds |
Started | Aug 27 12:42:56 AM UTC 24 |
Finished | Aug 27 12:44:10 AM UTC 24 |
Peak memory | 154664 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4208230697 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 68.prim_prince_test.4208230697 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/68.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/69.prim_prince_test.4095306425 |
Short name | T66 |
Test name | |
Test status | |
Simulation time | 2319467833 ps |
CPU time | 39.36 seconds |
Started | Aug 27 12:42:57 AM UTC 24 |
Finished | Aug 27 12:43:48 AM UTC 24 |
Peak memory | 154664 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4095306425 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 69.prim_prince_test.4095306425 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/69.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/7.prim_prince_test.985838155 |
Short name | T9 |
Test name | |
Test status | |
Simulation time | 2648131570 ps |
CPU time | 46.81 seconds |
Started | Aug 27 12:38:15 AM UTC 24 |
Finished | Aug 27 12:39:14 AM UTC 24 |
Peak memory | 154652 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=985838155 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 7.prim_prince_test.985838155 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/7.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/70.prim_prince_test.3189341518 |
Short name | T8 |
Test name | |
Test status | |
Simulation time | 2868069744 ps |
CPU time | 49.26 seconds |
Started | Aug 27 12:42:57 AM UTC 24 |
Finished | Aug 27 12:44:01 AM UTC 24 |
Peak memory | 154664 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3189341518 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 70.prim_prince_test.3189341518 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/70.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/71.prim_prince_test.3231030327 |
Short name | T80 |
Test name | |
Test status | |
Simulation time | 3694091561 ps |
CPU time | 62.07 seconds |
Started | Aug 27 12:43:05 AM UTC 24 |
Finished | Aug 27 12:44:25 AM UTC 24 |
Peak memory | 154664 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3231030327 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 71.prim_prince_test.3231030327 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/71.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/72.prim_prince_test.2253813089 |
Short name | T75 |
Test name | |
Test status | |
Simulation time | 2742343397 ps |
CPU time | 46.65 seconds |
Started | Aug 27 12:43:13 AM UTC 24 |
Finished | Aug 27 12:44:14 AM UTC 24 |
Peak memory | 154660 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2253813089 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 72.prim_prince_test.2253813089 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/72.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/73.prim_prince_test.1278914756 |
Short name | T70 |
Test name | |
Test status | |
Simulation time | 1910336097 ps |
CPU time | 32.2 seconds |
Started | Aug 27 12:43:15 AM UTC 24 |
Finished | Aug 27 12:43:58 AM UTC 24 |
Peak memory | 154588 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1278914756 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 73.prim_prince_test.1278914756 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/73.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/74.prim_prince_test.915117739 |
Short name | T67 |
Test name | |
Test status | |
Simulation time | 1426436905 ps |
CPU time | 24.41 seconds |
Started | Aug 27 12:43:17 AM UTC 24 |
Finished | Aug 27 12:43:49 AM UTC 24 |
Peak memory | 154600 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=915117739 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 74.prim_prince_test.915117739 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/74.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/75.prim_prince_test.2128482706 |
Short name | T73 |
Test name | |
Test status | |
Simulation time | 2292905599 ps |
CPU time | 39.24 seconds |
Started | Aug 27 12:43:17 AM UTC 24 |
Finished | Aug 27 12:44:07 AM UTC 24 |
Peak memory | 154660 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2128482706 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 75.prim_prince_test.2128482706 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/75.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/76.prim_prince_test.1167338738 |
Short name | T77 |
Test name | |
Test status | |
Simulation time | 1719897535 ps |
CPU time | 29.7 seconds |
Started | Aug 27 12:43:43 AM UTC 24 |
Finished | Aug 27 12:44:22 AM UTC 24 |
Peak memory | 154600 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1167338738 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 76.prim_prince_test.1167338738 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/76.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/77.prim_prince_test.4234535742 |
Short name | T86 |
Test name | |
Test status | |
Simulation time | 3244327658 ps |
CPU time | 54.65 seconds |
Started | Aug 27 12:43:49 AM UTC 24 |
Finished | Aug 27 12:44:59 AM UTC 24 |
Peak memory | 154664 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4234535742 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 77.prim_prince_test.4234535742 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/77.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/78.prim_prince_test.2872018850 |
Short name | T81 |
Test name | |
Test status | |
Simulation time | 2480308700 ps |
CPU time | 42.45 seconds |
Started | Aug 27 12:43:49 AM UTC 24 |
Finished | Aug 27 12:44:44 AM UTC 24 |
Peak memory | 154660 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2872018850 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 78.prim_prince_test.2872018850 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/78.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/79.prim_prince_test.1895834567 |
Short name | T79 |
Test name | |
Test status | |
Simulation time | 1448365419 ps |
CPU time | 24.75 seconds |
Started | Aug 27 12:43:52 AM UTC 24 |
Finished | Aug 27 12:44:25 AM UTC 24 |
Peak memory | 154600 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1895834567 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 79.prim_prince_test.1895834567 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/79.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/8.prim_prince_test.110565807 |
Short name | T6 |
Test name | |
Test status | |
Simulation time | 1575905282 ps |
CPU time | 27.4 seconds |
Started | Aug 27 12:38:24 AM UTC 24 |
Finished | Aug 27 12:38:59 AM UTC 24 |
Peak memory | 154596 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=110565807 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 8.prim_prince_test.110565807 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/8.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/80.prim_prince_test.2191255393 |
Short name | T85 |
Test name | |
Test status | |
Simulation time | 2986497963 ps |
CPU time | 50.51 seconds |
Started | Aug 27 12:43:52 AM UTC 24 |
Finished | Aug 27 12:44:57 AM UTC 24 |
Peak memory | 154664 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2191255393 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 80.prim_prince_test.2191255393 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/80.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/81.prim_prince_test.1148507967 |
Short name | T76 |
Test name | |
Test status | |
Simulation time | 947947244 ps |
CPU time | 16.7 seconds |
Started | Aug 27 12:43:55 AM UTC 24 |
Finished | Aug 27 12:44:17 AM UTC 24 |
Peak memory | 156056 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1148507967 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 81.prim_prince_test.1148507967 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/81.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/82.prim_prince_test.1144444294 |
Short name | T78 |
Test name | |
Test status | |
Simulation time | 1127406012 ps |
CPU time | 19.24 seconds |
Started | Aug 27 12:43:58 AM UTC 24 |
Finished | Aug 27 12:44:24 AM UTC 24 |
Peak memory | 154600 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1144444294 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 82.prim_prince_test.1144444294 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/82.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/83.prim_prince_test.3403472284 |
Short name | T84 |
Test name | |
Test status | |
Simulation time | 2552103272 ps |
CPU time | 44.12 seconds |
Started | Aug 27 12:44:00 AM UTC 24 |
Finished | Aug 27 12:44:57 AM UTC 24 |
Peak memory | 154664 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3403472284 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 83.prim_prince_test.3403472284 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/83.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/84.prim_prince_test.67116034 |
Short name | T89 |
Test name | |
Test status | |
Simulation time | 2959756773 ps |
CPU time | 51.17 seconds |
Started | Aug 27 12:44:02 AM UTC 24 |
Finished | Aug 27 12:45:07 AM UTC 24 |
Peak memory | 154660 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=67116034 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 84.prim_prince_test.67116034 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/84.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/85.prim_prince_test.1676649901 |
Short name | T87 |
Test name | |
Test status | |
Simulation time | 2804646344 ps |
CPU time | 47.09 seconds |
Started | Aug 27 12:44:03 AM UTC 24 |
Finished | Aug 27 12:45:04 AM UTC 24 |
Peak memory | 154664 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1676649901 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 85.prim_prince_test.1676649901 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/85.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/86.prim_prince_test.3035291207 |
Short name | T92 |
Test name | |
Test status | |
Simulation time | 3636890603 ps |
CPU time | 63.2 seconds |
Started | Aug 27 12:44:08 AM UTC 24 |
Finished | Aug 27 12:45:29 AM UTC 24 |
Peak memory | 154664 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3035291207 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 86.prim_prince_test.3035291207 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/86.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/87.prim_prince_test.3387875408 |
Short name | T90 |
Test name | |
Test status | |
Simulation time | 3109143455 ps |
CPU time | 53.03 seconds |
Started | Aug 27 12:44:11 AM UTC 24 |
Finished | Aug 27 12:45:19 AM UTC 24 |
Peak memory | 154660 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3387875408 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 87.prim_prince_test.3387875408 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/87.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/88.prim_prince_test.2465510410 |
Short name | T93 |
Test name | |
Test status | |
Simulation time | 3434315029 ps |
CPU time | 59.07 seconds |
Started | Aug 27 12:44:14 AM UTC 24 |
Finished | Aug 27 12:45:30 AM UTC 24 |
Peak memory | 154664 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2465510410 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 88.prim_prince_test.2465510410 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/88.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/89.prim_prince_test.3344556892 |
Short name | T88 |
Test name | |
Test status | |
Simulation time | 2156657593 ps |
CPU time | 36.39 seconds |
Started | Aug 27 12:44:18 AM UTC 24 |
Finished | Aug 27 12:45:05 AM UTC 24 |
Peak memory | 154664 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3344556892 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 89.prim_prince_test.3344556892 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/89.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/9.prim_prince_test.2275242205 |
Short name | T10 |
Test name | |
Test status | |
Simulation time | 1988779140 ps |
CPU time | 35.2 seconds |
Started | Aug 27 12:38:31 AM UTC 24 |
Finished | Aug 27 12:39:15 AM UTC 24 |
Peak memory | 154600 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2275242205 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 9.prim_prince_test.2275242205 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/9.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/90.prim_prince_test.2331407523 |
Short name | T82 |
Test name | |
Test status | |
Simulation time | 994375882 ps |
CPU time | 17.38 seconds |
Started | Aug 27 12:44:22 AM UTC 24 |
Finished | Aug 27 12:44:45 AM UTC 24 |
Peak memory | 154600 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2331407523 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 90.prim_prince_test.2331407523 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/90.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/91.prim_prince_test.2030825654 |
Short name | T83 |
Test name | |
Test status | |
Simulation time | 1071220963 ps |
CPU time | 18.59 seconds |
Started | Aug 27 12:44:24 AM UTC 24 |
Finished | Aug 27 12:44:49 AM UTC 24 |
Peak memory | 154600 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2030825654 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 91.prim_prince_test.2030825654 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/91.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/92.prim_prince_test.813595877 |
Short name | T98 |
Test name | |
Test status | |
Simulation time | 3638846778 ps |
CPU time | 62.45 seconds |
Started | Aug 27 12:44:25 AM UTC 24 |
Finished | Aug 27 12:45:46 AM UTC 24 |
Peak memory | 154664 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=813595877 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 92.prim_prince_test.813595877 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/92.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/93.prim_prince_test.3541233602 |
Short name | T95 |
Test name | |
Test status | |
Simulation time | 3125949119 ps |
CPU time | 52.86 seconds |
Started | Aug 27 12:44:27 AM UTC 24 |
Finished | Aug 27 12:45:35 AM UTC 24 |
Peak memory | 154664 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3541233602 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 93.prim_prince_test.3541233602 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/93.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/94.prim_prince_test.1486072643 |
Short name | T102 |
Test name | |
Test status | |
Simulation time | 3566362269 ps |
CPU time | 60.1 seconds |
Started | Aug 27 12:44:38 AM UTC 24 |
Finished | Aug 27 12:45:55 AM UTC 24 |
Peak memory | 154664 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1486072643 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 94.prim_prince_test.1486072643 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/94.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/95.prim_prince_test.4043757306 |
Short name | T96 |
Test name | |
Test status | |
Simulation time | 2661480538 ps |
CPU time | 45.22 seconds |
Started | Aug 27 12:44:45 AM UTC 24 |
Finished | Aug 27 12:45:43 AM UTC 24 |
Peak memory | 154664 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4043757306 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 95.prim_prince_test.4043757306 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/95.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/96.prim_prince_test.1461254886 |
Short name | T97 |
Test name | |
Test status | |
Simulation time | 2618632394 ps |
CPU time | 44.93 seconds |
Started | Aug 27 12:44:46 AM UTC 24 |
Finished | Aug 27 12:45:44 AM UTC 24 |
Peak memory | 154664 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1461254886 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 96.prim_prince_test.1461254886 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/96.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/97.prim_prince_test.220383552 |
Short name | T107 |
Test name | |
Test status | |
Simulation time | 3625836184 ps |
CPU time | 60.64 seconds |
Started | Aug 27 12:44:50 AM UTC 24 |
Finished | Aug 27 12:46:08 AM UTC 24 |
Peak memory | 156116 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=220383552 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 97.prim_prince_test.220383552 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/97.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/98.prim_prince_test.364631303 |
Short name | T105 |
Test name | |
Test status | |
Simulation time | 3143563259 ps |
CPU time | 52.77 seconds |
Started | Aug 27 12:44:58 AM UTC 24 |
Finished | Aug 27 12:46:07 AM UTC 24 |
Peak memory | 154288 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=364631303 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 98.prim_prince_test.364631303 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/98.prim_prince_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default/99.prim_prince_test.2748630764 |
Short name | T91 |
Test name | |
Test status | |
Simulation time | 927340800 ps |
CPU time | 16.21 seconds |
Started | Aug 27 12:44:58 AM UTC 24 |
Finished | Aug 27 12:45:20 AM UTC 24 |
Peak memory | 154556 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2748630764 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 99.prim_prince_test.2748630764 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_prince-sim-vcs/99.prim_prince_test/latest |
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