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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00 100.00


Total test records in report: 500
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html
T251 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/228.prim_prince_test.3541873157 Aug 28 06:14:00 PM UTC 24 Aug 28 06:15:20 PM UTC 24 3544702257 ps
T252 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/270.prim_prince_test.858451713 Aug 28 06:15:03 PM UTC 24 Aug 28 06:15:21 PM UTC 24 783956013 ps
T253 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/248.prim_prince_test.2167305174 Aug 28 06:14:32 PM UTC 24 Aug 28 06:15:22 PM UTC 24 2158207908 ps
T254 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/262.prim_prince_test.4176872412 Aug 28 06:14:54 PM UTC 24 Aug 28 06:15:27 PM UTC 24 1431531263 ps
T255 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/275.prim_prince_test.2745784085 Aug 28 06:15:07 PM UTC 24 Aug 28 06:15:32 PM UTC 24 1039150233 ps
T256 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/258.prim_prince_test.3541307923 Aug 28 06:14:49 PM UTC 24 Aug 28 06:15:32 PM UTC 24 1890591892 ps
T257 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/260.prim_prince_test.1103916734 Aug 28 06:14:54 PM UTC 24 Aug 28 06:15:36 PM UTC 24 1844927404 ps
T258 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/239.prim_prince_test.1571538952 Aug 28 06:14:19 PM UTC 24 Aug 28 06:15:38 PM UTC 24 3462060777 ps
T259 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/279.prim_prince_test.3801496904 Aug 28 06:15:15 PM UTC 24 Aug 28 06:15:39 PM UTC 24 1014032824 ps
T260 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/254.prim_prince_test.1677737682 Aug 28 06:14:42 PM UTC 24 Aug 28 06:15:41 PM UTC 24 2639772067 ps
T261 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/261.prim_prince_test.3579107867 Aug 28 06:14:54 PM UTC 24 Aug 28 06:15:44 PM UTC 24 2233684509 ps
T262 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/271.prim_prince_test.2548985143 Aug 28 06:15:03 PM UTC 24 Aug 28 06:15:45 PM UTC 24 1850147279 ps
T263 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/251.prim_prince_test.2165958216 Aug 28 06:14:36 PM UTC 24 Aug 28 06:15:45 PM UTC 24 3073658535 ps
T264 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/250.prim_prince_test.163828708 Aug 28 06:14:34 PM UTC 24 Aug 28 06:15:47 PM UTC 24 3198166480 ps
T265 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/273.prim_prince_test.919144185 Aug 28 06:15:05 PM UTC 24 Aug 28 06:15:47 PM UTC 24 1831173029 ps
T266 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/281.prim_prince_test.138100284 Aug 28 06:15:18 PM UTC 24 Aug 28 06:15:47 PM UTC 24 1258889431 ps
T267 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/282.prim_prince_test.2266573512 Aug 28 06:15:19 PM UTC 24 Aug 28 06:15:49 PM UTC 24 1332132631 ps
T268 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/267.prim_prince_test.1409582647 Aug 28 06:15:00 PM UTC 24 Aug 28 06:15:50 PM UTC 24 2177222242 ps
T269 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/252.prim_prince_test.3298523278 Aug 28 06:14:39 PM UTC 24 Aug 28 06:15:50 PM UTC 24 3149990093 ps
T270 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/255.prim_prince_test.4265087817 Aug 28 06:14:45 PM UTC 24 Aug 28 06:15:50 PM UTC 24 2882607897 ps
T271 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/288.prim_prince_test.3595503955 Aug 28 06:15:32 PM UTC 24 Aug 28 06:15:52 PM UTC 24 812700470 ps
T272 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/263.prim_prince_test.2148449266 Aug 28 06:14:55 PM UTC 24 Aug 28 06:15:53 PM UTC 24 2591856039 ps
T273 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/276.prim_prince_test.844667157 Aug 28 06:15:07 PM UTC 24 Aug 28 06:15:55 PM UTC 24 2138095087 ps
T274 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/280.prim_prince_test.1170489375 Aug 28 06:15:16 PM UTC 24 Aug 28 06:15:59 PM UTC 24 1899810462 ps
T275 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/265.prim_prince_test.812104989 Aug 28 06:14:58 PM UTC 24 Aug 28 06:16:01 PM UTC 24 2769457019 ps
T276 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/287.prim_prince_test.3075790003 Aug 28 06:15:29 PM UTC 24 Aug 28 06:16:01 PM UTC 24 1357825689 ps
T277 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/266.prim_prince_test.888842624 Aug 28 06:14:59 PM UTC 24 Aug 28 06:16:02 PM UTC 24 2766770831 ps
T278 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/284.prim_prince_test.3489285855 Aug 28 06:15:22 PM UTC 24 Aug 28 06:16:05 PM UTC 24 1892640549 ps
T279 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/269.prim_prince_test.3007138878 Aug 28 06:15:03 PM UTC 24 Aug 28 06:16:08 PM UTC 24 2922316070 ps
T280 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/259.prim_prince_test.2860907139 Aug 28 06:14:51 PM UTC 24 Aug 28 06:16:14 PM UTC 24 3676768771 ps
T281 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/305.prim_prince_test.1393347468 Aug 28 06:15:54 PM UTC 24 Aug 28 06:16:15 PM UTC 24 834019915 ps
T282 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/264.prim_prince_test.1290395406 Aug 28 06:14:56 PM UTC 24 Aug 28 06:16:19 PM UTC 24 3688992557 ps
T283 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/278.prim_prince_test.318887998 Aug 28 06:15:13 PM UTC 24 Aug 28 06:16:19 PM UTC 24 2920137850 ps
T284 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/307.prim_prince_test.2455657000 Aug 28 06:16:00 PM UTC 24 Aug 28 06:16:20 PM UTC 24 851872735 ps
T285 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/272.prim_prince_test.3688757223 Aug 28 06:15:04 PM UTC 24 Aug 28 06:16:22 PM UTC 24 3488658557 ps
T286 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/309.prim_prince_test.271506423 Aug 28 06:16:02 PM UTC 24 Aug 28 06:16:22 PM UTC 24 850984414 ps
T287 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/277.prim_prince_test.3664184733 Aug 28 06:15:09 PM UTC 24 Aug 28 06:16:23 PM UTC 24 3265604236 ps
T288 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/268.prim_prince_test.954091599 Aug 28 06:15:01 PM UTC 24 Aug 28 06:16:23 PM UTC 24 3640776456 ps
T289 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/304.prim_prince_test.741119728 Aug 28 06:15:52 PM UTC 24 Aug 28 06:16:23 PM UTC 24 1321324026 ps
T290 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/293.prim_prince_test.1937153778 Aug 28 06:15:42 PM UTC 24 Aug 28 06:16:25 PM UTC 24 1840873069 ps
T291 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/297.prim_prince_test.1538126936 Aug 28 06:15:48 PM UTC 24 Aug 28 06:16:25 PM UTC 24 1611172863 ps
T292 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/274.prim_prince_test.168686428 Aug 28 06:15:05 PM UTC 24 Aug 28 06:16:26 PM UTC 24 3592919686 ps
T293 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/301.prim_prince_test.3130236807 Aug 28 06:15:51 PM UTC 24 Aug 28 06:16:26 PM UTC 24 1518432685 ps
T294 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/303.prim_prince_test.2402606223 Aug 28 06:15:51 PM UTC 24 Aug 28 06:16:28 PM UTC 24 1590044594 ps
T295 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/311.prim_prince_test.1049306434 Aug 28 06:16:06 PM UTC 24 Aug 28 06:16:30 PM UTC 24 1028891781 ps
T296 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/310.prim_prince_test.919643262 Aug 28 06:16:03 PM UTC 24 Aug 28 06:16:32 PM UTC 24 1227029134 ps
T297 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/308.prim_prince_test.3708282270 Aug 28 06:16:02 PM UTC 24 Aug 28 06:16:34 PM UTC 24 1383488888 ps
T298 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/290.prim_prince_test.1460245232 Aug 28 06:15:37 PM UTC 24 Aug 28 06:16:35 PM UTC 24 2557010789 ps
T299 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/306.prim_prince_test.3030975751 Aug 28 06:15:56 PM UTC 24 Aug 28 06:16:36 PM UTC 24 1722581778 ps
T300 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/292.prim_prince_test.4196433489 Aug 28 06:15:40 PM UTC 24 Aug 28 06:16:37 PM UTC 24 2500757294 ps
T301 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/289.prim_prince_test.3105309087 Aug 28 06:15:34 PM UTC 24 Aug 28 06:16:39 PM UTC 24 2901722983 ps
T302 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/317.prim_prince_test.7681756 Aug 28 06:16:21 PM UTC 24 Aug 28 06:16:40 PM UTC 24 816766033 ps
T303 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/315.prim_prince_test.1687852350 Aug 28 06:16:20 PM UTC 24 Aug 28 06:16:41 PM UTC 24 899480007 ps
T304 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/283.prim_prince_test.3051635005 Aug 28 06:15:21 PM UTC 24 Aug 28 06:16:41 PM UTC 24 3578830425 ps
T305 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/302.prim_prince_test.3031913994 Aug 28 06:15:51 PM UTC 24 Aug 28 06:16:42 PM UTC 24 2237248632 ps
T306 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/295.prim_prince_test.2912956899 Aug 28 06:15:46 PM UTC 24 Aug 28 06:16:42 PM UTC 24 2443734613 ps
T307 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/298.prim_prince_test.1465010660 Aug 28 06:15:48 PM UTC 24 Aug 28 06:16:43 PM UTC 24 2460299701 ps
T308 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/314.prim_prince_test.145417760 Aug 28 06:16:15 PM UTC 24 Aug 28 06:16:45 PM UTC 24 1270700742 ps
T309 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/285.prim_prince_test.3411164408 Aug 28 06:15:23 PM UTC 24 Aug 28 06:16:46 PM UTC 24 3717941922 ps
T310 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/286.prim_prince_test.1669371844 Aug 28 06:15:27 PM UTC 24 Aug 28 06:16:51 PM UTC 24 3738263007 ps
T311 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/291.prim_prince_test.701315511 Aug 28 06:15:39 PM UTC 24 Aug 28 06:16:51 PM UTC 24 3219247174 ps
T312 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/294.prim_prince_test.3676553473 Aug 28 06:15:45 PM UTC 24 Aug 28 06:16:53 PM UTC 24 3005833314 ps
T313 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/328.prim_prince_test.2473456060 Aug 28 06:16:31 PM UTC 24 Aug 28 06:16:53 PM UTC 24 941845516 ps
T314 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/312.prim_prince_test.2234524321 Aug 28 06:16:09 PM UTC 24 Aug 28 06:16:54 PM UTC 24 1949491912 ps
T315 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/325.prim_prince_test.3187263755 Aug 28 06:16:27 PM UTC 24 Aug 28 06:17:03 PM UTC 24 1558441904 ps
T316 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/338.prim_prince_test.3417322953 Aug 28 06:16:42 PM UTC 24 Aug 28 06:17:04 PM UTC 24 911248589 ps
T317 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/327.prim_prince_test.2740515929 Aug 28 06:16:28 PM UTC 24 Aug 28 06:17:05 PM UTC 24 1608769602 ps
T318 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/337.prim_prince_test.2271277782 Aug 28 06:16:42 PM UTC 24 Aug 28 06:17:05 PM UTC 24 985309594 ps
T319 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/331.prim_prince_test.3463084807 Aug 28 06:16:36 PM UTC 24 Aug 28 06:17:05 PM UTC 24 1268895601 ps
T320 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/332.prim_prince_test.725364807 Aug 28 06:16:37 PM UTC 24 Aug 28 06:17:06 PM UTC 24 1231688785 ps
T321 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/296.prim_prince_test.1219718102 Aug 28 06:15:46 PM UTC 24 Aug 28 06:17:06 PM UTC 24 3531891103 ps
T322 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/300.prim_prince_test.3791630836 Aug 28 06:15:50 PM UTC 24 Aug 28 06:17:07 PM UTC 24 3423689616 ps
T323 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/339.prim_prince_test.1900127733 Aug 28 06:16:44 PM UTC 24 Aug 28 06:17:08 PM UTC 24 1030722958 ps
T324 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/299.prim_prince_test.4219588624 Aug 28 06:15:48 PM UTC 24 Aug 28 06:17:11 PM UTC 24 3691183270 ps
T325 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/335.prim_prince_test.3362135594 Aug 28 06:16:41 PM UTC 24 Aug 28 06:17:12 PM UTC 24 1327791998 ps
T326 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/324.prim_prince_test.4037732858 Aug 28 06:16:26 PM UTC 24 Aug 28 06:17:13 PM UTC 24 2050355015 ps
T327 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/330.prim_prince_test.2792360474 Aug 28 06:16:34 PM UTC 24 Aug 28 06:17:14 PM UTC 24 1715721731 ps
T328 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/313.prim_prince_test.1801982511 Aug 28 06:16:14 PM UTC 24 Aug 28 06:17:17 PM UTC 24 2751192351 ps
T329 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/323.prim_prince_test.1044619911 Aug 28 06:16:26 PM UTC 24 Aug 28 06:17:17 PM UTC 24 2237083118 ps
T330 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/342.prim_prince_test.2589258133 Aug 28 06:16:47 PM UTC 24 Aug 28 06:17:18 PM UTC 24 1325405319 ps
T331 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/343.prim_prince_test.4039037363 Aug 28 06:16:52 PM UTC 24 Aug 28 06:17:25 PM UTC 24 1426344384 ps
T332 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/333.prim_prince_test.3009642501 Aug 28 06:16:38 PM UTC 24 Aug 28 06:17:25 PM UTC 24 2100412441 ps
T333 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/356.prim_prince_test.2368066422 Aug 28 06:17:08 PM UTC 24 Aug 28 06:17:26 PM UTC 24 753247274 ps
T334 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/336.prim_prince_test.4141766855 Aug 28 06:16:42 PM UTC 24 Aug 28 06:17:28 PM UTC 24 1999422385 ps
T335 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/329.prim_prince_test.2402336907 Aug 28 06:16:32 PM UTC 24 Aug 28 06:17:28 PM UTC 24 2439889019 ps
T336 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/353.prim_prince_test.1944533370 Aug 28 06:17:06 PM UTC 24 Aug 28 06:17:29 PM UTC 24 959305035 ps
T337 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/316.prim_prince_test.1989420190 Aug 28 06:16:20 PM UTC 24 Aug 28 06:17:32 PM UTC 24 3239543221 ps
T338 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/320.prim_prince_test.2647665634 Aug 28 06:16:23 PM UTC 24 Aug 28 06:17:33 PM UTC 24 3104632929 ps
T339 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/354.prim_prince_test.3922758139 Aug 28 06:17:06 PM UTC 24 Aug 28 06:17:34 PM UTC 24 1220441988 ps
T340 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/326.prim_prince_test.717991058 Aug 28 06:16:27 PM UTC 24 Aug 28 06:17:35 PM UTC 24 3004350090 ps
T341 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/319.prim_prince_test.4236532539 Aug 28 06:16:23 PM UTC 24 Aug 28 06:17:37 PM UTC 24 3275781307 ps
T342 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/321.prim_prince_test.45391990 Aug 28 06:16:24 PM UTC 24 Aug 28 06:17:37 PM UTC 24 3259603901 ps
T343 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/322.prim_prince_test.1932534971 Aug 28 06:16:24 PM UTC 24 Aug 28 06:17:37 PM UTC 24 3258263361 ps
T344 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/348.prim_prince_test.4225982312 Aug 28 06:17:04 PM UTC 24 Aug 28 06:17:38 PM UTC 24 1483583772 ps
T345 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/358.prim_prince_test.1581947752 Aug 28 06:17:12 PM UTC 24 Aug 28 06:17:39 PM UTC 24 1183700289 ps
T346 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/318.prim_prince_test.2434976608 Aug 28 06:16:23 PM UTC 24 Aug 28 06:17:40 PM UTC 24 3424654040 ps
T347 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/340.prim_prince_test.2497791699 Aug 28 06:16:44 PM UTC 24 Aug 28 06:17:42 PM UTC 24 2595483272 ps
T348 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/349.prim_prince_test.1803578527 Aug 28 06:17:05 PM UTC 24 Aug 28 06:17:44 PM UTC 24 1705853872 ps
T349 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/359.prim_prince_test.2149159851 Aug 28 06:17:13 PM UTC 24 Aug 28 06:17:46 PM UTC 24 1437346365 ps
T350 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/355.prim_prince_test.2064010407 Aug 28 06:17:08 PM UTC 24 Aug 28 06:17:47 PM UTC 24 1713589773 ps
T351 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/357.prim_prince_test.4046451736 Aug 28 06:17:09 PM UTC 24 Aug 28 06:17:47 PM UTC 24 1664297239 ps
T352 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/341.prim_prince_test.2815288951 Aug 28 06:16:46 PM UTC 24 Aug 28 06:17:50 PM UTC 24 2845990389 ps
T353 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/360.prim_prince_test.4248040689 Aug 28 06:17:13 PM UTC 24 Aug 28 06:17:50 PM UTC 24 1618091933 ps
T354 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/334.prim_prince_test.47802822 Aug 28 06:16:40 PM UTC 24 Aug 28 06:17:52 PM UTC 24 3184654700 ps
T355 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/376.prim_prince_test.2300968155 Aug 28 06:17:37 PM UTC 24 Aug 28 06:17:57 PM UTC 24 818658271 ps
T356 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/352.prim_prince_test.3394453778 Aug 28 06:17:06 PM UTC 24 Aug 28 06:17:57 PM UTC 24 2259515973 ps
T357 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/362.prim_prince_test.876771857 Aug 28 06:17:18 PM UTC 24 Aug 28 06:17:57 PM UTC 24 1743543861 ps
T358 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/377.prim_prince_test.2379704902 Aug 28 06:17:39 PM UTC 24 Aug 28 06:17:59 PM UTC 24 877829482 ps
T359 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/378.prim_prince_test.2165405906 Aug 28 06:17:39 PM UTC 24 Aug 28 06:18:00 PM UTC 24 926322772 ps
T360 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/372.prim_prince_test.2940746700 Aug 28 06:17:34 PM UTC 24 Aug 28 06:18:01 PM UTC 24 1172191350 ps
T361 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/344.prim_prince_test.2012114997 Aug 28 06:16:52 PM UTC 24 Aug 28 06:18:04 PM UTC 24 3213822619 ps
T362 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/346.prim_prince_test.3804767934 Aug 28 06:16:55 PM UTC 24 Aug 28 06:18:05 PM UTC 24 3164541091 ps
T363 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/370.prim_prince_test.1824070744 Aug 28 06:17:30 PM UTC 24 Aug 28 06:18:05 PM UTC 24 1558674408 ps
T364 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/386.prim_prince_test.131040851 Aug 28 06:17:48 PM UTC 24 Aug 28 06:18:06 PM UTC 24 748053448 ps
T365 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/347.prim_prince_test.1817672771 Aug 28 06:16:55 PM UTC 24 Aug 28 06:18:06 PM UTC 24 3195667758 ps
T366 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/380.prim_prince_test.1492973839 Aug 28 06:17:40 PM UTC 24 Aug 28 06:18:07 PM UTC 24 1143161905 ps
T367 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/350.prim_prince_test.247178102 Aug 28 06:17:06 PM UTC 24 Aug 28 06:18:09 PM UTC 24 2802045159 ps
T368 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/371.prim_prince_test.3733278701 Aug 28 06:17:33 PM UTC 24 Aug 28 06:18:11 PM UTC 24 1647274871 ps
T369 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/368.prim_prince_test.2873640761 Aug 28 06:17:28 PM UTC 24 Aug 28 06:18:11 PM UTC 24 1842380070 ps
T370 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/345.prim_prince_test.134508296 Aug 28 06:16:53 PM UTC 24 Aug 28 06:18:11 PM UTC 24 3460253499 ps
T371 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/361.prim_prince_test.1409200933 Aug 28 06:17:14 PM UTC 24 Aug 28 06:18:17 PM UTC 24 2735840832 ps
T372 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/365.prim_prince_test.4269184415 Aug 28 06:17:26 PM UTC 24 Aug 28 06:18:19 PM UTC 24 2356993037 ps
T373 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/366.prim_prince_test.1780824823 Aug 28 06:17:26 PM UTC 24 Aug 28 06:18:20 PM UTC 24 2420111880 ps
T374 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/351.prim_prince_test.830798644 Aug 28 06:17:06 PM UTC 24 Aug 28 06:18:21 PM UTC 24 3361416709 ps
T375 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/390.prim_prince_test.3414165012 Aug 28 06:17:57 PM UTC 24 Aug 28 06:18:23 PM UTC 24 1087935309 ps
T376 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/385.prim_prince_test.1312902187 Aug 28 06:17:48 PM UTC 24 Aug 28 06:18:24 PM UTC 24 1592841581 ps
T377 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/382.prim_prince_test.1915117859 Aug 28 06:17:43 PM UTC 24 Aug 28 06:18:24 PM UTC 24 1801300558 ps
T378 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/367.prim_prince_test.4266625782 Aug 28 06:17:27 PM UTC 24 Aug 28 06:18:25 PM UTC 24 2557460718 ps
T379 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/400.prim_prince_test.165891026 Aug 28 06:18:06 PM UTC 24 Aug 28 06:18:25 PM UTC 24 784485201 ps
T380 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/387.prim_prince_test.1374157579 Aug 28 06:17:51 PM UTC 24 Aug 28 06:18:26 PM UTC 24 1511758407 ps
T381 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/383.prim_prince_test.1606546011 Aug 28 06:17:44 PM UTC 24 Aug 28 06:18:29 PM UTC 24 1977995853 ps
T382 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/397.prim_prince_test.3247687366 Aug 28 06:18:06 PM UTC 24 Aug 28 06:18:31 PM UTC 24 1060296856 ps
T383 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/393.prim_prince_test.3791884896 Aug 28 06:18:00 PM UTC 24 Aug 28 06:18:32 PM UTC 24 1362424119 ps
T384 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/364.prim_prince_test.2459867783 Aug 28 06:17:19 PM UTC 24 Aug 28 06:18:36 PM UTC 24 3441078876 ps
T385 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/373.prim_prince_test.2767213491 Aug 28 06:17:35 PM UTC 24 Aug 28 06:18:36 PM UTC 24 2698639603 ps
T386 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/394.prim_prince_test.2271977410 Aug 28 06:18:02 PM UTC 24 Aug 28 06:18:36 PM UTC 24 1509129344 ps
T387 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/391.prim_prince_test.4027585269 Aug 28 06:17:58 PM UTC 24 Aug 28 06:18:37 PM UTC 24 1669460905 ps
T388 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/384.prim_prince_test.3816304417 Aug 28 06:17:48 PM UTC 24 Aug 28 06:18:37 PM UTC 24 2183208721 ps
T389 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/363.prim_prince_test.2912808831 Aug 28 06:17:18 PM UTC 24 Aug 28 06:18:40 PM UTC 24 3698956375 ps
T390 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/379.prim_prince_test.2590361086 Aug 28 06:17:39 PM UTC 24 Aug 28 06:18:41 PM UTC 24 2764249270 ps
T391 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/374.prim_prince_test.3348795048 Aug 28 06:17:35 PM UTC 24 Aug 28 06:18:42 PM UTC 24 2983300267 ps
T392 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/369.prim_prince_test.2518078243 Aug 28 06:17:28 PM UTC 24 Aug 28 06:18:43 PM UTC 24 3306605730 ps
T393 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/375.prim_prince_test.1001584110 Aug 28 06:17:35 PM UTC 24 Aug 28 06:18:45 PM UTC 24 3119780698 ps
T394 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/403.prim_prince_test.359465820 Aug 28 06:18:11 PM UTC 24 Aug 28 06:18:51 PM UTC 24 1759705126 ps
T395 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/381.prim_prince_test.1221644681 Aug 28 06:17:41 PM UTC 24 Aug 28 06:18:58 PM UTC 24 3427272646 ps
T396 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/411.prim_prince_test.4248567556 Aug 28 06:18:25 PM UTC 24 Aug 28 06:19:00 PM UTC 24 1520967191 ps
T397 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/388.prim_prince_test.3679092522 Aug 28 06:17:51 PM UTC 24 Aug 28 06:19:00 PM UTC 24 3109200444 ps
T398 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/421.prim_prince_test.1651658947 Aug 28 06:18:37 PM UTC 24 Aug 28 06:19:06 PM UTC 24 1183782648 ps
T399 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/398.prim_prince_test.3200856407 Aug 28 06:18:06 PM UTC 24 Aug 28 06:19:06 PM UTC 24 2651654393 ps
T400 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/396.prim_prince_test.2708577784 Aug 28 06:18:05 PM UTC 24 Aug 28 06:19:06 PM UTC 24 2736703059 ps
T401 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/401.prim_prince_test.4002529874 Aug 28 06:18:08 PM UTC 24 Aug 28 06:19:08 PM UTC 24 2699968570 ps
T402 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/427.prim_prince_test.2924962481 Aug 28 06:18:43 PM UTC 24 Aug 28 06:19:09 PM UTC 24 1068460924 ps
T403 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/392.prim_prince_test.726925195 Aug 28 06:17:58 PM UTC 24 Aug 28 06:19:11 PM UTC 24 3241954980 ps
T404 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/416.prim_prince_test.288564709 Aug 28 06:18:27 PM UTC 24 Aug 28 06:19:11 PM UTC 24 1927545167 ps
T405 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/389.prim_prince_test.1660179699 Aug 28 06:17:53 PM UTC 24 Aug 28 06:19:11 PM UTC 24 3489167842 ps
T406 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/406.prim_prince_test.2116778991 Aug 28 06:18:17 PM UTC 24 Aug 28 06:19:12 PM UTC 24 2408899329 ps
T407 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/408.prim_prince_test.1078816869 Aug 28 06:18:22 PM UTC 24 Aug 28 06:19:13 PM UTC 24 2288823858 ps
T408 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/405.prim_prince_test.1620117385 Aug 28 06:18:12 PM UTC 24 Aug 28 06:19:13 PM UTC 24 2767333832 ps
T409 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/423.prim_prince_test.1918430632 Aug 28 06:18:38 PM UTC 24 Aug 28 06:19:14 PM UTC 24 1555986936 ps
T410 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/399.prim_prince_test.2319194704 Aug 28 06:18:06 PM UTC 24 Aug 28 06:19:15 PM UTC 24 3052275690 ps
T411 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/415.prim_prince_test.3342344378 Aug 28 06:18:27 PM UTC 24 Aug 28 06:19:17 PM UTC 24 2253552186 ps
T412 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/428.prim_prince_test.2307154967 Aug 28 06:18:44 PM UTC 24 Aug 28 06:19:19 PM UTC 24 1512652568 ps
T413 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/425.prim_prince_test.1158100263 Aug 28 06:18:41 PM UTC 24 Aug 28 06:19:20 PM UTC 24 1722604433 ps
T414 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/402.prim_prince_test.2666746242 Aug 28 06:18:10 PM UTC 24 Aug 28 06:19:22 PM UTC 24 3222547183 ps
T415 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/414.prim_prince_test.2132024647 Aug 28 06:18:26 PM UTC 24 Aug 28 06:19:22 PM UTC 24 2488390809 ps
T416 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/395.prim_prince_test.446826528 Aug 28 06:18:02 PM UTC 24 Aug 28 06:19:24 PM UTC 24 3712793514 ps
T417 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/412.prim_prince_test.3072317049 Aug 28 06:18:25 PM UTC 24 Aug 28 06:19:25 PM UTC 24 2667743508 ps
T418 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/413.prim_prince_test.232486190 Aug 28 06:18:26 PM UTC 24 Aug 28 06:19:25 PM UTC 24 2609680193 ps
T419 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/404.prim_prince_test.2062820767 Aug 28 06:18:12 PM UTC 24 Aug 28 06:19:27 PM UTC 24 3326552212 ps
T420 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/417.prim_prince_test.1788124218 Aug 28 06:18:30 PM UTC 24 Aug 28 06:19:30 PM UTC 24 2678209496 ps
T421 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/407.prim_prince_test.24205151 Aug 28 06:18:20 PM UTC 24 Aug 28 06:19:31 PM UTC 24 3158207462 ps
T422 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/420.prim_prince_test.3877825470 Aug 28 06:18:37 PM UTC 24 Aug 28 06:19:32 PM UTC 24 2391255740 ps
T423 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/444.prim_prince_test.848756555 Aug 28 06:19:15 PM UTC 24 Aug 28 06:19:34 PM UTC 24 817020251 ps
T424 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/418.prim_prince_test.2219618192 Aug 28 06:18:32 PM UTC 24 Aug 28 06:19:35 PM UTC 24 2802335420 ps
T425 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/410.prim_prince_test.2475195558 Aug 28 06:18:24 PM UTC 24 Aug 28 06:19:35 PM UTC 24 3209929172 ps
T426 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/445.prim_prince_test.3930314233 Aug 28 06:19:15 PM UTC 24 Aug 28 06:19:35 PM UTC 24 862927708 ps
T427 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/419.prim_prince_test.2906846593 Aug 28 06:18:33 PM UTC 24 Aug 28 06:19:36 PM UTC 24 2777089434 ps
T428 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/442.prim_prince_test.3098575410 Aug 28 06:19:12 PM UTC 24 Aug 28 06:19:39 PM UTC 24 1118275382 ps
T429 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/432.prim_prince_test.1357417956 Aug 28 06:19:01 PM UTC 24 Aug 28 06:19:41 PM UTC 24 1753870121 ps
T430 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/434.prim_prince_test.2973871531 Aug 28 06:19:06 PM UTC 24 Aug 28 06:19:42 PM UTC 24 1556052583 ps
T431 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/422.prim_prince_test.547082002 Aug 28 06:18:38 PM UTC 24 Aug 28 06:19:44 PM UTC 24 2945756187 ps
T432 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/409.prim_prince_test.1736424788 Aug 28 06:18:23 PM UTC 24 Aug 28 06:19:44 PM UTC 24 3687538999 ps
T433 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/424.prim_prince_test.3606158310 Aug 28 06:18:39 PM UTC 24 Aug 28 06:19:48 PM UTC 24 3073198159 ps
T434 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/446.prim_prince_test.1630618300 Aug 28 06:19:16 PM UTC 24 Aug 28 06:19:49 PM UTC 24 1444147816 ps
T435 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/458.prim_prince_test.1336748946 Aug 28 06:19:33 PM UTC 24 Aug 28 06:19:52 PM UTC 24 793773196 ps
T436 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/437.prim_prince_test.3455442221 Aug 28 06:19:09 PM UTC 24 Aug 28 06:19:53 PM UTC 24 1960625117 ps
T437 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/430.prim_prince_test.187292634 Aug 28 06:18:52 PM UTC 24 Aug 28 06:19:53 PM UTC 24 2747339464 ps
T438 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/448.prim_prince_test.3508015233 Aug 28 06:19:21 PM UTC 24 Aug 28 06:19:54 PM UTC 24 1447195271 ps
T439 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/462.prim_prince_test.243673188 Aug 28 06:19:37 PM UTC 24 Aug 28 06:19:57 PM UTC 24 850161040 ps
T440 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/426.prim_prince_test.3656226290 Aug 28 06:18:42 PM UTC 24 Aug 28 06:19:58 PM UTC 24 3390089318 ps
T441 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/456.prim_prince_test.3928902534 Aug 28 06:19:31 PM UTC 24 Aug 28 06:19:58 PM UTC 24 1192677494 ps
T442 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/438.prim_prince_test.4277230132 Aug 28 06:19:10 PM UTC 24 Aug 28 06:19:59 PM UTC 24 2171093656 ps
T443 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/429.prim_prince_test.794793386 Aug 28 06:18:45 PM UTC 24 Aug 28 06:20:00 PM UTC 24 3316635160 ps
T444 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/443.prim_prince_test.3749455304 Aug 28 06:19:14 PM UTC 24 Aug 28 06:20:00 PM UTC 24 2061310527 ps
T445 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/465.prim_prince_test.3379618440 Aug 28 06:19:42 PM UTC 24 Aug 28 06:20:02 PM UTC 24 855339288 ps
T446 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/469.prim_prince_test.3075524995 Aug 28 06:19:46 PM UTC 24 Aug 28 06:20:04 PM UTC 24 774633355 ps
T447 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/468.prim_prince_test.3011789657 Aug 28 06:19:46 PM UTC 24 Aug 28 06:20:05 PM UTC 24 812860055 ps
T448 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/463.prim_prince_test.463584958 Aug 28 06:19:37 PM UTC 24 Aug 28 06:20:05 PM UTC 24 1246666156 ps
T449 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/433.prim_prince_test.2470519968 Aug 28 06:19:01 PM UTC 24 Aug 28 06:20:06 PM UTC 24 2885142372 ps
T450 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/431.prim_prince_test.1949069796 Aug 28 06:18:59 PM UTC 24 Aug 28 06:20:07 PM UTC 24 3050365730 ps
T451 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/452.prim_prince_test.3136669846 Aug 28 06:19:25 PM UTC 24 Aug 28 06:20:11 PM UTC 24 2041855331 ps
T452 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/435.prim_prince_test.2589261947 Aug 28 06:19:06 PM UTC 24 Aug 28 06:20:12 PM UTC 24 2916422846 ps
T453 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/436.prim_prince_test.3571864077 Aug 28 06:19:08 PM UTC 24 Aug 28 06:20:13 PM UTC 24 2911746796 ps
T454 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/470.prim_prince_test.837931360 Aug 28 06:19:49 PM UTC 24 Aug 28 06:20:13 PM UTC 24 1057975299 ps
T455 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/440.prim_prince_test.298307955 Aug 28 06:19:11 PM UTC 24 Aug 28 06:20:17 PM UTC 24 2911069159 ps
T456 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/451.prim_prince_test.962618861 Aug 28 06:19:23 PM UTC 24 Aug 28 06:20:19 PM UTC 24 2486171134 ps
T457 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/447.prim_prince_test.3215515813 Aug 28 06:19:18 PM UTC 24 Aug 28 06:20:21 PM UTC 24 2798251432 ps
T458 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/464.prim_prince_test.58388797 Aug 28 06:19:39 PM UTC 24 Aug 28 06:20:21 PM UTC 24 1860681952 ps
T459 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/441.prim_prince_test.2863515152 Aug 28 06:19:12 PM UTC 24 Aug 28 06:20:21 PM UTC 24 3079725000 ps
T460 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/460.prim_prince_test.3925193009 Aug 28 06:19:37 PM UTC 24 Aug 28 06:20:21 PM UTC 24 1975579140 ps
T461 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/475.prim_prince_test.4091317097 Aug 28 06:19:55 PM UTC 24 Aug 28 06:20:23 PM UTC 24 1219982955 ps
T462 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/482.prim_prince_test.1805695169 Aug 28 06:20:03 PM UTC 24 Aug 28 06:20:23 PM UTC 24 809762834 ps
T463 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/454.prim_prince_test.291682548 Aug 28 06:19:25 PM UTC 24 Aug 28 06:20:23 PM UTC 24 2574079594 ps
T464 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/467.prim_prince_test.821520354 Aug 28 06:19:43 PM UTC 24 Aug 28 06:20:23 PM UTC 24 1750544758 ps
T465 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/478.prim_prince_test.2508486794 Aug 28 06:19:59 PM UTC 24 Aug 28 06:20:25 PM UTC 24 1097052728 ps
T466 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/457.prim_prince_test.1725145627 Aug 28 06:19:32 PM UTC 24 Aug 28 06:20:25 PM UTC 24 2368992350 ps
T467 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/455.prim_prince_test.4242575745 Aug 28 06:19:28 PM UTC 24 Aug 28 06:20:27 PM UTC 24 2657823647 ps
T468 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/474.prim_prince_test.1707137263 Aug 28 06:19:55 PM UTC 24 Aug 28 06:20:29 PM UTC 24 1523510956 ps
T469 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/449.prim_prince_test.4221271765 Aug 28 06:19:21 PM UTC 24 Aug 28 06:20:31 PM UTC 24 3142754645 ps
T470 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/439.prim_prince_test.3528766021 Aug 28 06:19:11 PM UTC 24 Aug 28 06:20:31 PM UTC 24 3593654402 ps
T471 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/477.prim_prince_test.1665624211 Aug 28 06:19:59 PM UTC 24 Aug 28 06:20:32 PM UTC 24 1435422363 ps
T472 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/453.prim_prince_test.3029743086 Aug 28 06:19:25 PM UTC 24 Aug 28 06:20:33 PM UTC 24 3039741208 ps
T473 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/479.prim_prince_test.225889822 Aug 28 06:20:00 PM UTC 24 Aug 28 06:20:36 PM UTC 24 1547563347 ps
T474 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/459.prim_prince_test.3142267029 Aug 28 06:19:35 PM UTC 24 Aug 28 06:20:38 PM UTC 24 2824822352 ps
T475 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/461.prim_prince_test.2117360235 Aug 28 06:19:37 PM UTC 24 Aug 28 06:20:39 PM UTC 24 2758063615 ps
T476 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/450.prim_prince_test.3616931913 Aug 28 06:19:23 PM UTC 24 Aug 28 06:20:39 PM UTC 24 3435837271 ps
T477 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/492.prim_prince_test.3444783059 Aug 28 06:20:17 PM UTC 24 Aug 28 06:20:42 PM UTC 24 1051337293 ps
T478 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/488.prim_prince_test.657932723 Aug 28 06:20:12 PM UTC 24 Aug 28 06:20:42 PM UTC 24 1329878039 ps
T479 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/484.prim_prince_test.1669782458 Aug 28 06:20:06 PM UTC 24 Aug 28 06:20:42 PM UTC 24 1561412328 ps
T480 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/466.prim_prince_test.436932031 Aug 28 06:19:43 PM UTC 24 Aug 28 06:20:43 PM UTC 24 2676693022 ps
T481 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/485.prim_prince_test.1781865193 Aug 28 06:20:06 PM UTC 24 Aug 28 06:20:47 PM UTC 24 1796650853 ps
T482 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/494.prim_prince_test.2556818737 Aug 28 06:20:22 PM UTC 24 Aug 28 06:20:48 PM UTC 24 1133345199 ps
T483 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/471.prim_prince_test.1661241519 Aug 28 06:19:50 PM UTC 24 Aug 28 06:20:49 PM UTC 24 2657598764 ps
T484 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/481.prim_prince_test.3497474668 Aug 28 06:20:02 PM UTC 24 Aug 28 06:20:51 PM UTC 24 2213858910 ps
T485 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/493.prim_prince_test.2338180915 Aug 28 06:20:20 PM UTC 24 Aug 28 06:20:54 PM UTC 24 1482649806 ps
T486 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/476.prim_prince_test.2374225140 Aug 28 06:19:58 PM UTC 24 Aug 28 06:20:57 PM UTC 24 2625314652 ps
T487 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/487.prim_prince_test.967755674 Aug 28 06:20:08 PM UTC 24 Aug 28 06:21:00 PM UTC 24 2318047313 ps
T488 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/496.prim_prince_test.1818294455 Aug 28 06:20:22 PM UTC 24 Aug 28 06:21:01 PM UTC 24 1731734225 ps
T489 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/480.prim_prince_test.1311216074 Aug 28 06:20:02 PM UTC 24 Aug 28 06:21:03 PM UTC 24 2744272193 ps
T490 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/489.prim_prince_test.1465057325 Aug 28 06:20:13 PM UTC 24 Aug 28 06:21:06 PM UTC 24 2384244348 ps
T491 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/473.prim_prince_test.635972978 Aug 28 06:19:55 PM UTC 24 Aug 28 06:21:07 PM UTC 24 3295438359 ps
T492 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/497.prim_prince_test.937308112 Aug 28 06:20:22 PM UTC 24 Aug 28 06:21:12 PM UTC 24 2194539813 ps
T493 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/483.prim_prince_test.3632621576 Aug 28 06:20:05 PM UTC 24 Aug 28 06:21:13 PM UTC 24 3095046347 ps
T494 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/472.prim_prince_test.4195483291 Aug 28 06:19:53 PM UTC 24 Aug 28 06:21:13 PM UTC 24 3644115219 ps
T495 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/491.prim_prince_test.854629151 Aug 28 06:20:14 PM UTC 24 Aug 28 06:21:13 PM UTC 24 2670754498 ps
T496 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/499.prim_prince_test.2122643269 Aug 28 06:20:24 PM UTC 24 Aug 28 06:21:14 PM UTC 24 2298447722 ps
T497 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/486.prim_prince_test.2178876714 Aug 28 06:20:08 PM UTC 24 Aug 28 06:21:18 PM UTC 24 3154234039 ps
T498 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/490.prim_prince_test.1993976571 Aug 28 06:20:13 PM UTC 24 Aug 28 06:21:19 PM UTC 24 2985051051 ps
T499 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/498.prim_prince_test.3968746186 Aug 28 06:20:22 PM UTC 24 Aug 28 06:21:37 PM UTC 24 3137904200 ps
T500 /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/495.prim_prince_test.554371709 Aug 28 06:20:22 PM UTC 24 Aug 28 06:21:38 PM UTC 24 3143172289 ps

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/0.prim_prince_test.929197182
Short name T5
Test name
Test status
Simulation time 1545319945 ps
CPU time 28.55 seconds
Started Aug 28 06:08:25 PM UTC 24
Finished Aug 28 06:09:02 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=929197182 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 0.prim_prince_test.929197182
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/0.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/1.prim_prince_test.4141467327
Short name T1
Test name
Test status
Simulation time 894849044 ps
CPU time 16.16 seconds
Started Aug 28 06:08:26 PM UTC 24
Finished Aug 28 06:08:48 PM UTC 24
Peak memory 154652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4141467327 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 1.prim_prince_test.4141467327
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/1.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/10.prim_prince_test.834842017
Short name T22
Test name
Test status
Simulation time 2909663500 ps
CPU time 51.95 seconds
Started Aug 28 06:08:30 PM UTC 24
Finished Aug 28 06:09:36 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=834842017 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 10.prim_prince_test.834842017
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/10.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/100.prim_prince_test.4157429516
Short name T83
Test name
Test status
Simulation time 798261267 ps
CPU time 14.6 seconds
Started Aug 28 06:10:45 PM UTC 24
Finished Aug 28 06:11:04 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4157429516 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 100.prim_prince_test.4157429516
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/100.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/101.prim_prince_test.1305463921
Short name T89
Test name
Test status
Simulation time 1151008114 ps
CPU time 20.83 seconds
Started Aug 28 06:10:46 PM UTC 24
Finished Aug 28 06:11:13 PM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1305463921 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 101.prim_prince_test.1305463921
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/101.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/102.prim_prince_test.2557899297
Short name T99
Test name
Test status
Simulation time 1610083863 ps
CPU time 28.56 seconds
Started Aug 28 06:10:48 PM UTC 24
Finished Aug 28 06:11:25 PM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2557899297 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 102.prim_prince_test.2557899297
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/102.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/103.prim_prince_test.1555260818
Short name T103
Test name
Test status
Simulation time 1786971745 ps
CPU time 31.94 seconds
Started Aug 28 06:10:50 PM UTC 24
Finished Aug 28 06:11:31 PM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1555260818 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 103.prim_prince_test.1555260818
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/103.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/104.prim_prince_test.2591968216
Short name T127
Test name
Test status
Simulation time 3494189871 ps
CPU time 61.59 seconds
Started Aug 28 06:10:50 PM UTC 24
Finished Aug 28 06:12:09 PM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2591968216 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 104.prim_prince_test.2591968216
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/104.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/105.prim_prince_test.4066184995
Short name T114
Test name
Test status
Simulation time 2520584066 ps
CPU time 44.54 seconds
Started Aug 28 06:10:51 PM UTC 24
Finished Aug 28 06:11:48 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4066184995 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 105.prim_prince_test.4066184995
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/105.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/106.prim_prince_test.3207544468
Short name T93
Test name
Test status
Simulation time 1021462536 ps
CPU time 18.74 seconds
Started Aug 28 06:10:54 PM UTC 24
Finished Aug 28 06:11:18 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3207544468 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 106.prim_prince_test.3207544468
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/106.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/107.prim_prince_test.3270602601
Short name T91
Test name
Test status
Simulation time 911323647 ps
CPU time 16.32 seconds
Started Aug 28 06:10:55 PM UTC 24
Finished Aug 28 06:11:16 PM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3270602601 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 107.prim_prince_test.3270602601
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/107.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/108.prim_prince_test.3663080283
Short name T128
Test name
Test status
Simulation time 3201923562 ps
CPU time 56.75 seconds
Started Aug 28 06:10:58 PM UTC 24
Finished Aug 28 06:12:10 PM UTC 24
Peak memory 155764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3663080283 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 108.prim_prince_test.3663080283
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/108.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/109.prim_prince_test.1451056717
Short name T92
Test name
Test status
Simulation time 849864126 ps
CPU time 15.31 seconds
Started Aug 28 06:10:58 PM UTC 24
Finished Aug 28 06:11:18 PM UTC 24
Peak memory 154308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1451056717 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 109.prim_prince_test.1451056717
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/109.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/11.prim_prince_test.3823574838
Short name T3
Test name
Test status
Simulation time 998684051 ps
CPU time 18.01 seconds
Started Aug 28 06:08:30 PM UTC 24
Finished Aug 28 06:08:53 PM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3823574838 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 11.prim_prince_test.3823574838
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/11.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/110.prim_prince_test.3298362404
Short name T108
Test name
Test status
Simulation time 1857634938 ps
CPU time 33.35 seconds
Started Aug 28 06:10:59 PM UTC 24
Finished Aug 28 06:11:41 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3298362404 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 110.prim_prince_test.3298362404
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/110.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/111.prim_prince_test.623358868
Short name T118
Test name
Test status
Simulation time 2378189864 ps
CPU time 42.26 seconds
Started Aug 28 06:11:00 PM UTC 24
Finished Aug 28 06:11:54 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=623358868 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 111.prim_prince_test.623358868
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/111.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/112.prim_prince_test.3070323181
Short name T120
Test name
Test status
Simulation time 2403792676 ps
CPU time 42.71 seconds
Started Aug 28 06:11:02 PM UTC 24
Finished Aug 28 06:11:57 PM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3070323181 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 112.prim_prince_test.3070323181
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/112.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/113.prim_prince_test.1583123641
Short name T123
Test name
Test status
Simulation time 2617028210 ps
CPU time 45.92 seconds
Started Aug 28 06:11:02 PM UTC 24
Finished Aug 28 06:12:01 PM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1583123641 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 113.prim_prince_test.1583123641
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/113.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/114.prim_prince_test.425827808
Short name T138
Test name
Test status
Simulation time 3542312524 ps
CPU time 63.27 seconds
Started Aug 28 06:11:05 PM UTC 24
Finished Aug 28 06:12:25 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=425827808 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 114.prim_prince_test.425827808
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/114.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/115.prim_prince_test.3227526270
Short name T98
Test name
Test status
Simulation time 780532757 ps
CPU time 14.3 seconds
Started Aug 28 06:11:06 PM UTC 24
Finished Aug 28 06:11:25 PM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3227526270 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 115.prim_prince_test.3227526270
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/115.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/116.prim_prince_test.3015829589
Short name T121
Test name
Test status
Simulation time 2243944237 ps
CPU time 40.1 seconds
Started Aug 28 06:11:07 PM UTC 24
Finished Aug 28 06:11:59 PM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3015829589 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 116.prim_prince_test.3015829589
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/116.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/117.prim_prince_test.3423204915
Short name T122
Test name
Test status
Simulation time 2275399421 ps
CPU time 40.84 seconds
Started Aug 28 06:11:08 PM UTC 24
Finished Aug 28 06:12:00 PM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3423204915 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 117.prim_prince_test.3423204915
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/117.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/118.prim_prince_test.388896460
Short name T132
Test name
Test status
Simulation time 2639752979 ps
CPU time 47.07 seconds
Started Aug 28 06:11:12 PM UTC 24
Finished Aug 28 06:12:12 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=388896460 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 118.prim_prince_test.388896460
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/118.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/119.prim_prince_test.500155956
Short name T111
Test name
Test status
Simulation time 1360171769 ps
CPU time 24.31 seconds
Started Aug 28 06:11:13 PM UTC 24
Finished Aug 28 06:11:45 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=500155956 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 119.prim_prince_test.500155956
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/119.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/12.prim_prince_test.1261673903
Short name T12
Test name
Test status
Simulation time 1962605443 ps
CPU time 35.16 seconds
Started Aug 28 06:08:30 PM UTC 24
Finished Aug 28 06:09:15 PM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1261673903 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 12.prim_prince_test.1261673903
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/12.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/120.prim_prince_test.3831369506
Short name T115
Test name
Test status
Simulation time 1549765658 ps
CPU time 27.58 seconds
Started Aug 28 06:11:14 PM UTC 24
Finished Aug 28 06:11:50 PM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3831369506 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 120.prim_prince_test.3831369506
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/120.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/121.prim_prince_test.1273051107
Short name T125
Test name
Test status
Simulation time 2036767954 ps
CPU time 36.1 seconds
Started Aug 28 06:11:16 PM UTC 24
Finished Aug 28 06:12:02 PM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1273051107 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 121.prim_prince_test.1273051107
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/121.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/122.prim_prince_test.906231441
Short name T130
Test name
Test status
Simulation time 2418754875 ps
CPU time 42.66 seconds
Started Aug 28 06:11:17 PM UTC 24
Finished Aug 28 06:12:11 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=906231441 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 122.prim_prince_test.906231441
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/122.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/123.prim_prince_test.3248592456
Short name T112
Test name
Test status
Simulation time 1224696005 ps
CPU time 21.94 seconds
Started Aug 28 06:11:19 PM UTC 24
Finished Aug 28 06:11:47 PM UTC 24
Peak memory 154044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3248592456 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 123.prim_prince_test.3248592456
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/123.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/124.prim_prince_test.2208628402
Short name T126
Test name
Test status
Simulation time 2196341197 ps
CPU time 38.86 seconds
Started Aug 28 06:11:19 PM UTC 24
Finished Aug 28 06:12:09 PM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2208628402 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 124.prim_prince_test.2208628402
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/124.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/125.prim_prince_test.1096694722
Short name T109
Test name
Test status
Simulation time 923427317 ps
CPU time 16.68 seconds
Started Aug 28 06:11:20 PM UTC 24
Finished Aug 28 06:11:42 PM UTC 24
Peak memory 156056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1096694722 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 125.prim_prince_test.1096694722
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/125.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/126.prim_prince_test.2174915303
Short name T119
Test name
Test status
Simulation time 1354169621 ps
CPU time 24.39 seconds
Started Aug 28 06:11:23 PM UTC 24
Finished Aug 28 06:11:54 PM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2174915303 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 126.prim_prince_test.2174915303
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/126.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/127.prim_prince_test.3841188314
Short name T144
Test name
Test status
Simulation time 3132936824 ps
CPU time 55.16 seconds
Started Aug 28 06:11:23 PM UTC 24
Finished Aug 28 06:12:33 PM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3841188314 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 127.prim_prince_test.3841188314
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/127.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/128.prim_prince_test.3238733948
Short name T151
Test name
Test status
Simulation time 3521850475 ps
CPU time 62.33 seconds
Started Aug 28 06:11:26 PM UTC 24
Finished Aug 28 06:12:45 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3238733948 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 128.prim_prince_test.3238733948
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/128.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/129.prim_prince_test.3476524944
Short name T129
Test name
Test status
Simulation time 1984989200 ps
CPU time 34.91 seconds
Started Aug 28 06:11:26 PM UTC 24
Finished Aug 28 06:12:11 PM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3476524944 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 129.prim_prince_test.3476524944
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/129.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/13.prim_prince_test.2634569236
Short name T40
Test name
Test status
Simulation time 3666302699 ps
CPU time 65.46 seconds
Started Aug 28 06:08:31 PM UTC 24
Finished Aug 28 06:09:54 PM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2634569236 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 13.prim_prince_test.2634569236
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/13.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/130.prim_prince_test.4171346566
Short name T140
Test name
Test status
Simulation time 2695369283 ps
CPU time 47.92 seconds
Started Aug 28 06:11:26 PM UTC 24
Finished Aug 28 06:12:27 PM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4171346566 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 130.prim_prince_test.4171346566
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/130.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/131.prim_prince_test.813761767
Short name T113
Test name
Test status
Simulation time 901676667 ps
CPU time 16.47 seconds
Started Aug 28 06:11:26 PM UTC 24
Finished Aug 28 06:11:48 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=813761767 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 131.prim_prince_test.813761767
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/131.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/132.prim_prince_test.1218585735
Short name T137
Test name
Test status
Simulation time 2485209520 ps
CPU time 44.3 seconds
Started Aug 28 06:11:27 PM UTC 24
Finished Aug 28 06:12:24 PM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1218585735 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 132.prim_prince_test.1218585735
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/132.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/133.prim_prince_test.46720231
Short name T116
Test name
Test status
Simulation time 886426419 ps
CPU time 16.03 seconds
Started Aug 28 06:11:29 PM UTC 24
Finished Aug 28 06:11:50 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=46720231 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 133.prim_prince_test.46720231
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/133.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/134.prim_prince_test.2392119419
Short name T117
Test name
Test status
Simulation time 931851473 ps
CPU time 17.14 seconds
Started Aug 28 06:11:30 PM UTC 24
Finished Aug 28 06:11:53 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2392119419 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 134.prim_prince_test.2392119419
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/134.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/135.prim_prince_test.2351232938
Short name T148
Test name
Test status
Simulation time 2950320472 ps
CPU time 53.04 seconds
Started Aug 28 06:11:32 PM UTC 24
Finished Aug 28 06:12:40 PM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2351232938 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 135.prim_prince_test.2351232938
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/135.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/136.prim_prince_test.1421260424
Short name T142
Test name
Test status
Simulation time 2572385486 ps
CPU time 45.68 seconds
Started Aug 28 06:11:33 PM UTC 24
Finished Aug 28 06:12:31 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1421260424 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 136.prim_prince_test.1421260424
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/136.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/137.prim_prince_test.2206325615
Short name T131
Test name
Test status
Simulation time 1628911577 ps
CPU time 29.2 seconds
Started Aug 28 06:11:34 PM UTC 24
Finished Aug 28 06:12:11 PM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2206325615 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 137.prim_prince_test.2206325615
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/137.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/138.prim_prince_test.3742972980
Short name T150
Test name
Test status
Simulation time 3100663573 ps
CPU time 55.23 seconds
Started Aug 28 06:11:35 PM UTC 24
Finished Aug 28 06:12:45 PM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3742972980 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 138.prim_prince_test.3742972980
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/138.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/139.prim_prince_test.3065468552
Short name T161
Test name
Test status
Simulation time 3697696113 ps
CPU time 65.47 seconds
Started Aug 28 06:11:35 PM UTC 24
Finished Aug 28 06:12:58 PM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3065468552 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 139.prim_prince_test.3065468552
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/139.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/14.prim_prince_test.666927645
Short name T35
Test name
Test status
Simulation time 3427744239 ps
CPU time 60.92 seconds
Started Aug 28 06:08:31 PM UTC 24
Finished Aug 28 06:09:48 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=666927645 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 14.prim_prince_test.666927645
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/14.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/140.prim_prince_test.2186146632
Short name T136
Test name
Test status
Simulation time 1799328104 ps
CPU time 31.69 seconds
Started Aug 28 06:11:42 PM UTC 24
Finished Aug 28 06:12:23 PM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2186146632 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 140.prim_prince_test.2186146632
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/140.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/141.prim_prince_test.3405546863
Short name T124
Test name
Test status
Simulation time 751859785 ps
CPU time 13.86 seconds
Started Aug 28 06:11:43 PM UTC 24
Finished Aug 28 06:12:01 PM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3405546863 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 141.prim_prince_test.3405546863
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/141.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/142.prim_prince_test.3517305315
Short name T163
Test name
Test status
Simulation time 3410314940 ps
CPU time 60.59 seconds
Started Aug 28 06:11:44 PM UTC 24
Finished Aug 28 06:13:01 PM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3517305315 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 142.prim_prince_test.3517305315
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/142.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/143.prim_prince_test.3566007588
Short name T149
Test name
Test status
Simulation time 2428691058 ps
CPU time 43.14 seconds
Started Aug 28 06:11:46 PM UTC 24
Finished Aug 28 06:12:41 PM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3566007588 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 143.prim_prince_test.3566007588
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/143.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/144.prim_prince_test.739922175
Short name T159
Test name
Test status
Simulation time 3036946662 ps
CPU time 53.4 seconds
Started Aug 28 06:11:48 PM UTC 24
Finished Aug 28 06:12:57 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=739922175 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 144.prim_prince_test.739922175
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/144.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/145.prim_prince_test.670135680
Short name T167
Test name
Test status
Simulation time 3619217011 ps
CPU time 63.56 seconds
Started Aug 28 06:11:48 PM UTC 24
Finished Aug 28 06:13:09 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=670135680 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 145.prim_prince_test.670135680
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/145.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/146.prim_prince_test.4006149593
Short name T135
Test name
Test status
Simulation time 1281932522 ps
CPU time 23.32 seconds
Started Aug 28 06:11:49 PM UTC 24
Finished Aug 28 06:12:20 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4006149593 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 146.prim_prince_test.4006149593
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/146.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/147.prim_prince_test.2760824904
Short name T133
Test name
Test status
Simulation time 994612880 ps
CPU time 17.71 seconds
Started Aug 28 06:11:50 PM UTC 24
Finished Aug 28 06:12:14 PM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2760824904 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 147.prim_prince_test.2760824904
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/147.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/148.prim_prince_test.1401774104
Short name T152
Test name
Test status
Simulation time 2472645191 ps
CPU time 43.64 seconds
Started Aug 28 06:11:51 PM UTC 24
Finished Aug 28 06:12:47 PM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1401774104 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 148.prim_prince_test.1401774104
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/148.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/149.prim_prince_test.634650113
Short name T143
Test name
Test status
Simulation time 1652169803 ps
CPU time 29.7 seconds
Started Aug 28 06:11:54 PM UTC 24
Finished Aug 28 06:12:32 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=634650113 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 149.prim_prince_test.634650113
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/149.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/15.prim_prince_test.3431693683
Short name T9
Test name
Test status
Simulation time 1660679828 ps
CPU time 29.65 seconds
Started Aug 28 06:08:33 PM UTC 24
Finished Aug 28 06:09:11 PM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3431693683 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 15.prim_prince_test.3431693683
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/15.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/150.prim_prince_test.1596159378
Short name T154
Test name
Test status
Simulation time 2353451567 ps
CPU time 41.56 seconds
Started Aug 28 06:11:55 PM UTC 24
Finished Aug 28 06:12:48 PM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1596159378 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 150.prim_prince_test.1596159378
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/150.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/151.prim_prince_test.398559361
Short name T145
Test name
Test status
Simulation time 1882968023 ps
CPU time 33.63 seconds
Started Aug 28 06:11:56 PM UTC 24
Finished Aug 28 06:12:39 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=398559361 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 151.prim_prince_test.398559361
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/151.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/152.prim_prince_test.3110794574
Short name T153
Test name
Test status
Simulation time 2178719771 ps
CPU time 39.1 seconds
Started Aug 28 06:11:58 PM UTC 24
Finished Aug 28 06:12:48 PM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3110794574 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 152.prim_prince_test.3110794574
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/152.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/153.prim_prince_test.2172979341
Short name T134
Test name
Test status
Simulation time 827079885 ps
CPU time 15.1 seconds
Started Aug 28 06:11:59 PM UTC 24
Finished Aug 28 06:12:19 PM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2172979341 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 153.prim_prince_test.2172979341
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/153.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/154.prim_prince_test.3575302914
Short name T156
Test name
Test status
Simulation time 2236068913 ps
CPU time 39.85 seconds
Started Aug 28 06:12:01 PM UTC 24
Finished Aug 28 06:12:52 PM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3575302914 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 154.prim_prince_test.3575302914
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/154.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/155.prim_prince_test.414872486
Short name T170
Test name
Test status
Simulation time 3344145446 ps
CPU time 59.14 seconds
Started Aug 28 06:12:02 PM UTC 24
Finished Aug 28 06:13:17 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=414872486 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 155.prim_prince_test.414872486
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/155.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/156.prim_prince_test.3718187837
Short name T172
Test name
Test status
Simulation time 3522891734 ps
CPU time 62.4 seconds
Started Aug 28 06:12:02 PM UTC 24
Finished Aug 28 06:13:21 PM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3718187837 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 156.prim_prince_test.3718187837
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/156.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/157.prim_prince_test.3730077575
Short name T139
Test name
Test status
Simulation time 989318697 ps
CPU time 18.03 seconds
Started Aug 28 06:12:03 PM UTC 24
Finished Aug 28 06:12:27 PM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3730077575 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 157.prim_prince_test.3730077575
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/157.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/158.prim_prince_test.2153080474
Short name T141
Test name
Test status
Simulation time 838068785 ps
CPU time 15.34 seconds
Started Aug 28 06:12:09 PM UTC 24
Finished Aug 28 06:12:29 PM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2153080474 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 158.prim_prince_test.2153080474
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/158.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/159.prim_prince_test.3193215587
Short name T173
Test name
Test status
Simulation time 3243358205 ps
CPU time 57.48 seconds
Started Aug 28 06:12:09 PM UTC 24
Finished Aug 28 06:13:22 PM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3193215587 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 159.prim_prince_test.3193215587
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/159.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/16.prim_prince_test.3348663720
Short name T4
Test name
Test status
Simulation time 991815250 ps
CPU time 18.04 seconds
Started Aug 28 06:08:33 PM UTC 24
Finished Aug 28 06:08:56 PM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3348663720 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 16.prim_prince_test.3348663720
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/16.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/160.prim_prince_test.2707809937
Short name T175
Test name
Test status
Simulation time 3387406507 ps
CPU time 59.92 seconds
Started Aug 28 06:12:10 PM UTC 24
Finished Aug 28 06:13:27 PM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2707809937 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 160.prim_prince_test.2707809937
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/160.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/161.prim_prince_test.3667282120
Short name T147
Test name
Test status
Simulation time 1216432301 ps
CPU time 21.79 seconds
Started Aug 28 06:12:12 PM UTC 24
Finished Aug 28 06:12:40 PM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3667282120 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 161.prim_prince_test.3667282120
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/161.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/162.prim_prince_test.1138641654
Short name T177
Test name
Test status
Simulation time 3587968832 ps
CPU time 63.66 seconds
Started Aug 28 06:12:12 PM UTC 24
Finished Aug 28 06:13:32 PM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1138641654 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 162.prim_prince_test.1138641654
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/162.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/163.prim_prince_test.3690675462
Short name T146
Test name
Test status
Simulation time 1177220064 ps
CPU time 21.33 seconds
Started Aug 28 06:12:12 PM UTC 24
Finished Aug 28 06:12:39 PM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3690675462 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 163.prim_prince_test.3690675462
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/163.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/164.prim_prince_test.2526207279
Short name T158
Test name
Test status
Simulation time 1820006535 ps
CPU time 32.27 seconds
Started Aug 28 06:12:13 PM UTC 24
Finished Aug 28 06:12:54 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2526207279 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 164.prim_prince_test.2526207279
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/164.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/165.prim_prince_test.1057376195
Short name T180
Test name
Test status
Simulation time 3576414753 ps
CPU time 63.56 seconds
Started Aug 28 06:12:15 PM UTC 24
Finished Aug 28 06:13:35 PM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1057376195 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 165.prim_prince_test.1057376195
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/165.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/166.prim_prince_test.2722196907
Short name T155
Test name
Test status
Simulation time 1345157544 ps
CPU time 24.24 seconds
Started Aug 28 06:12:20 PM UTC 24
Finished Aug 28 06:12:51 PM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2722196907 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 166.prim_prince_test.2722196907
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/166.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/167.prim_prince_test.2577577872
Short name T157
Test name
Test status
Simulation time 1410187494 ps
CPU time 25.39 seconds
Started Aug 28 06:12:21 PM UTC 24
Finished Aug 28 06:12:54 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2577577872 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 167.prim_prince_test.2577577872
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/167.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/168.prim_prince_test.1977117307
Short name T178
Test name
Test status
Simulation time 3110076906 ps
CPU time 54.89 seconds
Started Aug 28 06:12:23 PM UTC 24
Finished Aug 28 06:13:33 PM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1977117307 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 168.prim_prince_test.1977117307
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/168.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/169.prim_prince_test.1707675529
Short name T165
Test name
Test status
Simulation time 1823527233 ps
CPU time 32.3 seconds
Started Aug 28 06:12:24 PM UTC 24
Finished Aug 28 06:13:06 PM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1707675529 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 169.prim_prince_test.1707675529
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/169.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/17.prim_prince_test.1992103510
Short name T7
Test name
Test status
Simulation time 1275115399 ps
CPU time 23.16 seconds
Started Aug 28 06:08:34 PM UTC 24
Finished Aug 28 06:09:04 PM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1992103510 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 17.prim_prince_test.1992103510
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/17.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/170.prim_prince_test.655820708
Short name T169
Test name
Test status
Simulation time 2152959252 ps
CPU time 38.35 seconds
Started Aug 28 06:12:26 PM UTC 24
Finished Aug 28 06:13:15 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=655820708 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 170.prim_prince_test.655820708
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/170.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/171.prim_prince_test.1603449251
Short name T185
Test name
Test status
Simulation time 3421444289 ps
CPU time 60.69 seconds
Started Aug 28 06:12:27 PM UTC 24
Finished Aug 28 06:13:44 PM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1603449251 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 171.prim_prince_test.1603449251
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/171.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/172.prim_prince_test.335818610
Short name T192
Test name
Test status
Simulation time 3671113062 ps
CPU time 65.11 seconds
Started Aug 28 06:12:28 PM UTC 24
Finished Aug 28 06:13:51 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=335818610 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 172.prim_prince_test.335818610
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/172.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/173.prim_prince_test.1820703662
Short name T160
Test name
Test status
Simulation time 1132685480 ps
CPU time 20.09 seconds
Started Aug 28 06:12:30 PM UTC 24
Finished Aug 28 06:12:57 PM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1820703662 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 173.prim_prince_test.1820703662
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/173.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/174.prim_prince_test.2701994669
Short name T179
Test name
Test status
Simulation time 2816712173 ps
CPU time 49.86 seconds
Started Aug 28 06:12:31 PM UTC 24
Finished Aug 28 06:13:35 PM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2701994669 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 174.prim_prince_test.2701994669
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/174.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/175.prim_prince_test.3398809464
Short name T174
Test name
Test status
Simulation time 2314267735 ps
CPU time 41.01 seconds
Started Aug 28 06:12:33 PM UTC 24
Finished Aug 28 06:13:25 PM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3398809464 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 175.prim_prince_test.3398809464
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/175.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/176.prim_prince_test.2393816210
Short name T183
Test name
Test status
Simulation time 2875808707 ps
CPU time 51.01 seconds
Started Aug 28 06:12:34 PM UTC 24
Finished Aug 28 06:13:38 PM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2393816210 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 176.prim_prince_test.2393816210
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/176.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/177.prim_prince_test.2601529454
Short name T162
Test name
Test status
Simulation time 875220924 ps
CPU time 15.93 seconds
Started Aug 28 06:12:40 PM UTC 24
Finished Aug 28 06:13:01 PM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2601529454 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 177.prim_prince_test.2601529454
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/177.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/178.prim_prince_test.488910254
Short name T199
Test name
Test status
Simulation time 3610067932 ps
CPU time 63.79 seconds
Started Aug 28 06:12:40 PM UTC 24
Finished Aug 28 06:14:01 PM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=488910254 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 178.prim_prince_test.488910254
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/178.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/179.prim_prince_test.1726246756
Short name T164
Test name
Test status
Simulation time 944710552 ps
CPU time 17.26 seconds
Started Aug 28 06:12:41 PM UTC 24
Finished Aug 28 06:13:04 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1726246756 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 179.prim_prince_test.1726246756
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/179.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/18.prim_prince_test.402187442
Short name T6
Test name
Test status
Simulation time 1215076934 ps
CPU time 22.14 seconds
Started Aug 28 06:08:35 PM UTC 24
Finished Aug 28 06:09:04 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=402187442 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 18.prim_prince_test.402187442
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/18.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/180.prim_prince_test.3449671492
Short name T166
Test name
Test status
Simulation time 1144482296 ps
CPU time 20.77 seconds
Started Aug 28 06:12:41 PM UTC 24
Finished Aug 28 06:13:08 PM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3449671492 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 180.prim_prince_test.3449671492
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/180.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/181.prim_prince_test.1213245676
Short name T191
Test name
Test status
Simulation time 3050348999 ps
CPU time 54.14 seconds
Started Aug 28 06:12:42 PM UTC 24
Finished Aug 28 06:13:51 PM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1213245676 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 181.prim_prince_test.1213245676
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/181.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/182.prim_prince_test.2971527977
Short name T181
Test name
Test status
Simulation time 2213915171 ps
CPU time 39.52 seconds
Started Aug 28 06:12:46 PM UTC 24
Finished Aug 28 06:13:36 PM UTC 24
Peak memory 154652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2971527977 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 182.prim_prince_test.2971527977
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/182.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/183.prim_prince_test.2077933128
Short name T186
Test name
Test status
Simulation time 2653642181 ps
CPU time 46.86 seconds
Started Aug 28 06:12:46 PM UTC 24
Finished Aug 28 06:13:46 PM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2077933128 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 183.prim_prince_test.2077933128
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/183.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/184.prim_prince_test.2233783576
Short name T203
Test name
Test status
Simulation time 3669000981 ps
CPU time 64.79 seconds
Started Aug 28 06:12:48 PM UTC 24
Finished Aug 28 06:14:11 PM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2233783576 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 184.prim_prince_test.2233783576
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/184.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/185.prim_prince_test.405975208
Short name T182
Test name
Test status
Simulation time 2147221268 ps
CPU time 38.13 seconds
Started Aug 28 06:12:48 PM UTC 24
Finished Aug 28 06:13:37 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=405975208 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 185.prim_prince_test.405975208
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/185.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/186.prim_prince_test.1234015643
Short name T196
Test name
Test status
Simulation time 3144236349 ps
CPU time 55.56 seconds
Started Aug 28 06:12:48 PM UTC 24
Finished Aug 28 06:13:59 PM UTC 24
Peak memory 156120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1234015643 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 186.prim_prince_test.1234015643
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/186.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/187.prim_prince_test.545885245
Short name T198
Test name
Test status
Simulation time 3072012897 ps
CPU time 54.36 seconds
Started Aug 28 06:12:51 PM UTC 24
Finished Aug 28 06:14:01 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=545885245 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 187.prim_prince_test.545885245
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/187.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/188.prim_prince_test.2753478700
Short name T168
Test name
Test status
Simulation time 803586388 ps
CPU time 14.79 seconds
Started Aug 28 06:12:53 PM UTC 24
Finished Aug 28 06:13:12 PM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2753478700 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 188.prim_prince_test.2753478700
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/188.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/189.prim_prince_test.1070501215
Short name T171
Test name
Test status
Simulation time 1082354834 ps
CPU time 19.06 seconds
Started Aug 28 06:12:55 PM UTC 24
Finished Aug 28 06:13:20 PM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1070501215 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 189.prim_prince_test.1070501215
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/189.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/19.prim_prince_test.1231834708
Short name T42
Test name
Test status
Simulation time 3611636574 ps
CPU time 64.27 seconds
Started Aug 28 06:08:36 PM UTC 24
Finished Aug 28 06:09:58 PM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1231834708 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 19.prim_prince_test.1231834708
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/19.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/190.prim_prince_test.1597501019
Short name T193
Test name
Test status
Simulation time 2527133726 ps
CPU time 44.84 seconds
Started Aug 28 06:12:55 PM UTC 24
Finished Aug 28 06:13:52 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1597501019 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 190.prim_prince_test.1597501019
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/190.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/191.prim_prince_test.3268508856
Short name T176
Test name
Test status
Simulation time 1458780160 ps
CPU time 26.15 seconds
Started Aug 28 06:12:58 PM UTC 24
Finished Aug 28 06:13:32 PM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3268508856 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 191.prim_prince_test.3268508856
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/191.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/192.prim_prince_test.4272419221
Short name T195
Test name
Test status
Simulation time 2517567589 ps
CPU time 45.11 seconds
Started Aug 28 06:12:58 PM UTC 24
Finished Aug 28 06:13:56 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4272419221 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 192.prim_prince_test.4272419221
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/192.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/193.prim_prince_test.419706754
Short name T206
Test name
Test status
Simulation time 3489084570 ps
CPU time 62.08 seconds
Started Aug 28 06:12:59 PM UTC 24
Finished Aug 28 06:14:18 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=419706754 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 193.prim_prince_test.419706754
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/193.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/194.prim_prince_test.2088124718
Short name T188
Test name
Test status
Simulation time 1966095653 ps
CPU time 35.09 seconds
Started Aug 28 06:13:02 PM UTC 24
Finished Aug 28 06:13:47 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2088124718 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 194.prim_prince_test.2088124718
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/194.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/195.prim_prince_test.2221753208
Short name T190
Test name
Test status
Simulation time 2011974321 ps
CPU time 36.14 seconds
Started Aug 28 06:13:02 PM UTC 24
Finished Aug 28 06:13:48 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2221753208 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 195.prim_prince_test.2221753208
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/195.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/196.prim_prince_test.836721771
Short name T201
Test name
Test status
Simulation time 2588543825 ps
CPU time 46.33 seconds
Started Aug 28 06:13:04 PM UTC 24
Finished Aug 28 06:14:03 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=836721771 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 196.prim_prince_test.836721771
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/196.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/197.prim_prince_test.1388645310
Short name T204
Test name
Test status
Simulation time 2880767231 ps
CPU time 50.93 seconds
Started Aug 28 06:13:06 PM UTC 24
Finished Aug 28 06:14:11 PM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1388645310 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 197.prim_prince_test.1388645310
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/197.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/198.prim_prince_test.3799162777
Short name T208
Test name
Test status
Simulation time 3138859148 ps
CPU time 55.81 seconds
Started Aug 28 06:13:08 PM UTC 24
Finished Aug 28 06:14:19 PM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3799162777 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 198.prim_prince_test.3799162777
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/198.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/199.prim_prince_test.4078425616
Short name T194
Test name
Test status
Simulation time 1879982937 ps
CPU time 33.55 seconds
Started Aug 28 06:13:11 PM UTC 24
Finished Aug 28 06:13:54 PM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4078425616 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 199.prim_prince_test.4078425616
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/199.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/2.prim_prince_test.1372959455
Short name T18
Test name
Test status
Simulation time 2476421651 ps
CPU time 44.23 seconds
Started Aug 28 06:08:26 PM UTC 24
Finished Aug 28 06:09:23 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1372959455 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 2.prim_prince_test.1372959455
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/2.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/20.prim_prince_test.1043793135
Short name T8
Test name
Test status
Simulation time 1362330817 ps
CPU time 24.42 seconds
Started Aug 28 06:08:36 PM UTC 24
Finished Aug 28 06:09:07 PM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1043793135 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 20.prim_prince_test.1043793135
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/20.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/200.prim_prince_test.2434991107
Short name T187
Test name
Test status
Simulation time 1487047964 ps
CPU time 26.55 seconds
Started Aug 28 06:13:13 PM UTC 24
Finished Aug 28 06:13:47 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2434991107 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 200.prim_prince_test.2434991107
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/200.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/201.prim_prince_test.590491386
Short name T205
Test name
Test status
Simulation time 2546490700 ps
CPU time 45.15 seconds
Started Aug 28 06:13:16 PM UTC 24
Finished Aug 28 06:14:13 PM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=590491386 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 201.prim_prince_test.590491386
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/201.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/202.prim_prince_test.1692050158
Short name T217
Test name
Test status
Simulation time 3346423483 ps
CPU time 59.54 seconds
Started Aug 28 06:13:18 PM UTC 24
Finished Aug 28 06:14:33 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1692050158 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 202.prim_prince_test.1692050158
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/202.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/203.prim_prince_test.2195015307
Short name T184
Test name
Test status
Simulation time 933496346 ps
CPU time 17.11 seconds
Started Aug 28 06:13:21 PM UTC 24
Finished Aug 28 06:13:43 PM UTC 24
Peak memory 156048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2195015307 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 203.prim_prince_test.2195015307
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/203.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/204.prim_prince_test.702836241
Short name T189
Test name
Test status
Simulation time 1091616973 ps
CPU time 19.97 seconds
Started Aug 28 06:13:22 PM UTC 24
Finished Aug 28 06:13:48 PM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=702836241 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 204.prim_prince_test.702836241
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/204.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/205.prim_prince_test.4294055861
Short name T220
Test name
Test status
Simulation time 3329425881 ps
CPU time 59.36 seconds
Started Aug 28 06:13:23 PM UTC 24
Finished Aug 28 06:14:38 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4294055861 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 205.prim_prince_test.4294055861
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/205.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/206.prim_prince_test.4200887129
Short name T213
Test name
Test status
Simulation time 2712947081 ps
CPU time 47.9 seconds
Started Aug 28 06:13:26 PM UTC 24
Finished Aug 28 06:14:27 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4200887129 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 206.prim_prince_test.4200887129
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/206.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/207.prim_prince_test.3034991367
Short name T211
Test name
Test status
Simulation time 2436304133 ps
CPU time 42.95 seconds
Started Aug 28 06:13:27 PM UTC 24
Finished Aug 28 06:14:22 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3034991367 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 207.prim_prince_test.3034991367
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/207.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/208.prim_prince_test.2256064347
Short name T228
Test name
Test status
Simulation time 3590172814 ps
CPU time 63.37 seconds
Started Aug 28 06:13:32 PM UTC 24
Finished Aug 28 06:14:53 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2256064347 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 208.prim_prince_test.2256064347
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/208.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/209.prim_prince_test.3911484387
Short name T202
Test name
Test status
Simulation time 1479963358 ps
CPU time 26.4 seconds
Started Aug 28 06:13:33 PM UTC 24
Finished Aug 28 06:14:08 PM UTC 24
Peak memory 154420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3911484387 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 209.prim_prince_test.3911484387
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/209.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/21.prim_prince_test.3235533716
Short name T41
Test name
Test status
Simulation time 3588641631 ps
CPU time 63.43 seconds
Started Aug 28 06:08:36 PM UTC 24
Finished Aug 28 06:09:56 PM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3235533716 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 21.prim_prince_test.3235533716
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/21.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/210.prim_prince_test.3671054600
Short name T231
Test name
Test status
Simulation time 3560211591 ps
CPU time 63.17 seconds
Started Aug 28 06:13:34 PM UTC 24
Finished Aug 28 06:14:54 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3671054600 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 210.prim_prince_test.3671054600
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/210.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/211.prim_prince_test.3597070334
Short name T230
Test name
Test status
Simulation time 3448143377 ps
CPU time 61.14 seconds
Started Aug 28 06:13:36 PM UTC 24
Finished Aug 28 06:14:53 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3597070334 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 211.prim_prince_test.3597070334
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/211.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/212.prim_prince_test.503467960
Short name T215
Test name
Test status
Simulation time 2362482395 ps
CPU time 41.95 seconds
Started Aug 28 06:13:36 PM UTC 24
Finished Aug 28 06:14:29 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=503467960 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 212.prim_prince_test.503467960
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/212.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/213.prim_prince_test.1197813516
Short name T207
Test name
Test status
Simulation time 1823839945 ps
CPU time 32.78 seconds
Started Aug 28 06:13:37 PM UTC 24
Finished Aug 28 06:14:19 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1197813516 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 213.prim_prince_test.1197813516
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/213.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/214.prim_prince_test.4110773452
Short name T210
Test name
Test status
Simulation time 1887513381 ps
CPU time 33.73 seconds
Started Aug 28 06:13:38 PM UTC 24
Finished Aug 28 06:14:21 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4110773452 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 214.prim_prince_test.4110773452
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/214.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/215.prim_prince_test.1932702539
Short name T197
Test name
Test status
Simulation time 907234755 ps
CPU time 16.49 seconds
Started Aug 28 06:13:39 PM UTC 24
Finished Aug 28 06:14:01 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1932702539 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 215.prim_prince_test.1932702539
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/215.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/216.prim_prince_test.1451248820
Short name T200
Test name
Test status
Simulation time 756839717 ps
CPU time 13.82 seconds
Started Aug 28 06:13:44 PM UTC 24
Finished Aug 28 06:14:02 PM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1451248820 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 216.prim_prince_test.1451248820
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/216.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/217.prim_prince_test.4040484072
Short name T234
Test name
Test status
Simulation time 3257505317 ps
CPU time 57.21 seconds
Started Aug 28 06:13:45 PM UTC 24
Finished Aug 28 06:14:58 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4040484072 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 217.prim_prince_test.4040484072
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/217.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/218.prim_prince_test.4053395964
Short name T224
Test name
Test status
Simulation time 2549333544 ps
CPU time 45.32 seconds
Started Aug 28 06:13:46 PM UTC 24
Finished Aug 28 06:14:44 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4053395964 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 218.prim_prince_test.4053395964
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/218.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/219.prim_prince_test.2715749630
Short name T223
Test name
Test status
Simulation time 2500734370 ps
CPU time 44.31 seconds
Started Aug 28 06:13:47 PM UTC 24
Finished Aug 28 06:14:44 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2715749630 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 219.prim_prince_test.2715749630
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/219.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/22.prim_prince_test.2028521233
Short name T25
Test name
Test status
Simulation time 2715730525 ps
CPU time 48.63 seconds
Started Aug 28 06:08:37 PM UTC 24
Finished Aug 28 06:09:39 PM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2028521233 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 22.prim_prince_test.2028521233
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/22.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/220.prim_prince_test.3446618599
Short name T214
Test name
Test status
Simulation time 1753687335 ps
CPU time 31.4 seconds
Started Aug 28 06:13:47 PM UTC 24
Finished Aug 28 06:14:28 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3446618599 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 220.prim_prince_test.3446618599
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/220.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/221.prim_prince_test.1841457222
Short name T227
Test name
Test status
Simulation time 2736808144 ps
CPU time 48.78 seconds
Started Aug 28 06:13:49 PM UTC 24
Finished Aug 28 06:14:50 PM UTC 24
Peak memory 154624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1841457222 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 221.prim_prince_test.1841457222
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/221.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/222.prim_prince_test.3391197628
Short name T243
Test name
Test status
Simulation time 3461683385 ps
CPU time 61.02 seconds
Started Aug 28 06:13:49 PM UTC 24
Finished Aug 28 06:15:06 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3391197628 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 222.prim_prince_test.3391197628
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/222.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/223.prim_prince_test.2486604976
Short name T212
Test name
Test status
Simulation time 1326709533 ps
CPU time 23.96 seconds
Started Aug 28 06:13:52 PM UTC 24
Finished Aug 28 06:14:23 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2486604976 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 223.prim_prince_test.2486604976
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/223.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/224.prim_prince_test.1871064102
Short name T209
Test name
Test status
Simulation time 1224387730 ps
CPU time 22.1 seconds
Started Aug 28 06:13:52 PM UTC 24
Finished Aug 28 06:14:20 PM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1871064102 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 224.prim_prince_test.1871064102
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/224.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/225.prim_prince_test.3003734632
Short name T218
Test name
Test status
Simulation time 1784191751 ps
CPU time 31.73 seconds
Started Aug 28 06:13:53 PM UTC 24
Finished Aug 28 06:14:34 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3003734632 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 225.prim_prince_test.3003734632
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/225.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/226.prim_prince_test.2957322922
Short name T240
Test name
Test status
Simulation time 2988630443 ps
CPU time 53.13 seconds
Started Aug 28 06:13:55 PM UTC 24
Finished Aug 28 06:15:02 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2957322922 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 226.prim_prince_test.2957322922
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/226.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/227.prim_prince_test.3903972050
Short name T232
Test name
Test status
Simulation time 2598038911 ps
CPU time 46.22 seconds
Started Aug 28 06:13:56 PM UTC 24
Finished Aug 28 06:14:55 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3903972050 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 227.prim_prince_test.3903972050
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/227.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/228.prim_prince_test.3541873157
Short name T251
Test name
Test status
Simulation time 3544702257 ps
CPU time 62.62 seconds
Started Aug 28 06:14:00 PM UTC 24
Finished Aug 28 06:15:20 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3541873157 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 228.prim_prince_test.3541873157
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/228.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/229.prim_prince_test.1641019374
Short name T226
Test name
Test status
Simulation time 2096127889 ps
CPU time 37.26 seconds
Started Aug 28 06:14:01 PM UTC 24
Finished Aug 28 06:14:49 PM UTC 24
Peak memory 154128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1641019374 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 229.prim_prince_test.1641019374
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/229.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/23.prim_prince_test.4271992321
Short name T13
Test name
Test status
Simulation time 1733871252 ps
CPU time 30.98 seconds
Started Aug 28 06:08:40 PM UTC 24
Finished Aug 28 06:09:20 PM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4271992321 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 23.prim_prince_test.4271992321
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/23.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/230.prim_prince_test.2759848681
Short name T225
Test name
Test status
Simulation time 1889578150 ps
CPU time 33.23 seconds
Started Aug 28 06:14:01 PM UTC 24
Finished Aug 28 06:14:44 PM UTC 24
Peak memory 154224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2759848681 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 230.prim_prince_test.2759848681
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/230.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/231.prim_prince_test.316931841
Short name T216
Test name
Test status
Simulation time 1286477936 ps
CPU time 22.85 seconds
Started Aug 28 06:14:01 PM UTC 24
Finished Aug 28 06:14:31 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=316931841 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 231.prim_prince_test.316931841
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/231.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/232.prim_prince_test.3139577751
Short name T239
Test name
Test status
Simulation time 2627549731 ps
CPU time 46.92 seconds
Started Aug 28 06:14:03 PM UTC 24
Finished Aug 28 06:15:02 PM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3139577751 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 232.prim_prince_test.3139577751
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/232.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/233.prim_prince_test.1886353772
Short name T229
Test name
Test status
Simulation time 2170967046 ps
CPU time 38.52 seconds
Started Aug 28 06:14:04 PM UTC 24
Finished Aug 28 06:14:53 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1886353772 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 233.prim_prince_test.1886353772
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/233.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/234.prim_prince_test.3008067769
Short name T219
Test name
Test status
Simulation time 1104413256 ps
CPU time 19.78 seconds
Started Aug 28 06:14:09 PM UTC 24
Finished Aug 28 06:14:34 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3008067769 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 234.prim_prince_test.3008067769
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/234.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/235.prim_prince_test.154502354
Short name T222
Test name
Test status
Simulation time 1287357390 ps
CPU time 23.05 seconds
Started Aug 28 06:14:11 PM UTC 24
Finished Aug 28 06:14:41 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=154502354 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 235.prim_prince_test.154502354
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/235.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/236.prim_prince_test.1834950832
Short name T247
Test name
Test status
Simulation time 2769363351 ps
CPU time 48.91 seconds
Started Aug 28 06:14:12 PM UTC 24
Finished Aug 28 06:15:14 PM UTC 24
Peak memory 154648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1834950832 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 236.prim_prince_test.1834950832
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/236.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/237.prim_prince_test.2301807041
Short name T250
Test name
Test status
Simulation time 2850433761 ps
CPU time 50.15 seconds
Started Aug 28 06:14:14 PM UTC 24
Finished Aug 28 06:15:18 PM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2301807041 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 237.prim_prince_test.2301807041
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/237.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/238.prim_prince_test.1248152780
Short name T233
Test name
Test status
Simulation time 1684789593 ps
CPU time 30.03 seconds
Started Aug 28 06:14:18 PM UTC 24
Finished Aug 28 06:14:57 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1248152780 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 238.prim_prince_test.1248152780
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/238.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/239.prim_prince_test.1571538952
Short name T258
Test name
Test status
Simulation time 3462060777 ps
CPU time 61.61 seconds
Started Aug 28 06:14:19 PM UTC 24
Finished Aug 28 06:15:38 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1571538952 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 239.prim_prince_test.1571538952
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/239.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/24.prim_prince_test.1439557062
Short name T10
Test name
Test status
Simulation time 1432416458 ps
CPU time 25.81 seconds
Started Aug 28 06:08:40 PM UTC 24
Finished Aug 28 06:09:13 PM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1439557062 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 24.prim_prince_test.1439557062
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/24.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/240.prim_prince_test.2171616023
Short name T221
Test name
Test status
Simulation time 756758306 ps
CPU time 13.85 seconds
Started Aug 28 06:14:20 PM UTC 24
Finished Aug 28 06:14:39 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2171616023 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 240.prim_prince_test.2171616023
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/240.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/241.prim_prince_test.3614397335
Short name T241
Test name
Test status
Simulation time 1873962332 ps
CPU time 33.29 seconds
Started Aug 28 06:14:22 PM UTC 24
Finished Aug 28 06:15:04 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3614397335 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 241.prim_prince_test.3614397335
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/241.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/242.prim_prince_test.4150085021
Short name T235
Test name
Test status
Simulation time 1593202722 ps
CPU time 28.58 seconds
Started Aug 28 06:14:23 PM UTC 24
Finished Aug 28 06:14:59 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4150085021 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 242.prim_prince_test.4150085021
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/242.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/243.prim_prince_test.2912942281
Short name T248
Test name
Test status
Simulation time 2274169875 ps
CPU time 40.17 seconds
Started Aug 28 06:14:23 PM UTC 24
Finished Aug 28 06:15:14 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2912942281 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 243.prim_prince_test.2912942281
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/243.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/244.prim_prince_test.2664473182
Short name T246
Test name
Test status
Simulation time 2133089516 ps
CPU time 37.76 seconds
Started Aug 28 06:14:24 PM UTC 24
Finished Aug 28 06:15:12 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2664473182 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 244.prim_prince_test.2664473182
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/244.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/245.prim_prince_test.2684437175
Short name T237
Test name
Test status
Simulation time 1437249214 ps
CPU time 25.7 seconds
Started Aug 28 06:14:28 PM UTC 24
Finished Aug 28 06:15:01 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2684437175 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 245.prim_prince_test.2684437175
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/245.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/246.prim_prince_test.4071640763
Short name T245
Test name
Test status
Simulation time 1762396976 ps
CPU time 31.55 seconds
Started Aug 28 06:14:28 PM UTC 24
Finished Aug 28 06:15:08 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4071640763 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 246.prim_prince_test.4071640763
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/246.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/247.prim_prince_test.4125383734
Short name T242
Test name
Test status
Simulation time 1501768099 ps
CPU time 26.68 seconds
Started Aug 28 06:14:30 PM UTC 24
Finished Aug 28 06:15:05 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4125383734 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 247.prim_prince_test.4125383734
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/247.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/248.prim_prince_test.2167305174
Short name T253
Test name
Test status
Simulation time 2158207908 ps
CPU time 38.73 seconds
Started Aug 28 06:14:32 PM UTC 24
Finished Aug 28 06:15:22 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2167305174 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 248.prim_prince_test.2167305174
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/248.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/249.prim_prince_test.1158231406
Short name T236
Test name
Test status
Simulation time 1105390292 ps
CPU time 19.9 seconds
Started Aug 28 06:14:34 PM UTC 24
Finished Aug 28 06:15:00 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1158231406 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 249.prim_prince_test.1158231406
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/249.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/25.prim_prince_test.2572106400
Short name T24
Test name
Test status
Simulation time 2534919194 ps
CPU time 45.29 seconds
Started Aug 28 06:08:41 PM UTC 24
Finished Aug 28 06:09:39 PM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2572106400 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 25.prim_prince_test.2572106400
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/25.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/250.prim_prince_test.163828708
Short name T264
Test name
Test status
Simulation time 3198166480 ps
CPU time 56.73 seconds
Started Aug 28 06:14:34 PM UTC 24
Finished Aug 28 06:15:47 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=163828708 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 250.prim_prince_test.163828708
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/250.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/251.prim_prince_test.2165958216
Short name T263
Test name
Test status
Simulation time 3073658535 ps
CPU time 54.58 seconds
Started Aug 28 06:14:36 PM UTC 24
Finished Aug 28 06:15:45 PM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2165958216 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 251.prim_prince_test.2165958216
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/251.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/252.prim_prince_test.3298523278
Short name T269
Test name
Test status
Simulation time 3149990093 ps
CPU time 56.02 seconds
Started Aug 28 06:14:39 PM UTC 24
Finished Aug 28 06:15:50 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3298523278 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 252.prim_prince_test.3298523278
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/252.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/253.prim_prince_test.2994712135
Short name T238
Test name
Test status
Simulation time 939851331 ps
CPU time 17.03 seconds
Started Aug 28 06:14:40 PM UTC 24
Finished Aug 28 06:15:02 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2994712135 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 253.prim_prince_test.2994712135
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/253.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/254.prim_prince_test.1677737682
Short name T260
Test name
Test status
Simulation time 2639772067 ps
CPU time 46.86 seconds
Started Aug 28 06:14:42 PM UTC 24
Finished Aug 28 06:15:41 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1677737682 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 254.prim_prince_test.1677737682
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/254.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/255.prim_prince_test.4265087817
Short name T270
Test name
Test status
Simulation time 2882607897 ps
CPU time 50.99 seconds
Started Aug 28 06:14:45 PM UTC 24
Finished Aug 28 06:15:50 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4265087817 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 255.prim_prince_test.4265087817
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/255.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/256.prim_prince_test.2704765553
Short name T249
Test name
Test status
Simulation time 1352084070 ps
CPU time 24.29 seconds
Started Aug 28 06:14:45 PM UTC 24
Finished Aug 28 06:15:16 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2704765553 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 256.prim_prince_test.2704765553
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/256.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/257.prim_prince_test.916446752
Short name T244
Test name
Test status
Simulation time 893644699 ps
CPU time 16.07 seconds
Started Aug 28 06:14:45 PM UTC 24
Finished Aug 28 06:15:06 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=916446752 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 257.prim_prince_test.916446752
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/257.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/258.prim_prince_test.3541307923
Short name T256
Test name
Test status
Simulation time 1890591892 ps
CPU time 33.78 seconds
Started Aug 28 06:14:49 PM UTC 24
Finished Aug 28 06:15:32 PM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3541307923 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 258.prim_prince_test.3541307923
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/258.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/259.prim_prince_test.2860907139
Short name T280
Test name
Test status
Simulation time 3676768771 ps
CPU time 65.04 seconds
Started Aug 28 06:14:51 PM UTC 24
Finished Aug 28 06:16:14 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2860907139 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 259.prim_prince_test.2860907139
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/259.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/26.prim_prince_test.2584299200
Short name T14
Test name
Test status
Simulation time 1584359902 ps
CPU time 28.17 seconds
Started Aug 28 06:08:44 PM UTC 24
Finished Aug 28 06:09:21 PM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2584299200 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 26.prim_prince_test.2584299200
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/26.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/260.prim_prince_test.1103916734
Short name T257
Test name
Test status
Simulation time 1844927404 ps
CPU time 33.13 seconds
Started Aug 28 06:14:54 PM UTC 24
Finished Aug 28 06:15:36 PM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1103916734 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 260.prim_prince_test.1103916734
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/260.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/261.prim_prince_test.3579107867
Short name T261
Test name
Test status
Simulation time 2233684509 ps
CPU time 39.46 seconds
Started Aug 28 06:14:54 PM UTC 24
Finished Aug 28 06:15:44 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3579107867 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 261.prim_prince_test.3579107867
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/261.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/262.prim_prince_test.4176872412
Short name T254
Test name
Test status
Simulation time 1431531263 ps
CPU time 25.68 seconds
Started Aug 28 06:14:54 PM UTC 24
Finished Aug 28 06:15:27 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4176872412 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 262.prim_prince_test.4176872412
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/262.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/263.prim_prince_test.2148449266
Short name T272
Test name
Test status
Simulation time 2591856039 ps
CPU time 46.08 seconds
Started Aug 28 06:14:55 PM UTC 24
Finished Aug 28 06:15:53 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2148449266 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 263.prim_prince_test.2148449266
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/263.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/264.prim_prince_test.1290395406
Short name T282
Test name
Test status
Simulation time 3688992557 ps
CPU time 65.51 seconds
Started Aug 28 06:14:56 PM UTC 24
Finished Aug 28 06:16:19 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1290395406 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 264.prim_prince_test.1290395406
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/264.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/265.prim_prince_test.812104989
Short name T275
Test name
Test status
Simulation time 2769457019 ps
CPU time 49.24 seconds
Started Aug 28 06:14:58 PM UTC 24
Finished Aug 28 06:16:01 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=812104989 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 265.prim_prince_test.812104989
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/265.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/266.prim_prince_test.888842624
Short name T277
Test name
Test status
Simulation time 2766770831 ps
CPU time 49.45 seconds
Started Aug 28 06:14:59 PM UTC 24
Finished Aug 28 06:16:02 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=888842624 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 266.prim_prince_test.888842624
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/266.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/267.prim_prince_test.1409582647
Short name T268
Test name
Test status
Simulation time 2177222242 ps
CPU time 38.8 seconds
Started Aug 28 06:15:00 PM UTC 24
Finished Aug 28 06:15:50 PM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1409582647 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 267.prim_prince_test.1409582647
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/267.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/268.prim_prince_test.954091599
Short name T288
Test name
Test status
Simulation time 3640776456 ps
CPU time 64.49 seconds
Started Aug 28 06:15:01 PM UTC 24
Finished Aug 28 06:16:23 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=954091599 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 268.prim_prince_test.954091599
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/268.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/269.prim_prince_test.3007138878
Short name T279
Test name
Test status
Simulation time 2922316070 ps
CPU time 51.84 seconds
Started Aug 28 06:15:03 PM UTC 24
Finished Aug 28 06:16:08 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3007138878 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 269.prim_prince_test.3007138878
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/269.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/27.prim_prince_test.2370197446
Short name T19
Test name
Test status
Simulation time 1609008914 ps
CPU time 29.2 seconds
Started Aug 28 06:08:46 PM UTC 24
Finished Aug 28 06:09:24 PM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2370197446 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 27.prim_prince_test.2370197446
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/27.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/270.prim_prince_test.858451713
Short name T252
Test name
Test status
Simulation time 783956013 ps
CPU time 14.18 seconds
Started Aug 28 06:15:03 PM UTC 24
Finished Aug 28 06:15:21 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=858451713 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 270.prim_prince_test.858451713
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/270.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/271.prim_prince_test.2548985143
Short name T262
Test name
Test status
Simulation time 1850147279 ps
CPU time 33.08 seconds
Started Aug 28 06:15:03 PM UTC 24
Finished Aug 28 06:15:45 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2548985143 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 271.prim_prince_test.2548985143
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/271.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/272.prim_prince_test.3688757223
Short name T285
Test name
Test status
Simulation time 3488658557 ps
CPU time 62.01 seconds
Started Aug 28 06:15:04 PM UTC 24
Finished Aug 28 06:16:22 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3688757223 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 272.prim_prince_test.3688757223
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/272.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/273.prim_prince_test.919144185
Short name T265
Test name
Test status
Simulation time 1831173029 ps
CPU time 32.64 seconds
Started Aug 28 06:15:05 PM UTC 24
Finished Aug 28 06:15:47 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=919144185 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 273.prim_prince_test.919144185
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/273.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/274.prim_prince_test.168686428
Short name T292
Test name
Test status
Simulation time 3592919686 ps
CPU time 63.76 seconds
Started Aug 28 06:15:05 PM UTC 24
Finished Aug 28 06:16:26 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=168686428 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 274.prim_prince_test.168686428
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/274.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/275.prim_prince_test.2745784085
Short name T255
Test name
Test status
Simulation time 1039150233 ps
CPU time 18.82 seconds
Started Aug 28 06:15:07 PM UTC 24
Finished Aug 28 06:15:32 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2745784085 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 275.prim_prince_test.2745784085
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/275.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/276.prim_prince_test.844667157
Short name T273
Test name
Test status
Simulation time 2138095087 ps
CPU time 37.86 seconds
Started Aug 28 06:15:07 PM UTC 24
Finished Aug 28 06:15:55 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=844667157 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 276.prim_prince_test.844667157
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/276.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/277.prim_prince_test.3664184733
Short name T287
Test name
Test status
Simulation time 3265604236 ps
CPU time 57.85 seconds
Started Aug 28 06:15:09 PM UTC 24
Finished Aug 28 06:16:23 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3664184733 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 277.prim_prince_test.3664184733
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/277.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/278.prim_prince_test.318887998
Short name T283
Test name
Test status
Simulation time 2920137850 ps
CPU time 51.93 seconds
Started Aug 28 06:15:13 PM UTC 24
Finished Aug 28 06:16:19 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=318887998 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 278.prim_prince_test.318887998
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/278.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/279.prim_prince_test.3801496904
Short name T259
Test name
Test status
Simulation time 1014032824 ps
CPU time 18.29 seconds
Started Aug 28 06:15:15 PM UTC 24
Finished Aug 28 06:15:39 PM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3801496904 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 279.prim_prince_test.3801496904
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/279.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/28.prim_prince_test.954073950
Short name T21
Test name
Test status
Simulation time 2011604993 ps
CPU time 36.06 seconds
Started Aug 28 06:08:48 PM UTC 24
Finished Aug 28 06:09:35 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=954073950 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 28.prim_prince_test.954073950
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/28.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/280.prim_prince_test.1170489375
Short name T274
Test name
Test status
Simulation time 1899810462 ps
CPU time 33.91 seconds
Started Aug 28 06:15:16 PM UTC 24
Finished Aug 28 06:15:59 PM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1170489375 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 280.prim_prince_test.1170489375
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/280.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/281.prim_prince_test.138100284
Short name T266
Test name
Test status
Simulation time 1258889431 ps
CPU time 22.87 seconds
Started Aug 28 06:15:18 PM UTC 24
Finished Aug 28 06:15:47 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=138100284 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 281.prim_prince_test.138100284
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/281.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/282.prim_prince_test.2266573512
Short name T267
Test name
Test status
Simulation time 1332132631 ps
CPU time 23.69 seconds
Started Aug 28 06:15:19 PM UTC 24
Finished Aug 28 06:15:49 PM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2266573512 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 282.prim_prince_test.2266573512
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/282.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/283.prim_prince_test.3051635005
Short name T304
Test name
Test status
Simulation time 3578830425 ps
CPU time 63.26 seconds
Started Aug 28 06:15:21 PM UTC 24
Finished Aug 28 06:16:41 PM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3051635005 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 283.prim_prince_test.3051635005
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/283.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/284.prim_prince_test.3489285855
Short name T278
Test name
Test status
Simulation time 1892640549 ps
CPU time 33.94 seconds
Started Aug 28 06:15:22 PM UTC 24
Finished Aug 28 06:16:05 PM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3489285855 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 284.prim_prince_test.3489285855
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/284.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/285.prim_prince_test.3411164408
Short name T309
Test name
Test status
Simulation time 3717941922 ps
CPU time 65.13 seconds
Started Aug 28 06:15:23 PM UTC 24
Finished Aug 28 06:16:46 PM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3411164408 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 285.prim_prince_test.3411164408
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/285.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/286.prim_prince_test.1669371844
Short name T310
Test name
Test status
Simulation time 3738263007 ps
CPU time 66.17 seconds
Started Aug 28 06:15:27 PM UTC 24
Finished Aug 28 06:16:51 PM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1669371844 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 286.prim_prince_test.1669371844
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/286.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/287.prim_prince_test.3075790003
Short name T276
Test name
Test status
Simulation time 1357825689 ps
CPU time 24.34 seconds
Started Aug 28 06:15:29 PM UTC 24
Finished Aug 28 06:16:01 PM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3075790003 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 287.prim_prince_test.3075790003
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/287.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/288.prim_prince_test.3595503955
Short name T271
Test name
Test status
Simulation time 812700470 ps
CPU time 14.58 seconds
Started Aug 28 06:15:32 PM UTC 24
Finished Aug 28 06:15:52 PM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3595503955 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 288.prim_prince_test.3595503955
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/288.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/289.prim_prince_test.3105309087
Short name T301
Test name
Test status
Simulation time 2901722983 ps
CPU time 51.61 seconds
Started Aug 28 06:15:34 PM UTC 24
Finished Aug 28 06:16:39 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3105309087 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 289.prim_prince_test.3105309087
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/289.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/29.prim_prince_test.1875796691
Short name T16
Test name
Test status
Simulation time 1367686604 ps
CPU time 24.34 seconds
Started Aug 28 06:08:50 PM UTC 24
Finished Aug 28 06:09:21 PM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1875796691 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 29.prim_prince_test.1875796691
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/29.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/290.prim_prince_test.1460245232
Short name T298
Test name
Test status
Simulation time 2557010789 ps
CPU time 45.05 seconds
Started Aug 28 06:15:37 PM UTC 24
Finished Aug 28 06:16:35 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1460245232 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 290.prim_prince_test.1460245232
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/290.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/291.prim_prince_test.701315511
Short name T311
Test name
Test status
Simulation time 3219247174 ps
CPU time 57.05 seconds
Started Aug 28 06:15:39 PM UTC 24
Finished Aug 28 06:16:51 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=701315511 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 291.prim_prince_test.701315511
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/291.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/292.prim_prince_test.4196433489
Short name T300
Test name
Test status
Simulation time 2500757294 ps
CPU time 44.44 seconds
Started Aug 28 06:15:40 PM UTC 24
Finished Aug 28 06:16:37 PM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4196433489 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 292.prim_prince_test.4196433489
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/292.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/293.prim_prince_test.1937153778
Short name T290
Test name
Test status
Simulation time 1840873069 ps
CPU time 32.66 seconds
Started Aug 28 06:15:42 PM UTC 24
Finished Aug 28 06:16:25 PM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1937153778 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 293.prim_prince_test.1937153778
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/293.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/294.prim_prince_test.3676553473
Short name T312
Test name
Test status
Simulation time 3005833314 ps
CPU time 52.98 seconds
Started Aug 28 06:15:45 PM UTC 24
Finished Aug 28 06:16:53 PM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3676553473 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 294.prim_prince_test.3676553473
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/294.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/295.prim_prince_test.2912956899
Short name T306
Test name
Test status
Simulation time 2443734613 ps
CPU time 43.28 seconds
Started Aug 28 06:15:46 PM UTC 24
Finished Aug 28 06:16:42 PM UTC 24
Peak memory 154644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2912956899 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 295.prim_prince_test.2912956899
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/295.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/296.prim_prince_test.1219718102
Short name T321
Test name
Test status
Simulation time 3531891103 ps
CPU time 62.47 seconds
Started Aug 28 06:15:46 PM UTC 24
Finished Aug 28 06:17:06 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1219718102 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 296.prim_prince_test.1219718102
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/296.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/297.prim_prince_test.1538126936
Short name T291
Test name
Test status
Simulation time 1611172863 ps
CPU time 28.75 seconds
Started Aug 28 06:15:48 PM UTC 24
Finished Aug 28 06:16:25 PM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1538126936 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 297.prim_prince_test.1538126936
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/297.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/298.prim_prince_test.1465010660
Short name T307
Test name
Test status
Simulation time 2460299701 ps
CPU time 43.46 seconds
Started Aug 28 06:15:48 PM UTC 24
Finished Aug 28 06:16:43 PM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1465010660 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 298.prim_prince_test.1465010660
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/298.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/299.prim_prince_test.4219588624
Short name T324
Test name
Test status
Simulation time 3691183270 ps
CPU time 65.24 seconds
Started Aug 28 06:15:48 PM UTC 24
Finished Aug 28 06:17:11 PM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4219588624 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 299.prim_prince_test.4219588624
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/299.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/3.prim_prince_test.862074652
Short name T11
Test name
Test status
Simulation time 2062078271 ps
CPU time 37.13 seconds
Started Aug 28 06:08:26 PM UTC 24
Finished Aug 28 06:09:14 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=862074652 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 3.prim_prince_test.862074652
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/3.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/30.prim_prince_test.4009784909
Short name T31
Test name
Test status
Simulation time 2327027684 ps
CPU time 41.54 seconds
Started Aug 28 06:08:52 PM UTC 24
Finished Aug 28 06:09:45 PM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4009784909 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 30.prim_prince_test.4009784909
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/30.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/300.prim_prince_test.3791630836
Short name T322
Test name
Test status
Simulation time 3423689616 ps
CPU time 60.36 seconds
Started Aug 28 06:15:50 PM UTC 24
Finished Aug 28 06:17:07 PM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3791630836 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 300.prim_prince_test.3791630836
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/300.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/301.prim_prince_test.3130236807
Short name T293
Test name
Test status
Simulation time 1518432685 ps
CPU time 27.27 seconds
Started Aug 28 06:15:51 PM UTC 24
Finished Aug 28 06:16:26 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3130236807 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 301.prim_prince_test.3130236807
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/301.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/302.prim_prince_test.3031913994
Short name T305
Test name
Test status
Simulation time 2237248632 ps
CPU time 39.52 seconds
Started Aug 28 06:15:51 PM UTC 24
Finished Aug 28 06:16:42 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3031913994 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 302.prim_prince_test.3031913994
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/302.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/303.prim_prince_test.2402606223
Short name T294
Test name
Test status
Simulation time 1590044594 ps
CPU time 28.21 seconds
Started Aug 28 06:15:51 PM UTC 24
Finished Aug 28 06:16:28 PM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2402606223 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 303.prim_prince_test.2402606223
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/303.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/304.prim_prince_test.741119728
Short name T289
Test name
Test status
Simulation time 1321324026 ps
CPU time 23.94 seconds
Started Aug 28 06:15:52 PM UTC 24
Finished Aug 28 06:16:23 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=741119728 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 304.prim_prince_test.741119728
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/304.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/305.prim_prince_test.1393347468
Short name T281
Test name
Test status
Simulation time 834019915 ps
CPU time 15.24 seconds
Started Aug 28 06:15:54 PM UTC 24
Finished Aug 28 06:16:15 PM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1393347468 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 305.prim_prince_test.1393347468
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/305.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/306.prim_prince_test.3030975751
Short name T299
Test name
Test status
Simulation time 1722581778 ps
CPU time 30.59 seconds
Started Aug 28 06:15:56 PM UTC 24
Finished Aug 28 06:16:36 PM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3030975751 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 306.prim_prince_test.3030975751
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/306.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/307.prim_prince_test.2455657000
Short name T284
Test name
Test status
Simulation time 851872735 ps
CPU time 15.41 seconds
Started Aug 28 06:16:00 PM UTC 24
Finished Aug 28 06:16:20 PM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2455657000 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 307.prim_prince_test.2455657000
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/307.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/308.prim_prince_test.3708282270
Short name T297
Test name
Test status
Simulation time 1383488888 ps
CPU time 25.01 seconds
Started Aug 28 06:16:02 PM UTC 24
Finished Aug 28 06:16:34 PM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3708282270 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 308.prim_prince_test.3708282270
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/308.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/309.prim_prince_test.271506423
Short name T286
Test name
Test status
Simulation time 850984414 ps
CPU time 15.59 seconds
Started Aug 28 06:16:02 PM UTC 24
Finished Aug 28 06:16:22 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=271506423 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 309.prim_prince_test.271506423
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/309.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/31.prim_prince_test.1661335725
Short name T28
Test name
Test status
Simulation time 2070663058 ps
CPU time 36.84 seconds
Started Aug 28 06:08:54 PM UTC 24
Finished Aug 28 06:09:41 PM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1661335725 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 31.prim_prince_test.1661335725
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/31.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/310.prim_prince_test.919643262
Short name T296
Test name
Test status
Simulation time 1227029134 ps
CPU time 22.31 seconds
Started Aug 28 06:16:03 PM UTC 24
Finished Aug 28 06:16:32 PM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=919643262 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 310.prim_prince_test.919643262
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/310.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/311.prim_prince_test.1049306434
Short name T295
Test name
Test status
Simulation time 1028891781 ps
CPU time 18.5 seconds
Started Aug 28 06:16:06 PM UTC 24
Finished Aug 28 06:16:30 PM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1049306434 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 311.prim_prince_test.1049306434
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/311.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/312.prim_prince_test.2234524321
Short name T314
Test name
Test status
Simulation time 1949491912 ps
CPU time 34.88 seconds
Started Aug 28 06:16:09 PM UTC 24
Finished Aug 28 06:16:54 PM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2234524321 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 312.prim_prince_test.2234524321
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/312.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/313.prim_prince_test.1801982511
Short name T328
Test name
Test status
Simulation time 2751192351 ps
CPU time 49.01 seconds
Started Aug 28 06:16:14 PM UTC 24
Finished Aug 28 06:17:17 PM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1801982511 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 313.prim_prince_test.1801982511
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/313.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/314.prim_prince_test.145417760
Short name T308
Test name
Test status
Simulation time 1270700742 ps
CPU time 22.64 seconds
Started Aug 28 06:16:15 PM UTC 24
Finished Aug 28 06:16:45 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=145417760 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 314.prim_prince_test.145417760
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/314.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/315.prim_prince_test.1687852350
Short name T303
Test name
Test status
Simulation time 899480007 ps
CPU time 16.2 seconds
Started Aug 28 06:16:20 PM UTC 24
Finished Aug 28 06:16:41 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1687852350 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 315.prim_prince_test.1687852350
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/315.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/316.prim_prince_test.1989420190
Short name T337
Test name
Test status
Simulation time 3239543221 ps
CPU time 57.31 seconds
Started Aug 28 06:16:20 PM UTC 24
Finished Aug 28 06:17:32 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1989420190 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 316.prim_prince_test.1989420190
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/316.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/317.prim_prince_test.7681756
Short name T302
Test name
Test status
Simulation time 816766033 ps
CPU time 14.82 seconds
Started Aug 28 06:16:21 PM UTC 24
Finished Aug 28 06:16:40 PM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7681756 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 317.prim_prince_test.7681756
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/317.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/318.prim_prince_test.2434976608
Short name T346
Test name
Test status
Simulation time 3424654040 ps
CPU time 60.1 seconds
Started Aug 28 06:16:23 PM UTC 24
Finished Aug 28 06:17:40 PM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2434976608 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 318.prim_prince_test.2434976608
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/318.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/319.prim_prince_test.4236532539
Short name T341
Test name
Test status
Simulation time 3275781307 ps
CPU time 57.86 seconds
Started Aug 28 06:16:23 PM UTC 24
Finished Aug 28 06:17:37 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4236532539 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 319.prim_prince_test.4236532539
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/319.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/32.prim_prince_test.4218955871
Short name T15
Test name
Test status
Simulation time 1152620401 ps
CPU time 20.9 seconds
Started Aug 28 06:08:54 PM UTC 24
Finished Aug 28 06:09:21 PM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4218955871 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 32.prim_prince_test.4218955871
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/32.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/320.prim_prince_test.2647665634
Short name T338
Test name
Test status
Simulation time 3104632929 ps
CPU time 54.85 seconds
Started Aug 28 06:16:23 PM UTC 24
Finished Aug 28 06:17:33 PM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2647665634 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 320.prim_prince_test.2647665634
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/320.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/321.prim_prince_test.45391990
Short name T342
Test name
Test status
Simulation time 3259603901 ps
CPU time 57.2 seconds
Started Aug 28 06:16:24 PM UTC 24
Finished Aug 28 06:17:37 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=45391990 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 321.prim_prince_test.45391990
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/321.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/322.prim_prince_test.1932534971
Short name T343
Test name
Test status
Simulation time 3258263361 ps
CPU time 57.33 seconds
Started Aug 28 06:16:24 PM UTC 24
Finished Aug 28 06:17:37 PM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1932534971 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 322.prim_prince_test.1932534971
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/322.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/323.prim_prince_test.1044619911
Short name T329
Test name
Test status
Simulation time 2237083118 ps
CPU time 40.04 seconds
Started Aug 28 06:16:26 PM UTC 24
Finished Aug 28 06:17:17 PM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1044619911 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 323.prim_prince_test.1044619911
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/323.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/324.prim_prince_test.4037732858
Short name T326
Test name
Test status
Simulation time 2050355015 ps
CPU time 36.62 seconds
Started Aug 28 06:16:26 PM UTC 24
Finished Aug 28 06:17:13 PM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4037732858 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 324.prim_prince_test.4037732858
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/324.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/325.prim_prince_test.3187263755
Short name T315
Test name
Test status
Simulation time 1558441904 ps
CPU time 27.82 seconds
Started Aug 28 06:16:27 PM UTC 24
Finished Aug 28 06:17:03 PM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3187263755 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 325.prim_prince_test.3187263755
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/325.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/326.prim_prince_test.717991058
Short name T340
Test name
Test status
Simulation time 3004350090 ps
CPU time 53.11 seconds
Started Aug 28 06:16:27 PM UTC 24
Finished Aug 28 06:17:35 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=717991058 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 326.prim_prince_test.717991058
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/326.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/327.prim_prince_test.2740515929
Short name T317
Test name
Test status
Simulation time 1608769602 ps
CPU time 28.27 seconds
Started Aug 28 06:16:28 PM UTC 24
Finished Aug 28 06:17:05 PM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2740515929 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 327.prim_prince_test.2740515929
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/327.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/328.prim_prince_test.2473456060
Short name T313
Test name
Test status
Simulation time 941845516 ps
CPU time 16.91 seconds
Started Aug 28 06:16:31 PM UTC 24
Finished Aug 28 06:16:53 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2473456060 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 328.prim_prince_test.2473456060
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/328.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/329.prim_prince_test.2402336907
Short name T335
Test name
Test status
Simulation time 2439889019 ps
CPU time 43.44 seconds
Started Aug 28 06:16:32 PM UTC 24
Finished Aug 28 06:17:28 PM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2402336907 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 329.prim_prince_test.2402336907
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/329.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/33.prim_prince_test.3760500452
Short name T30
Test name
Test status
Simulation time 2146747933 ps
CPU time 38.5 seconds
Started Aug 28 06:08:55 PM UTC 24
Finished Aug 28 06:09:44 PM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3760500452 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 33.prim_prince_test.3760500452
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/33.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/330.prim_prince_test.2792360474
Short name T327
Test name
Test status
Simulation time 1715721731 ps
CPU time 30.7 seconds
Started Aug 28 06:16:34 PM UTC 24
Finished Aug 28 06:17:14 PM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2792360474 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 330.prim_prince_test.2792360474
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/330.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/331.prim_prince_test.3463084807
Short name T319
Test name
Test status
Simulation time 1268895601 ps
CPU time 23.03 seconds
Started Aug 28 06:16:36 PM UTC 24
Finished Aug 28 06:17:05 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3463084807 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 331.prim_prince_test.3463084807
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/331.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/332.prim_prince_test.725364807
Short name T320
Test name
Test status
Simulation time 1231688785 ps
CPU time 22.43 seconds
Started Aug 28 06:16:37 PM UTC 24
Finished Aug 28 06:17:06 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=725364807 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 332.prim_prince_test.725364807
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/332.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/333.prim_prince_test.3009642501
Short name T332
Test name
Test status
Simulation time 2100412441 ps
CPU time 37.31 seconds
Started Aug 28 06:16:38 PM UTC 24
Finished Aug 28 06:17:25 PM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3009642501 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 333.prim_prince_test.3009642501
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/333.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/334.prim_prince_test.47802822
Short name T354
Test name
Test status
Simulation time 3184654700 ps
CPU time 56.54 seconds
Started Aug 28 06:16:40 PM UTC 24
Finished Aug 28 06:17:52 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=47802822 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 334.prim_prince_test.47802822
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/334.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/335.prim_prince_test.3362135594
Short name T325
Test name
Test status
Simulation time 1327791998 ps
CPU time 24 seconds
Started Aug 28 06:16:41 PM UTC 24
Finished Aug 28 06:17:12 PM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3362135594 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 335.prim_prince_test.3362135594
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/335.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/336.prim_prince_test.4141766855
Short name T334
Test name
Test status
Simulation time 1999422385 ps
CPU time 35.35 seconds
Started Aug 28 06:16:42 PM UTC 24
Finished Aug 28 06:17:28 PM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4141766855 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 336.prim_prince_test.4141766855
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/336.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/337.prim_prince_test.2271277782
Short name T318
Test name
Test status
Simulation time 985309594 ps
CPU time 17.6 seconds
Started Aug 28 06:16:42 PM UTC 24
Finished Aug 28 06:17:05 PM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2271277782 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 337.prim_prince_test.2271277782
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/337.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/338.prim_prince_test.3417322953
Short name T316
Test name
Test status
Simulation time 911248589 ps
CPU time 16.67 seconds
Started Aug 28 06:16:42 PM UTC 24
Finished Aug 28 06:17:04 PM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3417322953 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 338.prim_prince_test.3417322953
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/338.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/339.prim_prince_test.1900127733
Short name T323
Test name
Test status
Simulation time 1030722958 ps
CPU time 18.45 seconds
Started Aug 28 06:16:44 PM UTC 24
Finished Aug 28 06:17:08 PM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1900127733 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 339.prim_prince_test.1900127733
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/339.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/34.prim_prince_test.2439229520
Short name T20
Test name
Test status
Simulation time 1195939093 ps
CPU time 21.51 seconds
Started Aug 28 06:08:57 PM UTC 24
Finished Aug 28 06:09:25 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2439229520 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 34.prim_prince_test.2439229520
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/34.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/340.prim_prince_test.2497791699
Short name T347
Test name
Test status
Simulation time 2595483272 ps
CPU time 45.52 seconds
Started Aug 28 06:16:44 PM UTC 24
Finished Aug 28 06:17:42 PM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2497791699 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 340.prim_prince_test.2497791699
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/340.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/341.prim_prince_test.2815288951
Short name T352
Test name
Test status
Simulation time 2845990389 ps
CPU time 50.46 seconds
Started Aug 28 06:16:46 PM UTC 24
Finished Aug 28 06:17:50 PM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2815288951 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 341.prim_prince_test.2815288951
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/341.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/342.prim_prince_test.2589258133
Short name T330
Test name
Test status
Simulation time 1325405319 ps
CPU time 23.79 seconds
Started Aug 28 06:16:47 PM UTC 24
Finished Aug 28 06:17:18 PM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2589258133 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 342.prim_prince_test.2589258133
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/342.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/343.prim_prince_test.4039037363
Short name T331
Test name
Test status
Simulation time 1426344384 ps
CPU time 25.82 seconds
Started Aug 28 06:16:52 PM UTC 24
Finished Aug 28 06:17:25 PM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4039037363 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 343.prim_prince_test.4039037363
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/343.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/344.prim_prince_test.2012114997
Short name T361
Test name
Test status
Simulation time 3213822619 ps
CPU time 56.53 seconds
Started Aug 28 06:16:52 PM UTC 24
Finished Aug 28 06:18:04 PM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2012114997 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 344.prim_prince_test.2012114997
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/344.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/345.prim_prince_test.134508296
Short name T370
Test name
Test status
Simulation time 3460253499 ps
CPU time 60.98 seconds
Started Aug 28 06:16:53 PM UTC 24
Finished Aug 28 06:18:11 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=134508296 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 345.prim_prince_test.134508296
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/345.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/346.prim_prince_test.3804767934
Short name T362
Test name
Test status
Simulation time 3164541091 ps
CPU time 55.78 seconds
Started Aug 28 06:16:55 PM UTC 24
Finished Aug 28 06:18:05 PM UTC 24
Peak memory 154420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3804767934 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 346.prim_prince_test.3804767934
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/346.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/347.prim_prince_test.1817672771
Short name T365
Test name
Test status
Simulation time 3195667758 ps
CPU time 56.14 seconds
Started Aug 28 06:16:55 PM UTC 24
Finished Aug 28 06:18:06 PM UTC 24
Peak memory 154440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1817672771 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 347.prim_prince_test.1817672771
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/347.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/348.prim_prince_test.4225982312
Short name T344
Test name
Test status
Simulation time 1483583772 ps
CPU time 26.46 seconds
Started Aug 28 06:17:04 PM UTC 24
Finished Aug 28 06:17:38 PM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4225982312 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 348.prim_prince_test.4225982312
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/348.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/349.prim_prince_test.1803578527
Short name T348
Test name
Test status
Simulation time 1705853872 ps
CPU time 30.26 seconds
Started Aug 28 06:17:05 PM UTC 24
Finished Aug 28 06:17:44 PM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1803578527 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 349.prim_prince_test.1803578527
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/349.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/35.prim_prince_test.751842898
Short name T34
Test name
Test status
Simulation time 1901326777 ps
CPU time 34.23 seconds
Started Aug 28 06:09:03 PM UTC 24
Finished Aug 28 06:09:47 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=751842898 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 35.prim_prince_test.751842898
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/35.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/350.prim_prince_test.247178102
Short name T367
Test name
Test status
Simulation time 2802045159 ps
CPU time 49.48 seconds
Started Aug 28 06:17:06 PM UTC 24
Finished Aug 28 06:18:09 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=247178102 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 350.prim_prince_test.247178102
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/350.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/351.prim_prince_test.830798644
Short name T374
Test name
Test status
Simulation time 3361416709 ps
CPU time 59.11 seconds
Started Aug 28 06:17:06 PM UTC 24
Finished Aug 28 06:18:21 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=830798644 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 351.prim_prince_test.830798644
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/351.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/352.prim_prince_test.3394453778
Short name T356
Test name
Test status
Simulation time 2259515973 ps
CPU time 39.83 seconds
Started Aug 28 06:17:06 PM UTC 24
Finished Aug 28 06:17:57 PM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3394453778 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 352.prim_prince_test.3394453778
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/352.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/353.prim_prince_test.1944533370
Short name T336
Test name
Test status
Simulation time 959305035 ps
CPU time 17.34 seconds
Started Aug 28 06:17:06 PM UTC 24
Finished Aug 28 06:17:29 PM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1944533370 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 353.prim_prince_test.1944533370
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/353.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/354.prim_prince_test.3922758139
Short name T339
Test name
Test status
Simulation time 1220441988 ps
CPU time 21.55 seconds
Started Aug 28 06:17:06 PM UTC 24
Finished Aug 28 06:17:34 PM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3922758139 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 354.prim_prince_test.3922758139
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/354.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/355.prim_prince_test.2064010407
Short name T350
Test name
Test status
Simulation time 1713589773 ps
CPU time 30.49 seconds
Started Aug 28 06:17:08 PM UTC 24
Finished Aug 28 06:17:47 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2064010407 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 355.prim_prince_test.2064010407
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/355.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/356.prim_prince_test.2368066422
Short name T333
Test name
Test status
Simulation time 753247274 ps
CPU time 13.74 seconds
Started Aug 28 06:17:08 PM UTC 24
Finished Aug 28 06:17:26 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2368066422 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 356.prim_prince_test.2368066422
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/356.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/357.prim_prince_test.4046451736
Short name T351
Test name
Test status
Simulation time 1664297239 ps
CPU time 29.64 seconds
Started Aug 28 06:17:09 PM UTC 24
Finished Aug 28 06:17:47 PM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4046451736 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 357.prim_prince_test.4046451736
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/357.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/358.prim_prince_test.1581947752
Short name T345
Test name
Test status
Simulation time 1183700289 ps
CPU time 21.11 seconds
Started Aug 28 06:17:12 PM UTC 24
Finished Aug 28 06:17:39 PM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1581947752 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 358.prim_prince_test.1581947752
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/358.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/359.prim_prince_test.2149159851
Short name T349
Test name
Test status
Simulation time 1437346365 ps
CPU time 25.74 seconds
Started Aug 28 06:17:13 PM UTC 24
Finished Aug 28 06:17:46 PM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2149159851 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 359.prim_prince_test.2149159851
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/359.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/36.prim_prince_test.382573518
Short name T29
Test name
Test status
Simulation time 1624968218 ps
CPU time 29.22 seconds
Started Aug 28 06:09:04 PM UTC 24
Finished Aug 28 06:09:42 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=382573518 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 36.prim_prince_test.382573518
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/36.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/360.prim_prince_test.4248040689
Short name T353
Test name
Test status
Simulation time 1618091933 ps
CPU time 28.81 seconds
Started Aug 28 06:17:13 PM UTC 24
Finished Aug 28 06:17:50 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4248040689 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 360.prim_prince_test.4248040689
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/360.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/361.prim_prince_test.1409200933
Short name T371
Test name
Test status
Simulation time 2735840832 ps
CPU time 48.76 seconds
Started Aug 28 06:17:14 PM UTC 24
Finished Aug 28 06:18:17 PM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1409200933 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 361.prim_prince_test.1409200933
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/361.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/362.prim_prince_test.876771857
Short name T357
Test name
Test status
Simulation time 1743543861 ps
CPU time 30.87 seconds
Started Aug 28 06:17:18 PM UTC 24
Finished Aug 28 06:17:57 PM UTC 24
Peak memory 154236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=876771857 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 362.prim_prince_test.876771857
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/362.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/363.prim_prince_test.2912808831
Short name T389
Test name
Test status
Simulation time 3698956375 ps
CPU time 65.03 seconds
Started Aug 28 06:17:18 PM UTC 24
Finished Aug 28 06:18:40 PM UTC 24
Peak memory 155660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2912808831 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 363.prim_prince_test.2912808831
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/363.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/364.prim_prince_test.2459867783
Short name T384
Test name
Test status
Simulation time 3441078876 ps
CPU time 60.58 seconds
Started Aug 28 06:17:19 PM UTC 24
Finished Aug 28 06:18:36 PM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2459867783 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 364.prim_prince_test.2459867783
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/364.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/365.prim_prince_test.4269184415
Short name T372
Test name
Test status
Simulation time 2356993037 ps
CPU time 41.85 seconds
Started Aug 28 06:17:26 PM UTC 24
Finished Aug 28 06:18:19 PM UTC 24
Peak memory 154588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4269184415 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 365.prim_prince_test.4269184415
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/365.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/366.prim_prince_test.1780824823
Short name T373
Test name
Test status
Simulation time 2420111880 ps
CPU time 42.58 seconds
Started Aug 28 06:17:26 PM UTC 24
Finished Aug 28 06:18:20 PM UTC 24
Peak memory 154572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1780824823 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 366.prim_prince_test.1780824823
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/366.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/367.prim_prince_test.4266625782
Short name T378
Test name
Test status
Simulation time 2557460718 ps
CPU time 45.04 seconds
Started Aug 28 06:17:27 PM UTC 24
Finished Aug 28 06:18:25 PM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4266625782 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 367.prim_prince_test.4266625782
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/367.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/368.prim_prince_test.2873640761
Short name T369
Test name
Test status
Simulation time 1842380070 ps
CPU time 32.71 seconds
Started Aug 28 06:17:28 PM UTC 24
Finished Aug 28 06:18:11 PM UTC 24
Peak memory 156056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2873640761 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 368.prim_prince_test.2873640761
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/368.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/369.prim_prince_test.2518078243
Short name T392
Test name
Test status
Simulation time 3306605730 ps
CPU time 58.38 seconds
Started Aug 28 06:17:28 PM UTC 24
Finished Aug 28 06:18:43 PM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2518078243 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 369.prim_prince_test.2518078243
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/369.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/37.prim_prince_test.3384406538
Short name T27
Test name
Test status
Simulation time 1485209756 ps
CPU time 26.67 seconds
Started Aug 28 06:09:05 PM UTC 24
Finished Aug 28 06:09:39 PM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3384406538 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 37.prim_prince_test.3384406538
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/37.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/370.prim_prince_test.1824070744
Short name T363
Test name
Test status
Simulation time 1558674408 ps
CPU time 27.58 seconds
Started Aug 28 06:17:30 PM UTC 24
Finished Aug 28 06:18:05 PM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1824070744 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 370.prim_prince_test.1824070744
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/370.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/371.prim_prince_test.3733278701
Short name T368
Test name
Test status
Simulation time 1647274871 ps
CPU time 29.26 seconds
Started Aug 28 06:17:33 PM UTC 24
Finished Aug 28 06:18:11 PM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3733278701 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 371.prim_prince_test.3733278701
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/371.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/372.prim_prince_test.2940746700
Short name T360
Test name
Test status
Simulation time 1172191350 ps
CPU time 20.94 seconds
Started Aug 28 06:17:34 PM UTC 24
Finished Aug 28 06:18:01 PM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2940746700 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 372.prim_prince_test.2940746700
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/372.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/373.prim_prince_test.2767213491
Short name T385
Test name
Test status
Simulation time 2698639603 ps
CPU time 47.91 seconds
Started Aug 28 06:17:35 PM UTC 24
Finished Aug 28 06:18:36 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2767213491 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 373.prim_prince_test.2767213491
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/373.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/374.prim_prince_test.3348795048
Short name T391
Test name
Test status
Simulation time 2983300267 ps
CPU time 52.46 seconds
Started Aug 28 06:17:35 PM UTC 24
Finished Aug 28 06:18:42 PM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3348795048 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 374.prim_prince_test.3348795048
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/374.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/375.prim_prince_test.1001584110
Short name T393
Test name
Test status
Simulation time 3119780698 ps
CPU time 55.09 seconds
Started Aug 28 06:17:35 PM UTC 24
Finished Aug 28 06:18:45 PM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1001584110 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 375.prim_prince_test.1001584110
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/375.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/376.prim_prince_test.2300968155
Short name T355
Test name
Test status
Simulation time 818658271 ps
CPU time 14.75 seconds
Started Aug 28 06:17:37 PM UTC 24
Finished Aug 28 06:17:57 PM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2300968155 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 376.prim_prince_test.2300968155
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/376.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/377.prim_prince_test.2379704902
Short name T358
Test name
Test status
Simulation time 877829482 ps
CPU time 15.86 seconds
Started Aug 28 06:17:39 PM UTC 24
Finished Aug 28 06:17:59 PM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2379704902 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 377.prim_prince_test.2379704902
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/377.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/378.prim_prince_test.2165405906
Short name T359
Test name
Test status
Simulation time 926322772 ps
CPU time 16.76 seconds
Started Aug 28 06:17:39 PM UTC 24
Finished Aug 28 06:18:00 PM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2165405906 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 378.prim_prince_test.2165405906
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/378.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/379.prim_prince_test.2590361086
Short name T390
Test name
Test status
Simulation time 2764249270 ps
CPU time 48.92 seconds
Started Aug 28 06:17:39 PM UTC 24
Finished Aug 28 06:18:41 PM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2590361086 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 379.prim_prince_test.2590361086
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/379.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/38.prim_prince_test.2767237521
Short name T26
Test name
Test status
Simulation time 1336737041 ps
CPU time 24.24 seconds
Started Aug 28 06:09:08 PM UTC 24
Finished Aug 28 06:09:39 PM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2767237521 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 38.prim_prince_test.2767237521
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/38.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/380.prim_prince_test.1492973839
Short name T366
Test name
Test status
Simulation time 1143161905 ps
CPU time 20.71 seconds
Started Aug 28 06:17:40 PM UTC 24
Finished Aug 28 06:18:07 PM UTC 24
Peak memory 156056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1492973839 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 380.prim_prince_test.1492973839
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/380.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/381.prim_prince_test.1221644681
Short name T395
Test name
Test status
Simulation time 3427272646 ps
CPU time 60.7 seconds
Started Aug 28 06:17:41 PM UTC 24
Finished Aug 28 06:18:58 PM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1221644681 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 381.prim_prince_test.1221644681
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/381.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/382.prim_prince_test.1915117859
Short name T377
Test name
Test status
Simulation time 1801300558 ps
CPU time 31.91 seconds
Started Aug 28 06:17:43 PM UTC 24
Finished Aug 28 06:18:24 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1915117859 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 382.prim_prince_test.1915117859
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/382.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/383.prim_prince_test.1606546011
Short name T381
Test name
Test status
Simulation time 1977995853 ps
CPU time 35.27 seconds
Started Aug 28 06:17:44 PM UTC 24
Finished Aug 28 06:18:29 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1606546011 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 383.prim_prince_test.1606546011
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/383.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/384.prim_prince_test.3816304417
Short name T388
Test name
Test status
Simulation time 2183208721 ps
CPU time 38.75 seconds
Started Aug 28 06:17:48 PM UTC 24
Finished Aug 28 06:18:37 PM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3816304417 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 384.prim_prince_test.3816304417
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/384.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/385.prim_prince_test.1312902187
Short name T376
Test name
Test status
Simulation time 1592841581 ps
CPU time 28.34 seconds
Started Aug 28 06:17:48 PM UTC 24
Finished Aug 28 06:18:24 PM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1312902187 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 385.prim_prince_test.1312902187
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/385.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/386.prim_prince_test.131040851
Short name T364
Test name
Test status
Simulation time 748053448 ps
CPU time 13.69 seconds
Started Aug 28 06:17:48 PM UTC 24
Finished Aug 28 06:18:06 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=131040851 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 386.prim_prince_test.131040851
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/386.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/387.prim_prince_test.1374157579
Short name T380
Test name
Test status
Simulation time 1511758407 ps
CPU time 27.17 seconds
Started Aug 28 06:17:51 PM UTC 24
Finished Aug 28 06:18:26 PM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1374157579 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 387.prim_prince_test.1374157579
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/387.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/388.prim_prince_test.3679092522
Short name T397
Test name
Test status
Simulation time 3109200444 ps
CPU time 54.84 seconds
Started Aug 28 06:17:51 PM UTC 24
Finished Aug 28 06:19:00 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3679092522 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 388.prim_prince_test.3679092522
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/388.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/389.prim_prince_test.1660179699
Short name T405
Test name
Test status
Simulation time 3489167842 ps
CPU time 61.68 seconds
Started Aug 28 06:17:53 PM UTC 24
Finished Aug 28 06:19:11 PM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1660179699 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 389.prim_prince_test.1660179699
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/389.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/39.prim_prince_test.1294749175
Short name T53
Test name
Test status
Simulation time 3084474977 ps
CPU time 54.82 seconds
Started Aug 28 06:09:12 PM UTC 24
Finished Aug 28 06:10:22 PM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1294749175 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 39.prim_prince_test.1294749175
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/39.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/390.prim_prince_test.3414165012
Short name T375
Test name
Test status
Simulation time 1087935309 ps
CPU time 19.57 seconds
Started Aug 28 06:17:57 PM UTC 24
Finished Aug 28 06:18:23 PM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3414165012 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 390.prim_prince_test.3414165012
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/390.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/391.prim_prince_test.4027585269
Short name T387
Test name
Test status
Simulation time 1669460905 ps
CPU time 29.75 seconds
Started Aug 28 06:17:58 PM UTC 24
Finished Aug 28 06:18:37 PM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4027585269 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 391.prim_prince_test.4027585269
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/391.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/392.prim_prince_test.726925195
Short name T403
Test name
Test status
Simulation time 3241954980 ps
CPU time 56.83 seconds
Started Aug 28 06:17:58 PM UTC 24
Finished Aug 28 06:19:11 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=726925195 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 392.prim_prince_test.726925195
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/392.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/393.prim_prince_test.3791884896
Short name T383
Test name
Test status
Simulation time 1362424119 ps
CPU time 24.41 seconds
Started Aug 28 06:18:00 PM UTC 24
Finished Aug 28 06:18:32 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3791884896 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 393.prim_prince_test.3791884896
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/393.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/394.prim_prince_test.2271977410
Short name T386
Test name
Test status
Simulation time 1509129344 ps
CPU time 27.02 seconds
Started Aug 28 06:18:02 PM UTC 24
Finished Aug 28 06:18:36 PM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2271977410 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 394.prim_prince_test.2271977410
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/394.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/395.prim_prince_test.446826528
Short name T416
Test name
Test status
Simulation time 3712793514 ps
CPU time 65.08 seconds
Started Aug 28 06:18:02 PM UTC 24
Finished Aug 28 06:19:24 PM UTC 24
Peak memory 156532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=446826528 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 395.prim_prince_test.446826528
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/395.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/396.prim_prince_test.2708577784
Short name T400
Test name
Test status
Simulation time 2736703059 ps
CPU time 48.24 seconds
Started Aug 28 06:18:05 PM UTC 24
Finished Aug 28 06:19:06 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2708577784 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 396.prim_prince_test.2708577784
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/396.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/397.prim_prince_test.3247687366
Short name T382
Test name
Test status
Simulation time 1060296856 ps
CPU time 19.08 seconds
Started Aug 28 06:18:06 PM UTC 24
Finished Aug 28 06:18:31 PM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3247687366 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 397.prim_prince_test.3247687366
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/397.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/398.prim_prince_test.3200856407
Short name T399
Test name
Test status
Simulation time 2651654393 ps
CPU time 46.72 seconds
Started Aug 28 06:18:06 PM UTC 24
Finished Aug 28 06:19:06 PM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3200856407 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 398.prim_prince_test.3200856407
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/398.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/399.prim_prince_test.2319194704
Short name T410
Test name
Test status
Simulation time 3052275690 ps
CPU time 53.68 seconds
Started Aug 28 06:18:06 PM UTC 24
Finished Aug 28 06:19:15 PM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2319194704 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 399.prim_prince_test.2319194704
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/399.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/4.prim_prince_test.3946140790
Short name T32
Test name
Test status
Simulation time 3417028444 ps
CPU time 60.82 seconds
Started Aug 28 06:08:27 PM UTC 24
Finished Aug 28 06:09:45 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3946140790 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 4.prim_prince_test.3946140790
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/4.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/40.prim_prince_test.2707875296
Short name T23
Test name
Test status
Simulation time 1002898865 ps
CPU time 18.13 seconds
Started Aug 28 06:09:14 PM UTC 24
Finished Aug 28 06:09:38 PM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2707875296 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 40.prim_prince_test.2707875296
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/40.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/400.prim_prince_test.165891026
Short name T379
Test name
Test status
Simulation time 784485201 ps
CPU time 14.08 seconds
Started Aug 28 06:18:06 PM UTC 24
Finished Aug 28 06:18:25 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=165891026 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 400.prim_prince_test.165891026
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/400.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/401.prim_prince_test.4002529874
Short name T401
Test name
Test status
Simulation time 2699968570 ps
CPU time 47.83 seconds
Started Aug 28 06:18:08 PM UTC 24
Finished Aug 28 06:19:08 PM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4002529874 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 401.prim_prince_test.4002529874
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/401.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/402.prim_prince_test.2666746242
Short name T414
Test name
Test status
Simulation time 3222547183 ps
CPU time 56.75 seconds
Started Aug 28 06:18:10 PM UTC 24
Finished Aug 28 06:19:22 PM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2666746242 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 402.prim_prince_test.2666746242
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/402.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/403.prim_prince_test.359465820
Short name T394
Test name
Test status
Simulation time 1759705126 ps
CPU time 31.2 seconds
Started Aug 28 06:18:11 PM UTC 24
Finished Aug 28 06:18:51 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=359465820 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 403.prim_prince_test.359465820
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/403.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/404.prim_prince_test.2062820767
Short name T419
Test name
Test status
Simulation time 3326552212 ps
CPU time 59.09 seconds
Started Aug 28 06:18:12 PM UTC 24
Finished Aug 28 06:19:27 PM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2062820767 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 404.prim_prince_test.2062820767
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/404.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/405.prim_prince_test.1620117385
Short name T408
Test name
Test status
Simulation time 2767333832 ps
CPU time 48.19 seconds
Started Aug 28 06:18:12 PM UTC 24
Finished Aug 28 06:19:13 PM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1620117385 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 405.prim_prince_test.1620117385
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/405.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/406.prim_prince_test.2116778991
Short name T406
Test name
Test status
Simulation time 2408899329 ps
CPU time 42.83 seconds
Started Aug 28 06:18:17 PM UTC 24
Finished Aug 28 06:19:12 PM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2116778991 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 406.prim_prince_test.2116778991
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/406.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/407.prim_prince_test.24205151
Short name T421
Test name
Test status
Simulation time 3158207462 ps
CPU time 55.91 seconds
Started Aug 28 06:18:20 PM UTC 24
Finished Aug 28 06:19:31 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=24205151 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 407.prim_prince_test.24205151
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/407.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/408.prim_prince_test.1078816869
Short name T407
Test name
Test status
Simulation time 2288823858 ps
CPU time 40.49 seconds
Started Aug 28 06:18:22 PM UTC 24
Finished Aug 28 06:19:13 PM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1078816869 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 408.prim_prince_test.1078816869
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/408.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/409.prim_prince_test.1736424788
Short name T432
Test name
Test status
Simulation time 3687538999 ps
CPU time 64.5 seconds
Started Aug 28 06:18:23 PM UTC 24
Finished Aug 28 06:19:44 PM UTC 24
Peak memory 156536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1736424788 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 409.prim_prince_test.1736424788
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/409.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/41.prim_prince_test.1545881175
Short name T62
Test name
Test status
Simulation time 3164857091 ps
CPU time 56.08 seconds
Started Aug 28 06:09:15 PM UTC 24
Finished Aug 28 06:10:26 PM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1545881175 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 41.prim_prince_test.1545881175
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/41.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/410.prim_prince_test.2475195558
Short name T425
Test name
Test status
Simulation time 3209929172 ps
CPU time 56.23 seconds
Started Aug 28 06:18:24 PM UTC 24
Finished Aug 28 06:19:35 PM UTC 24
Peak memory 154628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2475195558 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 410.prim_prince_test.2475195558
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/410.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/411.prim_prince_test.4248567556
Short name T396
Test name
Test status
Simulation time 1520967191 ps
CPU time 27.25 seconds
Started Aug 28 06:18:25 PM UTC 24
Finished Aug 28 06:19:00 PM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4248567556 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 411.prim_prince_test.4248567556
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/411.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/412.prim_prince_test.3072317049
Short name T417
Test name
Test status
Simulation time 2667743508 ps
CPU time 46.77 seconds
Started Aug 28 06:18:25 PM UTC 24
Finished Aug 28 06:19:25 PM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3072317049 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 412.prim_prince_test.3072317049
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/412.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/413.prim_prince_test.232486190
Short name T418
Test name
Test status
Simulation time 2609680193 ps
CPU time 45.76 seconds
Started Aug 28 06:18:26 PM UTC 24
Finished Aug 28 06:19:25 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=232486190 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 413.prim_prince_test.232486190
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/413.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/414.prim_prince_test.2132024647
Short name T415
Test name
Test status
Simulation time 2488390809 ps
CPU time 43.65 seconds
Started Aug 28 06:18:26 PM UTC 24
Finished Aug 28 06:19:22 PM UTC 24
Peak memory 154652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2132024647 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 414.prim_prince_test.2132024647
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/414.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/415.prim_prince_test.3342344378
Short name T411
Test name
Test status
Simulation time 2253552186 ps
CPU time 39.69 seconds
Started Aug 28 06:18:27 PM UTC 24
Finished Aug 28 06:19:17 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3342344378 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 415.prim_prince_test.3342344378
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/415.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/416.prim_prince_test.288564709
Short name T404
Test name
Test status
Simulation time 1927545167 ps
CPU time 34.43 seconds
Started Aug 28 06:18:27 PM UTC 24
Finished Aug 28 06:19:11 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=288564709 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 416.prim_prince_test.288564709
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/416.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/417.prim_prince_test.1788124218
Short name T420
Test name
Test status
Simulation time 2678209496 ps
CPU time 47.26 seconds
Started Aug 28 06:18:30 PM UTC 24
Finished Aug 28 06:19:30 PM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1788124218 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 417.prim_prince_test.1788124218
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/417.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/418.prim_prince_test.2219618192
Short name T424
Test name
Test status
Simulation time 2802335420 ps
CPU time 49.69 seconds
Started Aug 28 06:18:32 PM UTC 24
Finished Aug 28 06:19:35 PM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2219618192 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 418.prim_prince_test.2219618192
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/418.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/419.prim_prince_test.2906846593
Short name T427
Test name
Test status
Simulation time 2777089434 ps
CPU time 48.7 seconds
Started Aug 28 06:18:33 PM UTC 24
Finished Aug 28 06:19:36 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2906846593 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 419.prim_prince_test.2906846593
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/419.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/42.prim_prince_test.3674591851
Short name T54
Test name
Test status
Simulation time 2988987981 ps
CPU time 53.13 seconds
Started Aug 28 06:09:15 PM UTC 24
Finished Aug 28 06:10:23 PM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3674591851 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 42.prim_prince_test.3674591851
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/42.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/420.prim_prince_test.3877825470
Short name T422
Test name
Test status
Simulation time 2391255740 ps
CPU time 42.09 seconds
Started Aug 28 06:18:37 PM UTC 24
Finished Aug 28 06:19:32 PM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3877825470 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 420.prim_prince_test.3877825470
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/420.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/421.prim_prince_test.1651658947
Short name T398
Test name
Test status
Simulation time 1183782648 ps
CPU time 21.06 seconds
Started Aug 28 06:18:37 PM UTC 24
Finished Aug 28 06:19:06 PM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1651658947 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 421.prim_prince_test.1651658947
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/421.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/422.prim_prince_test.547082002
Short name T431
Test name
Test status
Simulation time 2945756187 ps
CPU time 52.01 seconds
Started Aug 28 06:18:38 PM UTC 24
Finished Aug 28 06:19:44 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=547082002 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 422.prim_prince_test.547082002
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/422.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/423.prim_prince_test.1918430632
Short name T409
Test name
Test status
Simulation time 1555986936 ps
CPU time 27.49 seconds
Started Aug 28 06:18:38 PM UTC 24
Finished Aug 28 06:19:14 PM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1918430632 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 423.prim_prince_test.1918430632
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/423.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/424.prim_prince_test.3606158310
Short name T433
Test name
Test status
Simulation time 3073198159 ps
CPU time 53.84 seconds
Started Aug 28 06:18:39 PM UTC 24
Finished Aug 28 06:19:48 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3606158310 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 424.prim_prince_test.3606158310
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/424.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/425.prim_prince_test.1158100263
Short name T413
Test name
Test status
Simulation time 1722604433 ps
CPU time 30.41 seconds
Started Aug 28 06:18:41 PM UTC 24
Finished Aug 28 06:19:20 PM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1158100263 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 425.prim_prince_test.1158100263
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/425.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/426.prim_prince_test.3656226290
Short name T440
Test name
Test status
Simulation time 3390089318 ps
CPU time 59.96 seconds
Started Aug 28 06:18:42 PM UTC 24
Finished Aug 28 06:19:58 PM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3656226290 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 426.prim_prince_test.3656226290
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/426.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/427.prim_prince_test.2924962481
Short name T402
Test name
Test status
Simulation time 1068460924 ps
CPU time 19.4 seconds
Started Aug 28 06:18:43 PM UTC 24
Finished Aug 28 06:19:09 PM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2924962481 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 427.prim_prince_test.2924962481
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/427.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/428.prim_prince_test.2307154967
Short name T412
Test name
Test status
Simulation time 1512652568 ps
CPU time 27.17 seconds
Started Aug 28 06:18:44 PM UTC 24
Finished Aug 28 06:19:19 PM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2307154967 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 428.prim_prince_test.2307154967
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/428.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/429.prim_prince_test.794793386
Short name T443
Test name
Test status
Simulation time 3316635160 ps
CPU time 58.61 seconds
Started Aug 28 06:18:45 PM UTC 24
Finished Aug 28 06:20:00 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=794793386 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 429.prim_prince_test.794793386
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/429.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/43.prim_prince_test.3998847070
Short name T60
Test name
Test status
Simulation time 2862569470 ps
CPU time 51.23 seconds
Started Aug 28 06:09:20 PM UTC 24
Finished Aug 28 06:10:25 PM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3998847070 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 43.prim_prince_test.3998847070
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/43.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/430.prim_prince_test.187292634
Short name T437
Test name
Test status
Simulation time 2747339464 ps
CPU time 48.59 seconds
Started Aug 28 06:18:52 PM UTC 24
Finished Aug 28 06:19:53 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=187292634 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 430.prim_prince_test.187292634
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/430.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/431.prim_prince_test.1949069796
Short name T450
Test name
Test status
Simulation time 3050365730 ps
CPU time 53.64 seconds
Started Aug 28 06:18:59 PM UTC 24
Finished Aug 28 06:20:07 PM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1949069796 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 431.prim_prince_test.1949069796
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/431.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/432.prim_prince_test.1357417956
Short name T429
Test name
Test status
Simulation time 1753870121 ps
CPU time 30.94 seconds
Started Aug 28 06:19:01 PM UTC 24
Finished Aug 28 06:19:41 PM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1357417956 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 432.prim_prince_test.1357417956
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/432.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/433.prim_prince_test.2470519968
Short name T449
Test name
Test status
Simulation time 2885142372 ps
CPU time 50.98 seconds
Started Aug 28 06:19:01 PM UTC 24
Finished Aug 28 06:20:06 PM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2470519968 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 433.prim_prince_test.2470519968
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/433.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/434.prim_prince_test.2973871531
Short name T430
Test name
Test status
Simulation time 1556052583 ps
CPU time 27.78 seconds
Started Aug 28 06:19:06 PM UTC 24
Finished Aug 28 06:19:42 PM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2973871531 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 434.prim_prince_test.2973871531
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/434.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/435.prim_prince_test.2589261947
Short name T452
Test name
Test status
Simulation time 2916422846 ps
CPU time 51.41 seconds
Started Aug 28 06:19:06 PM UTC 24
Finished Aug 28 06:20:12 PM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2589261947 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 435.prim_prince_test.2589261947
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/435.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/436.prim_prince_test.3571864077
Short name T453
Test name
Test status
Simulation time 2911746796 ps
CPU time 51.31 seconds
Started Aug 28 06:19:08 PM UTC 24
Finished Aug 28 06:20:13 PM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3571864077 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 436.prim_prince_test.3571864077
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/436.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/437.prim_prince_test.3455442221
Short name T436
Test name
Test status
Simulation time 1960625117 ps
CPU time 34.83 seconds
Started Aug 28 06:19:09 PM UTC 24
Finished Aug 28 06:19:53 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3455442221 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 437.prim_prince_test.3455442221
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/437.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/438.prim_prince_test.4277230132
Short name T442
Test name
Test status
Simulation time 2171093656 ps
CPU time 38.33 seconds
Started Aug 28 06:19:10 PM UTC 24
Finished Aug 28 06:19:59 PM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4277230132 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 438.prim_prince_test.4277230132
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/438.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/439.prim_prince_test.3528766021
Short name T470
Test name
Test status
Simulation time 3593654402 ps
CPU time 63.35 seconds
Started Aug 28 06:19:11 PM UTC 24
Finished Aug 28 06:20:31 PM UTC 24
Peak memory 156432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3528766021 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 439.prim_prince_test.3528766021
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/439.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/44.prim_prince_test.3596728285
Short name T52
Test name
Test status
Simulation time 2436619168 ps
CPU time 43.42 seconds
Started Aug 28 06:09:21 PM UTC 24
Finished Aug 28 06:10:17 PM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3596728285 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 44.prim_prince_test.3596728285
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/44.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/440.prim_prince_test.298307955
Short name T455
Test name
Test status
Simulation time 2911069159 ps
CPU time 51.57 seconds
Started Aug 28 06:19:11 PM UTC 24
Finished Aug 28 06:20:17 PM UTC 24
Peak memory 154584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=298307955 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 440.prim_prince_test.298307955
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/440.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/441.prim_prince_test.2863515152
Short name T459
Test name
Test status
Simulation time 3079725000 ps
CPU time 54.23 seconds
Started Aug 28 06:19:12 PM UTC 24
Finished Aug 28 06:20:21 PM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2863515152 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 441.prim_prince_test.2863515152
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/441.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/442.prim_prince_test.3098575410
Short name T428
Test name
Test status
Simulation time 1118275382 ps
CPU time 20.05 seconds
Started Aug 28 06:19:12 PM UTC 24
Finished Aug 28 06:19:39 PM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3098575410 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 442.prim_prince_test.3098575410
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/442.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/443.prim_prince_test.3749455304
Short name T444
Test name
Test status
Simulation time 2061310527 ps
CPU time 36.48 seconds
Started Aug 28 06:19:14 PM UTC 24
Finished Aug 28 06:20:00 PM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3749455304 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 443.prim_prince_test.3749455304
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/443.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/444.prim_prince_test.848756555
Short name T423
Test name
Test status
Simulation time 817020251 ps
CPU time 14.67 seconds
Started Aug 28 06:19:15 PM UTC 24
Finished Aug 28 06:19:34 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=848756555 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 444.prim_prince_test.848756555
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/444.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/445.prim_prince_test.3930314233
Short name T426
Test name
Test status
Simulation time 862927708 ps
CPU time 15.73 seconds
Started Aug 28 06:19:15 PM UTC 24
Finished Aug 28 06:19:35 PM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3930314233 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 445.prim_prince_test.3930314233
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/445.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/446.prim_prince_test.1630618300
Short name T434
Test name
Test status
Simulation time 1444147816 ps
CPU time 25.77 seconds
Started Aug 28 06:19:16 PM UTC 24
Finished Aug 28 06:19:49 PM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1630618300 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 446.prim_prince_test.1630618300
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/446.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/447.prim_prince_test.3215515813
Short name T457
Test name
Test status
Simulation time 2798251432 ps
CPU time 49.25 seconds
Started Aug 28 06:19:18 PM UTC 24
Finished Aug 28 06:20:21 PM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3215515813 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 447.prim_prince_test.3215515813
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/447.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/448.prim_prince_test.3508015233
Short name T438
Test name
Test status
Simulation time 1447195271 ps
CPU time 25.56 seconds
Started Aug 28 06:19:21 PM UTC 24
Finished Aug 28 06:19:54 PM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3508015233 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 448.prim_prince_test.3508015233
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/448.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/449.prim_prince_test.4221271765
Short name T469
Test name
Test status
Simulation time 3142754645 ps
CPU time 55.29 seconds
Started Aug 28 06:19:21 PM UTC 24
Finished Aug 28 06:20:31 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4221271765 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 449.prim_prince_test.4221271765
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/449.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/45.prim_prince_test.3181333101
Short name T36
Test name
Test status
Simulation time 1143655492 ps
CPU time 20.57 seconds
Started Aug 28 06:09:21 PM UTC 24
Finished Aug 28 06:09:48 PM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3181333101 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 45.prim_prince_test.3181333101
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/45.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/450.prim_prince_test.3616931913
Short name T476
Test name
Test status
Simulation time 3435837271 ps
CPU time 60.59 seconds
Started Aug 28 06:19:23 PM UTC 24
Finished Aug 28 06:20:39 PM UTC 24
Peak memory 154628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3616931913 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 450.prim_prince_test.3616931913
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/450.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/451.prim_prince_test.962618861
Short name T456
Test name
Test status
Simulation time 2486171134 ps
CPU time 43.79 seconds
Started Aug 28 06:19:23 PM UTC 24
Finished Aug 28 06:20:19 PM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=962618861 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 451.prim_prince_test.962618861
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/451.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/452.prim_prince_test.3136669846
Short name T451
Test name
Test status
Simulation time 2041855331 ps
CPU time 36.08 seconds
Started Aug 28 06:19:25 PM UTC 24
Finished Aug 28 06:20:11 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3136669846 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 452.prim_prince_test.3136669846
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/452.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/453.prim_prince_test.3029743086
Short name T472
Test name
Test status
Simulation time 3039741208 ps
CPU time 53.58 seconds
Started Aug 28 06:19:25 PM UTC 24
Finished Aug 28 06:20:33 PM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3029743086 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 453.prim_prince_test.3029743086
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/453.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/454.prim_prince_test.291682548
Short name T463
Test name
Test status
Simulation time 2574079594 ps
CPU time 45.35 seconds
Started Aug 28 06:19:25 PM UTC 24
Finished Aug 28 06:20:23 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=291682548 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 454.prim_prince_test.291682548
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/454.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/455.prim_prince_test.4242575745
Short name T467
Test name
Test status
Simulation time 2657823647 ps
CPU time 46.67 seconds
Started Aug 28 06:19:28 PM UTC 24
Finished Aug 28 06:20:27 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4242575745 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 455.prim_prince_test.4242575745
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/455.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/456.prim_prince_test.3928902534
Short name T441
Test name
Test status
Simulation time 1192677494 ps
CPU time 21.53 seconds
Started Aug 28 06:19:31 PM UTC 24
Finished Aug 28 06:19:58 PM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3928902534 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 456.prim_prince_test.3928902534
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/456.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/457.prim_prince_test.1725145627
Short name T466
Test name
Test status
Simulation time 2368992350 ps
CPU time 41.95 seconds
Started Aug 28 06:19:32 PM UTC 24
Finished Aug 28 06:20:25 PM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1725145627 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 457.prim_prince_test.1725145627
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/457.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/458.prim_prince_test.1336748946
Short name T435
Test name
Test status
Simulation time 793773196 ps
CPU time 14.33 seconds
Started Aug 28 06:19:33 PM UTC 24
Finished Aug 28 06:19:52 PM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1336748946 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 458.prim_prince_test.1336748946
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/458.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/459.prim_prince_test.3142267029
Short name T474
Test name
Test status
Simulation time 2824822352 ps
CPU time 49.56 seconds
Started Aug 28 06:19:35 PM UTC 24
Finished Aug 28 06:20:38 PM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3142267029 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 459.prim_prince_test.3142267029
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/459.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/46.prim_prince_test.2815060670
Short name T45
Test name
Test status
Simulation time 1958787047 ps
CPU time 34.94 seconds
Started Aug 28 06:09:22 PM UTC 24
Finished Aug 28 06:10:07 PM UTC 24
Peak memory 154580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2815060670 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 46.prim_prince_test.2815060670
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/46.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/460.prim_prince_test.3925193009
Short name T460
Test name
Test status
Simulation time 1975579140 ps
CPU time 34.91 seconds
Started Aug 28 06:19:37 PM UTC 24
Finished Aug 28 06:20:21 PM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3925193009 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 460.prim_prince_test.3925193009
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/460.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/461.prim_prince_test.2117360235
Short name T475
Test name
Test status
Simulation time 2758063615 ps
CPU time 48.72 seconds
Started Aug 28 06:19:37 PM UTC 24
Finished Aug 28 06:20:39 PM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2117360235 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 461.prim_prince_test.2117360235
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/461.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/462.prim_prince_test.243673188
Short name T439
Test name
Test status
Simulation time 850161040 ps
CPU time 15.47 seconds
Started Aug 28 06:19:37 PM UTC 24
Finished Aug 28 06:19:57 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=243673188 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 462.prim_prince_test.243673188
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/462.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/463.prim_prince_test.463584958
Short name T448
Test name
Test status
Simulation time 1246666156 ps
CPU time 22.27 seconds
Started Aug 28 06:19:37 PM UTC 24
Finished Aug 28 06:20:05 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=463584958 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 463.prim_prince_test.463584958
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/463.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/464.prim_prince_test.58388797
Short name T458
Test name
Test status
Simulation time 1860681952 ps
CPU time 32.85 seconds
Started Aug 28 06:19:39 PM UTC 24
Finished Aug 28 06:20:21 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=58388797 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 464.prim_prince_test.58388797
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/464.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/465.prim_prince_test.3379618440
Short name T445
Test name
Test status
Simulation time 855339288 ps
CPU time 15.41 seconds
Started Aug 28 06:19:42 PM UTC 24
Finished Aug 28 06:20:02 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3379618440 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 465.prim_prince_test.3379618440
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/465.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/466.prim_prince_test.436932031
Short name T480
Test name
Test status
Simulation time 2676693022 ps
CPU time 47.3 seconds
Started Aug 28 06:19:43 PM UTC 24
Finished Aug 28 06:20:43 PM UTC 24
Peak memory 154436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=436932031 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 466.prim_prince_test.436932031
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/466.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/467.prim_prince_test.821520354
Short name T464
Test name
Test status
Simulation time 1750544758 ps
CPU time 30.99 seconds
Started Aug 28 06:19:43 PM UTC 24
Finished Aug 28 06:20:23 PM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=821520354 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 467.prim_prince_test.821520354
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/467.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/468.prim_prince_test.3011789657
Short name T447
Test name
Test status
Simulation time 812860055 ps
CPU time 14.51 seconds
Started Aug 28 06:19:46 PM UTC 24
Finished Aug 28 06:20:05 PM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3011789657 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 468.prim_prince_test.3011789657
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/468.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/469.prim_prince_test.3075524995
Short name T446
Test name
Test status
Simulation time 774633355 ps
CPU time 13.97 seconds
Started Aug 28 06:19:46 PM UTC 24
Finished Aug 28 06:20:04 PM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3075524995 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 469.prim_prince_test.3075524995
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/469.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/47.prim_prince_test.829227866
Short name T38
Test name
Test status
Simulation time 1128533301 ps
CPU time 20.34 seconds
Started Aug 28 06:09:23 PM UTC 24
Finished Aug 28 06:09:50 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=829227866 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 47.prim_prince_test.829227866
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/47.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/470.prim_prince_test.837931360
Short name T454
Test name
Test status
Simulation time 1057975299 ps
CPU time 18.97 seconds
Started Aug 28 06:19:49 PM UTC 24
Finished Aug 28 06:20:13 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=837931360 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 470.prim_prince_test.837931360
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/470.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/471.prim_prince_test.1661241519
Short name T483
Test name
Test status
Simulation time 2657598764 ps
CPU time 46.67 seconds
Started Aug 28 06:19:50 PM UTC 24
Finished Aug 28 06:20:49 PM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1661241519 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 471.prim_prince_test.1661241519
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/471.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/472.prim_prince_test.4195483291
Short name T494
Test name
Test status
Simulation time 3644115219 ps
CPU time 63.06 seconds
Started Aug 28 06:19:53 PM UTC 24
Finished Aug 28 06:21:13 PM UTC 24
Peak memory 156536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4195483291 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 472.prim_prince_test.4195483291
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/472.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/473.prim_prince_test.635972978
Short name T491
Test name
Test status
Simulation time 3295438359 ps
CPU time 57.46 seconds
Started Aug 28 06:19:55 PM UTC 24
Finished Aug 28 06:21:07 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=635972978 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 473.prim_prince_test.635972978
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/473.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/474.prim_prince_test.1707137263
Short name T468
Test name
Test status
Simulation time 1523510956 ps
CPU time 27.1 seconds
Started Aug 28 06:19:55 PM UTC 24
Finished Aug 28 06:20:29 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1707137263 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 474.prim_prince_test.1707137263
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/474.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/475.prim_prince_test.4091317097
Short name T461
Test name
Test status
Simulation time 1219982955 ps
CPU time 21.69 seconds
Started Aug 28 06:19:55 PM UTC 24
Finished Aug 28 06:20:23 PM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4091317097 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 475.prim_prince_test.4091317097
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/475.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/476.prim_prince_test.2374225140
Short name T486
Test name
Test status
Simulation time 2625314652 ps
CPU time 46.79 seconds
Started Aug 28 06:19:58 PM UTC 24
Finished Aug 28 06:20:57 PM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2374225140 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 476.prim_prince_test.2374225140
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/476.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/477.prim_prince_test.1665624211
Short name T471
Test name
Test status
Simulation time 1435422363 ps
CPU time 25.5 seconds
Started Aug 28 06:19:59 PM UTC 24
Finished Aug 28 06:20:32 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1665624211 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 477.prim_prince_test.1665624211
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/477.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/478.prim_prince_test.2508486794
Short name T465
Test name
Test status
Simulation time 1097052728 ps
CPU time 19.48 seconds
Started Aug 28 06:19:59 PM UTC 24
Finished Aug 28 06:20:25 PM UTC 24
Peak memory 154572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2508486794 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 478.prim_prince_test.2508486794
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/478.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/479.prim_prince_test.225889822
Short name T473
Test name
Test status
Simulation time 1547563347 ps
CPU time 27.45 seconds
Started Aug 28 06:20:00 PM UTC 24
Finished Aug 28 06:20:36 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=225889822 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 479.prim_prince_test.225889822
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/479.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/48.prim_prince_test.3585371994
Short name T44
Test name
Test status
Simulation time 1800685644 ps
CPU time 32.01 seconds
Started Aug 28 06:09:23 PM UTC 24
Finished Aug 28 06:10:04 PM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3585371994 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 48.prim_prince_test.3585371994
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/48.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/480.prim_prince_test.1311216074
Short name T489
Test name
Test status
Simulation time 2744272193 ps
CPU time 48.21 seconds
Started Aug 28 06:20:02 PM UTC 24
Finished Aug 28 06:21:03 PM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1311216074 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 480.prim_prince_test.1311216074
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/480.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/481.prim_prince_test.3497474668
Short name T484
Test name
Test status
Simulation time 2213858910 ps
CPU time 39.16 seconds
Started Aug 28 06:20:02 PM UTC 24
Finished Aug 28 06:20:51 PM UTC 24
Peak memory 154644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3497474668 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 481.prim_prince_test.3497474668
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/481.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/482.prim_prince_test.1805695169
Short name T462
Test name
Test status
Simulation time 809762834 ps
CPU time 14.57 seconds
Started Aug 28 06:20:03 PM UTC 24
Finished Aug 28 06:20:23 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1805695169 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 482.prim_prince_test.1805695169
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/482.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/483.prim_prince_test.3632621576
Short name T493
Test name
Test status
Simulation time 3095046347 ps
CPU time 53 seconds
Started Aug 28 06:20:05 PM UTC 24
Finished Aug 28 06:21:13 PM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3632621576 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 483.prim_prince_test.3632621576
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/483.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/484.prim_prince_test.1669782458
Short name T479
Test name
Test status
Simulation time 1561412328 ps
CPU time 27.64 seconds
Started Aug 28 06:20:06 PM UTC 24
Finished Aug 28 06:20:42 PM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1669782458 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 484.prim_prince_test.1669782458
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/484.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/485.prim_prince_test.1781865193
Short name T481
Test name
Test status
Simulation time 1796650853 ps
CPU time 31.8 seconds
Started Aug 28 06:20:06 PM UTC 24
Finished Aug 28 06:20:47 PM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1781865193 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 485.prim_prince_test.1781865193
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/485.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/486.prim_prince_test.2178876714
Short name T497
Test name
Test status
Simulation time 3154234039 ps
CPU time 54.92 seconds
Started Aug 28 06:20:08 PM UTC 24
Finished Aug 28 06:21:18 PM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2178876714 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 486.prim_prince_test.2178876714
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/486.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/487.prim_prince_test.967755674
Short name T487
Test name
Test status
Simulation time 2318047313 ps
CPU time 40.8 seconds
Started Aug 28 06:20:08 PM UTC 24
Finished Aug 28 06:21:00 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=967755674 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 487.prim_prince_test.967755674
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/487.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/488.prim_prince_test.657932723
Short name T478
Test name
Test status
Simulation time 1329878039 ps
CPU time 23.62 seconds
Started Aug 28 06:20:12 PM UTC 24
Finished Aug 28 06:20:42 PM UTC 24
Peak memory 154580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=657932723 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 488.prim_prince_test.657932723
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/488.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/489.prim_prince_test.1465057325
Short name T490
Test name
Test status
Simulation time 2384244348 ps
CPU time 41.11 seconds
Started Aug 28 06:20:13 PM UTC 24
Finished Aug 28 06:21:06 PM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1465057325 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 489.prim_prince_test.1465057325
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/489.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/49.prim_prince_test.2548889627
Short name T43
Test name
Test status
Simulation time 1497578545 ps
CPU time 27.23 seconds
Started Aug 28 06:09:25 PM UTC 24
Finished Aug 28 06:10:00 PM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2548889627 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 49.prim_prince_test.2548889627
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/49.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/490.prim_prince_test.1993976571
Short name T498
Test name
Test status
Simulation time 2985051051 ps
CPU time 51.26 seconds
Started Aug 28 06:20:13 PM UTC 24
Finished Aug 28 06:21:19 PM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1993976571 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 490.prim_prince_test.1993976571
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/490.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/491.prim_prince_test.854629151
Short name T495
Test name
Test status
Simulation time 2670754498 ps
CPU time 46.26 seconds
Started Aug 28 06:20:14 PM UTC 24
Finished Aug 28 06:21:13 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=854629151 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 491.prim_prince_test.854629151
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/491.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/492.prim_prince_test.3444783059
Short name T477
Test name
Test status
Simulation time 1051337293 ps
CPU time 18.99 seconds
Started Aug 28 06:20:17 PM UTC 24
Finished Aug 28 06:20:42 PM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3444783059 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 492.prim_prince_test.3444783059
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/492.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/493.prim_prince_test.2338180915
Short name T485
Test name
Test status
Simulation time 1482649806 ps
CPU time 26.59 seconds
Started Aug 28 06:20:20 PM UTC 24
Finished Aug 28 06:20:54 PM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2338180915 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 493.prim_prince_test.2338180915
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/493.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/494.prim_prince_test.2556818737
Short name T482
Test name
Test status
Simulation time 1133345199 ps
CPU time 19.91 seconds
Started Aug 28 06:20:22 PM UTC 24
Finished Aug 28 06:20:48 PM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2556818737 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 494.prim_prince_test.2556818737
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/494.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/495.prim_prince_test.554371709
Short name T500
Test name
Test status
Simulation time 3143172289 ps
CPU time 59.2 seconds
Started Aug 28 06:20:22 PM UTC 24
Finished Aug 28 06:21:38 PM UTC 24
Peak memory 156532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=554371709 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 495.prim_prince_test.554371709
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/495.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/496.prim_prince_test.1818294455
Short name T488
Test name
Test status
Simulation time 1731734225 ps
CPU time 30.45 seconds
Started Aug 28 06:20:22 PM UTC 24
Finished Aug 28 06:21:01 PM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1818294455 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 496.prim_prince_test.1818294455
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/496.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/497.prim_prince_test.937308112
Short name T492
Test name
Test status
Simulation time 2194539813 ps
CPU time 38.74 seconds
Started Aug 28 06:20:22 PM UTC 24
Finished Aug 28 06:21:12 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=937308112 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 497.prim_prince_test.937308112
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/497.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/498.prim_prince_test.3968746186
Short name T499
Test name
Test status
Simulation time 3137904200 ps
CPU time 58.17 seconds
Started Aug 28 06:20:22 PM UTC 24
Finished Aug 28 06:21:37 PM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3968746186 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 498.prim_prince_test.3968746186
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/498.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/499.prim_prince_test.2122643269
Short name T496
Test name
Test status
Simulation time 2298447722 ps
CPU time 39.54 seconds
Started Aug 28 06:20:24 PM UTC 24
Finished Aug 28 06:21:14 PM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2122643269 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 499.prim_prince_test.2122643269
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/499.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/5.prim_prince_test.394309435
Short name T17
Test name
Test status
Simulation time 2341648590 ps
CPU time 42.25 seconds
Started Aug 28 06:08:28 PM UTC 24
Finished Aug 28 06:09:22 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=394309435 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 5.prim_prince_test.394309435
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/5.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/50.prim_prince_test.1710058033
Short name T49
Test name
Test status
Simulation time 2124045954 ps
CPU time 37.59 seconds
Started Aug 28 06:09:26 PM UTC 24
Finished Aug 28 06:10:14 PM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1710058033 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 50.prim_prince_test.1710058033
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/50.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/51.prim_prince_test.1551861473
Short name T46
Test name
Test status
Simulation time 1368685052 ps
CPU time 24.86 seconds
Started Aug 28 06:09:36 PM UTC 24
Finished Aug 28 06:10:08 PM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1551861473 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 51.prim_prince_test.1551861473
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/51.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/52.prim_prince_test.3137594870
Short name T55
Test name
Test status
Simulation time 2006449798 ps
CPU time 36.32 seconds
Started Aug 28 06:09:37 PM UTC 24
Finished Aug 28 06:10:23 PM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3137594870 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 52.prim_prince_test.3137594870
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/52.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/53.prim_prince_test.3994422676
Short name T57
Test name
Test status
Simulation time 2003898775 ps
CPU time 35.32 seconds
Started Aug 28 06:09:39 PM UTC 24
Finished Aug 28 06:10:24 PM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3994422676 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 53.prim_prince_test.3994422676
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/53.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/54.prim_prince_test.3642307864
Short name T68
Test name
Test status
Simulation time 2857899205 ps
CPU time 50.49 seconds
Started Aug 28 06:09:40 PM UTC 24
Finished Aug 28 06:10:44 PM UTC 24
Peak memory 154640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3642307864 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 54.prim_prince_test.3642307864
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/54.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/55.prim_prince_test.3566576149
Short name T59
Test name
Test status
Simulation time 1968912926 ps
CPU time 35.39 seconds
Started Aug 28 06:09:40 PM UTC 24
Finished Aug 28 06:10:25 PM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3566576149 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 55.prim_prince_test.3566576149
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/55.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/56.prim_prince_test.204913147
Short name T64
Test name
Test status
Simulation time 2281562270 ps
CPU time 40.59 seconds
Started Aug 28 06:09:40 PM UTC 24
Finished Aug 28 06:10:32 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=204913147 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 56.prim_prince_test.204913147
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/56.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/57.prim_prince_test.2827570516
Short name T73
Test name
Test status
Simulation time 3110643859 ps
CPU time 55.18 seconds
Started Aug 28 06:09:40 PM UTC 24
Finished Aug 28 06:10:50 PM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2827570516 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 57.prim_prince_test.2827570516
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/57.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/58.prim_prince_test.1716917369
Short name T50
Test name
Test status
Simulation time 1386322544 ps
CPU time 24.83 seconds
Started Aug 28 06:09:42 PM UTC 24
Finished Aug 28 06:10:14 PM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1716917369 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 58.prim_prince_test.1716917369
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/58.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/59.prim_prince_test.4032474344
Short name T63
Test name
Test status
Simulation time 1952151892 ps
CPU time 35.14 seconds
Started Aug 28 06:09:42 PM UTC 24
Finished Aug 28 06:10:27 PM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4032474344 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 59.prim_prince_test.4032474344
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/59.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/6.prim_prince_test.649519115
Short name T2
Test name
Test status
Simulation time 914651212 ps
CPU time 16.77 seconds
Started Aug 28 06:08:28 PM UTC 24
Finished Aug 28 06:08:50 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=649519115 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 6.prim_prince_test.649519115
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/6.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/60.prim_prince_test.2388180606
Short name T82
Test name
Test status
Simulation time 3389022735 ps
CPU time 59.94 seconds
Started Aug 28 06:09:45 PM UTC 24
Finished Aug 28 06:11:01 PM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2388180606 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 60.prim_prince_test.2388180606
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/60.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/61.prim_prince_test.1214469193
Short name T48
Test name
Test status
Simulation time 1028561481 ps
CPU time 18.94 seconds
Started Aug 28 06:09:45 PM UTC 24
Finished Aug 28 06:10:10 PM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1214469193 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 61.prim_prince_test.1214469193
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/61.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/62.prim_prince_test.3755828071
Short name T67
Test name
Test status
Simulation time 2499017103 ps
CPU time 44.35 seconds
Started Aug 28 06:09:45 PM UTC 24
Finished Aug 28 06:10:42 PM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3755828071 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 62.prim_prince_test.3755828071
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/62.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/63.prim_prince_test.295035710
Short name T56
Test name
Test status
Simulation time 1635266508 ps
CPU time 29.12 seconds
Started Aug 28 06:09:46 PM UTC 24
Finished Aug 28 06:10:23 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=295035710 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 63.prim_prince_test.295035710
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/63.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/64.prim_prince_test.4199385016
Short name T58
Test name
Test status
Simulation time 1602562238 ps
CPU time 28.91 seconds
Started Aug 28 06:09:47 PM UTC 24
Finished Aug 28 06:10:24 PM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4199385016 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 64.prim_prince_test.4199385016
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/64.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/65.prim_prince_test.1338856952
Short name T65
Test name
Test status
Simulation time 2029569071 ps
CPU time 36.02 seconds
Started Aug 28 06:09:49 PM UTC 24
Finished Aug 28 06:10:35 PM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1338856952 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 65.prim_prince_test.1338856952
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/65.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/66.prim_prince_test.1025338620
Short name T79
Test name
Test status
Simulation time 3049839078 ps
CPU time 54.55 seconds
Started Aug 28 06:09:49 PM UTC 24
Finished Aug 28 06:10:58 PM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1025338620 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 66.prim_prince_test.1025338620
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/66.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/67.prim_prince_test.1520421680
Short name T51
Test name
Test status
Simulation time 1125150994 ps
CPU time 20.26 seconds
Started Aug 28 06:09:50 PM UTC 24
Finished Aug 28 06:10:17 PM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1520421680 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 67.prim_prince_test.1520421680
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/67.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/68.prim_prince_test.1850013982
Short name T90
Test name
Test status
Simulation time 3747192525 ps
CPU time 66.6 seconds
Started Aug 28 06:09:50 PM UTC 24
Finished Aug 28 06:11:15 PM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1850013982 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 68.prim_prince_test.1850013982
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/68.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/69.prim_prince_test.418302921
Short name T70
Test name
Test status
Simulation time 2202405347 ps
CPU time 39.04 seconds
Started Aug 28 06:09:54 PM UTC 24
Finished Aug 28 06:10:44 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=418302921 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 69.prim_prince_test.418302921
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/69.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/7.prim_prince_test.1640154636
Short name T37
Test name
Test status
Simulation time 3586308769 ps
CPU time 63.94 seconds
Started Aug 28 06:08:29 PM UTC 24
Finished Aug 28 06:09:50 PM UTC 24
Peak memory 154652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1640154636 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 7.prim_prince_test.1640154636
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/7.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/70.prim_prince_test.1948381698
Short name T74
Test name
Test status
Simulation time 2458473262 ps
CPU time 43.89 seconds
Started Aug 28 06:09:54 PM UTC 24
Finished Aug 28 06:10:50 PM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1948381698 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 70.prim_prince_test.1948381698
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/70.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/71.prim_prince_test.3709650240
Short name T66
Test name
Test status
Simulation time 1682018332 ps
CPU time 30.37 seconds
Started Aug 28 06:09:57 PM UTC 24
Finished Aug 28 06:10:36 PM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3709650240 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 71.prim_prince_test.3709650240
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/71.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/72.prim_prince_test.2511098328
Short name T80
Test name
Test status
Simulation time 2654156581 ps
CPU time 47.42 seconds
Started Aug 28 06:09:59 PM UTC 24
Finished Aug 28 06:10:59 PM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2511098328 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 72.prim_prince_test.2511098328
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/72.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/73.prim_prince_test.71306331
Short name T76
Test name
Test status
Simulation time 2305496760 ps
CPU time 40.91 seconds
Started Aug 28 06:10:02 PM UTC 24
Finished Aug 28 06:10:54 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=71306331 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 73.prim_prince_test.71306331
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/73.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/74.prim_prince_test.3106460199
Short name T61
Test name
Test status
Simulation time 854250334 ps
CPU time 15.38 seconds
Started Aug 28 06:10:06 PM UTC 24
Finished Aug 28 06:10:26 PM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3106460199 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 74.prim_prince_test.3106460199
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/74.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/75.prim_prince_test.1664305342
Short name T96
Test name
Test status
Simulation time 3305094161 ps
CPU time 58.71 seconds
Started Aug 28 06:10:08 PM UTC 24
Finished Aug 28 06:11:22 PM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1664305342 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 75.prim_prince_test.1664305342
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/75.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/76.prim_prince_test.1767196893
Short name T71
Test name
Test status
Simulation time 1569573220 ps
CPU time 28.13 seconds
Started Aug 28 06:10:09 PM UTC 24
Finished Aug 28 06:10:45 PM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1767196893 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 76.prim_prince_test.1767196893
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/76.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/77.prim_prince_test.182079677
Short name T97
Test name
Test status
Simulation time 3330423884 ps
CPU time 59.04 seconds
Started Aug 28 06:10:10 PM UTC 24
Finished Aug 28 06:11:25 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=182079677 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 77.prim_prince_test.182079677
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/77.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/78.prim_prince_test.641729933
Short name T75
Test name
Test status
Simulation time 1674374414 ps
CPU time 30.09 seconds
Started Aug 28 06:10:14 PM UTC 24
Finished Aug 28 06:10:53 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=641729933 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 78.prim_prince_test.641729933
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/78.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/79.prim_prince_test.3554540407
Short name T88
Test name
Test status
Simulation time 2550687717 ps
CPU time 45.07 seconds
Started Aug 28 06:10:15 PM UTC 24
Finished Aug 28 06:11:12 PM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3554540407 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 79.prim_prince_test.3554540407
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/79.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/8.prim_prince_test.1833163394
Short name T39
Test name
Test status
Simulation time 3715217391 ps
CPU time 65.86 seconds
Started Aug 28 06:08:30 PM UTC 24
Finished Aug 28 06:09:53 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1833163394 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 8.prim_prince_test.1833163394
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/8.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/80.prim_prince_test.1659362353
Short name T85
Test name
Test status
Simulation time 2176898780 ps
CPU time 38.73 seconds
Started Aug 28 06:10:17 PM UTC 24
Finished Aug 28 06:11:07 PM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1659362353 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 80.prim_prince_test.1659362353
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/80.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/81.prim_prince_test.604832281
Short name T77
Test name
Test status
Simulation time 1744702938 ps
CPU time 31.08 seconds
Started Aug 28 06:10:17 PM UTC 24
Finished Aug 28 06:10:57 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=604832281 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 81.prim_prince_test.604832281
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/81.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/82.prim_prince_test.1823626555
Short name T72
Test name
Test status
Simulation time 1172559103 ps
CPU time 21.05 seconds
Started Aug 28 06:10:22 PM UTC 24
Finished Aug 28 06:10:50 PM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1823626555 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 82.prim_prince_test.1823626555
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/82.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/83.prim_prince_test.4257018749
Short name T69
Test name
Test status
Simulation time 911770644 ps
CPU time 16.51 seconds
Started Aug 28 06:10:22 PM UTC 24
Finished Aug 28 06:10:44 PM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4257018749 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 83.prim_prince_test.4257018749
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/83.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/84.prim_prince_test.1811595130
Short name T110
Test name
Test status
Simulation time 3539898151 ps
CPU time 62.72 seconds
Started Aug 28 06:10:23 PM UTC 24
Finished Aug 28 06:11:43 PM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1811595130 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 84.prim_prince_test.1811595130
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/84.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/85.prim_prince_test.3895001715
Short name T87
Test name
Test status
Simulation time 2149849721 ps
CPU time 38.09 seconds
Started Aug 28 06:10:23 PM UTC 24
Finished Aug 28 06:11:12 PM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3895001715 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 85.prim_prince_test.3895001715
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/85.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/86.prim_prince_test.3049669174
Short name T86
Test name
Test status
Simulation time 1864079787 ps
CPU time 33.23 seconds
Started Aug 28 06:10:24 PM UTC 24
Finished Aug 28 06:11:07 PM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3049669174 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 86.prim_prince_test.3049669174
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/86.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/87.prim_prince_test.3916375887
Short name T47
Test name
Test status
Simulation time 925410950 ps
CPU time 16.76 seconds
Started Aug 28 06:10:25 PM UTC 24
Finished Aug 28 06:10:48 PM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3916375887 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 87.prim_prince_test.3916375887
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/87.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/88.prim_prince_test.1435587546
Short name T95
Test name
Test status
Simulation time 2448873252 ps
CPU time 43.91 seconds
Started Aug 28 06:10:25 PM UTC 24
Finished Aug 28 06:11:22 PM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1435587546 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 88.prim_prince_test.1435587546
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/88.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/89.prim_prince_test.1969669836
Short name T101
Test name
Test status
Simulation time 2757437176 ps
CPU time 49.24 seconds
Started Aug 28 06:10:25 PM UTC 24
Finished Aug 28 06:11:28 PM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1969669836 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 89.prim_prince_test.1969669836
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/89.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/9.prim_prince_test.248042727
Short name T33
Test name
Test status
Simulation time 3315761121 ps
CPU time 59.37 seconds
Started Aug 28 06:08:30 PM UTC 24
Finished Aug 28 06:09:45 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=248042727 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 9.prim_prince_test.248042727
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/9.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/90.prim_prince_test.3758864390
Short name T100
Test name
Test status
Simulation time 2589084427 ps
CPU time 46.49 seconds
Started Aug 28 06:10:27 PM UTC 24
Finished Aug 28 06:11:26 PM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3758864390 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 90.prim_prince_test.3758864390
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/90.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/91.prim_prince_test.1987432462
Short name T84
Test name
Test status
Simulation time 1642472468 ps
CPU time 29.54 seconds
Started Aug 28 06:10:28 PM UTC 24
Finished Aug 28 06:11:06 PM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1987432462 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 91.prim_prince_test.1987432462
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/91.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/92.prim_prince_test.2525835052
Short name T94
Test name
Test status
Simulation time 2277004072 ps
CPU time 40.65 seconds
Started Aug 28 06:10:28 PM UTC 24
Finished Aug 28 06:11:19 PM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2525835052 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 92.prim_prince_test.2525835052
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/92.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/93.prim_prince_test.3091526875
Short name T107
Test name
Test status
Simulation time 2949583876 ps
CPU time 51.87 seconds
Started Aug 28 06:10:28 PM UTC 24
Finished Aug 28 06:11:34 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3091526875 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 93.prim_prince_test.3091526875
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/93.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/94.prim_prince_test.1056145034
Short name T78
Test name
Test status
Simulation time 1039931280 ps
CPU time 18.82 seconds
Started Aug 28 06:10:33 PM UTC 24
Finished Aug 28 06:10:57 PM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1056145034 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 94.prim_prince_test.1056145034
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/94.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/95.prim_prince_test.3185537416
Short name T81
Test name
Test status
Simulation time 1069394069 ps
CPU time 19.22 seconds
Started Aug 28 06:10:36 PM UTC 24
Finished Aug 28 06:11:01 PM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3185537416 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 95.prim_prince_test.3185537416
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/95.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/96.prim_prince_test.112323703
Short name T106
Test name
Test status
Simulation time 2514943173 ps
CPU time 44.69 seconds
Started Aug 28 06:10:37 PM UTC 24
Finished Aug 28 06:11:34 PM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=112323703 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 96.prim_prince_test.112323703
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/96.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/97.prim_prince_test.1954597088
Short name T104
Test name
Test status
Simulation time 2163672161 ps
CPU time 38.74 seconds
Started Aug 28 06:10:42 PM UTC 24
Finished Aug 28 06:11:31 PM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1954597088 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 97.prim_prince_test.1954597088
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/97.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/98.prim_prince_test.966528915
Short name T105
Test name
Test status
Simulation time 2081072113 ps
CPU time 37.21 seconds
Started Aug 28 06:10:45 PM UTC 24
Finished Aug 28 06:11:33 PM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=966528915 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 98.prim_prince_test.966528915
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/98.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default/99.prim_prince_test.1295321723
Short name T102
Test name
Test status
Simulation time 1964980502 ps
CPU time 34.86 seconds
Started Aug 28 06:10:45 PM UTC 24
Finished Aug 28 06:11:30 PM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1295321723 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 99.prim_prince_test.1295321723
Directory /workspaces/repo/scratch/os_regression_2024_08_28/prim_prince-sim-vcs/99.prim_prince_test/latest
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