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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00 100.00


Total test records in report: 500
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html
T251 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/247.prim_prince_test.981796155 Sep 01 04:38:46 AM UTC 24 Sep 01 04:39:56 AM UTC 24 3042910868 ps
T252 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/251.prim_prince_test.1753301257 Sep 01 04:38:51 AM UTC 24 Sep 01 04:39:56 AM UTC 24 2876508567 ps
T253 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/252.prim_prince_test.3756035483 Sep 01 04:38:53 AM UTC 24 Sep 01 04:39:59 AM UTC 24 2921456541 ps
T254 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/249.prim_prince_test.2025589102 Sep 01 04:38:50 AM UTC 24 Sep 01 04:40:02 AM UTC 24 3202049266 ps
T255 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/335.prim_prince_test.1538142603 Sep 01 04:42:49 AM UTC 24 Sep 01 04:43:43 AM UTC 24 2336826292 ps
T256 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/260.prim_prince_test.3915811488 Sep 01 04:39:34 AM UTC 24 Sep 01 04:40:06 AM UTC 24 1350347192 ps
T257 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/264.prim_prince_test.4282760885 Sep 01 04:39:40 AM UTC 24 Sep 01 04:40:07 AM UTC 24 1161838613 ps
T258 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/255.prim_prince_test.1456980254 Sep 01 04:38:58 AM UTC 24 Sep 01 04:40:07 AM UTC 24 3032756729 ps
T259 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/248.prim_prince_test.783365216 Sep 01 04:38:47 AM UTC 24 Sep 01 04:40:09 AM UTC 24 3598588951 ps
T260 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/267.prim_prince_test.1392202655 Sep 01 04:39:48 AM UTC 24 Sep 01 04:40:10 AM UTC 24 893359789 ps
T261 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/250.prim_prince_test.3430094605 Sep 01 04:38:50 AM UTC 24 Sep 01 04:40:12 AM UTC 24 3614054152 ps
T262 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/253.prim_prince_test.3672975365 Sep 01 04:38:56 AM UTC 24 Sep 01 04:40:14 AM UTC 24 3405338006 ps
T263 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/265.prim_prince_test.2939667569 Sep 01 04:39:45 AM UTC 24 Sep 01 04:40:14 AM UTC 24 1264969270 ps
T264 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/261.prim_prince_test.3419117389 Sep 01 04:39:35 AM UTC 24 Sep 01 04:40:15 AM UTC 24 1695615087 ps
T265 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/256.prim_prince_test.1880579226 Sep 01 04:38:59 AM UTC 24 Sep 01 04:40:16 AM UTC 24 3390658624 ps
T266 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/263.prim_prince_test.2280981190 Sep 01 04:39:40 AM UTC 24 Sep 01 04:40:29 AM UTC 24 2155363653 ps
T267 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/274.prim_prince_test.4007294528 Sep 01 04:40:08 AM UTC 24 Sep 01 04:40:34 AM UTC 24 1069767842 ps
T268 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/278.prim_prince_test.1109425254 Sep 01 04:40:12 AM UTC 24 Sep 01 04:40:35 AM UTC 24 956737357 ps
T269 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/275.prim_prince_test.499380240 Sep 01 04:40:08 AM UTC 24 Sep 01 04:40:36 AM UTC 24 1182029216 ps
T270 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/266.prim_prince_test.3426506161 Sep 01 04:39:47 AM UTC 24 Sep 01 04:40:36 AM UTC 24 2126685127 ps
T271 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/258.prim_prince_test.12094826 Sep 01 04:39:19 AM UTC 24 Sep 01 04:40:37 AM UTC 24 3425303294 ps
T272 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/269.prim_prince_test.119584515 Sep 01 04:39:56 AM UTC 24 Sep 01 04:40:44 AM UTC 24 2060103179 ps
T273 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/279.prim_prince_test.1619182372 Sep 01 04:40:15 AM UTC 24 Sep 01 04:40:46 AM UTC 24 1355656922 ps
T274 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/277.prim_prince_test.1545990369 Sep 01 04:40:11 AM UTC 24 Sep 01 04:40:47 AM UTC 24 1528419855 ps
T275 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/262.prim_prince_test.769104286 Sep 01 04:39:36 AM UTC 24 Sep 01 04:40:51 AM UTC 24 3270214184 ps
T276 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/276.prim_prince_test.1114775136 Sep 01 04:40:09 AM UTC 24 Sep 01 04:40:58 AM UTC 24 2121761171 ps
T277 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/273.prim_prince_test.3300068143 Sep 01 04:40:07 AM UTC 24 Sep 01 04:40:59 AM UTC 24 2243892941 ps
T278 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/272.prim_prince_test.592103592 Sep 01 04:40:04 AM UTC 24 Sep 01 04:41:01 AM UTC 24 2490387902 ps
T279 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/287.prim_prince_test.1482413419 Sep 01 04:40:38 AM UTC 24 Sep 01 04:41:02 AM UTC 24 1018128043 ps
T280 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/271.prim_prince_test.4018626308 Sep 01 04:40:01 AM UTC 24 Sep 01 04:41:04 AM UTC 24 2776978479 ps
T281 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/291.prim_prince_test.3505315099 Sep 01 04:40:47 AM UTC 24 Sep 01 04:41:07 AM UTC 24 818457275 ps
T282 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/268.prim_prince_test.4225330658 Sep 01 04:39:54 AM UTC 24 Sep 01 04:41:08 AM UTC 24 3289161866 ps
T283 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/270.prim_prince_test.4085569111 Sep 01 04:39:57 AM UTC 24 Sep 01 04:41:09 AM UTC 24 3141752769 ps
T284 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/282.prim_prince_test.3040630077 Sep 01 04:40:17 AM UTC 24 Sep 01 04:41:13 AM UTC 24 2444994065 ps
T285 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/283.prim_prince_test.2731335994 Sep 01 04:40:30 AM UTC 24 Sep 01 04:41:13 AM UTC 24 1861288712 ps
T286 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/290.prim_prince_test.63188196 Sep 01 04:40:47 AM UTC 24 Sep 01 04:41:23 AM UTC 24 1546657268 ps
T287 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/281.prim_prince_test.2661518371 Sep 01 04:40:16 AM UTC 24 Sep 01 04:41:25 AM UTC 24 3054137910 ps
T288 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/289.prim_prince_test.3869954278 Sep 01 04:40:45 AM UTC 24 Sep 01 04:41:27 AM UTC 24 1851790539 ps
T289 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/284.prim_prince_test.3433342690 Sep 01 04:40:34 AM UTC 24 Sep 01 04:41:28 AM UTC 24 2351474489 ps
T290 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/286.prim_prince_test.586846087 Sep 01 04:40:37 AM UTC 24 Sep 01 04:41:33 AM UTC 24 2438838735 ps
T291 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/280.prim_prince_test.2370202032 Sep 01 04:40:15 AM UTC 24 Sep 01 04:41:34 AM UTC 24 3535454345 ps
T292 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/293.prim_prince_test.3858530267 Sep 01 04:41:00 AM UTC 24 Sep 01 04:41:38 AM UTC 24 1666998437 ps
T293 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/294.prim_prince_test.3757122101 Sep 01 04:41:00 AM UTC 24 Sep 01 04:41:41 AM UTC 24 1777808557 ps
T294 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/288.prim_prince_test.1740870363 Sep 01 04:40:38 AM UTC 24 Sep 01 04:41:45 AM UTC 24 2950215356 ps
T295 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/285.prim_prince_test.3588929620 Sep 01 04:40:36 AM UTC 24 Sep 01 04:41:48 AM UTC 24 3169752755 ps
T296 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/296.prim_prince_test.1112291327 Sep 01 04:41:03 AM UTC 24 Sep 01 04:41:49 AM UTC 24 1994780301 ps
T297 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/295.prim_prince_test.112462044 Sep 01 04:41:02 AM UTC 24 Sep 01 04:41:54 AM UTC 24 2290663041 ps
T298 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/303.prim_prince_test.2826324109 Sep 01 04:41:24 AM UTC 24 Sep 01 04:41:55 AM UTC 24 1357998978 ps
T299 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/299.prim_prince_test.1987185975 Sep 01 04:41:09 AM UTC 24 Sep 01 04:41:58 AM UTC 24 2133379564 ps
T300 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/309.prim_prince_test.128441621 Sep 01 04:41:39 AM UTC 24 Sep 01 04:42:03 AM UTC 24 1008365125 ps
T301 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/302.prim_prince_test.3664728383 Sep 01 04:41:15 AM UTC 24 Sep 01 04:42:03 AM UTC 24 2121600555 ps
T302 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/304.prim_prince_test.2685930104 Sep 01 04:41:26 AM UTC 24 Sep 01 04:42:03 AM UTC 24 1615650677 ps
T303 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/298.prim_prince_test.2272576663 Sep 01 04:41:07 AM UTC 24 Sep 01 04:42:05 AM UTC 24 2565506482 ps
T304 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/297.prim_prince_test.643122959 Sep 01 04:41:05 AM UTC 24 Sep 01 04:42:06 AM UTC 24 2672125000 ps
T305 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/305.prim_prince_test.3820589079 Sep 01 04:41:28 AM UTC 24 Sep 01 04:42:07 AM UTC 24 1687909292 ps
T306 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/292.prim_prince_test.4004977890 Sep 01 04:40:51 AM UTC 24 Sep 01 04:42:10 AM UTC 24 3484560256 ps
T307 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/310.prim_prince_test.254337524 Sep 01 04:41:42 AM UTC 24 Sep 01 04:42:16 AM UTC 24 1474509635 ps
T308 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/300.prim_prince_test.922083692 Sep 01 04:41:09 AM UTC 24 Sep 01 04:42:21 AM UTC 24 3170468451 ps
T309 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/315.prim_prince_test.2511409065 Sep 01 04:41:57 AM UTC 24 Sep 01 04:42:29 AM UTC 24 1400732016 ps
T310 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/319.prim_prince_test.474176857 Sep 01 04:42:04 AM UTC 24 Sep 01 04:42:30 AM UTC 24 1111501211 ps
T311 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/308.prim_prince_test.3464142673 Sep 01 04:41:35 AM UTC 24 Sep 01 04:42:35 AM UTC 24 2628042030 ps
T312 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/301.prim_prince_test.2971175282 Sep 01 04:41:14 AM UTC 24 Sep 01 04:42:36 AM UTC 24 3600655295 ps
T313 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/312.prim_prince_test.1730398372 Sep 01 04:41:49 AM UTC 24 Sep 01 04:42:38 AM UTC 24 2124819851 ps
T314 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/311.prim_prince_test.1194453702 Sep 01 04:41:46 AM UTC 24 Sep 01 04:42:39 AM UTC 24 2299238275 ps
T315 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/307.prim_prince_test.1608731405 Sep 01 04:41:33 AM UTC 24 Sep 01 04:42:42 AM UTC 24 3023964878 ps
T316 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/306.prim_prince_test.2809579463 Sep 01 04:41:29 AM UTC 24 Sep 01 04:42:45 AM UTC 24 3364883178 ps
T317 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/313.prim_prince_test.3165213760 Sep 01 04:41:50 AM UTC 24 Sep 01 04:42:47 AM UTC 24 2529344835 ps
T318 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/325.prim_prince_test.722104667 Sep 01 04:42:22 AM UTC 24 Sep 01 04:42:49 AM UTC 24 1131517759 ps
T319 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/316.prim_prince_test.1483972774 Sep 01 04:41:59 AM UTC 24 Sep 01 04:42:55 AM UTC 24 2476028451 ps
T320 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/326.prim_prince_test.2120276205 Sep 01 04:42:29 AM UTC 24 Sep 01 04:42:59 AM UTC 24 1264767515 ps
T321 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/328.prim_prince_test.2319725940 Sep 01 04:42:36 AM UTC 24 Sep 01 04:43:05 AM UTC 24 1213197666 ps
T322 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/321.prim_prince_test.2786001366 Sep 01 04:42:07 AM UTC 24 Sep 01 04:43:05 AM UTC 24 2564589165 ps
T323 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/318.prim_prince_test.3791536272 Sep 01 04:42:04 AM UTC 24 Sep 01 04:43:12 AM UTC 24 3022063779 ps
T324 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/323.prim_prince_test.2049061222 Sep 01 04:42:11 AM UTC 24 Sep 01 04:43:13 AM UTC 24 2738088449 ps
T325 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/332.prim_prince_test.2001364792 Sep 01 04:42:43 AM UTC 24 Sep 01 04:43:15 AM UTC 24 1360708882 ps
T326 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/320.prim_prince_test.3991106676 Sep 01 04:42:06 AM UTC 24 Sep 01 04:43:15 AM UTC 24 3052772008 ps
T327 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/336.prim_prince_test.1694276783 Sep 01 04:42:56 AM UTC 24 Sep 01 04:43:16 AM UTC 24 817910095 ps
T328 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/330.prim_prince_test.799705187 Sep 01 04:42:39 AM UTC 24 Sep 01 04:43:16 AM UTC 24 1606081731 ps
T329 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/314.prim_prince_test.2770531978 Sep 01 04:41:54 AM UTC 24 Sep 01 04:43:18 AM UTC 24 3651905052 ps
T330 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/322.prim_prince_test.2047790084 Sep 01 04:42:07 AM UTC 24 Sep 01 04:43:18 AM UTC 24 3120388483 ps
T331 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/324.prim_prince_test.1650754580 Sep 01 04:42:17 AM UTC 24 Sep 01 04:43:19 AM UTC 24 2728157161 ps
T332 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/317.prim_prince_test.2793814756 Sep 01 04:42:04 AM UTC 24 Sep 01 04:43:23 AM UTC 24 3510842062 ps
T333 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/329.prim_prince_test.4123425758 Sep 01 04:42:38 AM UTC 24 Sep 01 04:43:26 AM UTC 24 2120089101 ps
T334 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/338.prim_prince_test.2544147934 Sep 01 04:43:06 AM UTC 24 Sep 01 04:43:29 AM UTC 24 941599236 ps
T335 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/327.prim_prince_test.401780309 Sep 01 04:42:31 AM UTC 24 Sep 01 04:43:43 AM UTC 24 3153269142 ps
T336 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/341.prim_prince_test.3666186860 Sep 01 04:43:14 AM UTC 24 Sep 01 04:43:44 AM UTC 24 1225245090 ps
T337 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/331.prim_prince_test.896088613 Sep 01 04:42:40 AM UTC 24 Sep 01 04:43:45 AM UTC 24 2843715902 ps
T338 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/339.prim_prince_test.3621763346 Sep 01 04:43:06 AM UTC 24 Sep 01 04:43:48 AM UTC 24 1794949428 ps
T339 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/344.prim_prince_test.3586536848 Sep 01 04:43:17 AM UTC 24 Sep 01 04:43:48 AM UTC 24 1342551800 ps
T340 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/343.prim_prince_test.4035459854 Sep 01 04:43:17 AM UTC 24 Sep 01 04:43:57 AM UTC 24 1729785515 ps
T341 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/347.prim_prince_test.2566430240 Sep 01 04:43:19 AM UTC 24 Sep 01 04:43:59 AM UTC 24 1740043415 ps
T342 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/348.prim_prince_test.3732960158 Sep 01 04:43:20 AM UTC 24 Sep 01 04:44:00 AM UTC 24 1744089998 ps
T343 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/334.prim_prince_test.3304867804 Sep 01 04:42:48 AM UTC 24 Sep 01 04:44:03 AM UTC 24 3320010195 ps
T344 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/351.prim_prince_test.3109620378 Sep 01 04:43:30 AM UTC 24 Sep 01 04:44:04 AM UTC 24 1499387266 ps
T345 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/342.prim_prince_test.3480389723 Sep 01 04:43:16 AM UTC 24 Sep 01 04:44:08 AM UTC 24 2241701472 ps
T346 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/337.prim_prince_test.1445491898 Sep 01 04:43:00 AM UTC 24 Sep 01 04:44:10 AM UTC 24 3031794433 ps
T347 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/333.prim_prince_test.1441961670 Sep 01 04:42:46 AM UTC 24 Sep 01 04:44:10 AM UTC 24 3693922089 ps
T348 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/352.prim_prince_test.3106928472 Sep 01 04:43:43 AM UTC 24 Sep 01 04:44:11 AM UTC 24 1178501429 ps
T349 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/349.prim_prince_test.2478933141 Sep 01 04:43:25 AM UTC 24 Sep 01 04:44:21 AM UTC 24 2437707997 ps
T350 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/346.prim_prince_test.1716871755 Sep 01 04:43:19 AM UTC 24 Sep 01 04:44:24 AM UTC 24 2824396958 ps
T351 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/359.prim_prince_test.3192159039 Sep 01 04:44:00 AM UTC 24 Sep 01 04:44:27 AM UTC 24 1150173739 ps
T352 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/356.prim_prince_test.2402381384 Sep 01 04:43:49 AM UTC 24 Sep 01 04:44:29 AM UTC 24 1757089528 ps
T353 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/340.prim_prince_test.2590314668 Sep 01 04:43:13 AM UTC 24 Sep 01 04:44:30 AM UTC 24 3393368842 ps
T354 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/350.prim_prince_test.352156885 Sep 01 04:43:27 AM UTC 24 Sep 01 04:44:30 AM UTC 24 2794737457 ps
T355 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/345.prim_prince_test.2212017891 Sep 01 04:43:17 AM UTC 24 Sep 01 04:44:34 AM UTC 24 3425431534 ps
T356 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/358.prim_prince_test.2670379347 Sep 01 04:43:57 AM UTC 24 Sep 01 04:44:37 AM UTC 24 1728562289 ps
T357 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/360.prim_prince_test.1400205451 Sep 01 04:44:01 AM UTC 24 Sep 01 04:44:40 AM UTC 24 1633824030 ps
T358 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/354.prim_prince_test.556090505 Sep 01 04:43:44 AM UTC 24 Sep 01 04:44:41 AM UTC 24 2452745217 ps
T359 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/370.prim_prince_test.1759088405 Sep 01 04:44:30 AM UTC 24 Sep 01 04:44:48 AM UTC 24 762248713 ps
T360 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/368.prim_prince_test.1662490238 Sep 01 04:44:24 AM UTC 24 Sep 01 04:44:51 AM UTC 24 1127702940 ps
T361 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/357.prim_prince_test.942623 Sep 01 04:43:50 AM UTC 24 Sep 01 04:44:52 AM UTC 24 2710249711 ps
T362 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/355.prim_prince_test.971522870 Sep 01 04:43:46 AM UTC 24 Sep 01 04:44:55 AM UTC 24 3026984103 ps
T363 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/361.prim_prince_test.3724023780 Sep 01 04:44:04 AM UTC 24 Sep 01 04:44:55 AM UTC 24 2205920019 ps
T364 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/353.prim_prince_test.2226768049 Sep 01 04:43:44 AM UTC 24 Sep 01 04:44:59 AM UTC 24 3267868865 ps
T365 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/371.prim_prince_test.4221950296 Sep 01 04:44:31 AM UTC 24 Sep 01 04:45:01 AM UTC 24 1273803684 ps
T366 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/362.prim_prince_test.2580024741 Sep 01 04:44:06 AM UTC 24 Sep 01 04:45:03 AM UTC 24 2508906677 ps
T367 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/369.prim_prince_test.2262590000 Sep 01 04:44:29 AM UTC 24 Sep 01 04:45:08 AM UTC 24 1669924558 ps
T368 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/367.prim_prince_test.905295727 Sep 01 04:44:21 AM UTC 24 Sep 01 04:45:17 AM UTC 24 2444135575 ps
T369 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/365.prim_prince_test.781031340 Sep 01 04:44:11 AM UTC 24 Sep 01 04:45:21 AM UTC 24 3067314496 ps
T370 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/363.prim_prince_test.3765852229 Sep 01 04:44:09 AM UTC 24 Sep 01 04:45:22 AM UTC 24 3233758335 ps
T371 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/375.prim_prince_test.552596390 Sep 01 04:44:41 AM UTC 24 Sep 01 04:45:23 AM UTC 24 1813465679 ps
T372 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/412.prim_prince_test.34263733 Sep 01 04:46:18 AM UTC 24 Sep 01 04:47:35 AM UTC 24 3388633327 ps
T373 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/373.prim_prince_test.1239590873 Sep 01 04:44:34 AM UTC 24 Sep 01 04:45:26 AM UTC 24 2207061536 ps
T374 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/376.prim_prince_test.661750352 Sep 01 04:44:42 AM UTC 24 Sep 01 04:45:30 AM UTC 24 2061370908 ps
T375 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/364.prim_prince_test.1669439026 Sep 01 04:44:11 AM UTC 24 Sep 01 04:45:32 AM UTC 24 3560416879 ps
T376 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/366.prim_prince_test.3203395389 Sep 01 04:44:12 AM UTC 24 Sep 01 04:45:34 AM UTC 24 3600848447 ps
T377 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/379.prim_prince_test.3435159842 Sep 01 04:44:53 AM UTC 24 Sep 01 04:45:35 AM UTC 24 1777465349 ps
T378 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/380.prim_prince_test.4235905413 Sep 01 04:44:56 AM UTC 24 Sep 01 04:45:39 AM UTC 24 1880664729 ps
T379 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/381.prim_prince_test.3964696495 Sep 01 04:44:56 AM UTC 24 Sep 01 04:45:44 AM UTC 24 2098505844 ps
T380 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/383.prim_prince_test.2215243108 Sep 01 04:45:02 AM UTC 24 Sep 01 04:45:47 AM UTC 24 1929507265 ps
T381 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/389.prim_prince_test.3374280541 Sep 01 04:45:24 AM UTC 24 Sep 01 04:45:52 AM UTC 24 1209715109 ps
T382 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/387.prim_prince_test.2483412349 Sep 01 04:45:22 AM UTC 24 Sep 01 04:45:54 AM UTC 24 1419050341 ps
T383 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/372.prim_prince_test.2063086524 Sep 01 04:44:31 AM UTC 24 Sep 01 04:45:55 AM UTC 24 3731916324 ps
T384 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/385.prim_prince_test.3720378197 Sep 01 04:45:08 AM UTC 24 Sep 01 04:45:57 AM UTC 24 2132092060 ps
T385 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/374.prim_prince_test.2091605106 Sep 01 04:44:37 AM UTC 24 Sep 01 04:45:58 AM UTC 24 3570476788 ps
T386 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/377.prim_prince_test.2002616505 Sep 01 04:44:49 AM UTC 24 Sep 01 04:45:59 AM UTC 24 3064755367 ps
T387 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/391.prim_prince_test.3962938515 Sep 01 04:45:30 AM UTC 24 Sep 01 04:46:00 AM UTC 24 1265334429 ps
T388 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/378.prim_prince_test.3297615404 Sep 01 04:44:52 AM UTC 24 Sep 01 04:46:00 AM UTC 24 2991196682 ps
T389 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/392.prim_prince_test.3466143044 Sep 01 04:45:32 AM UTC 24 Sep 01 04:46:12 AM UTC 24 1715295376 ps
T390 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/396.prim_prince_test.2659798670 Sep 01 04:45:45 AM UTC 24 Sep 01 04:46:12 AM UTC 24 1153375169 ps
T391 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/393.prim_prince_test.1757101717 Sep 01 04:45:34 AM UTC 24 Sep 01 04:46:12 AM UTC 24 1631990304 ps
T392 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/395.prim_prince_test.2843174855 Sep 01 04:45:40 AM UTC 24 Sep 01 04:46:15 AM UTC 24 1521837746 ps
T393 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/398.prim_prince_test.1020965074 Sep 01 04:45:53 AM UTC 24 Sep 01 04:46:15 AM UTC 24 924692154 ps
T394 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/394.prim_prince_test.2688035561 Sep 01 04:45:36 AM UTC 24 Sep 01 04:46:17 AM UTC 24 1785592461 ps
T395 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/382.prim_prince_test.1733343827 Sep 01 04:45:00 AM UTC 24 Sep 01 04:46:17 AM UTC 24 3422537727 ps
T396 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/384.prim_prince_test.2511297656 Sep 01 04:45:04 AM UTC 24 Sep 01 04:46:24 AM UTC 24 3502733841 ps
T397 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/403.prim_prince_test.1068075623 Sep 01 04:46:00 AM UTC 24 Sep 01 04:46:31 AM UTC 24 1314331778 ps
T398 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/402.prim_prince_test.762165532 Sep 01 04:45:59 AM UTC 24 Sep 01 04:46:33 AM UTC 24 1450069278 ps
T399 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/390.prim_prince_test.2217651472 Sep 01 04:45:27 AM UTC 24 Sep 01 04:46:34 AM UTC 24 2953385856 ps
T400 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/388.prim_prince_test.3458627979 Sep 01 04:45:23 AM UTC 24 Sep 01 04:46:35 AM UTC 24 3195564933 ps
T401 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/386.prim_prince_test.3302545661 Sep 01 04:45:18 AM UTC 24 Sep 01 04:46:37 AM UTC 24 3491215048 ps
T402 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/397.prim_prince_test.3500695947 Sep 01 04:45:48 AM UTC 24 Sep 01 04:46:41 AM UTC 24 2300461037 ps
T403 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/408.prim_prince_test.719899732 Sep 01 04:46:14 AM UTC 24 Sep 01 04:46:41 AM UTC 24 1170233119 ps
T404 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/399.prim_prince_test.3232730596 Sep 01 04:45:56 AM UTC 24 Sep 01 04:46:47 AM UTC 24 2252201459 ps
T405 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/404.prim_prince_test.3190831352 Sep 01 04:46:00 AM UTC 24 Sep 01 04:46:51 AM UTC 24 2221623565 ps
T406 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/407.prim_prince_test.1624563194 Sep 01 04:46:13 AM UTC 24 Sep 01 04:46:56 AM UTC 24 1901177127 ps
T407 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/420.prim_prince_test.3599151587 Sep 01 04:46:42 AM UTC 24 Sep 01 04:47:06 AM UTC 24 1017953059 ps
T408 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/421.prim_prince_test.4002182089 Sep 01 04:46:48 AM UTC 24 Sep 01 04:47:11 AM UTC 24 934745276 ps
T409 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/416.prim_prince_test.1255506064 Sep 01 04:46:35 AM UTC 24 Sep 01 04:47:14 AM UTC 24 1651441537 ps
T410 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/405.prim_prince_test.2141030707 Sep 01 04:46:01 AM UTC 24 Sep 01 04:47:15 AM UTC 24 3247298565 ps
T411 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/413.prim_prince_test.1597745226 Sep 01 04:46:25 AM UTC 24 Sep 01 04:47:15 AM UTC 24 2198290654 ps
T412 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/400.prim_prince_test.837788570 Sep 01 04:45:57 AM UTC 24 Sep 01 04:47:17 AM UTC 24 3498043155 ps
T413 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/419.prim_prince_test.3710476659 Sep 01 04:46:42 AM UTC 24 Sep 01 04:47:33 AM UTC 24 2217024739 ps
T414 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/415.prim_prince_test.3424318635 Sep 01 04:46:34 AM UTC 24 Sep 01 04:47:17 AM UTC 24 1830519348 ps
T415 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/401.prim_prince_test.467252497 Sep 01 04:45:58 AM UTC 24 Sep 01 04:47:19 AM UTC 24 3569774901 ps
T416 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/406.prim_prince_test.1340699115 Sep 01 04:46:13 AM UTC 24 Sep 01 04:47:23 AM UTC 24 3101251039 ps
T417 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/418.prim_prince_test.2711661224 Sep 01 04:46:38 AM UTC 24 Sep 01 04:47:24 AM UTC 24 2056943329 ps
T418 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/422.prim_prince_test.3919869300 Sep 01 04:46:52 AM UTC 24 Sep 01 04:47:28 AM UTC 24 1517907003 ps
T419 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/423.prim_prince_test.3965992061 Sep 01 04:46:58 AM UTC 24 Sep 01 04:47:29 AM UTC 24 1364911892 ps
T420 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/414.prim_prince_test.700040484 Sep 01 04:46:32 AM UTC 24 Sep 01 04:47:31 AM UTC 24 2591995159 ps
T421 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/410.prim_prince_test.1292920874 Sep 01 04:46:16 AM UTC 24 Sep 01 04:47:37 AM UTC 24 3572741413 ps
T422 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/409.prim_prince_test.1133236413 Sep 01 04:46:16 AM UTC 24 Sep 01 04:47:38 AM UTC 24 3610660362 ps
T423 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/411.prim_prince_test.2728937548 Sep 01 04:46:18 AM UTC 24 Sep 01 04:47:38 AM UTC 24 3591430876 ps
T424 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/429.prim_prince_test.30204405 Sep 01 04:47:18 AM UTC 24 Sep 01 04:47:40 AM UTC 24 914020670 ps
T425 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/417.prim_prince_test.1855215276 Sep 01 04:46:37 AM UTC 24 Sep 01 04:47:48 AM UTC 24 3155147152 ps
T426 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/431.prim_prince_test.2055761270 Sep 01 04:47:20 AM UTC 24 Sep 01 04:47:55 AM UTC 24 1499295755 ps
T427 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/432.prim_prince_test.3995176892 Sep 01 04:47:24 AM UTC 24 Sep 01 04:47:58 AM UTC 24 1464238720 ps
T428 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/430.prim_prince_test.3766787972 Sep 01 04:47:18 AM UTC 24 Sep 01 04:48:02 AM UTC 24 1914724595 ps
T429 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/436.prim_prince_test.74384931 Sep 01 04:47:32 AM UTC 24 Sep 01 04:48:05 AM UTC 24 1435881217 ps
T430 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/441.prim_prince_test.1957393899 Sep 01 04:47:40 AM UTC 24 Sep 01 04:48:09 AM UTC 24 1258131726 ps
T431 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/425.prim_prince_test.2980562439 Sep 01 04:47:12 AM UTC 24 Sep 01 04:48:12 AM UTC 24 2640846791 ps
T432 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/424.prim_prince_test.761714225 Sep 01 04:47:07 AM UTC 24 Sep 01 04:48:14 AM UTC 24 2944643719 ps
T433 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/440.prim_prince_test.3447349051 Sep 01 04:47:40 AM UTC 24 Sep 01 04:48:20 AM UTC 24 1761213004 ps
T434 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/427.prim_prince_test.2432783292 Sep 01 04:47:15 AM UTC 24 Sep 01 04:48:22 AM UTC 24 2907400024 ps
T435 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/434.prim_prince_test.70797075 Sep 01 04:47:28 AM UTC 24 Sep 01 04:48:23 AM UTC 24 2370642135 ps
T436 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/428.prim_prince_test.77761185 Sep 01 04:47:15 AM UTC 24 Sep 01 04:48:23 AM UTC 24 2967579612 ps
T437 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/426.prim_prince_test.2571390331 Sep 01 04:47:14 AM UTC 24 Sep 01 04:48:23 AM UTC 24 3038636945 ps
T438 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/439.prim_prince_test.2754270818 Sep 01 04:47:38 AM UTC 24 Sep 01 04:48:27 AM UTC 24 2120451229 ps
T439 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/433.prim_prince_test.1190031808 Sep 01 04:47:25 AM UTC 24 Sep 01 04:48:38 AM UTC 24 3209112345 ps
T440 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/445.prim_prince_test.1606497689 Sep 01 04:47:58 AM UTC 24 Sep 01 04:48:41 AM UTC 24 1819211427 ps
T441 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/438.prim_prince_test.789696007 Sep 01 04:47:36 AM UTC 24 Sep 01 04:48:49 AM UTC 24 3201262395 ps
T442 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/451.prim_prince_test.3366309544 Sep 01 04:48:22 AM UTC 24 Sep 01 04:48:50 AM UTC 24 1199004612 ps
T443 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/437.prim_prince_test.2807309730 Sep 01 04:47:33 AM UTC 24 Sep 01 04:48:50 AM UTC 24 3422500176 ps
T444 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/452.prim_prince_test.210159126 Sep 01 04:48:23 AM UTC 24 Sep 01 04:48:50 AM UTC 24 1154305135 ps
T445 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/435.prim_prince_test.909656683 Sep 01 04:47:30 AM UTC 24 Sep 01 04:48:53 AM UTC 24 3690020061 ps
T446 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/454.prim_prince_test.860253141 Sep 01 04:48:24 AM UTC 24 Sep 01 04:48:54 AM UTC 24 1271146207 ps
T447 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/442.prim_prince_test.1329996362 Sep 01 04:47:41 AM UTC 24 Sep 01 04:48:55 AM UTC 24 3266347086 ps
T448 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/444.prim_prince_test.2876108161 Sep 01 04:47:55 AM UTC 24 Sep 01 04:48:55 AM UTC 24 2638118468 ps
T449 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/448.prim_prince_test.2978745276 Sep 01 04:48:10 AM UTC 24 Sep 01 04:48:57 AM UTC 24 2084947178 ps
T450 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/455.prim_prince_test.953531947 Sep 01 04:48:24 AM UTC 24 Sep 01 04:49:00 AM UTC 24 1566499353 ps
T451 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/446.prim_prince_test.3512753007 Sep 01 04:48:03 AM UTC 24 Sep 01 04:49:08 AM UTC 24 2866637215 ps
T452 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/443.prim_prince_test.3513050132 Sep 01 04:47:49 AM UTC 24 Sep 01 04:49:10 AM UTC 24 3557687896 ps
T453 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/449.prim_prince_test.1942649501 Sep 01 04:48:13 AM UTC 24 Sep 01 04:49:16 AM UTC 24 2755426599 ps
T454 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/467.prim_prince_test.281247277 Sep 01 04:48:58 AM UTC 24 Sep 01 04:49:20 AM UTC 24 908713340 ps
T455 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/450.prim_prince_test.834804181 Sep 01 04:48:14 AM UTC 24 Sep 01 04:49:22 AM UTC 24 3004822469 ps
T456 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/447.prim_prince_test.1676367719 Sep 01 04:48:06 AM UTC 24 Sep 01 04:49:30 AM UTC 24 3721576798 ps
T457 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/459.prim_prince_test.1163614432 Sep 01 04:48:50 AM UTC 24 Sep 01 04:49:31 AM UTC 24 1803378470 ps
T458 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/470.prim_prince_test.4258270223 Sep 01 04:49:11 AM UTC 24 Sep 01 04:49:33 AM UTC 24 917236846 ps
T459 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/456.prim_prince_test.2790508052 Sep 01 04:48:27 AM UTC 24 Sep 01 04:49:33 AM UTC 24 2913810999 ps
T460 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/453.prim_prince_test.774351777 Sep 01 04:48:24 AM UTC 24 Sep 01 04:49:39 AM UTC 24 3322434802 ps
T461 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/460.prim_prince_test.2854353538 Sep 01 04:48:50 AM UTC 24 Sep 01 04:49:40 AM UTC 24 2164518637 ps
T462 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/458.prim_prince_test.3076330735 Sep 01 04:48:42 AM UTC 24 Sep 01 04:49:41 AM UTC 24 2605003427 ps
T463 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/457.prim_prince_test.2101755454 Sep 01 04:48:39 AM UTC 24 Sep 01 04:49:48 AM UTC 24 3099115552 ps
T464 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/461.prim_prince_test.3223631092 Sep 01 04:48:51 AM UTC 24 Sep 01 04:49:50 AM UTC 24 2585946715 ps
T465 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/462.prim_prince_test.3765017402 Sep 01 04:48:51 AM UTC 24 Sep 01 04:49:51 AM UTC 24 2620236886 ps
T466 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/463.prim_prince_test.425646170 Sep 01 04:48:54 AM UTC 24 Sep 01 04:49:57 AM UTC 24 2768139834 ps
T467 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/469.prim_prince_test.1840736452 Sep 01 04:49:09 AM UTC 24 Sep 01 04:49:57 AM UTC 24 2088313846 ps
T468 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/465.prim_prince_test.194937624 Sep 01 04:48:56 AM UTC 24 Sep 01 04:49:57 AM UTC 24 2671104107 ps
T469 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/479.prim_prince_test.2798194781 Sep 01 04:49:41 AM UTC 24 Sep 01 04:50:03 AM UTC 24 932061282 ps
T470 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/466.prim_prince_test.1317375249 Sep 01 04:48:56 AM UTC 24 Sep 01 04:50:04 AM UTC 24 2985904525 ps
T471 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/464.prim_prince_test.1704661078 Sep 01 04:48:55 AM UTC 24 Sep 01 04:50:08 AM UTC 24 3222493976 ps
T472 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/480.prim_prince_test.4133004024 Sep 01 04:49:42 AM UTC 24 Sep 01 04:50:08 AM UTC 24 1108212555 ps
T473 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/475.prim_prince_test.933029566 Sep 01 04:49:32 AM UTC 24 Sep 01 04:50:09 AM UTC 24 1582323268 ps
T474 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/473.prim_prince_test.1286510195 Sep 01 04:49:24 AM UTC 24 Sep 01 04:50:13 AM UTC 24 2122990576 ps
T475 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/468.prim_prince_test.1419197406 Sep 01 04:49:01 AM UTC 24 Sep 01 04:50:15 AM UTC 24 3279413851 ps
T476 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/472.prim_prince_test.581076728 Sep 01 04:49:21 AM UTC 24 Sep 01 04:50:29 AM UTC 24 2947821207 ps
T477 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/471.prim_prince_test.3053285393 Sep 01 04:49:17 AM UTC 24 Sep 01 04:50:33 AM UTC 24 3350105620 ps
T478 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/481.prim_prince_test.3518328533 Sep 01 04:49:49 AM UTC 24 Sep 01 04:50:33 AM UTC 24 1916882998 ps
T479 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/484.prim_prince_test.1995093102 Sep 01 04:49:58 AM UTC 24 Sep 01 04:50:35 AM UTC 24 1517462356 ps
T480 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/478.prim_prince_test.717209690 Sep 01 04:49:40 AM UTC 24 Sep 01 04:50:38 AM UTC 24 2521602769 ps
T481 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/474.prim_prince_test.2951760957 Sep 01 04:49:31 AM UTC 24 Sep 01 04:50:42 AM UTC 24 3103593679 ps
T482 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/488.prim_prince_test.1298141831 Sep 01 04:50:07 AM UTC 24 Sep 01 04:50:43 AM UTC 24 1547071300 ps
T483 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/483.prim_prince_test.2149884049 Sep 01 04:49:51 AM UTC 24 Sep 01 04:50:47 AM UTC 24 2448784555 ps
T484 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/490.prim_prince_test.80676967 Sep 01 04:50:09 AM UTC 24 Sep 01 04:50:47 AM UTC 24 1662322786 ps
T485 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/477.prim_prince_test.2676169297 Sep 01 04:49:34 AM UTC 24 Sep 01 04:50:54 AM UTC 24 3491198296 ps
T486 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/476.prim_prince_test.5247733 Sep 01 04:49:34 AM UTC 24 Sep 01 04:50:59 AM UTC 24 3730609055 ps
T487 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/486.prim_prince_test.2043721731 Sep 01 04:49:58 AM UTC 24 Sep 01 04:50:59 AM UTC 24 2684810025 ps
T488 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/487.prim_prince_test.1013763911 Sep 01 04:50:04 AM UTC 24 Sep 01 04:51:05 AM UTC 24 2654852750 ps
T489 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/498.prim_prince_test.618092161 Sep 01 04:50:35 AM UTC 24 Sep 01 04:51:07 AM UTC 24 1375321247 ps
T490 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/495.prim_prince_test.240920243 Sep 01 04:50:32 AM UTC 24 Sep 01 04:51:09 AM UTC 24 1610561551 ps
T491 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/482.prim_prince_test.1610559335 Sep 01 04:49:51 AM UTC 24 Sep 01 04:51:10 AM UTC 24 3477685720 ps
T492 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/492.prim_prince_test.533700506 Sep 01 04:50:13 AM UTC 24 Sep 01 04:51:14 AM UTC 24 2700465193 ps
T493 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/493.prim_prince_test.155780061 Sep 01 04:50:16 AM UTC 24 Sep 01 04:51:15 AM UTC 24 2670903910 ps
T494 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/485.prim_prince_test.1893251368 Sep 01 04:49:58 AM UTC 24 Sep 01 04:51:18 AM UTC 24 3500964992 ps
T495 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/491.prim_prince_test.2793593855 Sep 01 04:50:11 AM UTC 24 Sep 01 04:51:29 AM UTC 24 3405491430 ps
T496 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/489.prim_prince_test.3032799782 Sep 01 04:50:09 AM UTC 24 Sep 01 04:51:33 AM UTC 24 3683015628 ps
T497 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/499.prim_prince_test.1889484631 Sep 01 04:50:39 AM UTC 24 Sep 01 04:51:41 AM UTC 24 2795341247 ps
T498 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/497.prim_prince_test.232994767 Sep 01 04:50:34 AM UTC 24 Sep 01 04:51:41 AM UTC 24 3014926543 ps
T499 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/494.prim_prince_test.726850183 Sep 01 04:50:31 AM UTC 24 Sep 01 04:51:45 AM UTC 24 3344010963 ps
T500 /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/496.prim_prince_test.3030894005 Sep 01 04:50:34 AM UTC 24 Sep 01 04:51:55 AM UTC 24 3565343965 ps

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/10.prim_prince_test.15464589
Short name T7
Test name
Test status
Simulation time 2284502733 ps
CPU time 41.16 seconds
Started Sep 01 04:27:54 AM UTC 24
Finished Sep 01 04:28:47 AM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15464589 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 10.prim_prince_test.15464589
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/10.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/0.prim_prince_test.669128236
Short name T18
Test name
Test status
Simulation time 3443986153 ps
CPU time 61.23 seconds
Started Sep 01 04:27:53 AM UTC 24
Finished Sep 01 04:29:11 AM UTC 24
Peak memory 154420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=669128236 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 0.prim_prince_test.669128236
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/0.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/1.prim_prince_test.4284781220
Short name T12
Test name
Test status
Simulation time 2774654769 ps
CPU time 49.32 seconds
Started Sep 01 04:27:53 AM UTC 24
Finished Sep 01 04:28:56 AM UTC 24
Peak memory 154644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4284781220 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 1.prim_prince_test.4284781220
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/1.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/100.prim_prince_test.2459083507
Short name T102
Test name
Test status
Simulation time 2307708664 ps
CPU time 40.95 seconds
Started Sep 01 04:32:06 AM UTC 24
Finished Sep 01 04:32:59 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2459083507 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 100.prim_prince_test.2459083507
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/100.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/101.prim_prince_test.186042898
Short name T95
Test name
Test status
Simulation time 1389354005 ps
CPU time 24.43 seconds
Started Sep 01 04:32:07 AM UTC 24
Finished Sep 01 04:32:39 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=186042898 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 101.prim_prince_test.186042898
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/101.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/102.prim_prince_test.3109586797
Short name T97
Test name
Test status
Simulation time 1847434449 ps
CPU time 32.41 seconds
Started Sep 01 04:32:08 AM UTC 24
Finished Sep 01 04:32:51 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3109586797 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 102.prim_prince_test.3109586797
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/102.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/103.prim_prince_test.1889688884
Short name T99
Test name
Test status
Simulation time 1744016747 ps
CPU time 31.46 seconds
Started Sep 01 04:32:12 AM UTC 24
Finished Sep 01 04:32:53 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1889688884 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 103.prim_prince_test.1889688884
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/103.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/104.prim_prince_test.3794913355
Short name T100
Test name
Test status
Simulation time 1883596637 ps
CPU time 33.55 seconds
Started Sep 01 04:32:13 AM UTC 24
Finished Sep 01 04:32:57 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3794913355 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 104.prim_prince_test.3794913355
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/104.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/105.prim_prince_test.1614363333
Short name T101
Test name
Test status
Simulation time 1896746064 ps
CPU time 33.95 seconds
Started Sep 01 04:32:14 AM UTC 24
Finished Sep 01 04:32:58 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1614363333 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 105.prim_prince_test.1614363333
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/105.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/106.prim_prince_test.3333136398
Short name T109
Test name
Test status
Simulation time 2803276326 ps
CPU time 49.19 seconds
Started Sep 01 04:32:14 AM UTC 24
Finished Sep 01 04:33:18 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3333136398 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 106.prim_prince_test.3333136398
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/106.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/107.prim_prince_test.108380577
Short name T114
Test name
Test status
Simulation time 3231254898 ps
CPU time 56.78 seconds
Started Sep 01 04:32:22 AM UTC 24
Finished Sep 01 04:33:36 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=108380577 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 107.prim_prince_test.108380577
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/107.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/108.prim_prince_test.2233908883
Short name T112
Test name
Test status
Simulation time 2960997869 ps
CPU time 52.2 seconds
Started Sep 01 04:32:25 AM UTC 24
Finished Sep 01 04:33:32 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2233908883 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 108.prim_prince_test.2233908883
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/108.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/109.prim_prince_test.117158739
Short name T96
Test name
Test status
Simulation time 796020473 ps
CPU time 14.38 seconds
Started Sep 01 04:32:27 AM UTC 24
Finished Sep 01 04:32:46 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=117158739 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 109.prim_prince_test.117158739
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/109.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/11.prim_prince_test.55621864
Short name T14
Test name
Test status
Simulation time 2885134949 ps
CPU time 52.43 seconds
Started Sep 01 04:27:54 AM UTC 24
Finished Sep 01 04:29:01 AM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=55621864 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 11.prim_prince_test.55621864
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/11.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/110.prim_prince_test.1156109549
Short name T110
Test name
Test status
Simulation time 2434740000 ps
CPU time 42.9 seconds
Started Sep 01 04:32:28 AM UTC 24
Finished Sep 01 04:33:23 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1156109549 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 110.prim_prince_test.1156109549
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/110.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/111.prim_prince_test.1459594365
Short name T113
Test name
Test status
Simulation time 2719166709 ps
CPU time 47.46 seconds
Started Sep 01 04:32:31 AM UTC 24
Finished Sep 01 04:33:32 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1459594365 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 111.prim_prince_test.1459594365
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/111.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/112.prim_prince_test.2542369185
Short name T123
Test name
Test status
Simulation time 3093273487 ps
CPU time 54.44 seconds
Started Sep 01 04:32:40 AM UTC 24
Finished Sep 01 04:33:50 AM UTC 24
Peak memory 154652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2542369185 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 112.prim_prince_test.2542369185
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/112.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/113.prim_prince_test.3643135938
Short name T115
Test name
Test status
Simulation time 2508817398 ps
CPU time 44.38 seconds
Started Sep 01 04:32:40 AM UTC 24
Finished Sep 01 04:33:37 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3643135938 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 113.prim_prince_test.3643135938
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/113.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/114.prim_prince_test.812796400
Short name T124
Test name
Test status
Simulation time 2773619567 ps
CPU time 48.98 seconds
Started Sep 01 04:32:47 AM UTC 24
Finished Sep 01 04:33:51 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=812796400 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 114.prim_prince_test.812796400
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/114.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/115.prim_prince_test.3424758441
Short name T122
Test name
Test status
Simulation time 2299909194 ps
CPU time 40.88 seconds
Started Sep 01 04:32:51 AM UTC 24
Finished Sep 01 04:33:44 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3424758441 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 115.prim_prince_test.3424758441
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/115.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/116.prim_prince_test.3945344704
Short name T120
Test name
Test status
Simulation time 2235324848 ps
CPU time 39.98 seconds
Started Sep 01 04:32:51 AM UTC 24
Finished Sep 01 04:33:43 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3945344704 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 116.prim_prince_test.3945344704
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/116.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/117.prim_prince_test.3735170353
Short name T108
Test name
Test status
Simulation time 977135340 ps
CPU time 17.64 seconds
Started Sep 01 04:32:54 AM UTC 24
Finished Sep 01 04:33:18 AM UTC 24
Peak memory 154588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3735170353 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 117.prim_prince_test.3735170353
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/117.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/118.prim_prince_test.3410125290
Short name T130
Test name
Test status
Simulation time 3167685167 ps
CPU time 56.18 seconds
Started Sep 01 04:32:58 AM UTC 24
Finished Sep 01 04:34:10 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3410125290 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 118.prim_prince_test.3410125290
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/118.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/119.prim_prince_test.3048453129
Short name T117
Test name
Test status
Simulation time 1685370842 ps
CPU time 30.07 seconds
Started Sep 01 04:33:00 AM UTC 24
Finished Sep 01 04:33:39 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3048453129 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 119.prim_prince_test.3048453129
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/119.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/12.prim_prince_test.1798030554
Short name T19
Test name
Test status
Simulation time 3381711902 ps
CPU time 61.48 seconds
Started Sep 01 04:27:54 AM UTC 24
Finished Sep 01 04:29:12 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1798030554 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 12.prim_prince_test.1798030554
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/12.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/120.prim_prince_test.1153544313
Short name T119
Test name
Test status
Simulation time 1848455462 ps
CPU time 32.94 seconds
Started Sep 01 04:33:00 AM UTC 24
Finished Sep 01 04:33:43 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1153544313 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 120.prim_prince_test.1153544313
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/120.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/121.prim_prince_test.2293494765
Short name T111
Test name
Test status
Simulation time 1112526124 ps
CPU time 20.02 seconds
Started Sep 01 04:33:02 AM UTC 24
Finished Sep 01 04:33:28 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2293494765 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 121.prim_prince_test.2293494765
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/121.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/122.prim_prince_test.2092729012
Short name T118
Test name
Test status
Simulation time 1619480251 ps
CPU time 28.76 seconds
Started Sep 01 04:33:03 AM UTC 24
Finished Sep 01 04:33:40 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2092729012 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 122.prim_prince_test.2092729012
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/122.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/123.prim_prince_test.1557559689
Short name T116
Test name
Test status
Simulation time 1229212335 ps
CPU time 22.22 seconds
Started Sep 01 04:33:09 AM UTC 24
Finished Sep 01 04:33:38 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1557559689 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 123.prim_prince_test.1557559689
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/123.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/124.prim_prince_test.3023025523
Short name T121
Test name
Test status
Simulation time 1383572988 ps
CPU time 24.64 seconds
Started Sep 01 04:33:11 AM UTC 24
Finished Sep 01 04:33:43 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3023025523 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 124.prim_prince_test.3023025523
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/124.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/125.prim_prince_test.1358226636
Short name T125
Test name
Test status
Simulation time 1683518859 ps
CPU time 30.25 seconds
Started Sep 01 04:33:18 AM UTC 24
Finished Sep 01 04:33:57 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1358226636 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 125.prim_prince_test.1358226636
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/125.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/126.prim_prince_test.2227734074
Short name T132
Test name
Test status
Simulation time 2461569312 ps
CPU time 43.28 seconds
Started Sep 01 04:33:18 AM UTC 24
Finished Sep 01 04:34:14 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2227734074 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 126.prim_prince_test.2227734074
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/126.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/127.prim_prince_test.1026188579
Short name T141
Test name
Test status
Simulation time 3728200127 ps
CPU time 65.22 seconds
Started Sep 01 04:33:19 AM UTC 24
Finished Sep 01 04:34:43 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1026188579 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 127.prim_prince_test.1026188579
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/127.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/128.prim_prince_test.781175837
Short name T129
Test name
Test status
Simulation time 1915941731 ps
CPU time 34.03 seconds
Started Sep 01 04:33:24 AM UTC 24
Finished Sep 01 04:34:09 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=781175837 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 128.prim_prince_test.781175837
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/128.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/129.prim_prince_test.2960741905
Short name T126
Test name
Test status
Simulation time 1316595317 ps
CPU time 23.52 seconds
Started Sep 01 04:33:29 AM UTC 24
Finished Sep 01 04:34:00 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2960741905 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 129.prim_prince_test.2960741905
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/129.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/13.prim_prince_test.776216608
Short name T3
Test name
Test status
Simulation time 1193321058 ps
CPU time 22.09 seconds
Started Sep 01 04:27:54 AM UTC 24
Finished Sep 01 04:28:23 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=776216608 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 13.prim_prince_test.776216608
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/13.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/130.prim_prince_test.3205545185
Short name T148
Test name
Test status
Simulation time 3683068726 ps
CPU time 65.33 seconds
Started Sep 01 04:33:33 AM UTC 24
Finished Sep 01 04:34:57 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3205545185 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 130.prim_prince_test.3205545185
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/130.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/131.prim_prince_test.2648051786
Short name T145
Test name
Test status
Simulation time 3287032503 ps
CPU time 58.53 seconds
Started Sep 01 04:33:33 AM UTC 24
Finished Sep 01 04:34:48 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2648051786 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 131.prim_prince_test.2648051786
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/131.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/132.prim_prince_test.1117905670
Short name T136
Test name
Test status
Simulation time 2378558038 ps
CPU time 42.01 seconds
Started Sep 01 04:33:37 AM UTC 24
Finished Sep 01 04:34:31 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1117905670 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 132.prim_prince_test.1117905670
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/132.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/133.prim_prince_test.1973525353
Short name T128
Test name
Test status
Simulation time 1240766988 ps
CPU time 22.29 seconds
Started Sep 01 04:33:38 AM UTC 24
Finished Sep 01 04:34:07 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1973525353 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 133.prim_prince_test.1973525353
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/133.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/134.prim_prince_test.1753941661
Short name T127
Test name
Test status
Simulation time 959627149 ps
CPU time 17.23 seconds
Started Sep 01 04:33:39 AM UTC 24
Finished Sep 01 04:34:02 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1753941661 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 134.prim_prince_test.1753941661
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/134.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/135.prim_prince_test.2048779657
Short name T137
Test name
Test status
Simulation time 2375405994 ps
CPU time 41.92 seconds
Started Sep 01 04:33:40 AM UTC 24
Finished Sep 01 04:34:35 AM UTC 24
Peak memory 154652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2048779657 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 135.prim_prince_test.2048779657
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/135.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/136.prim_prince_test.2600609134
Short name T140
Test name
Test status
Simulation time 2656750756 ps
CPU time 47.8 seconds
Started Sep 01 04:33:41 AM UTC 24
Finished Sep 01 04:34:43 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2600609134 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 136.prim_prince_test.2600609134
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/136.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/137.prim_prince_test.1760345852
Short name T144
Test name
Test status
Simulation time 2767345554 ps
CPU time 49.6 seconds
Started Sep 01 04:33:43 AM UTC 24
Finished Sep 01 04:34:47 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1760345852 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 137.prim_prince_test.1760345852
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/137.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/138.prim_prince_test.4272009313
Short name T134
Test name
Test status
Simulation time 1544560705 ps
CPU time 27.89 seconds
Started Sep 01 04:33:44 AM UTC 24
Finished Sep 01 04:34:21 AM UTC 24
Peak memory 154588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4272009313 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 138.prim_prince_test.4272009313
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/138.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/139.prim_prince_test.1392022603
Short name T142
Test name
Test status
Simulation time 2701853866 ps
CPU time 47.43 seconds
Started Sep 01 04:33:44 AM UTC 24
Finished Sep 01 04:34:46 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1392022603 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 139.prim_prince_test.1392022603
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/139.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/14.prim_prince_test.1751335930
Short name T4
Test name
Test status
Simulation time 1110400608 ps
CPU time 20.31 seconds
Started Sep 01 04:27:57 AM UTC 24
Finished Sep 01 04:28:24 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1751335930 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 14.prim_prince_test.1751335930
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/14.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/140.prim_prince_test.4128297537
Short name T139
Test name
Test status
Simulation time 2518267303 ps
CPU time 44.07 seconds
Started Sep 01 04:33:46 AM UTC 24
Finished Sep 01 04:34:43 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4128297537 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 140.prim_prince_test.4128297537
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/140.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/141.prim_prince_test.2296531628
Short name T133
Test name
Test status
Simulation time 1139964318 ps
CPU time 20.3 seconds
Started Sep 01 04:33:51 AM UTC 24
Finished Sep 01 04:34:18 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2296531628 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 141.prim_prince_test.2296531628
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/141.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/142.prim_prince_test.1669503554
Short name T131
Test name
Test status
Simulation time 827484253 ps
CPU time 15.12 seconds
Started Sep 01 04:33:52 AM UTC 24
Finished Sep 01 04:34:12 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1669503554 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 142.prim_prince_test.1669503554
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/142.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/143.prim_prince_test.3338559727
Short name T135
Test name
Test status
Simulation time 1086465612 ps
CPU time 19.22 seconds
Started Sep 01 04:33:58 AM UTC 24
Finished Sep 01 04:34:23 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3338559727 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 143.prim_prince_test.3338559727
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/143.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/144.prim_prince_test.808762543
Short name T138
Test name
Test status
Simulation time 1529966088 ps
CPU time 27.13 seconds
Started Sep 01 04:34:00 AM UTC 24
Finished Sep 01 04:34:36 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=808762543 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 144.prim_prince_test.808762543
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/144.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/145.prim_prince_test.1961803526
Short name T143
Test name
Test status
Simulation time 1888084068 ps
CPU time 33.02 seconds
Started Sep 01 04:34:03 AM UTC 24
Finished Sep 01 04:34:46 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1961803526 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 145.prim_prince_test.1961803526
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/145.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/146.prim_prince_test.1689911245
Short name T146
Test name
Test status
Simulation time 1786035618 ps
CPU time 32.26 seconds
Started Sep 01 04:34:08 AM UTC 24
Finished Sep 01 04:34:50 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1689911245 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 146.prim_prince_test.1689911245
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/146.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/147.prim_prince_test.912212110
Short name T147
Test name
Test status
Simulation time 2004348103 ps
CPU time 36.08 seconds
Started Sep 01 04:34:09 AM UTC 24
Finished Sep 01 04:34:56 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=912212110 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 147.prim_prince_test.912212110
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/147.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/148.prim_prince_test.577586829
Short name T149
Test name
Test status
Simulation time 2276746490 ps
CPU time 39.69 seconds
Started Sep 01 04:34:10 AM UTC 24
Finished Sep 01 04:35:02 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=577586829 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 148.prim_prince_test.577586829
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/148.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/149.prim_prince_test.3704788411
Short name T154
Test name
Test status
Simulation time 3053810989 ps
CPU time 53.72 seconds
Started Sep 01 04:34:12 AM UTC 24
Finished Sep 01 04:35:22 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3704788411 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 149.prim_prince_test.3704788411
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/149.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/15.prim_prince_test.723924774
Short name T6
Test name
Test status
Simulation time 1699854957 ps
CPU time 30.84 seconds
Started Sep 01 04:27:57 AM UTC 24
Finished Sep 01 04:28:37 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=723924774 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 15.prim_prince_test.723924774
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/15.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/150.prim_prince_test.3617365575
Short name T160
Test name
Test status
Simulation time 3639361649 ps
CPU time 63.59 seconds
Started Sep 01 04:34:16 AM UTC 24
Finished Sep 01 04:35:38 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3617365575 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 150.prim_prince_test.3617365575
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/150.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/151.prim_prince_test.2010296717
Short name T158
Test name
Test status
Simulation time 3054208229 ps
CPU time 54.18 seconds
Started Sep 01 04:34:19 AM UTC 24
Finished Sep 01 04:35:29 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2010296717 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 151.prim_prince_test.2010296717
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/151.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/152.prim_prince_test.129048103
Short name T153
Test name
Test status
Simulation time 2541135886 ps
CPU time 45.54 seconds
Started Sep 01 04:34:22 AM UTC 24
Finished Sep 01 04:35:21 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=129048103 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 152.prim_prince_test.129048103
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/152.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/153.prim_prince_test.4243500843
Short name T151
Test name
Test status
Simulation time 2042804806 ps
CPU time 36.04 seconds
Started Sep 01 04:34:24 AM UTC 24
Finished Sep 01 04:35:11 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4243500843 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 153.prim_prince_test.4243500843
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/153.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/154.prim_prince_test.2530042492
Short name T162
Test name
Test status
Simulation time 3305559992 ps
CPU time 57.65 seconds
Started Sep 01 04:34:32 AM UTC 24
Finished Sep 01 04:35:47 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2530042492 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 154.prim_prince_test.2530042492
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/154.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/155.prim_prince_test.2636054202
Short name T156
Test name
Test status
Simulation time 2242882693 ps
CPU time 39.45 seconds
Started Sep 01 04:34:35 AM UTC 24
Finished Sep 01 04:35:26 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2636054202 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 155.prim_prince_test.2636054202
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/155.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/156.prim_prince_test.3051206191
Short name T163
Test name
Test status
Simulation time 3096968675 ps
CPU time 54.61 seconds
Started Sep 01 04:34:36 AM UTC 24
Finished Sep 01 04:35:47 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3051206191 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 156.prim_prince_test.3051206191
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/156.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/157.prim_prince_test.865445738
Short name T174
Test name
Test status
Simulation time 3614638284 ps
CPU time 63.06 seconds
Started Sep 01 04:34:44 AM UTC 24
Finished Sep 01 04:36:06 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=865445738 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 157.prim_prince_test.865445738
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/157.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/158.prim_prince_test.3665390007
Short name T157
Test name
Test status
Simulation time 1915772481 ps
CPU time 33.71 seconds
Started Sep 01 04:34:44 AM UTC 24
Finished Sep 01 04:35:28 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3665390007 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 158.prim_prince_test.3665390007
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/158.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/159.prim_prince_test.2431336385
Short name T150
Test name
Test status
Simulation time 796695421 ps
CPU time 14.21 seconds
Started Sep 01 04:34:44 AM UTC 24
Finished Sep 01 04:35:03 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2431336385 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 159.prim_prince_test.2431336385
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/159.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/16.prim_prince_test.848460495
Short name T13
Test name
Test status
Simulation time 2421584752 ps
CPU time 44.1 seconds
Started Sep 01 04:28:01 AM UTC 24
Finished Sep 01 04:28:57 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=848460495 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 16.prim_prince_test.848460495
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/16.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/160.prim_prince_test.33968196
Short name T173
Test name
Test status
Simulation time 3514512380 ps
CPU time 61.04 seconds
Started Sep 01 04:34:47 AM UTC 24
Finished Sep 01 04:36:06 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33968196 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 160.prim_prince_test.33968196
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/160.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/161.prim_prince_test.1704169035
Short name T166
Test name
Test status
Simulation time 3251542081 ps
CPU time 56.94 seconds
Started Sep 01 04:34:47 AM UTC 24
Finished Sep 01 04:36:00 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1704169035 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 161.prim_prince_test.1704169035
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/161.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/162.prim_prince_test.1816364611
Short name T152
Test name
Test status
Simulation time 1369282564 ps
CPU time 24.64 seconds
Started Sep 01 04:34:48 AM UTC 24
Finished Sep 01 04:35:20 AM UTC 24
Peak memory 154580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1816364611 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 162.prim_prince_test.1816364611
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/162.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/163.prim_prince_test.4232308683
Short name T155
Test name
Test status
Simulation time 1506324250 ps
CPU time 26.85 seconds
Started Sep 01 04:34:49 AM UTC 24
Finished Sep 01 04:35:24 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4232308683 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 163.prim_prince_test.4232308683
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/163.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/164.prim_prince_test.2655166668
Short name T168
Test name
Test status
Simulation time 3067729789 ps
CPU time 54.36 seconds
Started Sep 01 04:34:51 AM UTC 24
Finished Sep 01 04:36:01 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2655166668 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 164.prim_prince_test.2655166668
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/164.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/165.prim_prince_test.1555425845
Short name T175
Test name
Test status
Simulation time 3469844249 ps
CPU time 60.66 seconds
Started Sep 01 04:34:57 AM UTC 24
Finished Sep 01 04:36:16 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1555425845 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 165.prim_prince_test.1555425845
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/165.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/166.prim_prince_test.3187115155
Short name T159
Test name
Test status
Simulation time 1525961324 ps
CPU time 27.21 seconds
Started Sep 01 04:34:58 AM UTC 24
Finished Sep 01 04:35:34 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3187115155 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 166.prim_prince_test.3187115155
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/166.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/167.prim_prince_test.3667992803
Short name T170
Test name
Test status
Simulation time 2609246670 ps
CPU time 46.32 seconds
Started Sep 01 04:35:02 AM UTC 24
Finished Sep 01 04:36:02 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3667992803 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 167.prim_prince_test.3667992803
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/167.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/168.prim_prince_test.2196784783
Short name T161
Test name
Test status
Simulation time 1475234164 ps
CPU time 26.65 seconds
Started Sep 01 04:35:04 AM UTC 24
Finished Sep 01 04:35:39 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2196784783 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 168.prim_prince_test.2196784783
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/168.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/169.prim_prince_test.11713628
Short name T176
Test name
Test status
Simulation time 2933146495 ps
CPU time 51.15 seconds
Started Sep 01 04:35:11 AM UTC 24
Finished Sep 01 04:36:18 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11713628 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 169.prim_prince_test.11713628
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/169.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/17.prim_prince_test.2327239413
Short name T16
Test name
Test status
Simulation time 2866036890 ps
CPU time 50.9 seconds
Started Sep 01 04:28:04 AM UTC 24
Finished Sep 01 04:29:09 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2327239413 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 17.prim_prince_test.2327239413
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/17.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/170.prim_prince_test.4258584776
Short name T181
Test name
Test status
Simulation time 3115625098 ps
CPU time 54.4 seconds
Started Sep 01 04:35:21 AM UTC 24
Finished Sep 01 04:36:32 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4258584776 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 170.prim_prince_test.4258584776
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/170.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/171.prim_prince_test.2673611820
Short name T180
Test name
Test status
Simulation time 2992269226 ps
CPU time 51.96 seconds
Started Sep 01 04:35:22 AM UTC 24
Finished Sep 01 04:36:30 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2673611820 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 171.prim_prince_test.2673611820
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/171.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/172.prim_prince_test.3026946007
Short name T171
Test name
Test status
Simulation time 1715541994 ps
CPU time 30.59 seconds
Started Sep 01 04:35:23 AM UTC 24
Finished Sep 01 04:36:03 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3026946007 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 172.prim_prince_test.3026946007
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/172.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/173.prim_prince_test.2474365758
Short name T164
Test name
Test status
Simulation time 1381671081 ps
CPU time 24.63 seconds
Started Sep 01 04:35:25 AM UTC 24
Finished Sep 01 04:35:58 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2474365758 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 173.prim_prince_test.2474365758
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/173.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/174.prim_prince_test.385301993
Short name T172
Test name
Test status
Simulation time 1653274064 ps
CPU time 28.96 seconds
Started Sep 01 04:35:27 AM UTC 24
Finished Sep 01 04:36:05 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=385301993 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 174.prim_prince_test.385301993
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/174.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/175.prim_prince_test.1415886827
Short name T167
Test name
Test status
Simulation time 1342398359 ps
CPU time 23.72 seconds
Started Sep 01 04:35:29 AM UTC 24
Finished Sep 01 04:36:01 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1415886827 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 175.prim_prince_test.1415886827
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/175.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/176.prim_prince_test.4047048529
Short name T179
Test name
Test status
Simulation time 2625480436 ps
CPU time 46.3 seconds
Started Sep 01 04:35:29 AM UTC 24
Finished Sep 01 04:36:29 AM UTC 24
Peak memory 156112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4047048529 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 176.prim_prince_test.4047048529
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/176.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/177.prim_prince_test.2297734388
Short name T169
Test name
Test status
Simulation time 1163362707 ps
CPU time 20.67 seconds
Started Sep 01 04:35:34 AM UTC 24
Finished Sep 01 04:36:02 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2297734388 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 177.prim_prince_test.2297734388
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/177.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/178.prim_prince_test.4099489108
Short name T177
Test name
Test status
Simulation time 1830785356 ps
CPU time 32.37 seconds
Started Sep 01 04:35:38 AM UTC 24
Finished Sep 01 04:36:21 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4099489108 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 178.prim_prince_test.4099489108
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/178.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/179.prim_prince_test.1686563986
Short name T165
Test name
Test status
Simulation time 764488713 ps
CPU time 13.81 seconds
Started Sep 01 04:35:40 AM UTC 24
Finished Sep 01 04:35:58 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1686563986 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 179.prim_prince_test.1686563986
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/179.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/18.prim_prince_test.3801533083
Short name T10
Test name
Test status
Simulation time 1970107184 ps
CPU time 36.19 seconds
Started Sep 01 04:28:06 AM UTC 24
Finished Sep 01 04:28:52 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3801533083 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 18.prim_prince_test.3801533083
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/18.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/180.prim_prince_test.4230844845
Short name T193
Test name
Test status
Simulation time 3571600878 ps
CPU time 62.83 seconds
Started Sep 01 04:35:48 AM UTC 24
Finished Sep 01 04:37:09 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4230844845 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 180.prim_prince_test.4230844845
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/180.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/181.prim_prince_test.1368026119
Short name T187
Test name
Test status
Simulation time 3009344903 ps
CPU time 52.89 seconds
Started Sep 01 04:35:48 AM UTC 24
Finished Sep 01 04:36:56 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1368026119 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 181.prim_prince_test.1368026119
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/181.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/182.prim_prince_test.1559785701
Short name T192
Test name
Test status
Simulation time 2975066628 ps
CPU time 52.07 seconds
Started Sep 01 04:35:58 AM UTC 24
Finished Sep 01 04:37:05 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1559785701 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 182.prim_prince_test.1559785701
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/182.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/183.prim_prince_test.3261691905
Short name T186
Test name
Test status
Simulation time 2107856253 ps
CPU time 37.28 seconds
Started Sep 01 04:35:59 AM UTC 24
Finished Sep 01 04:36:48 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3261691905 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 183.prim_prince_test.3261691905
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/183.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/184.prim_prince_test.2704019590
Short name T178
Test name
Test status
Simulation time 1036968622 ps
CPU time 18.48 seconds
Started Sep 01 04:36:01 AM UTC 24
Finished Sep 01 04:36:26 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2704019590 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 184.prim_prince_test.2704019590
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/184.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/185.prim_prince_test.2872601941
Short name T194
Test name
Test status
Simulation time 2987905495 ps
CPU time 52.43 seconds
Started Sep 01 04:36:01 AM UTC 24
Finished Sep 01 04:37:09 AM UTC 24
Peak memory 154652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2872601941 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 185.prim_prince_test.2872601941
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/185.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/186.prim_prince_test.1604740698
Short name T182
Test name
Test status
Simulation time 1313269803 ps
CPU time 23.64 seconds
Started Sep 01 04:36:02 AM UTC 24
Finished Sep 01 04:36:33 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1604740698 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 186.prim_prince_test.1604740698
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/186.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/187.prim_prince_test.1096957210
Short name T191
Test name
Test status
Simulation time 2572280061 ps
CPU time 45.5 seconds
Started Sep 01 04:36:02 AM UTC 24
Finished Sep 01 04:37:01 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1096957210 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 187.prim_prince_test.1096957210
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/187.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/188.prim_prince_test.2379407876
Short name T183
Test name
Test status
Simulation time 1382066474 ps
CPU time 24.71 seconds
Started Sep 01 04:36:04 AM UTC 24
Finished Sep 01 04:36:36 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2379407876 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 188.prim_prince_test.2379407876
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/188.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/189.prim_prince_test.4125995974
Short name T189
Test name
Test status
Simulation time 2379840333 ps
CPU time 41.84 seconds
Started Sep 01 04:36:04 AM UTC 24
Finished Sep 01 04:36:58 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4125995974 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 189.prim_prince_test.4125995974
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/189.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/19.prim_prince_test.4112355458
Short name T21
Test name
Test status
Simulation time 2440704469 ps
CPU time 43.43 seconds
Started Sep 01 04:28:18 AM UTC 24
Finished Sep 01 04:29:14 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4112355458 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 19.prim_prince_test.4112355458
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/19.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/190.prim_prince_test.3497243260
Short name T184
Test name
Test status
Simulation time 1315828274 ps
CPU time 23.36 seconds
Started Sep 01 04:36:06 AM UTC 24
Finished Sep 01 04:36:37 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3497243260 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 190.prim_prince_test.3497243260
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/190.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/191.prim_prince_test.1098340132
Short name T200
Test name
Test status
Simulation time 3308660783 ps
CPU time 57.97 seconds
Started Sep 01 04:36:07 AM UTC 24
Finished Sep 01 04:37:22 AM UTC 24
Peak memory 154632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1098340132 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 191.prim_prince_test.1098340132
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/191.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/192.prim_prince_test.321042946
Short name T185
Test name
Test status
Simulation time 1705753527 ps
CPU time 30.25 seconds
Started Sep 01 04:36:07 AM UTC 24
Finished Sep 01 04:36:46 AM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=321042946 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 192.prim_prince_test.321042946
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/192.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/193.prim_prince_test.626231084
Short name T190
Test name
Test status
Simulation time 1889244533 ps
CPU time 33.35 seconds
Started Sep 01 04:36:16 AM UTC 24
Finished Sep 01 04:37:00 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=626231084 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 193.prim_prince_test.626231084
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/193.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/194.prim_prince_test.1132812279
Short name T204
Test name
Test status
Simulation time 3058161338 ps
CPU time 54.19 seconds
Started Sep 01 04:36:18 AM UTC 24
Finished Sep 01 04:37:28 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1132812279 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 194.prim_prince_test.1132812279
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/194.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/195.prim_prince_test.308827918
Short name T198
Test name
Test status
Simulation time 2553161109 ps
CPU time 44.86 seconds
Started Sep 01 04:36:21 AM UTC 24
Finished Sep 01 04:37:19 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=308827918 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 195.prim_prince_test.308827918
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/195.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/196.prim_prince_test.965234574
Short name T205
Test name
Test status
Simulation time 2915316552 ps
CPU time 51.26 seconds
Started Sep 01 04:36:26 AM UTC 24
Finished Sep 01 04:37:33 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=965234574 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 196.prim_prince_test.965234574
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/196.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/197.prim_prince_test.348648909
Short name T199
Test name
Test status
Simulation time 2161398876 ps
CPU time 38.08 seconds
Started Sep 01 04:36:31 AM UTC 24
Finished Sep 01 04:37:20 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=348648909 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 197.prim_prince_test.348648909
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/197.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/198.prim_prince_test.57790827
Short name T195
Test name
Test status
Simulation time 1685361433 ps
CPU time 30.06 seconds
Started Sep 01 04:36:31 AM UTC 24
Finished Sep 01 04:37:10 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=57790827 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 198.prim_prince_test.57790827
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/198.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/199.prim_prince_test.159961641
Short name T188
Test name
Test status
Simulation time 1013620499 ps
CPU time 18.28 seconds
Started Sep 01 04:36:33 AM UTC 24
Finished Sep 01 04:36:57 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=159961641 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 199.prim_prince_test.159961641
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/199.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/2.prim_prince_test.4232006864
Short name T15
Test name
Test status
Simulation time 3026631122 ps
CPU time 53.9 seconds
Started Sep 01 04:27:53 AM UTC 24
Finished Sep 01 04:29:01 AM UTC 24
Peak memory 154652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4232006864 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 2.prim_prince_test.4232006864
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/2.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/20.prim_prince_test.1258682446
Short name T30
Test name
Test status
Simulation time 3481299050 ps
CPU time 61.82 seconds
Started Sep 01 04:28:18 AM UTC 24
Finished Sep 01 04:29:37 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1258682446 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 20.prim_prince_test.1258682446
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/20.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/200.prim_prince_test.1427431095
Short name T202
Test name
Test status
Simulation time 2328735688 ps
CPU time 40.93 seconds
Started Sep 01 04:36:34 AM UTC 24
Finished Sep 01 04:37:27 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1427431095 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 200.prim_prince_test.1427431095
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/200.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/201.prim_prince_test.2302440
Short name T201
Test name
Test status
Simulation time 2081366237 ps
CPU time 36.9 seconds
Started Sep 01 04:36:37 AM UTC 24
Finished Sep 01 04:37:25 AM UTC 24
Peak memory 154460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2302440 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 201.prim_prince_test.2302440
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/201.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/202.prim_prince_test.639658388
Short name T196
Test name
Test status
Simulation time 1706965384 ps
CPU time 30.09 seconds
Started Sep 01 04:36:37 AM UTC 24
Finished Sep 01 04:37:16 AM UTC 24
Peak memory 154400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=639658388 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 202.prim_prince_test.639658388
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/202.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/203.prim_prince_test.238858876
Short name T203
Test name
Test status
Simulation time 1765824008 ps
CPU time 30.95 seconds
Started Sep 01 04:36:47 AM UTC 24
Finished Sep 01 04:37:28 AM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=238858876 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 203.prim_prince_test.238858876
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/203.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/204.prim_prince_test.3335098420
Short name T208
Test name
Test status
Simulation time 2912139320 ps
CPU time 50.87 seconds
Started Sep 01 04:36:48 AM UTC 24
Finished Sep 01 04:37:54 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3335098420 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 204.prim_prince_test.3335098420
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/204.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/205.prim_prince_test.3594928867
Short name T216
Test name
Test status
Simulation time 3647931886 ps
CPU time 63.73 seconds
Started Sep 01 04:36:57 AM UTC 24
Finished Sep 01 04:38:20 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3594928867 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 205.prim_prince_test.3594928867
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/205.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/206.prim_prince_test.504054158
Short name T210
Test name
Test status
Simulation time 2476734954 ps
CPU time 43.78 seconds
Started Sep 01 04:36:59 AM UTC 24
Finished Sep 01 04:37:56 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=504054158 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 206.prim_prince_test.504054158
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/206.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/207.prim_prince_test.2874385083
Short name T197
Test name
Test status
Simulation time 842860941 ps
CPU time 15.12 seconds
Started Sep 01 04:36:59 AM UTC 24
Finished Sep 01 04:37:19 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2874385083 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 207.prim_prince_test.2874385083
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/207.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/208.prim_prince_test.3415611615
Short name T221
Test name
Test status
Simulation time 3727810017 ps
CPU time 65.89 seconds
Started Sep 01 04:37:01 AM UTC 24
Finished Sep 01 04:38:26 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3415611615 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 208.prim_prince_test.3415611615
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/208.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/209.prim_prince_test.2059986995
Short name T206
Test name
Test status
Simulation time 1769871493 ps
CPU time 31.24 seconds
Started Sep 01 04:37:03 AM UTC 24
Finished Sep 01 04:37:44 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2059986995 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 209.prim_prince_test.2059986995
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/209.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/21.prim_prince_test.1738997676
Short name T23
Test name
Test status
Simulation time 2270809560 ps
CPU time 41.37 seconds
Started Sep 01 04:28:24 AM UTC 24
Finished Sep 01 04:29:17 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1738997676 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 21.prim_prince_test.1738997676
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/21.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/210.prim_prince_test.1543842213
Short name T219
Test name
Test status
Simulation time 3441803409 ps
CPU time 60.16 seconds
Started Sep 01 04:37:06 AM UTC 24
Finished Sep 01 04:38:24 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1543842213 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 210.prim_prince_test.1543842213
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/210.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/211.prim_prince_test.838920661
Short name T224
Test name
Test status
Simulation time 3448893632 ps
CPU time 60.1 seconds
Started Sep 01 04:37:10 AM UTC 24
Finished Sep 01 04:38:28 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=838920661 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 211.prim_prince_test.838920661
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/211.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/212.prim_prince_test.415018264
Short name T212
Test name
Test status
Simulation time 2180140114 ps
CPU time 38.33 seconds
Started Sep 01 04:37:10 AM UTC 24
Finished Sep 01 04:38:00 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=415018264 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 212.prim_prince_test.415018264
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/212.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/213.prim_prince_test.4196267865
Short name T215
Test name
Test status
Simulation time 2736370881 ps
CPU time 48.13 seconds
Started Sep 01 04:37:11 AM UTC 24
Finished Sep 01 04:38:14 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4196267865 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 213.prim_prince_test.4196267865
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/213.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/214.prim_prince_test.1846262660
Short name T218
Test name
Test status
Simulation time 2863219518 ps
CPU time 50.91 seconds
Started Sep 01 04:37:17 AM UTC 24
Finished Sep 01 04:38:23 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1846262660 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 214.prim_prince_test.1846262660
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/214.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/215.prim_prince_test.1113402257
Short name T209
Test name
Test status
Simulation time 1515504809 ps
CPU time 26.78 seconds
Started Sep 01 04:37:20 AM UTC 24
Finished Sep 01 04:37:55 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1113402257 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 215.prim_prince_test.1113402257
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/215.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/216.prim_prince_test.2664173584
Short name T227
Test name
Test status
Simulation time 3346006165 ps
CPU time 59.39 seconds
Started Sep 01 04:37:21 AM UTC 24
Finished Sep 01 04:38:38 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2664173584 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 216.prim_prince_test.2664173584
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/216.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/217.prim_prince_test.3916712813
Short name T207
Test name
Test status
Simulation time 1197065477 ps
CPU time 21.03 seconds
Started Sep 01 04:37:21 AM UTC 24
Finished Sep 01 04:37:49 AM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3916712813 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 217.prim_prince_test.3916712813
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/217.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/218.prim_prince_test.3817907744
Short name T217
Test name
Test status
Simulation time 2556053197 ps
CPU time 45.24 seconds
Started Sep 01 04:37:23 AM UTC 24
Finished Sep 01 04:38:22 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3817907744 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 218.prim_prince_test.3817907744
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/218.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/219.prim_prince_test.2195658079
Short name T211
Test name
Test status
Simulation time 1422002463 ps
CPU time 25.41 seconds
Started Sep 01 04:37:26 AM UTC 24
Finished Sep 01 04:38:00 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2195658079 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 219.prim_prince_test.2195658079
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/219.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/22.prim_prince_test.3006923416
Short name T8
Test name
Test status
Simulation time 934945313 ps
CPU time 17.45 seconds
Started Sep 01 04:28:25 AM UTC 24
Finished Sep 01 04:28:48 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3006923416 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 22.prim_prince_test.3006923416
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/22.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/220.prim_prince_test.2069872607
Short name T222
Test name
Test status
Simulation time 2593126049 ps
CPU time 45.31 seconds
Started Sep 01 04:37:28 AM UTC 24
Finished Sep 01 04:38:27 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2069872607 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 220.prim_prince_test.2069872607
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/220.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/221.prim_prince_test.1828219509
Short name T213
Test name
Test status
Simulation time 1439732659 ps
CPU time 25.75 seconds
Started Sep 01 04:37:28 AM UTC 24
Finished Sep 01 04:38:02 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1828219509 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 221.prim_prince_test.1828219509
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/221.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/222.prim_prince_test.3439663892
Short name T225
Test name
Test status
Simulation time 2661444044 ps
CPU time 47.49 seconds
Started Sep 01 04:37:29 AM UTC 24
Finished Sep 01 04:38:31 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3439663892 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 222.prim_prince_test.3439663892
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/222.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/223.prim_prince_test.3712452179
Short name T214
Test name
Test status
Simulation time 1673121875 ps
CPU time 29.33 seconds
Started Sep 01 04:37:33 AM UTC 24
Finished Sep 01 04:38:12 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3712452179 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 223.prim_prince_test.3712452179
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/223.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/224.prim_prince_test.2895341376
Short name T233
Test name
Test status
Simulation time 2851426618 ps
CPU time 50.6 seconds
Started Sep 01 04:37:45 AM UTC 24
Finished Sep 01 04:38:50 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2895341376 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 224.prim_prince_test.2895341376
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/224.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/225.prim_prince_test.1159499730
Short name T223
Test name
Test status
Simulation time 1670418922 ps
CPU time 29.11 seconds
Started Sep 01 04:37:50 AM UTC 24
Finished Sep 01 04:38:28 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1159499730 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 225.prim_prince_test.1159499730
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/225.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/226.prim_prince_test.1582744684
Short name T226
Test name
Test status
Simulation time 1600356690 ps
CPU time 29.03 seconds
Started Sep 01 04:37:55 AM UTC 24
Finished Sep 01 04:38:33 AM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1582744684 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 226.prim_prince_test.1582744684
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/226.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/227.prim_prince_test.1680191457
Short name T220
Test name
Test status
Simulation time 1241841535 ps
CPU time 21.96 seconds
Started Sep 01 04:37:56 AM UTC 24
Finished Sep 01 04:38:25 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1680191457 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 227.prim_prince_test.1680191457
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/227.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/228.prim_prince_test.2334676373
Short name T241
Test name
Test status
Simulation time 3708267794 ps
CPU time 65.9 seconds
Started Sep 01 04:37:56 AM UTC 24
Finished Sep 01 04:39:21 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2334676373 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 228.prim_prince_test.2334676373
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/228.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/229.prim_prince_test.2250811754
Short name T235
Test name
Test status
Simulation time 2404151980 ps
CPU time 42.03 seconds
Started Sep 01 04:38:00 AM UTC 24
Finished Sep 01 04:38:55 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2250811754 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 229.prim_prince_test.2250811754
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/229.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/23.prim_prince_test.3670289862
Short name T11
Test name
Test status
Simulation time 957504063 ps
CPU time 17.88 seconds
Started Sep 01 04:28:29 AM UTC 24
Finished Sep 01 04:28:53 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3670289862 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 23.prim_prince_test.3670289862
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/23.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/230.prim_prince_test.3578456019
Short name T231
Test name
Test status
Simulation time 2029390198 ps
CPU time 36.34 seconds
Started Sep 01 04:38:01 AM UTC 24
Finished Sep 01 04:38:49 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3578456019 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 230.prim_prince_test.3578456019
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/230.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/231.prim_prince_test.4040229490
Short name T239
Test name
Test status
Simulation time 2507806067 ps
CPU time 43.75 seconds
Started Sep 01 04:38:03 AM UTC 24
Finished Sep 01 04:39:00 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4040229490 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 231.prim_prince_test.4040229490
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/231.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/232.prim_prince_test.1725306739
Short name T236
Test name
Test status
Simulation time 1887790486 ps
CPU time 33.04 seconds
Started Sep 01 04:38:13 AM UTC 24
Finished Sep 01 04:38:56 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1725306739 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 232.prim_prince_test.1725306739
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/232.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/233.prim_prince_test.3713599412
Short name T229
Test name
Test status
Simulation time 1345768330 ps
CPU time 23.82 seconds
Started Sep 01 04:38:15 AM UTC 24
Finished Sep 01 04:38:46 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3713599412 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 233.prim_prince_test.3713599412
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/233.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/234.prim_prince_test.359851528
Short name T232
Test name
Test status
Simulation time 1197599452 ps
CPU time 21.24 seconds
Started Sep 01 04:38:21 AM UTC 24
Finished Sep 01 04:38:49 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=359851528 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 234.prim_prince_test.359851528
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/234.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/235.prim_prince_test.2300491207
Short name T228
Test name
Test status
Simulation time 880758465 ps
CPU time 15.65 seconds
Started Sep 01 04:38:23 AM UTC 24
Finished Sep 01 04:38:44 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2300491207 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 235.prim_prince_test.2300491207
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/235.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/236.prim_prince_test.1845112832
Short name T240
Test name
Test status
Simulation time 2372658447 ps
CPU time 41.53 seconds
Started Sep 01 04:38:24 AM UTC 24
Finished Sep 01 04:39:18 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1845112832 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 236.prim_prince_test.1845112832
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/236.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/237.prim_prince_test.1685095232
Short name T242
Test name
Test status
Simulation time 2939721379 ps
CPU time 51.83 seconds
Started Sep 01 04:38:25 AM UTC 24
Finished Sep 01 04:39:33 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1685095232 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 237.prim_prince_test.1685095232
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/237.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/238.prim_prince_test.956491458
Short name T230
Test name
Test status
Simulation time 792779455 ps
CPU time 14.23 seconds
Started Sep 01 04:38:26 AM UTC 24
Finished Sep 01 04:38:46 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=956491458 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 238.prim_prince_test.956491458
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/238.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/239.prim_prince_test.1990681832
Short name T238
Test name
Test status
Simulation time 1297169670 ps
CPU time 23.01 seconds
Started Sep 01 04:38:27 AM UTC 24
Finished Sep 01 04:38:58 AM UTC 24
Peak memory 154580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1990681832 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 239.prim_prince_test.1990681832
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/239.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/24.prim_prince_test.3630363179
Short name T24
Test name
Test status
Simulation time 1884137091 ps
CPU time 33.6 seconds
Started Sep 01 04:28:38 AM UTC 24
Finished Sep 01 04:29:22 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3630363179 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 24.prim_prince_test.3630363179
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/24.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/240.prim_prince_test.2947533772
Short name T244
Test name
Test status
Simulation time 2968718688 ps
CPU time 52.38 seconds
Started Sep 01 04:38:27 AM UTC 24
Finished Sep 01 04:39:36 AM UTC 24
Peak memory 154636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2947533772 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 240.prim_prince_test.2947533772
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/240.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/241.prim_prince_test.60577638
Short name T249
Test name
Test status
Simulation time 3447821312 ps
CPU time 60.57 seconds
Started Sep 01 04:38:29 AM UTC 24
Finished Sep 01 04:39:47 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=60577638 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 241.prim_prince_test.60577638
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/241.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/242.prim_prince_test.371275840
Short name T248
Test name
Test status
Simulation time 3334657995 ps
CPU time 58.78 seconds
Started Sep 01 04:38:30 AM UTC 24
Finished Sep 01 04:39:46 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=371275840 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 242.prim_prince_test.371275840
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/242.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/243.prim_prince_test.1659013572
Short name T234
Test name
Test status
Simulation time 852364698 ps
CPU time 15.37 seconds
Started Sep 01 04:38:32 AM UTC 24
Finished Sep 01 04:38:52 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1659013572 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 243.prim_prince_test.1659013572
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/243.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/244.prim_prince_test.3613638704
Short name T243
Test name
Test status
Simulation time 2644713365 ps
CPU time 46.78 seconds
Started Sep 01 04:38:34 AM UTC 24
Finished Sep 01 04:39:34 AM UTC 24
Peak memory 154640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3613638704 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 244.prim_prince_test.3613638704
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/244.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/245.prim_prince_test.3254420542
Short name T237
Test name
Test status
Simulation time 796418549 ps
CPU time 14.44 seconds
Started Sep 01 04:38:38 AM UTC 24
Finished Sep 01 04:38:58 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3254420542 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 245.prim_prince_test.3254420542
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/245.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/246.prim_prince_test.1523490990
Short name T245
Test name
Test status
Simulation time 2359337807 ps
CPU time 41.46 seconds
Started Sep 01 04:38:44 AM UTC 24
Finished Sep 01 04:39:38 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1523490990 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 246.prim_prince_test.1523490990
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/246.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/247.prim_prince_test.981796155
Short name T251
Test name
Test status
Simulation time 3042910868 ps
CPU time 53.81 seconds
Started Sep 01 04:38:46 AM UTC 24
Finished Sep 01 04:39:56 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=981796155 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 247.prim_prince_test.981796155
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/247.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/248.prim_prince_test.783365216
Short name T259
Test name
Test status
Simulation time 3598588951 ps
CPU time 63.03 seconds
Started Sep 01 04:38:47 AM UTC 24
Finished Sep 01 04:40:09 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=783365216 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 248.prim_prince_test.783365216
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/248.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/249.prim_prince_test.2025589102
Short name T254
Test name
Test status
Simulation time 3202049266 ps
CPU time 56.18 seconds
Started Sep 01 04:38:50 AM UTC 24
Finished Sep 01 04:40:02 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2025589102 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 249.prim_prince_test.2025589102
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/249.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/25.prim_prince_test.2330122745
Short name T36
Test name
Test status
Simulation time 3087933234 ps
CPU time 54.65 seconds
Started Sep 01 04:28:47 AM UTC 24
Finished Sep 01 04:29:58 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2330122745 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 25.prim_prince_test.2330122745
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/25.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/250.prim_prince_test.3430094605
Short name T261
Test name
Test status
Simulation time 3614054152 ps
CPU time 63.74 seconds
Started Sep 01 04:38:50 AM UTC 24
Finished Sep 01 04:40:12 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3430094605 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 250.prim_prince_test.3430094605
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/250.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/251.prim_prince_test.1753301257
Short name T252
Test name
Test status
Simulation time 2876508567 ps
CPU time 50.61 seconds
Started Sep 01 04:38:51 AM UTC 24
Finished Sep 01 04:39:56 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1753301257 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 251.prim_prince_test.1753301257
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/251.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/252.prim_prince_test.3756035483
Short name T253
Test name
Test status
Simulation time 2921456541 ps
CPU time 51.21 seconds
Started Sep 01 04:38:53 AM UTC 24
Finished Sep 01 04:39:59 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3756035483 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 252.prim_prince_test.3756035483
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/252.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/253.prim_prince_test.3672975365
Short name T262
Test name
Test status
Simulation time 3405338006 ps
CPU time 59.83 seconds
Started Sep 01 04:38:56 AM UTC 24
Finished Sep 01 04:40:14 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3672975365 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 253.prim_prince_test.3672975365
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/253.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/254.prim_prince_test.3646976740
Short name T246
Test name
Test status
Simulation time 1819914128 ps
CPU time 32.26 seconds
Started Sep 01 04:38:56 AM UTC 24
Finished Sep 01 04:39:38 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3646976740 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 254.prim_prince_test.3646976740
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/254.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/255.prim_prince_test.1456980254
Short name T258
Test name
Test status
Simulation time 3032756729 ps
CPU time 53.07 seconds
Started Sep 01 04:38:58 AM UTC 24
Finished Sep 01 04:40:07 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1456980254 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 255.prim_prince_test.1456980254
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/255.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/256.prim_prince_test.1880579226
Short name T265
Test name
Test status
Simulation time 3390658624 ps
CPU time 59.55 seconds
Started Sep 01 04:38:59 AM UTC 24
Finished Sep 01 04:40:16 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1880579226 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 256.prim_prince_test.1880579226
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/256.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/257.prim_prince_test.4189169592
Short name T250
Test name
Test status
Simulation time 2253160940 ps
CPU time 39.83 seconds
Started Sep 01 04:39:02 AM UTC 24
Finished Sep 01 04:39:53 AM UTC 24
Peak memory 154644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4189169592 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 257.prim_prince_test.4189169592
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/257.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/258.prim_prince_test.12094826
Short name T271
Test name
Test status
Simulation time 3425303294 ps
CPU time 60.29 seconds
Started Sep 01 04:39:19 AM UTC 24
Finished Sep 01 04:40:37 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=12094826 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 258.prim_prince_test.12094826
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/258.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/259.prim_prince_test.3232671501
Short name T247
Test name
Test status
Simulation time 903152508 ps
CPU time 16.39 seconds
Started Sep 01 04:39:22 AM UTC 24
Finished Sep 01 04:39:44 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3232671501 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 259.prim_prince_test.3232671501
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/259.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/26.prim_prince_test.2720483851
Short name T25
Test name
Test status
Simulation time 1589940485 ps
CPU time 28.29 seconds
Started Sep 01 04:28:48 AM UTC 24
Finished Sep 01 04:29:25 AM UTC 24
Peak memory 154584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2720483851 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 26.prim_prince_test.2720483851
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/26.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/260.prim_prince_test.3915811488
Short name T256
Test name
Test status
Simulation time 1350347192 ps
CPU time 23.98 seconds
Started Sep 01 04:39:34 AM UTC 24
Finished Sep 01 04:40:06 AM UTC 24
Peak memory 154588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3915811488 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 260.prim_prince_test.3915811488
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/260.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/261.prim_prince_test.3419117389
Short name T264
Test name
Test status
Simulation time 1695615087 ps
CPU time 29.98 seconds
Started Sep 01 04:39:35 AM UTC 24
Finished Sep 01 04:40:15 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3419117389 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 261.prim_prince_test.3419117389
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/261.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/262.prim_prince_test.769104286
Short name T275
Test name
Test status
Simulation time 3270214184 ps
CPU time 57.46 seconds
Started Sep 01 04:39:36 AM UTC 24
Finished Sep 01 04:40:51 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=769104286 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 262.prim_prince_test.769104286
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/262.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/263.prim_prince_test.2280981190
Short name T266
Test name
Test status
Simulation time 2155363653 ps
CPU time 38.15 seconds
Started Sep 01 04:39:40 AM UTC 24
Finished Sep 01 04:40:29 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2280981190 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 263.prim_prince_test.2280981190
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/263.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/264.prim_prince_test.4282760885
Short name T257
Test name
Test status
Simulation time 1161838613 ps
CPU time 20.71 seconds
Started Sep 01 04:39:40 AM UTC 24
Finished Sep 01 04:40:07 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4282760885 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 264.prim_prince_test.4282760885
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/264.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/265.prim_prince_test.2939667569
Short name T263
Test name
Test status
Simulation time 1264969270 ps
CPU time 22.48 seconds
Started Sep 01 04:39:45 AM UTC 24
Finished Sep 01 04:40:14 AM UTC 24
Peak memory 154576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2939667569 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 265.prim_prince_test.2939667569
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/265.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/266.prim_prince_test.3426506161
Short name T270
Test name
Test status
Simulation time 2126685127 ps
CPU time 37.69 seconds
Started Sep 01 04:39:47 AM UTC 24
Finished Sep 01 04:40:36 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3426506161 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 266.prim_prince_test.3426506161
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/266.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/267.prim_prince_test.1392202655
Short name T260
Test name
Test status
Simulation time 893359789 ps
CPU time 16.1 seconds
Started Sep 01 04:39:48 AM UTC 24
Finished Sep 01 04:40:10 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1392202655 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 267.prim_prince_test.1392202655
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/267.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/268.prim_prince_test.4225330658
Short name T282
Test name
Test status
Simulation time 3289161866 ps
CPU time 57.32 seconds
Started Sep 01 04:39:54 AM UTC 24
Finished Sep 01 04:41:08 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4225330658 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 268.prim_prince_test.4225330658
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/268.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/269.prim_prince_test.119584515
Short name T272
Test name
Test status
Simulation time 2060103179 ps
CPU time 36.43 seconds
Started Sep 01 04:39:56 AM UTC 24
Finished Sep 01 04:40:44 AM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=119584515 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 269.prim_prince_test.119584515
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/269.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/27.prim_prince_test.1294577274
Short name T26
Test name
Test status
Simulation time 1755077418 ps
CPU time 31.48 seconds
Started Sep 01 04:28:48 AM UTC 24
Finished Sep 01 04:29:29 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1294577274 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 27.prim_prince_test.1294577274
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/27.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/270.prim_prince_test.4085569111
Short name T283
Test name
Test status
Simulation time 3141752769 ps
CPU time 55.04 seconds
Started Sep 01 04:39:57 AM UTC 24
Finished Sep 01 04:41:09 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4085569111 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 270.prim_prince_test.4085569111
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/270.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/271.prim_prince_test.4018626308
Short name T280
Test name
Test status
Simulation time 2776978479 ps
CPU time 48.66 seconds
Started Sep 01 04:40:01 AM UTC 24
Finished Sep 01 04:41:04 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4018626308 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 271.prim_prince_test.4018626308
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/271.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/272.prim_prince_test.592103592
Short name T278
Test name
Test status
Simulation time 2490387902 ps
CPU time 43.67 seconds
Started Sep 01 04:40:04 AM UTC 24
Finished Sep 01 04:41:01 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=592103592 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 272.prim_prince_test.592103592
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/272.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/273.prim_prince_test.3300068143
Short name T277
Test name
Test status
Simulation time 2243892941 ps
CPU time 39.87 seconds
Started Sep 01 04:40:07 AM UTC 24
Finished Sep 01 04:40:59 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3300068143 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 273.prim_prince_test.3300068143
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/273.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/274.prim_prince_test.4007294528
Short name T267
Test name
Test status
Simulation time 1069767842 ps
CPU time 19.32 seconds
Started Sep 01 04:40:08 AM UTC 24
Finished Sep 01 04:40:34 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4007294528 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 274.prim_prince_test.4007294528
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/274.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/275.prim_prince_test.499380240
Short name T269
Test name
Test status
Simulation time 1182029216 ps
CPU time 21.01 seconds
Started Sep 01 04:40:08 AM UTC 24
Finished Sep 01 04:40:36 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=499380240 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 275.prim_prince_test.499380240
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/275.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/276.prim_prince_test.1114775136
Short name T276
Test name
Test status
Simulation time 2121761171 ps
CPU time 37.77 seconds
Started Sep 01 04:40:09 AM UTC 24
Finished Sep 01 04:40:58 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1114775136 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 276.prim_prince_test.1114775136
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/276.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/277.prim_prince_test.1545990369
Short name T274
Test name
Test status
Simulation time 1528419855 ps
CPU time 26.86 seconds
Started Sep 01 04:40:11 AM UTC 24
Finished Sep 01 04:40:47 AM UTC 24
Peak memory 154580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1545990369 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 277.prim_prince_test.1545990369
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/277.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/278.prim_prince_test.1109425254
Short name T268
Test name
Test status
Simulation time 956737357 ps
CPU time 17.03 seconds
Started Sep 01 04:40:12 AM UTC 24
Finished Sep 01 04:40:35 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1109425254 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 278.prim_prince_test.1109425254
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/278.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/279.prim_prince_test.1619182372
Short name T273
Test name
Test status
Simulation time 1355656922 ps
CPU time 24.03 seconds
Started Sep 01 04:40:15 AM UTC 24
Finished Sep 01 04:40:46 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1619182372 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 279.prim_prince_test.1619182372
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/279.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/28.prim_prince_test.2195615955
Short name T43
Test name
Test status
Simulation time 3386827300 ps
CPU time 59.56 seconds
Started Sep 01 04:28:52 AM UTC 24
Finished Sep 01 04:30:09 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2195615955 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 28.prim_prince_test.2195615955
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/28.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/280.prim_prince_test.2370202032
Short name T291
Test name
Test status
Simulation time 3535454345 ps
CPU time 61.53 seconds
Started Sep 01 04:40:15 AM UTC 24
Finished Sep 01 04:41:34 AM UTC 24
Peak memory 156568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2370202032 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 280.prim_prince_test.2370202032
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/280.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/281.prim_prince_test.2661518371
Short name T287
Test name
Test status
Simulation time 3054137910 ps
CPU time 53.25 seconds
Started Sep 01 04:40:16 AM UTC 24
Finished Sep 01 04:41:25 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2661518371 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 281.prim_prince_test.2661518371
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/281.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/282.prim_prince_test.3040630077
Short name T284
Test name
Test status
Simulation time 2444994065 ps
CPU time 43.13 seconds
Started Sep 01 04:40:17 AM UTC 24
Finished Sep 01 04:41:13 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3040630077 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 282.prim_prince_test.3040630077
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/282.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/283.prim_prince_test.2731335994
Short name T285
Test name
Test status
Simulation time 1861288712 ps
CPU time 32.95 seconds
Started Sep 01 04:40:30 AM UTC 24
Finished Sep 01 04:41:13 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2731335994 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 283.prim_prince_test.2731335994
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/283.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/284.prim_prince_test.3433342690
Short name T289
Test name
Test status
Simulation time 2351474489 ps
CPU time 41.24 seconds
Started Sep 01 04:40:34 AM UTC 24
Finished Sep 01 04:41:28 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3433342690 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 284.prim_prince_test.3433342690
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/284.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/285.prim_prince_test.3588929620
Short name T295
Test name
Test status
Simulation time 3169752755 ps
CPU time 55.61 seconds
Started Sep 01 04:40:36 AM UTC 24
Finished Sep 01 04:41:48 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3588929620 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 285.prim_prince_test.3588929620
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/285.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/286.prim_prince_test.586846087
Short name T290
Test name
Test status
Simulation time 2438838735 ps
CPU time 43.17 seconds
Started Sep 01 04:40:37 AM UTC 24
Finished Sep 01 04:41:33 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=586846087 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 286.prim_prince_test.586846087
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/286.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/287.prim_prince_test.1482413419
Short name T279
Test name
Test status
Simulation time 1018128043 ps
CPU time 18.31 seconds
Started Sep 01 04:40:38 AM UTC 24
Finished Sep 01 04:41:02 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1482413419 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 287.prim_prince_test.1482413419
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/287.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/288.prim_prince_test.1740870363
Short name T294
Test name
Test status
Simulation time 2950215356 ps
CPU time 51.79 seconds
Started Sep 01 04:40:38 AM UTC 24
Finished Sep 01 04:41:45 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1740870363 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 288.prim_prince_test.1740870363
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/288.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/289.prim_prince_test.3869954278
Short name T288
Test name
Test status
Simulation time 1851790539 ps
CPU time 32.66 seconds
Started Sep 01 04:40:45 AM UTC 24
Finished Sep 01 04:41:27 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3869954278 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 289.prim_prince_test.3869954278
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/289.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/29.prim_prince_test.3849588709
Short name T31
Test name
Test status
Simulation time 2028900020 ps
CPU time 36.64 seconds
Started Sep 01 04:28:54 AM UTC 24
Finished Sep 01 04:29:41 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3849588709 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 29.prim_prince_test.3849588709
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/29.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/290.prim_prince_test.63188196
Short name T286
Test name
Test status
Simulation time 1546657268 ps
CPU time 27.29 seconds
Started Sep 01 04:40:47 AM UTC 24
Finished Sep 01 04:41:23 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=63188196 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 290.prim_prince_test.63188196
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/290.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/291.prim_prince_test.3505315099
Short name T281
Test name
Test status
Simulation time 818457275 ps
CPU time 14.71 seconds
Started Sep 01 04:40:47 AM UTC 24
Finished Sep 01 04:41:07 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3505315099 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 291.prim_prince_test.3505315099
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/291.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/292.prim_prince_test.4004977890
Short name T306
Test name
Test status
Simulation time 3484560256 ps
CPU time 60.97 seconds
Started Sep 01 04:40:51 AM UTC 24
Finished Sep 01 04:42:10 AM UTC 24
Peak memory 156524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4004977890 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 292.prim_prince_test.4004977890
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/292.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/293.prim_prince_test.3858530267
Short name T292
Test name
Test status
Simulation time 1666998437 ps
CPU time 29.43 seconds
Started Sep 01 04:41:00 AM UTC 24
Finished Sep 01 04:41:38 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3858530267 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 293.prim_prince_test.3858530267
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/293.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/294.prim_prince_test.3757122101
Short name T293
Test name
Test status
Simulation time 1777808557 ps
CPU time 31.74 seconds
Started Sep 01 04:41:00 AM UTC 24
Finished Sep 01 04:41:41 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3757122101 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 294.prim_prince_test.3757122101
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/294.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/295.prim_prince_test.112462044
Short name T297
Test name
Test status
Simulation time 2290663041 ps
CPU time 40.08 seconds
Started Sep 01 04:41:02 AM UTC 24
Finished Sep 01 04:41:54 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=112462044 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 295.prim_prince_test.112462044
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/295.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/296.prim_prince_test.1112291327
Short name T296
Test name
Test status
Simulation time 1994780301 ps
CPU time 35.32 seconds
Started Sep 01 04:41:03 AM UTC 24
Finished Sep 01 04:41:49 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1112291327 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 296.prim_prince_test.1112291327
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/296.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/297.prim_prince_test.643122959
Short name T304
Test name
Test status
Simulation time 2672125000 ps
CPU time 47.38 seconds
Started Sep 01 04:41:05 AM UTC 24
Finished Sep 01 04:42:06 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=643122959 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 297.prim_prince_test.643122959
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/297.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/298.prim_prince_test.2272576663
Short name T303
Test name
Test status
Simulation time 2565506482 ps
CPU time 44.85 seconds
Started Sep 01 04:41:07 AM UTC 24
Finished Sep 01 04:42:05 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2272576663 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 298.prim_prince_test.2272576663
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/298.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/299.prim_prince_test.1987185975
Short name T299
Test name
Test status
Simulation time 2133379564 ps
CPU time 37.32 seconds
Started Sep 01 04:41:09 AM UTC 24
Finished Sep 01 04:41:58 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1987185975 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 299.prim_prince_test.1987185975
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/299.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/3.prim_prince_test.3575768797
Short name T1
Test name
Test status
Simulation time 1012748794 ps
CPU time 18.74 seconds
Started Sep 01 04:27:53 AM UTC 24
Finished Sep 01 04:28:17 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3575768797 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 3.prim_prince_test.3575768797
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/3.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/30.prim_prince_test.4132224989
Short name T38
Test name
Test status
Simulation time 2778112389 ps
CPU time 49.06 seconds
Started Sep 01 04:28:57 AM UTC 24
Finished Sep 01 04:30:00 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4132224989 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 30.prim_prince_test.4132224989
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/30.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/300.prim_prince_test.922083692
Short name T308
Test name
Test status
Simulation time 3170468451 ps
CPU time 55.29 seconds
Started Sep 01 04:41:09 AM UTC 24
Finished Sep 01 04:42:21 AM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=922083692 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 300.prim_prince_test.922083692
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/300.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/301.prim_prince_test.2971175282
Short name T312
Test name
Test status
Simulation time 3600655295 ps
CPU time 64.01 seconds
Started Sep 01 04:41:14 AM UTC 24
Finished Sep 01 04:42:36 AM UTC 24
Peak memory 156524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2971175282 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 301.prim_prince_test.2971175282
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/301.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/302.prim_prince_test.3664728383
Short name T301
Test name
Test status
Simulation time 2121600555 ps
CPU time 37.27 seconds
Started Sep 01 04:41:15 AM UTC 24
Finished Sep 01 04:42:03 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3664728383 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 302.prim_prince_test.3664728383
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/302.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/303.prim_prince_test.2826324109
Short name T298
Test name
Test status
Simulation time 1357998978 ps
CPU time 23.99 seconds
Started Sep 01 04:41:24 AM UTC 24
Finished Sep 01 04:41:55 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2826324109 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 303.prim_prince_test.2826324109
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/303.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/304.prim_prince_test.2685930104
Short name T302
Test name
Test status
Simulation time 1615650677 ps
CPU time 28.48 seconds
Started Sep 01 04:41:26 AM UTC 24
Finished Sep 01 04:42:03 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2685930104 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 304.prim_prince_test.2685930104
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/304.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/305.prim_prince_test.3820589079
Short name T305
Test name
Test status
Simulation time 1687909292 ps
CPU time 29.67 seconds
Started Sep 01 04:41:28 AM UTC 24
Finished Sep 01 04:42:07 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3820589079 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 305.prim_prince_test.3820589079
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/305.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/306.prim_prince_test.2809579463
Short name T316
Test name
Test status
Simulation time 3364883178 ps
CPU time 58.51 seconds
Started Sep 01 04:41:29 AM UTC 24
Finished Sep 01 04:42:45 AM UTC 24
Peak memory 156116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2809579463 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 306.prim_prince_test.2809579463
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/306.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/307.prim_prince_test.1608731405
Short name T315
Test name
Test status
Simulation time 3023964878 ps
CPU time 53.13 seconds
Started Sep 01 04:41:33 AM UTC 24
Finished Sep 01 04:42:42 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1608731405 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 307.prim_prince_test.1608731405
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/307.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/308.prim_prince_test.3464142673
Short name T311
Test name
Test status
Simulation time 2628042030 ps
CPU time 45.61 seconds
Started Sep 01 04:41:35 AM UTC 24
Finished Sep 01 04:42:35 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3464142673 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 308.prim_prince_test.3464142673
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/308.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/309.prim_prince_test.128441621
Short name T300
Test name
Test status
Simulation time 1008365125 ps
CPU time 18.05 seconds
Started Sep 01 04:41:39 AM UTC 24
Finished Sep 01 04:42:03 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=128441621 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 309.prim_prince_test.128441621
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/309.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/31.prim_prince_test.918419747
Short name T28
Test name
Test status
Simulation time 1582077933 ps
CPU time 28.84 seconds
Started Sep 01 04:28:58 AM UTC 24
Finished Sep 01 04:29:35 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=918419747 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 31.prim_prince_test.918419747
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/31.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/310.prim_prince_test.254337524
Short name T307
Test name
Test status
Simulation time 1474509635 ps
CPU time 26.04 seconds
Started Sep 01 04:41:42 AM UTC 24
Finished Sep 01 04:42:16 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=254337524 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 310.prim_prince_test.254337524
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/310.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/311.prim_prince_test.1194453702
Short name T314
Test name
Test status
Simulation time 2299238275 ps
CPU time 40.54 seconds
Started Sep 01 04:41:46 AM UTC 24
Finished Sep 01 04:42:39 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1194453702 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 311.prim_prince_test.1194453702
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/311.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/312.prim_prince_test.1730398372
Short name T313
Test name
Test status
Simulation time 2124819851 ps
CPU time 37.11 seconds
Started Sep 01 04:41:49 AM UTC 24
Finished Sep 01 04:42:38 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1730398372 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 312.prim_prince_test.1730398372
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/312.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/313.prim_prince_test.3165213760
Short name T317
Test name
Test status
Simulation time 2529344835 ps
CPU time 43.85 seconds
Started Sep 01 04:41:50 AM UTC 24
Finished Sep 01 04:42:47 AM UTC 24
Peak memory 154640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3165213760 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 313.prim_prince_test.3165213760
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/313.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/314.prim_prince_test.2770531978
Short name T329
Test name
Test status
Simulation time 3651905052 ps
CPU time 64.66 seconds
Started Sep 01 04:41:54 AM UTC 24
Finished Sep 01 04:43:18 AM UTC 24
Peak memory 156568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2770531978 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 314.prim_prince_test.2770531978
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/314.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/315.prim_prince_test.2511409065
Short name T309
Test name
Test status
Simulation time 1400732016 ps
CPU time 24.45 seconds
Started Sep 01 04:41:57 AM UTC 24
Finished Sep 01 04:42:29 AM UTC 24
Peak memory 154572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2511409065 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 315.prim_prince_test.2511409065
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/315.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/316.prim_prince_test.1483972774
Short name T319
Test name
Test status
Simulation time 2476028451 ps
CPU time 43.04 seconds
Started Sep 01 04:41:59 AM UTC 24
Finished Sep 01 04:42:55 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1483972774 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 316.prim_prince_test.1483972774
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/316.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/317.prim_prince_test.2793814756
Short name T332
Test name
Test status
Simulation time 3510842062 ps
CPU time 61.29 seconds
Started Sep 01 04:42:04 AM UTC 24
Finished Sep 01 04:43:23 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2793814756 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 317.prim_prince_test.2793814756
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/317.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/318.prim_prince_test.3791536272
Short name T323
Test name
Test status
Simulation time 3022063779 ps
CPU time 52.33 seconds
Started Sep 01 04:42:04 AM UTC 24
Finished Sep 01 04:43:12 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3791536272 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 318.prim_prince_test.3791536272
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/318.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/319.prim_prince_test.474176857
Short name T310
Test name
Test status
Simulation time 1111501211 ps
CPU time 19.72 seconds
Started Sep 01 04:42:04 AM UTC 24
Finished Sep 01 04:42:30 AM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=474176857 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 319.prim_prince_test.474176857
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/319.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/32.prim_prince_test.3659229038
Short name T29
Test name
Test status
Simulation time 1453838267 ps
CPU time 25.88 seconds
Started Sep 01 04:29:02 AM UTC 24
Finished Sep 01 04:29:35 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3659229038 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 32.prim_prince_test.3659229038
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/32.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/320.prim_prince_test.3991106676
Short name T326
Test name
Test status
Simulation time 3052772008 ps
CPU time 53.23 seconds
Started Sep 01 04:42:06 AM UTC 24
Finished Sep 01 04:43:15 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3991106676 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 320.prim_prince_test.3991106676
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/320.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/321.prim_prince_test.2786001366
Short name T322
Test name
Test status
Simulation time 2564589165 ps
CPU time 44.66 seconds
Started Sep 01 04:42:07 AM UTC 24
Finished Sep 01 04:43:05 AM UTC 24
Peak memory 156176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2786001366 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 321.prim_prince_test.2786001366
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/321.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/322.prim_prince_test.2047790084
Short name T330
Test name
Test status
Simulation time 3120388483 ps
CPU time 54.6 seconds
Started Sep 01 04:42:07 AM UTC 24
Finished Sep 01 04:43:18 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2047790084 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 322.prim_prince_test.2047790084
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/322.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/323.prim_prince_test.2049061222
Short name T324
Test name
Test status
Simulation time 2738088449 ps
CPU time 48.44 seconds
Started Sep 01 04:42:11 AM UTC 24
Finished Sep 01 04:43:13 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2049061222 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 323.prim_prince_test.2049061222
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/323.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/324.prim_prince_test.1650754580
Short name T331
Test name
Test status
Simulation time 2728157161 ps
CPU time 48.31 seconds
Started Sep 01 04:42:17 AM UTC 24
Finished Sep 01 04:43:19 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1650754580 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 324.prim_prince_test.1650754580
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/324.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/325.prim_prince_test.722104667
Short name T318
Test name
Test status
Simulation time 1131517759 ps
CPU time 20.15 seconds
Started Sep 01 04:42:22 AM UTC 24
Finished Sep 01 04:42:49 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=722104667 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 325.prim_prince_test.722104667
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/325.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/326.prim_prince_test.2120276205
Short name T320
Test name
Test status
Simulation time 1264767515 ps
CPU time 22.23 seconds
Started Sep 01 04:42:29 AM UTC 24
Finished Sep 01 04:42:59 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2120276205 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 326.prim_prince_test.2120276205
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/326.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/327.prim_prince_test.401780309
Short name T335
Test name
Test status
Simulation time 3153269142 ps
CPU time 54.75 seconds
Started Sep 01 04:42:31 AM UTC 24
Finished Sep 01 04:43:43 AM UTC 24
Peak memory 156532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=401780309 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 327.prim_prince_test.401780309
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/327.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/328.prim_prince_test.2319725940
Short name T321
Test name
Test status
Simulation time 1213197666 ps
CPU time 21.79 seconds
Started Sep 01 04:42:36 AM UTC 24
Finished Sep 01 04:43:05 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2319725940 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 328.prim_prince_test.2319725940
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/328.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/329.prim_prince_test.4123425758
Short name T333
Test name
Test status
Simulation time 2120089101 ps
CPU time 36.88 seconds
Started Sep 01 04:42:38 AM UTC 24
Finished Sep 01 04:43:26 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4123425758 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 329.prim_prince_test.4123425758
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/329.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/33.prim_prince_test.2594895304
Short name T32
Test name
Test status
Simulation time 1841016176 ps
CPU time 32.62 seconds
Started Sep 01 04:29:02 AM UTC 24
Finished Sep 01 04:29:44 AM UTC 24
Peak memory 154588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2594895304 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 33.prim_prince_test.2594895304
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/33.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/330.prim_prince_test.799705187
Short name T328
Test name
Test status
Simulation time 1606081731 ps
CPU time 28.31 seconds
Started Sep 01 04:42:39 AM UTC 24
Finished Sep 01 04:43:16 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=799705187 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 330.prim_prince_test.799705187
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/330.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/331.prim_prince_test.896088613
Short name T337
Test name
Test status
Simulation time 2843715902 ps
CPU time 50.44 seconds
Started Sep 01 04:42:40 AM UTC 24
Finished Sep 01 04:43:45 AM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=896088613 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 331.prim_prince_test.896088613
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/331.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/332.prim_prince_test.2001364792
Short name T325
Test name
Test status
Simulation time 1360708882 ps
CPU time 23.98 seconds
Started Sep 01 04:42:43 AM UTC 24
Finished Sep 01 04:43:15 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2001364792 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 332.prim_prince_test.2001364792
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/332.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/333.prim_prince_test.1441961670
Short name T347
Test name
Test status
Simulation time 3693922089 ps
CPU time 64.57 seconds
Started Sep 01 04:42:46 AM UTC 24
Finished Sep 01 04:44:10 AM UTC 24
Peak memory 156512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1441961670 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 333.prim_prince_test.1441961670
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/333.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/334.prim_prince_test.3304867804
Short name T343
Test name
Test status
Simulation time 3320010195 ps
CPU time 57.82 seconds
Started Sep 01 04:42:48 AM UTC 24
Finished Sep 01 04:44:03 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3304867804 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 334.prim_prince_test.3304867804
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/334.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/335.prim_prince_test.1538142603
Short name T255
Test name
Test status
Simulation time 2336826292 ps
CPU time 40.9 seconds
Started Sep 01 04:42:49 AM UTC 24
Finished Sep 01 04:43:43 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1538142603 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 335.prim_prince_test.1538142603
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/335.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/336.prim_prince_test.1694276783
Short name T327
Test name
Test status
Simulation time 817910095 ps
CPU time 14.94 seconds
Started Sep 01 04:42:56 AM UTC 24
Finished Sep 01 04:43:16 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1694276783 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 336.prim_prince_test.1694276783
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/336.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/337.prim_prince_test.1445491898
Short name T346
Test name
Test status
Simulation time 3031794433 ps
CPU time 53.94 seconds
Started Sep 01 04:43:00 AM UTC 24
Finished Sep 01 04:44:10 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1445491898 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 337.prim_prince_test.1445491898
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/337.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/338.prim_prince_test.2544147934
Short name T334
Test name
Test status
Simulation time 941599236 ps
CPU time 16.98 seconds
Started Sep 01 04:43:06 AM UTC 24
Finished Sep 01 04:43:29 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2544147934 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 338.prim_prince_test.2544147934
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/338.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/339.prim_prince_test.3621763346
Short name T338
Test name
Test status
Simulation time 1794949428 ps
CPU time 32.09 seconds
Started Sep 01 04:43:06 AM UTC 24
Finished Sep 01 04:43:48 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3621763346 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 339.prim_prince_test.3621763346
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/339.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/34.prim_prince_test.219724571
Short name T34
Test name
Test status
Simulation time 1637939430 ps
CPU time 29.76 seconds
Started Sep 01 04:29:10 AM UTC 24
Finished Sep 01 04:29:48 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=219724571 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 34.prim_prince_test.219724571
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/34.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/340.prim_prince_test.2590314668
Short name T353
Test name
Test status
Simulation time 3393368842 ps
CPU time 59.22 seconds
Started Sep 01 04:43:13 AM UTC 24
Finished Sep 01 04:44:30 AM UTC 24
Peak memory 154648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2590314668 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 340.prim_prince_test.2590314668
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/340.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/341.prim_prince_test.3666186860
Short name T336
Test name
Test status
Simulation time 1225245090 ps
CPU time 22.15 seconds
Started Sep 01 04:43:14 AM UTC 24
Finished Sep 01 04:43:44 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3666186860 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 341.prim_prince_test.3666186860
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/341.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/342.prim_prince_test.3480389723
Short name T345
Test name
Test status
Simulation time 2241701472 ps
CPU time 40.24 seconds
Started Sep 01 04:43:16 AM UTC 24
Finished Sep 01 04:44:08 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3480389723 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 342.prim_prince_test.3480389723
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/342.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/343.prim_prince_test.4035459854
Short name T340
Test name
Test status
Simulation time 1729785515 ps
CPU time 30.35 seconds
Started Sep 01 04:43:17 AM UTC 24
Finished Sep 01 04:43:57 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4035459854 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 343.prim_prince_test.4035459854
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/343.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/344.prim_prince_test.3586536848
Short name T339
Test name
Test status
Simulation time 1342551800 ps
CPU time 23.99 seconds
Started Sep 01 04:43:17 AM UTC 24
Finished Sep 01 04:43:48 AM UTC 24
Peak memory 154584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3586536848 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 344.prim_prince_test.3586536848
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/344.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/345.prim_prince_test.2212017891
Short name T355
Test name
Test status
Simulation time 3425431534 ps
CPU time 59.33 seconds
Started Sep 01 04:43:17 AM UTC 24
Finished Sep 01 04:44:34 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2212017891 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 345.prim_prince_test.2212017891
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/345.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/346.prim_prince_test.1716871755
Short name T350
Test name
Test status
Simulation time 2824396958 ps
CPU time 49.87 seconds
Started Sep 01 04:43:19 AM UTC 24
Finished Sep 01 04:44:24 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1716871755 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 346.prim_prince_test.1716871755
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/346.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/347.prim_prince_test.2566430240
Short name T341
Test name
Test status
Simulation time 1740043415 ps
CPU time 30.48 seconds
Started Sep 01 04:43:19 AM UTC 24
Finished Sep 01 04:43:59 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2566430240 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 347.prim_prince_test.2566430240
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/347.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/348.prim_prince_test.3732960158
Short name T342
Test name
Test status
Simulation time 1744089998 ps
CPU time 30.3 seconds
Started Sep 01 04:43:20 AM UTC 24
Finished Sep 01 04:44:00 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3732960158 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 348.prim_prince_test.3732960158
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/348.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/349.prim_prince_test.2478933141
Short name T349
Test name
Test status
Simulation time 2437707997 ps
CPU time 43.26 seconds
Started Sep 01 04:43:25 AM UTC 24
Finished Sep 01 04:44:21 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2478933141 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 349.prim_prince_test.2478933141
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/349.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/35.prim_prince_test.2416648088
Short name T41
Test name
Test status
Simulation time 2464021394 ps
CPU time 43.32 seconds
Started Sep 01 04:29:11 AM UTC 24
Finished Sep 01 04:30:07 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2416648088 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 35.prim_prince_test.2416648088
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/35.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/350.prim_prince_test.352156885
Short name T354
Test name
Test status
Simulation time 2794737457 ps
CPU time 48.57 seconds
Started Sep 01 04:43:27 AM UTC 24
Finished Sep 01 04:44:30 AM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=352156885 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 350.prim_prince_test.352156885
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/350.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/351.prim_prince_test.3109620378
Short name T344
Test name
Test status
Simulation time 1499387266 ps
CPU time 26.3 seconds
Started Sep 01 04:43:30 AM UTC 24
Finished Sep 01 04:44:04 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3109620378 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 351.prim_prince_test.3109620378
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/351.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/352.prim_prince_test.3106928472
Short name T348
Test name
Test status
Simulation time 1178501429 ps
CPU time 21.16 seconds
Started Sep 01 04:43:43 AM UTC 24
Finished Sep 01 04:44:11 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3106928472 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 352.prim_prince_test.3106928472
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/352.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/353.prim_prince_test.2226768049
Short name T364
Test name
Test status
Simulation time 3267868865 ps
CPU time 57.49 seconds
Started Sep 01 04:43:44 AM UTC 24
Finished Sep 01 04:44:59 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2226768049 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 353.prim_prince_test.2226768049
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/353.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/354.prim_prince_test.556090505
Short name T358
Test name
Test status
Simulation time 2452745217 ps
CPU time 43.6 seconds
Started Sep 01 04:43:44 AM UTC 24
Finished Sep 01 04:44:41 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=556090505 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 354.prim_prince_test.556090505
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/354.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/355.prim_prince_test.971522870
Short name T362
Test name
Test status
Simulation time 3026984103 ps
CPU time 52.78 seconds
Started Sep 01 04:43:46 AM UTC 24
Finished Sep 01 04:44:55 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=971522870 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 355.prim_prince_test.971522870
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/355.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/356.prim_prince_test.2402381384
Short name T352
Test name
Test status
Simulation time 1757089528 ps
CPU time 31.12 seconds
Started Sep 01 04:43:49 AM UTC 24
Finished Sep 01 04:44:29 AM UTC 24
Peak memory 156060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2402381384 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 356.prim_prince_test.2402381384
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/356.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/357.prim_prince_test.942623
Short name T361
Test name
Test status
Simulation time 2710249711 ps
CPU time 48.03 seconds
Started Sep 01 04:43:50 AM UTC 24
Finished Sep 01 04:44:52 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=942623 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 357.prim_prince_test.942623
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/357.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/358.prim_prince_test.2670379347
Short name T356
Test name
Test status
Simulation time 1728562289 ps
CPU time 30.19 seconds
Started Sep 01 04:43:57 AM UTC 24
Finished Sep 01 04:44:37 AM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2670379347 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 358.prim_prince_test.2670379347
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/358.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/359.prim_prince_test.3192159039
Short name T351
Test name
Test status
Simulation time 1150173739 ps
CPU time 20.4 seconds
Started Sep 01 04:44:00 AM UTC 24
Finished Sep 01 04:44:27 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3192159039 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 359.prim_prince_test.3192159039
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/359.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/36.prim_prince_test.1866505767
Short name T40
Test name
Test status
Simulation time 2337651947 ps
CPU time 41.81 seconds
Started Sep 01 04:29:11 AM UTC 24
Finished Sep 01 04:30:05 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1866505767 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 36.prim_prince_test.1866505767
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/36.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/360.prim_prince_test.1400205451
Short name T357
Test name
Test status
Simulation time 1633824030 ps
CPU time 29.11 seconds
Started Sep 01 04:44:01 AM UTC 24
Finished Sep 01 04:44:40 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1400205451 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 360.prim_prince_test.1400205451
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/360.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/361.prim_prince_test.3724023780
Short name T363
Test name
Test status
Simulation time 2205920019 ps
CPU time 38.76 seconds
Started Sep 01 04:44:04 AM UTC 24
Finished Sep 01 04:44:55 AM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3724023780 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 361.prim_prince_test.3724023780
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/361.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/362.prim_prince_test.2580024741
Short name T366
Test name
Test status
Simulation time 2508906677 ps
CPU time 44.09 seconds
Started Sep 01 04:44:06 AM UTC 24
Finished Sep 01 04:45:03 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2580024741 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 362.prim_prince_test.2580024741
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/362.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/363.prim_prince_test.3765852229
Short name T370
Test name
Test status
Simulation time 3233758335 ps
CPU time 56.49 seconds
Started Sep 01 04:44:09 AM UTC 24
Finished Sep 01 04:45:22 AM UTC 24
Peak memory 154676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3765852229 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 363.prim_prince_test.3765852229
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/363.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/364.prim_prince_test.1669439026
Short name T375
Test name
Test status
Simulation time 3560416879 ps
CPU time 62.09 seconds
Started Sep 01 04:44:11 AM UTC 24
Finished Sep 01 04:45:32 AM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1669439026 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 364.prim_prince_test.1669439026
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/364.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/365.prim_prince_test.781031340
Short name T369
Test name
Test status
Simulation time 3067314496 ps
CPU time 53.75 seconds
Started Sep 01 04:44:11 AM UTC 24
Finished Sep 01 04:45:21 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=781031340 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 365.prim_prince_test.781031340
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/365.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/366.prim_prince_test.3203395389
Short name T376
Test name
Test status
Simulation time 3600848447 ps
CPU time 62.82 seconds
Started Sep 01 04:44:12 AM UTC 24
Finished Sep 01 04:45:34 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3203395389 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 366.prim_prince_test.3203395389
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/366.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/367.prim_prince_test.905295727
Short name T368
Test name
Test status
Simulation time 2444135575 ps
CPU time 42.9 seconds
Started Sep 01 04:44:21 AM UTC 24
Finished Sep 01 04:45:17 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=905295727 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 367.prim_prince_test.905295727
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/367.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/368.prim_prince_test.1662490238
Short name T360
Test name
Test status
Simulation time 1127702940 ps
CPU time 20.12 seconds
Started Sep 01 04:44:24 AM UTC 24
Finished Sep 01 04:44:51 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1662490238 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 368.prim_prince_test.1662490238
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/368.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/369.prim_prince_test.2262590000
Short name T367
Test name
Test status
Simulation time 1669924558 ps
CPU time 29.82 seconds
Started Sep 01 04:44:29 AM UTC 24
Finished Sep 01 04:45:08 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2262590000 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 369.prim_prince_test.2262590000
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/369.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/37.prim_prince_test.524001188
Short name T46
Test name
Test status
Simulation time 2716775176 ps
CPU time 48.43 seconds
Started Sep 01 04:29:13 AM UTC 24
Finished Sep 01 04:30:15 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=524001188 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 37.prim_prince_test.524001188
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/37.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/370.prim_prince_test.1759088405
Short name T359
Test name
Test status
Simulation time 762248713 ps
CPU time 13.82 seconds
Started Sep 01 04:44:30 AM UTC 24
Finished Sep 01 04:44:48 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1759088405 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 370.prim_prince_test.1759088405
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/370.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/371.prim_prince_test.4221950296
Short name T365
Test name
Test status
Simulation time 1273803684 ps
CPU time 22.64 seconds
Started Sep 01 04:44:31 AM UTC 24
Finished Sep 01 04:45:01 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4221950296 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 371.prim_prince_test.4221950296
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/371.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/372.prim_prince_test.2063086524
Short name T383
Test name
Test status
Simulation time 3731916324 ps
CPU time 64.92 seconds
Started Sep 01 04:44:31 AM UTC 24
Finished Sep 01 04:45:55 AM UTC 24
Peak memory 156532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2063086524 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 372.prim_prince_test.2063086524
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/372.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/373.prim_prince_test.1239590873
Short name T373
Test name
Test status
Simulation time 2207061536 ps
CPU time 39.39 seconds
Started Sep 01 04:44:34 AM UTC 24
Finished Sep 01 04:45:26 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1239590873 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 373.prim_prince_test.1239590873
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/373.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/374.prim_prince_test.2091605106
Short name T385
Test name
Test status
Simulation time 3570476788 ps
CPU time 61.93 seconds
Started Sep 01 04:44:37 AM UTC 24
Finished Sep 01 04:45:58 AM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2091605106 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 374.prim_prince_test.2091605106
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/374.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/375.prim_prince_test.552596390
Short name T371
Test name
Test status
Simulation time 1813465679 ps
CPU time 31.96 seconds
Started Sep 01 04:44:41 AM UTC 24
Finished Sep 01 04:45:23 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=552596390 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 375.prim_prince_test.552596390
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/375.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/376.prim_prince_test.661750352
Short name T374
Test name
Test status
Simulation time 2061370908 ps
CPU time 36.61 seconds
Started Sep 01 04:44:42 AM UTC 24
Finished Sep 01 04:45:30 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=661750352 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 376.prim_prince_test.661750352
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/376.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/377.prim_prince_test.2002616505
Short name T386
Test name
Test status
Simulation time 3064755367 ps
CPU time 53.95 seconds
Started Sep 01 04:44:49 AM UTC 24
Finished Sep 01 04:45:59 AM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2002616505 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 377.prim_prince_test.2002616505
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/377.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/378.prim_prince_test.3297615404
Short name T388
Test name
Test status
Simulation time 2991196682 ps
CPU time 52.18 seconds
Started Sep 01 04:44:52 AM UTC 24
Finished Sep 01 04:46:00 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3297615404 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 378.prim_prince_test.3297615404
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/378.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/379.prim_prince_test.3435159842
Short name T377
Test name
Test status
Simulation time 1777465349 ps
CPU time 31.76 seconds
Started Sep 01 04:44:53 AM UTC 24
Finished Sep 01 04:45:35 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3435159842 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 379.prim_prince_test.3435159842
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/379.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/38.prim_prince_test.1851030875
Short name T33
Test name
Test status
Simulation time 1281875499 ps
CPU time 23.48 seconds
Started Sep 01 04:29:14 AM UTC 24
Finished Sep 01 04:29:45 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1851030875 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 38.prim_prince_test.1851030875
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/38.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/380.prim_prince_test.4235905413
Short name T378
Test name
Test status
Simulation time 1880664729 ps
CPU time 32.82 seconds
Started Sep 01 04:44:56 AM UTC 24
Finished Sep 01 04:45:39 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4235905413 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 380.prim_prince_test.4235905413
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/380.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/381.prim_prince_test.3964696495
Short name T379
Test name
Test status
Simulation time 2098505844 ps
CPU time 37.21 seconds
Started Sep 01 04:44:56 AM UTC 24
Finished Sep 01 04:45:44 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3964696495 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 381.prim_prince_test.3964696495
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/381.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/382.prim_prince_test.1733343827
Short name T395
Test name
Test status
Simulation time 3422537727 ps
CPU time 59.44 seconds
Started Sep 01 04:45:00 AM UTC 24
Finished Sep 01 04:46:17 AM UTC 24
Peak memory 154676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1733343827 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 382.prim_prince_test.1733343827
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/382.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/383.prim_prince_test.2215243108
Short name T380
Test name
Test status
Simulation time 1929507265 ps
CPU time 34.47 seconds
Started Sep 01 04:45:02 AM UTC 24
Finished Sep 01 04:45:47 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2215243108 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 383.prim_prince_test.2215243108
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/383.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/384.prim_prince_test.2511297656
Short name T396
Test name
Test status
Simulation time 3502733841 ps
CPU time 61.53 seconds
Started Sep 01 04:45:04 AM UTC 24
Finished Sep 01 04:46:24 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2511297656 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 384.prim_prince_test.2511297656
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/384.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/385.prim_prince_test.3720378197
Short name T384
Test name
Test status
Simulation time 2132092060 ps
CPU time 37.57 seconds
Started Sep 01 04:45:08 AM UTC 24
Finished Sep 01 04:45:57 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3720378197 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 385.prim_prince_test.3720378197
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/385.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/386.prim_prince_test.3302545661
Short name T401
Test name
Test status
Simulation time 3491215048 ps
CPU time 60.51 seconds
Started Sep 01 04:45:18 AM UTC 24
Finished Sep 01 04:46:37 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3302545661 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 386.prim_prince_test.3302545661
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/386.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/387.prim_prince_test.2483412349
Short name T382
Test name
Test status
Simulation time 1419050341 ps
CPU time 24.96 seconds
Started Sep 01 04:45:22 AM UTC 24
Finished Sep 01 04:45:54 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2483412349 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 387.prim_prince_test.2483412349
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/387.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/388.prim_prince_test.3458627979
Short name T400
Test name
Test status
Simulation time 3195564933 ps
CPU time 55.57 seconds
Started Sep 01 04:45:23 AM UTC 24
Finished Sep 01 04:46:35 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3458627979 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 388.prim_prince_test.3458627979
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/388.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/389.prim_prince_test.3374280541
Short name T381
Test name
Test status
Simulation time 1209715109 ps
CPU time 21.32 seconds
Started Sep 01 04:45:24 AM UTC 24
Finished Sep 01 04:45:52 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3374280541 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 389.prim_prince_test.3374280541
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/389.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/39.prim_prince_test.2365153160
Short name T45
Test name
Test status
Simulation time 2612004848 ps
CPU time 47.01 seconds
Started Sep 01 04:29:14 AM UTC 24
Finished Sep 01 04:30:15 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2365153160 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 39.prim_prince_test.2365153160
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/39.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/390.prim_prince_test.2217651472
Short name T399
Test name
Test status
Simulation time 2953385856 ps
CPU time 51.51 seconds
Started Sep 01 04:45:27 AM UTC 24
Finished Sep 01 04:46:34 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2217651472 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 390.prim_prince_test.2217651472
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/390.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/391.prim_prince_test.3962938515
Short name T387
Test name
Test status
Simulation time 1265334429 ps
CPU time 22.27 seconds
Started Sep 01 04:45:30 AM UTC 24
Finished Sep 01 04:46:00 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3962938515 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 391.prim_prince_test.3962938515
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/391.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/392.prim_prince_test.3466143044
Short name T389
Test name
Test status
Simulation time 1715295376 ps
CPU time 30.22 seconds
Started Sep 01 04:45:32 AM UTC 24
Finished Sep 01 04:46:12 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3466143044 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 392.prim_prince_test.3466143044
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/392.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/393.prim_prince_test.1757101717
Short name T391
Test name
Test status
Simulation time 1631990304 ps
CPU time 28.81 seconds
Started Sep 01 04:45:34 AM UTC 24
Finished Sep 01 04:46:12 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1757101717 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 393.prim_prince_test.1757101717
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/393.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/394.prim_prince_test.2688035561
Short name T394
Test name
Test status
Simulation time 1785592461 ps
CPU time 31.3 seconds
Started Sep 01 04:45:36 AM UTC 24
Finished Sep 01 04:46:17 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2688035561 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 394.prim_prince_test.2688035561
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/394.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/395.prim_prince_test.2843174855
Short name T392
Test name
Test status
Simulation time 1521837746 ps
CPU time 26.96 seconds
Started Sep 01 04:45:40 AM UTC 24
Finished Sep 01 04:46:15 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2843174855 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 395.prim_prince_test.2843174855
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/395.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/396.prim_prince_test.2659798670
Short name T390
Test name
Test status
Simulation time 1153375169 ps
CPU time 20.4 seconds
Started Sep 01 04:45:45 AM UTC 24
Finished Sep 01 04:46:12 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2659798670 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 396.prim_prince_test.2659798670
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/396.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/397.prim_prince_test.3500695947
Short name T402
Test name
Test status
Simulation time 2300461037 ps
CPU time 40.26 seconds
Started Sep 01 04:45:48 AM UTC 24
Finished Sep 01 04:46:41 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3500695947 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 397.prim_prince_test.3500695947
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/397.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/398.prim_prince_test.1020965074
Short name T393
Test name
Test status
Simulation time 924692154 ps
CPU time 16.59 seconds
Started Sep 01 04:45:53 AM UTC 24
Finished Sep 01 04:46:15 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1020965074 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 398.prim_prince_test.1020965074
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/398.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/399.prim_prince_test.3232730596
Short name T404
Test name
Test status
Simulation time 2252201459 ps
CPU time 39.44 seconds
Started Sep 01 04:45:56 AM UTC 24
Finished Sep 01 04:46:47 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3232730596 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 399.prim_prince_test.3232730596
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/399.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/4.prim_prince_test.2519053056
Short name T9
Test name
Test status
Simulation time 2421263292 ps
CPU time 43.16 seconds
Started Sep 01 04:27:53 AM UTC 24
Finished Sep 01 04:28:48 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2519053056 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 4.prim_prince_test.2519053056
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/4.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/40.prim_prince_test.899062185
Short name T27
Test name
Test status
Simulation time 751098903 ps
CPU time 13.65 seconds
Started Sep 01 04:29:16 AM UTC 24
Finished Sep 01 04:29:34 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=899062185 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 40.prim_prince_test.899062185
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/40.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/400.prim_prince_test.837788570
Short name T412
Test name
Test status
Simulation time 3498043155 ps
CPU time 61.64 seconds
Started Sep 01 04:45:57 AM UTC 24
Finished Sep 01 04:47:17 AM UTC 24
Peak memory 156572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=837788570 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 400.prim_prince_test.837788570
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/400.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/401.prim_prince_test.467252497
Short name T415
Test name
Test status
Simulation time 3569774901 ps
CPU time 62.75 seconds
Started Sep 01 04:45:58 AM UTC 24
Finished Sep 01 04:47:19 AM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=467252497 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 401.prim_prince_test.467252497
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/401.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/402.prim_prince_test.762165532
Short name T398
Test name
Test status
Simulation time 1450069278 ps
CPU time 25.67 seconds
Started Sep 01 04:45:59 AM UTC 24
Finished Sep 01 04:46:33 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=762165532 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 402.prim_prince_test.762165532
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/402.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/403.prim_prince_test.1068075623
Short name T397
Test name
Test status
Simulation time 1314331778 ps
CPU time 23.24 seconds
Started Sep 01 04:46:00 AM UTC 24
Finished Sep 01 04:46:31 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1068075623 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 403.prim_prince_test.1068075623
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/403.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/404.prim_prince_test.3190831352
Short name T405
Test name
Test status
Simulation time 2221623565 ps
CPU time 39.1 seconds
Started Sep 01 04:46:00 AM UTC 24
Finished Sep 01 04:46:51 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3190831352 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 404.prim_prince_test.3190831352
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/404.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/405.prim_prince_test.2141030707
Short name T410
Test name
Test status
Simulation time 3247298565 ps
CPU time 56.42 seconds
Started Sep 01 04:46:01 AM UTC 24
Finished Sep 01 04:47:15 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2141030707 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 405.prim_prince_test.2141030707
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/405.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/406.prim_prince_test.1340699115
Short name T416
Test name
Test status
Simulation time 3101251039 ps
CPU time 54.32 seconds
Started Sep 01 04:46:13 AM UTC 24
Finished Sep 01 04:47:23 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1340699115 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 406.prim_prince_test.1340699115
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/406.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/407.prim_prince_test.1624563194
Short name T406
Test name
Test status
Simulation time 1901177127 ps
CPU time 33.12 seconds
Started Sep 01 04:46:13 AM UTC 24
Finished Sep 01 04:46:56 AM UTC 24
Peak memory 154588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1624563194 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 407.prim_prince_test.1624563194
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/407.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/408.prim_prince_test.719899732
Short name T403
Test name
Test status
Simulation time 1170233119 ps
CPU time 20.74 seconds
Started Sep 01 04:46:14 AM UTC 24
Finished Sep 01 04:46:41 AM UTC 24
Peak memory 156120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=719899732 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 408.prim_prince_test.719899732
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/408.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/409.prim_prince_test.1133236413
Short name T422
Test name
Test status
Simulation time 3610660362 ps
CPU time 62.92 seconds
Started Sep 01 04:46:16 AM UTC 24
Finished Sep 01 04:47:38 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1133236413 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 409.prim_prince_test.1133236413
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/409.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/41.prim_prince_test.3869725136
Short name T35
Test name
Test status
Simulation time 1335259965 ps
CPU time 23.81 seconds
Started Sep 01 04:29:18 AM UTC 24
Finished Sep 01 04:29:50 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3869725136 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 41.prim_prince_test.3869725136
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/41.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/410.prim_prince_test.1292920874
Short name T421
Test name
Test status
Simulation time 3572741413 ps
CPU time 62.03 seconds
Started Sep 01 04:46:16 AM UTC 24
Finished Sep 01 04:47:37 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1292920874 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 410.prim_prince_test.1292920874
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/410.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/411.prim_prince_test.2728937548
Short name T423
Test name
Test status
Simulation time 3591430876 ps
CPU time 62.06 seconds
Started Sep 01 04:46:18 AM UTC 24
Finished Sep 01 04:47:38 AM UTC 24
Peak memory 154652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2728937548 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 411.prim_prince_test.2728937548
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/411.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/412.prim_prince_test.34263733
Short name T372
Test name
Test status
Simulation time 3388633327 ps
CPU time 59.62 seconds
Started Sep 01 04:46:18 AM UTC 24
Finished Sep 01 04:47:35 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34263733 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 412.prim_prince_test.34263733
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/412.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/413.prim_prince_test.1597745226
Short name T411
Test name
Test status
Simulation time 2198290654 ps
CPU time 38.06 seconds
Started Sep 01 04:46:25 AM UTC 24
Finished Sep 01 04:47:15 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1597745226 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 413.prim_prince_test.1597745226
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/413.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/414.prim_prince_test.700040484
Short name T420
Test name
Test status
Simulation time 2591995159 ps
CPU time 45.14 seconds
Started Sep 01 04:46:32 AM UTC 24
Finished Sep 01 04:47:31 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=700040484 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 414.prim_prince_test.700040484
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/414.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/415.prim_prince_test.3424318635
Short name T414
Test name
Test status
Simulation time 1830519348 ps
CPU time 32.57 seconds
Started Sep 01 04:46:34 AM UTC 24
Finished Sep 01 04:47:17 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3424318635 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 415.prim_prince_test.3424318635
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/415.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/416.prim_prince_test.1255506064
Short name T409
Test name
Test status
Simulation time 1651441537 ps
CPU time 29.04 seconds
Started Sep 01 04:46:35 AM UTC 24
Finished Sep 01 04:47:14 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1255506064 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 416.prim_prince_test.1255506064
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/416.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/417.prim_prince_test.1855215276
Short name T425
Test name
Test status
Simulation time 3155147152 ps
CPU time 54.78 seconds
Started Sep 01 04:46:37 AM UTC 24
Finished Sep 01 04:47:48 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1855215276 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 417.prim_prince_test.1855215276
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/417.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/418.prim_prince_test.2711661224
Short name T417
Test name
Test status
Simulation time 2056943329 ps
CPU time 35.56 seconds
Started Sep 01 04:46:38 AM UTC 24
Finished Sep 01 04:47:24 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2711661224 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 418.prim_prince_test.2711661224
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/418.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/419.prim_prince_test.3710476659
Short name T413
Test name
Test status
Simulation time 2217024739 ps
CPU time 38.52 seconds
Started Sep 01 04:46:42 AM UTC 24
Finished Sep 01 04:47:33 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3710476659 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 419.prim_prince_test.3710476659
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/419.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/42.prim_prince_test.1769301320
Short name T47
Test name
Test status
Simulation time 2289339899 ps
CPU time 41.06 seconds
Started Sep 01 04:29:22 AM UTC 24
Finished Sep 01 04:30:15 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1769301320 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 42.prim_prince_test.1769301320
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/42.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/420.prim_prince_test.3599151587
Short name T407
Test name
Test status
Simulation time 1017953059 ps
CPU time 18.19 seconds
Started Sep 01 04:46:42 AM UTC 24
Finished Sep 01 04:47:06 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3599151587 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 420.prim_prince_test.3599151587
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/420.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/421.prim_prince_test.4002182089
Short name T408
Test name
Test status
Simulation time 934745276 ps
CPU time 16.76 seconds
Started Sep 01 04:46:48 AM UTC 24
Finished Sep 01 04:47:11 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4002182089 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 421.prim_prince_test.4002182089
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/421.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/422.prim_prince_test.3919869300
Short name T418
Test name
Test status
Simulation time 1517907003 ps
CPU time 26.58 seconds
Started Sep 01 04:46:52 AM UTC 24
Finished Sep 01 04:47:28 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3919869300 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 422.prim_prince_test.3919869300
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/422.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/423.prim_prince_test.3965992061
Short name T419
Test name
Test status
Simulation time 1364911892 ps
CPU time 23.83 seconds
Started Sep 01 04:46:58 AM UTC 24
Finished Sep 01 04:47:29 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3965992061 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 423.prim_prince_test.3965992061
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/423.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/424.prim_prince_test.761714225
Short name T432
Test name
Test status
Simulation time 2944643719 ps
CPU time 51.27 seconds
Started Sep 01 04:47:07 AM UTC 24
Finished Sep 01 04:48:14 AM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=761714225 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 424.prim_prince_test.761714225
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/424.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/425.prim_prince_test.2980562439
Short name T431
Test name
Test status
Simulation time 2640846791 ps
CPU time 46.43 seconds
Started Sep 01 04:47:12 AM UTC 24
Finished Sep 01 04:48:12 AM UTC 24
Peak memory 156568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2980562439 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 425.prim_prince_test.2980562439
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/425.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/426.prim_prince_test.2571390331
Short name T437
Test name
Test status
Simulation time 3038636945 ps
CPU time 52.93 seconds
Started Sep 01 04:47:14 AM UTC 24
Finished Sep 01 04:48:23 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2571390331 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 426.prim_prince_test.2571390331
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/426.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/427.prim_prince_test.2432783292
Short name T434
Test name
Test status
Simulation time 2907400024 ps
CPU time 50.93 seconds
Started Sep 01 04:47:15 AM UTC 24
Finished Sep 01 04:48:22 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2432783292 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 427.prim_prince_test.2432783292
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/427.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/428.prim_prince_test.77761185
Short name T436
Test name
Test status
Simulation time 2967579612 ps
CPU time 51.75 seconds
Started Sep 01 04:47:15 AM UTC 24
Finished Sep 01 04:48:23 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=77761185 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 428.prim_prince_test.77761185
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/428.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/429.prim_prince_test.30204405
Short name T424
Test name
Test status
Simulation time 914020670 ps
CPU time 16.46 seconds
Started Sep 01 04:47:18 AM UTC 24
Finished Sep 01 04:47:40 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30204405 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 429.prim_prince_test.30204405
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/429.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/43.prim_prince_test.4274557944
Short name T53
Test name
Test status
Simulation time 3255944818 ps
CPU time 57.51 seconds
Started Sep 01 04:29:26 AM UTC 24
Finished Sep 01 04:30:40 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4274557944 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 43.prim_prince_test.4274557944
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/43.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/430.prim_prince_test.3766787972
Short name T428
Test name
Test status
Simulation time 1914724595 ps
CPU time 33.61 seconds
Started Sep 01 04:47:18 AM UTC 24
Finished Sep 01 04:48:02 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3766787972 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 430.prim_prince_test.3766787972
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/430.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/431.prim_prince_test.2055761270
Short name T426
Test name
Test status
Simulation time 1499295755 ps
CPU time 26.38 seconds
Started Sep 01 04:47:20 AM UTC 24
Finished Sep 01 04:47:55 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2055761270 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 431.prim_prince_test.2055761270
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/431.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/432.prim_prince_test.3995176892
Short name T427
Test name
Test status
Simulation time 1464238720 ps
CPU time 25.64 seconds
Started Sep 01 04:47:24 AM UTC 24
Finished Sep 01 04:47:58 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3995176892 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 432.prim_prince_test.3995176892
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/432.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/433.prim_prince_test.1190031808
Short name T439
Test name
Test status
Simulation time 3209112345 ps
CPU time 55.82 seconds
Started Sep 01 04:47:25 AM UTC 24
Finished Sep 01 04:48:38 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1190031808 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 433.prim_prince_test.1190031808
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/433.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/434.prim_prince_test.70797075
Short name T435
Test name
Test status
Simulation time 2370642135 ps
CPU time 41.49 seconds
Started Sep 01 04:47:28 AM UTC 24
Finished Sep 01 04:48:23 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=70797075 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 434.prim_prince_test.70797075
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/434.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/435.prim_prince_test.909656683
Short name T445
Test name
Test status
Simulation time 3690020061 ps
CPU time 63.89 seconds
Started Sep 01 04:47:30 AM UTC 24
Finished Sep 01 04:48:53 AM UTC 24
Peak memory 156576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=909656683 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 435.prim_prince_test.909656683
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/435.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/436.prim_prince_test.74384931
Short name T429
Test name
Test status
Simulation time 1435881217 ps
CPU time 25.4 seconds
Started Sep 01 04:47:32 AM UTC 24
Finished Sep 01 04:48:05 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=74384931 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 436.prim_prince_test.74384931
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/436.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/437.prim_prince_test.2807309730
Short name T443
Test name
Test status
Simulation time 3422500176 ps
CPU time 59.2 seconds
Started Sep 01 04:47:33 AM UTC 24
Finished Sep 01 04:48:50 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2807309730 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 437.prim_prince_test.2807309730
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/437.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/438.prim_prince_test.789696007
Short name T441
Test name
Test status
Simulation time 3201262395 ps
CPU time 55.69 seconds
Started Sep 01 04:47:36 AM UTC 24
Finished Sep 01 04:48:49 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=789696007 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 438.prim_prince_test.789696007
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/438.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/439.prim_prince_test.2754270818
Short name T438
Test name
Test status
Simulation time 2120451229 ps
CPU time 37.23 seconds
Started Sep 01 04:47:38 AM UTC 24
Finished Sep 01 04:48:27 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2754270818 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 439.prim_prince_test.2754270818
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/439.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/44.prim_prince_test.4213022782
Short name T44
Test name
Test status
Simulation time 1772588551 ps
CPU time 31.38 seconds
Started Sep 01 04:29:31 AM UTC 24
Finished Sep 01 04:30:11 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4213022782 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 44.prim_prince_test.4213022782
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/44.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/440.prim_prince_test.3447349051
Short name T433
Test name
Test status
Simulation time 1761213004 ps
CPU time 31.01 seconds
Started Sep 01 04:47:40 AM UTC 24
Finished Sep 01 04:48:20 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3447349051 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 440.prim_prince_test.3447349051
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/440.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/441.prim_prince_test.1957393899
Short name T430
Test name
Test status
Simulation time 1258131726 ps
CPU time 22.2 seconds
Started Sep 01 04:47:40 AM UTC 24
Finished Sep 01 04:48:09 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1957393899 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 441.prim_prince_test.1957393899
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/441.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/442.prim_prince_test.1329996362
Short name T447
Test name
Test status
Simulation time 3266347086 ps
CPU time 57.04 seconds
Started Sep 01 04:47:41 AM UTC 24
Finished Sep 01 04:48:55 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1329996362 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 442.prim_prince_test.1329996362
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/442.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/443.prim_prince_test.3513050132
Short name T452
Test name
Test status
Simulation time 3557687896 ps
CPU time 62.18 seconds
Started Sep 01 04:47:49 AM UTC 24
Finished Sep 01 04:49:10 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3513050132 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 443.prim_prince_test.3513050132
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/443.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/444.prim_prince_test.2876108161
Short name T448
Test name
Test status
Simulation time 2638118468 ps
CPU time 46.2 seconds
Started Sep 01 04:47:55 AM UTC 24
Finished Sep 01 04:48:55 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2876108161 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 444.prim_prince_test.2876108161
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/444.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/445.prim_prince_test.1606497689
Short name T440
Test name
Test status
Simulation time 1819211427 ps
CPU time 32.15 seconds
Started Sep 01 04:47:58 AM UTC 24
Finished Sep 01 04:48:41 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1606497689 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 445.prim_prince_test.1606497689
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/445.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/446.prim_prince_test.3512753007
Short name T451
Test name
Test status
Simulation time 2866637215 ps
CPU time 49.9 seconds
Started Sep 01 04:48:03 AM UTC 24
Finished Sep 01 04:49:08 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3512753007 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 446.prim_prince_test.3512753007
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/446.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/447.prim_prince_test.1676367719
Short name T456
Test name
Test status
Simulation time 3721576798 ps
CPU time 65.25 seconds
Started Sep 01 04:48:06 AM UTC 24
Finished Sep 01 04:49:30 AM UTC 24
Peak memory 156524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1676367719 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 447.prim_prince_test.1676367719
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/447.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/448.prim_prince_test.2978745276
Short name T449
Test name
Test status
Simulation time 2084947178 ps
CPU time 36.22 seconds
Started Sep 01 04:48:10 AM UTC 24
Finished Sep 01 04:48:57 AM UTC 24
Peak memory 154584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2978745276 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 448.prim_prince_test.2978745276
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/448.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/449.prim_prince_test.1942649501
Short name T453
Test name
Test status
Simulation time 2755426599 ps
CPU time 47.93 seconds
Started Sep 01 04:48:13 AM UTC 24
Finished Sep 01 04:49:16 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1942649501 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 449.prim_prince_test.1942649501
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/449.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/45.prim_prince_test.2097216097
Short name T37
Test name
Test status
Simulation time 989803711 ps
CPU time 17.84 seconds
Started Sep 01 04:29:36 AM UTC 24
Finished Sep 01 04:29:59 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2097216097 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 45.prim_prince_test.2097216097
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/45.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/450.prim_prince_test.834804181
Short name T455
Test name
Test status
Simulation time 3004822469 ps
CPU time 51.81 seconds
Started Sep 01 04:48:14 AM UTC 24
Finished Sep 01 04:49:22 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=834804181 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 450.prim_prince_test.834804181
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/450.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/451.prim_prince_test.3366309544
Short name T442
Test name
Test status
Simulation time 1199004612 ps
CPU time 21.1 seconds
Started Sep 01 04:48:22 AM UTC 24
Finished Sep 01 04:48:50 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3366309544 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 451.prim_prince_test.3366309544
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/451.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/452.prim_prince_test.210159126
Short name T444
Test name
Test status
Simulation time 1154305135 ps
CPU time 20.57 seconds
Started Sep 01 04:48:23 AM UTC 24
Finished Sep 01 04:48:50 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=210159126 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 452.prim_prince_test.210159126
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/452.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/453.prim_prince_test.774351777
Short name T460
Test name
Test status
Simulation time 3322434802 ps
CPU time 57.53 seconds
Started Sep 01 04:48:24 AM UTC 24
Finished Sep 01 04:49:39 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=774351777 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 453.prim_prince_test.774351777
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/453.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/454.prim_prince_test.860253141
Short name T446
Test name
Test status
Simulation time 1271146207 ps
CPU time 22.32 seconds
Started Sep 01 04:48:24 AM UTC 24
Finished Sep 01 04:48:54 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=860253141 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 454.prim_prince_test.860253141
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/454.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/455.prim_prince_test.953531947
Short name T450
Test name
Test status
Simulation time 1566499353 ps
CPU time 27.23 seconds
Started Sep 01 04:48:24 AM UTC 24
Finished Sep 01 04:49:00 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=953531947 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 455.prim_prince_test.953531947
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/455.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/456.prim_prince_test.2790508052
Short name T459
Test name
Test status
Simulation time 2913810999 ps
CPU time 50.62 seconds
Started Sep 01 04:48:27 AM UTC 24
Finished Sep 01 04:49:33 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2790508052 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 456.prim_prince_test.2790508052
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/456.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/457.prim_prince_test.2101755454
Short name T463
Test name
Test status
Simulation time 3099115552 ps
CPU time 53.69 seconds
Started Sep 01 04:48:39 AM UTC 24
Finished Sep 01 04:49:48 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2101755454 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 457.prim_prince_test.2101755454
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/457.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/458.prim_prince_test.3076330735
Short name T462
Test name
Test status
Simulation time 2605003427 ps
CPU time 45.58 seconds
Started Sep 01 04:48:42 AM UTC 24
Finished Sep 01 04:49:41 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3076330735 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 458.prim_prince_test.3076330735
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/458.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/459.prim_prince_test.1163614432
Short name T457
Test name
Test status
Simulation time 1803378470 ps
CPU time 31.53 seconds
Started Sep 01 04:48:50 AM UTC 24
Finished Sep 01 04:49:31 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1163614432 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 459.prim_prince_test.1163614432
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/459.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/46.prim_prince_test.3056504257
Short name T58
Test name
Test status
Simulation time 3662127575 ps
CPU time 64.72 seconds
Started Sep 01 04:29:36 AM UTC 24
Finished Sep 01 04:30:59 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3056504257 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 46.prim_prince_test.3056504257
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/46.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/460.prim_prince_test.2854353538
Short name T461
Test name
Test status
Simulation time 2164518637 ps
CPU time 37.92 seconds
Started Sep 01 04:48:50 AM UTC 24
Finished Sep 01 04:49:40 AM UTC 24
Peak memory 154652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2854353538 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 460.prim_prince_test.2854353538
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/460.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/461.prim_prince_test.3223631092
Short name T464
Test name
Test status
Simulation time 2585946715 ps
CPU time 45.25 seconds
Started Sep 01 04:48:51 AM UTC 24
Finished Sep 01 04:49:50 AM UTC 24
Peak memory 154652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3223631092 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 461.prim_prince_test.3223631092
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/461.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/462.prim_prince_test.3765017402
Short name T465
Test name
Test status
Simulation time 2620236886 ps
CPU time 45.73 seconds
Started Sep 01 04:48:51 AM UTC 24
Finished Sep 01 04:49:51 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3765017402 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 462.prim_prince_test.3765017402
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/462.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/463.prim_prince_test.425646170
Short name T466
Test name
Test status
Simulation time 2768139834 ps
CPU time 48.22 seconds
Started Sep 01 04:48:54 AM UTC 24
Finished Sep 01 04:49:57 AM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=425646170 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 463.prim_prince_test.425646170
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/463.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/464.prim_prince_test.1704661078
Short name T471
Test name
Test status
Simulation time 3222493976 ps
CPU time 56.08 seconds
Started Sep 01 04:48:55 AM UTC 24
Finished Sep 01 04:50:08 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1704661078 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 464.prim_prince_test.1704661078
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/464.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/465.prim_prince_test.194937624
Short name T468
Test name
Test status
Simulation time 2671104107 ps
CPU time 46.62 seconds
Started Sep 01 04:48:56 AM UTC 24
Finished Sep 01 04:49:57 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=194937624 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 465.prim_prince_test.194937624
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/465.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/466.prim_prince_test.1317375249
Short name T470
Test name
Test status
Simulation time 2985904525 ps
CPU time 52.24 seconds
Started Sep 01 04:48:56 AM UTC 24
Finished Sep 01 04:50:04 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1317375249 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 466.prim_prince_test.1317375249
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/466.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/467.prim_prince_test.281247277
Short name T454
Test name
Test status
Simulation time 908713340 ps
CPU time 16.14 seconds
Started Sep 01 04:48:58 AM UTC 24
Finished Sep 01 04:49:20 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=281247277 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 467.prim_prince_test.281247277
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/467.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/468.prim_prince_test.1419197406
Short name T475
Test name
Test status
Simulation time 3279413851 ps
CPU time 57.23 seconds
Started Sep 01 04:49:01 AM UTC 24
Finished Sep 01 04:50:15 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1419197406 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 468.prim_prince_test.1419197406
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/468.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/469.prim_prince_test.1840736452
Short name T467
Test name
Test status
Simulation time 2088313846 ps
CPU time 36.56 seconds
Started Sep 01 04:49:09 AM UTC 24
Finished Sep 01 04:49:57 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1840736452 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 469.prim_prince_test.1840736452
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/469.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/47.prim_prince_test.996451882
Short name T42
Test name
Test status
Simulation time 1358432493 ps
CPU time 24.22 seconds
Started Sep 01 04:29:37 AM UTC 24
Finished Sep 01 04:30:08 AM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=996451882 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 47.prim_prince_test.996451882
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/47.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/470.prim_prince_test.4258270223
Short name T458
Test name
Test status
Simulation time 917236846 ps
CPU time 16.39 seconds
Started Sep 01 04:49:11 AM UTC 24
Finished Sep 01 04:49:33 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4258270223 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 470.prim_prince_test.4258270223
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/470.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/471.prim_prince_test.3053285393
Short name T477
Test name
Test status
Simulation time 3350105620 ps
CPU time 58.25 seconds
Started Sep 01 04:49:17 AM UTC 24
Finished Sep 01 04:50:33 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3053285393 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 471.prim_prince_test.3053285393
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/471.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/472.prim_prince_test.581076728
Short name T476
Test name
Test status
Simulation time 2947821207 ps
CPU time 51.64 seconds
Started Sep 01 04:49:21 AM UTC 24
Finished Sep 01 04:50:29 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=581076728 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 472.prim_prince_test.581076728
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/472.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/473.prim_prince_test.1286510195
Short name T474
Test name
Test status
Simulation time 2122990576 ps
CPU time 37.45 seconds
Started Sep 01 04:49:24 AM UTC 24
Finished Sep 01 04:50:13 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1286510195 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 473.prim_prince_test.1286510195
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/473.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/474.prim_prince_test.2951760957
Short name T481
Test name
Test status
Simulation time 3103593679 ps
CPU time 54.91 seconds
Started Sep 01 04:49:31 AM UTC 24
Finished Sep 01 04:50:42 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2951760957 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 474.prim_prince_test.2951760957
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/474.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/475.prim_prince_test.933029566
Short name T473
Test name
Test status
Simulation time 1582323268 ps
CPU time 28.13 seconds
Started Sep 01 04:49:32 AM UTC 24
Finished Sep 01 04:50:09 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=933029566 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 475.prim_prince_test.933029566
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/475.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/476.prim_prince_test.5247733
Short name T486
Test name
Test status
Simulation time 3730609055 ps
CPU time 65.55 seconds
Started Sep 01 04:49:34 AM UTC 24
Finished Sep 01 04:50:59 AM UTC 24
Peak memory 156536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5247733 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 476.prim_prince_test.5247733
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/476.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/477.prim_prince_test.2676169297
Short name T485
Test name
Test status
Simulation time 3491198296 ps
CPU time 61.68 seconds
Started Sep 01 04:49:34 AM UTC 24
Finished Sep 01 04:50:54 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2676169297 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 477.prim_prince_test.2676169297
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/477.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/478.prim_prince_test.717209690
Short name T480
Test name
Test status
Simulation time 2521602769 ps
CPU time 44.95 seconds
Started Sep 01 04:49:40 AM UTC 24
Finished Sep 01 04:50:38 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=717209690 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 478.prim_prince_test.717209690
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/478.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/479.prim_prince_test.2798194781
Short name T469
Test name
Test status
Simulation time 932061282 ps
CPU time 16.81 seconds
Started Sep 01 04:49:41 AM UTC 24
Finished Sep 01 04:50:03 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2798194781 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 479.prim_prince_test.2798194781
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/479.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/48.prim_prince_test.4211455791
Short name T39
Test name
Test status
Simulation time 1058468711 ps
CPU time 19.23 seconds
Started Sep 01 04:29:38 AM UTC 24
Finished Sep 01 04:30:03 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4211455791 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 48.prim_prince_test.4211455791
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/48.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/480.prim_prince_test.4133004024
Short name T472
Test name
Test status
Simulation time 1108212555 ps
CPU time 19.87 seconds
Started Sep 01 04:49:42 AM UTC 24
Finished Sep 01 04:50:08 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4133004024 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 480.prim_prince_test.4133004024
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/480.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/481.prim_prince_test.3518328533
Short name T478
Test name
Test status
Simulation time 1916882998 ps
CPU time 33.79 seconds
Started Sep 01 04:49:49 AM UTC 24
Finished Sep 01 04:50:33 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3518328533 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 481.prim_prince_test.3518328533
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/481.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/482.prim_prince_test.1610559335
Short name T491
Test name
Test status
Simulation time 3477685720 ps
CPU time 60.53 seconds
Started Sep 01 04:49:51 AM UTC 24
Finished Sep 01 04:51:10 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1610559335 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 482.prim_prince_test.1610559335
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/482.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/483.prim_prince_test.2149884049
Short name T483
Test name
Test status
Simulation time 2448784555 ps
CPU time 42.75 seconds
Started Sep 01 04:49:51 AM UTC 24
Finished Sep 01 04:50:47 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2149884049 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 483.prim_prince_test.2149884049
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/483.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/484.prim_prince_test.1995093102
Short name T479
Test name
Test status
Simulation time 1517462356 ps
CPU time 27.36 seconds
Started Sep 01 04:49:58 AM UTC 24
Finished Sep 01 04:50:35 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1995093102 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 484.prim_prince_test.1995093102
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/484.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/485.prim_prince_test.1893251368
Short name T494
Test name
Test status
Simulation time 3500964992 ps
CPU time 61.31 seconds
Started Sep 01 04:49:58 AM UTC 24
Finished Sep 01 04:51:18 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1893251368 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 485.prim_prince_test.1893251368
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/485.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/486.prim_prince_test.2043721731
Short name T487
Test name
Test status
Simulation time 2684810025 ps
CPU time 46.47 seconds
Started Sep 01 04:49:58 AM UTC 24
Finished Sep 01 04:50:59 AM UTC 24
Peak memory 154648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2043721731 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 486.prim_prince_test.2043721731
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/486.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/487.prim_prince_test.1013763911
Short name T488
Test name
Test status
Simulation time 2654852750 ps
CPU time 46.46 seconds
Started Sep 01 04:50:04 AM UTC 24
Finished Sep 01 04:51:05 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1013763911 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 487.prim_prince_test.1013763911
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/487.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/488.prim_prince_test.1298141831
Short name T482
Test name
Test status
Simulation time 1547071300 ps
CPU time 27.71 seconds
Started Sep 01 04:50:07 AM UTC 24
Finished Sep 01 04:50:43 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1298141831 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 488.prim_prince_test.1298141831
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/488.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/489.prim_prince_test.3032799782
Short name T496
Test name
Test status
Simulation time 3683015628 ps
CPU time 63.77 seconds
Started Sep 01 04:50:09 AM UTC 24
Finished Sep 01 04:51:33 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3032799782 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 489.prim_prince_test.3032799782
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/489.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/49.prim_prince_test.3878821088
Short name T57
Test name
Test status
Simulation time 3176851627 ps
CPU time 56.83 seconds
Started Sep 01 04:29:42 AM UTC 24
Finished Sep 01 04:30:55 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3878821088 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 49.prim_prince_test.3878821088
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/49.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/490.prim_prince_test.80676967
Short name T484
Test name
Test status
Simulation time 1662322786 ps
CPU time 29.04 seconds
Started Sep 01 04:50:09 AM UTC 24
Finished Sep 01 04:50:47 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=80676967 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 490.prim_prince_test.80676967
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/490.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/491.prim_prince_test.2793593855
Short name T495
Test name
Test status
Simulation time 3405491430 ps
CPU time 59.67 seconds
Started Sep 01 04:50:11 AM UTC 24
Finished Sep 01 04:51:29 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2793593855 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 491.prim_prince_test.2793593855
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/491.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/492.prim_prince_test.533700506
Short name T492
Test name
Test status
Simulation time 2700465193 ps
CPU time 46.2 seconds
Started Sep 01 04:50:13 AM UTC 24
Finished Sep 01 04:51:14 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=533700506 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 492.prim_prince_test.533700506
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/492.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/493.prim_prince_test.155780061
Short name T493
Test name
Test status
Simulation time 2670903910 ps
CPU time 45.56 seconds
Started Sep 01 04:50:16 AM UTC 24
Finished Sep 01 04:51:15 AM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=155780061 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 493.prim_prince_test.155780061
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/493.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/494.prim_prince_test.726850183
Short name T499
Test name
Test status
Simulation time 3344010963 ps
CPU time 55.96 seconds
Started Sep 01 04:50:31 AM UTC 24
Finished Sep 01 04:51:45 AM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=726850183 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 494.prim_prince_test.726850183
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/494.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/495.prim_prince_test.240920243
Short name T490
Test name
Test status
Simulation time 1610561551 ps
CPU time 28.28 seconds
Started Sep 01 04:50:32 AM UTC 24
Finished Sep 01 04:51:09 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=240920243 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 495.prim_prince_test.240920243
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/495.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/496.prim_prince_test.3030894005
Short name T500
Test name
Test status
Simulation time 3565343965 ps
CPU time 61.43 seconds
Started Sep 01 04:50:34 AM UTC 24
Finished Sep 01 04:51:55 AM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3030894005 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 496.prim_prince_test.3030894005
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/496.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/497.prim_prince_test.232994767
Short name T498
Test name
Test status
Simulation time 3014926543 ps
CPU time 50.98 seconds
Started Sep 01 04:50:34 AM UTC 24
Finished Sep 01 04:51:41 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=232994767 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 497.prim_prince_test.232994767
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/497.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/498.prim_prince_test.618092161
Short name T489
Test name
Test status
Simulation time 1375321247 ps
CPU time 23.62 seconds
Started Sep 01 04:50:35 AM UTC 24
Finished Sep 01 04:51:07 AM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=618092161 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 498.prim_prince_test.618092161
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/498.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/499.prim_prince_test.1889484631
Short name T497
Test name
Test status
Simulation time 2795341247 ps
CPU time 46.9 seconds
Started Sep 01 04:50:39 AM UTC 24
Finished Sep 01 04:51:41 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1889484631 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 499.prim_prince_test.1889484631
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/499.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/5.prim_prince_test.4145452867
Short name T22
Test name
Test status
Simulation time 3617619789 ps
CPU time 65.13 seconds
Started Sep 01 04:27:53 AM UTC 24
Finished Sep 01 04:29:16 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4145452867 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 5.prim_prince_test.4145452867
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/5.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/50.prim_prince_test.3157919672
Short name T48
Test name
Test status
Simulation time 1683900641 ps
CPU time 30.19 seconds
Started Sep 01 04:29:45 AM UTC 24
Finished Sep 01 04:30:24 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3157919672 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 50.prim_prince_test.3157919672
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/50.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/51.prim_prince_test.3724752323
Short name T54
Test name
Test status
Simulation time 2466645842 ps
CPU time 43.83 seconds
Started Sep 01 04:29:46 AM UTC 24
Finished Sep 01 04:30:43 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3724752323 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 51.prim_prince_test.3724752323
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/51.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/52.prim_prince_test.3102935470
Short name T49
Test name
Test status
Simulation time 1733412009 ps
CPU time 31.05 seconds
Started Sep 01 04:29:49 AM UTC 24
Finished Sep 01 04:30:29 AM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3102935470 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 52.prim_prince_test.3102935470
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/52.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/53.prim_prince_test.2184404460
Short name T52
Test name
Test status
Simulation time 2157580323 ps
CPU time 38.68 seconds
Started Sep 01 04:29:50 AM UTC 24
Finished Sep 01 04:30:40 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2184404460 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 53.prim_prince_test.2184404460
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/53.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/54.prim_prince_test.3712834442
Short name T51
Test name
Test status
Simulation time 1627092538 ps
CPU time 29.19 seconds
Started Sep 01 04:29:58 AM UTC 24
Finished Sep 01 04:30:36 AM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3712834442 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 54.prim_prince_test.3712834442
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/54.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/55.prim_prince_test.1259259290
Short name T56
Test name
Test status
Simulation time 2281550101 ps
CPU time 40.59 seconds
Started Sep 01 04:30:00 AM UTC 24
Finished Sep 01 04:30:53 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1259259290 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 55.prim_prince_test.1259259290
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/55.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/56.prim_prince_test.4294599637
Short name T62
Test name
Test status
Simulation time 2754692247 ps
CPU time 49.11 seconds
Started Sep 01 04:30:00 AM UTC 24
Finished Sep 01 04:31:04 AM UTC 24
Peak memory 156116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4294599637 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 56.prim_prince_test.4294599637
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/56.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/57.prim_prince_test.1827880445
Short name T68
Test name
Test status
Simulation time 3199160584 ps
CPU time 56.9 seconds
Started Sep 01 04:30:04 AM UTC 24
Finished Sep 01 04:31:17 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1827880445 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 57.prim_prince_test.1827880445
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/57.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/58.prim_prince_test.2723118525
Short name T60
Test name
Test status
Simulation time 2415946417 ps
CPU time 43.07 seconds
Started Sep 01 04:30:06 AM UTC 24
Finished Sep 01 04:31:01 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2723118525 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 58.prim_prince_test.2723118525
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/58.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/59.prim_prince_test.1511710598
Short name T50
Test name
Test status
Simulation time 1173913084 ps
CPU time 21.3 seconds
Started Sep 01 04:30:08 AM UTC 24
Finished Sep 01 04:30:35 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1511710598 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 59.prim_prince_test.1511710598
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/59.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/6.prim_prince_test.1687728097
Short name T5
Test name
Test status
Simulation time 1517514917 ps
CPU time 27.91 seconds
Started Sep 01 04:27:53 AM UTC 24
Finished Sep 01 04:28:29 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1687728097 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 6.prim_prince_test.1687728097
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/6.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/60.prim_prince_test.1836252536
Short name T59
Test name
Test status
Simulation time 2235703841 ps
CPU time 39.7 seconds
Started Sep 01 04:30:10 AM UTC 24
Finished Sep 01 04:31:01 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1836252536 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 60.prim_prince_test.1836252536
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/60.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/61.prim_prince_test.3844624538
Short name T63
Test name
Test status
Simulation time 2510555440 ps
CPU time 44.51 seconds
Started Sep 01 04:30:10 AM UTC 24
Finished Sep 01 04:31:07 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3844624538 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 61.prim_prince_test.3844624538
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/61.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/62.prim_prince_test.1290011862
Short name T66
Test name
Test status
Simulation time 2560297641 ps
CPU time 46 seconds
Started Sep 01 04:30:12 AM UTC 24
Finished Sep 01 04:31:11 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1290011862 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 62.prim_prince_test.1290011862
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/62.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/63.prim_prince_test.3749976979
Short name T61
Test name
Test status
Simulation time 1984520434 ps
CPU time 35.3 seconds
Started Sep 01 04:30:16 AM UTC 24
Finished Sep 01 04:31:02 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3749976979 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 63.prim_prince_test.3749976979
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/63.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/64.prim_prince_test.4012461299
Short name T55
Test name
Test status
Simulation time 1471043924 ps
CPU time 26.55 seconds
Started Sep 01 04:30:16 AM UTC 24
Finished Sep 01 04:30:50 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4012461299 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 64.prim_prince_test.4012461299
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/64.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/65.prim_prince_test.2347672551
Short name T70
Test name
Test status
Simulation time 3257409579 ps
CPU time 58.48 seconds
Started Sep 01 04:30:16 AM UTC 24
Finished Sep 01 04:31:31 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2347672551 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 65.prim_prince_test.2347672551
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/65.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/66.prim_prince_test.1550766257
Short name T74
Test name
Test status
Simulation time 3409283712 ps
CPU time 60.71 seconds
Started Sep 01 04:30:25 AM UTC 24
Finished Sep 01 04:31:43 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1550766257 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 66.prim_prince_test.1550766257
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/66.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/67.prim_prince_test.2836379623
Short name T73
Test name
Test status
Simulation time 3065393086 ps
CPU time 53.64 seconds
Started Sep 01 04:30:30 AM UTC 24
Finished Sep 01 04:31:40 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2836379623 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 67.prim_prince_test.2836379623
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/67.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/68.prim_prince_test.2744382369
Short name T71
Test name
Test status
Simulation time 2428119205 ps
CPU time 43.92 seconds
Started Sep 01 04:30:36 AM UTC 24
Finished Sep 01 04:31:33 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2744382369 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 68.prim_prince_test.2744382369
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/68.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/69.prim_prince_test.2746357788
Short name T67
Test name
Test status
Simulation time 1466607565 ps
CPU time 26.31 seconds
Started Sep 01 04:30:37 AM UTC 24
Finished Sep 01 04:31:12 AM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2746357788 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 69.prim_prince_test.2746357788
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/69.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/7.prim_prince_test.1765486257
Short name T2
Test name
Test status
Simulation time 961107994 ps
CPU time 17.99 seconds
Started Sep 01 04:27:54 AM UTC 24
Finished Sep 01 04:28:17 AM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1765486257 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 7.prim_prince_test.1765486257
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/7.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/70.prim_prince_test.2510791724
Short name T76
Test name
Test status
Simulation time 3012238079 ps
CPU time 52.84 seconds
Started Sep 01 04:30:41 AM UTC 24
Finished Sep 01 04:31:50 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2510791724 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 70.prim_prince_test.2510791724
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/70.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/71.prim_prince_test.3030862332
Short name T64
Test name
Test status
Simulation time 1107010845 ps
CPU time 19.87 seconds
Started Sep 01 04:30:42 AM UTC 24
Finished Sep 01 04:31:08 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3030862332 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 71.prim_prince_test.3030862332
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/71.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/72.prim_prince_test.2552848237
Short name T65
Test name
Test status
Simulation time 1017897484 ps
CPU time 18.35 seconds
Started Sep 01 04:30:44 AM UTC 24
Finished Sep 01 04:31:08 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2552848237 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 72.prim_prince_test.2552848237
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/72.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/73.prim_prince_test.3246734130
Short name T80
Test name
Test status
Simulation time 2916673042 ps
CPU time 51.37 seconds
Started Sep 01 04:30:51 AM UTC 24
Finished Sep 01 04:31:57 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3246734130 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 73.prim_prince_test.3246734130
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/73.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/74.prim_prince_test.3639408566
Short name T69
Test name
Test status
Simulation time 1148944829 ps
CPU time 20.4 seconds
Started Sep 01 04:30:54 AM UTC 24
Finished Sep 01 04:31:21 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3639408566 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 74.prim_prince_test.3639408566
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/74.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/75.prim_prince_test.2945674011
Short name T72
Test name
Test status
Simulation time 1696715776 ps
CPU time 30.21 seconds
Started Sep 01 04:30:56 AM UTC 24
Finished Sep 01 04:31:35 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2945674011 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 75.prim_prince_test.2945674011
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/75.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/76.prim_prince_test.4231921744
Short name T79
Test name
Test status
Simulation time 2383923106 ps
CPU time 42.51 seconds
Started Sep 01 04:31:00 AM UTC 24
Finished Sep 01 04:31:55 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4231921744 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 76.prim_prince_test.4231921744
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/76.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/77.prim_prince_test.2710485744
Short name T91
Test name
Test status
Simulation time 3703667048 ps
CPU time 65.03 seconds
Started Sep 01 04:31:02 AM UTC 24
Finished Sep 01 04:32:26 AM UTC 24
Peak memory 154580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2710485744 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 77.prim_prince_test.2710485744
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/77.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/78.prim_prince_test.3083434650
Short name T87
Test name
Test status
Simulation time 3123570823 ps
CPU time 55.12 seconds
Started Sep 01 04:31:02 AM UTC 24
Finished Sep 01 04:32:13 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3083434650 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 78.prim_prince_test.3083434650
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/78.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/79.prim_prince_test.571774132
Short name T83
Test name
Test status
Simulation time 2801579607 ps
CPU time 50.06 seconds
Started Sep 01 04:31:02 AM UTC 24
Finished Sep 01 04:32:07 AM UTC 24
Peak memory 154588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=571774132 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 79.prim_prince_test.571774132
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/79.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/8.prim_prince_test.3320488810
Short name T20
Test name
Test status
Simulation time 3436780386 ps
CPU time 62.41 seconds
Started Sep 01 04:27:54 AM UTC 24
Finished Sep 01 04:29:13 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3320488810 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 8.prim_prince_test.3320488810
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/8.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/80.prim_prince_test.571190785
Short name T81
Test name
Test status
Simulation time 2402062295 ps
CPU time 42.54 seconds
Started Sep 01 04:31:04 AM UTC 24
Finished Sep 01 04:31:59 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=571190785 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 80.prim_prince_test.571190785
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/80.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/81.prim_prince_test.2451881737
Short name T93
Test name
Test status
Simulation time 3550716905 ps
CPU time 63.15 seconds
Started Sep 01 04:31:08 AM UTC 24
Finished Sep 01 04:32:30 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2451881737 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 81.prim_prince_test.2451881737
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/81.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/82.prim_prince_test.2573157478
Short name T82
Test name
Test status
Simulation time 2465689926 ps
CPU time 43.54 seconds
Started Sep 01 04:31:08 AM UTC 24
Finished Sep 01 04:32:05 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2573157478 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 82.prim_prince_test.2573157478
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/82.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/83.prim_prince_test.2381654168
Short name T77
Test name
Test status
Simulation time 1812885554 ps
CPU time 32.29 seconds
Started Sep 01 04:31:08 AM UTC 24
Finished Sep 01 04:31:50 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2381654168 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 83.prim_prince_test.2381654168
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/83.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/84.prim_prince_test.1810709448
Short name T86
Test name
Test status
Simulation time 2646093142 ps
CPU time 46.78 seconds
Started Sep 01 04:31:12 AM UTC 24
Finished Sep 01 04:32:12 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1810709448 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 84.prim_prince_test.1810709448
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/84.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/85.prim_prince_test.1907393255
Short name T90
Test name
Test status
Simulation time 3123245035 ps
CPU time 55.35 seconds
Started Sep 01 04:31:13 AM UTC 24
Finished Sep 01 04:32:24 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1907393255 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 85.prim_prince_test.1907393255
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/85.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/86.prim_prince_test.4010936626
Short name T78
Test name
Test status
Simulation time 1575884120 ps
CPU time 28.13 seconds
Started Sep 01 04:31:18 AM UTC 24
Finished Sep 01 04:31:54 AM UTC 24
Peak memory 154584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4010936626 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 86.prim_prince_test.4010936626
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/86.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/87.prim_prince_test.2700797780
Short name T75
Test name
Test status
Simulation time 979423398 ps
CPU time 17.65 seconds
Started Sep 01 04:31:22 AM UTC 24
Finished Sep 01 04:31:45 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2700797780 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 87.prim_prince_test.2700797780
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/87.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/88.prim_prince_test.147201559
Short name T89
Test name
Test status
Simulation time 2182561548 ps
CPU time 38.71 seconds
Started Sep 01 04:31:32 AM UTC 24
Finished Sep 01 04:32:22 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=147201559 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 88.prim_prince_test.147201559
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/88.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/89.prim_prince_test.2173205069
Short name T84
Test name
Test status
Simulation time 1429071869 ps
CPU time 25.73 seconds
Started Sep 01 04:31:34 AM UTC 24
Finished Sep 01 04:32:08 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2173205069 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 89.prim_prince_test.2173205069
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/89.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/9.prim_prince_test.525698700
Short name T17
Test name
Test status
Simulation time 3331029824 ps
CPU time 59.48 seconds
Started Sep 01 04:27:54 AM UTC 24
Finished Sep 01 04:29:10 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=525698700 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 9.prim_prince_test.525698700
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/9.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/90.prim_prince_test.2701112297
Short name T88
Test name
Test status
Simulation time 1620697226 ps
CPU time 28.98 seconds
Started Sep 01 04:31:36 AM UTC 24
Finished Sep 01 04:32:14 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2701112297 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 90.prim_prince_test.2701112297
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/90.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/91.prim_prince_test.71841596
Short name T104
Test name
Test status
Simulation time 3634670295 ps
CPU time 63.82 seconds
Started Sep 01 04:31:40 AM UTC 24
Finished Sep 01 04:33:02 AM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=71841596 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 91.prim_prince_test.71841596
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/91.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/92.prim_prince_test.3499214912
Short name T105
Test name
Test status
Simulation time 3732407188 ps
CPU time 65.43 seconds
Started Sep 01 04:31:44 AM UTC 24
Finished Sep 01 04:33:08 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3499214912 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 92.prim_prince_test.3499214912
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/92.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/93.prim_prince_test.1198510788
Short name T103
Test name
Test status
Simulation time 3268281790 ps
CPU time 58.16 seconds
Started Sep 01 04:31:46 AM UTC 24
Finished Sep 01 04:33:01 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1198510788 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 93.prim_prince_test.1198510788
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/93.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/94.prim_prince_test.1795970265
Short name T85
Test name
Test status
Simulation time 870878043 ps
CPU time 15.81 seconds
Started Sep 01 04:31:50 AM UTC 24
Finished Sep 01 04:32:11 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1795970265 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 94.prim_prince_test.1795970265
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/94.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/95.prim_prince_test.70828990
Short name T98
Test name
Test status
Simulation time 2574851558 ps
CPU time 45.96 seconds
Started Sep 01 04:31:51 AM UTC 24
Finished Sep 01 04:32:51 AM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=70828990 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 95.prim_prince_test.70828990
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/95.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/96.prim_prince_test.203014448
Short name T106
Test name
Test status
Simulation time 3259756059 ps
CPU time 57.35 seconds
Started Sep 01 04:31:56 AM UTC 24
Finished Sep 01 04:33:10 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=203014448 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 96.prim_prince_test.203014448
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/96.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/97.prim_prince_test.2029557535
Short name T94
Test name
Test status
Simulation time 1881727957 ps
CPU time 33.2 seconds
Started Sep 01 04:31:56 AM UTC 24
Finished Sep 01 04:32:39 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2029557535 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 97.prim_prince_test.2029557535
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/97.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/98.prim_prince_test.1332844566
Short name T107
Test name
Test status
Simulation time 3455992957 ps
CPU time 61.73 seconds
Started Sep 01 04:31:58 AM UTC 24
Finished Sep 01 04:33:17 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1332844566 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 98.prim_prince_test.1332844566
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/98.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default/99.prim_prince_test.153013463
Short name T92
Test name
Test status
Simulation time 1162739881 ps
CPU time 20.81 seconds
Started Sep 01 04:32:00 AM UTC 24
Finished Sep 01 04:32:27 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=153013463 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 99.prim_prince_test.153013463
Directory /workspaces/repo/scratch/os_regression_2024_08_31/prim_prince-sim-vcs/99.prim_prince_test/latest
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