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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00 100.00


Total test records in report: 500
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html
T251 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/236.prim_prince_test.79188033 Sep 03 11:24:17 PM UTC 24 Sep 03 11:25:14 PM UTC 24 2603281105 ps
T252 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/234.prim_prince_test.1580711476 Sep 03 11:24:16 PM UTC 24 Sep 03 11:25:14 PM UTC 24 2681337806 ps
T253 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/253.prim_prince_test.4036717862 Sep 03 11:24:32 PM UTC 24 Sep 03 11:25:15 PM UTC 24 1948288123 ps
T254 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/251.prim_prince_test.1896080159 Sep 03 11:24:31 PM UTC 24 Sep 03 11:25:16 PM UTC 24 2034815477 ps
T255 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/228.prim_prince_test.1975210208 Sep 03 11:24:12 PM UTC 24 Sep 03 11:25:16 PM UTC 24 2941300228 ps
T256 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/255.prim_prince_test.3335123587 Sep 03 11:24:33 PM UTC 24 Sep 03 11:25:17 PM UTC 24 2003425480 ps
T257 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/231.prim_prince_test.3141901979 Sep 03 11:24:14 PM UTC 24 Sep 03 11:25:17 PM UTC 24 2917240504 ps
T258 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/275.prim_prince_test.1626134355 Sep 03 11:24:46 PM UTC 24 Sep 03 11:25:17 PM UTC 24 1426108577 ps
T259 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/295.prim_prince_test.2431893596 Sep 03 11:24:59 PM UTC 24 Sep 03 11:25:18 PM UTC 24 844711438 ps
T260 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/215.prim_prince_test.618747714 Sep 03 11:23:59 PM UTC 24 Sep 03 11:25:19 PM UTC 24 3654420857 ps
T261 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/282.prim_prince_test.3875320821 Sep 03 11:24:52 PM UTC 24 Sep 03 11:25:21 PM UTC 24 1294971098 ps
T262 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/265.prim_prince_test.3548090460 Sep 03 11:24:41 PM UTC 24 Sep 03 11:25:22 PM UTC 24 1854250439 ps
T263 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/269.prim_prince_test.1302475202 Sep 03 11:24:42 PM UTC 24 Sep 03 11:25:22 PM UTC 24 1767262018 ps
T264 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/288.prim_prince_test.3614084919 Sep 03 11:24:53 PM UTC 24 Sep 03 11:25:22 PM UTC 24 1309256736 ps
T265 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/289.prim_prince_test.817816674 Sep 03 11:24:54 PM UTC 24 Sep 03 11:25:22 PM UTC 24 1228428145 ps
T266 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/272.prim_prince_test.2827765209 Sep 03 11:24:45 PM UTC 24 Sep 03 11:25:25 PM UTC 24 1813333358 ps
T267 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/257.prim_prince_test.283556701 Sep 03 11:24:35 PM UTC 24 Sep 03 11:25:26 PM UTC 24 2287035983 ps
T268 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/298.prim_prince_test.746195258 Sep 03 11:25:02 PM UTC 24 Sep 03 11:25:27 PM UTC 24 1140234918 ps
T269 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/247.prim_prince_test.1939911425 Sep 03 11:24:25 PM UTC 24 Sep 03 11:25:28 PM UTC 24 2976908729 ps
T270 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/277.prim_prince_test.157242409 Sep 03 11:24:48 PM UTC 24 Sep 03 11:25:29 PM UTC 24 1842717881 ps
T271 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/278.prim_prince_test.3422035745 Sep 03 11:24:48 PM UTC 24 Sep 03 11:25:30 PM UTC 24 1896835833 ps
T272 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/268.prim_prince_test.4230936578 Sep 03 11:24:41 PM UTC 24 Sep 03 11:25:31 PM UTC 24 2260737032 ps
T273 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/299.prim_prince_test.3193153576 Sep 03 11:25:03 PM UTC 24 Sep 03 11:25:33 PM UTC 24 1305240642 ps
T274 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/281.prim_prince_test.3917458116 Sep 03 11:24:49 PM UTC 24 Sep 03 11:25:35 PM UTC 24 2034051374 ps
T275 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/256.prim_prince_test.3960793288 Sep 03 11:24:34 PM UTC 24 Sep 03 11:25:35 PM UTC 24 2808648866 ps
T276 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/290.prim_prince_test.66636303 Sep 03 11:24:54 PM UTC 24 Sep 03 11:25:35 PM UTC 24 1822039713 ps
T277 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/264.prim_prince_test.3337573885 Sep 03 11:24:40 PM UTC 24 Sep 03 11:25:36 PM UTC 24 2575604860 ps
T278 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/262.prim_prince_test.3494624565 Sep 03 11:24:39 PM UTC 24 Sep 03 11:25:38 PM UTC 24 2730301334 ps
T279 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/294.prim_prince_test.4187932011 Sep 03 11:24:57 PM UTC 24 Sep 03 11:25:38 PM UTC 24 1862888375 ps
T280 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/270.prim_prince_test.1945525557 Sep 03 11:24:42 PM UTC 24 Sep 03 11:25:38 PM UTC 24 2579044334 ps
T281 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/307.prim_prince_test.1070416170 Sep 03 11:25:12 PM UTC 24 Sep 03 11:25:38 PM UTC 24 1155959108 ps
T282 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/244.prim_prince_test.1967279195 Sep 03 11:24:24 PM UTC 24 Sep 03 11:25:39 PM UTC 24 3528081252 ps
T283 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/310.prim_prince_test.1715115342 Sep 03 11:25:15 PM UTC 24 Sep 03 11:25:39 PM UTC 24 1094535794 ps
T284 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/316.prim_prince_test.4043031546 Sep 03 11:25:17 PM UTC 24 Sep 03 11:25:39 PM UTC 24 984775086 ps
T285 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/254.prim_prince_test.2638177248 Sep 03 11:24:33 PM UTC 24 Sep 03 11:25:39 PM UTC 24 3054819944 ps
T286 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/285.prim_prince_test.1013680085 Sep 03 11:24:52 PM UTC 24 Sep 03 11:25:40 PM UTC 24 2171833861 ps
T287 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/291.prim_prince_test.1482130789 Sep 03 11:24:55 PM UTC 24 Sep 03 11:25:40 PM UTC 24 2045722247 ps
T288 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/266.prim_prince_test.3072392505 Sep 03 11:24:41 PM UTC 24 Sep 03 11:25:41 PM UTC 24 2733652917 ps
T289 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/309.prim_prince_test.2352709500 Sep 03 11:25:13 PM UTC 24 Sep 03 11:25:41 PM UTC 24 1236553534 ps
T290 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/322.prim_prince_test.1582383014 Sep 03 11:25:23 PM UTC 24 Sep 03 11:25:42 PM UTC 24 843508398 ps
T291 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/319.prim_prince_test.2206869023 Sep 03 11:25:18 PM UTC 24 Sep 03 11:25:44 PM UTC 24 1136447789 ps
T292 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/260.prim_prince_test.594028231 Sep 03 11:24:37 PM UTC 24 Sep 03 11:25:44 PM UTC 24 3088663883 ps
T293 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/287.prim_prince_test.4070818415 Sep 03 11:24:53 PM UTC 24 Sep 03 11:25:44 PM UTC 24 2333941183 ps
T294 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/252.prim_prince_test.505848837 Sep 03 11:24:31 PM UTC 24 Sep 03 11:25:45 PM UTC 24 3430693128 ps
T295 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/267.prim_prince_test.2206121193 Sep 03 11:24:41 PM UTC 24 Sep 03 11:25:46 PM UTC 24 2963437637 ps
T296 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/326.prim_prince_test.1111711350 Sep 03 11:25:26 PM UTC 24 Sep 03 11:25:46 PM UTC 24 867099009 ps
T297 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/300.prim_prince_test.2198190214 Sep 03 11:25:08 PM UTC 24 Sep 03 11:25:48 PM UTC 24 1805508288 ps
T298 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/312.prim_prince_test.246650241 Sep 03 11:25:16 PM UTC 24 Sep 03 11:25:48 PM UTC 24 1471309967 ps
T299 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/320.prim_prince_test.342146292 Sep 03 11:25:20 PM UTC 24 Sep 03 11:25:48 PM UTC 24 1307735769 ps
T300 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/303.prim_prince_test.908848437 Sep 03 11:25:10 PM UTC 24 Sep 03 11:25:51 PM UTC 24 1855099145 ps
T301 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/261.prim_prince_test.2893543487 Sep 03 11:24:37 PM UTC 24 Sep 03 11:25:55 PM UTC 24 3592422346 ps
T302 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/273.prim_prince_test.900651184 Sep 03 11:24:45 PM UTC 24 Sep 03 11:25:59 PM UTC 24 3431180077 ps
T303 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/311.prim_prince_test.1955454347 Sep 03 11:25:15 PM UTC 24 Sep 03 11:26:00 PM UTC 24 2075864973 ps
T304 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/296.prim_prince_test.2167695056 Sep 03 11:25:01 PM UTC 24 Sep 03 11:26:01 PM UTC 24 2748510552 ps
T305 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/280.prim_prince_test.1481069947 Sep 03 11:24:49 PM UTC 24 Sep 03 11:26:01 PM UTC 24 3298934852 ps
T306 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/351.prim_prince_test.242545118 Sep 03 11:25:43 PM UTC 24 Sep 03 11:26:02 PM UTC 24 802801941 ps
T307 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/293.prim_prince_test.3827923134 Sep 03 11:24:57 PM UTC 24 Sep 03 11:26:02 PM UTC 24 2998984902 ps
T308 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/302.prim_prince_test.894732403 Sep 03 11:25:10 PM UTC 24 Sep 03 11:26:03 PM UTC 24 2456069032 ps
T309 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/317.prim_prince_test.3747446923 Sep 03 11:25:18 PM UTC 24 Sep 03 11:26:04 PM UTC 24 2094218086 ps
T310 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/283.prim_prince_test.3523119629 Sep 03 11:24:52 PM UTC 24 Sep 03 11:26:04 PM UTC 24 3342939983 ps
T311 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/333.prim_prince_test.1613408674 Sep 03 11:25:33 PM UTC 24 Sep 03 11:26:05 PM UTC 24 1431323319 ps
T312 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/304.prim_prince_test.99671673 Sep 03 11:25:10 PM UTC 24 Sep 03 11:26:06 PM UTC 24 2611854148 ps
T313 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/286.prim_prince_test.3079721324 Sep 03 11:24:53 PM UTC 24 Sep 03 11:26:07 PM UTC 24 3399113290 ps
T314 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/276.prim_prince_test.952679044 Sep 03 11:24:48 PM UTC 24 Sep 03 11:26:08 PM UTC 24 3692722970 ps
T315 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/292.prim_prince_test.1838598764 Sep 03 11:24:55 PM UTC 24 Sep 03 11:26:08 PM UTC 24 3356605485 ps
T316 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/356.prim_prince_test.4085056608 Sep 03 11:25:47 PM UTC 24 Sep 03 11:26:08 PM UTC 24 938792042 ps
T317 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/313.prim_prince_test.4080049361 Sep 03 11:25:16 PM UTC 24 Sep 03 11:26:10 PM UTC 24 2514976496 ps
T318 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/284.prim_prince_test.4110766343 Sep 03 11:24:52 PM UTC 24 Sep 03 11:26:11 PM UTC 24 3650319979 ps
T319 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/354.prim_prince_test.1528435191 Sep 03 11:25:46 PM UTC 24 Sep 03 11:26:11 PM UTC 24 1116307078 ps
T320 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/337.prim_prince_test.4286015391 Sep 03 11:25:37 PM UTC 24 Sep 03 11:26:11 PM UTC 24 1557285734 ps
T321 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/314.prim_prince_test.3473533417 Sep 03 11:25:17 PM UTC 24 Sep 03 11:26:11 PM UTC 24 2478677273 ps
T322 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/324.prim_prince_test.2370498808 Sep 03 11:25:23 PM UTC 24 Sep 03 11:26:12 PM UTC 24 2232901636 ps
T323 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/327.prim_prince_test.2453313558 Sep 03 11:25:26 PM UTC 24 Sep 03 11:26:12 PM UTC 24 2089204598 ps
T324 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/357.prim_prince_test.1271865329 Sep 03 11:25:47 PM UTC 24 Sep 03 11:26:13 PM UTC 24 1153299055 ps
T325 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/329.prim_prince_test.94049988 Sep 03 11:25:30 PM UTC 24 Sep 03 11:26:20 PM UTC 24 2346442325 ps
T326 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/371.prim_prince_test.1696458101 Sep 03 11:26:05 PM UTC 24 Sep 03 11:26:22 PM UTC 24 761029998 ps
T327 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/353.prim_prince_test.575347463 Sep 03 11:25:46 PM UTC 24 Sep 03 11:26:13 PM UTC 24 1255013428 ps
T328 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/305.prim_prince_test.1592736561 Sep 03 11:25:11 PM UTC 24 Sep 03 11:26:17 PM UTC 24 3080681641 ps
T329 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/328.prim_prince_test.4264455385 Sep 03 11:25:29 PM UTC 24 Sep 03 11:26:18 PM UTC 24 2240299528 ps
T330 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/297.prim_prince_test.1446103270 Sep 03 11:25:01 PM UTC 24 Sep 03 11:26:18 PM UTC 24 3595073747 ps
T331 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/325.prim_prince_test.1544284551 Sep 03 11:25:23 PM UTC 24 Sep 03 11:26:18 PM UTC 24 2545637297 ps
T332 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/341.prim_prince_test.1734256809 Sep 03 11:25:39 PM UTC 24 Sep 03 11:26:20 PM UTC 24 1831158541 ps
T333 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/301.prim_prince_test.2956070083 Sep 03 11:25:10 PM UTC 24 Sep 03 11:26:20 PM UTC 24 3246265388 ps
T334 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/323.prim_prince_test.2661398313 Sep 03 11:25:23 PM UTC 24 Sep 03 11:26:20 PM UTC 24 2620980601 ps
T335 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/306.prim_prince_test.720580138 Sep 03 11:25:11 PM UTC 24 Sep 03 11:26:22 PM UTC 24 3298652788 ps
T336 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/343.prim_prince_test.3161226191 Sep 03 11:25:41 PM UTC 24 Sep 03 11:26:22 PM UTC 24 1881220660 ps
T337 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/318.prim_prince_test.1670825678 Sep 03 11:25:18 PM UTC 24 Sep 03 11:26:24 PM UTC 24 3015609102 ps
T338 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/339.prim_prince_test.2916590478 Sep 03 11:25:39 PM UTC 24 Sep 03 11:26:24 PM UTC 24 2045929728 ps
T339 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/308.prim_prince_test.3658347128 Sep 03 11:25:12 PM UTC 24 Sep 03 11:26:24 PM UTC 24 3364805584 ps
T340 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/334.prim_prince_test.2843173578 Sep 03 11:25:35 PM UTC 24 Sep 03 11:26:25 PM UTC 24 2255945578 ps
T341 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/315.prim_prince_test.2164108825 Sep 03 11:25:17 PM UTC 24 Sep 03 11:26:26 PM UTC 24 3230278969 ps
T342 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/375.prim_prince_test.159288720 Sep 03 11:26:09 PM UTC 24 Sep 03 11:26:27 PM UTC 24 776933299 ps
T343 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/359.prim_prince_test.2932897036 Sep 03 11:25:49 PM UTC 24 Sep 03 11:26:27 PM UTC 24 1737442561 ps
T344 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/330.prim_prince_test.4163425005 Sep 03 11:25:30 PM UTC 24 Sep 03 11:26:30 PM UTC 24 2779484779 ps
T345 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/364.prim_prince_test.4071331997 Sep 03 11:26:01 PM UTC 24 Sep 03 11:26:30 PM UTC 24 1298464512 ps
T346 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/340.prim_prince_test.4238986438 Sep 03 11:25:39 PM UTC 24 Sep 03 11:26:30 PM UTC 24 2320885276 ps
T347 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/338.prim_prince_test.4084880992 Sep 03 11:25:39 PM UTC 24 Sep 03 11:26:30 PM UTC 24 2368250693 ps
T348 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/363.prim_prince_test.3730207932 Sep 03 11:26:00 PM UTC 24 Sep 03 11:26:32 PM UTC 24 1438149768 ps
T349 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/373.prim_prince_test.1644075894 Sep 03 11:26:07 PM UTC 24 Sep 03 11:26:33 PM UTC 24 1148789788 ps
T350 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/352.prim_prince_test.1626795246 Sep 03 11:25:44 PM UTC 24 Sep 03 11:26:33 PM UTC 24 2241319015 ps
T351 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/369.prim_prince_test.3476893929 Sep 03 11:26:03 PM UTC 24 Sep 03 11:26:34 PM UTC 24 1388814383 ps
T352 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/358.prim_prince_test.2557964715 Sep 03 11:25:49 PM UTC 24 Sep 03 11:26:37 PM UTC 24 2153632875 ps
T353 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/331.prim_prince_test.1666055034 Sep 03 11:25:31 PM UTC 24 Sep 03 11:26:37 PM UTC 24 3043904033 ps
T354 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/335.prim_prince_test.1676306912 Sep 03 11:25:35 PM UTC 24 Sep 03 11:26:37 PM UTC 24 2883570585 ps
T355 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/345.prim_prince_test.2976035770 Sep 03 11:25:41 PM UTC 24 Sep 03 11:26:40 PM UTC 24 2734060530 ps
T356 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/332.prim_prince_test.4317590 Sep 03 11:25:31 PM UTC 24 Sep 03 11:26:40 PM UTC 24 3199943050 ps
T357 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/321.prim_prince_test.4101804406 Sep 03 11:25:22 PM UTC 24 Sep 03 11:26:41 PM UTC 24 3651468900 ps
T358 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/391.prim_prince_test.1194377037 Sep 03 11:26:20 PM UTC 24 Sep 03 11:26:43 PM UTC 24 1014599536 ps
T359 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/349.prim_prince_test.3100336514 Sep 03 11:25:42 PM UTC 24 Sep 03 11:26:43 PM UTC 24 2830541262 ps
T360 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/380.prim_prince_test.2772622756 Sep 03 11:26:12 PM UTC 24 Sep 03 11:26:44 PM UTC 24 1429289800 ps
T361 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/346.prim_prince_test.944581367 Sep 03 11:25:41 PM UTC 24 Sep 03 11:26:46 PM UTC 24 2983538398 ps
T362 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/377.prim_prince_test.3687688415 Sep 03 11:26:10 PM UTC 24 Sep 03 11:26:46 PM UTC 24 1656673905 ps
T363 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/372.prim_prince_test.2901899951 Sep 03 11:26:06 PM UTC 24 Sep 03 11:26:46 PM UTC 24 1841430568 ps
T364 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/365.prim_prince_test.664703589 Sep 03 11:26:02 PM UTC 24 Sep 03 11:26:46 PM UTC 24 2036501645 ps
T365 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/336.prim_prince_test.2478625031 Sep 03 11:25:35 PM UTC 24 Sep 03 11:26:47 PM UTC 24 3298642104 ps
T366 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/390.prim_prince_test.4142410723 Sep 03 11:26:19 PM UTC 24 Sep 03 11:26:47 PM UTC 24 1236595526 ps
T367 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/342.prim_prince_test.384885153 Sep 03 11:25:40 PM UTC 24 Sep 03 11:26:48 PM UTC 24 3093984836 ps
T368 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/387.prim_prince_test.3297085102 Sep 03 11:26:18 PM UTC 24 Sep 03 11:26:48 PM UTC 24 1377928280 ps
T369 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/383.prim_prince_test.2108277705 Sep 03 11:26:13 PM UTC 24 Sep 03 11:26:50 PM UTC 24 1652589746 ps
T370 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/347.prim_prince_test.2822898055 Sep 03 11:25:41 PM UTC 24 Sep 03 11:26:50 PM UTC 24 3216800640 ps
T371 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/361.prim_prince_test.509464222 Sep 03 11:25:51 PM UTC 24 Sep 03 11:26:52 PM UTC 24 2772678260 ps
T372 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/370.prim_prince_test.1725754932 Sep 03 11:26:05 PM UTC 24 Sep 03 11:26:52 PM UTC 24 2146237732 ps
T373 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/378.prim_prince_test.4120091562 Sep 03 11:26:11 PM UTC 24 Sep 03 11:26:52 PM UTC 24 1909733969 ps
T374 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/344.prim_prince_test.586684521 Sep 03 11:25:41 PM UTC 24 Sep 03 11:26:53 PM UTC 24 3353982034 ps
T375 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/360.prim_prince_test.2423741217 Sep 03 11:25:49 PM UTC 24 Sep 03 11:26:54 PM UTC 24 2992594849 ps
T376 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/348.prim_prince_test.2993398738 Sep 03 11:25:42 PM UTC 24 Sep 03 11:26:55 PM UTC 24 3401151906 ps
T377 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/368.prim_prince_test.1522949750 Sep 03 11:26:03 PM UTC 24 Sep 03 11:26:56 PM UTC 24 2459894929 ps
T378 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/355.prim_prince_test.4071378763 Sep 03 11:25:46 PM UTC 24 Sep 03 11:26:57 PM UTC 24 3287733653 ps
T379 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/374.prim_prince_test.1475452940 Sep 03 11:26:07 PM UTC 24 Sep 03 11:26:59 PM UTC 24 2385615119 ps
T380 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/385.prim_prince_test.1013600377 Sep 03 11:26:13 PM UTC 24 Sep 03 11:27:00 PM UTC 24 2164163752 ps
T381 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/350.prim_prince_test.3949570398 Sep 03 11:25:42 PM UTC 24 Sep 03 11:27:00 PM UTC 24 3631441816 ps
T382 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/403.prim_prince_test.4219545010 Sep 03 11:26:28 PM UTC 24 Sep 03 11:27:01 PM UTC 24 1504672591 ps
T383 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/362.prim_prince_test.1275195811 Sep 03 11:25:55 PM UTC 24 Sep 03 11:27:07 PM UTC 24 3319808515 ps
T384 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/398.prim_prince_test.636759449 Sep 03 11:26:24 PM UTC 24 Sep 03 11:27:08 PM UTC 24 1993317954 ps
T385 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/397.prim_prince_test.3973969986 Sep 03 11:26:23 PM UTC 24 Sep 03 11:27:08 PM UTC 24 2067651215 ps
T386 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/418.prim_prince_test.3600412909 Sep 03 11:26:42 PM UTC 24 Sep 03 11:27:09 PM UTC 24 1202060198 ps
T387 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/376.prim_prince_test.1308214329 Sep 03 11:26:09 PM UTC 24 Sep 03 11:27:09 PM UTC 24 2753072548 ps
T388 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/425.prim_prince_test.1469926604 Sep 03 11:26:48 PM UTC 24 Sep 03 11:27:11 PM UTC 24 976335899 ps
T389 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/395.prim_prince_test.2549349334 Sep 03 11:26:23 PM UTC 24 Sep 03 11:27:12 PM UTC 24 2261173461 ps
T390 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/415.prim_prince_test.1731025845 Sep 03 11:26:39 PM UTC 24 Sep 03 11:27:14 PM UTC 24 1592328574 ps
T391 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/366.prim_prince_test.2381083820 Sep 03 11:26:02 PM UTC 24 Sep 03 11:27:16 PM UTC 24 3459723599 ps
T392 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/367.prim_prince_test.867496634 Sep 03 11:26:02 PM UTC 24 Sep 03 11:27:17 PM UTC 24 3523250974 ps
T393 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/410.prim_prince_test.4220446892 Sep 03 11:26:34 PM UTC 24 Sep 03 11:27:18 PM UTC 24 1980229574 ps
T394 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/388.prim_prince_test.2406661836 Sep 03 11:26:19 PM UTC 24 Sep 03 11:27:19 PM UTC 24 2795450262 ps
T395 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/412.prim_prince_test.428226531 Sep 03 11:26:35 PM UTC 24 Sep 03 11:27:19 PM UTC 24 1960944385 ps
T396 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/384.prim_prince_test.443797653 Sep 03 11:26:13 PM UTC 24 Sep 03 11:27:21 PM UTC 24 3168067586 ps
T397 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/417.prim_prince_test.3432938655 Sep 03 11:26:41 PM UTC 24 Sep 03 11:27:22 PM UTC 24 1868851726 ps
T398 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/400.prim_prince_test.37694561 Sep 03 11:26:25 PM UTC 24 Sep 03 11:27:23 PM UTC 24 2667458217 ps
T399 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/443.prim_prince_test.3466759712 Sep 03 11:27:02 PM UTC 24 Sep 03 11:27:23 PM UTC 24 963701775 ps
T400 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/435.prim_prince_test.3914483568 Sep 03 11:26:54 PM UTC 24 Sep 03 11:27:23 PM UTC 24 1327918433 ps
T401 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/379.prim_prince_test.3618476537 Sep 03 11:26:12 PM UTC 24 Sep 03 11:27:24 PM UTC 24 3376011916 ps
T402 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/399.prim_prince_test.1585506080 Sep 03 11:26:24 PM UTC 24 Sep 03 11:27:24 PM UTC 24 2742652996 ps
T403 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/430.prim_prince_test.502844269 Sep 03 11:26:51 PM UTC 24 Sep 03 11:27:24 PM UTC 24 1507347533 ps
T404 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/409.prim_prince_test.778530600 Sep 03 11:26:33 PM UTC 24 Sep 03 11:27:25 PM UTC 24 2396674618 ps
T405 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/382.prim_prince_test.899371648 Sep 03 11:26:12 PM UTC 24 Sep 03 11:27:25 PM UTC 24 3369623526 ps
T406 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/414.prim_prince_test.1530703771 Sep 03 11:26:39 PM UTC 24 Sep 03 11:27:25 PM UTC 24 2139120549 ps
T407 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/432.prim_prince_test.169487532 Sep 03 11:26:53 PM UTC 24 Sep 03 11:27:25 PM UTC 24 1481088824 ps
T408 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/394.prim_prince_test.1477767948 Sep 03 11:26:22 PM UTC 24 Sep 03 11:27:26 PM UTC 24 2963201226 ps
T409 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/411.prim_prince_test.497426137 Sep 03 11:26:34 PM UTC 24 Sep 03 11:27:28 PM UTC 24 2499207505 ps
T410 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/381.prim_prince_test.3247328770 Sep 03 11:26:12 PM UTC 24 Sep 03 11:27:28 PM UTC 24 3527579439 ps
T411 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/408.prim_prince_test.3219628079 Sep 03 11:26:32 PM UTC 24 Sep 03 11:27:28 PM UTC 24 2612578766 ps
T412 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/420.prim_prince_test.2851532315 Sep 03 11:26:44 PM UTC 24 Sep 03 11:27:28 PM UTC 24 2024349023 ps
T413 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/439.prim_prince_test.2765036184 Sep 03 11:26:57 PM UTC 24 Sep 03 11:27:29 PM UTC 24 1459008384 ps
T414 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/386.prim_prince_test.2099109964 Sep 03 11:26:15 PM UTC 24 Sep 03 11:27:30 PM UTC 24 3507850930 ps
T415 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/451.prim_prince_test.4015735011 Sep 03 11:27:13 PM UTC 24 Sep 03 11:27:31 PM UTC 24 808455974 ps
T416 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/438.prim_prince_test.2191907723 Sep 03 11:26:56 PM UTC 24 Sep 03 11:27:32 PM UTC 24 1641492626 ps
T417 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/429.prim_prince_test.3375794708 Sep 03 11:26:49 PM UTC 24 Sep 03 11:27:32 PM UTC 24 1961980818 ps
T418 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/406.prim_prince_test.1187821598 Sep 03 11:26:32 PM UTC 24 Sep 03 11:27:33 PM UTC 24 2881668180 ps
T419 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/393.prim_prince_test.2930958348 Sep 03 11:26:22 PM UTC 24 Sep 03 11:27:34 PM UTC 24 3290490274 ps
T420 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/413.prim_prince_test.2538905744 Sep 03 11:26:37 PM UTC 24 Sep 03 11:27:34 PM UTC 24 2626144779 ps
T421 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/392.prim_prince_test.770412008 Sep 03 11:26:20 PM UTC 24 Sep 03 11:27:35 PM UTC 24 3472216698 ps
T422 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/404.prim_prince_test.323508963 Sep 03 11:26:28 PM UTC 24 Sep 03 11:27:35 PM UTC 24 3088983656 ps
T423 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/427.prim_prince_test.175534497 Sep 03 11:26:48 PM UTC 24 Sep 03 11:27:36 PM UTC 24 2211458306 ps
T424 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/401.prim_prince_test.644116189 Sep 03 11:26:27 PM UTC 24 Sep 03 11:27:36 PM UTC 24 3223831675 ps
T425 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/389.prim_prince_test.2101696328 Sep 03 11:26:19 PM UTC 24 Sep 03 11:27:38 PM UTC 24 3719513903 ps
T426 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/396.prim_prince_test.214367909 Sep 03 11:26:23 PM UTC 24 Sep 03 11:27:39 PM UTC 24 3536357995 ps
T427 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/428.prim_prince_test.198597408 Sep 03 11:26:48 PM UTC 24 Sep 03 11:27:39 PM UTC 24 2297927033 ps
T428 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/407.prim_prince_test.1105569822 Sep 03 11:26:32 PM UTC 24 Sep 03 11:27:40 PM UTC 24 3164444919 ps
T429 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/405.prim_prince_test.1945898457 Sep 03 11:26:30 PM UTC 24 Sep 03 11:27:42 PM UTC 24 3319786668 ps
T430 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/446.prim_prince_test.3222054928 Sep 03 11:27:09 PM UTC 24 Sep 03 11:27:46 PM UTC 24 1648767687 ps
T431 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/402.prim_prince_test.3476153700 Sep 03 11:26:27 PM UTC 24 Sep 03 11:27:46 PM UTC 24 3683631198 ps
T432 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/424.prim_prince_test.3817070042 Sep 03 11:26:47 PM UTC 24 Sep 03 11:27:46 PM UTC 24 2742435366 ps
T433 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/437.prim_prince_test.1994835409 Sep 03 11:26:56 PM UTC 24 Sep 03 11:27:47 PM UTC 24 2371381425 ps
T434 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/449.prim_prince_test.1304645797 Sep 03 11:27:10 PM UTC 24 Sep 03 11:27:48 PM UTC 24 1684912068 ps
T435 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/466.prim_prince_test.913930531 Sep 03 11:27:27 PM UTC 24 Sep 03 11:27:48 PM UTC 24 936421489 ps
T436 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/421.prim_prince_test.3464643670 Sep 03 11:26:44 PM UTC 24 Sep 03 11:27:49 PM UTC 24 2949030613 ps
T437 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/458.prim_prince_test.1890785285 Sep 03 11:27:22 PM UTC 24 Sep 03 11:27:50 PM UTC 24 1290435760 ps
T438 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/419.prim_prince_test.739093171 Sep 03 11:26:44 PM UTC 24 Sep 03 11:27:50 PM UTC 24 3034729739 ps
T439 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/465.prim_prince_test.187873492 Sep 03 11:27:26 PM UTC 24 Sep 03 11:27:52 PM UTC 24 1105605165 ps
T440 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/448.prim_prince_test.410379592 Sep 03 11:27:09 PM UTC 24 Sep 03 11:27:52 PM UTC 24 1912687315 ps
T441 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/441.prim_prince_test.779455556 Sep 03 11:26:59 PM UTC 24 Sep 03 11:27:55 PM UTC 24 2590848947 ps
T442 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/445.prim_prince_test.3726249792 Sep 03 11:27:08 PM UTC 24 Sep 03 11:27:56 PM UTC 24 2173764380 ps
T443 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/426.prim_prince_test.1287770299 Sep 03 11:26:48 PM UTC 24 Sep 03 11:27:56 PM UTC 24 3118526225 ps
T444 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/476.prim_prince_test.3170160695 Sep 03 11:27:31 PM UTC 24 Sep 03 11:27:56 PM UTC 24 1140385628 ps
T445 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/442.prim_prince_test.2534635479 Sep 03 11:27:02 PM UTC 24 Sep 03 11:27:57 PM UTC 24 2509099933 ps
T446 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/416.prim_prince_test.63672943 Sep 03 11:26:41 PM UTC 24 Sep 03 11:27:58 PM UTC 24 3531268805 ps
T447 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/444.prim_prince_test.629871987 Sep 03 11:27:02 PM UTC 24 Sep 03 11:27:59 PM UTC 24 2590019557 ps
T448 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/456.prim_prince_test.3119361697 Sep 03 11:27:20 PM UTC 24 Sep 03 11:27:59 PM UTC 24 1813670930 ps
T449 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/474.prim_prince_test.3148300004 Sep 03 11:27:29 PM UTC 24 Sep 03 11:28:01 PM UTC 24 1440856797 ps
T450 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/452.prim_prince_test.1823492975 Sep 03 11:27:15 PM UTC 24 Sep 03 11:28:02 PM UTC 24 2190855954 ps
T451 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/436.prim_prince_test.1931364377 Sep 03 11:26:54 PM UTC 24 Sep 03 11:28:03 PM UTC 24 3210586146 ps
T452 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/472.prim_prince_test.3941783573 Sep 03 11:27:29 PM UTC 24 Sep 03 11:28:04 PM UTC 24 1521377441 ps
T453 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/422.prim_prince_test.1975914344 Sep 03 11:26:47 PM UTC 24 Sep 03 11:28:05 PM UTC 24 3580943686 ps
T454 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/434.prim_prince_test.674249585 Sep 03 11:26:53 PM UTC 24 Sep 03 11:28:07 PM UTC 24 3370193297 ps
T455 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/423.prim_prince_test.3416483613 Sep 03 11:26:47 PM UTC 24 Sep 03 11:28:08 PM UTC 24 3710447256 ps
T456 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/477.prim_prince_test.3018715422 Sep 03 11:27:32 PM UTC 24 Sep 03 11:28:09 PM UTC 24 1677640059 ps
T457 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/431.prim_prince_test.2039446755 Sep 03 11:26:52 PM UTC 24 Sep 03 11:28:10 PM UTC 24 3567022159 ps
T458 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/462.prim_prince_test.2779555782 Sep 03 11:27:25 PM UTC 24 Sep 03 11:28:11 PM UTC 24 2149957990 ps
T459 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/453.prim_prince_test.3838262557 Sep 03 11:27:17 PM UTC 24 Sep 03 11:28:11 PM UTC 24 2445318685 ps
T460 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/433.prim_prince_test.4232589844 Sep 03 11:26:53 PM UTC 24 Sep 03 11:28:12 PM UTC 24 3572619030 ps
T461 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/463.prim_prince_test.1244073029 Sep 03 11:27:26 PM UTC 24 Sep 03 11:28:13 PM UTC 24 2113271890 ps
T462 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/464.prim_prince_test.2843751911 Sep 03 11:27:26 PM UTC 24 Sep 03 11:28:13 PM UTC 24 2159329104 ps
T463 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/460.prim_prince_test.830787723 Sep 03 11:27:24 PM UTC 24 Sep 03 11:28:14 PM UTC 24 2210513807 ps
T464 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/447.prim_prince_test.3772054216 Sep 03 11:27:09 PM UTC 24 Sep 03 11:28:14 PM UTC 24 3031036776 ps
T465 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/471.prim_prince_test.738462891 Sep 03 11:27:29 PM UTC 24 Sep 03 11:28:15 PM UTC 24 2048487891 ps
T466 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/454.prim_prince_test.2217209709 Sep 03 11:27:18 PM UTC 24 Sep 03 11:28:17 PM UTC 24 2720860290 ps
T467 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/480.prim_prince_test.1916275890 Sep 03 11:27:35 PM UTC 24 Sep 03 11:28:17 PM UTC 24 1927478022 ps
T468 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/440.prim_prince_test.3670348007 Sep 03 11:26:58 PM UTC 24 Sep 03 11:28:18 PM UTC 24 3703181906 ps
T469 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/488.prim_prince_test.1825569712 Sep 03 11:27:40 PM UTC 24 Sep 03 11:28:20 PM UTC 24 1773359668 ps
T470 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/485.prim_prince_test.1872206893 Sep 03 11:27:37 PM UTC 24 Sep 03 11:28:20 PM UTC 24 1923360587 ps
T471 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/475.prim_prince_test.3181912478 Sep 03 11:27:31 PM UTC 24 Sep 03 11:28:21 PM UTC 24 2296358676 ps
T472 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/457.prim_prince_test.2825220854 Sep 03 11:27:20 PM UTC 24 Sep 03 11:28:21 PM UTC 24 2833609512 ps
T473 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/450.prim_prince_test.408302970 Sep 03 11:27:12 PM UTC 24 Sep 03 11:28:21 PM UTC 24 3209741344 ps
T474 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/467.prim_prince_test.2237217597 Sep 03 11:27:27 PM UTC 24 Sep 03 11:28:21 PM UTC 24 2506273894 ps
T475 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/497.prim_prince_test.3988135818 Sep 03 11:27:49 PM UTC 24 Sep 03 11:28:22 PM UTC 24 1439456520 ps
T476 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/499.prim_prince_test.2111807764 Sep 03 11:27:52 PM UTC 24 Sep 03 11:28:22 PM UTC 24 1374348528 ps
T477 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/496.prim_prince_test.174813108 Sep 03 11:27:49 PM UTC 24 Sep 03 11:28:23 PM UTC 24 1510609754 ps
T478 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/468.prim_prince_test.2881370955 Sep 03 11:27:27 PM UTC 24 Sep 03 11:28:23 PM UTC 24 2646437972 ps
T479 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/461.prim_prince_test.996556094 Sep 03 11:27:25 PM UTC 24 Sep 03 11:28:26 PM UTC 24 2826097804 ps
T480 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/473.prim_prince_test.1173302531 Sep 03 11:27:29 PM UTC 24 Sep 03 11:28:32 PM UTC 24 2887855514 ps
T481 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/481.prim_prince_test.2178244278 Sep 03 11:27:35 PM UTC 24 Sep 03 11:28:33 PM UTC 24 2634677403 ps
T482 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/469.prim_prince_test.660164678 Sep 03 11:27:27 PM UTC 24 Sep 03 11:28:33 PM UTC 24 3012300735 ps
T483 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/486.prim_prince_test.1112919314 Sep 03 11:27:37 PM UTC 24 Sep 03 11:28:34 PM UTC 24 2548834067 ps
T484 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/482.prim_prince_test.3679235137 Sep 03 11:27:35 PM UTC 24 Sep 03 11:28:38 PM UTC 24 2888056142 ps
T485 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/455.prim_prince_test.2726534366 Sep 03 11:27:20 PM UTC 24 Sep 03 11:28:41 PM UTC 24 3678239119 ps
T486 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/459.prim_prince_test.3830898664 Sep 03 11:27:23 PM UTC 24 Sep 03 11:28:42 PM UTC 24 3563291707 ps
T487 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/487.prim_prince_test.3391704102 Sep 03 11:27:40 PM UTC 24 Sep 03 11:28:47 PM UTC 24 2956873015 ps
T488 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/478.prim_prince_test.4126748404 Sep 03 11:27:33 PM UTC 24 Sep 03 11:28:47 PM UTC 24 3243359970 ps
T489 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/490.prim_prince_test.1277760620 Sep 03 11:27:41 PM UTC 24 Sep 03 11:28:48 PM UTC 24 2882226404 ps
T490 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/470.prim_prince_test.4148741351 Sep 03 11:27:28 PM UTC 24 Sep 03 11:28:49 PM UTC 24 3707446962 ps
T491 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/484.prim_prince_test.3264292040 Sep 03 11:27:36 PM UTC 24 Sep 03 11:28:54 PM UTC 24 3417482019 ps
T492 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/489.prim_prince_test.2689334808 Sep 03 11:27:40 PM UTC 24 Sep 03 11:28:55 PM UTC 24 3229604588 ps
T493 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/495.prim_prince_test.267829060 Sep 03 11:27:49 PM UTC 24 Sep 03 11:28:56 PM UTC 24 2841747341 ps
T494 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/479.prim_prince_test.2541315666 Sep 03 11:27:33 PM UTC 24 Sep 03 11:28:58 PM UTC 24 3696151847 ps
T495 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/483.prim_prince_test.3245073409 Sep 03 11:27:36 PM UTC 24 Sep 03 11:28:59 PM UTC 24 3701606967 ps
T496 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/492.prim_prince_test.36785927 Sep 03 11:27:46 PM UTC 24 Sep 03 11:29:00 PM UTC 24 3330376559 ps
T497 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/493.prim_prince_test.2759446767 Sep 03 11:27:49 PM UTC 24 Sep 03 11:29:05 PM UTC 24 3170903938 ps
T498 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/491.prim_prince_test.3137158158 Sep 03 11:27:42 PM UTC 24 Sep 03 11:29:10 PM UTC 24 3732219176 ps
T499 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/494.prim_prince_test.1390526962 Sep 03 11:27:49 PM UTC 24 Sep 03 11:29:12 PM UTC 24 3542940889 ps
T500 /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/498.prim_prince_test.2329273857 Sep 03 11:27:52 PM UTC 24 Sep 03 11:29:12 PM UTC 24 3408604531 ps

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/0.prim_prince_test.2516914029
Short name T1
Test name
Test status
Simulation time 842265396 ps
CPU time 13.65 seconds
Started Sep 03 11:21:21 PM UTC 24
Finished Sep 03 11:21:39 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2516914029 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 0.prim_prince_test.2516914029
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/0.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/1.prim_prince_test.2483805042
Short name T49
Test name
Test status
Simulation time 3384838502 ps
CPU time 57.82 seconds
Started Sep 03 11:21:21 PM UTC 24
Finished Sep 03 11:22:33 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2483805042 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 1.prim_prince_test.2483805042
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/1.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/10.prim_prince_test.1773370673
Short name T40
Test name
Test status
Simulation time 2891429685 ps
CPU time 50.34 seconds
Started Sep 03 11:21:24 PM UTC 24
Finished Sep 03 11:22:26 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1773370673 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 10.prim_prince_test.1773370673
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/10.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/100.prim_prince_test.1523319743
Short name T126
Test name
Test status
Simulation time 2827405805 ps
CPU time 50.7 seconds
Started Sep 03 11:22:29 PM UTC 24
Finished Sep 03 11:23:31 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1523319743 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 100.prim_prince_test.1523319743
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/100.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/101.prim_prince_test.3786970817
Short name T124
Test name
Test status
Simulation time 2801915883 ps
CPU time 49.59 seconds
Started Sep 03 11:22:29 PM UTC 24
Finished Sep 03 11:23:30 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3786970817 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 101.prim_prince_test.3786970817
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/101.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/102.prim_prince_test.1306906214
Short name T116
Test name
Test status
Simulation time 2536363550 ps
CPU time 44.93 seconds
Started Sep 03 11:22:29 PM UTC 24
Finished Sep 03 11:23:24 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1306906214 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 102.prim_prince_test.1306906214
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/102.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/103.prim_prince_test.691137024
Short name T87
Test name
Test status
Simulation time 1236862892 ps
CPU time 21.65 seconds
Started Sep 03 11:22:30 PM UTC 24
Finished Sep 03 11:22:57 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=691137024 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 103.prim_prince_test.691137024
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/103.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/104.prim_prince_test.895364607
Short name T117
Test name
Test status
Simulation time 2567323139 ps
CPU time 45.68 seconds
Started Sep 03 11:22:30 PM UTC 24
Finished Sep 03 11:23:26 PM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=895364607 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 104.prim_prince_test.895364607
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/104.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/105.prim_prince_test.3205131612
Short name T107
Test name
Test status
Simulation time 2105674145 ps
CPU time 37.32 seconds
Started Sep 03 11:22:31 PM UTC 24
Finished Sep 03 11:23:17 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3205131612 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 105.prim_prince_test.3205131612
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/105.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/106.prim_prince_test.634107748
Short name T122
Test name
Test status
Simulation time 2589724790 ps
CPU time 46.23 seconds
Started Sep 03 11:22:31 PM UTC 24
Finished Sep 03 11:23:28 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=634107748 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 106.prim_prince_test.634107748
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/106.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/107.prim_prince_test.2740725731
Short name T94
Test name
Test status
Simulation time 1656756331 ps
CPU time 29.82 seconds
Started Sep 03 11:22:33 PM UTC 24
Finished Sep 03 11:23:10 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2740725731 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 107.prim_prince_test.2740725731
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/107.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/108.prim_prince_test.2769620978
Short name T121
Test name
Test status
Simulation time 2460810673 ps
CPU time 43.67 seconds
Started Sep 03 11:22:34 PM UTC 24
Finished Sep 03 11:23:28 PM UTC 24
Peak memory 154572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2769620978 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 108.prim_prince_test.2769620978
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/108.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/109.prim_prince_test.3720403881
Short name T141
Test name
Test status
Simulation time 3108208078 ps
CPU time 55.41 seconds
Started Sep 03 11:22:34 PM UTC 24
Finished Sep 03 11:23:42 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3720403881 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 109.prim_prince_test.3720403881
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/109.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/11.prim_prince_test.16907136
Short name T47
Test name
Test status
Simulation time 3086898928 ps
CPU time 54.15 seconds
Started Sep 03 11:21:24 PM UTC 24
Finished Sep 03 11:22:30 PM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16907136 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 11.prim_prince_test.16907136
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/11.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/110.prim_prince_test.2339513916
Short name T120
Test name
Test status
Simulation time 2433396682 ps
CPU time 43.13 seconds
Started Sep 03 11:22:34 PM UTC 24
Finished Sep 03 11:23:27 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2339513916 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 110.prim_prince_test.2339513916
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/110.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/111.prim_prince_test.1953165306
Short name T114
Test name
Test status
Simulation time 2223708926 ps
CPU time 39.54 seconds
Started Sep 03 11:22:35 PM UTC 24
Finished Sep 03 11:23:24 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1953165306 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 111.prim_prince_test.1953165306
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/111.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/112.prim_prince_test.1025652350
Short name T90
Test name
Test status
Simulation time 1396699179 ps
CPU time 25.07 seconds
Started Sep 03 11:22:35 PM UTC 24
Finished Sep 03 11:23:06 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1025652350 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 112.prim_prince_test.1025652350
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/112.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/113.prim_prince_test.3821771827
Short name T104
Test name
Test status
Simulation time 1771694047 ps
CPU time 32.26 seconds
Started Sep 03 11:22:35 PM UTC 24
Finished Sep 03 11:23:15 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3821771827 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 113.prim_prince_test.3821771827
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/113.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/114.prim_prince_test.2457162855
Short name T128
Test name
Test status
Simulation time 2497855854 ps
CPU time 44.9 seconds
Started Sep 03 11:22:36 PM UTC 24
Finished Sep 03 11:23:32 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2457162855 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 114.prim_prince_test.2457162855
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/114.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/115.prim_prince_test.300246263
Short name T125
Test name
Test status
Simulation time 2375659702 ps
CPU time 42.89 seconds
Started Sep 03 11:22:37 PM UTC 24
Finished Sep 03 11:23:30 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=300246263 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 115.prim_prince_test.300246263
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/115.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/116.prim_prince_test.881199773
Short name T115
Test name
Test status
Simulation time 2100509739 ps
CPU time 37.98 seconds
Started Sep 03 11:22:37 PM UTC 24
Finished Sep 03 11:23:24 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=881199773 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 116.prim_prince_test.881199773
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/116.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/117.prim_prince_test.1626872879
Short name T149
Test name
Test status
Simulation time 3322953764 ps
CPU time 59.29 seconds
Started Sep 03 11:22:38 PM UTC 24
Finished Sep 03 11:23:51 PM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1626872879 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 117.prim_prince_test.1626872879
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/117.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/118.prim_prince_test.1080779673
Short name T93
Test name
Test status
Simulation time 1316154338 ps
CPU time 23.76 seconds
Started Sep 03 11:22:39 PM UTC 24
Finished Sep 03 11:23:08 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1080779673 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 118.prim_prince_test.1080779673
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/118.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/119.prim_prince_test.3649511528
Short name T91
Test name
Test status
Simulation time 1184508839 ps
CPU time 21.48 seconds
Started Sep 03 11:22:40 PM UTC 24
Finished Sep 03 11:23:07 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3649511528 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 119.prim_prince_test.3649511528
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/119.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/12.prim_prince_test.321650759
Short name T2
Test name
Test status
Simulation time 1026181415 ps
CPU time 17.59 seconds
Started Sep 03 11:21:24 PM UTC 24
Finished Sep 03 11:21:46 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=321650759 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 12.prim_prince_test.321650759
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/12.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/120.prim_prince_test.2023359214
Short name T140
Test name
Test status
Simulation time 2830422309 ps
CPU time 50.05 seconds
Started Sep 03 11:22:40 PM UTC 24
Finished Sep 03 11:23:41 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2023359214 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 120.prim_prince_test.2023359214
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/120.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/121.prim_prince_test.2761078963
Short name T138
Test name
Test status
Simulation time 2704169282 ps
CPU time 48.19 seconds
Started Sep 03 11:22:41 PM UTC 24
Finished Sep 03 11:23:40 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2761078963 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 121.prim_prince_test.2761078963
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/121.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/122.prim_prince_test.2072447771
Short name T129
Test name
Test status
Simulation time 2298317296 ps
CPU time 41.61 seconds
Started Sep 03 11:22:41 PM UTC 24
Finished Sep 03 11:23:32 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2072447771 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 122.prim_prince_test.2072447771
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/122.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/123.prim_prince_test.2131308126
Short name T147
Test name
Test status
Simulation time 3174598606 ps
CPU time 56.35 seconds
Started Sep 03 11:22:41 PM UTC 24
Finished Sep 03 11:23:50 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2131308126 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 123.prim_prince_test.2131308126
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/123.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/124.prim_prince_test.2940940882
Short name T89
Test name
Test status
Simulation time 766956847 ps
CPU time 14.23 seconds
Started Sep 03 11:22:43 PM UTC 24
Finished Sep 03 11:23:01 PM UTC 24
Peak memory 154348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2940940882 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 124.prim_prince_test.2940940882
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/124.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/125.prim_prince_test.980434396
Short name T145
Test name
Test status
Simulation time 2917788683 ps
CPU time 52.19 seconds
Started Sep 03 11:22:44 PM UTC 24
Finished Sep 03 11:23:48 PM UTC 24
Peak memory 154652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=980434396 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 125.prim_prince_test.980434396
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/125.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/126.prim_prince_test.430959414
Short name T96
Test name
Test status
Simulation time 1222189928 ps
CPU time 22.13 seconds
Started Sep 03 11:22:44 PM UTC 24
Finished Sep 03 11:23:12 PM UTC 24
Peak memory 154580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=430959414 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 126.prim_prince_test.430959414
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/126.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/127.prim_prince_test.1621657350
Short name T135
Test name
Test status
Simulation time 2375650607 ps
CPU time 42.39 seconds
Started Sep 03 11:22:45 PM UTC 24
Finished Sep 03 11:23:37 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1621657350 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 127.prim_prince_test.1621657350
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/127.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/128.prim_prince_test.1611329772
Short name T97
Test name
Test status
Simulation time 1153019241 ps
CPU time 20.77 seconds
Started Sep 03 11:22:46 PM UTC 24
Finished Sep 03 11:23:12 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1611329772 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 128.prim_prince_test.1611329772
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/128.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/129.prim_prince_test.1731495252
Short name T153
Test name
Test status
Simulation time 3138127614 ps
CPU time 55.7 seconds
Started Sep 03 11:22:47 PM UTC 24
Finished Sep 03 11:23:55 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1731495252 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 129.prim_prince_test.1731495252
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/129.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/13.prim_prince_test.1404171212
Short name T42
Test name
Test status
Simulation time 2987005419 ps
CPU time 51.91 seconds
Started Sep 03 11:21:24 PM UTC 24
Finished Sep 03 11:22:28 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1404171212 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 13.prim_prince_test.1404171212
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/13.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/130.prim_prince_test.4023048362
Short name T137
Test name
Test status
Simulation time 2338135827 ps
CPU time 41.88 seconds
Started Sep 03 11:22:47 PM UTC 24
Finished Sep 03 11:23:39 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4023048362 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 130.prim_prince_test.4023048362
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/130.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/131.prim_prince_test.621434901
Short name T98
Test name
Test status
Simulation time 1122984508 ps
CPU time 20.24 seconds
Started Sep 03 11:22:47 PM UTC 24
Finished Sep 03 11:23:13 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=621434901 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 131.prim_prince_test.621434901
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/131.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/132.prim_prince_test.355876033
Short name T113
Test name
Test status
Simulation time 1626634592 ps
CPU time 28.72 seconds
Started Sep 03 11:22:47 PM UTC 24
Finished Sep 03 11:23:23 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=355876033 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 132.prim_prince_test.355876033
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/132.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/133.prim_prince_test.308983880
Short name T165
Test name
Test status
Simulation time 3717126130 ps
CPU time 65.06 seconds
Started Sep 03 11:22:48 PM UTC 24
Finished Sep 03 11:24:08 PM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=308983880 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 133.prim_prince_test.308983880
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/133.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/134.prim_prince_test.3396901219
Short name T151
Test name
Test status
Simulation time 2879891182 ps
CPU time 51.31 seconds
Started Sep 03 11:22:50 PM UTC 24
Finished Sep 03 11:23:53 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3396901219 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 134.prim_prince_test.3396901219
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/134.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/135.prim_prince_test.18591799
Short name T118
Test name
Test status
Simulation time 1604985101 ps
CPU time 29 seconds
Started Sep 03 11:22:50 PM UTC 24
Finished Sep 03 11:23:26 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18591799 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 135.prim_prince_test.18591799
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/135.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/136.prim_prince_test.2817206770
Short name T156
Test name
Test status
Simulation time 3068580496 ps
CPU time 54.5 seconds
Started Sep 03 11:22:52 PM UTC 24
Finished Sep 03 11:23:58 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2817206770 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 136.prim_prince_test.2817206770
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/136.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/137.prim_prince_test.2270958041
Short name T171
Test name
Test status
Simulation time 3713767297 ps
CPU time 66.3 seconds
Started Sep 03 11:22:52 PM UTC 24
Finished Sep 03 11:24:13 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2270958041 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 137.prim_prince_test.2270958041
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/137.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/138.prim_prince_test.714944731
Short name T131
Test name
Test status
Simulation time 1815195913 ps
CPU time 32.63 seconds
Started Sep 03 11:22:53 PM UTC 24
Finished Sep 03 11:23:33 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=714944731 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 138.prim_prince_test.714944731
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/138.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/139.prim_prince_test.802087564
Short name T101
Test name
Test status
Simulation time 935769379 ps
CPU time 16.7 seconds
Started Sep 03 11:22:53 PM UTC 24
Finished Sep 03 11:23:14 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=802087564 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 139.prim_prince_test.802087564
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/139.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/14.prim_prince_test.3684615046
Short name T27
Test name
Test status
Simulation time 2253994158 ps
CPU time 39.28 seconds
Started Sep 03 11:21:24 PM UTC 24
Finished Sep 03 11:22:13 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3684615046 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 14.prim_prince_test.3684615046
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/14.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/140.prim_prince_test.1385877663
Short name T123
Test name
Test status
Simulation time 1593375351 ps
CPU time 28.35 seconds
Started Sep 03 11:22:53 PM UTC 24
Finished Sep 03 11:23:28 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1385877663 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 140.prim_prince_test.1385877663
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/140.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/141.prim_prince_test.1295589051
Short name T144
Test name
Test status
Simulation time 2337407119 ps
CPU time 41.85 seconds
Started Sep 03 11:22:54 PM UTC 24
Finished Sep 03 11:23:45 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1295589051 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 141.prim_prince_test.1295589051
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/141.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/142.prim_prince_test.2799287080
Short name T175
Test name
Test status
Simulation time 3711423856 ps
CPU time 65.13 seconds
Started Sep 03 11:22:55 PM UTC 24
Finished Sep 03 11:24:15 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2799287080 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 142.prim_prince_test.2799287080
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/142.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/143.prim_prince_test.2767884106
Short name T105
Test name
Test status
Simulation time 898712668 ps
CPU time 16.59 seconds
Started Sep 03 11:22:55 PM UTC 24
Finished Sep 03 11:23:16 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2767884106 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 143.prim_prince_test.2767884106
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/143.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/144.prim_prince_test.1500990784
Short name T103
Test name
Test status
Simulation time 822811404 ps
CPU time 14.48 seconds
Started Sep 03 11:22:56 PM UTC 24
Finished Sep 03 11:23:15 PM UTC 24
Peak memory 154348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1500990784 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 144.prim_prince_test.1500990784
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/144.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/145.prim_prince_test.2014171317
Short name T148
Test name
Test status
Simulation time 2457798415 ps
CPU time 43.81 seconds
Started Sep 03 11:22:56 PM UTC 24
Finished Sep 03 11:23:50 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2014171317 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 145.prim_prince_test.2014171317
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/145.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/146.prim_prince_test.2920129883
Short name T109
Test name
Test status
Simulation time 855463406 ps
CPU time 15.3 seconds
Started Sep 03 11:22:58 PM UTC 24
Finished Sep 03 11:23:18 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2920129883 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 146.prim_prince_test.2920129883
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/146.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/147.prim_prince_test.1302332432
Short name T162
Test name
Test status
Simulation time 2978011871 ps
CPU time 53.03 seconds
Started Sep 03 11:22:59 PM UTC 24
Finished Sep 03 11:24:05 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1302332432 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 147.prim_prince_test.1302332432
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/147.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/148.prim_prince_test.2440625495
Short name T136
Test name
Test status
Simulation time 1608381366 ps
CPU time 28.89 seconds
Started Sep 03 11:23:02 PM UTC 24
Finished Sep 03 11:23:39 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2440625495 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 148.prim_prince_test.2440625495
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/148.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/149.prim_prince_test.4237328379
Short name T127
Test name
Test status
Simulation time 1059080989 ps
CPU time 19.12 seconds
Started Sep 03 11:23:07 PM UTC 24
Finished Sep 03 11:23:31 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4237328379 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 149.prim_prince_test.4237328379
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/149.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/15.prim_prince_test.3982012034
Short name T15
Test name
Test status
Simulation time 1867963883 ps
CPU time 32.78 seconds
Started Sep 03 11:21:24 PM UTC 24
Finished Sep 03 11:22:05 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3982012034 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 15.prim_prince_test.3982012034
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/15.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/150.prim_prince_test.3053692031
Short name T172
Test name
Test status
Simulation time 3011833275 ps
CPU time 53.27 seconds
Started Sep 03 11:23:07 PM UTC 24
Finished Sep 03 11:24:13 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3053692031 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 150.prim_prince_test.3053692031
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/150.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/151.prim_prince_test.2681827424
Short name T154
Test name
Test status
Simulation time 2192416303 ps
CPU time 38.54 seconds
Started Sep 03 11:23:09 PM UTC 24
Finished Sep 03 11:23:56 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2681827424 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 151.prim_prince_test.2681827424
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/151.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/152.prim_prince_test.2923686005
Short name T119
Test name
Test status
Simulation time 770388578 ps
CPU time 13.91 seconds
Started Sep 03 11:23:09 PM UTC 24
Finished Sep 03 11:23:26 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2923686005 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 152.prim_prince_test.2923686005
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/152.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/153.prim_prince_test.510385557
Short name T159
Test name
Test status
Simulation time 2267628244 ps
CPU time 40.3 seconds
Started Sep 03 11:23:11 PM UTC 24
Finished Sep 03 11:24:00 PM UTC 24
Peak memory 154520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=510385557 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 153.prim_prince_test.510385557
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/153.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/154.prim_prince_test.3524256437
Short name T134
Test name
Test status
Simulation time 1103175425 ps
CPU time 19.92 seconds
Started Sep 03 11:23:11 PM UTC 24
Finished Sep 03 11:23:36 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3524256437 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 154.prim_prince_test.3524256437
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/154.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/155.prim_prince_test.2208930997
Short name T152
Test name
Test status
Simulation time 1828802721 ps
CPU time 32.92 seconds
Started Sep 03 11:23:13 PM UTC 24
Finished Sep 03 11:23:54 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2208930997 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 155.prim_prince_test.2208930997
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/155.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/156.prim_prince_test.3044919508
Short name T160
Test name
Test status
Simulation time 2261391386 ps
CPU time 39.97 seconds
Started Sep 03 11:23:13 PM UTC 24
Finished Sep 03 11:24:02 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3044919508 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 156.prim_prince_test.3044919508
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/156.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/157.prim_prince_test.3016539330
Short name T174
Test name
Test status
Simulation time 2751117713 ps
CPU time 49.44 seconds
Started Sep 03 11:23:14 PM UTC 24
Finished Sep 03 11:24:15 PM UTC 24
Peak memory 154652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3016539330 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 157.prim_prince_test.3016539330
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/157.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/158.prim_prince_test.3594415775
Short name T155
Test name
Test status
Simulation time 2023745351 ps
CPU time 35.6 seconds
Started Sep 03 11:23:14 PM UTC 24
Finished Sep 03 11:23:58 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3594415775 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 158.prim_prince_test.3594415775
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/158.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/159.prim_prince_test.2886895671
Short name T181
Test name
Test status
Simulation time 3080584553 ps
CPU time 55.42 seconds
Started Sep 03 11:23:14 PM UTC 24
Finished Sep 03 11:24:22 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2886895671 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 159.prim_prince_test.2886895671
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/159.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/16.prim_prince_test.2766250421
Short name T45
Test name
Test status
Simulation time 2937683088 ps
CPU time 51.68 seconds
Started Sep 03 11:21:26 PM UTC 24
Finished Sep 03 11:22:29 PM UTC 24
Peak memory 154588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2766250421 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 16.prim_prince_test.2766250421
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/16.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/160.prim_prince_test.4154349728
Short name T143
Test name
Test status
Simulation time 1289177258 ps
CPU time 22.94 seconds
Started Sep 03 11:23:15 PM UTC 24
Finished Sep 03 11:23:44 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4154349728 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 160.prim_prince_test.4154349728
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/160.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/161.prim_prince_test.4254757481
Short name T142
Test name
Test status
Simulation time 1223185340 ps
CPU time 21.86 seconds
Started Sep 03 11:23:15 PM UTC 24
Finished Sep 03 11:23:43 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4254757481 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 161.prim_prince_test.4254757481
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/161.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/162.prim_prince_test.681320444
Short name T176
Test name
Test status
Simulation time 2714643418 ps
CPU time 48.56 seconds
Started Sep 03 11:23:16 PM UTC 24
Finished Sep 03 11:24:16 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=681320444 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 162.prim_prince_test.681320444
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/162.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/163.prim_prince_test.2552525087
Short name T132
Test name
Test status
Simulation time 779304999 ps
CPU time 14.12 seconds
Started Sep 03 11:23:16 PM UTC 24
Finished Sep 03 11:23:35 PM UTC 24
Peak memory 154348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2552525087 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 163.prim_prince_test.2552525087
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/163.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/164.prim_prince_test.3937905505
Short name T187
Test name
Test status
Simulation time 3066937499 ps
CPU time 54.37 seconds
Started Sep 03 11:23:17 PM UTC 24
Finished Sep 03 11:24:24 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3937905505 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 164.prim_prince_test.3937905505
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/164.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/165.prim_prince_test.982368425
Short name T146
Test name
Test status
Simulation time 1356231591 ps
CPU time 24.53 seconds
Started Sep 03 11:23:17 PM UTC 24
Finished Sep 03 11:23:48 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=982368425 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 165.prim_prince_test.982368425
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/165.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/166.prim_prince_test.2224992000
Short name T198
Test name
Test status
Simulation time 3524032007 ps
CPU time 62.28 seconds
Started Sep 03 11:23:19 PM UTC 24
Finished Sep 03 11:24:35 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2224992000 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 166.prim_prince_test.2224992000
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/166.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/167.prim_prince_test.2563368925
Short name T169
Test name
Test status
Simulation time 2439534761 ps
CPU time 42.96 seconds
Started Sep 03 11:23:19 PM UTC 24
Finished Sep 03 11:24:12 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2563368925 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 167.prim_prince_test.2563368925
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/167.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/168.prim_prince_test.4237160655
Short name T180
Test name
Test status
Simulation time 2890601497 ps
CPU time 51.4 seconds
Started Sep 03 11:23:19 PM UTC 24
Finished Sep 03 11:24:22 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4237160655 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 168.prim_prince_test.4237160655
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/168.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/169.prim_prince_test.2666373119
Short name T184
Test name
Test status
Simulation time 2887269894 ps
CPU time 51.17 seconds
Started Sep 03 11:23:20 PM UTC 24
Finished Sep 03 11:24:23 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2666373119 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 169.prim_prince_test.2666373119
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/169.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/17.prim_prince_test.1760162282
Short name T46
Test name
Test status
Simulation time 2978162284 ps
CPU time 52.13 seconds
Started Sep 03 11:21:26 PM UTC 24
Finished Sep 03 11:22:30 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1760162282 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 17.prim_prince_test.1760162282
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/17.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/170.prim_prince_test.2913659808
Short name T179
Test name
Test status
Simulation time 2721627198 ps
CPU time 48.97 seconds
Started Sep 03 11:23:20 PM UTC 24
Finished Sep 03 11:24:20 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2913659808 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 170.prim_prince_test.2913659808
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/170.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/171.prim_prince_test.2865425898
Short name T203
Test name
Test status
Simulation time 3510846680 ps
CPU time 62.68 seconds
Started Sep 03 11:23:22 PM UTC 24
Finished Sep 03 11:24:38 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2865425898 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 171.prim_prince_test.2865425898
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/171.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/172.prim_prince_test.3698184539
Short name T209
Test name
Test status
Simulation time 3542026019 ps
CPU time 63.2 seconds
Started Sep 03 11:23:24 PM UTC 24
Finished Sep 03 11:24:41 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3698184539 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 172.prim_prince_test.3698184539
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/172.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/173.prim_prince_test.3330124724
Short name T188
Test name
Test status
Simulation time 2773791441 ps
CPU time 48.72 seconds
Started Sep 03 11:23:25 PM UTC 24
Finished Sep 03 11:24:25 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3330124724 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 173.prim_prince_test.3330124724
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/173.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/174.prim_prince_test.3212022486
Short name T192
Test name
Test status
Simulation time 2993808495 ps
CPU time 53.22 seconds
Started Sep 03 11:23:25 PM UTC 24
Finished Sep 03 11:24:30 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3212022486 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 174.prim_prince_test.3212022486
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/174.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/175.prim_prince_test.3235048552
Short name T170
Test name
Test status
Simulation time 2163131960 ps
CPU time 38.07 seconds
Started Sep 03 11:23:25 PM UTC 24
Finished Sep 03 11:24:12 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3235048552 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 175.prim_prince_test.3235048552
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/175.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/176.prim_prince_test.3832628640
Short name T166
Test name
Test status
Simulation time 1919308551 ps
CPU time 34.05 seconds
Started Sep 03 11:23:27 PM UTC 24
Finished Sep 03 11:24:09 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3832628640 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 176.prim_prince_test.3832628640
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/176.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/177.prim_prince_test.610088737
Short name T157
Test name
Test status
Simulation time 1400467038 ps
CPU time 25.6 seconds
Started Sep 03 11:23:27 PM UTC 24
Finished Sep 03 11:23:59 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=610088737 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 177.prim_prince_test.610088737
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/177.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/178.prim_prince_test.2997269387
Short name T168
Test name
Test status
Simulation time 2001905463 ps
CPU time 35.73 seconds
Started Sep 03 11:23:27 PM UTC 24
Finished Sep 03 11:24:11 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2997269387 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 178.prim_prince_test.2997269387
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/178.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/179.prim_prince_test.449243898
Short name T194
Test name
Test status
Simulation time 2898817203 ps
CPU time 51.73 seconds
Started Sep 03 11:23:28 PM UTC 24
Finished Sep 03 11:24:32 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=449243898 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 179.prim_prince_test.449243898
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/179.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/18.prim_prince_test.2574916848
Short name T37
Test name
Test status
Simulation time 2671865265 ps
CPU time 47.16 seconds
Started Sep 03 11:21:26 PM UTC 24
Finished Sep 03 11:22:24 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2574916848 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 18.prim_prince_test.2574916848
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/18.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/180.prim_prince_test.939403604
Short name T206
Test name
Test status
Simulation time 3257949955 ps
CPU time 58.08 seconds
Started Sep 03 11:23:29 PM UTC 24
Finished Sep 03 11:24:40 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=939403604 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 180.prim_prince_test.939403604
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/180.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/181.prim_prince_test.1752557848
Short name T178
Test name
Test status
Simulation time 2343321868 ps
CPU time 41.49 seconds
Started Sep 03 11:23:29 PM UTC 24
Finished Sep 03 11:24:19 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1752557848 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 181.prim_prince_test.1752557848
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/181.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/182.prim_prince_test.3599629385
Short name T215
Test name
Test status
Simulation time 3516528447 ps
CPU time 62.12 seconds
Started Sep 03 11:23:29 PM UTC 24
Finished Sep 03 11:24:45 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3599629385 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 182.prim_prince_test.3599629385
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/182.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/183.prim_prince_test.2220317175
Short name T219
Test name
Test status
Simulation time 3545323059 ps
CPU time 63.04 seconds
Started Sep 03 11:23:31 PM UTC 24
Finished Sep 03 11:24:48 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2220317175 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 183.prim_prince_test.2220317175
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/183.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/184.prim_prince_test.2573706275
Short name T150
Test name
Test status
Simulation time 996031265 ps
CPU time 17.65 seconds
Started Sep 03 11:23:31 PM UTC 24
Finished Sep 03 11:23:53 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2573706275 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 184.prim_prince_test.2573706275
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/184.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/185.prim_prince_test.4198703312
Short name T163
Test name
Test status
Simulation time 1535353132 ps
CPU time 27.4 seconds
Started Sep 03 11:23:32 PM UTC 24
Finished Sep 03 11:24:06 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4198703312 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 185.prim_prince_test.4198703312
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/185.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/186.prim_prince_test.2224682382
Short name T226
Test name
Test status
Simulation time 3644306632 ps
CPU time 65.09 seconds
Started Sep 03 11:23:32 PM UTC 24
Finished Sep 03 11:24:51 PM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2224682382 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 186.prim_prince_test.2224682382
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/186.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/187.prim_prince_test.1281965980
Short name T158
Test name
Test status
Simulation time 1200531018 ps
CPU time 21.82 seconds
Started Sep 03 11:23:32 PM UTC 24
Finished Sep 03 11:23:59 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1281965980 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 187.prim_prince_test.1281965980
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/187.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/188.prim_prince_test.813012487
Short name T182
Test name
Test status
Simulation time 2273527373 ps
CPU time 40.18 seconds
Started Sep 03 11:23:33 PM UTC 24
Finished Sep 03 11:24:23 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=813012487 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 188.prim_prince_test.813012487
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/188.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/189.prim_prince_test.1387169277
Short name T193
Test name
Test status
Simulation time 2664071206 ps
CPU time 47 seconds
Started Sep 03 11:23:33 PM UTC 24
Finished Sep 03 11:24:31 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1387169277 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 189.prim_prince_test.1387169277
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/189.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/19.prim_prince_test.1254376317
Short name T54
Test name
Test status
Simulation time 3086954983 ps
CPU time 55.02 seconds
Started Sep 03 11:21:27 PM UTC 24
Finished Sep 03 11:22:35 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1254376317 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 19.prim_prince_test.1254376317
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/19.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/190.prim_prince_test.3637078269
Short name T204
Test name
Test status
Simulation time 3001487334 ps
CPU time 52.42 seconds
Started Sep 03 11:23:34 PM UTC 24
Finished Sep 03 11:24:39 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3637078269 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 190.prim_prince_test.3637078269
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/190.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/191.prim_prince_test.2630859791
Short name T177
Test name
Test status
Simulation time 1955720762 ps
CPU time 35.08 seconds
Started Sep 03 11:23:35 PM UTC 24
Finished Sep 03 11:24:19 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2630859791 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 191.prim_prince_test.2630859791
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/191.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/192.prim_prince_test.1035313772
Short name T233
Test name
Test status
Simulation time 3656896280 ps
CPU time 65.19 seconds
Started Sep 03 11:23:36 PM UTC 24
Finished Sep 03 11:24:56 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1035313772 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 192.prim_prince_test.1035313772
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/192.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/193.prim_prince_test.2375792808
Short name T216
Test name
Test status
Simulation time 3252061953 ps
CPU time 57.74 seconds
Started Sep 03 11:23:36 PM UTC 24
Finished Sep 03 11:24:47 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2375792808 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 193.prim_prince_test.2375792808
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/193.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/194.prim_prince_test.3062892061
Short name T210
Test name
Test status
Simulation time 2977135470 ps
CPU time 52.29 seconds
Started Sep 03 11:23:38 PM UTC 24
Finished Sep 03 11:24:42 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3062892061 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 194.prim_prince_test.3062892061
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/194.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/195.prim_prince_test.2839782780
Short name T186
Test name
Test status
Simulation time 2020688615 ps
CPU time 35.89 seconds
Started Sep 03 11:23:40 PM UTC 24
Finished Sep 03 11:24:24 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2839782780 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 195.prim_prince_test.2839782780
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/195.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/196.prim_prince_test.3556025474
Short name T164
Test name
Test status
Simulation time 1187329085 ps
CPU time 21.39 seconds
Started Sep 03 11:23:40 PM UTC 24
Finished Sep 03 11:24:06 PM UTC 24
Peak memory 154584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3556025474 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 196.prim_prince_test.3556025474
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/196.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/197.prim_prince_test.1068241334
Short name T202
Test name
Test status
Simulation time 2632104948 ps
CPU time 46.74 seconds
Started Sep 03 11:23:41 PM UTC 24
Finished Sep 03 11:24:38 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1068241334 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 197.prim_prince_test.1068241334
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/197.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/198.prim_prince_test.3618038074
Short name T161
Test name
Test status
Simulation time 877072057 ps
CPU time 16.4 seconds
Started Sep 03 11:23:42 PM UTC 24
Finished Sep 03 11:24:03 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3618038074 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 198.prim_prince_test.3618038074
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/198.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/199.prim_prince_test.3776681715
Short name T195
Test name
Test status
Simulation time 2275455454 ps
CPU time 40.67 seconds
Started Sep 03 11:23:42 PM UTC 24
Finished Sep 03 11:24:32 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3776681715 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 199.prim_prince_test.3776681715
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/199.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/2.prim_prince_test.932604895
Short name T5
Test name
Test status
Simulation time 1231375439 ps
CPU time 20.9 seconds
Started Sep 03 11:21:22 PM UTC 24
Finished Sep 03 11:21:49 PM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=932604895 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 2.prim_prince_test.932604895
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/2.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/20.prim_prince_test.3303212149
Short name T72
Test name
Test status
Simulation time 3678643230 ps
CPU time 64.96 seconds
Started Sep 03 11:21:27 PM UTC 24
Finished Sep 03 11:22:47 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3303212149 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 20.prim_prince_test.3303212149
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/20.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/200.prim_prince_test.2931394688
Short name T220
Test name
Test status
Simulation time 2990070554 ps
CPU time 53.28 seconds
Started Sep 03 11:23:43 PM UTC 24
Finished Sep 03 11:24:48 PM UTC 24
Peak memory 154264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2931394688 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 200.prim_prince_test.2931394688
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/200.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/201.prim_prince_test.3266088107
Short name T167
Test name
Test status
Simulation time 1163923774 ps
CPU time 21.13 seconds
Started Sep 03 11:23:43 PM UTC 24
Finished Sep 03 11:24:09 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3266088107 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 201.prim_prince_test.3266088107
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/201.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/202.prim_prince_test.3783747809
Short name T183
Test name
Test status
Simulation time 1728205424 ps
CPU time 30.3 seconds
Started Sep 03 11:23:45 PM UTC 24
Finished Sep 03 11:24:23 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3783747809 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 202.prim_prince_test.3783747809
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/202.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/203.prim_prince_test.1697121038
Short name T223
Test name
Test status
Simulation time 2957273077 ps
CPU time 52.83 seconds
Started Sep 03 11:23:46 PM UTC 24
Finished Sep 03 11:24:51 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1697121038 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 203.prim_prince_test.1697121038
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/203.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/204.prim_prince_test.773702593
Short name T245
Test name
Test status
Simulation time 3736813306 ps
CPU time 66.53 seconds
Started Sep 03 11:23:48 PM UTC 24
Finished Sep 03 11:25:10 PM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=773702593 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 204.prim_prince_test.773702593
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/204.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/205.prim_prince_test.1142041815
Short name T230
Test name
Test status
Simulation time 2971651797 ps
CPU time 52.6 seconds
Started Sep 03 11:23:49 PM UTC 24
Finished Sep 03 11:24:54 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1142041815 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 205.prim_prince_test.1142041815
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/205.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/206.prim_prince_test.105820060
Short name T213
Test name
Test status
Simulation time 2411814156 ps
CPU time 43.36 seconds
Started Sep 03 11:23:50 PM UTC 24
Finished Sep 03 11:24:44 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=105820060 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 206.prim_prince_test.105820060
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/206.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/207.prim_prince_test.389333474
Short name T207
Test name
Test status
Simulation time 2186328525 ps
CPU time 39.2 seconds
Started Sep 03 11:23:52 PM UTC 24
Finished Sep 03 11:24:40 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=389333474 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 207.prim_prince_test.389333474
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/207.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/208.prim_prince_test.907771884
Short name T211
Test name
Test status
Simulation time 2303730248 ps
CPU time 40.85 seconds
Started Sep 03 11:23:52 PM UTC 24
Finished Sep 03 11:24:42 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=907771884 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 208.prim_prince_test.907771884
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/208.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/209.prim_prince_test.313812952
Short name T189
Test name
Test status
Simulation time 1451446399 ps
CPU time 26.27 seconds
Started Sep 03 11:23:54 PM UTC 24
Finished Sep 03 11:24:26 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=313812952 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 209.prim_prince_test.313812952
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/209.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/21.prim_prince_test.1373441233
Short name T20
Test name
Test status
Simulation time 1848413148 ps
CPU time 32.5 seconds
Started Sep 03 11:21:27 PM UTC 24
Finished Sep 03 11:22:07 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1373441233 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 21.prim_prince_test.1373441233
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/21.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/210.prim_prince_test.715738340
Short name T236
Test name
Test status
Simulation time 3031749562 ps
CPU time 53.9 seconds
Started Sep 03 11:23:54 PM UTC 24
Finished Sep 03 11:25:00 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=715738340 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 210.prim_prince_test.715738340
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/210.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/211.prim_prince_test.573074636
Short name T173
Test name
Test status
Simulation time 802265589 ps
CPU time 14.62 seconds
Started Sep 03 11:23:55 PM UTC 24
Finished Sep 03 11:24:13 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=573074636 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 211.prim_prince_test.573074636
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/211.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/212.prim_prince_test.3218673893
Short name T228
Test name
Test status
Simulation time 2543298197 ps
CPU time 45.85 seconds
Started Sep 03 11:23:56 PM UTC 24
Finished Sep 03 11:24:52 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3218673893 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 212.prim_prince_test.3218673893
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/212.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/213.prim_prince_test.168389908
Short name T224
Test name
Test status
Simulation time 2447058109 ps
CPU time 43.97 seconds
Started Sep 03 11:23:57 PM UTC 24
Finished Sep 03 11:24:51 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=168389908 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 213.prim_prince_test.168389908
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/213.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/214.prim_prince_test.3860499361
Short name T231
Test name
Test status
Simulation time 2539416225 ps
CPU time 44.91 seconds
Started Sep 03 11:23:59 PM UTC 24
Finished Sep 03 11:24:54 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3860499361 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 214.prim_prince_test.3860499361
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/214.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/215.prim_prince_test.618747714
Short name T260
Test name
Test status
Simulation time 3654420857 ps
CPU time 65.12 seconds
Started Sep 03 11:23:59 PM UTC 24
Finished Sep 03 11:25:19 PM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=618747714 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 215.prim_prince_test.618747714
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/215.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/216.prim_prince_test.779601391
Short name T191
Test name
Test status
Simulation time 1338824408 ps
CPU time 24.4 seconds
Started Sep 03 11:23:59 PM UTC 24
Finished Sep 03 11:24:30 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=779601391 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 216.prim_prince_test.779601391
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/216.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/217.prim_prince_test.1378446395
Short name T222
Test name
Test status
Simulation time 2268960582 ps
CPU time 40.79 seconds
Started Sep 03 11:24:00 PM UTC 24
Finished Sep 03 11:24:51 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1378446395 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 217.prim_prince_test.1378446395
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/217.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/218.prim_prince_test.1673375603
Short name T201
Test name
Test status
Simulation time 1583322065 ps
CPU time 28.52 seconds
Started Sep 03 11:24:02 PM UTC 24
Finished Sep 03 11:24:37 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1673375603 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 218.prim_prince_test.1673375603
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/218.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/219.prim_prince_test.1457737479
Short name T212
Test name
Test status
Simulation time 1804739188 ps
CPU time 32.12 seconds
Started Sep 03 11:24:04 PM UTC 24
Finished Sep 03 11:24:43 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1457737479 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 219.prim_prince_test.1457737479
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/219.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/22.prim_prince_test.2737664169
Short name T7
Test name
Test status
Simulation time 1067685862 ps
CPU time 18.99 seconds
Started Sep 03 11:21:27 PM UTC 24
Finished Sep 03 11:21:51 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2737664169 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 22.prim_prince_test.2737664169
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/22.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/220.prim_prince_test.213318041
Short name T185
Test name
Test status
Simulation time 886016709 ps
CPU time 15.74 seconds
Started Sep 03 11:24:04 PM UTC 24
Finished Sep 03 11:24:24 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=213318041 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 220.prim_prince_test.213318041
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/220.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/221.prim_prince_test.3613069797
Short name T225
Test name
Test status
Simulation time 2109892439 ps
CPU time 37.85 seconds
Started Sep 03 11:24:05 PM UTC 24
Finished Sep 03 11:24:51 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3613069797 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 221.prim_prince_test.3613069797
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/221.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/222.prim_prince_test.3704625346
Short name T218
Test name
Test status
Simulation time 1892953370 ps
CPU time 33.76 seconds
Started Sep 03 11:24:06 PM UTC 24
Finished Sep 03 11:24:48 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3704625346 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 222.prim_prince_test.3704625346
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/222.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/223.prim_prince_test.1178167078
Short name T197
Test name
Test status
Simulation time 1225838495 ps
CPU time 21.7 seconds
Started Sep 03 11:24:07 PM UTC 24
Finished Sep 03 11:24:34 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1178167078 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 223.prim_prince_test.1178167078
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/223.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/224.prim_prince_test.1805973528
Short name T190
Test name
Test status
Simulation time 848666792 ps
CPU time 15.67 seconds
Started Sep 03 11:24:07 PM UTC 24
Finished Sep 03 11:24:27 PM UTC 24
Peak memory 154348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1805973528 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 224.prim_prince_test.1805973528
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/224.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/225.prim_prince_test.1613658598
Short name T208
Test name
Test status
Simulation time 1400026873 ps
CPU time 24.73 seconds
Started Sep 03 11:24:09 PM UTC 24
Finished Sep 03 11:24:40 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1613658598 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 225.prim_prince_test.1613658598
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/225.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/226.prim_prince_test.3242360230
Short name T199
Test name
Test status
Simulation time 1078833791 ps
CPU time 19.66 seconds
Started Sep 03 11:24:10 PM UTC 24
Finished Sep 03 11:24:35 PM UTC 24
Peak memory 154348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3242360230 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 226.prim_prince_test.3242360230
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/226.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/227.prim_prince_test.210101183
Short name T241
Test name
Test status
Simulation time 2670788394 ps
CPU time 46.96 seconds
Started Sep 03 11:24:10 PM UTC 24
Finished Sep 03 11:25:08 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=210101183 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 227.prim_prince_test.210101183
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/227.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/228.prim_prince_test.1975210208
Short name T255
Test name
Test status
Simulation time 2941300228 ps
CPU time 52.3 seconds
Started Sep 03 11:24:12 PM UTC 24
Finished Sep 03 11:25:16 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1975210208 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 228.prim_prince_test.1975210208
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/228.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/229.prim_prince_test.3691020067
Short name T242
Test name
Test status
Simulation time 2556879843 ps
CPU time 45.23 seconds
Started Sep 03 11:24:12 PM UTC 24
Finished Sep 03 11:25:08 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3691020067 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 229.prim_prince_test.3691020067
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/229.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/23.prim_prince_test.3928223305
Short name T31
Test name
Test status
Simulation time 2444196248 ps
CPU time 42.35 seconds
Started Sep 03 11:21:27 PM UTC 24
Finished Sep 03 11:22:20 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3928223305 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 23.prim_prince_test.3928223305
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/23.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/230.prim_prince_test.2658650035
Short name T196
Test name
Test status
Simulation time 905072890 ps
CPU time 16.55 seconds
Started Sep 03 11:24:13 PM UTC 24
Finished Sep 03 11:24:33 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2658650035 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 230.prim_prince_test.2658650035
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/230.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/231.prim_prince_test.3141901979
Short name T257
Test name
Test status
Simulation time 2917240504 ps
CPU time 51.59 seconds
Started Sep 03 11:24:14 PM UTC 24
Finished Sep 03 11:25:17 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3141901979 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 231.prim_prince_test.3141901979
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/231.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/232.prim_prince_test.569379922
Short name T200
Test name
Test status
Simulation time 1010564949 ps
CPU time 18.23 seconds
Started Sep 03 11:24:14 PM UTC 24
Finished Sep 03 11:24:37 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=569379922 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 232.prim_prince_test.569379922
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/232.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/233.prim_prince_test.1077543224
Short name T205
Test name
Test status
Simulation time 1110613761 ps
CPU time 19.73 seconds
Started Sep 03 11:24:15 PM UTC 24
Finished Sep 03 11:24:40 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1077543224 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 233.prim_prince_test.1077543224
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/233.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/234.prim_prince_test.1580711476
Short name T252
Test name
Test status
Simulation time 2681337806 ps
CPU time 47.61 seconds
Started Sep 03 11:24:16 PM UTC 24
Finished Sep 03 11:25:14 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1580711476 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 234.prim_prince_test.1580711476
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/234.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/235.prim_prince_test.3521442312
Short name T235
Test name
Test status
Simulation time 1907183756 ps
CPU time 34.02 seconds
Started Sep 03 11:24:16 PM UTC 24
Finished Sep 03 11:24:58 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3521442312 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 235.prim_prince_test.3521442312
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/235.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/236.prim_prince_test.79188033
Short name T251
Test name
Test status
Simulation time 2603281105 ps
CPU time 46.53 seconds
Started Sep 03 11:24:17 PM UTC 24
Finished Sep 03 11:25:14 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=79188033 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 236.prim_prince_test.79188033
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/236.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/237.prim_prince_test.1414905145
Short name T247
Test name
Test status
Simulation time 2404342895 ps
CPU time 42.12 seconds
Started Sep 03 11:24:19 PM UTC 24
Finished Sep 03 11:25:11 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1414905145 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 237.prim_prince_test.1414905145
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/237.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/238.prim_prince_test.1023613174
Short name T221
Test name
Test status
Simulation time 1256829338 ps
CPU time 22.54 seconds
Started Sep 03 11:24:20 PM UTC 24
Finished Sep 03 11:24:48 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1023613174 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 238.prim_prince_test.1023613174
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/238.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/239.prim_prince_test.2406655570
Short name T244
Test name
Test status
Simulation time 2217707053 ps
CPU time 39.39 seconds
Started Sep 03 11:24:20 PM UTC 24
Finished Sep 03 11:25:09 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2406655570 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 239.prim_prince_test.2406655570
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/239.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/24.prim_prince_test.598630477
Short name T61
Test name
Test status
Simulation time 3354707786 ps
CPU time 58.6 seconds
Started Sep 03 11:21:27 PM UTC 24
Finished Sep 03 11:22:39 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=598630477 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 24.prim_prince_test.598630477
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/24.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/240.prim_prince_test.2099543097
Short name T214
Test name
Test status
Simulation time 974670181 ps
CPU time 17.42 seconds
Started Sep 03 11:24:23 PM UTC 24
Finished Sep 03 11:24:44 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2099543097 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 240.prim_prince_test.2099543097
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/240.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/241.prim_prince_test.387315763
Short name T240
Test name
Test status
Simulation time 2080594857 ps
CPU time 36.22 seconds
Started Sep 03 11:24:23 PM UTC 24
Finished Sep 03 11:25:07 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=387315763 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 241.prim_prince_test.387315763
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/241.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/242.prim_prince_test.2756411307
Short name T237
Test name
Test status
Simulation time 1652122912 ps
CPU time 29.5 seconds
Started Sep 03 11:24:24 PM UTC 24
Finished Sep 03 11:25:00 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2756411307 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 242.prim_prince_test.2756411307
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/242.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/243.prim_prince_test.316614023
Short name T238
Test name
Test status
Simulation time 1710413932 ps
CPU time 30.6 seconds
Started Sep 03 11:24:24 PM UTC 24
Finished Sep 03 11:25:01 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=316614023 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 243.prim_prince_test.316614023
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/243.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/244.prim_prince_test.1967279195
Short name T282
Test name
Test status
Simulation time 3528081252 ps
CPU time 61.57 seconds
Started Sep 03 11:24:24 PM UTC 24
Finished Sep 03 11:25:39 PM UTC 24
Peak memory 156524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1967279195 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 244.prim_prince_test.1967279195
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/244.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/245.prim_prince_test.2858644286
Short name T246
Test name
Test status
Simulation time 2037375780 ps
CPU time 36.29 seconds
Started Sep 03 11:24:25 PM UTC 24
Finished Sep 03 11:25:10 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2858644286 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 245.prim_prince_test.2858644286
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/245.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/246.prim_prince_test.2910357899
Short name T234
Test name
Test status
Simulation time 1407914323 ps
CPU time 25.05 seconds
Started Sep 03 11:24:25 PM UTC 24
Finished Sep 03 11:24:56 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2910357899 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 246.prim_prince_test.2910357899
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/246.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/247.prim_prince_test.1939911425
Short name T269
Test name
Test status
Simulation time 2976908729 ps
CPU time 51.62 seconds
Started Sep 03 11:24:25 PM UTC 24
Finished Sep 03 11:25:28 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1939911425 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 247.prim_prince_test.1939911425
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/247.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/248.prim_prince_test.2370045018
Short name T217
Test name
Test status
Simulation time 910291721 ps
CPU time 16.67 seconds
Started Sep 03 11:24:26 PM UTC 24
Finished Sep 03 11:24:47 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2370045018 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 248.prim_prince_test.2370045018
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/248.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/249.prim_prince_test.1980664337
Short name T227
Test name
Test status
Simulation time 1074446227 ps
CPU time 19.72 seconds
Started Sep 03 11:24:27 PM UTC 24
Finished Sep 03 11:24:52 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1980664337 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 249.prim_prince_test.1980664337
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/249.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/25.prim_prince_test.998383156
Short name T24
Test name
Test status
Simulation time 2032004396 ps
CPU time 35.97 seconds
Started Sep 03 11:21:27 PM UTC 24
Finished Sep 03 11:22:12 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=998383156 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 25.prim_prince_test.998383156
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/25.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/250.prim_prince_test.3815423686
Short name T232
Test name
Test status
Simulation time 1212269793 ps
CPU time 21.77 seconds
Started Sep 03 11:24:27 PM UTC 24
Finished Sep 03 11:24:55 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3815423686 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 250.prim_prince_test.3815423686
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/250.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/251.prim_prince_test.1896080159
Short name T254
Test name
Test status
Simulation time 2034815477 ps
CPU time 36.43 seconds
Started Sep 03 11:24:31 PM UTC 24
Finished Sep 03 11:25:16 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1896080159 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 251.prim_prince_test.1896080159
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/251.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/252.prim_prince_test.505848837
Short name T294
Test name
Test status
Simulation time 3430693128 ps
CPU time 60.61 seconds
Started Sep 03 11:24:31 PM UTC 24
Finished Sep 03 11:25:45 PM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=505848837 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 252.prim_prince_test.505848837
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/252.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/253.prim_prince_test.4036717862
Short name T253
Test name
Test status
Simulation time 1948288123 ps
CPU time 34.68 seconds
Started Sep 03 11:24:32 PM UTC 24
Finished Sep 03 11:25:15 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4036717862 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 253.prim_prince_test.4036717862
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/253.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/254.prim_prince_test.2638177248
Short name T285
Test name
Test status
Simulation time 3054819944 ps
CPU time 54.26 seconds
Started Sep 03 11:24:33 PM UTC 24
Finished Sep 03 11:25:39 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2638177248 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 254.prim_prince_test.2638177248
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/254.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/255.prim_prince_test.3335123587
Short name T256
Test name
Test status
Simulation time 2003425480 ps
CPU time 35.26 seconds
Started Sep 03 11:24:33 PM UTC 24
Finished Sep 03 11:25:17 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3335123587 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 255.prim_prince_test.3335123587
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/255.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/256.prim_prince_test.3960793288
Short name T275
Test name
Test status
Simulation time 2808648866 ps
CPU time 49.54 seconds
Started Sep 03 11:24:34 PM UTC 24
Finished Sep 03 11:25:35 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3960793288 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 256.prim_prince_test.3960793288
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/256.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/257.prim_prince_test.283556701
Short name T267
Test name
Test status
Simulation time 2287035983 ps
CPU time 40.77 seconds
Started Sep 03 11:24:35 PM UTC 24
Finished Sep 03 11:25:26 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=283556701 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 257.prim_prince_test.283556701
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/257.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/258.prim_prince_test.1057737311
Short name T248
Test name
Test status
Simulation time 1666372756 ps
CPU time 29.3 seconds
Started Sep 03 11:24:35 PM UTC 24
Finished Sep 03 11:25:12 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1057737311 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 258.prim_prince_test.1057737311
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/258.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/259.prim_prince_test.3619952982
Short name T229
Test name
Test status
Simulation time 783860946 ps
CPU time 13.88 seconds
Started Sep 03 11:24:35 PM UTC 24
Finished Sep 03 11:24:53 PM UTC 24
Peak memory 154348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3619952982 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 259.prim_prince_test.3619952982
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/259.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/26.prim_prince_test.411360137
Short name T13
Test name
Test status
Simulation time 1504815086 ps
CPU time 27 seconds
Started Sep 03 11:21:29 PM UTC 24
Finished Sep 03 11:22:03 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=411360137 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 26.prim_prince_test.411360137
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/26.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/260.prim_prince_test.594028231
Short name T292
Test name
Test status
Simulation time 3088663883 ps
CPU time 54.4 seconds
Started Sep 03 11:24:37 PM UTC 24
Finished Sep 03 11:25:44 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=594028231 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 260.prim_prince_test.594028231
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/260.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/261.prim_prince_test.2893543487
Short name T301
Test name
Test status
Simulation time 3592422346 ps
CPU time 63.35 seconds
Started Sep 03 11:24:37 PM UTC 24
Finished Sep 03 11:25:55 PM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2893543487 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 261.prim_prince_test.2893543487
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/261.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/262.prim_prince_test.3494624565
Short name T278
Test name
Test status
Simulation time 2730301334 ps
CPU time 48.23 seconds
Started Sep 03 11:24:39 PM UTC 24
Finished Sep 03 11:25:38 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3494624565 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 262.prim_prince_test.3494624565
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/262.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/263.prim_prince_test.3944788871
Short name T249
Test name
Test status
Simulation time 1494330620 ps
CPU time 26.57 seconds
Started Sep 03 11:24:40 PM UTC 24
Finished Sep 03 11:25:13 PM UTC 24
Peak memory 154552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3944788871 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 263.prim_prince_test.3944788871
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/263.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/264.prim_prince_test.3337573885
Short name T277
Test name
Test status
Simulation time 2575604860 ps
CPU time 45.94 seconds
Started Sep 03 11:24:40 PM UTC 24
Finished Sep 03 11:25:36 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3337573885 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 264.prim_prince_test.3337573885
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/264.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/265.prim_prince_test.3548090460
Short name T262
Test name
Test status
Simulation time 1854250439 ps
CPU time 32.63 seconds
Started Sep 03 11:24:41 PM UTC 24
Finished Sep 03 11:25:22 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3548090460 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 265.prim_prince_test.3548090460
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/265.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/266.prim_prince_test.3072392505
Short name T288
Test name
Test status
Simulation time 2733652917 ps
CPU time 48.52 seconds
Started Sep 03 11:24:41 PM UTC 24
Finished Sep 03 11:25:41 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3072392505 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 266.prim_prince_test.3072392505
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/266.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/267.prim_prince_test.2206121193
Short name T295
Test name
Test status
Simulation time 2963437637 ps
CPU time 52.56 seconds
Started Sep 03 11:24:41 PM UTC 24
Finished Sep 03 11:25:46 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2206121193 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 267.prim_prince_test.2206121193
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/267.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/268.prim_prince_test.4230936578
Short name T272
Test name
Test status
Simulation time 2260737032 ps
CPU time 40.07 seconds
Started Sep 03 11:24:41 PM UTC 24
Finished Sep 03 11:25:31 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4230936578 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 268.prim_prince_test.4230936578
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/268.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/269.prim_prince_test.1302475202
Short name T263
Test name
Test status
Simulation time 1767262018 ps
CPU time 31.74 seconds
Started Sep 03 11:24:42 PM UTC 24
Finished Sep 03 11:25:22 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1302475202 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 269.prim_prince_test.1302475202
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/269.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/27.prim_prince_test.902928479
Short name T73
Test name
Test status
Simulation time 3529711060 ps
CPU time 61.95 seconds
Started Sep 03 11:21:30 PM UTC 24
Finished Sep 03 11:22:47 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=902928479 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 27.prim_prince_test.902928479
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/27.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/270.prim_prince_test.1945525557
Short name T280
Test name
Test status
Simulation time 2579044334 ps
CPU time 45.2 seconds
Started Sep 03 11:24:42 PM UTC 24
Finished Sep 03 11:25:38 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1945525557 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 270.prim_prince_test.1945525557
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/270.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/271.prim_prince_test.1651942161
Short name T239
Test name
Test status
Simulation time 857769045 ps
CPU time 15.77 seconds
Started Sep 03 11:24:42 PM UTC 24
Finished Sep 03 11:25:02 PM UTC 24
Peak memory 154348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1651942161 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 271.prim_prince_test.1651942161
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/271.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/272.prim_prince_test.2827765209
Short name T266
Test name
Test status
Simulation time 1813333358 ps
CPU time 32.7 seconds
Started Sep 03 11:24:45 PM UTC 24
Finished Sep 03 11:25:25 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2827765209 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 272.prim_prince_test.2827765209
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/272.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/273.prim_prince_test.900651184
Short name T302
Test name
Test status
Simulation time 3431180077 ps
CPU time 60.33 seconds
Started Sep 03 11:24:45 PM UTC 24
Finished Sep 03 11:25:59 PM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=900651184 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 273.prim_prince_test.900651184
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/273.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/274.prim_prince_test.425986361
Short name T243
Test name
Test status
Simulation time 1006906445 ps
CPU time 17.82 seconds
Started Sep 03 11:24:46 PM UTC 24
Finished Sep 03 11:25:08 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=425986361 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 274.prim_prince_test.425986361
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/274.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/275.prim_prince_test.1626134355
Short name T258
Test name
Test status
Simulation time 1426108577 ps
CPU time 25.49 seconds
Started Sep 03 11:24:46 PM UTC 24
Finished Sep 03 11:25:17 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1626134355 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 275.prim_prince_test.1626134355
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/275.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/276.prim_prince_test.952679044
Short name T314
Test name
Test status
Simulation time 3692722970 ps
CPU time 64.94 seconds
Started Sep 03 11:24:48 PM UTC 24
Finished Sep 03 11:26:08 PM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=952679044 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 276.prim_prince_test.952679044
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/276.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/277.prim_prince_test.157242409
Short name T270
Test name
Test status
Simulation time 1842717881 ps
CPU time 32.58 seconds
Started Sep 03 11:24:48 PM UTC 24
Finished Sep 03 11:25:29 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=157242409 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 277.prim_prince_test.157242409
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/277.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/278.prim_prince_test.3422035745
Short name T271
Test name
Test status
Simulation time 1896835833 ps
CPU time 33.65 seconds
Started Sep 03 11:24:48 PM UTC 24
Finished Sep 03 11:25:30 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3422035745 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 278.prim_prince_test.3422035745
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/278.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/279.prim_prince_test.1642337665
Short name T250
Test name
Test status
Simulation time 1037940478 ps
CPU time 18.5 seconds
Started Sep 03 11:24:49 PM UTC 24
Finished Sep 03 11:25:13 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1642337665 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 279.prim_prince_test.1642337665
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/279.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/28.prim_prince_test.644731899
Short name T19
Test name
Test status
Simulation time 1646829965 ps
CPU time 29.13 seconds
Started Sep 03 11:21:30 PM UTC 24
Finished Sep 03 11:22:07 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=644731899 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 28.prim_prince_test.644731899
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/28.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/280.prim_prince_test.1481069947
Short name T305
Test name
Test status
Simulation time 3298934852 ps
CPU time 58 seconds
Started Sep 03 11:24:49 PM UTC 24
Finished Sep 03 11:26:01 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1481069947 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 280.prim_prince_test.1481069947
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/280.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/281.prim_prince_test.3917458116
Short name T274
Test name
Test status
Simulation time 2034051374 ps
CPU time 36.29 seconds
Started Sep 03 11:24:49 PM UTC 24
Finished Sep 03 11:25:35 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3917458116 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 281.prim_prince_test.3917458116
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/281.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/282.prim_prince_test.3875320821
Short name T261
Test name
Test status
Simulation time 1294971098 ps
CPU time 23.01 seconds
Started Sep 03 11:24:52 PM UTC 24
Finished Sep 03 11:25:21 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3875320821 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 282.prim_prince_test.3875320821
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/282.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/283.prim_prince_test.3523119629
Short name T310
Test name
Test status
Simulation time 3342939983 ps
CPU time 59.14 seconds
Started Sep 03 11:24:52 PM UTC 24
Finished Sep 03 11:26:04 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3523119629 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 283.prim_prince_test.3523119629
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/283.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/284.prim_prince_test.4110766343
Short name T318
Test name
Test status
Simulation time 3650319979 ps
CPU time 64.21 seconds
Started Sep 03 11:24:52 PM UTC 24
Finished Sep 03 11:26:11 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4110766343 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 284.prim_prince_test.4110766343
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/284.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/285.prim_prince_test.1013680085
Short name T286
Test name
Test status
Simulation time 2171833861 ps
CPU time 38.77 seconds
Started Sep 03 11:24:52 PM UTC 24
Finished Sep 03 11:25:40 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1013680085 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 285.prim_prince_test.1013680085
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/285.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/286.prim_prince_test.3079721324
Short name T313
Test name
Test status
Simulation time 3399113290 ps
CPU time 60.11 seconds
Started Sep 03 11:24:53 PM UTC 24
Finished Sep 03 11:26:07 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3079721324 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 286.prim_prince_test.3079721324
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/286.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/287.prim_prince_test.4070818415
Short name T293
Test name
Test status
Simulation time 2333941183 ps
CPU time 41.78 seconds
Started Sep 03 11:24:53 PM UTC 24
Finished Sep 03 11:25:44 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4070818415 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 287.prim_prince_test.4070818415
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/287.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/288.prim_prince_test.3614084919
Short name T264
Test name
Test status
Simulation time 1309256736 ps
CPU time 22.99 seconds
Started Sep 03 11:24:53 PM UTC 24
Finished Sep 03 11:25:22 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3614084919 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 288.prim_prince_test.3614084919
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/288.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/289.prim_prince_test.817816674
Short name T265
Test name
Test status
Simulation time 1228428145 ps
CPU time 22.31 seconds
Started Sep 03 11:24:54 PM UTC 24
Finished Sep 03 11:25:22 PM UTC 24
Peak memory 154560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=817816674 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 289.prim_prince_test.817816674
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/289.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/29.prim_prince_test.2147865787
Short name T14
Test name
Test status
Simulation time 1481081255 ps
CPU time 26.16 seconds
Started Sep 03 11:21:30 PM UTC 24
Finished Sep 03 11:22:04 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2147865787 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 29.prim_prince_test.2147865787
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/29.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/290.prim_prince_test.66636303
Short name T276
Test name
Test status
Simulation time 1822039713 ps
CPU time 32.67 seconds
Started Sep 03 11:24:54 PM UTC 24
Finished Sep 03 11:25:35 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=66636303 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 290.prim_prince_test.66636303
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/290.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/291.prim_prince_test.1482130789
Short name T287
Test name
Test status
Simulation time 2045722247 ps
CPU time 36.43 seconds
Started Sep 03 11:24:55 PM UTC 24
Finished Sep 03 11:25:40 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1482130789 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 291.prim_prince_test.1482130789
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/291.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/292.prim_prince_test.1838598764
Short name T315
Test name
Test status
Simulation time 3356605485 ps
CPU time 59.37 seconds
Started Sep 03 11:24:55 PM UTC 24
Finished Sep 03 11:26:08 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1838598764 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 292.prim_prince_test.1838598764
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/292.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/293.prim_prince_test.3827923134
Short name T307
Test name
Test status
Simulation time 2998984902 ps
CPU time 53.18 seconds
Started Sep 03 11:24:57 PM UTC 24
Finished Sep 03 11:26:02 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3827923134 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 293.prim_prince_test.3827923134
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/293.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/294.prim_prince_test.4187932011
Short name T279
Test name
Test status
Simulation time 1862888375 ps
CPU time 33.24 seconds
Started Sep 03 11:24:57 PM UTC 24
Finished Sep 03 11:25:38 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4187932011 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 294.prim_prince_test.4187932011
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/294.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/295.prim_prince_test.2431893596
Short name T259
Test name
Test status
Simulation time 844711438 ps
CPU time 15.06 seconds
Started Sep 03 11:24:59 PM UTC 24
Finished Sep 03 11:25:18 PM UTC 24
Peak memory 154348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2431893596 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 295.prim_prince_test.2431893596
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/295.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/296.prim_prince_test.2167695056
Short name T304
Test name
Test status
Simulation time 2748510552 ps
CPU time 48.51 seconds
Started Sep 03 11:25:01 PM UTC 24
Finished Sep 03 11:26:01 PM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2167695056 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 296.prim_prince_test.2167695056
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/296.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/297.prim_prince_test.1446103270
Short name T330
Test name
Test status
Simulation time 3595073747 ps
CPU time 62.89 seconds
Started Sep 03 11:25:01 PM UTC 24
Finished Sep 03 11:26:18 PM UTC 24
Peak memory 154620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1446103270 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 297.prim_prince_test.1446103270
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/297.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/298.prim_prince_test.746195258
Short name T268
Test name
Test status
Simulation time 1140234918 ps
CPU time 20.08 seconds
Started Sep 03 11:25:02 PM UTC 24
Finished Sep 03 11:25:27 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=746195258 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 298.prim_prince_test.746195258
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/298.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/299.prim_prince_test.3193153576
Short name T273
Test name
Test status
Simulation time 1305240642 ps
CPU time 23.33 seconds
Started Sep 03 11:25:03 PM UTC 24
Finished Sep 03 11:25:33 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3193153576 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 299.prim_prince_test.3193153576
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/299.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/3.prim_prince_test.4274897627
Short name T33
Test name
Test status
Simulation time 2689883376 ps
CPU time 46.59 seconds
Started Sep 03 11:21:22 PM UTC 24
Finished Sep 03 11:22:20 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4274897627 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 3.prim_prince_test.4274897627
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/3.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/30.prim_prince_test.2167509581
Short name T63
Test name
Test status
Simulation time 3192163463 ps
CPU time 56.32 seconds
Started Sep 03 11:21:30 PM UTC 24
Finished Sep 03 11:22:40 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2167509581 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 30.prim_prince_test.2167509581
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/30.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/300.prim_prince_test.2198190214
Short name T297
Test name
Test status
Simulation time 1805508288 ps
CPU time 32.13 seconds
Started Sep 03 11:25:08 PM UTC 24
Finished Sep 03 11:25:48 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2198190214 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 300.prim_prince_test.2198190214
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/300.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/301.prim_prince_test.2956070083
Short name T333
Test name
Test status
Simulation time 3246265388 ps
CPU time 57.28 seconds
Started Sep 03 11:25:10 PM UTC 24
Finished Sep 03 11:26:20 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2956070083 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 301.prim_prince_test.2956070083
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/301.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/302.prim_prince_test.894732403
Short name T308
Test name
Test status
Simulation time 2456069032 ps
CPU time 43.32 seconds
Started Sep 03 11:25:10 PM UTC 24
Finished Sep 03 11:26:03 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=894732403 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 302.prim_prince_test.894732403
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/302.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/303.prim_prince_test.908848437
Short name T300
Test name
Test status
Simulation time 1855099145 ps
CPU time 33.22 seconds
Started Sep 03 11:25:10 PM UTC 24
Finished Sep 03 11:25:51 PM UTC 24
Peak memory 154540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=908848437 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 303.prim_prince_test.908848437
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/303.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/304.prim_prince_test.99671673
Short name T312
Test name
Test status
Simulation time 2611854148 ps
CPU time 46.14 seconds
Started Sep 03 11:25:10 PM UTC 24
Finished Sep 03 11:26:06 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=99671673 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 304.prim_prince_test.99671673
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/304.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/305.prim_prince_test.1592736561
Short name T328
Test name
Test status
Simulation time 3080681641 ps
CPU time 53.6 seconds
Started Sep 03 11:25:11 PM UTC 24
Finished Sep 03 11:26:17 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1592736561 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 305.prim_prince_test.1592736561
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/305.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/306.prim_prince_test.720580138
Short name T335
Test name
Test status
Simulation time 3298652788 ps
CPU time 57.83 seconds
Started Sep 03 11:25:11 PM UTC 24
Finished Sep 03 11:26:22 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=720580138 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 306.prim_prince_test.720580138
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/306.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/307.prim_prince_test.1070416170
Short name T281
Test name
Test status
Simulation time 1155959108 ps
CPU time 20.77 seconds
Started Sep 03 11:25:12 PM UTC 24
Finished Sep 03 11:25:38 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1070416170 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 307.prim_prince_test.1070416170
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/307.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/308.prim_prince_test.3658347128
Short name T339
Test name
Test status
Simulation time 3364805584 ps
CPU time 58.9 seconds
Started Sep 03 11:25:12 PM UTC 24
Finished Sep 03 11:26:24 PM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3658347128 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 308.prim_prince_test.3658347128
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/308.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/309.prim_prince_test.2352709500
Short name T289
Test name
Test status
Simulation time 1236553534 ps
CPU time 22.12 seconds
Started Sep 03 11:25:13 PM UTC 24
Finished Sep 03 11:25:41 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2352709500 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 309.prim_prince_test.2352709500
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/309.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/31.prim_prince_test.3766289470
Short name T10
Test name
Test status
Simulation time 1206717683 ps
CPU time 21.82 seconds
Started Sep 03 11:21:30 PM UTC 24
Finished Sep 03 11:21:58 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3766289470 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 31.prim_prince_test.3766289470
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/31.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/310.prim_prince_test.1715115342
Short name T283
Test name
Test status
Simulation time 1094535794 ps
CPU time 19.65 seconds
Started Sep 03 11:25:15 PM UTC 24
Finished Sep 03 11:25:39 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1715115342 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 310.prim_prince_test.1715115342
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/310.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/311.prim_prince_test.1955454347
Short name T303
Test name
Test status
Simulation time 2075864973 ps
CPU time 36.74 seconds
Started Sep 03 11:25:15 PM UTC 24
Finished Sep 03 11:26:00 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1955454347 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 311.prim_prince_test.1955454347
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/311.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/312.prim_prince_test.246650241
Short name T298
Test name
Test status
Simulation time 1471309967 ps
CPU time 26.28 seconds
Started Sep 03 11:25:16 PM UTC 24
Finished Sep 03 11:25:48 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=246650241 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 312.prim_prince_test.246650241
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/312.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/313.prim_prince_test.4080049361
Short name T317
Test name
Test status
Simulation time 2514976496 ps
CPU time 44.35 seconds
Started Sep 03 11:25:16 PM UTC 24
Finished Sep 03 11:26:10 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4080049361 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 313.prim_prince_test.4080049361
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/313.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/314.prim_prince_test.3473533417
Short name T321
Test name
Test status
Simulation time 2478677273 ps
CPU time 44.39 seconds
Started Sep 03 11:25:17 PM UTC 24
Finished Sep 03 11:26:11 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3473533417 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 314.prim_prince_test.3473533417
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/314.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/315.prim_prince_test.2164108825
Short name T341
Test name
Test status
Simulation time 3230278969 ps
CPU time 56.55 seconds
Started Sep 03 11:25:17 PM UTC 24
Finished Sep 03 11:26:26 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2164108825 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 315.prim_prince_test.2164108825
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/315.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/316.prim_prince_test.4043031546
Short name T284
Test name
Test status
Simulation time 984775086 ps
CPU time 17.67 seconds
Started Sep 03 11:25:17 PM UTC 24
Finished Sep 03 11:25:39 PM UTC 24
Peak memory 154348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4043031546 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 316.prim_prince_test.4043031546
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/316.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/317.prim_prince_test.3747446923
Short name T309
Test name
Test status
Simulation time 2094218086 ps
CPU time 37.13 seconds
Started Sep 03 11:25:18 PM UTC 24
Finished Sep 03 11:26:04 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3747446923 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 317.prim_prince_test.3747446923
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/317.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/318.prim_prince_test.1670825678
Short name T337
Test name
Test status
Simulation time 3015609102 ps
CPU time 53.22 seconds
Started Sep 03 11:25:18 PM UTC 24
Finished Sep 03 11:26:24 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1670825678 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 318.prim_prince_test.1670825678
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/318.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/319.prim_prince_test.2206869023
Short name T291
Test name
Test status
Simulation time 1136447789 ps
CPU time 20.3 seconds
Started Sep 03 11:25:18 PM UTC 24
Finished Sep 03 11:25:44 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2206869023 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 319.prim_prince_test.2206869023
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/319.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/32.prim_prince_test.3964935327
Short name T71
Test name
Test status
Simulation time 3456328571 ps
CPU time 61.21 seconds
Started Sep 03 11:21:30 PM UTC 24
Finished Sep 03 11:22:46 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3964935327 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 32.prim_prince_test.3964935327
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/32.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/320.prim_prince_test.342146292
Short name T299
Test name
Test status
Simulation time 1307735769 ps
CPU time 23.22 seconds
Started Sep 03 11:25:20 PM UTC 24
Finished Sep 03 11:25:48 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=342146292 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 320.prim_prince_test.342146292
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/320.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/321.prim_prince_test.4101804406
Short name T357
Test name
Test status
Simulation time 3651468900 ps
CPU time 64.75 seconds
Started Sep 03 11:25:22 PM UTC 24
Finished Sep 03 11:26:41 PM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4101804406 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 321.prim_prince_test.4101804406
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/321.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/322.prim_prince_test.1582383014
Short name T290
Test name
Test status
Simulation time 843508398 ps
CPU time 14.96 seconds
Started Sep 03 11:25:23 PM UTC 24
Finished Sep 03 11:25:42 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1582383014 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 322.prim_prince_test.1582383014
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/322.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/323.prim_prince_test.2661398313
Short name T334
Test name
Test status
Simulation time 2620980601 ps
CPU time 46.62 seconds
Started Sep 03 11:25:23 PM UTC 24
Finished Sep 03 11:26:20 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2661398313 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 323.prim_prince_test.2661398313
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/323.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/324.prim_prince_test.2370498808
Short name T322
Test name
Test status
Simulation time 2232901636 ps
CPU time 39.83 seconds
Started Sep 03 11:25:23 PM UTC 24
Finished Sep 03 11:26:12 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2370498808 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 324.prim_prince_test.2370498808
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/324.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/325.prim_prince_test.1544284551
Short name T331
Test name
Test status
Simulation time 2545637297 ps
CPU time 44.94 seconds
Started Sep 03 11:25:23 PM UTC 24
Finished Sep 03 11:26:18 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1544284551 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 325.prim_prince_test.1544284551
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/325.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/326.prim_prince_test.1111711350
Short name T296
Test name
Test status
Simulation time 867099009 ps
CPU time 15.69 seconds
Started Sep 03 11:25:26 PM UTC 24
Finished Sep 03 11:25:46 PM UTC 24
Peak memory 154348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1111711350 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 326.prim_prince_test.1111711350
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/326.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/327.prim_prince_test.2453313558
Short name T323
Test name
Test status
Simulation time 2089204598 ps
CPU time 37.02 seconds
Started Sep 03 11:25:26 PM UTC 24
Finished Sep 03 11:26:12 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2453313558 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 327.prim_prince_test.2453313558
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/327.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/328.prim_prince_test.4264455385
Short name T329
Test name
Test status
Simulation time 2240299528 ps
CPU time 39.83 seconds
Started Sep 03 11:25:29 PM UTC 24
Finished Sep 03 11:26:18 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4264455385 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 328.prim_prince_test.4264455385
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/328.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/329.prim_prince_test.94049988
Short name T325
Test name
Test status
Simulation time 2346442325 ps
CPU time 41.05 seconds
Started Sep 03 11:25:30 PM UTC 24
Finished Sep 03 11:26:20 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=94049988 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 329.prim_prince_test.94049988
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/329.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/33.prim_prince_test.2175689899
Short name T30
Test name
Test status
Simulation time 2027541718 ps
CPU time 35.54 seconds
Started Sep 03 11:21:31 PM UTC 24
Finished Sep 03 11:22:15 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2175689899 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 33.prim_prince_test.2175689899
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/33.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/330.prim_prince_test.4163425005
Short name T344
Test name
Test status
Simulation time 2779484779 ps
CPU time 48.7 seconds
Started Sep 03 11:25:30 PM UTC 24
Finished Sep 03 11:26:30 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4163425005 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 330.prim_prince_test.4163425005
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/330.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/331.prim_prince_test.1666055034
Short name T353
Test name
Test status
Simulation time 3043904033 ps
CPU time 53.88 seconds
Started Sep 03 11:25:31 PM UTC 24
Finished Sep 03 11:26:37 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1666055034 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 331.prim_prince_test.1666055034
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/331.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/332.prim_prince_test.4317590
Short name T356
Test name
Test status
Simulation time 3199943050 ps
CPU time 56.51 seconds
Started Sep 03 11:25:31 PM UTC 24
Finished Sep 03 11:26:40 PM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4317590 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 332.prim_prince_test.4317590
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/332.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/333.prim_prince_test.1613408674
Short name T311
Test name
Test status
Simulation time 1431323319 ps
CPU time 25.58 seconds
Started Sep 03 11:25:33 PM UTC 24
Finished Sep 03 11:26:05 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1613408674 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 333.prim_prince_test.1613408674
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/333.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/334.prim_prince_test.2843173578
Short name T340
Test name
Test status
Simulation time 2255945578 ps
CPU time 40.36 seconds
Started Sep 03 11:25:35 PM UTC 24
Finished Sep 03 11:26:25 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2843173578 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 334.prim_prince_test.2843173578
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/334.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/335.prim_prince_test.1676306912
Short name T354
Test name
Test status
Simulation time 2883570585 ps
CPU time 50.33 seconds
Started Sep 03 11:25:35 PM UTC 24
Finished Sep 03 11:26:37 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1676306912 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 335.prim_prince_test.1676306912
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/335.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/336.prim_prince_test.2478625031
Short name T365
Test name
Test status
Simulation time 3298642104 ps
CPU time 58.33 seconds
Started Sep 03 11:25:35 PM UTC 24
Finished Sep 03 11:26:47 PM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2478625031 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 336.prim_prince_test.2478625031
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/336.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/337.prim_prince_test.4286015391
Short name T320
Test name
Test status
Simulation time 1557285734 ps
CPU time 27.52 seconds
Started Sep 03 11:25:37 PM UTC 24
Finished Sep 03 11:26:11 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4286015391 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 337.prim_prince_test.4286015391
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/337.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/338.prim_prince_test.4084880992
Short name T347
Test name
Test status
Simulation time 2368250693 ps
CPU time 41.69 seconds
Started Sep 03 11:25:39 PM UTC 24
Finished Sep 03 11:26:30 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4084880992 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 338.prim_prince_test.4084880992
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/338.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/339.prim_prince_test.2916590478
Short name T338
Test name
Test status
Simulation time 2045929728 ps
CPU time 36.23 seconds
Started Sep 03 11:25:39 PM UTC 24
Finished Sep 03 11:26:24 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2916590478 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 339.prim_prince_test.2916590478
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/339.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/34.prim_prince_test.1703989777
Short name T18
Test name
Test status
Simulation time 1530372893 ps
CPU time 27.41 seconds
Started Sep 03 11:21:31 PM UTC 24
Finished Sep 03 11:22:05 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1703989777 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 34.prim_prince_test.1703989777
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/34.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/340.prim_prince_test.4238986438
Short name T346
Test name
Test status
Simulation time 2320885276 ps
CPU time 41.55 seconds
Started Sep 03 11:25:39 PM UTC 24
Finished Sep 03 11:26:30 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4238986438 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 340.prim_prince_test.4238986438
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/340.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/341.prim_prince_test.1734256809
Short name T332
Test name
Test status
Simulation time 1831158541 ps
CPU time 32.92 seconds
Started Sep 03 11:25:39 PM UTC 24
Finished Sep 03 11:26:20 PM UTC 24
Peak memory 156112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1734256809 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 341.prim_prince_test.1734256809
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/341.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/342.prim_prince_test.384885153
Short name T367
Test name
Test status
Simulation time 3093984836 ps
CPU time 54.92 seconds
Started Sep 03 11:25:40 PM UTC 24
Finished Sep 03 11:26:48 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=384885153 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 342.prim_prince_test.384885153
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/342.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/343.prim_prince_test.3161226191
Short name T336
Test name
Test status
Simulation time 1881220660 ps
CPU time 33.48 seconds
Started Sep 03 11:25:41 PM UTC 24
Finished Sep 03 11:26:22 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3161226191 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 343.prim_prince_test.3161226191
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/343.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/344.prim_prince_test.586684521
Short name T374
Test name
Test status
Simulation time 3353982034 ps
CPU time 59.07 seconds
Started Sep 03 11:25:41 PM UTC 24
Finished Sep 03 11:26:53 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=586684521 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 344.prim_prince_test.586684521
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/344.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/345.prim_prince_test.2976035770
Short name T355
Test name
Test status
Simulation time 2734060530 ps
CPU time 48.14 seconds
Started Sep 03 11:25:41 PM UTC 24
Finished Sep 03 11:26:40 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2976035770 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 345.prim_prince_test.2976035770
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/345.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/346.prim_prince_test.944581367
Short name T361
Test name
Test status
Simulation time 2983538398 ps
CPU time 53.04 seconds
Started Sep 03 11:25:41 PM UTC 24
Finished Sep 03 11:26:46 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=944581367 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 346.prim_prince_test.944581367
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/346.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/347.prim_prince_test.2822898055
Short name T370
Test name
Test status
Simulation time 3216800640 ps
CPU time 56.87 seconds
Started Sep 03 11:25:41 PM UTC 24
Finished Sep 03 11:26:50 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2822898055 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 347.prim_prince_test.2822898055
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/347.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/348.prim_prince_test.2993398738
Short name T376
Test name
Test status
Simulation time 3401151906 ps
CPU time 59.37 seconds
Started Sep 03 11:25:42 PM UTC 24
Finished Sep 03 11:26:55 PM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2993398738 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 348.prim_prince_test.2993398738
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/348.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/349.prim_prince_test.3100336514
Short name T359
Test name
Test status
Simulation time 2830541262 ps
CPU time 50.01 seconds
Started Sep 03 11:25:42 PM UTC 24
Finished Sep 03 11:26:43 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3100336514 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 349.prim_prince_test.3100336514
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/349.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/35.prim_prince_test.603504907
Short name T6
Test name
Test status
Simulation time 858941411 ps
CPU time 15.38 seconds
Started Sep 03 11:21:31 PM UTC 24
Finished Sep 03 11:21:51 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=603504907 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 35.prim_prince_test.603504907
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/35.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/350.prim_prince_test.3949570398
Short name T381
Test name
Test status
Simulation time 3631441816 ps
CPU time 64.2 seconds
Started Sep 03 11:25:42 PM UTC 24
Finished Sep 03 11:27:00 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3949570398 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 350.prim_prince_test.3949570398
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/350.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/351.prim_prince_test.242545118
Short name T306
Test name
Test status
Simulation time 802801941 ps
CPU time 14.57 seconds
Started Sep 03 11:25:43 PM UTC 24
Finished Sep 03 11:26:02 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=242545118 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 351.prim_prince_test.242545118
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/351.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/352.prim_prince_test.1626795246
Short name T350
Test name
Test status
Simulation time 2241319015 ps
CPU time 39.92 seconds
Started Sep 03 11:25:44 PM UTC 24
Finished Sep 03 11:26:33 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1626795246 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 352.prim_prince_test.1626795246
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/352.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/353.prim_prince_test.575347463
Short name T327
Test name
Test status
Simulation time 1255013428 ps
CPU time 22.31 seconds
Started Sep 03 11:25:46 PM UTC 24
Finished Sep 03 11:26:13 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=575347463 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 353.prim_prince_test.575347463
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/353.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/354.prim_prince_test.1528435191
Short name T319
Test name
Test status
Simulation time 1116307078 ps
CPU time 19.97 seconds
Started Sep 03 11:25:46 PM UTC 24
Finished Sep 03 11:26:11 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1528435191 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 354.prim_prince_test.1528435191
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/354.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/355.prim_prince_test.4071378763
Short name T378
Test name
Test status
Simulation time 3287733653 ps
CPU time 58.11 seconds
Started Sep 03 11:25:46 PM UTC 24
Finished Sep 03 11:26:57 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4071378763 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 355.prim_prince_test.4071378763
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/355.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/356.prim_prince_test.4085056608
Short name T316
Test name
Test status
Simulation time 938792042 ps
CPU time 17.01 seconds
Started Sep 03 11:25:47 PM UTC 24
Finished Sep 03 11:26:08 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4085056608 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 356.prim_prince_test.4085056608
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/356.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/357.prim_prince_test.1271865329
Short name T324
Test name
Test status
Simulation time 1153299055 ps
CPU time 20.81 seconds
Started Sep 03 11:25:47 PM UTC 24
Finished Sep 03 11:26:13 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1271865329 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 357.prim_prince_test.1271865329
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/357.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/358.prim_prince_test.2557964715
Short name T352
Test name
Test status
Simulation time 2153632875 ps
CPU time 38.59 seconds
Started Sep 03 11:25:49 PM UTC 24
Finished Sep 03 11:26:37 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2557964715 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 358.prim_prince_test.2557964715
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/358.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/359.prim_prince_test.2932897036
Short name T343
Test name
Test status
Simulation time 1737442561 ps
CPU time 30.9 seconds
Started Sep 03 11:25:49 PM UTC 24
Finished Sep 03 11:26:27 PM UTC 24
Peak memory 154520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2932897036 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 359.prim_prince_test.2932897036
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/359.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/36.prim_prince_test.2979718255
Short name T75
Test name
Test status
Simulation time 3528185412 ps
CPU time 63.43 seconds
Started Sep 03 11:21:32 PM UTC 24
Finished Sep 03 11:22:49 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2979718255 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 36.prim_prince_test.2979718255
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/36.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/360.prim_prince_test.2423741217
Short name T375
Test name
Test status
Simulation time 2992594849 ps
CPU time 53.09 seconds
Started Sep 03 11:25:49 PM UTC 24
Finished Sep 03 11:26:54 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2423741217 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 360.prim_prince_test.2423741217
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/360.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/361.prim_prince_test.509464222
Short name T371
Test name
Test status
Simulation time 2772678260 ps
CPU time 49.13 seconds
Started Sep 03 11:25:51 PM UTC 24
Finished Sep 03 11:26:52 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=509464222 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 361.prim_prince_test.509464222
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/361.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/362.prim_prince_test.1275195811
Short name T383
Test name
Test status
Simulation time 3319808515 ps
CPU time 58.4 seconds
Started Sep 03 11:25:55 PM UTC 24
Finished Sep 03 11:27:07 PM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1275195811 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 362.prim_prince_test.1275195811
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/362.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/363.prim_prince_test.3730207932
Short name T348
Test name
Test status
Simulation time 1438149768 ps
CPU time 25.68 seconds
Started Sep 03 11:26:00 PM UTC 24
Finished Sep 03 11:26:32 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3730207932 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 363.prim_prince_test.3730207932
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/363.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/364.prim_prince_test.4071331997
Short name T345
Test name
Test status
Simulation time 1298464512 ps
CPU time 23.43 seconds
Started Sep 03 11:26:01 PM UTC 24
Finished Sep 03 11:26:30 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4071331997 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 364.prim_prince_test.4071331997
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/364.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/365.prim_prince_test.664703589
Short name T364
Test name
Test status
Simulation time 2036501645 ps
CPU time 35.99 seconds
Started Sep 03 11:26:02 PM UTC 24
Finished Sep 03 11:26:46 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=664703589 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 365.prim_prince_test.664703589
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/365.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/366.prim_prince_test.2381083820
Short name T391
Test name
Test status
Simulation time 3459723599 ps
CPU time 60.73 seconds
Started Sep 03 11:26:02 PM UTC 24
Finished Sep 03 11:27:16 PM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2381083820 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 366.prim_prince_test.2381083820
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/366.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/367.prim_prince_test.867496634
Short name T392
Test name
Test status
Simulation time 3523250974 ps
CPU time 61.6 seconds
Started Sep 03 11:26:02 PM UTC 24
Finished Sep 03 11:27:17 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=867496634 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 367.prim_prince_test.867496634
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/367.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/368.prim_prince_test.1522949750
Short name T377
Test name
Test status
Simulation time 2459894929 ps
CPU time 43.19 seconds
Started Sep 03 11:26:03 PM UTC 24
Finished Sep 03 11:26:56 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1522949750 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 368.prim_prince_test.1522949750
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/368.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/369.prim_prince_test.3476893929
Short name T351
Test name
Test status
Simulation time 1388814383 ps
CPU time 24.84 seconds
Started Sep 03 11:26:03 PM UTC 24
Finished Sep 03 11:26:34 PM UTC 24
Peak memory 154348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3476893929 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 369.prim_prince_test.3476893929
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/369.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/37.prim_prince_test.2046231056
Short name T44
Test name
Test status
Simulation time 2574899409 ps
CPU time 45.74 seconds
Started Sep 03 11:21:32 PM UTC 24
Finished Sep 03 11:22:29 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2046231056 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 37.prim_prince_test.2046231056
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/37.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/370.prim_prince_test.1725754932
Short name T372
Test name
Test status
Simulation time 2146237732 ps
CPU time 38.34 seconds
Started Sep 03 11:26:05 PM UTC 24
Finished Sep 03 11:26:52 PM UTC 24
Peak memory 154556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1725754932 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 370.prim_prince_test.1725754932
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/370.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/371.prim_prince_test.1696458101
Short name T326
Test name
Test status
Simulation time 761029998 ps
CPU time 13.85 seconds
Started Sep 03 11:26:05 PM UTC 24
Finished Sep 03 11:26:22 PM UTC 24
Peak memory 154312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1696458101 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 371.prim_prince_test.1696458101
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/371.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/372.prim_prince_test.2901899951
Short name T363
Test name
Test status
Simulation time 1841430568 ps
CPU time 32.79 seconds
Started Sep 03 11:26:06 PM UTC 24
Finished Sep 03 11:26:46 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2901899951 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 372.prim_prince_test.2901899951
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/372.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/373.prim_prince_test.1644075894
Short name T349
Test name
Test status
Simulation time 1148789788 ps
CPU time 20.7 seconds
Started Sep 03 11:26:07 PM UTC 24
Finished Sep 03 11:26:33 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1644075894 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 373.prim_prince_test.1644075894
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/373.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/374.prim_prince_test.1475452940
Short name T379
Test name
Test status
Simulation time 2385615119 ps
CPU time 41.87 seconds
Started Sep 03 11:26:07 PM UTC 24
Finished Sep 03 11:26:59 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1475452940 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 374.prim_prince_test.1475452940
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/374.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/375.prim_prince_test.159288720
Short name T342
Test name
Test status
Simulation time 776933299 ps
CPU time 13.92 seconds
Started Sep 03 11:26:09 PM UTC 24
Finished Sep 03 11:26:27 PM UTC 24
Peak memory 154104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=159288720 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 375.prim_prince_test.159288720
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/375.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/376.prim_prince_test.1308214329
Short name T387
Test name
Test status
Simulation time 2753072548 ps
CPU time 48.97 seconds
Started Sep 03 11:26:09 PM UTC 24
Finished Sep 03 11:27:09 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1308214329 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 376.prim_prince_test.1308214329
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/376.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/377.prim_prince_test.3687688415
Short name T362
Test name
Test status
Simulation time 1656673905 ps
CPU time 29.63 seconds
Started Sep 03 11:26:10 PM UTC 24
Finished Sep 03 11:26:46 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3687688415 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 377.prim_prince_test.3687688415
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/377.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/378.prim_prince_test.4120091562
Short name T373
Test name
Test status
Simulation time 1909733969 ps
CPU time 33.55 seconds
Started Sep 03 11:26:11 PM UTC 24
Finished Sep 03 11:26:52 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4120091562 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 378.prim_prince_test.4120091562
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/378.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/379.prim_prince_test.3618476537
Short name T401
Test name
Test status
Simulation time 3376011916 ps
CPU time 58.98 seconds
Started Sep 03 11:26:12 PM UTC 24
Finished Sep 03 11:27:24 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3618476537 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 379.prim_prince_test.3618476537
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/379.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/38.prim_prince_test.252526161
Short name T11
Test name
Test status
Simulation time 1274534383 ps
CPU time 22.65 seconds
Started Sep 03 11:21:32 PM UTC 24
Finished Sep 03 11:22:01 PM UTC 24
Peak memory 154588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=252526161 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 38.prim_prince_test.252526161
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/38.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/380.prim_prince_test.2772622756
Short name T360
Test name
Test status
Simulation time 1429289800 ps
CPU time 25.64 seconds
Started Sep 03 11:26:12 PM UTC 24
Finished Sep 03 11:26:44 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2772622756 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 380.prim_prince_test.2772622756
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/380.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/381.prim_prince_test.3247328770
Short name T410
Test name
Test status
Simulation time 3527579439 ps
CPU time 62.28 seconds
Started Sep 03 11:26:12 PM UTC 24
Finished Sep 03 11:27:28 PM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3247328770 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 381.prim_prince_test.3247328770
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/381.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/382.prim_prince_test.899371648
Short name T405
Test name
Test status
Simulation time 3369623526 ps
CPU time 59.56 seconds
Started Sep 03 11:26:12 PM UTC 24
Finished Sep 03 11:27:25 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=899371648 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 382.prim_prince_test.899371648
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/382.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/383.prim_prince_test.2108277705
Short name T369
Test name
Test status
Simulation time 1652589746 ps
CPU time 29.61 seconds
Started Sep 03 11:26:13 PM UTC 24
Finished Sep 03 11:26:50 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2108277705 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 383.prim_prince_test.2108277705
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/383.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/384.prim_prince_test.443797653
Short name T396
Test name
Test status
Simulation time 3168067586 ps
CPU time 55.41 seconds
Started Sep 03 11:26:13 PM UTC 24
Finished Sep 03 11:27:21 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=443797653 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 384.prim_prince_test.443797653
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/384.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/385.prim_prince_test.1013600377
Short name T380
Test name
Test status
Simulation time 2164163752 ps
CPU time 38.11 seconds
Started Sep 03 11:26:13 PM UTC 24
Finished Sep 03 11:27:00 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1013600377 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 385.prim_prince_test.1013600377
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/385.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/386.prim_prince_test.2099109964
Short name T414
Test name
Test status
Simulation time 3507850930 ps
CPU time 62.03 seconds
Started Sep 03 11:26:15 PM UTC 24
Finished Sep 03 11:27:30 PM UTC 24
Peak memory 154648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2099109964 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 386.prim_prince_test.2099109964
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/386.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/387.prim_prince_test.3297085102
Short name T368
Test name
Test status
Simulation time 1377928280 ps
CPU time 24.51 seconds
Started Sep 03 11:26:18 PM UTC 24
Finished Sep 03 11:26:48 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3297085102 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 387.prim_prince_test.3297085102
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/387.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/388.prim_prince_test.2406661836
Short name T394
Test name
Test status
Simulation time 2795450262 ps
CPU time 48.55 seconds
Started Sep 03 11:26:19 PM UTC 24
Finished Sep 03 11:27:19 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2406661836 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 388.prim_prince_test.2406661836
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/388.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/389.prim_prince_test.2101696328
Short name T425
Test name
Test status
Simulation time 3719513903 ps
CPU time 64.82 seconds
Started Sep 03 11:26:19 PM UTC 24
Finished Sep 03 11:27:38 PM UTC 24
Peak memory 154460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2101696328 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 389.prim_prince_test.2101696328
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/389.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/39.prim_prince_test.127750999
Short name T26
Test name
Test status
Simulation time 1792816549 ps
CPU time 32.49 seconds
Started Sep 03 11:21:32 PM UTC 24
Finished Sep 03 11:22:12 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=127750999 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 39.prim_prince_test.127750999
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/39.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/390.prim_prince_test.4142410723
Short name T366
Test name
Test status
Simulation time 1236595526 ps
CPU time 22.41 seconds
Started Sep 03 11:26:19 PM UTC 24
Finished Sep 03 11:26:47 PM UTC 24
Peak memory 154464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4142410723 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 390.prim_prince_test.4142410723
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/390.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/391.prim_prince_test.1194377037
Short name T358
Test name
Test status
Simulation time 1014599536 ps
CPU time 18.13 seconds
Started Sep 03 11:26:20 PM UTC 24
Finished Sep 03 11:26:43 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1194377037 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 391.prim_prince_test.1194377037
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/391.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/392.prim_prince_test.770412008
Short name T421
Test name
Test status
Simulation time 3472216698 ps
CPU time 61.01 seconds
Started Sep 03 11:26:20 PM UTC 24
Finished Sep 03 11:27:35 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=770412008 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 392.prim_prince_test.770412008
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/392.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/393.prim_prince_test.2930958348
Short name T419
Test name
Test status
Simulation time 3290490274 ps
CPU time 59.04 seconds
Started Sep 03 11:26:22 PM UTC 24
Finished Sep 03 11:27:34 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2930958348 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 393.prim_prince_test.2930958348
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/393.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/394.prim_prince_test.1477767948
Short name T408
Test name
Test status
Simulation time 2963201226 ps
CPU time 52.95 seconds
Started Sep 03 11:26:22 PM UTC 24
Finished Sep 03 11:27:26 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1477767948 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 394.prim_prince_test.1477767948
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/394.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/395.prim_prince_test.2549349334
Short name T389
Test name
Test status
Simulation time 2261173461 ps
CPU time 39.77 seconds
Started Sep 03 11:26:23 PM UTC 24
Finished Sep 03 11:27:12 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2549349334 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 395.prim_prince_test.2549349334
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/395.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/396.prim_prince_test.214367909
Short name T426
Test name
Test status
Simulation time 3536357995 ps
CPU time 61.76 seconds
Started Sep 03 11:26:23 PM UTC 24
Finished Sep 03 11:27:39 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=214367909 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 396.prim_prince_test.214367909
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/396.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/397.prim_prince_test.3973969986
Short name T385
Test name
Test status
Simulation time 2067651215 ps
CPU time 36.6 seconds
Started Sep 03 11:26:23 PM UTC 24
Finished Sep 03 11:27:08 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3973969986 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 397.prim_prince_test.3973969986
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/397.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/398.prim_prince_test.636759449
Short name T384
Test name
Test status
Simulation time 1993317954 ps
CPU time 35.35 seconds
Started Sep 03 11:26:24 PM UTC 24
Finished Sep 03 11:27:08 PM UTC 24
Peak memory 154216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=636759449 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 398.prim_prince_test.636759449
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/398.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/399.prim_prince_test.1585506080
Short name T402
Test name
Test status
Simulation time 2742652996 ps
CPU time 48.84 seconds
Started Sep 03 11:26:24 PM UTC 24
Finished Sep 03 11:27:24 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1585506080 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 399.prim_prince_test.1585506080
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/399.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/4.prim_prince_test.2281927738
Short name T12
Test name
Test status
Simulation time 1813916082 ps
CPU time 31.04 seconds
Started Sep 03 11:21:22 PM UTC 24
Finished Sep 03 11:22:01 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2281927738 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 4.prim_prince_test.2281927738
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/4.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/40.prim_prince_test.3310294607
Short name T77
Test name
Test status
Simulation time 3616439380 ps
CPU time 64.18 seconds
Started Sep 03 11:21:32 PM UTC 24
Finished Sep 03 11:22:51 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3310294607 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 40.prim_prince_test.3310294607
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/40.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/400.prim_prince_test.37694561
Short name T398
Test name
Test status
Simulation time 2667458217 ps
CPU time 46.8 seconds
Started Sep 03 11:26:25 PM UTC 24
Finished Sep 03 11:27:23 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37694561 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 400.prim_prince_test.37694561
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/400.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/401.prim_prince_test.644116189
Short name T424
Test name
Test status
Simulation time 3223831675 ps
CPU time 56.72 seconds
Started Sep 03 11:26:27 PM UTC 24
Finished Sep 03 11:27:36 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=644116189 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 401.prim_prince_test.644116189
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/401.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/402.prim_prince_test.3476153700
Short name T431
Test name
Test status
Simulation time 3683631198 ps
CPU time 65.27 seconds
Started Sep 03 11:26:27 PM UTC 24
Finished Sep 03 11:27:46 PM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3476153700 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 402.prim_prince_test.3476153700
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/402.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/403.prim_prince_test.4219545010
Short name T382
Test name
Test status
Simulation time 1504672591 ps
CPU time 26.18 seconds
Started Sep 03 11:26:28 PM UTC 24
Finished Sep 03 11:27:01 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4219545010 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 403.prim_prince_test.4219545010
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/403.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/404.prim_prince_test.323508963
Short name T422
Test name
Test status
Simulation time 3088983656 ps
CPU time 54.79 seconds
Started Sep 03 11:26:28 PM UTC 24
Finished Sep 03 11:27:35 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=323508963 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 404.prim_prince_test.323508963
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/404.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/405.prim_prince_test.1945898457
Short name T429
Test name
Test status
Simulation time 3319786668 ps
CPU time 58.52 seconds
Started Sep 03 11:26:30 PM UTC 24
Finished Sep 03 11:27:42 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1945898457 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 405.prim_prince_test.1945898457
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/405.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/406.prim_prince_test.1187821598
Short name T418
Test name
Test status
Simulation time 2881668180 ps
CPU time 50.51 seconds
Started Sep 03 11:26:32 PM UTC 24
Finished Sep 03 11:27:33 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1187821598 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 406.prim_prince_test.1187821598
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/406.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/407.prim_prince_test.1105569822
Short name T428
Test name
Test status
Simulation time 3164444919 ps
CPU time 55.67 seconds
Started Sep 03 11:26:32 PM UTC 24
Finished Sep 03 11:27:40 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1105569822 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 407.prim_prince_test.1105569822
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/407.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/408.prim_prince_test.3219628079
Short name T411
Test name
Test status
Simulation time 2612578766 ps
CPU time 46.14 seconds
Started Sep 03 11:26:32 PM UTC 24
Finished Sep 03 11:27:28 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3219628079 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 408.prim_prince_test.3219628079
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/408.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/409.prim_prince_test.778530600
Short name T404
Test name
Test status
Simulation time 2396674618 ps
CPU time 41.83 seconds
Started Sep 03 11:26:33 PM UTC 24
Finished Sep 03 11:27:25 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=778530600 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 409.prim_prince_test.778530600
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/409.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/41.prim_prince_test.58845202
Short name T67
Test name
Test status
Simulation time 3227557235 ps
CPU time 57.47 seconds
Started Sep 03 11:21:32 PM UTC 24
Finished Sep 03 11:22:43 PM UTC 24
Peak memory 154612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=58845202 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 41.prim_prince_test.58845202
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/41.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/410.prim_prince_test.4220446892
Short name T393
Test name
Test status
Simulation time 1980229574 ps
CPU time 35.73 seconds
Started Sep 03 11:26:34 PM UTC 24
Finished Sep 03 11:27:18 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4220446892 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 410.prim_prince_test.4220446892
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/410.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/411.prim_prince_test.497426137
Short name T409
Test name
Test status
Simulation time 2499207505 ps
CPU time 43.73 seconds
Started Sep 03 11:26:34 PM UTC 24
Finished Sep 03 11:27:28 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=497426137 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 411.prim_prince_test.497426137
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/411.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/412.prim_prince_test.428226531
Short name T395
Test name
Test status
Simulation time 1960944385 ps
CPU time 34.97 seconds
Started Sep 03 11:26:35 PM UTC 24
Finished Sep 03 11:27:19 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=428226531 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 412.prim_prince_test.428226531
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/412.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/413.prim_prince_test.2538905744
Short name T420
Test name
Test status
Simulation time 2626144779 ps
CPU time 45.74 seconds
Started Sep 03 11:26:37 PM UTC 24
Finished Sep 03 11:27:34 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2538905744 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 413.prim_prince_test.2538905744
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/413.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/414.prim_prince_test.1530703771
Short name T406
Test name
Test status
Simulation time 2139120549 ps
CPU time 37.44 seconds
Started Sep 03 11:26:39 PM UTC 24
Finished Sep 03 11:27:25 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1530703771 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 414.prim_prince_test.1530703771
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/414.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/415.prim_prince_test.1731025845
Short name T390
Test name
Test status
Simulation time 1592328574 ps
CPU time 28.31 seconds
Started Sep 03 11:26:39 PM UTC 24
Finished Sep 03 11:27:14 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1731025845 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 415.prim_prince_test.1731025845
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/415.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/416.prim_prince_test.63672943
Short name T446
Test name
Test status
Simulation time 3531268805 ps
CPU time 63.07 seconds
Started Sep 03 11:26:41 PM UTC 24
Finished Sep 03 11:27:58 PM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=63672943 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 416.prim_prince_test.63672943
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/416.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/417.prim_prince_test.3432938655
Short name T397
Test name
Test status
Simulation time 1868851726 ps
CPU time 33.06 seconds
Started Sep 03 11:26:41 PM UTC 24
Finished Sep 03 11:27:22 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3432938655 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 417.prim_prince_test.3432938655
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/417.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/418.prim_prince_test.3600412909
Short name T386
Test name
Test status
Simulation time 1202060198 ps
CPU time 21.33 seconds
Started Sep 03 11:26:42 PM UTC 24
Finished Sep 03 11:27:09 PM UTC 24
Peak memory 154348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3600412909 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 418.prim_prince_test.3600412909
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/418.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/419.prim_prince_test.739093171
Short name T438
Test name
Test status
Simulation time 3034729739 ps
CPU time 53.79 seconds
Started Sep 03 11:26:44 PM UTC 24
Finished Sep 03 11:27:50 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=739093171 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 419.prim_prince_test.739093171
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/419.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/42.prim_prince_test.1708616270
Short name T48
Test name
Test status
Simulation time 2706511991 ps
CPU time 48.32 seconds
Started Sep 03 11:21:32 PM UTC 24
Finished Sep 03 11:22:32 PM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1708616270 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 42.prim_prince_test.1708616270
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/42.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/420.prim_prince_test.2851532315
Short name T412
Test name
Test status
Simulation time 2024349023 ps
CPU time 35.71 seconds
Started Sep 03 11:26:44 PM UTC 24
Finished Sep 03 11:27:28 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2851532315 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 420.prim_prince_test.2851532315
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/420.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/421.prim_prince_test.3464643670
Short name T436
Test name
Test status
Simulation time 2949030613 ps
CPU time 52.67 seconds
Started Sep 03 11:26:44 PM UTC 24
Finished Sep 03 11:27:49 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3464643670 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 421.prim_prince_test.3464643670
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/421.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/422.prim_prince_test.1975914344
Short name T453
Test name
Test status
Simulation time 3580943686 ps
CPU time 63.65 seconds
Started Sep 03 11:26:47 PM UTC 24
Finished Sep 03 11:28:05 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1975914344 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 422.prim_prince_test.1975914344
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/422.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/423.prim_prince_test.3416483613
Short name T455
Test name
Test status
Simulation time 3710447256 ps
CPU time 66.03 seconds
Started Sep 03 11:26:47 PM UTC 24
Finished Sep 03 11:28:08 PM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3416483613 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 423.prim_prince_test.3416483613
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/423.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/424.prim_prince_test.3817070042
Short name T432
Test name
Test status
Simulation time 2742435366 ps
CPU time 48.36 seconds
Started Sep 03 11:26:47 PM UTC 24
Finished Sep 03 11:27:46 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3817070042 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 424.prim_prince_test.3817070042
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/424.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/425.prim_prince_test.1469926604
Short name T388
Test name
Test status
Simulation time 976335899 ps
CPU time 17.56 seconds
Started Sep 03 11:26:48 PM UTC 24
Finished Sep 03 11:27:11 PM UTC 24
Peak memory 154264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1469926604 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 425.prim_prince_test.1469926604
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/425.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/426.prim_prince_test.1287770299
Short name T443
Test name
Test status
Simulation time 3118526225 ps
CPU time 55.46 seconds
Started Sep 03 11:26:48 PM UTC 24
Finished Sep 03 11:27:56 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1287770299 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 426.prim_prince_test.1287770299
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/426.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/427.prim_prince_test.175534497
Short name T423
Test name
Test status
Simulation time 2211458306 ps
CPU time 38.77 seconds
Started Sep 03 11:26:48 PM UTC 24
Finished Sep 03 11:27:36 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=175534497 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 427.prim_prince_test.175534497
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/427.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/428.prim_prince_test.198597408
Short name T427
Test name
Test status
Simulation time 2297927033 ps
CPU time 40.98 seconds
Started Sep 03 11:26:48 PM UTC 24
Finished Sep 03 11:27:39 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=198597408 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 428.prim_prince_test.198597408
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/428.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/429.prim_prince_test.3375794708
Short name T417
Test name
Test status
Simulation time 1961980818 ps
CPU time 34.41 seconds
Started Sep 03 11:26:49 PM UTC 24
Finished Sep 03 11:27:32 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3375794708 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 429.prim_prince_test.3375794708
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/429.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/43.prim_prince_test.1030277315
Short name T74
Test name
Test status
Simulation time 3472861493 ps
CPU time 60.67 seconds
Started Sep 03 11:21:32 PM UTC 24
Finished Sep 03 11:22:47 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1030277315 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 43.prim_prince_test.1030277315
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/43.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/430.prim_prince_test.502844269
Short name T403
Test name
Test status
Simulation time 1507347533 ps
CPU time 26.83 seconds
Started Sep 03 11:26:51 PM UTC 24
Finished Sep 03 11:27:24 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=502844269 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 430.prim_prince_test.502844269
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/430.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/431.prim_prince_test.2039446755
Short name T457
Test name
Test status
Simulation time 3567022159 ps
CPU time 63.66 seconds
Started Sep 03 11:26:52 PM UTC 24
Finished Sep 03 11:28:10 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2039446755 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 431.prim_prince_test.2039446755
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/431.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/432.prim_prince_test.169487532
Short name T407
Test name
Test status
Simulation time 1481088824 ps
CPU time 25.78 seconds
Started Sep 03 11:26:53 PM UTC 24
Finished Sep 03 11:27:25 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=169487532 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 432.prim_prince_test.169487532
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/432.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/433.prim_prince_test.4232589844
Short name T460
Test name
Test status
Simulation time 3572619030 ps
CPU time 64.1 seconds
Started Sep 03 11:26:53 PM UTC 24
Finished Sep 03 11:28:12 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4232589844 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 433.prim_prince_test.4232589844
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/433.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/434.prim_prince_test.674249585
Short name T454
Test name
Test status
Simulation time 3370193297 ps
CPU time 59.8 seconds
Started Sep 03 11:26:53 PM UTC 24
Finished Sep 03 11:28:07 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=674249585 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 434.prim_prince_test.674249585
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/434.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/435.prim_prince_test.3914483568
Short name T400
Test name
Test status
Simulation time 1327918433 ps
CPU time 23.41 seconds
Started Sep 03 11:26:54 PM UTC 24
Finished Sep 03 11:27:23 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3914483568 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 435.prim_prince_test.3914483568
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/435.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/436.prim_prince_test.1931364377
Short name T451
Test name
Test status
Simulation time 3210586146 ps
CPU time 55.8 seconds
Started Sep 03 11:26:54 PM UTC 24
Finished Sep 03 11:28:03 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1931364377 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 436.prim_prince_test.1931364377
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/436.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/437.prim_prince_test.1994835409
Short name T433
Test name
Test status
Simulation time 2371381425 ps
CPU time 41.87 seconds
Started Sep 03 11:26:56 PM UTC 24
Finished Sep 03 11:27:47 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1994835409 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 437.prim_prince_test.1994835409
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/437.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/438.prim_prince_test.2191907723
Short name T416
Test name
Test status
Simulation time 1641492626 ps
CPU time 28.99 seconds
Started Sep 03 11:26:56 PM UTC 24
Finished Sep 03 11:27:32 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2191907723 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 438.prim_prince_test.2191907723
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/438.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/439.prim_prince_test.2765036184
Short name T413
Test name
Test status
Simulation time 1459008384 ps
CPU time 26.01 seconds
Started Sep 03 11:26:57 PM UTC 24
Finished Sep 03 11:27:29 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2765036184 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 439.prim_prince_test.2765036184
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/439.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/44.prim_prince_test.1033822962
Short name T36
Test name
Test status
Simulation time 2333946986 ps
CPU time 41.45 seconds
Started Sep 03 11:21:32 PM UTC 24
Finished Sep 03 11:22:24 PM UTC 24
Peak memory 154616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1033822962 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 44.prim_prince_test.1033822962
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/44.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/440.prim_prince_test.3670348007
Short name T468
Test name
Test status
Simulation time 3703181906 ps
CPU time 65.11 seconds
Started Sep 03 11:26:58 PM UTC 24
Finished Sep 03 11:28:18 PM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3670348007 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 440.prim_prince_test.3670348007
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/440.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/441.prim_prince_test.779455556
Short name T441
Test name
Test status
Simulation time 2590848947 ps
CPU time 45.23 seconds
Started Sep 03 11:26:59 PM UTC 24
Finished Sep 03 11:27:55 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=779455556 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 441.prim_prince_test.779455556
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/441.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/442.prim_prince_test.2534635479
Short name T445
Test name
Test status
Simulation time 2509099933 ps
CPU time 45.01 seconds
Started Sep 03 11:27:02 PM UTC 24
Finished Sep 03 11:27:57 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2534635479 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 442.prim_prince_test.2534635479
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/442.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/443.prim_prince_test.3466759712
Short name T399
Test name
Test status
Simulation time 963701775 ps
CPU time 17.11 seconds
Started Sep 03 11:27:02 PM UTC 24
Finished Sep 03 11:27:23 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3466759712 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 443.prim_prince_test.3466759712
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/443.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/444.prim_prince_test.629871987
Short name T447
Test name
Test status
Simulation time 2590019557 ps
CPU time 46.31 seconds
Started Sep 03 11:27:02 PM UTC 24
Finished Sep 03 11:27:59 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=629871987 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 444.prim_prince_test.629871987
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/444.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/445.prim_prince_test.3726249792
Short name T442
Test name
Test status
Simulation time 2173764380 ps
CPU time 38.8 seconds
Started Sep 03 11:27:08 PM UTC 24
Finished Sep 03 11:27:56 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3726249792 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 445.prim_prince_test.3726249792
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/445.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/446.prim_prince_test.3222054928
Short name T430
Test name
Test status
Simulation time 1648767687 ps
CPU time 29.49 seconds
Started Sep 03 11:27:09 PM UTC 24
Finished Sep 03 11:27:46 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3222054928 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 446.prim_prince_test.3222054928
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/446.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/447.prim_prince_test.3772054216
Short name T464
Test name
Test status
Simulation time 3031036776 ps
CPU time 53 seconds
Started Sep 03 11:27:09 PM UTC 24
Finished Sep 03 11:28:14 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3772054216 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 447.prim_prince_test.3772054216
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/447.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/448.prim_prince_test.410379592
Short name T440
Test name
Test status
Simulation time 1912687315 ps
CPU time 34.48 seconds
Started Sep 03 11:27:09 PM UTC 24
Finished Sep 03 11:27:52 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=410379592 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 448.prim_prince_test.410379592
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/448.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/449.prim_prince_test.1304645797
Short name T434
Test name
Test status
Simulation time 1684912068 ps
CPU time 30.07 seconds
Started Sep 03 11:27:10 PM UTC 24
Finished Sep 03 11:27:48 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1304645797 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 449.prim_prince_test.1304645797
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/449.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/45.prim_prince_test.1999978464
Short name T69
Test name
Test status
Simulation time 3362910673 ps
CPU time 59.3 seconds
Started Sep 03 11:21:32 PM UTC 24
Finished Sep 03 11:22:45 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1999978464 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 45.prim_prince_test.1999978464
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/45.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/450.prim_prince_test.408302970
Short name T473
Test name
Test status
Simulation time 3209741344 ps
CPU time 56.7 seconds
Started Sep 03 11:27:12 PM UTC 24
Finished Sep 03 11:28:21 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=408302970 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 450.prim_prince_test.408302970
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/450.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/451.prim_prince_test.4015735011
Short name T415
Test name
Test status
Simulation time 808455974 ps
CPU time 14.44 seconds
Started Sep 03 11:27:13 PM UTC 24
Finished Sep 03 11:27:31 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4015735011 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 451.prim_prince_test.4015735011
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/451.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/452.prim_prince_test.1823492975
Short name T450
Test name
Test status
Simulation time 2190855954 ps
CPU time 38.26 seconds
Started Sep 03 11:27:15 PM UTC 24
Finished Sep 03 11:28:02 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1823492975 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 452.prim_prince_test.1823492975
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/452.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/453.prim_prince_test.3838262557
Short name T459
Test name
Test status
Simulation time 2445318685 ps
CPU time 44.28 seconds
Started Sep 03 11:27:17 PM UTC 24
Finished Sep 03 11:28:11 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3838262557 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 453.prim_prince_test.3838262557
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/453.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/454.prim_prince_test.2217209709
Short name T466
Test name
Test status
Simulation time 2720860290 ps
CPU time 47.47 seconds
Started Sep 03 11:27:18 PM UTC 24
Finished Sep 03 11:28:17 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2217209709 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 454.prim_prince_test.2217209709
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/454.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/455.prim_prince_test.2726534366
Short name T485
Test name
Test status
Simulation time 3678239119 ps
CPU time 66.28 seconds
Started Sep 03 11:27:20 PM UTC 24
Finished Sep 03 11:28:41 PM UTC 24
Peak memory 156520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2726534366 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 455.prim_prince_test.2726534366
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/455.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/456.prim_prince_test.3119361697
Short name T448
Test name
Test status
Simulation time 1813670930 ps
CPU time 31.83 seconds
Started Sep 03 11:27:20 PM UTC 24
Finished Sep 03 11:27:59 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3119361697 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 456.prim_prince_test.3119361697
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/456.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/457.prim_prince_test.2825220854
Short name T472
Test name
Test status
Simulation time 2833609512 ps
CPU time 49.6 seconds
Started Sep 03 11:27:20 PM UTC 24
Finished Sep 03 11:28:21 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2825220854 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 457.prim_prince_test.2825220854
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/457.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/458.prim_prince_test.1890785285
Short name T437
Test name
Test status
Simulation time 1290435760 ps
CPU time 22.69 seconds
Started Sep 03 11:27:22 PM UTC 24
Finished Sep 03 11:27:50 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1890785285 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 458.prim_prince_test.1890785285
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/458.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/459.prim_prince_test.3830898664
Short name T486
Test name
Test status
Simulation time 3563291707 ps
CPU time 64.43 seconds
Started Sep 03 11:27:23 PM UTC 24
Finished Sep 03 11:28:42 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3830898664 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 459.prim_prince_test.3830898664
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/459.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/46.prim_prince_test.2649324144
Short name T16
Test name
Test status
Simulation time 1471061419 ps
CPU time 25.84 seconds
Started Sep 03 11:21:32 PM UTC 24
Finished Sep 03 11:22:05 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2649324144 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 46.prim_prince_test.2649324144
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/46.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/460.prim_prince_test.830787723
Short name T463
Test name
Test status
Simulation time 2210513807 ps
CPU time 39.91 seconds
Started Sep 03 11:27:24 PM UTC 24
Finished Sep 03 11:28:14 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=830787723 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 460.prim_prince_test.830787723
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/460.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/461.prim_prince_test.996556094
Short name T479
Test name
Test status
Simulation time 2826097804 ps
CPU time 50.01 seconds
Started Sep 03 11:27:25 PM UTC 24
Finished Sep 03 11:28:26 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=996556094 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 461.prim_prince_test.996556094
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/461.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/462.prim_prince_test.2779555782
Short name T458
Test name
Test status
Simulation time 2149957990 ps
CPU time 37.19 seconds
Started Sep 03 11:27:25 PM UTC 24
Finished Sep 03 11:28:11 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2779555782 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 462.prim_prince_test.2779555782
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/462.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/463.prim_prince_test.1244073029
Short name T461
Test name
Test status
Simulation time 2113271890 ps
CPU time 37.57 seconds
Started Sep 03 11:27:26 PM UTC 24
Finished Sep 03 11:28:13 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1244073029 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 463.prim_prince_test.1244073029
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/463.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/464.prim_prince_test.2843751911
Short name T462
Test name
Test status
Simulation time 2159329104 ps
CPU time 37.43 seconds
Started Sep 03 11:27:26 PM UTC 24
Finished Sep 03 11:28:13 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2843751911 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 464.prim_prince_test.2843751911
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/464.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/465.prim_prince_test.187873492
Short name T439
Test name
Test status
Simulation time 1105605165 ps
CPU time 20.12 seconds
Started Sep 03 11:27:26 PM UTC 24
Finished Sep 03 11:27:52 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=187873492 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 465.prim_prince_test.187873492
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/465.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/466.prim_prince_test.913930531
Short name T435
Test name
Test status
Simulation time 936421489 ps
CPU time 16.79 seconds
Started Sep 03 11:27:27 PM UTC 24
Finished Sep 03 11:27:48 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=913930531 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 466.prim_prince_test.913930531
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/466.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/467.prim_prince_test.2237217597
Short name T474
Test name
Test status
Simulation time 2506273894 ps
CPU time 44.43 seconds
Started Sep 03 11:27:27 PM UTC 24
Finished Sep 03 11:28:21 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2237217597 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 467.prim_prince_test.2237217597
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/467.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/468.prim_prince_test.2881370955
Short name T478
Test name
Test status
Simulation time 2646437972 ps
CPU time 46.05 seconds
Started Sep 03 11:27:27 PM UTC 24
Finished Sep 03 11:28:23 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2881370955 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 468.prim_prince_test.2881370955
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/468.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/469.prim_prince_test.660164678
Short name T482
Test name
Test status
Simulation time 3012300735 ps
CPU time 54.02 seconds
Started Sep 03 11:27:27 PM UTC 24
Finished Sep 03 11:28:33 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=660164678 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 469.prim_prince_test.660164678
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/469.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/47.prim_prince_test.56559250
Short name T62
Test name
Test status
Simulation time 3046764627 ps
CPU time 54.46 seconds
Started Sep 03 11:21:32 PM UTC 24
Finished Sep 03 11:22:39 PM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=56559250 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 47.prim_prince_test.56559250
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/47.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/470.prim_prince_test.4148741351
Short name T490
Test name
Test status
Simulation time 3707446962 ps
CPU time 66.14 seconds
Started Sep 03 11:27:28 PM UTC 24
Finished Sep 03 11:28:49 PM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4148741351 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 470.prim_prince_test.4148741351
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/470.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/471.prim_prince_test.738462891
Short name T465
Test name
Test status
Simulation time 2048487891 ps
CPU time 36.46 seconds
Started Sep 03 11:27:29 PM UTC 24
Finished Sep 03 11:28:15 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=738462891 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 471.prim_prince_test.738462891
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/471.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/472.prim_prince_test.3941783573
Short name T452
Test name
Test status
Simulation time 1521377441 ps
CPU time 27.37 seconds
Started Sep 03 11:27:29 PM UTC 24
Finished Sep 03 11:28:04 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3941783573 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 472.prim_prince_test.3941783573
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/472.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/473.prim_prince_test.1173302531
Short name T480
Test name
Test status
Simulation time 2887855514 ps
CPU time 50.67 seconds
Started Sep 03 11:27:29 PM UTC 24
Finished Sep 03 11:28:32 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1173302531 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 473.prim_prince_test.1173302531
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/473.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/474.prim_prince_test.3148300004
Short name T449
Test name
Test status
Simulation time 1440856797 ps
CPU time 25.24 seconds
Started Sep 03 11:27:29 PM UTC 24
Finished Sep 03 11:28:01 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3148300004 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 474.prim_prince_test.3148300004
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/474.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/475.prim_prince_test.3181912478
Short name T471
Test name
Test status
Simulation time 2296358676 ps
CPU time 40.14 seconds
Started Sep 03 11:27:31 PM UTC 24
Finished Sep 03 11:28:21 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3181912478 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 475.prim_prince_test.3181912478
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/475.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/476.prim_prince_test.3170160695
Short name T444
Test name
Test status
Simulation time 1140385628 ps
CPU time 20.51 seconds
Started Sep 03 11:27:31 PM UTC 24
Finished Sep 03 11:27:56 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3170160695 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 476.prim_prince_test.3170160695
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/476.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/477.prim_prince_test.3018715422
Short name T456
Test name
Test status
Simulation time 1677640059 ps
CPU time 30.03 seconds
Started Sep 03 11:27:32 PM UTC 24
Finished Sep 03 11:28:09 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3018715422 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 477.prim_prince_test.3018715422
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/477.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/478.prim_prince_test.4126748404
Short name T488
Test name
Test status
Simulation time 3243359970 ps
CPU time 60.31 seconds
Started Sep 03 11:27:33 PM UTC 24
Finished Sep 03 11:28:47 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4126748404 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 478.prim_prince_test.4126748404
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/478.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/479.prim_prince_test.2541315666
Short name T494
Test name
Test status
Simulation time 3696151847 ps
CPU time 69.03 seconds
Started Sep 03 11:27:33 PM UTC 24
Finished Sep 03 11:28:58 PM UTC 24
Peak memory 154652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2541315666 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 479.prim_prince_test.2541315666
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/479.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/48.prim_prince_test.3987902725
Short name T41
Test name
Test status
Simulation time 2495368078 ps
CPU time 44.69 seconds
Started Sep 03 11:21:32 PM UTC 24
Finished Sep 03 11:22:28 PM UTC 24
Peak memory 154644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3987902725 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 48.prim_prince_test.3987902725
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/48.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/480.prim_prince_test.1916275890
Short name T467
Test name
Test status
Simulation time 1927478022 ps
CPU time 34.61 seconds
Started Sep 03 11:27:35 PM UTC 24
Finished Sep 03 11:28:17 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1916275890 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 480.prim_prince_test.1916275890
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/480.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/481.prim_prince_test.2178244278
Short name T481
Test name
Test status
Simulation time 2634677403 ps
CPU time 47.07 seconds
Started Sep 03 11:27:35 PM UTC 24
Finished Sep 03 11:28:33 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2178244278 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 481.prim_prince_test.2178244278
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/481.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/482.prim_prince_test.3679235137
Short name T484
Test name
Test status
Simulation time 2888056142 ps
CPU time 51.57 seconds
Started Sep 03 11:27:35 PM UTC 24
Finished Sep 03 11:28:38 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3679235137 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 482.prim_prince_test.3679235137
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/482.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/483.prim_prince_test.3245073409
Short name T495
Test name
Test status
Simulation time 3701606967 ps
CPU time 67.21 seconds
Started Sep 03 11:27:36 PM UTC 24
Finished Sep 03 11:28:59 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3245073409 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 483.prim_prince_test.3245073409
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/483.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/484.prim_prince_test.3264292040
Short name T491
Test name
Test status
Simulation time 3417482019 ps
CPU time 63.49 seconds
Started Sep 03 11:27:36 PM UTC 24
Finished Sep 03 11:28:54 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3264292040 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 484.prim_prince_test.3264292040
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/484.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/485.prim_prince_test.1872206893
Short name T470
Test name
Test status
Simulation time 1923360587 ps
CPU time 34.53 seconds
Started Sep 03 11:27:37 PM UTC 24
Finished Sep 03 11:28:20 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1872206893 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 485.prim_prince_test.1872206893
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/485.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/486.prim_prince_test.1112919314
Short name T483
Test name
Test status
Simulation time 2548834067 ps
CPU time 46.12 seconds
Started Sep 03 11:27:37 PM UTC 24
Finished Sep 03 11:28:34 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1112919314 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 486.prim_prince_test.1112919314
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/486.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/487.prim_prince_test.3391704102
Short name T487
Test name
Test status
Simulation time 2956873015 ps
CPU time 54.59 seconds
Started Sep 03 11:27:40 PM UTC 24
Finished Sep 03 11:28:47 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3391704102 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 487.prim_prince_test.3391704102
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/487.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/488.prim_prince_test.1825569712
Short name T469
Test name
Test status
Simulation time 1773359668 ps
CPU time 32.08 seconds
Started Sep 03 11:27:40 PM UTC 24
Finished Sep 03 11:28:20 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1825569712 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 488.prim_prince_test.1825569712
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/488.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/489.prim_prince_test.2689334808
Short name T492
Test name
Test status
Simulation time 3229604588 ps
CPU time 60.71 seconds
Started Sep 03 11:27:40 PM UTC 24
Finished Sep 03 11:28:55 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2689334808 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 489.prim_prince_test.2689334808
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/489.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/49.prim_prince_test.597069845
Short name T38
Test name
Test status
Simulation time 2397658420 ps
CPU time 42.07 seconds
Started Sep 03 11:21:33 PM UTC 24
Finished Sep 03 11:22:25 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=597069845 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 49.prim_prince_test.597069845
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/49.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/490.prim_prince_test.1277760620
Short name T489
Test name
Test status
Simulation time 2882226404 ps
CPU time 54.21 seconds
Started Sep 03 11:27:41 PM UTC 24
Finished Sep 03 11:28:48 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1277760620 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 490.prim_prince_test.1277760620
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/490.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/491.prim_prince_test.3137158158
Short name T498
Test name
Test status
Simulation time 3732219176 ps
CPU time 70.55 seconds
Started Sep 03 11:27:42 PM UTC 24
Finished Sep 03 11:29:10 PM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3137158158 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 491.prim_prince_test.3137158158
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/491.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/492.prim_prince_test.36785927
Short name T496
Test name
Test status
Simulation time 3330376559 ps
CPU time 59.51 seconds
Started Sep 03 11:27:46 PM UTC 24
Finished Sep 03 11:29:00 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=36785927 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 492.prim_prince_test.36785927
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/492.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/493.prim_prince_test.2759446767
Short name T497
Test name
Test status
Simulation time 3170903938 ps
CPU time 61.06 seconds
Started Sep 03 11:27:49 PM UTC 24
Finished Sep 03 11:29:05 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2759446767 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 493.prim_prince_test.2759446767
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/493.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/494.prim_prince_test.1390526962
Short name T499
Test name
Test status
Simulation time 3542940889 ps
CPU time 66.42 seconds
Started Sep 03 11:27:49 PM UTC 24
Finished Sep 03 11:29:12 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1390526962 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 494.prim_prince_test.1390526962
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/494.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/495.prim_prince_test.267829060
Short name T493
Test name
Test status
Simulation time 2841747341 ps
CPU time 54.65 seconds
Started Sep 03 11:27:49 PM UTC 24
Finished Sep 03 11:28:56 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=267829060 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 495.prim_prince_test.267829060
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/495.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/496.prim_prince_test.174813108
Short name T477
Test name
Test status
Simulation time 1510609754 ps
CPU time 26.81 seconds
Started Sep 03 11:27:49 PM UTC 24
Finished Sep 03 11:28:23 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=174813108 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 496.prim_prince_test.174813108
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/496.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/497.prim_prince_test.3988135818
Short name T475
Test name
Test status
Simulation time 1439456520 ps
CPU time 26.06 seconds
Started Sep 03 11:27:49 PM UTC 24
Finished Sep 03 11:28:22 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3988135818 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 497.prim_prince_test.3988135818
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/497.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/498.prim_prince_test.2329273857
Short name T500
Test name
Test status
Simulation time 3408604531 ps
CPU time 64.74 seconds
Started Sep 03 11:27:52 PM UTC 24
Finished Sep 03 11:29:12 PM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2329273857 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 498.prim_prince_test.2329273857
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/498.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/499.prim_prince_test.2111807764
Short name T476
Test name
Test status
Simulation time 1374348528 ps
CPU time 24.69 seconds
Started Sep 03 11:27:52 PM UTC 24
Finished Sep 03 11:28:22 PM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2111807764 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 499.prim_prince_test.2111807764
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/499.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/5.prim_prince_test.575507235
Short name T8
Test name
Test status
Simulation time 1357939669 ps
CPU time 22.49 seconds
Started Sep 03 11:21:22 PM UTC 24
Finished Sep 03 11:21:51 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=575507235 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 5.prim_prince_test.575507235
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/5.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/50.prim_prince_test.2126412175
Short name T32
Test name
Test status
Simulation time 2088816510 ps
CPU time 37.52 seconds
Started Sep 03 11:21:33 PM UTC 24
Finished Sep 03 11:22:20 PM UTC 24
Peak memory 154480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2126412175 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 50.prim_prince_test.2126412175
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/50.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/51.prim_prince_test.1645503242
Short name T50
Test name
Test status
Simulation time 2715005426 ps
CPU time 48.46 seconds
Started Sep 03 11:21:33 PM UTC 24
Finished Sep 03 11:22:33 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1645503242 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 51.prim_prince_test.1645503242
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/51.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/52.prim_prince_test.766577495
Short name T22
Test name
Test status
Simulation time 1559446220 ps
CPU time 27.76 seconds
Started Sep 03 11:21:33 PM UTC 24
Finished Sep 03 11:22:08 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=766577495 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 52.prim_prince_test.766577495
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/52.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/53.prim_prince_test.555950636
Short name T68
Test name
Test status
Simulation time 3235369087 ps
CPU time 57.36 seconds
Started Sep 03 11:21:33 PM UTC 24
Finished Sep 03 11:22:44 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=555950636 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 53.prim_prince_test.555950636
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/53.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/54.prim_prince_test.1332841824
Short name T58
Test name
Test status
Simulation time 2859184938 ps
CPU time 50.97 seconds
Started Sep 03 11:21:34 PM UTC 24
Finished Sep 03 11:22:37 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1332841824 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 54.prim_prince_test.1332841824
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/54.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/55.prim_prince_test.1860388346
Short name T52
Test name
Test status
Simulation time 2698323447 ps
CPU time 48.1 seconds
Started Sep 03 11:21:34 PM UTC 24
Finished Sep 03 11:22:34 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1860388346 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 55.prim_prince_test.1860388346
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/55.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/56.prim_prince_test.4137018522
Short name T28
Test name
Test status
Simulation time 1684693760 ps
CPU time 29.77 seconds
Started Sep 03 11:21:35 PM UTC 24
Finished Sep 03 11:22:13 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4137018522 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 56.prim_prince_test.4137018522
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/56.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/57.prim_prince_test.1600840914
Short name T34
Test name
Test status
Simulation time 2050568536 ps
CPU time 36.24 seconds
Started Sep 03 11:21:36 PM UTC 24
Finished Sep 03 11:22:21 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1600840914 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 57.prim_prince_test.1600840914
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/57.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/58.prim_prince_test.620923449
Short name T17
Test name
Test status
Simulation time 1279860536 ps
CPU time 23.07 seconds
Started Sep 03 11:21:37 PM UTC 24
Finished Sep 03 11:22:05 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=620923449 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 58.prim_prince_test.620923449
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/58.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/59.prim_prince_test.2636722704
Short name T43
Test name
Test status
Simulation time 2206462272 ps
CPU time 38.94 seconds
Started Sep 03 11:21:40 PM UTC 24
Finished Sep 03 11:22:28 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2636722704 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 59.prim_prince_test.2636722704
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/59.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/6.prim_prince_test.2925596478
Short name T4
Test name
Test status
Simulation time 1100256246 ps
CPU time 18.96 seconds
Started Sep 03 11:21:23 PM UTC 24
Finished Sep 03 11:21:48 PM UTC 24
Peak memory 154588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2925596478 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 6.prim_prince_test.2925596478
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/6.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/60.prim_prince_test.2896942540
Short name T23
Test name
Test status
Simulation time 1236042162 ps
CPU time 22.5 seconds
Started Sep 03 11:21:42 PM UTC 24
Finished Sep 03 11:22:10 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2896942540 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 60.prim_prince_test.2896942540
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/60.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/61.prim_prince_test.940757608
Short name T29
Test name
Test status
Simulation time 1211760756 ps
CPU time 21.8 seconds
Started Sep 03 11:21:47 PM UTC 24
Finished Sep 03 11:22:14 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=940757608 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 61.prim_prince_test.940757608
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/61.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/62.prim_prince_test.491054262
Short name T21
Test name
Test status
Simulation time 875985872 ps
CPU time 15.93 seconds
Started Sep 03 11:21:48 PM UTC 24
Finished Sep 03 11:22:08 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=491054262 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 62.prim_prince_test.491054262
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/62.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/63.prim_prince_test.2176967779
Short name T39
Test name
Test status
Simulation time 1694657306 ps
CPU time 30.41 seconds
Started Sep 03 11:21:48 PM UTC 24
Finished Sep 03 11:22:26 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2176967779 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 63.prim_prince_test.2176967779
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/63.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/64.prim_prince_test.4106020747
Short name T51
Test name
Test status
Simulation time 1928974025 ps
CPU time 34.96 seconds
Started Sep 03 11:21:50 PM UTC 24
Finished Sep 03 11:22:33 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4106020747 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 64.prim_prince_test.4106020747
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/64.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/65.prim_prince_test.190275082
Short name T57
Test name
Test status
Simulation time 2061345035 ps
CPU time 36.8 seconds
Started Sep 03 11:21:51 PM UTC 24
Finished Sep 03 11:22:37 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=190275082 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 65.prim_prince_test.190275082
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/65.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/66.prim_prince_test.2478780660
Short name T35
Test name
Test status
Simulation time 1302558094 ps
CPU time 23.55 seconds
Started Sep 03 11:21:52 PM UTC 24
Finished Sep 03 11:22:21 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2478780660 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 66.prim_prince_test.2478780660
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/66.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/67.prim_prince_test.1714538248
Short name T64
Test name
Test status
Simulation time 2192403540 ps
CPU time 39.03 seconds
Started Sep 03 11:21:52 PM UTC 24
Finished Sep 03 11:22:40 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1714538248 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 67.prim_prince_test.1714538248
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/67.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/68.prim_prince_test.1752572338
Short name T95
Test name
Test status
Simulation time 3336898965 ps
CPU time 59.67 seconds
Started Sep 03 11:21:57 PM UTC 24
Finished Sep 03 11:23:10 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1752572338 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 68.prim_prince_test.1752572338
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/68.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/69.prim_prince_test.1228409753
Short name T99
Test name
Test status
Simulation time 3348884007 ps
CPU time 60.07 seconds
Started Sep 03 11:21:59 PM UTC 24
Finished Sep 03 11:23:13 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1228409753 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 69.prim_prince_test.1228409753
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/69.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/7.prim_prince_test.1942490859
Short name T3
Test name
Test status
Simulation time 1079473221 ps
CPU time 18.56 seconds
Started Sep 03 11:21:23 PM UTC 24
Finished Sep 03 11:21:47 PM UTC 24
Peak memory 154276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1942490859 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 7.prim_prince_test.1942490859
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/7.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/70.prim_prince_test.645535222
Short name T76
Test name
Test status
Simulation time 2245513146 ps
CPU time 39.5 seconds
Started Sep 03 11:22:01 PM UTC 24
Finished Sep 03 11:22:50 PM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=645535222 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 70.prim_prince_test.645535222
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/70.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/71.prim_prince_test.3558799505
Short name T66
Test name
Test status
Simulation time 1834385500 ps
CPU time 32.51 seconds
Started Sep 03 11:22:02 PM UTC 24
Finished Sep 03 11:22:43 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3558799505 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 71.prim_prince_test.3558799505
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/71.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/72.prim_prince_test.2216460768
Short name T88
Test name
Test status
Simulation time 2520307259 ps
CPU time 44.19 seconds
Started Sep 03 11:22:04 PM UTC 24
Finished Sep 03 11:22:59 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2216460768 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 72.prim_prince_test.2216460768
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/72.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/73.prim_prince_test.631621136
Short name T110
Test name
Test status
Simulation time 3423326197 ps
CPU time 60.15 seconds
Started Sep 03 11:22:04 PM UTC 24
Finished Sep 03 11:23:18 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=631621136 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 73.prim_prince_test.631621136
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/73.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/74.prim_prince_test.3226376388
Short name T78
Test name
Test status
Simulation time 2101015937 ps
CPU time 37.02 seconds
Started Sep 03 11:22:05 PM UTC 24
Finished Sep 03 11:22:51 PM UTC 24
Peak memory 154116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3226376388 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 74.prim_prince_test.3226376388
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/74.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/75.prim_prince_test.627294276
Short name T82
Test name
Test status
Simulation time 2151885480 ps
CPU time 38.69 seconds
Started Sep 03 11:22:05 PM UTC 24
Finished Sep 03 11:22:53 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=627294276 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 75.prim_prince_test.627294276
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/75.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/76.prim_prince_test.4201117875
Short name T59
Test name
Test status
Simulation time 1405344131 ps
CPU time 25.22 seconds
Started Sep 03 11:22:06 PM UTC 24
Finished Sep 03 11:22:38 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4201117875 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 76.prim_prince_test.4201117875
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/76.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/77.prim_prince_test.1375481531
Short name T79
Test name
Test status
Simulation time 2072073937 ps
CPU time 36.59 seconds
Started Sep 03 11:22:07 PM UTC 24
Finished Sep 03 11:22:52 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1375481531 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 77.prim_prince_test.1375481531
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/77.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/78.prim_prince_test.483704706
Short name T92
Test name
Test status
Simulation time 2745228994 ps
CPU time 48.97 seconds
Started Sep 03 11:22:08 PM UTC 24
Finished Sep 03 11:23:08 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=483704706 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 78.prim_prince_test.483704706
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/78.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/79.prim_prince_test.1203526887
Short name T102
Test name
Test status
Simulation time 2962625273 ps
CPU time 53.2 seconds
Started Sep 03 11:22:09 PM UTC 24
Finished Sep 03 11:23:14 PM UTC 24
Peak memory 154240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1203526887 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 79.prim_prince_test.1203526887
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/79.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/8.prim_prince_test.248240994
Short name T9
Test name
Test status
Simulation time 1529888685 ps
CPU time 26.48 seconds
Started Sep 03 11:21:24 PM UTC 24
Finished Sep 03 11:21:57 PM UTC 24
Peak memory 154456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=248240994 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 8.prim_prince_test.248240994
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/8.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/80.prim_prince_test.3659696441
Short name T84
Test name
Test status
Simulation time 2071934937 ps
CPU time 37.08 seconds
Started Sep 03 11:22:09 PM UTC 24
Finished Sep 03 11:22:54 PM UTC 24
Peak memory 154292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3659696441 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 80.prim_prince_test.3659696441
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/80.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/81.prim_prince_test.1565046882
Short name T83
Test name
Test status
Simulation time 2066602755 ps
CPU time 36.8 seconds
Started Sep 03 11:22:09 PM UTC 24
Finished Sep 03 11:22:54 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1565046882 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 81.prim_prince_test.1565046882
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/81.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/82.prim_prince_test.3415570263
Short name T100
Test name
Test status
Simulation time 2824375621 ps
CPU time 50.69 seconds
Started Sep 03 11:22:11 PM UTC 24
Finished Sep 03 11:23:13 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3415570263 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 82.prim_prince_test.3415570263
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/82.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/83.prim_prince_test.2395675141
Short name T85
Test name
Test status
Simulation time 1918745199 ps
CPU time 34.54 seconds
Started Sep 03 11:22:13 PM UTC 24
Finished Sep 03 11:22:55 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2395675141 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 83.prim_prince_test.2395675141
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/83.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/84.prim_prince_test.1415087173
Short name T108
Test name
Test status
Simulation time 2968450761 ps
CPU time 52.54 seconds
Started Sep 03 11:22:13 PM UTC 24
Finished Sep 03 11:23:17 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1415087173 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 84.prim_prince_test.1415087173
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/84.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/85.prim_prince_test.3191422934
Short name T86
Test name
Test status
Simulation time 1941749733 ps
CPU time 34.57 seconds
Started Sep 03 11:22:13 PM UTC 24
Finished Sep 03 11:22:56 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3191422934 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 85.prim_prince_test.3191422934
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/85.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/86.prim_prince_test.3921091907
Short name T53
Test name
Test status
Simulation time 882078279 ps
CPU time 16.09 seconds
Started Sep 03 11:22:14 PM UTC 24
Finished Sep 03 11:22:34 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3921091907 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 86.prim_prince_test.3921091907
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/86.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/87.prim_prince_test.3979698193
Short name T56
Test name
Test status
Simulation time 984721459 ps
CPU time 17.93 seconds
Started Sep 03 11:22:14 PM UTC 24
Finished Sep 03 11:22:37 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3979698193 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 87.prim_prince_test.3979698193
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/87.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/88.prim_prince_test.1540819655
Short name T112
Test name
Test status
Simulation time 3003863613 ps
CPU time 53.53 seconds
Started Sep 03 11:22:15 PM UTC 24
Finished Sep 03 11:23:21 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1540819655 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 88.prim_prince_test.1540819655
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/88.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/89.prim_prince_test.24740120
Short name T55
Test name
Test status
Simulation time 865269881 ps
CPU time 15.45 seconds
Started Sep 03 11:22:16 PM UTC 24
Finished Sep 03 11:22:36 PM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=24740120 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 89.prim_prince_test.24740120
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/89.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/9.prim_prince_test.3661176615
Short name T25
Test name
Test status
Simulation time 2259391545 ps
CPU time 39.06 seconds
Started Sep 03 11:21:24 PM UTC 24
Finished Sep 03 11:22:12 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3661176615 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 9.prim_prince_test.3661176615
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/9.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/90.prim_prince_test.368543896
Short name T65
Test name
Test status
Simulation time 950781009 ps
CPU time 17.79 seconds
Started Sep 03 11:22:20 PM UTC 24
Finished Sep 03 11:22:42 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=368543896 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 90.prim_prince_test.368543896
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/90.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/91.prim_prince_test.2594759911
Short name T60
Test name
Test status
Simulation time 801153645 ps
CPU time 14.46 seconds
Started Sep 03 11:22:20 PM UTC 24
Finished Sep 03 11:22:39 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2594759911 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 91.prim_prince_test.2594759911
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/91.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/92.prim_prince_test.3693073095
Short name T139
Test name
Test status
Simulation time 3703690085 ps
CPU time 65.99 seconds
Started Sep 03 11:22:20 PM UTC 24
Finished Sep 03 11:23:41 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3693073095 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 92.prim_prince_test.3693073095
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/92.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/93.prim_prince_test.889221882
Short name T111
Test name
Test status
Simulation time 2637321247 ps
CPU time 46.29 seconds
Started Sep 03 11:22:21 PM UTC 24
Finished Sep 03 11:23:18 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=889221882 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 93.prim_prince_test.889221882
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/93.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/94.prim_prince_test.151955305
Short name T81
Test name
Test status
Simulation time 1339312742 ps
CPU time 23.67 seconds
Started Sep 03 11:22:22 PM UTC 24
Finished Sep 03 11:22:52 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=151955305 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 94.prim_prince_test.151955305
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/94.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/95.prim_prince_test.2016185396
Short name T70
Test name
Test status
Simulation time 936117400 ps
CPU time 16.92 seconds
Started Sep 03 11:22:24 PM UTC 24
Finished Sep 03 11:22:46 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2016185396 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 95.prim_prince_test.2016185396
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/95.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/96.prim_prince_test.3761504183
Short name T106
Test name
Test status
Simulation time 2373047768 ps
CPU time 42.2 seconds
Started Sep 03 11:22:24 PM UTC 24
Finished Sep 03 11:23:17 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3761504183 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 96.prim_prince_test.3761504183
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/96.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/97.prim_prince_test.521000518
Short name T133
Test name
Test status
Simulation time 3145938666 ps
CPU time 56.37 seconds
Started Sep 03 11:22:27 PM UTC 24
Finished Sep 03 11:23:36 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=521000518 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 97.prim_prince_test.521000518
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/97.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/98.prim_prince_test.261841658
Short name T130
Test name
Test status
Simulation time 2970085201 ps
CPU time 53.26 seconds
Started Sep 03 11:22:27 PM UTC 24
Finished Sep 03 11:23:32 PM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=261841658 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 98.prim_prince_test.261841658
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/98.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default/99.prim_prince_test.1196083892
Short name T80
Test name
Test status
Simulation time 1093768298 ps
CPU time 19.95 seconds
Started Sep 03 11:22:27 PM UTC 24
Finished Sep 03 11:22:52 PM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1196083892 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 99.prim_prince_test.1196083892
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_prince-sim-vcs/99.prim_prince_test/latest
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