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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00 100.00


Total test records in report: 500
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html
T251 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/228.prim_prince_test.829653099 Sep 09 10:55:32 AM UTC 24 Sep 09 10:56:54 AM UTC 24 3692879009 ps
T252 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/226.prim_prince_test.1281005504 Sep 09 10:55:32 AM UTC 24 Sep 09 10:56:55 AM UTC 24 3626526612 ps
T253 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/240.prim_prince_test.3904157210 Sep 09 10:55:49 AM UTC 24 Sep 09 10:56:55 AM UTC 24 2928225578 ps
T254 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/271.prim_prince_test.271476345 Sep 09 10:56:26 AM UTC 24 Sep 09 10:56:55 AM UTC 24 1192779450 ps
T255 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/266.prim_prince_test.2185460431 Sep 09 10:56:20 AM UTC 24 Sep 09 10:56:57 AM UTC 24 1619348970 ps
T256 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/258.prim_prince_test.2556463737 Sep 09 10:56:09 AM UTC 24 Sep 09 10:56:58 AM UTC 24 2164852814 ps
T257 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/274.prim_prince_test.2214685182 Sep 09 10:56:29 AM UTC 24 Sep 09 10:57:00 AM UTC 24 1364594852 ps
T258 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/259.prim_prince_test.3410282068 Sep 09 10:56:09 AM UTC 24 Sep 09 10:57:01 AM UTC 24 2283232681 ps
T259 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/279.prim_prince_test.3505526340 Sep 09 10:56:32 AM UTC 24 Sep 09 10:57:04 AM UTC 24 1319712395 ps
T260 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/284.prim_prince_test.4045402185 Sep 09 10:56:41 AM UTC 24 Sep 09 10:57:04 AM UTC 24 1016912122 ps
T261 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/246.prim_prince_test.2362485287 Sep 09 10:55:56 AM UTC 24 Sep 09 10:57:04 AM UTC 24 2977901898 ps
T262 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/237.prim_prince_test.3867351778 Sep 09 10:55:43 AM UTC 24 Sep 09 10:57:04 AM UTC 24 3644105052 ps
T263 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/261.prim_prince_test.1784161171 Sep 09 10:56:12 AM UTC 24 Sep 09 10:57:04 AM UTC 24 2300083131 ps
T264 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/236.prim_prince_test.593336661 Sep 09 10:55:41 AM UTC 24 Sep 09 10:57:04 AM UTC 24 3734207759 ps
T265 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/245.prim_prince_test.1774759487 Sep 09 10:55:53 AM UTC 24 Sep 09 10:57:07 AM UTC 24 3305542092 ps
T266 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/265.prim_prince_test.2620401973 Sep 09 10:56:19 AM UTC 24 Sep 09 10:57:08 AM UTC 24 2068576299 ps
T267 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/257.prim_prince_test.3710091771 Sep 09 10:56:08 AM UTC 24 Sep 09 10:57:11 AM UTC 24 2807652319 ps
T268 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/267.prim_prince_test.933848601 Sep 09 10:56:25 AM UTC 24 Sep 09 10:57:13 AM UTC 24 2066963809 ps
T269 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/281.prim_prince_test.1005186725 Sep 09 10:56:34 AM UTC 24 Sep 09 10:57:13 AM UTC 24 1650004578 ps
T270 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/243.prim_prince_test.1375171747 Sep 09 10:55:50 AM UTC 24 Sep 09 10:57:14 AM UTC 24 3650402212 ps
T271 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/280.prim_prince_test.2971348818 Sep 09 10:56:33 AM UTC 24 Sep 09 10:57:14 AM UTC 24 1793059762 ps
T272 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/273.prim_prince_test.3898755324 Sep 09 10:56:27 AM UTC 24 Sep 09 10:57:15 AM UTC 24 2086750018 ps
T273 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/291.prim_prince_test.2827490654 Sep 09 10:56:54 AM UTC 24 Sep 09 10:57:16 AM UTC 24 906249477 ps
T274 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/268.prim_prince_test.1862572900 Sep 09 10:56:25 AM UTC 24 Sep 09 10:57:17 AM UTC 24 2269257995 ps
T275 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/276.prim_prince_test.2821174734 Sep 09 10:56:30 AM UTC 24 Sep 09 10:57:18 AM UTC 24 2072878956 ps
T276 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/262.prim_prince_test.1435669366 Sep 09 10:56:13 AM UTC 24 Sep 09 10:57:21 AM UTC 24 3000341770 ps
T277 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/288.prim_prince_test.2468144827 Sep 09 10:56:50 AM UTC 24 Sep 09 10:57:22 AM UTC 24 1377179951 ps
T278 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/298.prim_prince_test.3841543455 Sep 09 10:57:01 AM UTC 24 Sep 09 10:57:23 AM UTC 24 930675166 ps
T279 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/282.prim_prince_test.2039005629 Sep 09 10:56:34 AM UTC 24 Sep 09 10:57:23 AM UTC 24 2092080469 ps
T280 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/294.prim_prince_test.3860775238 Sep 09 10:56:56 AM UTC 24 Sep 09 10:57:23 AM UTC 24 1145695720 ps
T281 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/253.prim_prince_test.3146163009 Sep 09 10:56:03 AM UTC 24 Sep 09 10:57:23 AM UTC 24 3598706971 ps
T282 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/275.prim_prince_test.3846833271 Sep 09 10:56:30 AM UTC 24 Sep 09 10:57:25 AM UTC 24 2456593328 ps
T283 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/278.prim_prince_test.3503099703 Sep 09 10:56:32 AM UTC 24 Sep 09 10:57:25 AM UTC 24 2323747007 ps
T284 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/285.prim_prince_test.2611827976 Sep 09 10:56:43 AM UTC 24 Sep 09 10:57:26 AM UTC 24 1821994956 ps
T285 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/269.prim_prince_test.4106467643 Sep 09 10:56:25 AM UTC 24 Sep 09 10:57:26 AM UTC 24 2686626998 ps
T286 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/303.prim_prince_test.3466919512 Sep 09 10:57:06 AM UTC 24 Sep 09 10:57:26 AM UTC 24 833121993 ps
T287 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/272.prim_prince_test.3188087265 Sep 09 10:56:26 AM UTC 24 Sep 09 10:57:26 AM UTC 24 2666112199 ps
T288 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/295.prim_prince_test.2919240079 Sep 09 10:56:56 AM UTC 24 Sep 09 10:57:28 AM UTC 24 1414998201 ps
T289 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/304.prim_prince_test.471912899 Sep 09 10:57:06 AM UTC 24 Sep 09 10:57:30 AM UTC 24 1011207929 ps
T290 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/270.prim_prince_test.3632062017 Sep 09 10:56:25 AM UTC 24 Sep 09 10:57:32 AM UTC 24 3001313284 ps
T291 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/292.prim_prince_test.2784900415 Sep 09 10:56:54 AM UTC 24 Sep 09 10:57:32 AM UTC 24 1630812726 ps
T292 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/277.prim_prince_test.2113045455 Sep 09 10:56:31 AM UTC 24 Sep 09 10:57:33 AM UTC 24 2736779108 ps
T293 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/264.prim_prince_test.1666705468 Sep 09 10:56:17 AM UTC 24 Sep 09 10:57:36 AM UTC 24 3454684558 ps
T294 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/307.prim_prince_test.4073583255 Sep 09 10:57:08 AM UTC 24 Sep 09 10:57:36 AM UTC 24 1166524205 ps
T295 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/297.prim_prince_test.522675877 Sep 09 10:56:59 AM UTC 24 Sep 09 10:57:43 AM UTC 24 1961991678 ps
T296 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/300.prim_prince_test.4173620357 Sep 09 10:57:04 AM UTC 24 Sep 09 10:57:43 AM UTC 24 1706541562 ps
T297 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/306.prim_prince_test.581951475 Sep 09 10:57:08 AM UTC 24 Sep 09 10:57:44 AM UTC 24 1531880675 ps
T298 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/289.prim_prince_test.4008577386 Sep 09 10:56:50 AM UTC 24 Sep 09 10:57:44 AM UTC 24 2333799197 ps
T299 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/327.prim_prince_test.2652559141 Sep 09 10:57:28 AM UTC 24 Sep 09 10:57:46 AM UTC 24 752483822 ps
T300 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/299.prim_prince_test.1051422171 Sep 09 10:57:02 AM UTC 24 Sep 09 10:57:47 AM UTC 24 1941251272 ps
T301 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/311.prim_prince_test.1820235466 Sep 09 10:57:16 AM UTC 24 Sep 09 10:57:48 AM UTC 24 1423960212 ps
T302 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/322.prim_prince_test.2483279595 Sep 09 10:57:25 AM UTC 24 Sep 09 10:57:50 AM UTC 24 1055559016 ps
T303 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/305.prim_prince_test.1520392414 Sep 09 10:57:06 AM UTC 24 Sep 09 10:57:53 AM UTC 24 2024969176 ps
T304 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/290.prim_prince_test.186518940 Sep 09 10:56:54 AM UTC 24 Sep 09 10:57:54 AM UTC 24 2571056521 ps
T305 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/293.prim_prince_test.3303878336 Sep 09 10:56:56 AM UTC 24 Sep 09 10:57:54 AM UTC 24 2586181745 ps
T306 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/321.prim_prince_test.2893805306 Sep 09 10:57:24 AM UTC 24 Sep 09 10:57:54 AM UTC 24 1305819402 ps
T307 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/301.prim_prince_test.4201956596 Sep 09 10:57:04 AM UTC 24 Sep 09 10:57:58 AM UTC 24 2310685348 ps
T308 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/283.prim_prince_test.798499589 Sep 09 10:56:38 AM UTC 24 Sep 09 10:57:58 AM UTC 24 3569387465 ps
T309 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/286.prim_prince_test.2686591748 Sep 09 10:56:48 AM UTC 24 Sep 09 10:57:59 AM UTC 24 3193899032 ps
T310 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/330.prim_prince_test.1300273507 Sep 09 10:57:31 AM UTC 24 Sep 09 10:57:59 AM UTC 24 1243254120 ps
T311 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/319.prim_prince_test.3717898199 Sep 09 10:57:24 AM UTC 24 Sep 09 10:58:01 AM UTC 24 1619288955 ps
T312 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/287.prim_prince_test.1639345342 Sep 09 10:56:49 AM UTC 24 Sep 09 10:58:08 AM UTC 24 3444014591 ps
T313 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/326.prim_prince_test.2921139365 Sep 09 10:57:28 AM UTC 24 Sep 09 10:58:10 AM UTC 24 1829808977 ps
T314 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/318.prim_prince_test.2788407174 Sep 09 10:57:24 AM UTC 24 Sep 09 10:58:10 AM UTC 24 1988904484 ps
T315 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/316.prim_prince_test.1851779858 Sep 09 10:57:19 AM UTC 24 Sep 09 10:58:10 AM UTC 24 2308955657 ps
T316 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/296.prim_prince_test.3654464119 Sep 09 10:56:58 AM UTC 24 Sep 09 10:58:12 AM UTC 24 3329085049 ps
T317 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/344.prim_prince_test.3407535984 Sep 09 10:57:54 AM UTC 24 Sep 09 10:58:13 AM UTC 24 814940853 ps
T318 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/320.prim_prince_test.503186563 Sep 09 10:57:24 AM UTC 24 Sep 09 10:58:14 AM UTC 24 2248177499 ps
T319 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/309.prim_prince_test.791873242 Sep 09 10:57:13 AM UTC 24 Sep 09 10:58:15 AM UTC 24 2738812219 ps
T320 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/325.prim_prince_test.1394935865 Sep 09 10:57:26 AM UTC 24 Sep 09 10:58:17 AM UTC 24 2234514796 ps
T321 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/332.prim_prince_test.284012041 Sep 09 10:57:33 AM UTC 24 Sep 09 10:58:17 AM UTC 24 1894773408 ps
T322 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/315.prim_prince_test.1699605587 Sep 09 10:57:18 AM UTC 24 Sep 09 10:58:18 AM UTC 24 2638278990 ps
T323 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/308.prim_prince_test.1399593383 Sep 09 10:57:11 AM UTC 24 Sep 09 10:58:20 AM UTC 24 3068159530 ps
T324 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/317.prim_prince_test.1525615044 Sep 09 10:57:22 AM UTC 24 Sep 09 10:58:22 AM UTC 24 2663396373 ps
T325 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/310.prim_prince_test.2441130154 Sep 09 10:57:13 AM UTC 24 Sep 09 10:58:22 AM UTC 24 3023462096 ps
T326 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/302.prim_prince_test.1758553707 Sep 09 10:57:06 AM UTC 24 Sep 09 10:58:22 AM UTC 24 3443916818 ps
T327 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/351.prim_prince_test.2860773254 Sep 09 10:58:00 AM UTC 24 Sep 09 10:58:23 AM UTC 24 945839401 ps
T328 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/338.prim_prince_test.3865652615 Sep 09 10:57:45 AM UTC 24 Sep 09 10:58:25 AM UTC 24 1747179501 ps
T329 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/324.prim_prince_test.1000874475 Sep 09 10:57:26 AM UTC 24 Sep 09 10:58:25 AM UTC 24 2630803045 ps
T330 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/339.prim_prince_test.1126137022 Sep 09 10:57:45 AM UTC 24 Sep 09 10:58:26 AM UTC 24 1741124388 ps
T331 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/336.prim_prince_test.1853613193 Sep 09 10:57:44 AM UTC 24 Sep 09 10:58:26 AM UTC 24 1875805855 ps
T332 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/347.prim_prince_test.911909709 Sep 09 10:57:55 AM UTC 24 Sep 09 10:58:26 AM UTC 24 1388414552 ps
T333 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/335.prim_prince_test.2891407502 Sep 09 10:57:37 AM UTC 24 Sep 09 10:58:28 AM UTC 24 2246508180 ps
T334 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/323.prim_prince_test.3889554438 Sep 09 10:57:26 AM UTC 24 Sep 09 10:58:29 AM UTC 24 2757791992 ps
T335 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/356.prim_prince_test.1887177614 Sep 09 10:58:11 AM UTC 24 Sep 09 10:58:30 AM UTC 24 781174091 ps
T336 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/341.prim_prince_test.912930371 Sep 09 10:57:47 AM UTC 24 Sep 09 10:58:31 AM UTC 24 1935751871 ps
T337 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/312.prim_prince_test.3932278313 Sep 09 10:57:16 AM UTC 24 Sep 09 10:58:34 AM UTC 24 3456574944 ps
T338 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/314.prim_prince_test.687626051 Sep 09 10:57:17 AM UTC 24 Sep 09 10:58:37 AM UTC 24 3487368661 ps
T339 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/342.prim_prince_test.3976683845 Sep 09 10:57:49 AM UTC 24 Sep 09 10:58:37 AM UTC 24 2056642136 ps
T340 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/313.prim_prince_test.4040866104 Sep 09 10:57:16 AM UTC 24 Sep 09 10:58:39 AM UTC 24 3647562529 ps
T341 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/340.prim_prince_test.807841430 Sep 09 10:57:46 AM UTC 24 Sep 09 10:58:40 AM UTC 24 2397071152 ps
T342 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/348.prim_prince_test.2733871037 Sep 09 10:57:58 AM UTC 24 Sep 09 10:58:41 AM UTC 24 1870406312 ps
T343 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/362.prim_prince_test.265216315 Sep 09 10:58:18 AM UTC 24 Sep 09 10:58:41 AM UTC 24 972767565 ps
T344 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/337.prim_prince_test.3710552924 Sep 09 10:57:44 AM UTC 24 Sep 09 10:58:42 AM UTC 24 2579507753 ps
T345 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/353.prim_prince_test.4134718132 Sep 09 10:58:09 AM UTC 24 Sep 09 10:58:42 AM UTC 24 1480839212 ps
T346 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/333.prim_prince_test.3123059213 Sep 09 10:57:34 AM UTC 24 Sep 09 10:58:43 AM UTC 24 3081621399 ps
T347 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/334.prim_prince_test.2805927603 Sep 09 10:57:37 AM UTC 24 Sep 09 10:58:44 AM UTC 24 3010867128 ps
T348 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/359.prim_prince_test.3155224012 Sep 09 10:58:15 AM UTC 24 Sep 09 10:58:44 AM UTC 24 1316687480 ps
T349 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/370.prim_prince_test.125142867 Sep 09 10:58:24 AM UTC 24 Sep 09 10:58:45 AM UTC 24 883799742 ps
T350 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/369.prim_prince_test.3952071274 Sep 09 10:58:23 AM UTC 24 Sep 09 10:58:46 AM UTC 24 941721259 ps
T351 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/329.prim_prince_test.342105791 Sep 09 10:57:29 AM UTC 24 Sep 09 10:58:46 AM UTC 24 3379957052 ps
T352 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/345.prim_prince_test.3334632508 Sep 09 10:57:55 AM UTC 24 Sep 09 10:58:47 AM UTC 24 2292581296 ps
T353 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/365.prim_prince_test.3423506499 Sep 09 10:58:21 AM UTC 24 Sep 09 10:58:48 AM UTC 24 1201873725 ps
T354 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/331.prim_prince_test.2860059797 Sep 09 10:57:33 AM UTC 24 Sep 09 10:58:51 AM UTC 24 3417477993 ps
T355 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/328.prim_prince_test.4186740901 Sep 09 10:57:28 AM UTC 24 Sep 09 10:58:52 AM UTC 24 3724103331 ps
T356 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/361.prim_prince_test.3237484702 Sep 09 10:58:16 AM UTC 24 Sep 09 10:58:53 AM UTC 24 1636954792 ps
T357 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/343.prim_prince_test.2834205438 Sep 09 10:57:50 AM UTC 24 Sep 09 10:58:55 AM UTC 24 2845168928 ps
T358 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/350.prim_prince_test.2122134117 Sep 09 10:58:00 AM UTC 24 Sep 09 10:58:56 AM UTC 24 2450688762 ps
T359 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/371.prim_prince_test.1469929666 Sep 09 10:58:26 AM UTC 24 Sep 09 10:58:57 AM UTC 24 1323963402 ps
T360 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/378.prim_prince_test.2018546452 Sep 09 10:58:31 AM UTC 24 Sep 09 10:58:57 AM UTC 24 1077383596 ps
T361 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/375.prim_prince_test.3159026987 Sep 09 10:58:27 AM UTC 24 Sep 09 10:59:01 AM UTC 24 1452560956 ps
T362 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/358.prim_prince_test.1465222649 Sep 09 10:58:13 AM UTC 24 Sep 09 10:59:02 AM UTC 24 2200291568 ps
T363 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/355.prim_prince_test.1778633658 Sep 09 10:58:11 AM UTC 24 Sep 09 10:59:08 AM UTC 24 2524258617 ps
T364 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/368.prim_prince_test.2905897845 Sep 09 10:58:23 AM UTC 24 Sep 09 10:59:12 AM UTC 24 2236202005 ps
T365 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/387.prim_prince_test.1336884490 Sep 09 10:58:43 AM UTC 24 Sep 09 10:59:13 AM UTC 24 1285220773 ps
T366 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/401.prim_prince_test.1381326506 Sep 09 10:58:56 AM UTC 24 Sep 09 10:59:15 AM UTC 24 757160657 ps
T367 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/346.prim_prince_test.2826781687 Sep 09 10:57:55 AM UTC 24 Sep 09 10:59:15 AM UTC 24 3622442860 ps
T368 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/376.prim_prince_test.1065763675 Sep 09 10:58:29 AM UTC 24 Sep 09 10:59:17 AM UTC 24 2090067126 ps
T369 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/363.prim_prince_test.689084329 Sep 09 10:58:18 AM UTC 24 Sep 09 10:59:18 AM UTC 24 2712241885 ps
T370 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/397.prim_prince_test.1210696249 Sep 09 10:58:50 AM UTC 24 Sep 09 10:59:19 AM UTC 24 1228519679 ps
T371 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/372.prim_prince_test.3915888761 Sep 09 10:58:26 AM UTC 24 Sep 09 10:59:19 AM UTC 24 2399508842 ps
T372 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/366.prim_prince_test.4231382173 Sep 09 10:58:23 AM UTC 24 Sep 09 10:59:20 AM UTC 24 2583512615 ps
T373 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/357.prim_prince_test.4009829042 Sep 09 10:58:12 AM UTC 24 Sep 09 10:59:22 AM UTC 24 3169574738 ps
T374 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/377.prim_prince_test.2407753004 Sep 09 10:58:30 AM UTC 24 Sep 09 10:59:22 AM UTC 24 2345580111 ps
T375 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/349.prim_prince_test.3791162031 Sep 09 10:57:59 AM UTC 24 Sep 09 10:59:24 AM UTC 24 3695378410 ps
T376 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/400.prim_prince_test.2871752838 Sep 09 10:58:54 AM UTC 24 Sep 09 10:59:24 AM UTC 24 1283777710 ps
T377 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/396.prim_prince_test.2323418121 Sep 09 10:58:48 AM UTC 24 Sep 09 11:00:10 AM UTC 24 3567563444 ps
T378 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/360.prim_prince_test.242748689 Sep 09 10:58:15 AM UTC 24 Sep 09 10:59:24 AM UTC 24 3161506100 ps
T379 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/352.prim_prince_test.3118271400 Sep 09 10:58:02 AM UTC 24 Sep 09 10:59:24 AM UTC 24 3618937540 ps
T380 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/364.prim_prince_test.1375586667 Sep 09 10:58:19 AM UTC 24 Sep 09 10:59:25 AM UTC 24 2906578159 ps
T381 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/354.prim_prince_test.2657127431 Sep 09 10:58:10 AM UTC 24 Sep 09 10:59:27 AM UTC 24 3385015272 ps
T382 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/374.prim_prince_test.1494429908 Sep 09 10:58:27 AM UTC 24 Sep 09 10:59:28 AM UTC 24 2679575792 ps
T383 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/389.prim_prince_test.2760062720 Sep 09 10:58:43 AM UTC 24 Sep 09 10:59:29 AM UTC 24 2033717160 ps
T384 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/392.prim_prince_test.2551397452 Sep 09 10:58:46 AM UTC 24 Sep 09 10:59:32 AM UTC 24 2007179541 ps
T385 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/390.prim_prince_test.209912776 Sep 09 10:58:45 AM UTC 24 Sep 09 10:59:34 AM UTC 24 2194988018 ps
T386 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/386.prim_prince_test.35430569 Sep 09 10:58:41 AM UTC 24 Sep 09 10:59:37 AM UTC 24 2517429195 ps
T387 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/384.prim_prince_test.3636769656 Sep 09 10:58:41 AM UTC 24 Sep 09 10:59:38 AM UTC 24 2579744273 ps
T388 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/382.prim_prince_test.2162244060 Sep 09 10:58:38 AM UTC 24 Sep 09 10:59:40 AM UTC 24 2835725714 ps
T389 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/373.prim_prince_test.3729565902 Sep 09 10:58:26 AM UTC 24 Sep 09 10:59:41 AM UTC 24 3404751786 ps
T390 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/402.prim_prince_test.704230259 Sep 09 10:58:58 AM UTC 24 Sep 09 10:59:42 AM UTC 24 1936733447 ps
T391 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/380.prim_prince_test.1712824974 Sep 09 10:58:34 AM UTC 24 Sep 09 10:59:43 AM UTC 24 3101437760 ps
T392 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/393.prim_prince_test.1841320848 Sep 09 10:58:47 AM UTC 24 Sep 09 10:59:43 AM UTC 24 2484700253 ps
T393 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/422.prim_prince_test.690876616 Sep 09 10:59:25 AM UTC 24 Sep 09 10:59:44 AM UTC 24 769850073 ps
T394 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/367.prim_prince_test.2185902208 Sep 09 10:58:23 AM UTC 24 Sep 09 10:59:44 AM UTC 24 3579785452 ps
T395 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/419.prim_prince_test.365141418 Sep 09 10:59:23 AM UTC 24 Sep 09 10:59:45 AM UTC 24 965226891 ps
T396 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/407.prim_prince_test.2090522728 Sep 09 10:59:08 AM UTC 24 Sep 09 10:59:45 AM UTC 24 1612859225 ps
T397 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/391.prim_prince_test.3726415981 Sep 09 10:58:45 AM UTC 24 Sep 09 10:59:45 AM UTC 24 2677857555 ps
T398 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/406.prim_prince_test.3060007679 Sep 09 10:59:03 AM UTC 24 Sep 09 10:59:46 AM UTC 24 1819577248 ps
T399 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/405.prim_prince_test.4219233447 Sep 09 10:59:03 AM UTC 24 Sep 09 10:59:46 AM UTC 24 1903374679 ps
T400 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/388.prim_prince_test.2758059197 Sep 09 10:58:43 AM UTC 24 Sep 09 10:59:48 AM UTC 24 2968260604 ps
T401 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/426.prim_prince_test.3797102155 Sep 09 10:59:29 AM UTC 24 Sep 09 10:59:48 AM UTC 24 842842402 ps
T402 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/415.prim_prince_test.2295772033 Sep 09 10:59:19 AM UTC 24 Sep 09 10:59:49 AM UTC 24 1272652548 ps
T403 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/379.prim_prince_test.3471546595 Sep 09 10:58:32 AM UTC 24 Sep 09 10:59:51 AM UTC 24 3435842114 ps
T404 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/381.prim_prince_test.823846584 Sep 09 10:58:37 AM UTC 24 Sep 09 10:59:53 AM UTC 24 3505007037 ps
T405 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/383.prim_prince_test.4252602145 Sep 09 10:58:40 AM UTC 24 Sep 09 10:59:54 AM UTC 24 3257809497 ps
T406 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/394.prim_prince_test.633162267 Sep 09 10:58:47 AM UTC 24 Sep 09 10:59:55 AM UTC 24 2994968948 ps
T407 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/408.prim_prince_test.827240201 Sep 09 10:59:11 AM UTC 24 Sep 09 10:59:57 AM UTC 24 1990040372 ps
T408 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/409.prim_prince_test.3419182304 Sep 09 10:59:13 AM UTC 24 Sep 09 10:59:58 AM UTC 24 1918762074 ps
T409 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/385.prim_prince_test.2421578673 Sep 09 10:58:41 AM UTC 24 Sep 09 10:59:59 AM UTC 24 3536214650 ps
T410 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/417.prim_prince_test.2644303931 Sep 09 10:59:21 AM UTC 24 Sep 09 11:00:00 AM UTC 24 1622117259 ps
T411 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/433.prim_prince_test.463503718 Sep 09 10:59:43 AM UTC 24 Sep 09 11:00:01 AM UTC 24 804272782 ps
T412 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/420.prim_prince_test.2450178717 Sep 09 10:59:25 AM UTC 24 Sep 09 11:00:02 AM UTC 24 1566196340 ps
T413 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/395.prim_prince_test.3487408802 Sep 09 10:58:47 AM UTC 24 Sep 09 11:00:02 AM UTC 24 3414077476 ps
T414 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/431.prim_prince_test.2844793057 Sep 09 10:59:39 AM UTC 24 Sep 09 11:00:03 AM UTC 24 1058592576 ps
T415 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/425.prim_prince_test.4183901933 Sep 09 10:59:29 AM UTC 24 Sep 09 11:00:04 AM UTC 24 1525588828 ps
T416 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/418.prim_prince_test.161184010 Sep 09 10:59:23 AM UTC 24 Sep 09 11:00:07 AM UTC 24 1982724055 ps
T417 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/421.prim_prince_test.3072027897 Sep 09 10:59:25 AM UTC 24 Sep 09 11:00:08 AM UTC 24 1902323705 ps
T418 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/430.prim_prince_test.643818370 Sep 09 10:59:37 AM UTC 24 Sep 09 11:00:09 AM UTC 24 1419431184 ps
T419 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/404.prim_prince_test.671793261 Sep 09 10:58:58 AM UTC 24 Sep 09 11:00:09 AM UTC 24 3233521532 ps
T420 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/437.prim_prince_test.947259597 Sep 09 10:59:45 AM UTC 24 Sep 09 11:00:11 AM UTC 24 1087393684 ps
T421 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/411.prim_prince_test.551261127 Sep 09 10:59:16 AM UTC 24 Sep 09 11:00:11 AM UTC 24 2462148985 ps
T422 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/412.prim_prince_test.2361158796 Sep 09 10:59:17 AM UTC 24 Sep 09 11:00:11 AM UTC 24 2370717216 ps
T423 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/399.prim_prince_test.2413728120 Sep 09 10:58:53 AM UTC 24 Sep 09 11:00:12 AM UTC 24 3598320814 ps
T424 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/441.prim_prince_test.2286308695 Sep 09 10:59:47 AM UTC 24 Sep 09 11:00:16 AM UTC 24 1245397909 ps
T425 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/398.prim_prince_test.1210176259 Sep 09 10:58:52 AM UTC 24 Sep 09 11:00:16 AM UTC 24 3686858732 ps
T426 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/442.prim_prince_test.2987637868 Sep 09 10:59:47 AM UTC 24 Sep 09 11:00:17 AM UTC 24 1325084093 ps
T427 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/424.prim_prince_test.432144669 Sep 09 10:59:26 AM UTC 24 Sep 09 11:00:18 AM UTC 24 2339850715 ps
T428 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/435.prim_prince_test.3496960081 Sep 09 10:59:44 AM UTC 24 Sep 09 11:00:19 AM UTC 24 1597212103 ps
T429 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/403.prim_prince_test.2180319123 Sep 09 10:58:58 AM UTC 24 Sep 09 11:00:20 AM UTC 24 3740747871 ps
T430 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/413.prim_prince_test.831167433 Sep 09 10:59:18 AM UTC 24 Sep 09 11:00:21 AM UTC 24 2912695499 ps
T431 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/427.prim_prince_test.3660240504 Sep 09 10:59:30 AM UTC 24 Sep 09 11:00:23 AM UTC 24 2363031199 ps
T432 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/456.prim_prince_test.701985509 Sep 09 11:00:02 AM UTC 24 Sep 09 11:00:24 AM UTC 24 781401889 ps
T433 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/447.prim_prince_test.2245784060 Sep 09 10:59:52 AM UTC 24 Sep 09 11:00:25 AM UTC 24 1425772121 ps
T434 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/436.prim_prince_test.4018113818 Sep 09 10:59:44 AM UTC 24 Sep 09 11:00:26 AM UTC 24 1882547327 ps
T435 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/428.prim_prince_test.3604194230 Sep 09 10:59:33 AM UTC 24 Sep 09 11:00:26 AM UTC 24 2315821152 ps
T436 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/410.prim_prince_test.740175806 Sep 09 10:59:14 AM UTC 24 Sep 09 11:00:27 AM UTC 24 3322715976 ps
T437 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/440.prim_prince_test.1491531064 Sep 09 10:59:47 AM UTC 24 Sep 09 11:00:27 AM UTC 24 1799165371 ps
T438 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/454.prim_prince_test.337878176 Sep 09 11:00:01 AM UTC 24 Sep 09 11:00:31 AM UTC 24 1143163823 ps
T439 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/448.prim_prince_test.1411141705 Sep 09 10:59:54 AM UTC 24 Sep 09 11:00:31 AM UTC 24 1604275787 ps
T440 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/452.prim_prince_test.1865110202 Sep 09 11:00:00 AM UTC 24 Sep 09 11:00:32 AM UTC 24 1421973517 ps
T441 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/432.prim_prince_test.1748269698 Sep 09 10:59:41 AM UTC 24 Sep 09 11:00:32 AM UTC 24 2273002861 ps
T442 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/423.prim_prince_test.1279676240 Sep 09 10:59:25 AM UTC 24 Sep 09 11:00:33 AM UTC 24 2986244464 ps
T443 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/460.prim_prince_test.1964227143 Sep 09 11:00:08 AM UTC 24 Sep 09 11:00:35 AM UTC 24 1179623430 ps
T444 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/444.prim_prince_test.1739313367 Sep 09 10:59:49 AM UTC 24 Sep 09 11:00:35 AM UTC 24 2033921697 ps
T445 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/465.prim_prince_test.1284803123 Sep 09 11:00:12 AM UTC 24 Sep 09 11:00:38 AM UTC 24 1082285017 ps
T446 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/458.prim_prince_test.2398591022 Sep 09 11:00:07 AM UTC 24 Sep 09 11:00:38 AM UTC 24 1351332188 ps
T447 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/466.prim_prince_test.658591708 Sep 09 11:00:12 AM UTC 24 Sep 09 11:00:38 AM UTC 24 1129460094 ps
T448 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/414.prim_prince_test.791828499 Sep 09 10:59:19 AM UTC 24 Sep 09 11:00:38 AM UTC 24 3591944330 ps
T449 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/474.prim_prince_test.1981324053 Sep 09 11:00:21 AM UTC 24 Sep 09 11:00:42 AM UTC 24 885853985 ps
T450 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/416.prim_prince_test.2219829492 Sep 09 10:59:20 AM UTC 24 Sep 09 11:00:42 AM UTC 24 3750903422 ps
T451 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/443.prim_prince_test.4063698325 Sep 09 10:59:47 AM UTC 24 Sep 09 11:00:45 AM UTC 24 2621554847 ps
T452 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/429.prim_prince_test.514264501 Sep 09 10:59:35 AM UTC 24 Sep 09 11:00:46 AM UTC 24 3222716866 ps
T453 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/464.prim_prince_test.3938982526 Sep 09 11:00:10 AM UTC 24 Sep 09 11:00:47 AM UTC 24 1589007541 ps
T454 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/482.prim_prince_test.1042312220 Sep 09 11:00:28 AM UTC 24 Sep 09 11:00:47 AM UTC 24 814466103 ps
T455 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/438.prim_prince_test.2052952562 Sep 09 10:59:45 AM UTC 24 Sep 09 11:00:48 AM UTC 24 2779764134 ps
T456 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/457.prim_prince_test.3012469982 Sep 09 11:00:02 AM UTC 24 Sep 09 11:00:48 AM UTC 24 1904829962 ps
T457 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/445.prim_prince_test.3397861527 Sep 09 10:59:50 AM UTC 24 Sep 09 11:00:50 AM UTC 24 2664364752 ps
T458 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/483.prim_prince_test.2169433006 Sep 09 11:00:32 AM UTC 24 Sep 09 11:00:50 AM UTC 24 761607303 ps
T459 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/467.prim_prince_test.1618270310 Sep 09 11:00:12 AM UTC 24 Sep 09 11:00:51 AM UTC 24 1693551188 ps
T460 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/475.prim_prince_test.739230091 Sep 09 11:00:22 AM UTC 24 Sep 09 11:00:51 AM UTC 24 1232143258 ps
T461 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/434.prim_prince_test.63624063 Sep 09 10:59:43 AM UTC 24 Sep 09 11:00:51 AM UTC 24 3047014394 ps
T462 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/446.prim_prince_test.3240881889 Sep 09 10:59:51 AM UTC 24 Sep 09 11:00:55 AM UTC 24 2759724538 ps
T463 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/450.prim_prince_test.1001150312 Sep 09 10:59:56 AM UTC 24 Sep 09 11:00:56 AM UTC 24 2691296631 ps
T464 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/473.prim_prince_test.2267601122 Sep 09 11:00:20 AM UTC 24 Sep 09 11:00:56 AM UTC 24 1592261770 ps
T465 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/461.prim_prince_test.1309493855 Sep 09 11:00:09 AM UTC 24 Sep 09 11:00:58 AM UTC 24 2075995087 ps
T466 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/470.prim_prince_test.3733320815 Sep 09 11:00:18 AM UTC 24 Sep 09 11:00:58 AM UTC 24 1827384555 ps
T467 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/480.prim_prince_test.724883287 Sep 09 11:00:27 AM UTC 24 Sep 09 11:00:59 AM UTC 24 1418619819 ps
T468 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/468.prim_prince_test.1207599932 Sep 09 11:00:13 AM UTC 24 Sep 09 11:00:59 AM UTC 24 2084098237 ps
T469 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/439.prim_prince_test.2954143550 Sep 09 10:59:46 AM UTC 24 Sep 09 11:01:01 AM UTC 24 3294246369 ps
T470 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/487.prim_prince_test.1253511248 Sep 09 11:00:34 AM UTC 24 Sep 09 11:01:02 AM UTC 24 1204960408 ps
T471 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/494.prim_prince_test.3659798570 Sep 09 11:00:43 AM UTC 24 Sep 09 11:01:03 AM UTC 24 826760974 ps
T472 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/479.prim_prince_test.3439793489 Sep 09 11:00:27 AM UTC 24 Sep 09 11:01:07 AM UTC 24 1835348846 ps
T473 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/478.prim_prince_test.1483606940 Sep 09 11:00:26 AM UTC 24 Sep 09 11:01:09 AM UTC 24 1935503994 ps
T474 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/451.prim_prince_test.3822437527 Sep 09 10:59:58 AM UTC 24 Sep 09 11:01:10 AM UTC 24 3256661423 ps
T475 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/449.prim_prince_test.468058042 Sep 09 10:59:54 AM UTC 24 Sep 09 11:01:10 AM UTC 24 3328049223 ps
T476 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/498.prim_prince_test.3607106909 Sep 09 11:00:48 AM UTC 24 Sep 09 11:01:11 AM UTC 24 966750004 ps
T477 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/496.prim_prince_test.3537995902 Sep 09 11:00:46 AM UTC 24 Sep 09 11:01:12 AM UTC 24 1086293068 ps
T478 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/489.prim_prince_test.2430412806 Sep 09 11:00:37 AM UTC 24 Sep 09 11:01:18 AM UTC 24 1790177183 ps
T479 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/459.prim_prince_test.2130958659 Sep 09 11:00:07 AM UTC 24 Sep 09 11:01:18 AM UTC 24 3216514731 ps
T480 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/471.prim_prince_test.2771861490 Sep 09 11:00:18 AM UTC 24 Sep 09 11:01:21 AM UTC 24 2710219258 ps
T481 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/476.prim_prince_test.846913011 Sep 09 11:00:23 AM UTC 24 Sep 09 11:01:23 AM UTC 24 2621712076 ps
T482 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/484.prim_prince_test.2092430609 Sep 09 11:00:33 AM UTC 24 Sep 09 11:01:25 AM UTC 24 2281908791 ps
T483 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/455.prim_prince_test.2594313128 Sep 09 11:00:02 AM UTC 24 Sep 09 11:01:25 AM UTC 24 3454705181 ps
T484 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/462.prim_prince_test.1807157465 Sep 09 11:00:09 AM UTC 24 Sep 09 11:01:26 AM UTC 24 3380965401 ps
T485 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/453.prim_prince_test.3028701915 Sep 09 11:00:01 AM UTC 24 Sep 09 11:01:27 AM UTC 24 3701851252 ps
T486 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/493.prim_prince_test.3788133412 Sep 09 11:00:39 AM UTC 24 Sep 09 11:01:27 AM UTC 24 2105515754 ps
T487 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/463.prim_prince_test.3058315136 Sep 09 11:00:10 AM UTC 24 Sep 09 11:01:29 AM UTC 24 3345989955 ps
T488 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/472.prim_prince_test.2149777713 Sep 09 11:00:20 AM UTC 24 Sep 09 11:01:30 AM UTC 24 3004579943 ps
T489 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/469.prim_prince_test.931655288 Sep 09 11:00:16 AM UTC 24 Sep 09 11:01:35 AM UTC 24 3461533644 ps
T490 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/491.prim_prince_test.915236189 Sep 09 11:00:39 AM UTC 24 Sep 09 11:01:35 AM UTC 24 2434159484 ps
T491 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/477.prim_prince_test.3716669704 Sep 09 11:00:25 AM UTC 24 Sep 09 11:01:36 AM UTC 24 3194121943 ps
T492 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/488.prim_prince_test.1085135471 Sep 09 11:00:35 AM UTC 24 Sep 09 11:01:37 AM UTC 24 2640521849 ps
T493 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/485.prim_prince_test.1984893668 Sep 09 11:00:33 AM UTC 24 Sep 09 11:01:48 AM UTC 24 3163341125 ps
T494 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/486.prim_prince_test.1473107473 Sep 09 11:00:33 AM UTC 24 Sep 09 11:01:50 AM UTC 24 3336350787 ps
T495 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/481.prim_prince_test.3098221857 Sep 09 11:00:28 AM UTC 24 Sep 09 11:01:53 AM UTC 24 3618206447 ps
T496 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/495.prim_prince_test.748576202 Sep 09 11:00:43 AM UTC 24 Sep 09 11:01:58 AM UTC 24 3094900271 ps
T497 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/497.prim_prince_test.4013942745 Sep 09 11:00:47 AM UTC 24 Sep 09 11:02:00 AM UTC 24 2994491938 ps
T498 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/490.prim_prince_test.4014313381 Sep 09 11:00:39 AM UTC 24 Sep 09 11:02:02 AM UTC 24 3383871391 ps
T499 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/492.prim_prince_test.2207922658 Sep 09 11:00:39 AM UTC 24 Sep 09 11:02:07 AM UTC 24 3511528918 ps
T500 /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/499.prim_prince_test.1045385426 Sep 09 11:00:48 AM UTC 24 Sep 09 11:02:22 AM UTC 24 3690288824 ps

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/0.prim_prince_test.1550267767
Short name T9
Test name
Test status
Simulation time 2181718150 ps
CPU time 41.38 seconds
Started Sep 09 10:50:16 AM UTC 24
Finished Sep 09 10:51:09 AM UTC 24
Peak memory 154632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1550267767 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 0.prim_prince_test.1550267767
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/0.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/1.prim_prince_test.3769882650
Short name T2
Test name
Test status
Simulation time 1290476158 ps
CPU time 24.42 seconds
Started Sep 09 10:50:16 AM UTC 24
Finished Sep 09 10:50:49 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3769882650 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 1.prim_prince_test.3769882650
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/1.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/10.prim_prince_test.4258471117
Short name T38
Test name
Test status
Simulation time 3732229020 ps
CPU time 70.9 seconds
Started Sep 09 10:50:20 AM UTC 24
Finished Sep 09 10:51:55 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4258471117 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 10.prim_prince_test.4258471117
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/10.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/100.prim_prince_test.4024822428
Short name T82
Test name
Test status
Simulation time 1172512237 ps
CPU time 21.34 seconds
Started Sep 09 10:52:30 AM UTC 24
Finished Sep 09 10:52:58 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4024822428 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 100.prim_prince_test.4024822428
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/100.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/101.prim_prince_test.3893052655
Short name T118
Test name
Test status
Simulation time 2876163424 ps
CPU time 53.75 seconds
Started Sep 09 10:52:34 AM UTC 24
Finished Sep 09 10:53:40 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3893052655 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 101.prim_prince_test.3893052655
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/101.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/102.prim_prince_test.1613448124
Short name T93
Test name
Test status
Simulation time 1306926288 ps
CPU time 24.51 seconds
Started Sep 09 10:52:36 AM UTC 24
Finished Sep 09 10:53:07 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1613448124 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 102.prim_prince_test.1613448124
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/102.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/103.prim_prince_test.61761078
Short name T113
Test name
Test status
Simulation time 2572651596 ps
CPU time 48.39 seconds
Started Sep 09 10:52:36 AM UTC 24
Finished Sep 09 10:53:36 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=61761078 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 103.prim_prince_test.61761078
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/103.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/104.prim_prince_test.524606727
Short name T104
Test name
Test status
Simulation time 2162596599 ps
CPU time 40.09 seconds
Started Sep 09 10:52:36 AM UTC 24
Finished Sep 09 10:53:26 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=524606727 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 104.prim_prince_test.524606727
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/104.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/105.prim_prince_test.668777352
Short name T101
Test name
Test status
Simulation time 1993068786 ps
CPU time 36.43 seconds
Started Sep 09 10:52:37 AM UTC 24
Finished Sep 09 10:53:23 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=668777352 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 105.prim_prince_test.668777352
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/105.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/106.prim_prince_test.3264331026
Short name T91
Test name
Test status
Simulation time 1006174439 ps
CPU time 19.18 seconds
Started Sep 09 10:52:41 AM UTC 24
Finished Sep 09 10:53:06 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3264331026 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 106.prim_prince_test.3264331026
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/106.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/107.prim_prince_test.1257188564
Short name T105
Test name
Test status
Simulation time 1882794898 ps
CPU time 36.13 seconds
Started Sep 09 10:52:42 AM UTC 24
Finished Sep 09 10:53:27 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1257188564 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 107.prim_prince_test.1257188564
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/107.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/108.prim_prince_test.3394554525
Short name T124
Test name
Test status
Simulation time 2827725764 ps
CPU time 53.87 seconds
Started Sep 09 10:52:42 AM UTC 24
Finished Sep 09 10:53:49 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3394554525 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 108.prim_prince_test.3394554525
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/108.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/109.prim_prince_test.2826249821
Short name T130
Test name
Test status
Simulation time 3493198597 ps
CPU time 64.82 seconds
Started Sep 09 10:52:42 AM UTC 24
Finished Sep 09 10:54:03 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2826249821 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 109.prim_prince_test.2826249821
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/109.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/11.prim_prince_test.2878957520
Short name T8
Test name
Test status
Simulation time 1779097121 ps
CPU time 33.86 seconds
Started Sep 09 10:50:20 AM UTC 24
Finished Sep 09 10:51:09 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2878957520 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 11.prim_prince_test.2878957520
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/11.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/110.prim_prince_test.1028074989
Short name T132
Test name
Test status
Simulation time 3520377110 ps
CPU time 66.12 seconds
Started Sep 09 10:52:43 AM UTC 24
Finished Sep 09 10:54:06 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1028074989 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 110.prim_prince_test.1028074989
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/110.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/111.prim_prince_test.293629745
Short name T114
Test name
Test status
Simulation time 2341276829 ps
CPU time 42.16 seconds
Started Sep 09 10:52:43 AM UTC 24
Finished Sep 09 10:53:37 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=293629745 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 111.prim_prince_test.293629745
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/111.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/112.prim_prince_test.1146914294
Short name T86
Test name
Test status
Simulation time 752596805 ps
CPU time 14.52 seconds
Started Sep 09 10:52:44 AM UTC 24
Finished Sep 09 10:53:03 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1146914294 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 112.prim_prince_test.1146914294
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/112.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/113.prim_prince_test.1216352286
Short name T136
Test name
Test status
Simulation time 3650707717 ps
CPU time 67.84 seconds
Started Sep 09 10:52:50 AM UTC 24
Finished Sep 09 10:54:15 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1216352286 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 113.prim_prince_test.1216352286
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/113.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/114.prim_prince_test.881513460
Short name T100
Test name
Test status
Simulation time 1202401167 ps
CPU time 23.29 seconds
Started Sep 09 10:52:52 AM UTC 24
Finished Sep 09 10:53:22 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=881513460 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 114.prim_prince_test.881513460
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/114.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/115.prim_prince_test.922947667
Short name T107
Test name
Test status
Simulation time 1506317846 ps
CPU time 28.51 seconds
Started Sep 09 10:52:54 AM UTC 24
Finished Sep 09 10:53:30 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=922947667 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 115.prim_prince_test.922947667
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/115.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/116.prim_prince_test.730661572
Short name T127
Test name
Test status
Simulation time 2824860774 ps
CPU time 52.3 seconds
Started Sep 09 10:52:55 AM UTC 24
Finished Sep 09 10:54:01 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=730661572 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 116.prim_prince_test.730661572
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/116.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/117.prim_prince_test.4259956892
Short name T99
Test name
Test status
Simulation time 928388815 ps
CPU time 17.87 seconds
Started Sep 09 10:52:57 AM UTC 24
Finished Sep 09 10:53:19 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4259956892 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 117.prim_prince_test.4259956892
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/117.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/118.prim_prince_test.3729531372
Short name T126
Test name
Test status
Simulation time 2369999447 ps
CPU time 42.89 seconds
Started Sep 09 10:52:59 AM UTC 24
Finished Sep 09 10:53:52 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3729531372 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 118.prim_prince_test.3729531372
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/118.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/119.prim_prince_test.1115690366
Short name T106
Test name
Test status
Simulation time 1150267824 ps
CPU time 22.42 seconds
Started Sep 09 10:53:00 AM UTC 24
Finished Sep 09 10:53:28 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1115690366 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 119.prim_prince_test.1115690366
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/119.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/12.prim_prince_test.1165102631
Short name T36
Test name
Test status
Simulation time 3599808102 ps
CPU time 69.23 seconds
Started Sep 09 10:50:20 AM UTC 24
Finished Sep 09 10:51:53 AM UTC 24
Peak memory 154648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1165102631 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 12.prim_prince_test.1165102631
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/12.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/120.prim_prince_test.2596726898
Short name T119
Test name
Test status
Simulation time 1591752786 ps
CPU time 30.01 seconds
Started Sep 09 10:53:03 AM UTC 24
Finished Sep 09 10:53:41 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2596726898 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 120.prim_prince_test.2596726898
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/120.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/121.prim_prince_test.1689029524
Short name T150
Test name
Test status
Simulation time 3708849033 ps
CPU time 67.19 seconds
Started Sep 09 10:53:04 AM UTC 24
Finished Sep 09 10:54:28 AM UTC 24
Peak memory 154404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1689029524 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 121.prim_prince_test.1689029524
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/121.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/122.prim_prince_test.2107297748
Short name T115
Test name
Test status
Simulation time 1476937470 ps
CPU time 27.4 seconds
Started Sep 09 10:53:04 AM UTC 24
Finished Sep 09 10:53:38 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2107297748 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 122.prim_prince_test.2107297748
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/122.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/123.prim_prince_test.809642020
Short name T117
Test name
Test status
Simulation time 1411227038 ps
CPU time 27.01 seconds
Started Sep 09 10:53:05 AM UTC 24
Finished Sep 09 10:53:39 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=809642020 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 123.prim_prince_test.809642020
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/123.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/124.prim_prince_test.2083699288
Short name T135
Test name
Test status
Simulation time 2936777429 ps
CPU time 54.04 seconds
Started Sep 09 10:53:05 AM UTC 24
Finished Sep 09 10:54:13 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2083699288 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 124.prim_prince_test.2083699288
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/124.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/125.prim_prince_test.2972019700
Short name T144
Test name
Test status
Simulation time 3284714530 ps
CPU time 59.78 seconds
Started Sep 09 10:53:06 AM UTC 24
Finished Sep 09 10:54:21 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2972019700 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 125.prim_prince_test.2972019700
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/125.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/126.prim_prince_test.2851146072
Short name T151
Test name
Test status
Simulation time 3582693029 ps
CPU time 65.7 seconds
Started Sep 09 10:53:06 AM UTC 24
Finished Sep 09 10:54:28 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2851146072 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 126.prim_prince_test.2851146072
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/126.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/127.prim_prince_test.723890264
Short name T116
Test name
Test status
Simulation time 1318184486 ps
CPU time 24.89 seconds
Started Sep 09 10:53:07 AM UTC 24
Finished Sep 09 10:53:39 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=723890264 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 127.prim_prince_test.723890264
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/127.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/128.prim_prince_test.769741287
Short name T125
Test name
Test status
Simulation time 1877160954 ps
CPU time 34.46 seconds
Started Sep 09 10:53:07 AM UTC 24
Finished Sep 09 10:53:51 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=769741287 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 128.prim_prince_test.769741287
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/128.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/129.prim_prince_test.3402793148
Short name T153
Test name
Test status
Simulation time 3741525206 ps
CPU time 67.63 seconds
Started Sep 09 10:53:07 AM UTC 24
Finished Sep 09 10:54:32 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3402793148 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 129.prim_prince_test.3402793148
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/129.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/13.prim_prince_test.2794969664
Short name T14
Test name
Test status
Simulation time 2018753189 ps
CPU time 39.6 seconds
Started Sep 09 10:50:20 AM UTC 24
Finished Sep 09 10:51:16 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2794969664 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 13.prim_prince_test.2794969664
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/13.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/130.prim_prince_test.1664830740
Short name T128
Test name
Test status
Simulation time 2248456539 ps
CPU time 41.75 seconds
Started Sep 09 10:53:09 AM UTC 24
Finished Sep 09 10:54:02 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1664830740 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 130.prim_prince_test.1664830740
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/130.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/131.prim_prince_test.3531169175
Short name T120
Test name
Test status
Simulation time 1251813910 ps
CPU time 23.57 seconds
Started Sep 09 10:53:11 AM UTC 24
Finished Sep 09 10:53:41 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3531169175 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 131.prim_prince_test.3531169175
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/131.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/132.prim_prince_test.2688090299
Short name T147
Test name
Test status
Simulation time 2928250293 ps
CPU time 53.18 seconds
Started Sep 09 10:53:18 AM UTC 24
Finished Sep 09 10:54:24 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2688090299 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 132.prim_prince_test.2688090299
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/132.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/133.prim_prince_test.1921476670
Short name T112
Test name
Test status
Simulation time 777332255 ps
CPU time 14.27 seconds
Started Sep 09 10:53:18 AM UTC 24
Finished Sep 09 10:53:36 AM UTC 24
Peak memory 154344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1921476670 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 133.prim_prince_test.1921476670
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/133.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/134.prim_prince_test.3258744514
Short name T131
Test name
Test status
Simulation time 1998038915 ps
CPU time 37.05 seconds
Started Sep 09 10:53:19 AM UTC 24
Finished Sep 09 10:54:05 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3258744514 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 134.prim_prince_test.3258744514
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/134.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/135.prim_prince_test.4035691429
Short name T121
Test name
Test status
Simulation time 1081988342 ps
CPU time 20.07 seconds
Started Sep 09 10:53:20 AM UTC 24
Finished Sep 09 10:53:45 AM UTC 24
Peak memory 154348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4035691429 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 135.prim_prince_test.4035691429
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/135.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/136.prim_prince_test.1928732524
Short name T143
Test name
Test status
Simulation time 2500045817 ps
CPU time 45.64 seconds
Started Sep 09 10:53:23 AM UTC 24
Finished Sep 09 10:54:20 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1928732524 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 136.prim_prince_test.1928732524
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/136.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/137.prim_prince_test.437093077
Short name T165
Test name
Test status
Simulation time 3737767980 ps
CPU time 69.76 seconds
Started Sep 09 10:53:24 AM UTC 24
Finished Sep 09 10:54:50 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=437093077 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 137.prim_prince_test.437093077
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/137.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/138.prim_prince_test.15312706
Short name T141
Test name
Test status
Simulation time 2299440055 ps
CPU time 43.29 seconds
Started Sep 09 10:53:25 AM UTC 24
Finished Sep 09 10:54:19 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15312706 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 138.prim_prince_test.15312706
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/138.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/139.prim_prince_test.849554044
Short name T146
Test name
Test status
Simulation time 2507344135 ps
CPU time 46.18 seconds
Started Sep 09 10:53:26 AM UTC 24
Finished Sep 09 10:54:24 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=849554044 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 139.prim_prince_test.849554044
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/139.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/14.prim_prince_test.907200267
Short name T24
Test name
Test status
Simulation time 3156551953 ps
CPU time 58.84 seconds
Started Sep 09 10:50:21 AM UTC 24
Finished Sep 09 10:51:35 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=907200267 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 14.prim_prince_test.907200267
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/14.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/140.prim_prince_test.2183919420
Short name T154
Test name
Test status
Simulation time 2950510766 ps
CPU time 54.45 seconds
Started Sep 09 10:53:27 AM UTC 24
Finished Sep 09 10:54:35 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2183919420 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 140.prim_prince_test.2183919420
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/140.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/141.prim_prince_test.3253817144
Short name T123
Test name
Test status
Simulation time 817242106 ps
CPU time 16.19 seconds
Started Sep 09 10:53:27 AM UTC 24
Finished Sep 09 10:53:48 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3253817144 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 141.prim_prince_test.3253817144
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/141.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/142.prim_prince_test.4126061222
Short name T122
Test name
Test status
Simulation time 786672544 ps
CPU time 14.98 seconds
Started Sep 09 10:53:28 AM UTC 24
Finished Sep 09 10:53:47 AM UTC 24
Peak memory 154348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4126061222 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 142.prim_prince_test.4126061222
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/142.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/143.prim_prince_test.1777246830
Short name T156
Test name
Test status
Simulation time 2983979744 ps
CPU time 55.34 seconds
Started Sep 09 10:53:29 AM UTC 24
Finished Sep 09 10:54:38 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1777246830 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 143.prim_prince_test.1777246830
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/143.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/144.prim_prince_test.2715881241
Short name T157
Test name
Test status
Simulation time 2895032326 ps
CPU time 53.53 seconds
Started Sep 09 10:53:31 AM UTC 24
Finished Sep 09 10:54:38 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2715881241 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 144.prim_prince_test.2715881241
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/144.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/145.prim_prince_test.543435666
Short name T134
Test name
Test status
Simulation time 1724975770 ps
CPU time 31.84 seconds
Started Sep 09 10:53:32 AM UTC 24
Finished Sep 09 10:54:11 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=543435666 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 145.prim_prince_test.543435666
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/145.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/146.prim_prince_test.2468783108
Short name T161
Test name
Test status
Simulation time 3068325541 ps
CPU time 56.36 seconds
Started Sep 09 10:53:35 AM UTC 24
Finished Sep 09 10:54:45 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2468783108 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 146.prim_prince_test.2468783108
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/146.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/147.prim_prince_test.3298246759
Short name T137
Test name
Test status
Simulation time 1782502256 ps
CPU time 32.99 seconds
Started Sep 09 10:53:35 AM UTC 24
Finished Sep 09 10:54:16 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3298246759 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 147.prim_prince_test.3298246759
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/147.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/148.prim_prince_test.2821559829
Short name T152
Test name
Test status
Simulation time 2357286246 ps
CPU time 43.6 seconds
Started Sep 09 10:53:37 AM UTC 24
Finished Sep 09 10:54:31 AM UTC 24
Peak memory 154412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2821559829 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 148.prim_prince_test.2821559829
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/148.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/149.prim_prince_test.2502505683
Short name T142
Test name
Test status
Simulation time 1835872860 ps
CPU time 33.83 seconds
Started Sep 09 10:53:37 AM UTC 24
Finished Sep 09 10:54:19 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2502505683 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 149.prim_prince_test.2502505683
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/149.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/15.prim_prince_test.2992800528
Short name T11
Test name
Test status
Simulation time 2167996235 ps
CPU time 41.51 seconds
Started Sep 09 10:50:21 AM UTC 24
Finished Sep 09 10:51:14 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2992800528 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 15.prim_prince_test.2992800528
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/15.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/150.prim_prince_test.521759884
Short name T140
Test name
Test status
Simulation time 1797240800 ps
CPU time 32.62 seconds
Started Sep 09 10:53:37 AM UTC 24
Finished Sep 09 10:54:18 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=521759884 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 150.prim_prince_test.521759884
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/150.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/151.prim_prince_test.366765435
Short name T133
Test name
Test status
Simulation time 1208953730 ps
CPU time 22.26 seconds
Started Sep 09 10:53:38 AM UTC 24
Finished Sep 09 10:54:06 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=366765435 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 151.prim_prince_test.366765435
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/151.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/152.prim_prince_test.2962340000
Short name T139
Test name
Test status
Simulation time 1654361052 ps
CPU time 30.44 seconds
Started Sep 09 10:53:39 AM UTC 24
Finished Sep 09 10:54:18 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2962340000 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 152.prim_prince_test.2962340000
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/152.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/153.prim_prince_test.409527071
Short name T149
Test name
Test status
Simulation time 1952340363 ps
CPU time 36.49 seconds
Started Sep 09 10:53:40 AM UTC 24
Finished Sep 09 10:54:26 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=409527071 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 153.prim_prince_test.409527071
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/153.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/154.prim_prince_test.1742991759
Short name T158
Test name
Test status
Simulation time 2526207661 ps
CPU time 47.15 seconds
Started Sep 09 10:53:40 AM UTC 24
Finished Sep 09 10:54:39 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1742991759 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 154.prim_prince_test.1742991759
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/154.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/155.prim_prince_test.831437732
Short name T129
Test name
Test status
Simulation time 887648003 ps
CPU time 16.31 seconds
Started Sep 09 10:53:41 AM UTC 24
Finished Sep 09 10:54:02 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=831437732 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 155.prim_prince_test.831437732
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/155.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/156.prim_prince_test.738103369
Short name T173
Test name
Test status
Simulation time 3585758823 ps
CPU time 66.63 seconds
Started Sep 09 10:53:41 AM UTC 24
Finished Sep 09 10:55:04 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=738103369 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 156.prim_prince_test.738103369
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/156.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/157.prim_prince_test.1927169465
Short name T138
Test name
Test status
Simulation time 1473960146 ps
CPU time 27.93 seconds
Started Sep 09 10:53:41 AM UTC 24
Finished Sep 09 10:54:17 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1927169465 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 157.prim_prince_test.1927169465
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/157.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/158.prim_prince_test.3530713105
Short name T145
Test name
Test status
Simulation time 1503202872 ps
CPU time 28.64 seconds
Started Sep 09 10:53:46 AM UTC 24
Finished Sep 09 10:54:22 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3530713105 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 158.prim_prince_test.3530713105
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/158.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/159.prim_prince_test.173419166
Short name T148
Test name
Test status
Simulation time 1513170291 ps
CPU time 28.67 seconds
Started Sep 09 10:53:49 AM UTC 24
Finished Sep 09 10:54:25 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=173419166 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 159.prim_prince_test.173419166
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/159.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/16.prim_prince_test.3210301839
Short name T18
Test name
Test status
Simulation time 2566818786 ps
CPU time 47.95 seconds
Started Sep 09 10:50:21 AM UTC 24
Finished Sep 09 10:51:22 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3210301839 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 16.prim_prince_test.3210301839
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/16.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/160.prim_prince_test.2739863958
Short name T175
Test name
Test status
Simulation time 3271593290 ps
CPU time 62.08 seconds
Started Sep 09 10:53:49 AM UTC 24
Finished Sep 09 10:55:06 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2739863958 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 160.prim_prince_test.2739863958
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/160.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/161.prim_prince_test.2875173259
Short name T176
Test name
Test status
Simulation time 3411879427 ps
CPU time 61.22 seconds
Started Sep 09 10:53:50 AM UTC 24
Finished Sep 09 10:55:06 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2875173259 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 161.prim_prince_test.2875173259
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/161.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/162.prim_prince_test.1322141129
Short name T184
Test name
Test status
Simulation time 3742783913 ps
CPU time 69.05 seconds
Started Sep 09 10:53:52 AM UTC 24
Finished Sep 09 10:55:18 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1322141129 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 162.prim_prince_test.1322141129
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/162.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/163.prim_prince_test.3141082118
Short name T159
Test name
Test status
Simulation time 2079667091 ps
CPU time 39.13 seconds
Started Sep 09 10:53:53 AM UTC 24
Finished Sep 09 10:54:42 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3141082118 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 163.prim_prince_test.3141082118
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/163.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/164.prim_prince_test.839204416
Short name T185
Test name
Test status
Simulation time 3478150168 ps
CPU time 64.46 seconds
Started Sep 09 10:54:02 AM UTC 24
Finished Sep 09 10:55:22 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=839204416 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 164.prim_prince_test.839204416
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/164.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/165.prim_prince_test.2728722999
Short name T171
Test name
Test status
Simulation time 2434225032 ps
CPU time 44.32 seconds
Started Sep 09 10:54:02 AM UTC 24
Finished Sep 09 10:54:58 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2728722999 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 165.prim_prince_test.2728722999
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/165.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/166.prim_prince_test.3269230715
Short name T166
Test name
Test status
Simulation time 2037498718 ps
CPU time 37.7 seconds
Started Sep 09 10:54:03 AM UTC 24
Finished Sep 09 10:54:51 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3269230715 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 166.prim_prince_test.3269230715
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/166.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/167.prim_prince_test.1914238200
Short name T163
Test name
Test status
Simulation time 1880052514 ps
CPU time 36.09 seconds
Started Sep 09 10:54:03 AM UTC 24
Finished Sep 09 10:54:49 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1914238200 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 167.prim_prince_test.1914238200
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/167.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/168.prim_prince_test.2516937247
Short name T168
Test name
Test status
Simulation time 1979906392 ps
CPU time 37.85 seconds
Started Sep 09 10:54:05 AM UTC 24
Finished Sep 09 10:54:53 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2516937247 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 168.prim_prince_test.2516937247
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/168.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/169.prim_prince_test.2138538216
Short name T155
Test name
Test status
Simulation time 1228603254 ps
CPU time 23.72 seconds
Started Sep 09 10:54:06 AM UTC 24
Finished Sep 09 10:54:36 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2138538216 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 169.prim_prince_test.2138538216
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/169.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/17.prim_prince_test.3948080209
Short name T25
Test name
Test status
Simulation time 3140171843 ps
CPU time 60.65 seconds
Started Sep 09 10:50:21 AM UTC 24
Finished Sep 09 10:51:38 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3948080209 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 17.prim_prince_test.3948080209
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/17.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/170.prim_prince_test.126502584
Short name T183
Test name
Test status
Simulation time 2998913824 ps
CPU time 54.77 seconds
Started Sep 09 10:54:07 AM UTC 24
Finished Sep 09 10:55:16 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=126502584 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 170.prim_prince_test.126502584
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/170.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/171.prim_prince_test.1911700605
Short name T179
Test name
Test status
Simulation time 2523723491 ps
CPU time 45.98 seconds
Started Sep 09 10:54:13 AM UTC 24
Finished Sep 09 10:55:10 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1911700605 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 171.prim_prince_test.1911700605
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/171.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/172.prim_prince_test.3908027933
Short name T172
Test name
Test status
Simulation time 2071592785 ps
CPU time 39.04 seconds
Started Sep 09 10:54:14 AM UTC 24
Finished Sep 09 10:55:02 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3908027933 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 172.prim_prince_test.3908027933
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/172.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/173.prim_prince_test.1595707282
Short name T169
Test name
Test status
Simulation time 1588722971 ps
CPU time 29.33 seconds
Started Sep 09 10:54:16 AM UTC 24
Finished Sep 09 10:54:53 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1595707282 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 173.prim_prince_test.1595707282
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/173.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/174.prim_prince_test.819276412
Short name T160
Test name
Test status
Simulation time 1171220762 ps
CPU time 21.8 seconds
Started Sep 09 10:54:17 AM UTC 24
Finished Sep 09 10:54:45 AM UTC 24
Peak memory 154136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=819276412 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 174.prim_prince_test.819276412
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/174.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/175.prim_prince_test.2661548409
Short name T187
Test name
Test status
Simulation time 2926887324 ps
CPU time 54.88 seconds
Started Sep 09 10:54:17 AM UTC 24
Finished Sep 09 10:55:25 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2661548409 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 175.prim_prince_test.2661548409
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/175.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/176.prim_prince_test.3008268802
Short name T177
Test name
Test status
Simulation time 2158568221 ps
CPU time 39.3 seconds
Started Sep 09 10:54:18 AM UTC 24
Finished Sep 09 10:55:07 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3008268802 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 176.prim_prince_test.3008268802
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/176.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/177.prim_prince_test.643648500
Short name T174
Test name
Test status
Simulation time 1962851427 ps
CPU time 36.31 seconds
Started Sep 09 10:54:19 AM UTC 24
Finished Sep 09 10:55:05 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=643648500 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 177.prim_prince_test.643648500
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/177.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/178.prim_prince_test.36290333
Short name T180
Test name
Test status
Simulation time 2173160294 ps
CPU time 40.41 seconds
Started Sep 09 10:54:20 AM UTC 24
Finished Sep 09 10:55:11 AM UTC 24
Peak memory 156180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=36290333 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 178.prim_prince_test.36290333
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/178.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/179.prim_prince_test.3517071281
Short name T197
Test name
Test status
Simulation time 3374114616 ps
CPU time 61.93 seconds
Started Sep 09 10:54:20 AM UTC 24
Finished Sep 09 10:55:38 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3517071281 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 179.prim_prince_test.3517071281
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/179.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/18.prim_prince_test.2074514473
Short name T3
Test name
Test status
Simulation time 1235307747 ps
CPU time 23.7 seconds
Started Sep 09 10:50:21 AM UTC 24
Finished Sep 09 10:50:52 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2074514473 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 18.prim_prince_test.2074514473
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/18.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/180.prim_prince_test.1538549259
Short name T193
Test name
Test status
Simulation time 3138745840 ps
CPU time 59.04 seconds
Started Sep 09 10:54:20 AM UTC 24
Finished Sep 09 10:55:34 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1538549259 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 180.prim_prince_test.1538549259
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/180.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/181.prim_prince_test.1662043372
Short name T164
Test name
Test status
Simulation time 1221316071 ps
CPU time 22.34 seconds
Started Sep 09 10:54:21 AM UTC 24
Finished Sep 09 10:54:50 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1662043372 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 181.prim_prince_test.1662043372
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/181.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/182.prim_prince_test.2286883409
Short name T195
Test name
Test status
Simulation time 3227021251 ps
CPU time 58.42 seconds
Started Sep 09 10:54:22 AM UTC 24
Finished Sep 09 10:55:36 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2286883409 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 182.prim_prince_test.2286883409
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/182.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/183.prim_prince_test.1374386212
Short name T191
Test name
Test status
Simulation time 2988446822 ps
CPU time 54.27 seconds
Started Sep 09 10:54:25 AM UTC 24
Finished Sep 09 10:55:32 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1374386212 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 183.prim_prince_test.1374386212
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/183.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/184.prim_prince_test.1387164558
Short name T188
Test name
Test status
Simulation time 2722761724 ps
CPU time 50.2 seconds
Started Sep 09 10:54:25 AM UTC 24
Finished Sep 09 10:55:27 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1387164558 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 184.prim_prince_test.1387164558
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/184.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/185.prim_prince_test.2447565373
Short name T162
Test name
Test status
Simulation time 941925105 ps
CPU time 17.95 seconds
Started Sep 09 10:54:26 AM UTC 24
Finished Sep 09 10:54:48 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2447565373 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 185.prim_prince_test.2447565373
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/185.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/186.prim_prince_test.1765773486
Short name T167
Test name
Test status
Simulation time 997452991 ps
CPU time 18.65 seconds
Started Sep 09 10:54:27 AM UTC 24
Finished Sep 09 10:54:51 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1765773486 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 186.prim_prince_test.1765773486
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/186.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/187.prim_prince_test.1991213255
Short name T181
Test name
Test status
Simulation time 1872114244 ps
CPU time 35.22 seconds
Started Sep 09 10:54:28 AM UTC 24
Finished Sep 09 10:55:12 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1991213255 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 187.prim_prince_test.1991213255
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/187.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/188.prim_prince_test.2863409494
Short name T170
Test name
Test status
Simulation time 1011089182 ps
CPU time 18.91 seconds
Started Sep 09 10:54:29 AM UTC 24
Finished Sep 09 10:54:53 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2863409494 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 188.prim_prince_test.2863409494
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/188.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/189.prim_prince_test.595042420
Short name T196
Test name
Test status
Simulation time 2837121931 ps
CPU time 51.59 seconds
Started Sep 09 10:54:32 AM UTC 24
Finished Sep 09 10:55:37 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=595042420 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 189.prim_prince_test.595042420
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/189.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/19.prim_prince_test.984630420
Short name T34
Test name
Test status
Simulation time 3631032651 ps
CPU time 68.35 seconds
Started Sep 09 10:50:21 AM UTC 24
Finished Sep 09 10:51:47 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=984630420 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 19.prim_prince_test.984630420
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/19.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/190.prim_prince_test.2163854206
Short name T190
Test name
Test status
Simulation time 2480047423 ps
CPU time 46.07 seconds
Started Sep 09 10:54:33 AM UTC 24
Finished Sep 09 10:55:31 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2163854206 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 190.prim_prince_test.2163854206
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/190.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/191.prim_prince_test.2454477897
Short name T182
Test name
Test status
Simulation time 1637789529 ps
CPU time 30.75 seconds
Started Sep 09 10:54:36 AM UTC 24
Finished Sep 09 10:55:15 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2454477897 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 191.prim_prince_test.2454477897
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/191.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/192.prim_prince_test.947651542
Short name T213
Test name
Test status
Simulation time 3698916941 ps
CPU time 68.59 seconds
Started Sep 09 10:54:37 AM UTC 24
Finished Sep 09 10:56:03 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=947651542 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 192.prim_prince_test.947651542
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/192.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/193.prim_prince_test.431172204
Short name T189
Test name
Test status
Simulation time 2230034659 ps
CPU time 41.18 seconds
Started Sep 09 10:54:38 AM UTC 24
Finished Sep 09 10:55:30 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=431172204 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 193.prim_prince_test.431172204
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/193.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/194.prim_prince_test.505409076
Short name T178
Test name
Test status
Simulation time 1257563890 ps
CPU time 23.36 seconds
Started Sep 09 10:54:40 AM UTC 24
Finished Sep 09 10:55:09 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=505409076 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 194.prim_prince_test.505409076
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/194.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/195.prim_prince_test.1077256200
Short name T204
Test name
Test status
Simulation time 3031608566 ps
CPU time 55.87 seconds
Started Sep 09 10:54:40 AM UTC 24
Finished Sep 09 10:55:49 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1077256200 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 195.prim_prince_test.1077256200
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/195.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/196.prim_prince_test.2662839175
Short name T209
Test name
Test status
Simulation time 3158739090 ps
CPU time 58.36 seconds
Started Sep 09 10:54:43 AM UTC 24
Finished Sep 09 10:55:55 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2662839175 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 196.prim_prince_test.2662839175
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/196.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/197.prim_prince_test.294002564
Short name T211
Test name
Test status
Simulation time 3167196438 ps
CPU time 57.28 seconds
Started Sep 09 10:54:46 AM UTC 24
Finished Sep 09 10:55:58 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=294002564 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 197.prim_prince_test.294002564
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/197.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/198.prim_prince_test.1352939330
Short name T217
Test name
Test status
Simulation time 3536153263 ps
CPU time 64.39 seconds
Started Sep 09 10:54:46 AM UTC 24
Finished Sep 09 10:56:06 AM UTC 24
Peak memory 154652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1352939330 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 198.prim_prince_test.1352939330
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/198.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/199.prim_prince_test.2742191549
Short name T218
Test name
Test status
Simulation time 3395756571 ps
CPU time 62.16 seconds
Started Sep 09 10:54:49 AM UTC 24
Finished Sep 09 10:56:06 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2742191549 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 199.prim_prince_test.2742191549
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/199.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/2.prim_prince_test.411903773
Short name T15
Test name
Test status
Simulation time 2544489474 ps
CPU time 48.11 seconds
Started Sep 09 10:50:16 AM UTC 24
Finished Sep 09 10:51:18 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=411903773 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 2.prim_prince_test.411903773
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/2.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/20.prim_prince_test.4141350043
Short name T22
Test name
Test status
Simulation time 2859674656 ps
CPU time 54.48 seconds
Started Sep 09 10:50:21 AM UTC 24
Finished Sep 09 10:51:30 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4141350043 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 20.prim_prince_test.4141350043
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/20.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/200.prim_prince_test.2930392961
Short name T192
Test name
Test status
Simulation time 1858040142 ps
CPU time 34.41 seconds
Started Sep 09 10:54:49 AM UTC 24
Finished Sep 09 10:55:33 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2930392961 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 200.prim_prince_test.2930392961
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/200.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/201.prim_prince_test.443826893
Short name T216
Test name
Test status
Simulation time 3153815595 ps
CPU time 58.54 seconds
Started Sep 09 10:54:50 AM UTC 24
Finished Sep 09 10:56:03 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=443826893 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 201.prim_prince_test.443826893
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/201.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/202.prim_prince_test.109599217
Short name T207
Test name
Test status
Simulation time 2728542043 ps
CPU time 50.27 seconds
Started Sep 09 10:54:51 AM UTC 24
Finished Sep 09 10:55:55 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=109599217 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 202.prim_prince_test.109599217
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/202.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/203.prim_prince_test.3682439434
Short name T203
Test name
Test status
Simulation time 2519351063 ps
CPU time 45.78 seconds
Started Sep 09 10:54:51 AM UTC 24
Finished Sep 09 10:55:49 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3682439434 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 203.prim_prince_test.3682439434
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/203.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/204.prim_prince_test.1912247012
Short name T202
Test name
Test status
Simulation time 2417001245 ps
CPU time 44.99 seconds
Started Sep 09 10:54:51 AM UTC 24
Finished Sep 09 10:55:48 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1912247012 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 204.prim_prince_test.1912247012
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/204.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/205.prim_prince_test.359075776
Short name T214
Test name
Test status
Simulation time 3002399237 ps
CPU time 55.28 seconds
Started Sep 09 10:54:54 AM UTC 24
Finished Sep 09 10:56:03 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=359075776 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 205.prim_prince_test.359075776
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/205.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/206.prim_prince_test.1589418509
Short name T210
Test name
Test status
Simulation time 2761195011 ps
CPU time 50.63 seconds
Started Sep 09 10:54:54 AM UTC 24
Finished Sep 09 10:55:57 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1589418509 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 206.prim_prince_test.1589418509
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/206.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/207.prim_prince_test.3608167204
Short name T223
Test name
Test status
Simulation time 3482170696 ps
CPU time 63.35 seconds
Started Sep 09 10:54:54 AM UTC 24
Finished Sep 09 10:56:13 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3608167204 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 207.prim_prince_test.3608167204
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/207.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/208.prim_prince_test.1303561416
Short name T186
Test name
Test status
Simulation time 1055385166 ps
CPU time 20.02 seconds
Started Sep 09 10:54:59 AM UTC 24
Finished Sep 09 10:55:24 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1303561416 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 208.prim_prince_test.1303561416
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/208.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/209.prim_prince_test.1237117343
Short name T201
Test name
Test status
Simulation time 1744185579 ps
CPU time 31.99 seconds
Started Sep 09 10:55:03 AM UTC 24
Finished Sep 09 10:55:44 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1237117343 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 209.prim_prince_test.1237117343
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/209.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/21.prim_prince_test.781234993
Short name T12
Test name
Test status
Simulation time 2263188402 ps
CPU time 42.07 seconds
Started Sep 09 10:50:21 AM UTC 24
Finished Sep 09 10:51:15 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=781234993 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 21.prim_prince_test.781234993
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/21.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/210.prim_prince_test.1634287620
Short name T238
Test name
Test status
Simulation time 3693998148 ps
CPU time 68.82 seconds
Started Sep 09 10:55:05 AM UTC 24
Finished Sep 09 10:56:31 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1634287620 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 210.prim_prince_test.1634287620
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/210.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/211.prim_prince_test.3194687611
Short name T198
Test name
Test status
Simulation time 1484222898 ps
CPU time 27.59 seconds
Started Sep 09 10:55:05 AM UTC 24
Finished Sep 09 10:55:40 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3194687611 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 211.prim_prince_test.3194687611
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/211.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/212.prim_prince_test.510218228
Short name T194
Test name
Test status
Simulation time 1173914212 ps
CPU time 21.75 seconds
Started Sep 09 10:55:06 AM UTC 24
Finished Sep 09 10:55:34 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=510218228 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 212.prim_prince_test.510218228
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/212.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/213.prim_prince_test.3326332975
Short name T199
Test name
Test status
Simulation time 1495738868 ps
CPU time 27.34 seconds
Started Sep 09 10:55:07 AM UTC 24
Finished Sep 09 10:55:42 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3326332975 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 213.prim_prince_test.3326332975
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/213.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/214.prim_prince_test.441658749
Short name T208
Test name
Test status
Simulation time 1996970444 ps
CPU time 37.04 seconds
Started Sep 09 10:55:08 AM UTC 24
Finished Sep 09 10:55:55 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=441658749 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 214.prim_prince_test.441658749
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/214.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/215.prim_prince_test.3615293405
Short name T205
Test name
Test status
Simulation time 1726418709 ps
CPU time 31.79 seconds
Started Sep 09 10:55:09 AM UTC 24
Finished Sep 09 10:55:50 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3615293405 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 215.prim_prince_test.3615293405
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/215.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/216.prim_prince_test.3165123775
Short name T206
Test name
Test status
Simulation time 1669483849 ps
CPU time 30.81 seconds
Started Sep 09 10:55:11 AM UTC 24
Finished Sep 09 10:55:50 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3165123775 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 216.prim_prince_test.3165123775
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/216.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/217.prim_prince_test.1884929638
Short name T241
Test name
Test status
Simulation time 3500167143 ps
CPU time 65.01 seconds
Started Sep 09 10:55:12 AM UTC 24
Finished Sep 09 10:56:33 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1884929638 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 217.prim_prince_test.1884929638
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/217.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/218.prim_prince_test.74888856
Short name T229
Test name
Test status
Simulation time 3072625747 ps
CPU time 57.45 seconds
Started Sep 09 10:55:13 AM UTC 24
Finished Sep 09 10:56:24 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=74888856 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 218.prim_prince_test.74888856
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/218.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/219.prim_prince_test.1153267806
Short name T220
Test name
Test status
Simulation time 2271973089 ps
CPU time 42.11 seconds
Started Sep 09 10:55:16 AM UTC 24
Finished Sep 09 10:56:08 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1153267806 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 219.prim_prince_test.1153267806
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/219.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/22.prim_prince_test.3373139738
Short name T39
Test name
Test status
Simulation time 3711420568 ps
CPU time 69.47 seconds
Started Sep 09 10:50:21 AM UTC 24
Finished Sep 09 10:51:56 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3373139738 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 22.prim_prince_test.3373139738
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/22.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/220.prim_prince_test.2025557453
Short name T200
Test name
Test status
Simulation time 1091348539 ps
CPU time 20.29 seconds
Started Sep 09 10:55:17 AM UTC 24
Finished Sep 09 10:55:43 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2025557453 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 220.prim_prince_test.2025557453
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/220.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/221.prim_prince_test.2881124145
Short name T225
Test name
Test status
Simulation time 2447275183 ps
CPU time 45.99 seconds
Started Sep 09 10:55:19 AM UTC 24
Finished Sep 09 10:56:16 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2881124145 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 221.prim_prince_test.2881124145
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/221.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/222.prim_prince_test.591350335
Short name T212
Test name
Test status
Simulation time 1622206522 ps
CPU time 29.96 seconds
Started Sep 09 10:55:23 AM UTC 24
Finished Sep 09 10:56:01 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=591350335 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 222.prim_prince_test.591350335
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/222.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/223.prim_prince_test.3363551426
Short name T233
Test name
Test status
Simulation time 2603907517 ps
CPU time 48.6 seconds
Started Sep 09 10:55:25 AM UTC 24
Finished Sep 09 10:56:26 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3363551426 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 223.prim_prince_test.3363551426
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/223.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/224.prim_prince_test.3722654357
Short name T219
Test name
Test status
Simulation time 1790474600 ps
CPU time 32.75 seconds
Started Sep 09 10:55:26 AM UTC 24
Finished Sep 09 10:56:08 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3722654357 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 224.prim_prince_test.3722654357
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/224.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/225.prim_prince_test.2848063045
Short name T215
Test name
Test status
Simulation time 1481225824 ps
CPU time 27.36 seconds
Started Sep 09 10:55:28 AM UTC 24
Finished Sep 09 10:56:03 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2848063045 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 225.prim_prince_test.2848063045
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/225.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/226.prim_prince_test.1281005504
Short name T252
Test name
Test status
Simulation time 3626526612 ps
CPU time 66.73 seconds
Started Sep 09 10:55:32 AM UTC 24
Finished Sep 09 10:56:55 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1281005504 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 226.prim_prince_test.1281005504
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/226.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/227.prim_prince_test.796319069
Short name T236
Test name
Test status
Simulation time 2460388497 ps
CPU time 46.03 seconds
Started Sep 09 10:55:32 AM UTC 24
Finished Sep 09 10:56:29 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=796319069 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 227.prim_prince_test.796319069
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/227.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/228.prim_prince_test.829653099
Short name T251
Test name
Test status
Simulation time 3692879009 ps
CPU time 65.66 seconds
Started Sep 09 10:55:32 AM UTC 24
Finished Sep 09 10:56:54 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=829653099 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 228.prim_prince_test.829653099
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/228.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/229.prim_prince_test.1961325284
Short name T242
Test name
Test status
Simulation time 2678101492 ps
CPU time 48.97 seconds
Started Sep 09 10:55:33 AM UTC 24
Finished Sep 09 10:56:34 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1961325284 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 229.prim_prince_test.1961325284
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/229.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/23.prim_prince_test.1404466902
Short name T5
Test name
Test status
Simulation time 1792168189 ps
CPU time 33.59 seconds
Started Sep 09 10:50:21 AM UTC 24
Finished Sep 09 10:51:05 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1404466902 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 23.prim_prince_test.1404466902
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/23.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/230.prim_prince_test.53945163
Short name T244
Test name
Test status
Simulation time 2920745982 ps
CPU time 52.74 seconds
Started Sep 09 10:55:34 AM UTC 24
Finished Sep 09 10:56:40 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=53945163 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 230.prim_prince_test.53945163
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/230.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/231.prim_prince_test.62043360
Short name T231
Test name
Test status
Simulation time 2222544727 ps
CPU time 40.82 seconds
Started Sep 09 10:55:34 AM UTC 24
Finished Sep 09 10:56:25 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=62043360 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 231.prim_prince_test.62043360
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/231.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/232.prim_prince_test.515476723
Short name T246
Test name
Test status
Simulation time 3250557844 ps
CPU time 58.61 seconds
Started Sep 09 10:55:35 AM UTC 24
Finished Sep 09 10:56:48 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=515476723 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 232.prim_prince_test.515476723
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/232.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/233.prim_prince_test.1261782810
Short name T245
Test name
Test status
Simulation time 2843338517 ps
CPU time 52.32 seconds
Started Sep 09 10:55:36 AM UTC 24
Finished Sep 09 10:56:41 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1261782810 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 233.prim_prince_test.1261782810
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/233.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/234.prim_prince_test.236831932
Short name T250
Test name
Test status
Simulation time 3409484797 ps
CPU time 61.27 seconds
Started Sep 09 10:55:37 AM UTC 24
Finished Sep 09 10:56:54 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=236831932 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 234.prim_prince_test.236831932
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/234.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/235.prim_prince_test.2390458023
Short name T224
Test name
Test status
Simulation time 1480361959 ps
CPU time 27.18 seconds
Started Sep 09 10:55:38 AM UTC 24
Finished Sep 09 10:56:13 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2390458023 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 235.prim_prince_test.2390458023
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/235.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/236.prim_prince_test.593336661
Short name T264
Test name
Test status
Simulation time 3734207759 ps
CPU time 67.29 seconds
Started Sep 09 10:55:41 AM UTC 24
Finished Sep 09 10:57:04 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=593336661 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 236.prim_prince_test.593336661
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/236.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/237.prim_prince_test.3867351778
Short name T262
Test name
Test status
Simulation time 3644105052 ps
CPU time 65.19 seconds
Started Sep 09 10:55:43 AM UTC 24
Finished Sep 09 10:57:04 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3867351778 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 237.prim_prince_test.3867351778
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/237.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/238.prim_prince_test.310922414
Short name T222
Test name
Test status
Simulation time 1158891267 ps
CPU time 21.33 seconds
Started Sep 09 10:55:44 AM UTC 24
Finished Sep 09 10:56:11 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=310922414 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 238.prim_prince_test.310922414
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/238.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/239.prim_prince_test.3818742283
Short name T221
Test name
Test status
Simulation time 1108204202 ps
CPU time 20.1 seconds
Started Sep 09 10:55:45 AM UTC 24
Finished Sep 09 10:56:10 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3818742283 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 239.prim_prince_test.3818742283
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/239.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/24.prim_prince_test.1725699614
Short name T27
Test name
Test status
Simulation time 3057711422 ps
CPU time 57.17 seconds
Started Sep 09 10:50:21 AM UTC 24
Finished Sep 09 10:51:41 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1725699614 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 24.prim_prince_test.1725699614
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/24.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/240.prim_prince_test.3904157210
Short name T253
Test name
Test status
Simulation time 2928225578 ps
CPU time 52.62 seconds
Started Sep 09 10:55:49 AM UTC 24
Finished Sep 09 10:56:55 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3904157210 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 240.prim_prince_test.3904157210
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/240.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/241.prim_prince_test.1888622131
Short name T228
Test name
Test status
Simulation time 1459249138 ps
CPU time 26.59 seconds
Started Sep 09 10:55:50 AM UTC 24
Finished Sep 09 10:56:24 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1888622131 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 241.prim_prince_test.1888622131
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/241.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/242.prim_prince_test.1854455684
Short name T239
Test name
Test status
Simulation time 1754540060 ps
CPU time 32.73 seconds
Started Sep 09 10:55:50 AM UTC 24
Finished Sep 09 10:56:32 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1854455684 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 242.prim_prince_test.1854455684
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/242.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/243.prim_prince_test.1375171747
Short name T270
Test name
Test status
Simulation time 3650402212 ps
CPU time 67.45 seconds
Started Sep 09 10:55:50 AM UTC 24
Finished Sep 09 10:57:14 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1375171747 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 243.prim_prince_test.1375171747
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/243.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/244.prim_prince_test.4104518993
Short name T227
Test name
Test status
Simulation time 1179683442 ps
CPU time 22.45 seconds
Started Sep 09 10:55:51 AM UTC 24
Finished Sep 09 10:56:19 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4104518993 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 244.prim_prince_test.4104518993
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/244.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/245.prim_prince_test.1774759487
Short name T265
Test name
Test status
Simulation time 3305542092 ps
CPU time 59.93 seconds
Started Sep 09 10:55:53 AM UTC 24
Finished Sep 09 10:57:07 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1774759487 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 245.prim_prince_test.1774759487
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/245.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/246.prim_prince_test.2362485287
Short name T261
Test name
Test status
Simulation time 2977901898 ps
CPU time 54.92 seconds
Started Sep 09 10:55:56 AM UTC 24
Finished Sep 09 10:57:04 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2362485287 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 246.prim_prince_test.2362485287
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/246.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/247.prim_prince_test.2739239559
Short name T226
Test name
Test status
Simulation time 962980815 ps
CPU time 17.52 seconds
Started Sep 09 10:55:56 AM UTC 24
Finished Sep 09 10:56:18 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2739239559 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 247.prim_prince_test.2739239559
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/247.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/248.prim_prince_test.987783484
Short name T243
Test name
Test status
Simulation time 1776523764 ps
CPU time 32.26 seconds
Started Sep 09 10:55:57 AM UTC 24
Finished Sep 09 10:56:37 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=987783484 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 248.prim_prince_test.987783484
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/248.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/249.prim_prince_test.1333683911
Short name T249
Test name
Test status
Simulation time 2415776731 ps
CPU time 44.46 seconds
Started Sep 09 10:55:58 AM UTC 24
Finished Sep 09 10:56:54 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1333683911 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 249.prim_prince_test.1333683911
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/249.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/25.prim_prince_test.1900569776
Short name T37
Test name
Test status
Simulation time 3583748074 ps
CPU time 67.28 seconds
Started Sep 09 10:50:21 AM UTC 24
Finished Sep 09 10:51:53 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1900569776 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 25.prim_prince_test.1900569776
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/25.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/250.prim_prince_test.2694165835
Short name T234
Test name
Test status
Simulation time 1285086659 ps
CPU time 23.57 seconds
Started Sep 09 10:55:58 AM UTC 24
Finished Sep 09 10:56:28 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2694165835 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 250.prim_prince_test.2694165835
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/250.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/251.prim_prince_test.1735936579
Short name T237
Test name
Test status
Simulation time 1180451979 ps
CPU time 21.55 seconds
Started Sep 09 10:56:02 AM UTC 24
Finished Sep 09 10:56:30 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1735936579 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 251.prim_prince_test.1735936579
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/251.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/252.prim_prince_test.2299038344
Short name T230
Test name
Test status
Simulation time 900580999 ps
CPU time 16.65 seconds
Started Sep 09 10:56:03 AM UTC 24
Finished Sep 09 10:56:25 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2299038344 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 252.prim_prince_test.2299038344
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/252.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/253.prim_prince_test.3146163009
Short name T281
Test name
Test status
Simulation time 3598706971 ps
CPU time 64.2 seconds
Started Sep 09 10:56:03 AM UTC 24
Finished Sep 09 10:57:23 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3146163009 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 253.prim_prince_test.3146163009
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/253.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/254.prim_prince_test.1812176044
Short name T232
Test name
Test status
Simulation time 909682471 ps
CPU time 17.17 seconds
Started Sep 09 10:56:03 AM UTC 24
Finished Sep 09 10:56:26 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1812176044 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 254.prim_prince_test.1812176044
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/254.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/255.prim_prince_test.1687139835
Short name T235
Test name
Test status
Simulation time 1026057160 ps
CPU time 18.94 seconds
Started Sep 09 10:56:05 AM UTC 24
Finished Sep 09 10:56:29 AM UTC 24
Peak memory 154348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1687139835 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 255.prim_prince_test.1687139835
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/255.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/256.prim_prince_test.2680690053
Short name T248
Test name
Test status
Simulation time 1819187499 ps
CPU time 33.8 seconds
Started Sep 09 10:56:07 AM UTC 24
Finished Sep 09 10:56:49 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2680690053 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 256.prim_prince_test.2680690053
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/256.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/257.prim_prince_test.3710091771
Short name T267
Test name
Test status
Simulation time 2807652319 ps
CPU time 50.47 seconds
Started Sep 09 10:56:08 AM UTC 24
Finished Sep 09 10:57:11 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3710091771 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 257.prim_prince_test.3710091771
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/257.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/258.prim_prince_test.2556463737
Short name T256
Test name
Test status
Simulation time 2164852814 ps
CPU time 39.45 seconds
Started Sep 09 10:56:09 AM UTC 24
Finished Sep 09 10:56:58 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2556463737 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 258.prim_prince_test.2556463737
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/258.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/259.prim_prince_test.3410282068
Short name T258
Test name
Test status
Simulation time 2283232681 ps
CPU time 41.29 seconds
Started Sep 09 10:56:09 AM UTC 24
Finished Sep 09 10:57:01 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3410282068 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 259.prim_prince_test.3410282068
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/259.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/26.prim_prince_test.224699998
Short name T26
Test name
Test status
Simulation time 2934785969 ps
CPU time 54.57 seconds
Started Sep 09 10:50:21 AM UTC 24
Finished Sep 09 10:51:38 AM UTC 24
Peak memory 154280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=224699998 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 26.prim_prince_test.224699998
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/26.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/260.prim_prince_test.4208599324
Short name T240
Test name
Test status
Simulation time 891008480 ps
CPU time 16.36 seconds
Started Sep 09 10:56:11 AM UTC 24
Finished Sep 09 10:56:32 AM UTC 24
Peak memory 154348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4208599324 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 260.prim_prince_test.4208599324
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/260.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/261.prim_prince_test.1784161171
Short name T263
Test name
Test status
Simulation time 2300083131 ps
CPU time 41.58 seconds
Started Sep 09 10:56:12 AM UTC 24
Finished Sep 09 10:57:04 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1784161171 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 261.prim_prince_test.1784161171
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/261.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/262.prim_prince_test.1435669366
Short name T276
Test name
Test status
Simulation time 3000341770 ps
CPU time 54.49 seconds
Started Sep 09 10:56:13 AM UTC 24
Finished Sep 09 10:57:21 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1435669366 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 262.prim_prince_test.1435669366
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/262.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/263.prim_prince_test.784002578
Short name T247
Test name
Test status
Simulation time 1557709645 ps
CPU time 28.16 seconds
Started Sep 09 10:56:13 AM UTC 24
Finished Sep 09 10:56:49 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=784002578 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 263.prim_prince_test.784002578
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/263.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/264.prim_prince_test.1666705468
Short name T293
Test name
Test status
Simulation time 3454684558 ps
CPU time 63.46 seconds
Started Sep 09 10:56:17 AM UTC 24
Finished Sep 09 10:57:36 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1666705468 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 264.prim_prince_test.1666705468
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/264.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/265.prim_prince_test.2620401973
Short name T266
Test name
Test status
Simulation time 2068576299 ps
CPU time 39.51 seconds
Started Sep 09 10:56:19 AM UTC 24
Finished Sep 09 10:57:08 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2620401973 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 265.prim_prince_test.2620401973
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/265.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/266.prim_prince_test.2185460431
Short name T255
Test name
Test status
Simulation time 1619348970 ps
CPU time 29.8 seconds
Started Sep 09 10:56:20 AM UTC 24
Finished Sep 09 10:56:57 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2185460431 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 266.prim_prince_test.2185460431
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/266.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/267.prim_prince_test.933848601
Short name T268
Test name
Test status
Simulation time 2066963809 ps
CPU time 37.77 seconds
Started Sep 09 10:56:25 AM UTC 24
Finished Sep 09 10:57:13 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=933848601 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 267.prim_prince_test.933848601
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/267.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/268.prim_prince_test.1862572900
Short name T274
Test name
Test status
Simulation time 2269257995 ps
CPU time 41 seconds
Started Sep 09 10:56:25 AM UTC 24
Finished Sep 09 10:57:17 AM UTC 24
Peak memory 154584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1862572900 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 268.prim_prince_test.1862572900
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/268.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/269.prim_prince_test.4106467643
Short name T285
Test name
Test status
Simulation time 2686626998 ps
CPU time 48.51 seconds
Started Sep 09 10:56:25 AM UTC 24
Finished Sep 09 10:57:26 AM UTC 24
Peak memory 154572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4106467643 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 269.prim_prince_test.4106467643
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/269.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/27.prim_prince_test.2747351094
Short name T28
Test name
Test status
Simulation time 3070445757 ps
CPU time 57.66 seconds
Started Sep 09 10:50:22 AM UTC 24
Finished Sep 09 10:51:41 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2747351094 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 27.prim_prince_test.2747351094
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/27.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/270.prim_prince_test.3632062017
Short name T290
Test name
Test status
Simulation time 3001313284 ps
CPU time 53.49 seconds
Started Sep 09 10:56:25 AM UTC 24
Finished Sep 09 10:57:32 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3632062017 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 270.prim_prince_test.3632062017
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/270.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/271.prim_prince_test.271476345
Short name T254
Test name
Test status
Simulation time 1192779450 ps
CPU time 22.6 seconds
Started Sep 09 10:56:26 AM UTC 24
Finished Sep 09 10:56:55 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=271476345 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 271.prim_prince_test.271476345
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/271.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/272.prim_prince_test.3188087265
Short name T287
Test name
Test status
Simulation time 2666112199 ps
CPU time 48.17 seconds
Started Sep 09 10:56:26 AM UTC 24
Finished Sep 09 10:57:26 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3188087265 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 272.prim_prince_test.3188087265
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/272.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/273.prim_prince_test.3898755324
Short name T272
Test name
Test status
Simulation time 2086750018 ps
CPU time 37.74 seconds
Started Sep 09 10:56:27 AM UTC 24
Finished Sep 09 10:57:15 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3898755324 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 273.prim_prince_test.3898755324
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/273.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/274.prim_prince_test.2214685182
Short name T257
Test name
Test status
Simulation time 1364594852 ps
CPU time 24.66 seconds
Started Sep 09 10:56:29 AM UTC 24
Finished Sep 09 10:57:00 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2214685182 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 274.prim_prince_test.2214685182
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/274.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/275.prim_prince_test.3846833271
Short name T282
Test name
Test status
Simulation time 2456593328 ps
CPU time 44.07 seconds
Started Sep 09 10:56:30 AM UTC 24
Finished Sep 09 10:57:25 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3846833271 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 275.prim_prince_test.3846833271
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/275.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/276.prim_prince_test.2821174734
Short name T275
Test name
Test status
Simulation time 2072878956 ps
CPU time 38.77 seconds
Started Sep 09 10:56:30 AM UTC 24
Finished Sep 09 10:57:18 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2821174734 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 276.prim_prince_test.2821174734
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/276.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/277.prim_prince_test.2113045455
Short name T292
Test name
Test status
Simulation time 2736779108 ps
CPU time 49.72 seconds
Started Sep 09 10:56:31 AM UTC 24
Finished Sep 09 10:57:33 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2113045455 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 277.prim_prince_test.2113045455
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/277.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/278.prim_prince_test.3503099703
Short name T283
Test name
Test status
Simulation time 2323747007 ps
CPU time 42.31 seconds
Started Sep 09 10:56:32 AM UTC 24
Finished Sep 09 10:57:25 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3503099703 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 278.prim_prince_test.3503099703
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/278.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/279.prim_prince_test.3505526340
Short name T259
Test name
Test status
Simulation time 1319712395 ps
CPU time 24.89 seconds
Started Sep 09 10:56:32 AM UTC 24
Finished Sep 09 10:57:04 AM UTC 24
Peak memory 154348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3505526340 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 279.prim_prince_test.3505526340
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/279.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/28.prim_prince_test.4050132026
Short name T6
Test name
Test status
Simulation time 1441198526 ps
CPU time 28.13 seconds
Started Sep 09 10:50:30 AM UTC 24
Finished Sep 09 10:51:05 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4050132026 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 28.prim_prince_test.4050132026
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/28.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/280.prim_prince_test.2971348818
Short name T271
Test name
Test status
Simulation time 1793059762 ps
CPU time 32.63 seconds
Started Sep 09 10:56:33 AM UTC 24
Finished Sep 09 10:57:14 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2971348818 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 280.prim_prince_test.2971348818
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/280.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/281.prim_prince_test.1005186725
Short name T269
Test name
Test status
Simulation time 1650004578 ps
CPU time 30.52 seconds
Started Sep 09 10:56:34 AM UTC 24
Finished Sep 09 10:57:13 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1005186725 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 281.prim_prince_test.1005186725
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/281.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/282.prim_prince_test.2039005629
Short name T279
Test name
Test status
Simulation time 2092080469 ps
CPU time 38.62 seconds
Started Sep 09 10:56:34 AM UTC 24
Finished Sep 09 10:57:23 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2039005629 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 282.prim_prince_test.2039005629
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/282.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/283.prim_prince_test.798499589
Short name T308
Test name
Test status
Simulation time 3569387465 ps
CPU time 63.96 seconds
Started Sep 09 10:56:38 AM UTC 24
Finished Sep 09 10:57:58 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=798499589 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 283.prim_prince_test.798499589
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/283.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/284.prim_prince_test.4045402185
Short name T260
Test name
Test status
Simulation time 1016912122 ps
CPU time 18.03 seconds
Started Sep 09 10:56:41 AM UTC 24
Finished Sep 09 10:57:04 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4045402185 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 284.prim_prince_test.4045402185
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/284.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/285.prim_prince_test.2611827976
Short name T284
Test name
Test status
Simulation time 1821994956 ps
CPU time 34.1 seconds
Started Sep 09 10:56:43 AM UTC 24
Finished Sep 09 10:57:26 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2611827976 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 285.prim_prince_test.2611827976
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/285.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/286.prim_prince_test.2686591748
Short name T309
Test name
Test status
Simulation time 3193899032 ps
CPU time 56.96 seconds
Started Sep 09 10:56:48 AM UTC 24
Finished Sep 09 10:57:59 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2686591748 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 286.prim_prince_test.2686591748
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/286.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/287.prim_prince_test.1639345342
Short name T312
Test name
Test status
Simulation time 3444014591 ps
CPU time 63.32 seconds
Started Sep 09 10:56:49 AM UTC 24
Finished Sep 09 10:58:08 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1639345342 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 287.prim_prince_test.1639345342
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/287.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/288.prim_prince_test.2468144827
Short name T277
Test name
Test status
Simulation time 1377179951 ps
CPU time 25 seconds
Started Sep 09 10:56:50 AM UTC 24
Finished Sep 09 10:57:22 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2468144827 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 288.prim_prince_test.2468144827
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/288.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/289.prim_prince_test.4008577386
Short name T298
Test name
Test status
Simulation time 2333799197 ps
CPU time 43.33 seconds
Started Sep 09 10:56:50 AM UTC 24
Finished Sep 09 10:57:44 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4008577386 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 289.prim_prince_test.4008577386
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/289.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/29.prim_prince_test.4230692035
Short name T10
Test name
Test status
Simulation time 1777383216 ps
CPU time 33.14 seconds
Started Sep 09 10:50:31 AM UTC 24
Finished Sep 09 10:51:12 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4230692035 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 29.prim_prince_test.4230692035
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/29.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/290.prim_prince_test.186518940
Short name T304
Test name
Test status
Simulation time 2571056521 ps
CPU time 47.78 seconds
Started Sep 09 10:56:54 AM UTC 24
Finished Sep 09 10:57:54 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=186518940 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 290.prim_prince_test.186518940
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/290.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/291.prim_prince_test.2827490654
Short name T273
Test name
Test status
Simulation time 906249477 ps
CPU time 16.87 seconds
Started Sep 09 10:56:54 AM UTC 24
Finished Sep 09 10:57:16 AM UTC 24
Peak memory 154348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2827490654 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 291.prim_prince_test.2827490654
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/291.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/292.prim_prince_test.2784900415
Short name T291
Test name
Test status
Simulation time 1630812726 ps
CPU time 30.05 seconds
Started Sep 09 10:56:54 AM UTC 24
Finished Sep 09 10:57:32 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2784900415 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 292.prim_prince_test.2784900415
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/292.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/293.prim_prince_test.3303878336
Short name T305
Test name
Test status
Simulation time 2586181745 ps
CPU time 46.82 seconds
Started Sep 09 10:56:56 AM UTC 24
Finished Sep 09 10:57:54 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3303878336 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 293.prim_prince_test.3303878336
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/293.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/294.prim_prince_test.3860775238
Short name T280
Test name
Test status
Simulation time 1145695720 ps
CPU time 21.68 seconds
Started Sep 09 10:56:56 AM UTC 24
Finished Sep 09 10:57:23 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3860775238 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 294.prim_prince_test.3860775238
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/294.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/295.prim_prince_test.2919240079
Short name T288
Test name
Test status
Simulation time 1414998201 ps
CPU time 25.44 seconds
Started Sep 09 10:56:56 AM UTC 24
Finished Sep 09 10:57:28 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2919240079 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 295.prim_prince_test.2919240079
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/295.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/296.prim_prince_test.3654464119
Short name T316
Test name
Test status
Simulation time 3329085049 ps
CPU time 59.55 seconds
Started Sep 09 10:56:58 AM UTC 24
Finished Sep 09 10:58:12 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3654464119 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 296.prim_prince_test.3654464119
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/296.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/297.prim_prince_test.522675877
Short name T295
Test name
Test status
Simulation time 1961991678 ps
CPU time 35.09 seconds
Started Sep 09 10:56:59 AM UTC 24
Finished Sep 09 10:57:43 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=522675877 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 297.prim_prince_test.522675877
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/297.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/298.prim_prince_test.3841543455
Short name T278
Test name
Test status
Simulation time 930675166 ps
CPU time 16.84 seconds
Started Sep 09 10:57:01 AM UTC 24
Finished Sep 09 10:57:23 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3841543455 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 298.prim_prince_test.3841543455
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/298.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/299.prim_prince_test.1051422171
Short name T300
Test name
Test status
Simulation time 1941251272 ps
CPU time 35.4 seconds
Started Sep 09 10:57:02 AM UTC 24
Finished Sep 09 10:57:47 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1051422171 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 299.prim_prince_test.1051422171
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/299.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/3.prim_prince_test.73849451
Short name T4
Test name
Test status
Simulation time 1881105528 ps
CPU time 34.66 seconds
Started Sep 09 10:50:16 AM UTC 24
Finished Sep 09 10:51:01 AM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=73849451 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 3.prim_prince_test.73849451
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/3.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/30.prim_prince_test.4095051995
Short name T17
Test name
Test status
Simulation time 2058844959 ps
CPU time 38.35 seconds
Started Sep 09 10:50:31 AM UTC 24
Finished Sep 09 10:51:19 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4095051995 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 30.prim_prince_test.4095051995
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/30.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/300.prim_prince_test.4173620357
Short name T296
Test name
Test status
Simulation time 1706541562 ps
CPU time 30.7 seconds
Started Sep 09 10:57:04 AM UTC 24
Finished Sep 09 10:57:43 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4173620357 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 300.prim_prince_test.4173620357
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/300.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/301.prim_prince_test.4201956596
Short name T307
Test name
Test status
Simulation time 2310685348 ps
CPU time 42.83 seconds
Started Sep 09 10:57:04 AM UTC 24
Finished Sep 09 10:57:58 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4201956596 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 301.prim_prince_test.4201956596
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/301.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/302.prim_prince_test.1758553707
Short name T326
Test name
Test status
Simulation time 3443916818 ps
CPU time 61.42 seconds
Started Sep 09 10:57:06 AM UTC 24
Finished Sep 09 10:58:22 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1758553707 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 302.prim_prince_test.1758553707
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/302.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/303.prim_prince_test.3466919512
Short name T286
Test name
Test status
Simulation time 833121993 ps
CPU time 15.91 seconds
Started Sep 09 10:57:06 AM UTC 24
Finished Sep 09 10:57:26 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3466919512 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 303.prim_prince_test.3466919512
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/303.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/304.prim_prince_test.471912899
Short name T289
Test name
Test status
Simulation time 1011207929 ps
CPU time 18.66 seconds
Started Sep 09 10:57:06 AM UTC 24
Finished Sep 09 10:57:30 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=471912899 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 304.prim_prince_test.471912899
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/304.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/305.prim_prince_test.1520392414
Short name T303
Test name
Test status
Simulation time 2024969176 ps
CPU time 37.65 seconds
Started Sep 09 10:57:06 AM UTC 24
Finished Sep 09 10:57:53 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1520392414 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 305.prim_prince_test.1520392414
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/305.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/306.prim_prince_test.581951475
Short name T297
Test name
Test status
Simulation time 1531880675 ps
CPU time 28.42 seconds
Started Sep 09 10:57:08 AM UTC 24
Finished Sep 09 10:57:44 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=581951475 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 306.prim_prince_test.581951475
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/306.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/307.prim_prince_test.4073583255
Short name T294
Test name
Test status
Simulation time 1166524205 ps
CPU time 22.57 seconds
Started Sep 09 10:57:08 AM UTC 24
Finished Sep 09 10:57:36 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4073583255 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 307.prim_prince_test.4073583255
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/307.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/308.prim_prince_test.1399593383
Short name T323
Test name
Test status
Simulation time 3068159530 ps
CPU time 55.84 seconds
Started Sep 09 10:57:11 AM UTC 24
Finished Sep 09 10:58:20 AM UTC 24
Peak memory 154652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1399593383 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 308.prim_prince_test.1399593383
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/308.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/309.prim_prince_test.791873242
Short name T319
Test name
Test status
Simulation time 2738812219 ps
CPU time 49.79 seconds
Started Sep 09 10:57:13 AM UTC 24
Finished Sep 09 10:58:15 AM UTC 24
Peak memory 154180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=791873242 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 309.prim_prince_test.791873242
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/309.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/31.prim_prince_test.1453518115
Short name T7
Test name
Test status
Simulation time 1313017558 ps
CPU time 25.87 seconds
Started Sep 09 10:50:36 AM UTC 24
Finished Sep 09 10:51:08 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1453518115 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 31.prim_prince_test.1453518115
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/31.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/310.prim_prince_test.2441130154
Short name T325
Test name
Test status
Simulation time 3023462096 ps
CPU time 55.32 seconds
Started Sep 09 10:57:13 AM UTC 24
Finished Sep 09 10:58:22 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2441130154 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 310.prim_prince_test.2441130154
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/310.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/311.prim_prince_test.1820235466
Short name T301
Test name
Test status
Simulation time 1423960212 ps
CPU time 25.82 seconds
Started Sep 09 10:57:16 AM UTC 24
Finished Sep 09 10:57:48 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1820235466 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 311.prim_prince_test.1820235466
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/311.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/312.prim_prince_test.3932278313
Short name T337
Test name
Test status
Simulation time 3456574944 ps
CPU time 63.03 seconds
Started Sep 09 10:57:16 AM UTC 24
Finished Sep 09 10:58:34 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3932278313 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 312.prim_prince_test.3932278313
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/312.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/313.prim_prince_test.4040866104
Short name T340
Test name
Test status
Simulation time 3647562529 ps
CPU time 67.31 seconds
Started Sep 09 10:57:16 AM UTC 24
Finished Sep 09 10:58:39 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4040866104 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 313.prim_prince_test.4040866104
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/313.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/314.prim_prince_test.687626051
Short name T338
Test name
Test status
Simulation time 3487368661 ps
CPU time 64.85 seconds
Started Sep 09 10:57:17 AM UTC 24
Finished Sep 09 10:58:37 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=687626051 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 314.prim_prince_test.687626051
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/314.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/315.prim_prince_test.1699605587
Short name T322
Test name
Test status
Simulation time 2638278990 ps
CPU time 48.62 seconds
Started Sep 09 10:57:18 AM UTC 24
Finished Sep 09 10:58:18 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1699605587 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 315.prim_prince_test.1699605587
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/315.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/316.prim_prince_test.1851779858
Short name T315
Test name
Test status
Simulation time 2308955657 ps
CPU time 40.71 seconds
Started Sep 09 10:57:19 AM UTC 24
Finished Sep 09 10:58:10 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1851779858 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 316.prim_prince_test.1851779858
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/316.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/317.prim_prince_test.1525615044
Short name T324
Test name
Test status
Simulation time 2663396373 ps
CPU time 47.52 seconds
Started Sep 09 10:57:22 AM UTC 24
Finished Sep 09 10:58:22 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1525615044 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 317.prim_prince_test.1525615044
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/317.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/318.prim_prince_test.2788407174
Short name T314
Test name
Test status
Simulation time 1988904484 ps
CPU time 37.14 seconds
Started Sep 09 10:57:24 AM UTC 24
Finished Sep 09 10:58:10 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2788407174 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 318.prim_prince_test.2788407174
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/318.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/319.prim_prince_test.3717898199
Short name T311
Test name
Test status
Simulation time 1619288955 ps
CPU time 29.59 seconds
Started Sep 09 10:57:24 AM UTC 24
Finished Sep 09 10:58:01 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3717898199 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 319.prim_prince_test.3717898199
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/319.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/32.prim_prince_test.740757918
Short name T19
Test name
Test status
Simulation time 1967569882 ps
CPU time 38.08 seconds
Started Sep 09 10:50:38 AM UTC 24
Finished Sep 09 10:51:26 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=740757918 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 32.prim_prince_test.740757918
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/32.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/320.prim_prince_test.503186563
Short name T318
Test name
Test status
Simulation time 2248177499 ps
CPU time 40 seconds
Started Sep 09 10:57:24 AM UTC 24
Finished Sep 09 10:58:14 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=503186563 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 320.prim_prince_test.503186563
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/320.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/321.prim_prince_test.2893805306
Short name T306
Test name
Test status
Simulation time 1305819402 ps
CPU time 24.44 seconds
Started Sep 09 10:57:24 AM UTC 24
Finished Sep 09 10:57:54 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2893805306 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 321.prim_prince_test.2893805306
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/321.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/322.prim_prince_test.2483279595
Short name T302
Test name
Test status
Simulation time 1055559016 ps
CPU time 19.44 seconds
Started Sep 09 10:57:25 AM UTC 24
Finished Sep 09 10:57:50 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2483279595 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 322.prim_prince_test.2483279595
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/322.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/323.prim_prince_test.3889554438
Short name T334
Test name
Test status
Simulation time 2757791992 ps
CPU time 50.71 seconds
Started Sep 09 10:57:26 AM UTC 24
Finished Sep 09 10:58:29 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3889554438 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 323.prim_prince_test.3889554438
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/323.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/324.prim_prince_test.1000874475
Short name T329
Test name
Test status
Simulation time 2630803045 ps
CPU time 47.32 seconds
Started Sep 09 10:57:26 AM UTC 24
Finished Sep 09 10:58:25 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1000874475 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 324.prim_prince_test.1000874475
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/324.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/325.prim_prince_test.1394935865
Short name T320
Test name
Test status
Simulation time 2234514796 ps
CPU time 40.49 seconds
Started Sep 09 10:57:26 AM UTC 24
Finished Sep 09 10:58:17 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1394935865 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 325.prim_prince_test.1394935865
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/325.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/326.prim_prince_test.2921139365
Short name T313
Test name
Test status
Simulation time 1829808977 ps
CPU time 33.28 seconds
Started Sep 09 10:57:28 AM UTC 24
Finished Sep 09 10:58:10 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2921139365 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 326.prim_prince_test.2921139365
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/326.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/327.prim_prince_test.2652559141
Short name T299
Test name
Test status
Simulation time 752483822 ps
CPU time 14.08 seconds
Started Sep 09 10:57:28 AM UTC 24
Finished Sep 09 10:57:46 AM UTC 24
Peak memory 154512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2652559141 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 327.prim_prince_test.2652559141
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/327.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/328.prim_prince_test.4186740901
Short name T355
Test name
Test status
Simulation time 3724103331 ps
CPU time 68.46 seconds
Started Sep 09 10:57:28 AM UTC 24
Finished Sep 09 10:58:52 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4186740901 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 328.prim_prince_test.4186740901
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/328.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/329.prim_prince_test.342105791
Short name T351
Test name
Test status
Simulation time 3379957052 ps
CPU time 62.28 seconds
Started Sep 09 10:57:29 AM UTC 24
Finished Sep 09 10:58:46 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=342105791 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 329.prim_prince_test.342105791
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/329.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/33.prim_prince_test.2775136111
Short name T42
Test name
Test status
Simulation time 3616993730 ps
CPU time 68.37 seconds
Started Sep 09 10:50:39 AM UTC 24
Finished Sep 09 10:52:04 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2775136111 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 33.prim_prince_test.2775136111
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/33.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/330.prim_prince_test.1300273507
Short name T310
Test name
Test status
Simulation time 1243254120 ps
CPU time 22.44 seconds
Started Sep 09 10:57:31 AM UTC 24
Finished Sep 09 10:57:59 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1300273507 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 330.prim_prince_test.1300273507
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/330.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/331.prim_prince_test.2860059797
Short name T354
Test name
Test status
Simulation time 3417477993 ps
CPU time 62.77 seconds
Started Sep 09 10:57:33 AM UTC 24
Finished Sep 09 10:58:51 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2860059797 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 331.prim_prince_test.2860059797
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/331.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/332.prim_prince_test.284012041
Short name T321
Test name
Test status
Simulation time 1894773408 ps
CPU time 35.34 seconds
Started Sep 09 10:57:33 AM UTC 24
Finished Sep 09 10:58:17 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=284012041 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 332.prim_prince_test.284012041
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/332.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/333.prim_prince_test.3123059213
Short name T346
Test name
Test status
Simulation time 3081621399 ps
CPU time 54.91 seconds
Started Sep 09 10:57:34 AM UTC 24
Finished Sep 09 10:58:43 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3123059213 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 333.prim_prince_test.3123059213
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/333.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/334.prim_prince_test.2805927603
Short name T347
Test name
Test status
Simulation time 3010867128 ps
CPU time 53.46 seconds
Started Sep 09 10:57:37 AM UTC 24
Finished Sep 09 10:58:44 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2805927603 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 334.prim_prince_test.2805927603
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/334.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/335.prim_prince_test.2891407502
Short name T333
Test name
Test status
Simulation time 2246508180 ps
CPU time 40.63 seconds
Started Sep 09 10:57:37 AM UTC 24
Finished Sep 09 10:58:28 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2891407502 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 335.prim_prince_test.2891407502
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/335.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/336.prim_prince_test.1853613193
Short name T331
Test name
Test status
Simulation time 1875805855 ps
CPU time 33.35 seconds
Started Sep 09 10:57:44 AM UTC 24
Finished Sep 09 10:58:26 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1853613193 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 336.prim_prince_test.1853613193
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/336.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/337.prim_prince_test.3710552924
Short name T344
Test name
Test status
Simulation time 2579507753 ps
CPU time 46.67 seconds
Started Sep 09 10:57:44 AM UTC 24
Finished Sep 09 10:58:42 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3710552924 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 337.prim_prince_test.3710552924
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/337.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/338.prim_prince_test.3865652615
Short name T328
Test name
Test status
Simulation time 1747179501 ps
CPU time 31.51 seconds
Started Sep 09 10:57:45 AM UTC 24
Finished Sep 09 10:58:25 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3865652615 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 338.prim_prince_test.3865652615
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/338.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/339.prim_prince_test.1126137022
Short name T330
Test name
Test status
Simulation time 1741124388 ps
CPU time 32.01 seconds
Started Sep 09 10:57:45 AM UTC 24
Finished Sep 09 10:58:26 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1126137022 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 339.prim_prince_test.1126137022
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/339.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/34.prim_prince_test.289517949
Short name T49
Test name
Test status
Simulation time 3496311754 ps
CPU time 66.59 seconds
Started Sep 09 10:50:49 AM UTC 24
Finished Sep 09 10:52:12 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=289517949 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 34.prim_prince_test.289517949
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/34.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/340.prim_prince_test.807841430
Short name T341
Test name
Test status
Simulation time 2397071152 ps
CPU time 43.23 seconds
Started Sep 09 10:57:46 AM UTC 24
Finished Sep 09 10:58:40 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=807841430 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 340.prim_prince_test.807841430
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/340.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/341.prim_prince_test.912930371
Short name T336
Test name
Test status
Simulation time 1935751871 ps
CPU time 34.58 seconds
Started Sep 09 10:57:47 AM UTC 24
Finished Sep 09 10:58:31 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=912930371 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 341.prim_prince_test.912930371
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/341.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/342.prim_prince_test.3976683845
Short name T339
Test name
Test status
Simulation time 2056642136 ps
CPU time 37.82 seconds
Started Sep 09 10:57:49 AM UTC 24
Finished Sep 09 10:58:37 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3976683845 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 342.prim_prince_test.3976683845
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/342.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/343.prim_prince_test.2834205438
Short name T357
Test name
Test status
Simulation time 2845168928 ps
CPU time 51.67 seconds
Started Sep 09 10:57:50 AM UTC 24
Finished Sep 09 10:58:55 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2834205438 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 343.prim_prince_test.2834205438
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/343.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/344.prim_prince_test.3407535984
Short name T317
Test name
Test status
Simulation time 814940853 ps
CPU time 15.17 seconds
Started Sep 09 10:57:54 AM UTC 24
Finished Sep 09 10:58:13 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3407535984 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 344.prim_prince_test.3407535984
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/344.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/345.prim_prince_test.3334632508
Short name T352
Test name
Test status
Simulation time 2292581296 ps
CPU time 41.51 seconds
Started Sep 09 10:57:55 AM UTC 24
Finished Sep 09 10:58:47 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3334632508 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 345.prim_prince_test.3334632508
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/345.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/346.prim_prince_test.2826781687
Short name T367
Test name
Test status
Simulation time 3622442860 ps
CPU time 64.6 seconds
Started Sep 09 10:57:55 AM UTC 24
Finished Sep 09 10:59:15 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2826781687 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 346.prim_prince_test.2826781687
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/346.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/347.prim_prince_test.911909709
Short name T332
Test name
Test status
Simulation time 1388414552 ps
CPU time 24.68 seconds
Started Sep 09 10:57:55 AM UTC 24
Finished Sep 09 10:58:26 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=911909709 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 347.prim_prince_test.911909709
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/347.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/348.prim_prince_test.2733871037
Short name T342
Test name
Test status
Simulation time 1870406312 ps
CPU time 33.92 seconds
Started Sep 09 10:57:58 AM UTC 24
Finished Sep 09 10:58:41 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2733871037 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 348.prim_prince_test.2733871037
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/348.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/349.prim_prince_test.3791162031
Short name T375
Test name
Test status
Simulation time 3695378410 ps
CPU time 68.5 seconds
Started Sep 09 10:57:59 AM UTC 24
Finished Sep 09 10:59:24 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3791162031 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 349.prim_prince_test.3791162031
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/349.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/35.prim_prince_test.1348010676
Short name T20
Test name
Test status
Simulation time 1424421631 ps
CPU time 27.43 seconds
Started Sep 09 10:50:53 AM UTC 24
Finished Sep 09 10:51:28 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1348010676 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 35.prim_prince_test.1348010676
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/35.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/350.prim_prince_test.2122134117
Short name T358
Test name
Test status
Simulation time 2450688762 ps
CPU time 44.93 seconds
Started Sep 09 10:58:00 AM UTC 24
Finished Sep 09 10:58:56 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2122134117 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 350.prim_prince_test.2122134117
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/350.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/351.prim_prince_test.2860773254
Short name T327
Test name
Test status
Simulation time 945839401 ps
CPU time 17.44 seconds
Started Sep 09 10:58:00 AM UTC 24
Finished Sep 09 10:58:23 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2860773254 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 351.prim_prince_test.2860773254
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/351.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/352.prim_prince_test.3118271400
Short name T379
Test name
Test status
Simulation time 3618937540 ps
CPU time 66.88 seconds
Started Sep 09 10:58:02 AM UTC 24
Finished Sep 09 10:59:24 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3118271400 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 352.prim_prince_test.3118271400
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/352.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/353.prim_prince_test.4134718132
Short name T345
Test name
Test status
Simulation time 1480839212 ps
CPU time 26.5 seconds
Started Sep 09 10:58:09 AM UTC 24
Finished Sep 09 10:58:42 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4134718132 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 353.prim_prince_test.4134718132
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/353.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/354.prim_prince_test.2657127431
Short name T381
Test name
Test status
Simulation time 3385015272 ps
CPU time 62.46 seconds
Started Sep 09 10:58:10 AM UTC 24
Finished Sep 09 10:59:27 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2657127431 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 354.prim_prince_test.2657127431
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/354.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/355.prim_prince_test.1778633658
Short name T363
Test name
Test status
Simulation time 2524258617 ps
CPU time 45.39 seconds
Started Sep 09 10:58:11 AM UTC 24
Finished Sep 09 10:59:08 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1778633658 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 355.prim_prince_test.1778633658
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/355.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/356.prim_prince_test.1887177614
Short name T335
Test name
Test status
Simulation time 781174091 ps
CPU time 14.35 seconds
Started Sep 09 10:58:11 AM UTC 24
Finished Sep 09 10:58:30 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1887177614 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 356.prim_prince_test.1887177614
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/356.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/357.prim_prince_test.4009829042
Short name T373
Test name
Test status
Simulation time 3169574738 ps
CPU time 55.58 seconds
Started Sep 09 10:58:12 AM UTC 24
Finished Sep 09 10:59:22 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4009829042 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 357.prim_prince_test.4009829042
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/357.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/358.prim_prince_test.1465222649
Short name T362
Test name
Test status
Simulation time 2200291568 ps
CPU time 39.16 seconds
Started Sep 09 10:58:13 AM UTC 24
Finished Sep 09 10:59:02 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1465222649 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 358.prim_prince_test.1465222649
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/358.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/359.prim_prince_test.3155224012
Short name T348
Test name
Test status
Simulation time 1316687480 ps
CPU time 23.31 seconds
Started Sep 09 10:58:15 AM UTC 24
Finished Sep 09 10:58:44 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3155224012 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 359.prim_prince_test.3155224012
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/359.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/36.prim_prince_test.258771249
Short name T52
Test name
Test status
Simulation time 3176975314 ps
CPU time 59.8 seconds
Started Sep 09 10:51:02 AM UTC 24
Finished Sep 09 10:52:16 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=258771249 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 36.prim_prince_test.258771249
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/36.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/360.prim_prince_test.242748689
Short name T378
Test name
Test status
Simulation time 3161506100 ps
CPU time 55.9 seconds
Started Sep 09 10:58:15 AM UTC 24
Finished Sep 09 10:59:24 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=242748689 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 360.prim_prince_test.242748689
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/360.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/361.prim_prince_test.3237484702
Short name T356
Test name
Test status
Simulation time 1636954792 ps
CPU time 29.86 seconds
Started Sep 09 10:58:16 AM UTC 24
Finished Sep 09 10:58:53 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3237484702 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 361.prim_prince_test.3237484702
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/361.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/362.prim_prince_test.265216315
Short name T343
Test name
Test status
Simulation time 972767565 ps
CPU time 17.73 seconds
Started Sep 09 10:58:18 AM UTC 24
Finished Sep 09 10:58:41 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=265216315 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 362.prim_prince_test.265216315
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/362.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/363.prim_prince_test.689084329
Short name T369
Test name
Test status
Simulation time 2712241885 ps
CPU time 48.12 seconds
Started Sep 09 10:58:18 AM UTC 24
Finished Sep 09 10:59:18 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=689084329 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 363.prim_prince_test.689084329
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/363.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/364.prim_prince_test.1375586667
Short name T380
Test name
Test status
Simulation time 2906578159 ps
CPU time 53.03 seconds
Started Sep 09 10:58:19 AM UTC 24
Finished Sep 09 10:59:25 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1375586667 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 364.prim_prince_test.1375586667
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/364.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/365.prim_prince_test.3423506499
Short name T353
Test name
Test status
Simulation time 1201873725 ps
CPU time 21.34 seconds
Started Sep 09 10:58:21 AM UTC 24
Finished Sep 09 10:58:48 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3423506499 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 365.prim_prince_test.3423506499
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/365.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/366.prim_prince_test.4231382173
Short name T372
Test name
Test status
Simulation time 2583512615 ps
CPU time 46.38 seconds
Started Sep 09 10:58:23 AM UTC 24
Finished Sep 09 10:59:20 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4231382173 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 366.prim_prince_test.4231382173
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/366.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/367.prim_prince_test.2185902208
Short name T394
Test name
Test status
Simulation time 3579785452 ps
CPU time 65.8 seconds
Started Sep 09 10:58:23 AM UTC 24
Finished Sep 09 10:59:44 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2185902208 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 367.prim_prince_test.2185902208
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/367.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/368.prim_prince_test.2905897845
Short name T364
Test name
Test status
Simulation time 2236202005 ps
CPU time 39.79 seconds
Started Sep 09 10:58:23 AM UTC 24
Finished Sep 09 10:59:12 AM UTC 24
Peak memory 154624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2905897845 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 368.prim_prince_test.2905897845
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/368.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/369.prim_prince_test.3952071274
Short name T350
Test name
Test status
Simulation time 941721259 ps
CPU time 18.2 seconds
Started Sep 09 10:58:23 AM UTC 24
Finished Sep 09 10:58:46 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3952071274 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 369.prim_prince_test.3952071274
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/369.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/37.prim_prince_test.1737150960
Short name T43
Test name
Test status
Simulation time 2586718657 ps
CPU time 48.66 seconds
Started Sep 09 10:51:05 AM UTC 24
Finished Sep 09 10:52:06 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1737150960 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 37.prim_prince_test.1737150960
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/37.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/370.prim_prince_test.125142867
Short name T349
Test name
Test status
Simulation time 883799742 ps
CPU time 16.39 seconds
Started Sep 09 10:58:24 AM UTC 24
Finished Sep 09 10:58:45 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=125142867 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 370.prim_prince_test.125142867
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/370.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/371.prim_prince_test.1469929666
Short name T359
Test name
Test status
Simulation time 1323963402 ps
CPU time 24.13 seconds
Started Sep 09 10:58:26 AM UTC 24
Finished Sep 09 10:58:57 AM UTC 24
Peak memory 154348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1469929666 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 371.prim_prince_test.1469929666
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/371.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/372.prim_prince_test.3915888761
Short name T371
Test name
Test status
Simulation time 2399508842 ps
CPU time 42.32 seconds
Started Sep 09 10:58:26 AM UTC 24
Finished Sep 09 10:59:19 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3915888761 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 372.prim_prince_test.3915888761
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/372.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/373.prim_prince_test.3729565902
Short name T389
Test name
Test status
Simulation time 3404751786 ps
CPU time 60.49 seconds
Started Sep 09 10:58:26 AM UTC 24
Finished Sep 09 10:59:41 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3729565902 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 373.prim_prince_test.3729565902
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/373.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/374.prim_prince_test.1494429908
Short name T382
Test name
Test status
Simulation time 2679575792 ps
CPU time 48.04 seconds
Started Sep 09 10:58:27 AM UTC 24
Finished Sep 09 10:59:28 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1494429908 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 374.prim_prince_test.1494429908
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/374.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/375.prim_prince_test.3159026987
Short name T361
Test name
Test status
Simulation time 1452560956 ps
CPU time 27.03 seconds
Started Sep 09 10:58:27 AM UTC 24
Finished Sep 09 10:59:01 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3159026987 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 375.prim_prince_test.3159026987
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/375.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/376.prim_prince_test.1065763675
Short name T368
Test name
Test status
Simulation time 2090067126 ps
CPU time 38.78 seconds
Started Sep 09 10:58:29 AM UTC 24
Finished Sep 09 10:59:17 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1065763675 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 376.prim_prince_test.1065763675
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/376.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/377.prim_prince_test.2407753004
Short name T374
Test name
Test status
Simulation time 2345580111 ps
CPU time 41.99 seconds
Started Sep 09 10:58:30 AM UTC 24
Finished Sep 09 10:59:22 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2407753004 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 377.prim_prince_test.2407753004
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/377.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/378.prim_prince_test.2018546452
Short name T360
Test name
Test status
Simulation time 1077383596 ps
CPU time 20.44 seconds
Started Sep 09 10:58:31 AM UTC 24
Finished Sep 09 10:58:57 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2018546452 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 378.prim_prince_test.2018546452
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/378.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/379.prim_prince_test.3471546595
Short name T403
Test name
Test status
Simulation time 3435842114 ps
CPU time 63.93 seconds
Started Sep 09 10:58:32 AM UTC 24
Finished Sep 09 10:59:51 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3471546595 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 379.prim_prince_test.3471546595
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/379.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/38.prim_prince_test.2240544939
Short name T21
Test name
Test status
Simulation time 997596288 ps
CPU time 19.27 seconds
Started Sep 09 10:51:05 AM UTC 24
Finished Sep 09 10:51:30 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2240544939 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 38.prim_prince_test.2240544939
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/38.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/380.prim_prince_test.1712824974
Short name T391
Test name
Test status
Simulation time 3101437760 ps
CPU time 55.08 seconds
Started Sep 09 10:58:34 AM UTC 24
Finished Sep 09 10:59:43 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1712824974 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 380.prim_prince_test.1712824974
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/380.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/381.prim_prince_test.823846584
Short name T404
Test name
Test status
Simulation time 3505007037 ps
CPU time 61.12 seconds
Started Sep 09 10:58:37 AM UTC 24
Finished Sep 09 10:59:53 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=823846584 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 381.prim_prince_test.823846584
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/381.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/382.prim_prince_test.2162244060
Short name T388
Test name
Test status
Simulation time 2835725714 ps
CPU time 50.03 seconds
Started Sep 09 10:58:38 AM UTC 24
Finished Sep 09 10:59:40 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2162244060 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 382.prim_prince_test.2162244060
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/382.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/383.prim_prince_test.4252602145
Short name T405
Test name
Test status
Simulation time 3257809497 ps
CPU time 59.96 seconds
Started Sep 09 10:58:40 AM UTC 24
Finished Sep 09 10:59:54 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4252602145 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 383.prim_prince_test.4252602145
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/383.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/384.prim_prince_test.3636769656
Short name T387
Test name
Test status
Simulation time 2579744273 ps
CPU time 46.26 seconds
Started Sep 09 10:58:41 AM UTC 24
Finished Sep 09 10:59:38 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3636769656 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 384.prim_prince_test.3636769656
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/384.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/385.prim_prince_test.2421578673
Short name T409
Test name
Test status
Simulation time 3536214650 ps
CPU time 63.17 seconds
Started Sep 09 10:58:41 AM UTC 24
Finished Sep 09 10:59:59 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2421578673 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 385.prim_prince_test.2421578673
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/385.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/386.prim_prince_test.35430569
Short name T386
Test name
Test status
Simulation time 2517429195 ps
CPU time 44.51 seconds
Started Sep 09 10:58:41 AM UTC 24
Finished Sep 09 10:59:37 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=35430569 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 386.prim_prince_test.35430569
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/386.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/387.prim_prince_test.1336884490
Short name T365
Test name
Test status
Simulation time 1285220773 ps
CPU time 23.55 seconds
Started Sep 09 10:58:43 AM UTC 24
Finished Sep 09 10:59:13 AM UTC 24
Peak memory 154560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1336884490 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 387.prim_prince_test.1336884490
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/387.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/388.prim_prince_test.2758059197
Short name T400
Test name
Test status
Simulation time 2968260604 ps
CPU time 52.17 seconds
Started Sep 09 10:58:43 AM UTC 24
Finished Sep 09 10:59:48 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2758059197 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 388.prim_prince_test.2758059197
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/388.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/389.prim_prince_test.2760062720
Short name T383
Test name
Test status
Simulation time 2033717160 ps
CPU time 36.72 seconds
Started Sep 09 10:58:43 AM UTC 24
Finished Sep 09 10:59:29 AM UTC 24
Peak memory 154572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2760062720 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 389.prim_prince_test.2760062720
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/389.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/39.prim_prince_test.3064088855
Short name T46
Test name
Test status
Simulation time 2490997455 ps
CPU time 47.74 seconds
Started Sep 09 10:51:09 AM UTC 24
Finished Sep 09 10:52:09 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3064088855 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 39.prim_prince_test.3064088855
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/39.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/390.prim_prince_test.209912776
Short name T385
Test name
Test status
Simulation time 2194988018 ps
CPU time 39.55 seconds
Started Sep 09 10:58:45 AM UTC 24
Finished Sep 09 10:59:34 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=209912776 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 390.prim_prince_test.209912776
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/390.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/391.prim_prince_test.3726415981
Short name T397
Test name
Test status
Simulation time 2677857555 ps
CPU time 48.86 seconds
Started Sep 09 10:58:45 AM UTC 24
Finished Sep 09 10:59:45 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3726415981 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 391.prim_prince_test.3726415981
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/391.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/392.prim_prince_test.2551397452
Short name T384
Test name
Test status
Simulation time 2007179541 ps
CPU time 37.3 seconds
Started Sep 09 10:58:46 AM UTC 24
Finished Sep 09 10:59:32 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2551397452 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 392.prim_prince_test.2551397452
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/392.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/393.prim_prince_test.1841320848
Short name T392
Test name
Test status
Simulation time 2484700253 ps
CPU time 44.85 seconds
Started Sep 09 10:58:47 AM UTC 24
Finished Sep 09 10:59:43 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1841320848 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 393.prim_prince_test.1841320848
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/393.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/394.prim_prince_test.633162267
Short name T406
Test name
Test status
Simulation time 2994968948 ps
CPU time 54.95 seconds
Started Sep 09 10:58:47 AM UTC 24
Finished Sep 09 10:59:55 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=633162267 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 394.prim_prince_test.633162267
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/394.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/395.prim_prince_test.3487408802
Short name T413
Test name
Test status
Simulation time 3414077476 ps
CPU time 60.01 seconds
Started Sep 09 10:58:47 AM UTC 24
Finished Sep 09 11:00:02 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3487408802 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 395.prim_prince_test.3487408802
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/395.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/396.prim_prince_test.2323418121
Short name T377
Test name
Test status
Simulation time 3567563444 ps
CPU time 65.81 seconds
Started Sep 09 10:58:48 AM UTC 24
Finished Sep 09 11:00:10 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2323418121 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 396.prim_prince_test.2323418121
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/396.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/397.prim_prince_test.1210696249
Short name T370
Test name
Test status
Simulation time 1228519679 ps
CPU time 23.07 seconds
Started Sep 09 10:58:50 AM UTC 24
Finished Sep 09 10:59:19 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1210696249 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 397.prim_prince_test.1210696249
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/397.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/398.prim_prince_test.1210176259
Short name T425
Test name
Test status
Simulation time 3686858732 ps
CPU time 68.67 seconds
Started Sep 09 10:58:52 AM UTC 24
Finished Sep 09 11:00:16 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1210176259 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 398.prim_prince_test.1210176259
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/398.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/399.prim_prince_test.2413728120
Short name T423
Test name
Test status
Simulation time 3598320814 ps
CPU time 63.79 seconds
Started Sep 09 10:58:53 AM UTC 24
Finished Sep 09 11:00:12 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2413728120 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 399.prim_prince_test.2413728120
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/399.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/4.prim_prince_test.1595035615
Short name T30
Test name
Test status
Simulation time 3661375101 ps
CPU time 68.97 seconds
Started Sep 09 10:50:16 AM UTC 24
Finished Sep 09 10:51:44 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1595035615 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 4.prim_prince_test.1595035615
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/4.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/40.prim_prince_test.3590619632
Short name T31
Test name
Test status
Simulation time 1383452807 ps
CPU time 26.75 seconds
Started Sep 09 10:51:10 AM UTC 24
Finished Sep 09 10:51:44 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3590619632 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 40.prim_prince_test.3590619632
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/40.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/400.prim_prince_test.2871752838
Short name T376
Test name
Test status
Simulation time 1283777710 ps
CPU time 23.88 seconds
Started Sep 09 10:58:54 AM UTC 24
Finished Sep 09 10:59:24 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2871752838 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 400.prim_prince_test.2871752838
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/400.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/401.prim_prince_test.1381326506
Short name T366
Test name
Test status
Simulation time 757160657 ps
CPU time 14.53 seconds
Started Sep 09 10:58:56 AM UTC 24
Finished Sep 09 10:59:15 AM UTC 24
Peak memory 154348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1381326506 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 401.prim_prince_test.1381326506
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/401.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/402.prim_prince_test.704230259
Short name T390
Test name
Test status
Simulation time 1936733447 ps
CPU time 35.06 seconds
Started Sep 09 10:58:58 AM UTC 24
Finished Sep 09 10:59:42 AM UTC 24
Peak memory 154588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=704230259 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 402.prim_prince_test.704230259
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/402.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/403.prim_prince_test.2180319123
Short name T429
Test name
Test status
Simulation time 3740747871 ps
CPU time 66.56 seconds
Started Sep 09 10:58:58 AM UTC 24
Finished Sep 09 11:00:20 AM UTC 24
Peak memory 154644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2180319123 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 403.prim_prince_test.2180319123
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/403.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/404.prim_prince_test.671793261
Short name T419
Test name
Test status
Simulation time 3233521532 ps
CPU time 57.94 seconds
Started Sep 09 10:58:58 AM UTC 24
Finished Sep 09 11:00:09 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=671793261 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 404.prim_prince_test.671793261
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/404.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/405.prim_prince_test.4219233447
Short name T399
Test name
Test status
Simulation time 1903374679 ps
CPU time 34.84 seconds
Started Sep 09 10:59:03 AM UTC 24
Finished Sep 09 10:59:46 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4219233447 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 405.prim_prince_test.4219233447
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/405.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/406.prim_prince_test.3060007679
Short name T398
Test name
Test status
Simulation time 1819577248 ps
CPU time 34.53 seconds
Started Sep 09 10:59:03 AM UTC 24
Finished Sep 09 10:59:46 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3060007679 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 406.prim_prince_test.3060007679
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/406.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/407.prim_prince_test.2090522728
Short name T396
Test name
Test status
Simulation time 1612859225 ps
CPU time 29.63 seconds
Started Sep 09 10:59:08 AM UTC 24
Finished Sep 09 10:59:45 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2090522728 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 407.prim_prince_test.2090522728
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/407.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/408.prim_prince_test.827240201
Short name T407
Test name
Test status
Simulation time 1990040372 ps
CPU time 37.11 seconds
Started Sep 09 10:59:11 AM UTC 24
Finished Sep 09 10:59:57 AM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=827240201 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 408.prim_prince_test.827240201
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/408.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/409.prim_prince_test.3419182304
Short name T408
Test name
Test status
Simulation time 1918762074 ps
CPU time 35.82 seconds
Started Sep 09 10:59:13 AM UTC 24
Finished Sep 09 10:59:58 AM UTC 24
Peak memory 154588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3419182304 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 409.prim_prince_test.3419182304
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/409.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/41.prim_prince_test.2368420605
Short name T44
Test name
Test status
Simulation time 2360333107 ps
CPU time 44.28 seconds
Started Sep 09 10:51:11 AM UTC 24
Finished Sep 09 10:52:06 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2368420605 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 41.prim_prince_test.2368420605
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/41.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/410.prim_prince_test.740175806
Short name T436
Test name
Test status
Simulation time 3322715976 ps
CPU time 57.91 seconds
Started Sep 09 10:59:14 AM UTC 24
Finished Sep 09 11:00:27 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=740175806 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 410.prim_prince_test.740175806
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/410.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/411.prim_prince_test.551261127
Short name T421
Test name
Test status
Simulation time 2462148985 ps
CPU time 44.24 seconds
Started Sep 09 10:59:16 AM UTC 24
Finished Sep 09 11:00:11 AM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=551261127 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 411.prim_prince_test.551261127
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/411.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/412.prim_prince_test.2361158796
Short name T422
Test name
Test status
Simulation time 2370717216 ps
CPU time 43.54 seconds
Started Sep 09 10:59:17 AM UTC 24
Finished Sep 09 11:00:11 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2361158796 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 412.prim_prince_test.2361158796
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/412.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/413.prim_prince_test.831167433
Short name T430
Test name
Test status
Simulation time 2912695499 ps
CPU time 50.86 seconds
Started Sep 09 10:59:18 AM UTC 24
Finished Sep 09 11:00:21 AM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=831167433 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 413.prim_prince_test.831167433
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/413.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/414.prim_prince_test.791828499
Short name T448
Test name
Test status
Simulation time 3591944330 ps
CPU time 63.56 seconds
Started Sep 09 10:59:19 AM UTC 24
Finished Sep 09 11:00:38 AM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=791828499 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 414.prim_prince_test.791828499
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/414.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/415.prim_prince_test.2295772033
Short name T402
Test name
Test status
Simulation time 1272652548 ps
CPU time 23.71 seconds
Started Sep 09 10:59:19 AM UTC 24
Finished Sep 09 10:59:49 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2295772033 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 415.prim_prince_test.2295772033
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/415.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/416.prim_prince_test.2219829492
Short name T450
Test name
Test status
Simulation time 3750903422 ps
CPU time 65.51 seconds
Started Sep 09 10:59:20 AM UTC 24
Finished Sep 09 11:00:42 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2219829492 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 416.prim_prince_test.2219829492
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/416.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/417.prim_prince_test.2644303931
Short name T410
Test name
Test status
Simulation time 1622117259 ps
CPU time 30.48 seconds
Started Sep 09 10:59:21 AM UTC 24
Finished Sep 09 11:00:00 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2644303931 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 417.prim_prince_test.2644303931
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/417.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/418.prim_prince_test.161184010
Short name T416
Test name
Test status
Simulation time 1982724055 ps
CPU time 35.71 seconds
Started Sep 09 10:59:23 AM UTC 24
Finished Sep 09 11:00:07 AM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=161184010 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 418.prim_prince_test.161184010
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/418.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/419.prim_prince_test.365141418
Short name T395
Test name
Test status
Simulation time 965226891 ps
CPU time 17.2 seconds
Started Sep 09 10:59:23 AM UTC 24
Finished Sep 09 10:59:45 AM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=365141418 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 419.prim_prince_test.365141418
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/419.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/42.prim_prince_test.223056272
Short name T72
Test name
Test status
Simulation time 3711867475 ps
CPU time 70.37 seconds
Started Sep 09 10:51:14 AM UTC 24
Finished Sep 09 10:52:41 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=223056272 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 42.prim_prince_test.223056272
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/42.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/420.prim_prince_test.2450178717
Short name T412
Test name
Test status
Simulation time 1566196340 ps
CPU time 29.41 seconds
Started Sep 09 10:59:25 AM UTC 24
Finished Sep 09 11:00:02 AM UTC 24
Peak memory 154508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2450178717 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 420.prim_prince_test.2450178717
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/420.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/421.prim_prince_test.3072027897
Short name T417
Test name
Test status
Simulation time 1902323705 ps
CPU time 34.18 seconds
Started Sep 09 10:59:25 AM UTC 24
Finished Sep 09 11:00:08 AM UTC 24
Peak memory 154476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3072027897 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 421.prim_prince_test.3072027897
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/421.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/422.prim_prince_test.690876616
Short name T393
Test name
Test status
Simulation time 769850073 ps
CPU time 14.35 seconds
Started Sep 09 10:59:25 AM UTC 24
Finished Sep 09 10:59:44 AM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=690876616 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 422.prim_prince_test.690876616
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/422.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/423.prim_prince_test.1279676240
Short name T442
Test name
Test status
Simulation time 2986244464 ps
CPU time 54.42 seconds
Started Sep 09 10:59:25 AM UTC 24
Finished Sep 09 11:00:33 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1279676240 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 423.prim_prince_test.1279676240
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/423.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/424.prim_prince_test.432144669
Short name T427
Test name
Test status
Simulation time 2339850715 ps
CPU time 41.98 seconds
Started Sep 09 10:59:26 AM UTC 24
Finished Sep 09 11:00:18 AM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=432144669 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 424.prim_prince_test.432144669
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/424.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/425.prim_prince_test.4183901933
Short name T415
Test name
Test status
Simulation time 1525588828 ps
CPU time 27.89 seconds
Started Sep 09 10:59:29 AM UTC 24
Finished Sep 09 11:00:04 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4183901933 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 425.prim_prince_test.4183901933
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/425.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/426.prim_prince_test.3797102155
Short name T401
Test name
Test status
Simulation time 842842402 ps
CPU time 15.35 seconds
Started Sep 09 10:59:29 AM UTC 24
Finished Sep 09 10:59:48 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3797102155 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 426.prim_prince_test.3797102155
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/426.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/427.prim_prince_test.3660240504
Short name T431
Test name
Test status
Simulation time 2363031199 ps
CPU time 42.13 seconds
Started Sep 09 10:59:30 AM UTC 24
Finished Sep 09 11:00:23 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3660240504 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 427.prim_prince_test.3660240504
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/427.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/428.prim_prince_test.3604194230
Short name T435
Test name
Test status
Simulation time 2315821152 ps
CPU time 42.4 seconds
Started Sep 09 10:59:33 AM UTC 24
Finished Sep 09 11:00:26 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3604194230 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 428.prim_prince_test.3604194230
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/428.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/429.prim_prince_test.514264501
Short name T452
Test name
Test status
Simulation time 3222716866 ps
CPU time 57.03 seconds
Started Sep 09 10:59:35 AM UTC 24
Finished Sep 09 11:00:46 AM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=514264501 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 429.prim_prince_test.514264501
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/429.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/43.prim_prince_test.2942385323
Short name T51
Test name
Test status
Simulation time 2551648523 ps
CPU time 48.37 seconds
Started Sep 09 10:51:15 AM UTC 24
Finished Sep 09 10:52:15 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2942385323 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 43.prim_prince_test.2942385323
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/43.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/430.prim_prince_test.643818370
Short name T418
Test name
Test status
Simulation time 1419431184 ps
CPU time 24.9 seconds
Started Sep 09 10:59:37 AM UTC 24
Finished Sep 09 11:00:09 AM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=643818370 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 430.prim_prince_test.643818370
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/430.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/431.prim_prince_test.2844793057
Short name T414
Test name
Test status
Simulation time 1058592576 ps
CPU time 19.05 seconds
Started Sep 09 10:59:39 AM UTC 24
Finished Sep 09 11:00:03 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2844793057 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 431.prim_prince_test.2844793057
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/431.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/432.prim_prince_test.1748269698
Short name T441
Test name
Test status
Simulation time 2273002861 ps
CPU time 41.52 seconds
Started Sep 09 10:59:41 AM UTC 24
Finished Sep 09 11:00:32 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1748269698 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 432.prim_prince_test.1748269698
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/432.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/433.prim_prince_test.463503718
Short name T411
Test name
Test status
Simulation time 804272782 ps
CPU time 14.18 seconds
Started Sep 09 10:59:43 AM UTC 24
Finished Sep 09 11:00:01 AM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=463503718 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 433.prim_prince_test.463503718
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/433.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/434.prim_prince_test.63624063
Short name T461
Test name
Test status
Simulation time 3047014394 ps
CPU time 55.3 seconds
Started Sep 09 10:59:43 AM UTC 24
Finished Sep 09 11:00:51 AM UTC 24
Peak memory 154660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=63624063 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 434.prim_prince_test.63624063
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/434.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/435.prim_prince_test.3496960081
Short name T428
Test name
Test status
Simulation time 1597212103 ps
CPU time 27.92 seconds
Started Sep 09 10:59:44 AM UTC 24
Finished Sep 09 11:00:19 AM UTC 24
Peak memory 154432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3496960081 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 435.prim_prince_test.3496960081
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/435.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/436.prim_prince_test.4018113818
Short name T434
Test name
Test status
Simulation time 1882547327 ps
CPU time 33.28 seconds
Started Sep 09 10:59:44 AM UTC 24
Finished Sep 09 11:00:26 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4018113818 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 436.prim_prince_test.4018113818
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/436.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/437.prim_prince_test.947259597
Short name T420
Test name
Test status
Simulation time 1087393684 ps
CPU time 19.93 seconds
Started Sep 09 10:59:45 AM UTC 24
Finished Sep 09 11:00:11 AM UTC 24
Peak memory 154604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=947259597 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 437.prim_prince_test.947259597
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/437.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/438.prim_prince_test.2052952562
Short name T455
Test name
Test status
Simulation time 2779764134 ps
CPU time 50.37 seconds
Started Sep 09 10:59:45 AM UTC 24
Finished Sep 09 11:00:48 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2052952562 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 438.prim_prince_test.2052952562
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/438.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/439.prim_prince_test.2954143550
Short name T469
Test name
Test status
Simulation time 3294246369 ps
CPU time 61.25 seconds
Started Sep 09 10:59:46 AM UTC 24
Finished Sep 09 11:01:01 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2954143550 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 439.prim_prince_test.2954143550
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/439.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/44.prim_prince_test.1033262554
Short name T75
Test name
Test status
Simulation time 3688780947 ps
CPU time 69.32 seconds
Started Sep 09 10:51:16 AM UTC 24
Finished Sep 09 10:52:42 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1033262554 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 44.prim_prince_test.1033262554
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/44.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/440.prim_prince_test.1491531064
Short name T437
Test name
Test status
Simulation time 1799165371 ps
CPU time 32.35 seconds
Started Sep 09 10:59:47 AM UTC 24
Finished Sep 09 11:00:27 AM UTC 24
Peak memory 154272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1491531064 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 440.prim_prince_test.1491531064
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/440.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/441.prim_prince_test.2286308695
Short name T424
Test name
Test status
Simulation time 1245397909 ps
CPU time 22.67 seconds
Started Sep 09 10:59:47 AM UTC 24
Finished Sep 09 11:00:16 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2286308695 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 441.prim_prince_test.2286308695
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/441.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/442.prim_prince_test.2987637868
Short name T426
Test name
Test status
Simulation time 1325084093 ps
CPU time 23.76 seconds
Started Sep 09 10:59:47 AM UTC 24
Finished Sep 09 11:00:17 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2987637868 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 442.prim_prince_test.2987637868
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/442.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/443.prim_prince_test.4063698325
Short name T451
Test name
Test status
Simulation time 2621554847 ps
CPU time 46.59 seconds
Started Sep 09 10:59:47 AM UTC 24
Finished Sep 09 11:00:45 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4063698325 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 443.prim_prince_test.4063698325
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/443.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/444.prim_prince_test.1739313367
Short name T444
Test name
Test status
Simulation time 2033921697 ps
CPU time 36.53 seconds
Started Sep 09 10:59:49 AM UTC 24
Finished Sep 09 11:00:35 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1739313367 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 444.prim_prince_test.1739313367
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/444.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/445.prim_prince_test.3397861527
Short name T457
Test name
Test status
Simulation time 2664364752 ps
CPU time 48.58 seconds
Started Sep 09 10:59:50 AM UTC 24
Finished Sep 09 11:00:50 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3397861527 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 445.prim_prince_test.3397861527
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/445.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/446.prim_prince_test.3240881889
Short name T462
Test name
Test status
Simulation time 2759724538 ps
CPU time 51.96 seconds
Started Sep 09 10:59:51 AM UTC 24
Finished Sep 09 11:00:55 AM UTC 24
Peak memory 154656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3240881889 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 446.prim_prince_test.3240881889
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/446.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/447.prim_prince_test.2245784060
Short name T433
Test name
Test status
Simulation time 1425772121 ps
CPU time 26.17 seconds
Started Sep 09 10:59:52 AM UTC 24
Finished Sep 09 11:00:25 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2245784060 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 447.prim_prince_test.2245784060
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/447.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/448.prim_prince_test.1411141705
Short name T439
Test name
Test status
Simulation time 1604275787 ps
CPU time 29.91 seconds
Started Sep 09 10:59:54 AM UTC 24
Finished Sep 09 11:00:31 AM UTC 24
Peak memory 154592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1411141705 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 448.prim_prince_test.1411141705
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/448.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/449.prim_prince_test.468058042
Short name T475
Test name
Test status
Simulation time 3328049223 ps
CPU time 61.52 seconds
Started Sep 09 10:59:54 AM UTC 24
Finished Sep 09 11:01:10 AM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=468058042 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 449.prim_prince_test.468058042
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/449.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/45.prim_prince_test.3894489577
Short name T32
Test name
Test status
Simulation time 1197861542 ps
CPU time 22.82 seconds
Started Sep 09 10:51:16 AM UTC 24
Finished Sep 09 10:51:45 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3894489577 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 45.prim_prince_test.3894489577
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/45.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/450.prim_prince_test.1001150312
Short name T463
Test name
Test status
Simulation time 2691296631 ps
CPU time 47.53 seconds
Started Sep 09 10:59:56 AM UTC 24
Finished Sep 09 11:00:56 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1001150312 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 450.prim_prince_test.1001150312
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/450.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/451.prim_prince_test.3822437527
Short name T474
Test name
Test status
Simulation time 3256661423 ps
CPU time 57.41 seconds
Started Sep 09 10:59:58 AM UTC 24
Finished Sep 09 11:01:10 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3822437527 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 451.prim_prince_test.3822437527
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/451.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/452.prim_prince_test.1865110202
Short name T440
Test name
Test status
Simulation time 1421973517 ps
CPU time 25.35 seconds
Started Sep 09 11:00:00 AM UTC 24
Finished Sep 09 11:00:32 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1865110202 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 452.prim_prince_test.1865110202
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/452.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/453.prim_prince_test.3028701915
Short name T485
Test name
Test status
Simulation time 3701851252 ps
CPU time 66.49 seconds
Started Sep 09 11:00:01 AM UTC 24
Finished Sep 09 11:01:27 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3028701915 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 453.prim_prince_test.3028701915
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/453.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/454.prim_prince_test.337878176
Short name T438
Test name
Test status
Simulation time 1143163823 ps
CPU time 20.83 seconds
Started Sep 09 11:00:01 AM UTC 24
Finished Sep 09 11:00:31 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=337878176 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 454.prim_prince_test.337878176
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/454.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/455.prim_prince_test.2594313128
Short name T483
Test name
Test status
Simulation time 3454705181 ps
CPU time 64.33 seconds
Started Sep 09 11:00:02 AM UTC 24
Finished Sep 09 11:01:25 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2594313128 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 455.prim_prince_test.2594313128
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/455.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/456.prim_prince_test.701985509
Short name T432
Test name
Test status
Simulation time 781401889 ps
CPU time 14.07 seconds
Started Sep 09 11:00:02 AM UTC 24
Finished Sep 09 11:00:24 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=701985509 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 456.prim_prince_test.701985509
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/456.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/457.prim_prince_test.3012469982
Short name T456
Test name
Test status
Simulation time 1904829962 ps
CPU time 34.39 seconds
Started Sep 09 11:00:02 AM UTC 24
Finished Sep 09 11:00:48 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3012469982 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 457.prim_prince_test.3012469982
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/457.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/458.prim_prince_test.2398591022
Short name T446
Test name
Test status
Simulation time 1351332188 ps
CPU time 24.86 seconds
Started Sep 09 11:00:07 AM UTC 24
Finished Sep 09 11:00:38 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2398591022 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 458.prim_prince_test.2398591022
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/458.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/459.prim_prince_test.2130958659
Short name T479
Test name
Test status
Simulation time 3216514731 ps
CPU time 56.88 seconds
Started Sep 09 11:00:07 AM UTC 24
Finished Sep 09 11:01:18 AM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2130958659 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 459.prim_prince_test.2130958659
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/459.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/46.prim_prince_test.1953332932
Short name T33
Test name
Test status
Simulation time 1213825909 ps
CPU time 22.32 seconds
Started Sep 09 10:51:17 AM UTC 24
Finished Sep 09 10:51:45 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1953332932 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 46.prim_prince_test.1953332932
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/46.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/460.prim_prince_test.1964227143
Short name T443
Test name
Test status
Simulation time 1179623430 ps
CPU time 21.25 seconds
Started Sep 09 11:00:08 AM UTC 24
Finished Sep 09 11:00:35 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1964227143 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 460.prim_prince_test.1964227143
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/460.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/461.prim_prince_test.1309493855
Short name T465
Test name
Test status
Simulation time 2075995087 ps
CPU time 39.09 seconds
Started Sep 09 11:00:09 AM UTC 24
Finished Sep 09 11:00:58 AM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1309493855 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 461.prim_prince_test.1309493855
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/461.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/462.prim_prince_test.1807157465
Short name T484
Test name
Test status
Simulation time 3380965401 ps
CPU time 61.32 seconds
Started Sep 09 11:00:09 AM UTC 24
Finished Sep 09 11:01:26 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1807157465 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 462.prim_prince_test.1807157465
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/462.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/463.prim_prince_test.3058315136
Short name T487
Test name
Test status
Simulation time 3345989955 ps
CPU time 63.39 seconds
Started Sep 09 11:00:10 AM UTC 24
Finished Sep 09 11:01:29 AM UTC 24
Peak memory 154580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3058315136 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 463.prim_prince_test.3058315136
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/463.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/464.prim_prince_test.3938982526
Short name T453
Test name
Test status
Simulation time 1589007541 ps
CPU time 29 seconds
Started Sep 09 11:00:10 AM UTC 24
Finished Sep 09 11:00:47 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3938982526 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 464.prim_prince_test.3938982526
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/464.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/465.prim_prince_test.1284803123
Short name T445
Test name
Test status
Simulation time 1082285017 ps
CPU time 20.58 seconds
Started Sep 09 11:00:12 AM UTC 24
Finished Sep 09 11:00:38 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1284803123 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 465.prim_prince_test.1284803123
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/465.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/466.prim_prince_test.658591708
Short name T447
Test name
Test status
Simulation time 1129460094 ps
CPU time 20.57 seconds
Started Sep 09 11:00:12 AM UTC 24
Finished Sep 09 11:00:38 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=658591708 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 466.prim_prince_test.658591708
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/466.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/467.prim_prince_test.1618270310
Short name T459
Test name
Test status
Simulation time 1693551188 ps
CPU time 30.92 seconds
Started Sep 09 11:00:12 AM UTC 24
Finished Sep 09 11:00:51 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1618270310 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 467.prim_prince_test.1618270310
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/467.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/468.prim_prince_test.1207599932
Short name T468
Test name
Test status
Simulation time 2084098237 ps
CPU time 36.88 seconds
Started Sep 09 11:00:13 AM UTC 24
Finished Sep 09 11:00:59 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1207599932 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 468.prim_prince_test.1207599932
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/468.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/469.prim_prince_test.931655288
Short name T489
Test name
Test status
Simulation time 3461533644 ps
CPU time 63.04 seconds
Started Sep 09 11:00:16 AM UTC 24
Finished Sep 09 11:01:35 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=931655288 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 469.prim_prince_test.931655288
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/469.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/47.prim_prince_test.324671518
Short name T35
Test name
Test status
Simulation time 1313541886 ps
CPU time 24.64 seconds
Started Sep 09 10:51:19 AM UTC 24
Finished Sep 09 10:51:50 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=324671518 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 47.prim_prince_test.324671518
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/47.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/470.prim_prince_test.3733320815
Short name T466
Test name
Test status
Simulation time 1827384555 ps
CPU time 32.57 seconds
Started Sep 09 11:00:18 AM UTC 24
Finished Sep 09 11:00:58 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3733320815 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 470.prim_prince_test.3733320815
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/470.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/471.prim_prince_test.2771861490
Short name T480
Test name
Test status
Simulation time 2710219258 ps
CPU time 50.96 seconds
Started Sep 09 11:00:18 AM UTC 24
Finished Sep 09 11:01:21 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2771861490 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 471.prim_prince_test.2771861490
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/471.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/472.prim_prince_test.2149777713
Short name T488
Test name
Test status
Simulation time 3004579943 ps
CPU time 56.2 seconds
Started Sep 09 11:00:20 AM UTC 24
Finished Sep 09 11:01:30 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2149777713 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 472.prim_prince_test.2149777713
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/472.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/473.prim_prince_test.2267601122
Short name T464
Test name
Test status
Simulation time 1592261770 ps
CPU time 28.73 seconds
Started Sep 09 11:00:20 AM UTC 24
Finished Sep 09 11:00:56 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2267601122 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 473.prim_prince_test.2267601122
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/473.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/474.prim_prince_test.1981324053
Short name T449
Test name
Test status
Simulation time 885853985 ps
CPU time 16.19 seconds
Started Sep 09 11:00:21 AM UTC 24
Finished Sep 09 11:00:42 AM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1981324053 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 474.prim_prince_test.1981324053
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/474.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/475.prim_prince_test.739230091
Short name T460
Test name
Test status
Simulation time 1232143258 ps
CPU time 22.98 seconds
Started Sep 09 11:00:22 AM UTC 24
Finished Sep 09 11:00:51 AM UTC 24
Peak memory 154596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=739230091 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 475.prim_prince_test.739230091
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/475.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/476.prim_prince_test.846913011
Short name T481
Test name
Test status
Simulation time 2621712076 ps
CPU time 48.15 seconds
Started Sep 09 11:00:23 AM UTC 24
Finished Sep 09 11:01:23 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=846913011 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 476.prim_prince_test.846913011
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/476.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/477.prim_prince_test.3716669704
Short name T491
Test name
Test status
Simulation time 3194121943 ps
CPU time 57.37 seconds
Started Sep 09 11:00:25 AM UTC 24
Finished Sep 09 11:01:36 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3716669704 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 477.prim_prince_test.3716669704
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/477.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/478.prim_prince_test.1483606940
Short name T473
Test name
Test status
Simulation time 1935503994 ps
CPU time 34.8 seconds
Started Sep 09 11:00:26 AM UTC 24
Finished Sep 09 11:01:09 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1483606940 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 478.prim_prince_test.1483606940
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/478.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/479.prim_prince_test.3439793489
Short name T472
Test name
Test status
Simulation time 1835348846 ps
CPU time 31.93 seconds
Started Sep 09 11:00:27 AM UTC 24
Finished Sep 09 11:01:07 AM UTC 24
Peak memory 154608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3439793489 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 479.prim_prince_test.3439793489
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/479.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/48.prim_prince_test.3928197866
Short name T50
Test name
Test status
Simulation time 2247341632 ps
CPU time 41.94 seconds
Started Sep 09 10:51:20 AM UTC 24
Finished Sep 09 10:52:12 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3928197866 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 48.prim_prince_test.3928197866
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/48.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/480.prim_prince_test.724883287
Short name T467
Test name
Test status
Simulation time 1418619819 ps
CPU time 25.38 seconds
Started Sep 09 11:00:27 AM UTC 24
Finished Sep 09 11:00:59 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=724883287 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 480.prim_prince_test.724883287
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/480.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/481.prim_prince_test.3098221857
Short name T495
Test name
Test status
Simulation time 3618206447 ps
CPU time 68.02 seconds
Started Sep 09 11:00:28 AM UTC 24
Finished Sep 09 11:01:53 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3098221857 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 481.prim_prince_test.3098221857
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/481.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/482.prim_prince_test.1042312220
Short name T454
Test name
Test status
Simulation time 814466103 ps
CPU time 14.98 seconds
Started Sep 09 11:00:28 AM UTC 24
Finished Sep 09 11:00:47 AM UTC 24
Peak memory 154352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1042312220 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 482.prim_prince_test.1042312220
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/482.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/483.prim_prince_test.2169433006
Short name T458
Test name
Test status
Simulation time 761607303 ps
CPU time 14.26 seconds
Started Sep 09 11:00:32 AM UTC 24
Finished Sep 09 11:00:50 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2169433006 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 483.prim_prince_test.2169433006
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/483.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/484.prim_prince_test.2092430609
Short name T482
Test name
Test status
Simulation time 2281908791 ps
CPU time 41 seconds
Started Sep 09 11:00:33 AM UTC 24
Finished Sep 09 11:01:25 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2092430609 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 484.prim_prince_test.2092430609
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/484.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/485.prim_prince_test.1984893668
Short name T493
Test name
Test status
Simulation time 3163341125 ps
CPU time 59.03 seconds
Started Sep 09 11:00:33 AM UTC 24
Finished Sep 09 11:01:48 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1984893668 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 485.prim_prince_test.1984893668
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/485.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/486.prim_prince_test.1473107473
Short name T494
Test name
Test status
Simulation time 3336350787 ps
CPU time 61.22 seconds
Started Sep 09 11:00:33 AM UTC 24
Finished Sep 09 11:01:50 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1473107473 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 486.prim_prince_test.1473107473
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/486.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/487.prim_prince_test.1253511248
Short name T470
Test name
Test status
Simulation time 1204960408 ps
CPU time 22.12 seconds
Started Sep 09 11:00:34 AM UTC 24
Finished Sep 09 11:01:02 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1253511248 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 487.prim_prince_test.1253511248
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/487.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/488.prim_prince_test.1085135471
Short name T492
Test name
Test status
Simulation time 2640521849 ps
CPU time 49.04 seconds
Started Sep 09 11:00:35 AM UTC 24
Finished Sep 09 11:01:37 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1085135471 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 488.prim_prince_test.1085135471
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/488.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/489.prim_prince_test.2430412806
Short name T478
Test name
Test status
Simulation time 1790177183 ps
CPU time 32.4 seconds
Started Sep 09 11:00:37 AM UTC 24
Finished Sep 09 11:01:18 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2430412806 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 489.prim_prince_test.2430412806
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/489.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/49.prim_prince_test.1509202624
Short name T60
Test name
Test status
Simulation time 2833700936 ps
CPU time 54.19 seconds
Started Sep 09 10:51:20 AM UTC 24
Finished Sep 09 10:52:27 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1509202624 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 49.prim_prince_test.1509202624
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/49.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/490.prim_prince_test.4014313381
Short name T498
Test name
Test status
Simulation time 3383871391 ps
CPU time 65.8 seconds
Started Sep 09 11:00:39 AM UTC 24
Finished Sep 09 11:02:02 AM UTC 24
Peak memory 154612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4014313381 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 490.prim_prince_test.4014313381
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/490.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/491.prim_prince_test.915236189
Short name T490
Test name
Test status
Simulation time 2434159484 ps
CPU time 44.38 seconds
Started Sep 09 11:00:39 AM UTC 24
Finished Sep 09 11:01:35 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=915236189 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 491.prim_prince_test.915236189
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/491.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/492.prim_prince_test.2207922658
Short name T499
Test name
Test status
Simulation time 3511528918 ps
CPU time 69.08 seconds
Started Sep 09 11:00:39 AM UTC 24
Finished Sep 09 11:02:07 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2207922658 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 492.prim_prince_test.2207922658
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/492.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/493.prim_prince_test.3788133412
Short name T486
Test name
Test status
Simulation time 2105515754 ps
CPU time 37.96 seconds
Started Sep 09 11:00:39 AM UTC 24
Finished Sep 09 11:01:27 AM UTC 24
Peak memory 154520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3788133412 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 493.prim_prince_test.3788133412
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/493.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/494.prim_prince_test.3659798570
Short name T471
Test name
Test status
Simulation time 826760974 ps
CPU time 15.63 seconds
Started Sep 09 11:00:43 AM UTC 24
Finished Sep 09 11:01:03 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3659798570 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 494.prim_prince_test.3659798570
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/494.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/495.prim_prince_test.748576202
Short name T496
Test name
Test status
Simulation time 3094900271 ps
CPU time 60.19 seconds
Started Sep 09 11:00:43 AM UTC 24
Finished Sep 09 11:01:58 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=748576202 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 495.prim_prince_test.748576202
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/495.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/496.prim_prince_test.3537995902
Short name T477
Test name
Test status
Simulation time 1086293068 ps
CPU time 20.28 seconds
Started Sep 09 11:00:46 AM UTC 24
Finished Sep 09 11:01:12 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3537995902 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 496.prim_prince_test.3537995902
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/496.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/497.prim_prince_test.4013942745
Short name T497
Test name
Test status
Simulation time 2994491938 ps
CPU time 57.61 seconds
Started Sep 09 11:00:47 AM UTC 24
Finished Sep 09 11:02:00 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4013942745 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 497.prim_prince_test.4013942745
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/497.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/498.prim_prince_test.3607106909
Short name T476
Test name
Test status
Simulation time 966750004 ps
CPU time 17.67 seconds
Started Sep 09 11:00:48 AM UTC 24
Finished Sep 09 11:01:11 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3607106909 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 498.prim_prince_test.3607106909
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/498.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/499.prim_prince_test.1045385426
Short name T500
Test name
Test status
Simulation time 3690288824 ps
CPU time 74.11 seconds
Started Sep 09 11:00:48 AM UTC 24
Finished Sep 09 11:02:22 AM UTC 24
Peak memory 154672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1045385426 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 499.prim_prince_test.1045385426
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/499.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/5.prim_prince_test.3044654161
Short name T1
Test name
Test status
Simulation time 788527274 ps
CPU time 15.05 seconds
Started Sep 09 10:50:17 AM UTC 24
Finished Sep 09 10:50:37 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3044654161 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 5.prim_prince_test.3044654161
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/5.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/50.prim_prince_test.1452719371
Short name T56
Test name
Test status
Simulation time 2720024008 ps
CPU time 49.69 seconds
Started Sep 09 10:51:22 AM UTC 24
Finished Sep 09 10:52:24 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1452719371 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 50.prim_prince_test.1452719371
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/50.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/51.prim_prince_test.3936733167
Short name T66
Test name
Test status
Simulation time 3108717294 ps
CPU time 56.92 seconds
Started Sep 09 10:51:23 AM UTC 24
Finished Sep 09 10:52:35 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3936733167 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 51.prim_prince_test.3936733167
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/51.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/52.prim_prince_test.1096843817
Short name T54
Test name
Test status
Simulation time 2349805097 ps
CPU time 43.56 seconds
Started Sep 09 10:51:26 AM UTC 24
Finished Sep 09 10:52:21 AM UTC 24
Peak memory 156120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1096843817 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 52.prim_prince_test.1096843817
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/52.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/53.prim_prince_test.2520294257
Short name T77
Test name
Test status
Simulation time 3478808053 ps
CPU time 64.79 seconds
Started Sep 09 10:51:28 AM UTC 24
Finished Sep 09 10:52:49 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2520294257 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 53.prim_prince_test.2520294257
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/53.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/54.prim_prince_test.3779319469
Short name T40
Test name
Test status
Simulation time 1148019265 ps
CPU time 21.38 seconds
Started Sep 09 10:51:30 AM UTC 24
Finished Sep 09 10:51:57 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3779319469 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 54.prim_prince_test.3779319469
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/54.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/55.prim_prince_test.2098002484
Short name T63
Test name
Test status
Simulation time 2402640636 ps
CPU time 46.15 seconds
Started Sep 09 10:51:31 AM UTC 24
Finished Sep 09 10:52:29 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2098002484 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 55.prim_prince_test.2098002484
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/55.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/56.prim_prince_test.2078825124
Short name T65
Test name
Test status
Simulation time 2556145705 ps
CPU time 46.77 seconds
Started Sep 09 10:51:33 AM UTC 24
Finished Sep 09 10:52:32 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2078825124 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 56.prim_prince_test.2078825124
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/56.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/57.prim_prince_test.2337251348
Short name T55
Test name
Test status
Simulation time 1943315581 ps
CPU time 36.17 seconds
Started Sep 09 10:51:36 AM UTC 24
Finished Sep 09 10:52:21 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2337251348 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 57.prim_prince_test.2337251348
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/57.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/58.prim_prince_test.2700819389
Short name T41
Test name
Test status
Simulation time 1098132083 ps
CPU time 20.6 seconds
Started Sep 09 10:51:37 AM UTC 24
Finished Sep 09 10:52:03 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2700819389 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 58.prim_prince_test.2700819389
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/58.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/59.prim_prince_test.256057492
Short name T58
Test name
Test status
Simulation time 1981840027 ps
CPU time 36.56 seconds
Started Sep 09 10:51:39 AM UTC 24
Finished Sep 09 10:52:25 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=256057492 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 59.prim_prince_test.256057492
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/59.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/6.prim_prince_test.49885207
Short name T23
Test name
Test status
Simulation time 3375300461 ps
CPU time 62.08 seconds
Started Sep 09 10:50:17 AM UTC 24
Finished Sep 09 10:51:35 AM UTC 24
Peak memory 154668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=49885207 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 6.prim_prince_test.49885207
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/6.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/60.prim_prince_test.2075706860
Short name T47
Test name
Test status
Simulation time 1390056469 ps
CPU time 26.11 seconds
Started Sep 09 10:51:39 AM UTC 24
Finished Sep 09 10:52:12 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2075706860 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 60.prim_prince_test.2075706860
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/60.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/61.prim_prince_test.2844879377
Short name T59
Test name
Test status
Simulation time 1932197789 ps
CPU time 35.65 seconds
Started Sep 09 10:51:42 AM UTC 24
Finished Sep 09 10:52:27 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2844879377 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 61.prim_prince_test.2844879377
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/61.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/62.prim_prince_test.3692805073
Short name T83
Test name
Test status
Simulation time 3330603780 ps
CPU time 61.21 seconds
Started Sep 09 10:51:43 AM UTC 24
Finished Sep 09 10:52:59 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3692805073 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 62.prim_prince_test.3692805073
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/62.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/63.prim_prince_test.2582983069
Short name T90
Test name
Test status
Simulation time 3635148968 ps
CPU time 65.91 seconds
Started Sep 09 10:51:43 AM UTC 24
Finished Sep 09 10:53:05 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2582983069 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 63.prim_prince_test.2582983069
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/63.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/64.prim_prince_test.3755122819
Short name T45
Test name
Test status
Simulation time 989576386 ps
CPU time 19.08 seconds
Started Sep 09 10:51:44 AM UTC 24
Finished Sep 09 10:52:08 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3755122819 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 64.prim_prince_test.3755122819
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/64.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/65.prim_prince_test.152065581
Short name T73
Test name
Test status
Simulation time 2412288700 ps
CPU time 44.98 seconds
Started Sep 09 10:51:45 AM UTC 24
Finished Sep 09 10:52:41 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=152065581 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 65.prim_prince_test.152065581
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/65.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/66.prim_prince_test.3128850499
Short name T88
Test name
Test status
Simulation time 3366783599 ps
CPU time 62.34 seconds
Started Sep 09 10:51:46 AM UTC 24
Finished Sep 09 10:53:04 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3128850499 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 66.prim_prince_test.3128850499
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/66.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/67.prim_prince_test.3025838755
Short name T61
Test name
Test status
Simulation time 1763403416 ps
CPU time 33.31 seconds
Started Sep 09 10:51:46 AM UTC 24
Finished Sep 09 10:52:28 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3025838755 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 67.prim_prince_test.3025838755
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/67.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/68.prim_prince_test.3500707410
Short name T53
Test name
Test status
Simulation time 1176501802 ps
CPU time 23.26 seconds
Started Sep 09 10:51:48 AM UTC 24
Finished Sep 09 10:52:17 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3500707410 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 68.prim_prince_test.3500707410
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/68.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/69.prim_prince_test.1406786353
Short name T76
Test name
Test status
Simulation time 2232028233 ps
CPU time 41.47 seconds
Started Sep 09 10:51:51 AM UTC 24
Finished Sep 09 10:52:43 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1406786353 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 69.prim_prince_test.1406786353
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/69.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/7.prim_prince_test.3066617220
Short name T29
Test name
Test status
Simulation time 3617377416 ps
CPU time 67.11 seconds
Started Sep 09 10:50:17 AM UTC 24
Finished Sep 09 10:51:42 AM UTC 24
Peak memory 154636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3066617220 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 7.prim_prince_test.3066617220
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/7.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/70.prim_prince_test.2684818167
Short name T48
Test name
Test status
Simulation time 763189319 ps
CPU time 14.44 seconds
Started Sep 09 10:51:53 AM UTC 24
Finished Sep 09 10:52:12 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2684818167 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 70.prim_prince_test.2684818167
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/70.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/71.prim_prince_test.3051788887
Short name T67
Test name
Test status
Simulation time 1765863393 ps
CPU time 33.31 seconds
Started Sep 09 10:51:53 AM UTC 24
Finished Sep 09 10:52:35 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3051788887 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 71.prim_prince_test.3051788887
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/71.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/72.prim_prince_test.1032699402
Short name T79
Test name
Test status
Simulation time 2469386225 ps
CPU time 46.36 seconds
Started Sep 09 10:51:55 AM UTC 24
Finished Sep 09 10:52:53 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1032699402 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 72.prim_prince_test.1032699402
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/72.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/73.prim_prince_test.2304056439
Short name T64
Test name
Test status
Simulation time 1397732559 ps
CPU time 26.35 seconds
Started Sep 09 10:51:56 AM UTC 24
Finished Sep 09 10:52:30 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2304056439 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 73.prim_prince_test.2304056439
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/73.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/74.prim_prince_test.802580473
Short name T98
Test name
Test status
Simulation time 3447676054 ps
CPU time 64.12 seconds
Started Sep 09 10:51:58 AM UTC 24
Finished Sep 09 10:53:18 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=802580473 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 74.prim_prince_test.802580473
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/74.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/75.prim_prince_test.3320420613
Short name T57
Test name
Test status
Simulation time 852847633 ps
CPU time 16.63 seconds
Started Sep 09 10:52:03 AM UTC 24
Finished Sep 09 10:52:25 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3320420613 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 75.prim_prince_test.3320420613
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/75.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/76.prim_prince_test.559869983
Short name T94
Test name
Test status
Simulation time 2793720126 ps
CPU time 50.49 seconds
Started Sep 09 10:52:05 AM UTC 24
Finished Sep 09 10:53:08 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=559869983 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 76.prim_prince_test.559869983
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/76.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/77.prim_prince_test.2229271065
Short name T109
Test name
Test status
Simulation time 3721467295 ps
CPU time 70.69 seconds
Started Sep 09 10:52:07 AM UTC 24
Finished Sep 09 10:53:34 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2229271065 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 77.prim_prince_test.2229271065
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/77.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/78.prim_prince_test.2763244967
Short name T62
Test name
Test status
Simulation time 895630711 ps
CPU time 17.06 seconds
Started Sep 09 10:52:07 AM UTC 24
Finished Sep 09 10:52:28 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2763244967 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 78.prim_prince_test.2763244967
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/78.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/79.prim_prince_test.1804985304
Short name T69
Test name
Test status
Simulation time 1148609650 ps
CPU time 20.98 seconds
Started Sep 09 10:52:09 AM UTC 24
Finished Sep 09 10:52:36 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1804985304 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 79.prim_prince_test.1804985304
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/79.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/8.prim_prince_test.3540807519
Short name T16
Test name
Test status
Simulation time 2523571330 ps
CPU time 48.9 seconds
Started Sep 09 10:50:17 AM UTC 24
Finished Sep 09 10:51:19 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3540807519 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 8.prim_prince_test.3540807519
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/8.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/80.prim_prince_test.2271872316
Short name T70
Test name
Test status
Simulation time 1274780301 ps
CPU time 24.16 seconds
Started Sep 09 10:52:09 AM UTC 24
Finished Sep 09 10:52:40 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2271872316 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 80.prim_prince_test.2271872316
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/80.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/81.prim_prince_test.3351040161
Short name T80
Test name
Test status
Simulation time 1859238116 ps
CPU time 35.42 seconds
Started Sep 09 10:52:10 AM UTC 24
Finished Sep 09 10:52:54 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3351040161 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 81.prim_prince_test.3351040161
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/81.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/82.prim_prince_test.221861703
Short name T111
Test name
Test status
Simulation time 3751117564 ps
CPU time 66.87 seconds
Started Sep 09 10:52:12 AM UTC 24
Finished Sep 09 10:53:36 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=221861703 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 82.prim_prince_test.221861703
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/82.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/83.prim_prince_test.1299707561
Short name T95
Test name
Test status
Simulation time 2509458614 ps
CPU time 45.77 seconds
Started Sep 09 10:52:12 AM UTC 24
Finished Sep 09 10:53:10 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1299707561 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 83.prim_prince_test.1299707561
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/83.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/84.prim_prince_test.3268238414
Short name T68
Test name
Test status
Simulation time 957582436 ps
CPU time 17.69 seconds
Started Sep 09 10:52:12 AM UTC 24
Finished Sep 09 10:52:35 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3268238414 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 84.prim_prince_test.3268238414
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/84.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/85.prim_prince_test.687240281
Short name T96
Test name
Test status
Simulation time 2786582586 ps
CPU time 50.41 seconds
Started Sep 09 10:52:13 AM UTC 24
Finished Sep 09 10:53:17 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=687240281 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 85.prim_prince_test.687240281
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/85.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/86.prim_prince_test.3657154444
Short name T74
Test name
Test status
Simulation time 1126857012 ps
CPU time 20.64 seconds
Started Sep 09 10:52:16 AM UTC 24
Finished Sep 09 10:52:42 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3657154444 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 86.prim_prince_test.3657154444
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/86.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/87.prim_prince_test.104964109
Short name T71
Test name
Test status
Simulation time 973255052 ps
CPU time 18.2 seconds
Started Sep 09 10:52:18 AM UTC 24
Finished Sep 09 10:52:41 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=104964109 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 87.prim_prince_test.104964109
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/87.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/88.prim_prince_test.1151981501
Short name T92
Test name
Test status
Simulation time 2041709674 ps
CPU time 38.14 seconds
Started Sep 09 10:52:19 AM UTC 24
Finished Sep 09 10:53:07 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1151981501 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 88.prim_prince_test.1151981501
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/88.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/89.prim_prince_test.3619606117
Short name T78
Test name
Test status
Simulation time 1248336513 ps
CPU time 23.74 seconds
Started Sep 09 10:52:21 AM UTC 24
Finished Sep 09 10:52:51 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3619606117 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 89.prim_prince_test.3619606117
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/89.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/9.prim_prince_test.1067537592
Short name T13
Test name
Test status
Simulation time 2494796027 ps
CPU time 45.87 seconds
Started Sep 09 10:50:17 AM UTC 24
Finished Sep 09 10:51:15 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1067537592 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 9.prim_prince_test.1067537592
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/9.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/90.prim_prince_test.3042573577
Short name T102
Test name
Test status
Simulation time 2731174600 ps
CPU time 49.47 seconds
Started Sep 09 10:52:22 AM UTC 24
Finished Sep 09 10:53:24 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3042573577 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 90.prim_prince_test.3042573577
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/90.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/91.prim_prince_test.119805362
Short name T110
Test name
Test status
Simulation time 3069206918 ps
CPU time 58.45 seconds
Started Sep 09 10:52:22 AM UTC 24
Finished Sep 09 10:53:34 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=119805362 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 91.prim_prince_test.119805362
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/91.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/92.prim_prince_test.3515135120
Short name T87
Test name
Test status
Simulation time 1635758771 ps
CPU time 30.67 seconds
Started Sep 09 10:52:25 AM UTC 24
Finished Sep 09 10:53:04 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3515135120 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 92.prim_prince_test.3515135120
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/92.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/93.prim_prince_test.1185387371
Short name T81
Test name
Test status
Simulation time 1308315853 ps
CPU time 23.5 seconds
Started Sep 09 10:52:26 AM UTC 24
Finished Sep 09 10:52:56 AM UTC 24
Peak memory 156120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1185387371 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 93.prim_prince_test.1185387371
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/93.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/94.prim_prince_test.4173651339
Short name T89
Test name
Test status
Simulation time 1677885679 ps
CPU time 30.77 seconds
Started Sep 09 10:52:26 AM UTC 24
Finished Sep 09 10:53:05 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4173651339 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 94.prim_prince_test.4173651339
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/94.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/95.prim_prince_test.2809833895
Short name T85
Test name
Test status
Simulation time 1544355262 ps
CPU time 28.39 seconds
Started Sep 09 10:52:27 AM UTC 24
Finished Sep 09 10:53:03 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2809833895 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 95.prim_prince_test.2809833895
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/95.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/96.prim_prince_test.3141189857
Short name T97
Test name
Test status
Simulation time 2094020364 ps
CPU time 38.85 seconds
Started Sep 09 10:52:28 AM UTC 24
Finished Sep 09 10:53:17 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3141189857 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 96.prim_prince_test.3141189857
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/96.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/97.prim_prince_test.1277184850
Short name T84
Test name
Test status
Simulation time 1410811587 ps
CPU time 25.4 seconds
Started Sep 09 10:52:29 AM UTC 24
Finished Sep 09 10:53:02 AM UTC 24
Peak memory 154600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1277184850 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 97.prim_prince_test.1277184850
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/97.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/98.prim_prince_test.1183623984
Short name T108
Test name
Test status
Simulation time 2681514323 ps
CPU time 48.82 seconds
Started Sep 09 10:52:29 AM UTC 24
Finished Sep 09 10:53:30 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1183623984 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 98.prim_prince_test.1183623984
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/98.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default/99.prim_prince_test.2798576597
Short name T103
Test name
Test status
Simulation time 2367918968 ps
CPU time 44.47 seconds
Started Sep 09 10:52:29 AM UTC 24
Finished Sep 09 10:53:25 AM UTC 24
Peak memory 154664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2798576597 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 99.prim_prince_test.2798576597
Directory /workspaces/repo/scratch/os_regression_2024_09_08/prim_prince-sim-vcs/99.prim_prince_test/latest
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