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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00 100.00


Total test records in report: 500
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html
T251 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/252.prim_prince_test.3927731707 Sep 11 10:08:53 AM UTC 24 Sep 11 10:09:35 AM UTC 24 1717903501 ps
T252 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/263.prim_prince_test.1617371595 Sep 11 10:09:08 AM UTC 24 Sep 11 10:09:35 AM UTC 24 1064506177 ps
T253 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/255.prim_prince_test.1138478355 Sep 11 10:08:55 AM UTC 24 Sep 11 10:09:36 AM UTC 24 1621355288 ps
T254 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/256.prim_prince_test.1060877404 Sep 11 10:08:56 AM UTC 24 Sep 11 10:09:37 AM UTC 24 1648530261 ps
T255 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/271.prim_prince_test.3668123455 Sep 11 10:09:19 AM UTC 24 Sep 11 10:09:42 AM UTC 24 890856428 ps
T256 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/268.prim_prince_test.1883449571 Sep 11 10:09:15 AM UTC 24 Sep 11 10:09:43 AM UTC 24 1097363519 ps
T257 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/273.prim_prince_test.534023686 Sep 11 10:09:25 AM UTC 24 Sep 11 10:09:48 AM UTC 24 864784765 ps
T258 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/265.prim_prince_test.2031206390 Sep 11 10:09:09 AM UTC 24 Sep 11 10:09:50 AM UTC 24 1598972428 ps
T259 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/239.prim_prince_test.2128458795 Sep 11 10:08:28 AM UTC 24 Sep 11 10:09:50 AM UTC 24 3351612787 ps
T260 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/247.prim_prince_test.3242504222 Sep 11 10:08:40 AM UTC 24 Sep 11 10:09:51 AM UTC 24 2944270134 ps
T261 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/274.prim_prince_test.2466737461 Sep 11 10:09:25 AM UTC 24 Sep 11 10:09:51 AM UTC 24 1032486925 ps
T262 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/260.prim_prince_test.752749011 Sep 11 10:09:04 AM UTC 24 Sep 11 10:09:52 AM UTC 24 2031348422 ps
T263 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/269.prim_prince_test.1763141153 Sep 11 10:09:17 AM UTC 24 Sep 11 10:09:53 AM UTC 24 1482155266 ps
T264 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/264.prim_prince_test.3062042284 Sep 11 10:09:09 AM UTC 24 Sep 11 10:09:54 AM UTC 24 1753040070 ps
T265 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/257.prim_prince_test.2286410183 Sep 11 10:09:01 AM UTC 24 Sep 11 10:09:59 AM UTC 24 2300180700 ps
T266 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/259.prim_prince_test.2164473580 Sep 11 10:09:04 AM UTC 24 Sep 11 10:10:00 AM UTC 24 2271529911 ps
T267 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/279.prim_prince_test.2318548276 Sep 11 10:09:36 AM UTC 24 Sep 11 10:10:01 AM UTC 24 948199513 ps
T268 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/272.prim_prince_test.1116531444 Sep 11 10:09:24 AM UTC 24 Sep 11 10:10:01 AM UTC 24 1527018115 ps
T269 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/254.prim_prince_test.620680887 Sep 11 10:08:54 AM UTC 24 Sep 11 10:10:09 AM UTC 24 3144542776 ps
T270 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/266.prim_prince_test.2674251608 Sep 11 10:09:10 AM UTC 24 Sep 11 10:10:09 AM UTC 24 2389532438 ps
T271 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/249.prim_prince_test.3177839155 Sep 11 10:08:43 AM UTC 24 Sep 11 10:10:10 AM UTC 24 3458013995 ps
T272 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/278.prim_prince_test.853618847 Sep 11 10:09:36 AM UTC 24 Sep 11 10:10:10 AM UTC 24 1345285984 ps
T273 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/283.prim_prince_test.234423571 Sep 11 10:09:41 AM UTC 24 Sep 11 10:10:11 AM UTC 24 1150276988 ps
T274 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/287.prim_prince_test.3714807430 Sep 11 10:09:50 AM UTC 24 Sep 11 10:10:12 AM UTC 24 875418106 ps
T275 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/258.prim_prince_test.24382709 Sep 11 10:09:02 AM UTC 24 Sep 11 10:10:13 AM UTC 24 2790175608 ps
T276 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/250.prim_prince_test.189950956 Sep 11 10:08:52 AM UTC 24 Sep 11 10:10:18 AM UTC 24 3577692974 ps
T277 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/293.prim_prince_test.4141910083 Sep 11 10:09:55 AM UTC 24 Sep 11 10:10:21 AM UTC 24 1045450380 ps
T278 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/292.prim_prince_test.1635197585 Sep 11 10:09:55 AM UTC 24 Sep 11 10:10:25 AM UTC 24 1214423446 ps
T279 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/270.prim_prince_test.4071705735 Sep 11 10:09:18 AM UTC 24 Sep 11 10:10:27 AM UTC 24 2787002183 ps
T280 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/277.prim_prince_test.2952438913 Sep 11 10:09:35 AM UTC 24 Sep 11 10:10:27 AM UTC 24 2080802920 ps
T281 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/297.prim_prince_test.3496352668 Sep 11 10:10:02 AM UTC 24 Sep 11 10:10:29 AM UTC 24 1068118611 ps
T282 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/301.prim_prince_test.21375609 Sep 11 10:10:12 AM UTC 24 Sep 11 10:10:31 AM UTC 24 769087266 ps
T283 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/288.prim_prince_test.3735549534 Sep 11 10:09:51 AM UTC 24 Sep 11 10:10:35 AM UTC 24 1770539953 ps
T284 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/267.prim_prince_test.1143292467 Sep 11 10:09:12 AM UTC 24 Sep 11 10:10:36 AM UTC 24 3415166395 ps
T285 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/261.prim_prince_test.3593295148 Sep 11 10:09:07 AM UTC 24 Sep 11 10:10:38 AM UTC 24 3668395722 ps
T286 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/302.prim_prince_test.1723547668 Sep 11 10:10:12 AM UTC 24 Sep 11 10:10:44 AM UTC 24 1337719821 ps
T287 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/285.prim_prince_test.2441657644 Sep 11 10:09:44 AM UTC 24 Sep 11 10:10:48 AM UTC 24 2602236343 ps
T288 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/276.prim_prince_test.920763008 Sep 11 10:09:30 AM UTC 24 Sep 11 10:10:48 AM UTC 24 3316319468 ps
T289 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/286.prim_prince_test.3908714007 Sep 11 10:09:49 AM UTC 24 Sep 11 10:10:48 AM UTC 24 2427518301 ps
T290 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/284.prim_prince_test.3750748796 Sep 11 10:09:44 AM UTC 24 Sep 11 10:10:49 AM UTC 24 2646233871 ps
T291 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/280.prim_prince_test.1763063558 Sep 11 10:09:36 AM UTC 24 Sep 11 10:10:49 AM UTC 24 2972015273 ps
T292 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/275.prim_prince_test.2349027766 Sep 11 10:09:27 AM UTC 24 Sep 11 10:10:53 AM UTC 24 3577860371 ps
T293 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/300.prim_prince_test.3692535571 Sep 11 10:10:10 AM UTC 24 Sep 11 10:10:54 AM UTC 24 1744611779 ps
T294 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/310.prim_prince_test.2979189202 Sep 11 10:10:30 AM UTC 24 Sep 11 10:10:56 AM UTC 24 980377174 ps
T295 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/309.prim_prince_test.2792800179 Sep 11 10:10:28 AM UTC 24 Sep 11 10:10:57 AM UTC 24 1133971424 ps
T296 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/308.prim_prince_test.4016709024 Sep 11 10:10:28 AM UTC 24 Sep 11 10:10:58 AM UTC 24 1217329471 ps
T297 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/290.prim_prince_test.3091214699 Sep 11 10:09:52 AM UTC 24 Sep 11 10:11:00 AM UTC 24 2748687539 ps
T298 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/312.prim_prince_test.3047984979 Sep 11 10:10:35 AM UTC 24 Sep 11 10:11:01 AM UTC 24 1001285332 ps
T299 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/289.prim_prince_test.480563226 Sep 11 10:09:52 AM UTC 24 Sep 11 10:11:02 AM UTC 24 2942848049 ps
T300 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/281.prim_prince_test.2161780409 Sep 11 10:09:36 AM UTC 24 Sep 11 10:11:02 AM UTC 24 3586178988 ps
T301 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/282.prim_prince_test.3670114411 Sep 11 10:09:38 AM UTC 24 Sep 11 10:11:03 AM UTC 24 3568745430 ps
T302 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/296.prim_prince_test.862701987 Sep 11 10:10:02 AM UTC 24 Sep 11 10:11:04 AM UTC 24 2549495740 ps
T303 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/299.prim_prince_test.1791648558 Sep 11 10:10:10 AM UTC 24 Sep 11 10:11:05 AM UTC 24 2175122445 ps
T304 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/295.prim_prince_test.172258805 Sep 11 10:10:01 AM UTC 24 Sep 11 10:11:06 AM UTC 24 2625938263 ps
T305 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/303.prim_prince_test.210069192 Sep 11 10:10:13 AM UTC 24 Sep 11 10:11:07 AM UTC 24 2174670752 ps
T306 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/304.prim_prince_test.855703602 Sep 11 10:10:14 AM UTC 24 Sep 11 10:11:10 AM UTC 24 2310209794 ps
T307 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/298.prim_prince_test.677680863 Sep 11 10:10:10 AM UTC 24 Sep 11 10:11:12 AM UTC 24 2494533654 ps
T308 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/306.prim_prince_test.3518916160 Sep 11 10:10:22 AM UTC 24 Sep 11 10:11:12 AM UTC 24 2034522665 ps
T309 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/291.prim_prince_test.2243151579 Sep 11 10:09:53 AM UTC 24 Sep 11 10:11:12 AM UTC 24 3328588385 ps
T310 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/294.prim_prince_test.3209397818 Sep 11 10:10:00 AM UTC 24 Sep 11 10:11:16 AM UTC 24 3181165436 ps
T311 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/322.prim_prince_test.3285863101 Sep 11 10:10:54 AM UTC 24 Sep 11 10:11:16 AM UTC 24 819999936 ps
T312 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/321.prim_prince_test.964562636 Sep 11 10:10:54 AM UTC 24 Sep 11 10:11:19 AM UTC 24 960543414 ps
T313 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/307.prim_prince_test.1370913447 Sep 11 10:10:25 AM UTC 24 Sep 11 10:11:19 AM UTC 24 2148408250 ps
T314 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/313.prim_prince_test.302631853 Sep 11 10:10:37 AM UTC 24 Sep 11 10:11:21 AM UTC 24 1764145846 ps
T315 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/316.prim_prince_test.3011398741 Sep 11 10:10:49 AM UTC 24 Sep 11 10:11:27 AM UTC 24 1528593177 ps
T316 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/331.prim_prince_test.2636582033 Sep 11 10:11:06 AM UTC 24 Sep 11 10:11:27 AM UTC 24 826445283 ps
T317 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/311.prim_prince_test.428595773 Sep 11 10:10:33 AM UTC 24 Sep 11 10:11:30 AM UTC 24 2271417692 ps
T318 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/314.prim_prince_test.4249540966 Sep 11 10:10:38 AM UTC 24 Sep 11 10:11:41 AM UTC 24 2563028561 ps
T319 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/305.prim_prince_test.2051969056 Sep 11 10:10:19 AM UTC 24 Sep 11 10:11:41 AM UTC 24 3416604457 ps
T320 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/320.prim_prince_test.3004543462 Sep 11 10:10:50 AM UTC 24 Sep 11 10:11:43 AM UTC 24 2173581092 ps
T321 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/324.prim_prince_test.4247606176 Sep 11 10:10:58 AM UTC 24 Sep 11 10:11:44 AM UTC 24 1890773728 ps
T322 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/317.prim_prince_test.1703726091 Sep 11 10:10:49 AM UTC 24 Sep 11 10:11:44 AM UTC 24 2228524696 ps
T323 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/330.prim_prince_test.2340333523 Sep 11 10:11:04 AM UTC 24 Sep 11 10:11:47 AM UTC 24 1647668529 ps
T324 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/337.prim_prince_test.4019740707 Sep 11 10:11:12 AM UTC 24 Sep 11 10:11:47 AM UTC 24 1383709936 ps
T325 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/334.prim_prince_test.3864488889 Sep 11 10:11:08 AM UTC 24 Sep 11 10:11:49 AM UTC 24 1636246804 ps
T326 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/327.prim_prince_test.112504618 Sep 11 10:11:02 AM UTC 24 Sep 11 10:11:51 AM UTC 24 1961487466 ps
T327 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/333.prim_prince_test.3051418663 Sep 11 10:11:07 AM UTC 24 Sep 11 10:11:52 AM UTC 24 1765571875 ps
T328 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/315.prim_prince_test.186533363 Sep 11 10:10:46 AM UTC 24 Sep 11 10:11:52 AM UTC 24 2750565229 ps
T329 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/319.prim_prince_test.1055134403 Sep 11 10:10:50 AM UTC 24 Sep 11 10:11:53 AM UTC 24 2545795311 ps
T330 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/338.prim_prince_test.3390266648 Sep 11 10:11:13 AM UTC 24 Sep 11 10:11:54 AM UTC 24 1652756906 ps
T331 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/326.prim_prince_test.54911026 Sep 11 10:11:01 AM UTC 24 Sep 11 10:11:55 AM UTC 24 2193480918 ps
T332 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/318.prim_prince_test.3225922695 Sep 11 10:10:50 AM UTC 24 Sep 11 10:11:57 AM UTC 24 2687271468 ps
T333 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/342.prim_prince_test.3859850818 Sep 11 10:11:20 AM UTC 24 Sep 11 10:11:59 AM UTC 24 1566234056 ps
T334 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/339.prim_prince_test.1418912085 Sep 11 10:11:17 AM UTC 24 Sep 11 10:11:59 AM UTC 24 1716301753 ps
T335 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/323.prim_prince_test.2562528823 Sep 11 10:10:57 AM UTC 24 Sep 11 10:12:00 AM UTC 24 2611847232 ps
T336 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/341.prim_prince_test.1662455654 Sep 11 10:11:20 AM UTC 24 Sep 11 10:12:01 AM UTC 24 1647529443 ps
T337 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/350.prim_prince_test.3063932834 Sep 11 10:11:44 AM UTC 24 Sep 11 10:12:08 AM UTC 24 932787273 ps
T338 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/336.prim_prince_test.612723964 Sep 11 10:11:12 AM UTC 24 Sep 11 10:12:14 AM UTC 24 2559950587 ps
T339 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/328.prim_prince_test.2877312409 Sep 11 10:11:03 AM UTC 24 Sep 11 10:12:16 AM UTC 24 2998406887 ps
T340 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/325.prim_prince_test.3011599058 Sep 11 10:10:59 AM UTC 24 Sep 11 10:12:21 AM UTC 24 3468595786 ps
T341 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/332.prim_prince_test.2829979409 Sep 11 10:11:06 AM UTC 24 Sep 11 10:12:22 AM UTC 24 3208826143 ps
T342 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/357.prim_prince_test.576504659 Sep 11 10:11:53 AM UTC 24 Sep 11 10:12:23 AM UTC 24 1197824130 ps
T343 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/356.prim_prince_test.2779818815 Sep 11 10:11:53 AM UTC 24 Sep 11 10:12:24 AM UTC 24 1218302125 ps
T344 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/364.prim_prince_test.573572154 Sep 11 10:12:01 AM UTC 24 Sep 11 10:12:29 AM UTC 24 1121657352 ps
T345 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/346.prim_prince_test.3295710694 Sep 11 10:11:31 AM UTC 24 Sep 11 10:12:30 AM UTC 24 2423722773 ps
T346 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/351.prim_prince_test.1913968679 Sep 11 10:11:45 AM UTC 24 Sep 11 10:12:31 AM UTC 24 1827292708 ps
T347 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/329.prim_prince_test.493436715 Sep 11 10:11:03 AM UTC 24 Sep 11 10:12:31 AM UTC 24 3587851374 ps
T348 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/340.prim_prince_test.422569385 Sep 11 10:11:17 AM UTC 24 Sep 11 10:12:33 AM UTC 24 3120154278 ps
T349 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/335.prim_prince_test.1633239661 Sep 11 10:11:11 AM UTC 24 Sep 11 10:12:33 AM UTC 24 3422663921 ps
T350 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/365.prim_prince_test.614054564 Sep 11 10:12:02 AM UTC 24 Sep 11 10:12:35 AM UTC 24 1307027822 ps
T351 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/367.prim_prince_test.408289108 Sep 11 10:12:14 AM UTC 24 Sep 11 10:12:35 AM UTC 24 803262921 ps
T352 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/361.prim_prince_test.1870862809 Sep 11 10:11:58 AM UTC 24 Sep 11 10:12:35 AM UTC 24 1531664725 ps
T353 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/343.prim_prince_test.3632148843 Sep 11 10:11:22 AM UTC 24 Sep 11 10:12:38 AM UTC 24 3103002495 ps
T354 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/363.prim_prince_test.554714913 Sep 11 10:12:01 AM UTC 24 Sep 11 10:12:38 AM UTC 24 1470174930 ps
T355 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/345.prim_prince_test.753136398 Sep 11 10:11:28 AM UTC 24 Sep 11 10:12:39 AM UTC 24 2870964141 ps
T356 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/362.prim_prince_test.2109847077 Sep 11 10:12:00 AM UTC 24 Sep 11 10:12:42 AM UTC 24 1726005034 ps
T357 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/371.prim_prince_test.61400202 Sep 11 10:12:23 AM UTC 24 Sep 11 10:12:44 AM UTC 24 797106917 ps
T358 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/344.prim_prince_test.4005591313 Sep 11 10:11:28 AM UTC 24 Sep 11 10:12:45 AM UTC 24 3135805126 ps
T359 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/353.prim_prince_test.3240317485 Sep 11 10:11:47 AM UTC 24 Sep 11 10:12:45 AM UTC 24 2375993967 ps
T360 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/352.prim_prince_test.341291703 Sep 11 10:11:47 AM UTC 24 Sep 11 10:12:50 AM UTC 24 2554301995 ps
T361 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/355.prim_prince_test.874228346 Sep 11 10:11:52 AM UTC 24 Sep 11 10:12:52 AM UTC 24 2561824428 ps
T362 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/348.prim_prince_test.3152461606 Sep 11 10:11:42 AM UTC 24 Sep 11 10:12:56 AM UTC 24 3080437031 ps
T363 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/385.prim_prince_test.1966184194 Sep 11 10:12:40 AM UTC 24 Sep 11 10:13:01 AM UTC 24 806454631 ps
T364 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/359.prim_prince_test.3279292191 Sep 11 10:11:54 AM UTC 24 Sep 11 10:13:05 AM UTC 24 2911705609 ps
T365 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/372.prim_prince_test.2607880522 Sep 11 10:12:24 AM UTC 24 Sep 11 10:13:07 AM UTC 24 1726861426 ps
T366 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/382.prim_prince_test.767910319 Sep 11 10:12:37 AM UTC 24 Sep 11 10:13:08 AM UTC 24 1222523071 ps
T367 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/347.prim_prince_test.4150598821 Sep 11 10:11:42 AM UTC 24 Sep 11 10:13:09 AM UTC 24 3555776358 ps
T368 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/349.prim_prince_test.277275043 Sep 11 10:11:44 AM UTC 24 Sep 11 10:13:09 AM UTC 24 3541739865 ps
T369 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/358.prim_prince_test.2140935635 Sep 11 10:11:54 AM UTC 24 Sep 11 10:13:09 AM UTC 24 3020818169 ps
T370 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/360.prim_prince_test.3258844161 Sep 11 10:11:55 AM UTC 24 Sep 11 10:13:12 AM UTC 24 3151756066 ps
T371 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/390.prim_prince_test.746769499 Sep 11 10:12:50 AM UTC 24 Sep 11 10:13:14 AM UTC 24 926136188 ps
T372 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/377.prim_prince_test.3271213887 Sep 11 10:12:32 AM UTC 24 Sep 11 10:13:14 AM UTC 24 1696383280 ps
T373 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/366.prim_prince_test.258727349 Sep 11 10:12:09 AM UTC 24 Sep 11 10:13:16 AM UTC 24 2788659840 ps
T374 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/354.prim_prince_test.1722000175 Sep 11 10:11:50 AM UTC 24 Sep 11 10:13:16 AM UTC 24 3579280691 ps
T375 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/373.prim_prince_test.1508912354 Sep 11 10:12:24 AM UTC 24 Sep 11 10:13:18 AM UTC 24 2201615830 ps
T376 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/389.prim_prince_test.3196142203 Sep 11 10:12:46 AM UTC 24 Sep 11 10:13:21 AM UTC 24 1389153504 ps
T377 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/388.prim_prince_test.4178876539 Sep 11 10:12:46 AM UTC 24 Sep 11 10:13:21 AM UTC 24 1399054538 ps
T378 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/380.prim_prince_test.347619709 Sep 11 10:12:35 AM UTC 24 Sep 11 10:13:24 AM UTC 24 2027465660 ps
T379 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/369.prim_prince_test.3411680705 Sep 11 10:12:23 AM UTC 24 Sep 11 10:13:34 AM UTC 24 2902524458 ps
T380 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/375.prim_prince_test.3753330323 Sep 11 10:12:32 AM UTC 24 Sep 11 10:13:36 AM UTC 24 2603600113 ps
T381 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/403.prim_prince_test.3477714547 Sep 11 10:13:17 AM UTC 24 Sep 11 10:13:39 AM UTC 24 847619317 ps
T382 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/387.prim_prince_test.3650801814 Sep 11 10:12:44 AM UTC 24 Sep 11 10:13:39 AM UTC 24 2239066479 ps
T383 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/368.prim_prince_test.1394241669 Sep 11 10:12:17 AM UTC 24 Sep 11 10:13:42 AM UTC 24 3517796971 ps
T384 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/381.prim_prince_test.3008850692 Sep 11 10:12:37 AM UTC 24 Sep 11 10:13:42 AM UTC 24 2666751489 ps
T385 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/396.prim_prince_test.264504167 Sep 11 10:13:09 AM UTC 24 Sep 11 10:13:45 AM UTC 24 1454134114 ps
T386 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/374.prim_prince_test.3201929468 Sep 11 10:12:31 AM UTC 24 Sep 11 10:13:46 AM UTC 24 3133974936 ps
T387 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/400.prim_prince_test.2125886601 Sep 11 10:13:13 AM UTC 24 Sep 11 10:13:48 AM UTC 24 1412029604 ps
T388 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/376.prim_prince_test.2330247628 Sep 11 10:12:32 AM UTC 24 Sep 11 10:13:49 AM UTC 24 3185148344 ps
T389 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/383.prim_prince_test.2292049315 Sep 11 10:12:39 AM UTC 24 Sep 11 10:13:53 AM UTC 24 3114532152 ps
T390 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/370.prim_prince_test.1725909375 Sep 11 10:12:23 AM UTC 24 Sep 11 10:13:54 AM UTC 24 3732327962 ps
T391 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/378.prim_prince_test.4043741121 Sep 11 10:12:33 AM UTC 24 Sep 11 10:13:56 AM UTC 24 3504075717 ps
T392 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/407.prim_prince_test.451968325 Sep 11 10:13:23 AM UTC 24 Sep 11 10:13:58 AM UTC 24 1389229532 ps
T393 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/379.prim_prince_test.2944837842 Sep 11 10:12:34 AM UTC 24 Sep 11 10:14:00 AM UTC 24 3501124017 ps
T394 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/384.prim_prince_test.2752636322 Sep 11 10:12:39 AM UTC 24 Sep 11 10:14:00 AM UTC 24 3346694966 ps
T395 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/391.prim_prince_test.1805829068 Sep 11 10:12:53 AM UTC 24 Sep 11 10:14:02 AM UTC 24 2848091447 ps
T396 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/408.prim_prince_test.1023982595 Sep 11 10:13:25 AM UTC 24 Sep 11 10:14:03 AM UTC 24 1561650024 ps
T397 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/386.prim_prince_test.69179669 Sep 11 10:12:42 AM UTC 24 Sep 11 10:14:03 AM UTC 24 3398062454 ps
T398 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/394.prim_prince_test.2502254786 Sep 11 10:13:07 AM UTC 24 Sep 11 10:14:05 AM UTC 24 2428414594 ps
T399 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/406.prim_prince_test.2757071034 Sep 11 10:13:21 AM UTC 24 Sep 11 10:14:07 AM UTC 24 1813291199 ps
T400 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/404.prim_prince_test.4211690109 Sep 11 10:13:17 AM UTC 24 Sep 11 10:14:09 AM UTC 24 2120006042 ps
T401 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/392.prim_prince_test.2230632606 Sep 11 10:12:56 AM UTC 24 Sep 11 10:14:16 AM UTC 24 3345013142 ps
T402 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/398.prim_prince_test.3462618701 Sep 11 10:13:10 AM UTC 24 Sep 11 10:14:16 AM UTC 24 2716201935 ps
T403 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/414.prim_prince_test.1442222848 Sep 11 10:13:43 AM UTC 24 Sep 11 10:14:18 AM UTC 24 1435267169 ps
T404 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/416.prim_prince_test.3326594999 Sep 11 10:13:45 AM UTC 24 Sep 11 10:14:24 AM UTC 24 1550106841 ps
T405 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/401.prim_prince_test.2471596232 Sep 11 10:13:15 AM UTC 24 Sep 11 10:14:25 AM UTC 24 2869012946 ps
T406 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/393.prim_prince_test.1638621110 Sep 11 10:13:02 AM UTC 24 Sep 11 10:14:25 AM UTC 24 3392457420 ps
T407 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/410.prim_prince_test.1495128015 Sep 11 10:13:34 AM UTC 24 Sep 11 10:14:25 AM UTC 24 2083442551 ps
T408 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/395.prim_prince_test.1214719422 Sep 11 10:13:09 AM UTC 24 Sep 11 10:14:27 AM UTC 24 3275718525 ps
T409 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/426.prim_prince_test.3018572139 Sep 11 10:14:03 AM UTC 24 Sep 11 10:14:28 AM UTC 24 1001290919 ps
T410 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/397.prim_prince_test.3372761631 Sep 11 10:13:10 AM UTC 24 Sep 11 10:14:30 AM UTC 24 3228796351 ps
T411 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/399.prim_prince_test.3738003982 Sep 11 10:13:10 AM UTC 24 Sep 11 10:14:30 AM UTC 24 3250074258 ps
T412 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/419.prim_prince_test.1710881933 Sep 11 10:13:50 AM UTC 24 Sep 11 10:14:31 AM UTC 24 1707453894 ps
T413 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/405.prim_prince_test.1043203696 Sep 11 10:13:19 AM UTC 24 Sep 11 10:14:38 AM UTC 24 3313236026 ps
T414 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/425.prim_prince_test.3470510644 Sep 11 10:14:02 AM UTC 24 Sep 11 10:14:39 AM UTC 24 1531475872 ps
T415 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/422.prim_prince_test.824446180 Sep 11 10:13:57 AM UTC 24 Sep 11 10:14:39 AM UTC 24 1665748105 ps
T416 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/431.prim_prince_test.1887391476 Sep 11 10:14:10 AM UTC 24 Sep 11 10:14:39 AM UTC 24 1208703910 ps
T417 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/411.prim_prince_test.1883664230 Sep 11 10:13:37 AM UTC 24 Sep 11 10:14:42 AM UTC 24 2632228031 ps
T418 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/402.prim_prince_test.2309099681 Sep 11 10:13:16 AM UTC 24 Sep 11 10:14:42 AM UTC 24 3572094020 ps
T419 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/409.prim_prince_test.3306074183 Sep 11 10:13:25 AM UTC 24 Sep 11 10:14:43 AM UTC 24 3277912840 ps
T420 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/415.prim_prince_test.497137008 Sep 11 10:13:43 AM UTC 24 Sep 11 10:14:43 AM UTC 24 2475310779 ps
T421 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/418.prim_prince_test.1013796986 Sep 11 10:13:48 AM UTC 24 Sep 11 10:14:43 AM UTC 24 2248372215 ps
T422 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/434.prim_prince_test.1578247770 Sep 11 10:14:19 AM UTC 24 Sep 11 10:14:49 AM UTC 24 1204643548 ps
T423 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/443.prim_prince_test.286461297 Sep 11 10:14:30 AM UTC 24 Sep 11 10:14:50 AM UTC 24 772750957 ps
T424 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/412.prim_prince_test.2188396547 Sep 11 10:13:39 AM UTC 24 Sep 11 10:14:52 AM UTC 24 2985750797 ps
T425 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/437.prim_prince_test.2382369839 Sep 11 10:14:26 AM UTC 24 Sep 11 10:14:53 AM UTC 24 1092527821 ps
T426 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/436.prim_prince_test.745184085 Sep 11 10:14:26 AM UTC 24 Sep 11 10:14:55 AM UTC 24 1184682942 ps
T427 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/423.prim_prince_test.1977360064 Sep 11 10:13:58 AM UTC 24 Sep 11 10:14:59 AM UTC 24 2546389698 ps
T428 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/435.prim_prince_test.2384298786 Sep 11 10:14:25 AM UTC 24 Sep 11 10:15:00 AM UTC 24 1440647785 ps
T429 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/446.prim_prince_test.2097238154 Sep 11 10:14:40 AM UTC 24 Sep 11 10:15:03 AM UTC 24 904036019 ps
T430 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/440.prim_prince_test.1121881216 Sep 11 10:14:28 AM UTC 24 Sep 11 10:15:04 AM UTC 24 1468350841 ps
T431 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/449.prim_prince_test.614190056 Sep 11 10:14:43 AM UTC 24 Sep 11 10:15:05 AM UTC 24 914419313 ps
T432 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/432.prim_prince_test.875775888 Sep 11 10:14:17 AM UTC 24 Sep 11 10:15:06 AM UTC 24 1996895184 ps
T433 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/413.prim_prince_test.4005554574 Sep 11 10:13:41 AM UTC 24 Sep 11 10:15:07 AM UTC 24 3705360530 ps
T434 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/433.prim_prince_test.3698945355 Sep 11 10:14:17 AM UTC 24 Sep 11 10:15:08 AM UTC 24 2145407031 ps
T435 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/424.prim_prince_test.1613960059 Sep 11 10:14:00 AM UTC 24 Sep 11 10:15:13 AM UTC 24 3025355922 ps
T436 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/427.prim_prince_test.1375263629 Sep 11 10:14:04 AM UTC 24 Sep 11 10:15:13 AM UTC 24 2797606544 ps
T437 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/417.prim_prince_test.1144908585 Sep 11 10:13:47 AM UTC 24 Sep 11 10:15:13 AM UTC 24 3656384115 ps
T438 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/430.prim_prince_test.1318301892 Sep 11 10:14:07 AM UTC 24 Sep 11 10:15:14 AM UTC 24 2760040051 ps
T439 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/421.prim_prince_test.1901260098 Sep 11 10:13:55 AM UTC 24 Sep 11 10:15:17 AM UTC 24 3374641868 ps
T440 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/458.prim_prince_test.3397452046 Sep 11 10:14:56 AM UTC 24 Sep 11 10:15:19 AM UTC 24 906564755 ps
T441 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/454.prim_prince_test.3366997582 Sep 11 10:14:49 AM UTC 24 Sep 11 10:15:21 AM UTC 24 1320093021 ps
T442 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/420.prim_prince_test.3303870988 Sep 11 10:13:54 AM UTC 24 Sep 11 10:15:22 AM UTC 24 3616467451 ps
T443 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/457.prim_prince_test.130560014 Sep 11 10:14:54 AM UTC 24 Sep 11 10:15:24 AM UTC 24 1258772410 ps
T444 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/453.prim_prince_test.2394992964 Sep 11 10:14:44 AM UTC 24 Sep 11 10:15:26 AM UTC 24 1704151271 ps
T445 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/428.prim_prince_test.1983308347 Sep 11 10:14:04 AM UTC 24 Sep 11 10:15:30 AM UTC 24 3685419474 ps
T446 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/429.prim_prince_test.16190451 Sep 11 10:14:06 AM UTC 24 Sep 11 10:15:31 AM UTC 24 3612637798 ps
T447 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/439.prim_prince_test.2955096834 Sep 11 10:14:27 AM UTC 24 Sep 11 10:15:32 AM UTC 24 2675495051 ps
T448 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/447.prim_prince_test.1222028413 Sep 11 10:14:40 AM UTC 24 Sep 11 10:15:33 AM UTC 24 2231772659 ps
T449 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/452.prim_prince_test.974548177 Sep 11 10:14:44 AM UTC 24 Sep 11 10:15:36 AM UTC 24 2117461407 ps
T450 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/456.prim_prince_test.1468090451 Sep 11 10:14:53 AM UTC 24 Sep 11 10:15:39 AM UTC 24 1911057098 ps
T451 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/468.prim_prince_test.3734874764 Sep 11 10:15:14 AM UTC 24 Sep 11 10:15:40 AM UTC 24 1050223617 ps
T452 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/459.prim_prince_test.3211377538 Sep 11 10:15:00 AM UTC 24 Sep 11 10:15:47 AM UTC 24 1882265846 ps
T453 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/441.prim_prince_test.1247889065 Sep 11 10:14:29 AM UTC 24 Sep 11 10:15:47 AM UTC 24 3355663497 ps
T454 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/462.prim_prince_test.4024413271 Sep 11 10:15:05 AM UTC 24 Sep 11 10:15:48 AM UTC 24 1734676840 ps
T455 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/442.prim_prince_test.2411424878 Sep 11 10:14:30 AM UTC 24 Sep 11 10:15:49 AM UTC 24 3255224027 ps
T456 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/444.prim_prince_test.3163542924 Sep 11 10:14:32 AM UTC 24 Sep 11 10:15:52 AM UTC 24 3455152051 ps
T457 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/465.prim_prince_test.671423561 Sep 11 10:15:08 AM UTC 24 Sep 11 10:15:55 AM UTC 24 1893608424 ps
T458 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/438.prim_prince_test.2098766614 Sep 11 10:14:27 AM UTC 24 Sep 11 10:15:55 AM UTC 24 3657201458 ps
T459 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/471.prim_prince_test.4125813988 Sep 11 10:15:17 AM UTC 24 Sep 11 10:15:57 AM UTC 24 1643445262 ps
T460 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/481.prim_prince_test.3445554068 Sep 11 10:15:37 AM UTC 24 Sep 11 10:15:59 AM UTC 24 836732348 ps
T461 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/450.prim_prince_test.2150765980 Sep 11 10:14:44 AM UTC 24 Sep 11 10:16:00 AM UTC 24 3117326579 ps
T462 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/451.prim_prince_test.3918047225 Sep 11 10:14:44 AM UTC 24 Sep 11 10:16:03 AM UTC 24 3365658774 ps
T463 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/482.prim_prince_test.459642135 Sep 11 10:15:40 AM UTC 24 Sep 11 10:16:03 AM UTC 24 887210287 ps
T464 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/448.prim_prince_test.2926838934 Sep 11 10:14:40 AM UTC 24 Sep 11 10:16:05 AM UTC 24 3512896998 ps
T465 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/445.prim_prince_test.468494774 Sep 11 10:14:39 AM UTC 24 Sep 11 10:16:05 AM UTC 24 3608401249 ps
T466 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/463.prim_prince_test.2561789957 Sep 11 10:15:06 AM UTC 24 Sep 11 10:16:05 AM UTC 24 2387887799 ps
T467 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/461.prim_prince_test.3961129207 Sep 11 10:15:04 AM UTC 24 Sep 11 10:16:06 AM UTC 24 2513485658 ps
T468 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/470.prim_prince_test.46053240 Sep 11 10:15:15 AM UTC 24 Sep 11 10:16:06 AM UTC 24 2063033281 ps
T469 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/455.prim_prince_test.1977984258 Sep 11 10:14:52 AM UTC 24 Sep 11 10:16:08 AM UTC 24 3113252123 ps
T470 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/485.prim_prince_test.4113226969 Sep 11 10:15:49 AM UTC 24 Sep 11 10:16:08 AM UTC 24 778691483 ps
T471 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/473.prim_prince_test.348878600 Sep 11 10:15:22 AM UTC 24 Sep 11 10:16:10 AM UTC 24 2053427898 ps
T472 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/467.prim_prince_test.4225789789 Sep 11 10:15:14 AM UTC 24 Sep 11 10:16:14 AM UTC 24 2435711022 ps
T473 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/472.prim_prince_test.2715705928 Sep 11 10:15:19 AM UTC 24 Sep 11 10:16:15 AM UTC 24 2262305750 ps
T474 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/464.prim_prince_test.3930898453 Sep 11 10:15:07 AM UTC 24 Sep 11 10:16:20 AM UTC 24 2969094224 ps
T475 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/460.prim_prince_test.3387600170 Sep 11 10:15:01 AM UTC 24 Sep 11 10:16:21 AM UTC 24 3334541393 ps
T476 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/492.prim_prince_test.3664262837 Sep 11 10:16:00 AM UTC 24 Sep 11 10:16:23 AM UTC 24 885689704 ps
T477 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/483.prim_prince_test.892860190 Sep 11 10:15:40 AM UTC 24 Sep 11 10:16:23 AM UTC 24 1728860201 ps
T478 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/493.prim_prince_test.2494719190 Sep 11 10:16:01 AM UTC 24 Sep 11 10:16:24 AM UTC 24 861277845 ps
T479 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/497.prim_prince_test.868004807 Sep 11 10:16:06 AM UTC 24 Sep 11 10:16:25 AM UTC 24 769958080 ps
T480 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/490.prim_prince_test.3073842813 Sep 11 10:15:55 AM UTC 24 Sep 11 10:16:25 AM UTC 24 1195642493 ps
T481 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/496.prim_prince_test.886526391 Sep 11 10:16:06 AM UTC 24 Sep 11 10:16:27 AM UTC 24 827461264 ps
T482 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/487.prim_prince_test.3003880389 Sep 11 10:15:50 AM UTC 24 Sep 11 10:16:28 AM UTC 24 1579605404 ps
T483 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/484.prim_prince_test.3556769622 Sep 11 10:15:49 AM UTC 24 Sep 11 10:16:28 AM UTC 24 1578809801 ps
T484 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/475.prim_prince_test.3883551271 Sep 11 10:15:25 AM UTC 24 Sep 11 10:16:29 AM UTC 24 2576598921 ps
T485 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/469.prim_prince_test.1814828497 Sep 11 10:15:15 AM UTC 24 Sep 11 10:16:32 AM UTC 24 3120953702 ps
T486 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/499.prim_prince_test.3038788536 Sep 11 10:16:07 AM UTC 24 Sep 11 10:16:33 AM UTC 24 989410782 ps
T487 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/479.prim_prince_test.946799970 Sep 11 10:15:33 AM UTC 24 Sep 11 10:16:33 AM UTC 24 2492651775 ps
T488 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/466.prim_prince_test.1373249645 Sep 11 10:15:09 AM UTC 24 Sep 11 10:16:34 AM UTC 24 3573209856 ps
T489 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/489.prim_prince_test.3886108484 Sep 11 10:15:55 AM UTC 24 Sep 11 10:16:35 AM UTC 24 1598599910 ps
T490 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/478.prim_prince_test.4158331905 Sep 11 10:15:33 AM UTC 24 Sep 11 10:16:37 AM UTC 24 2604633489 ps
T491 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/480.prim_prince_test.1495336457 Sep 11 10:15:34 AM UTC 24 Sep 11 10:16:40 AM UTC 24 2790113928 ps
T492 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/495.prim_prince_test.4179860225 Sep 11 10:16:04 AM UTC 24 Sep 11 10:16:40 AM UTC 24 1425465756 ps
T493 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/474.prim_prince_test.3268467839 Sep 11 10:15:23 AM UTC 24 Sep 11 10:16:40 AM UTC 24 3152603317 ps
T494 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/488.prim_prince_test.2914358232 Sep 11 10:15:53 AM UTC 24 Sep 11 10:16:44 AM UTC 24 2025438363 ps
T495 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/476.prim_prince_test.45302134 Sep 11 10:15:27 AM UTC 24 Sep 11 10:16:47 AM UTC 24 3350507334 ps
T496 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/486.prim_prince_test.940680164 Sep 11 10:15:49 AM UTC 24 Sep 11 10:16:56 AM UTC 24 2648415504 ps
T497 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/477.prim_prince_test.2052381496 Sep 11 10:15:31 AM UTC 24 Sep 11 10:17:01 AM UTC 24 3720616815 ps
T498 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/494.prim_prince_test.2320679108 Sep 11 10:16:04 AM UTC 24 Sep 11 10:17:19 AM UTC 24 2950700699 ps
T499 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/491.prim_prince_test.1704039164 Sep 11 10:15:58 AM UTC 24 Sep 11 10:17:24 AM UTC 24 3254071455 ps
T500 /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/498.prim_prince_test.2595693841 Sep 11 10:16:06 AM UTC 24 Sep 11 10:17:26 AM UTC 24 3156674911 ps

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/0.prim_prince_test.2789145176
Short name T6
Test name
Test status
Simulation time 1664471336 ps
CPU time 33.15 seconds
Started Sep 11 09:59:55 AM UTC 24
Finished Sep 11 10:00:38 AM UTC 24
Peak memory 154592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2789145176 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 0.prim_prince_test.2789145176
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/0.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/1.prim_prince_test.3783393760
Short name T4
Test name
Test status
Simulation time 1242368334 ps
CPU time 25.18 seconds
Started Sep 11 09:59:56 AM UTC 24
Finished Sep 11 10:00:30 AM UTC 24
Peak memory 154564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3783393760 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 1.prim_prince_test.3783393760
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/1.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/10.prim_prince_test.1871823711
Short name T9
Test name
Test status
Simulation time 2073376579 ps
CPU time 42 seconds
Started Sep 11 09:59:56 AM UTC 24
Finished Sep 11 10:00:51 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1871823711 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 10.prim_prince_test.1871823711
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/10.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/100.prim_prince_test.821144889
Short name T117
Test name
Test status
Simulation time 3442024955 ps
CPU time 65.52 seconds
Started Sep 11 10:03:28 AM UTC 24
Finished Sep 11 10:04:52 AM UTC 24
Peak memory 154656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=821144889 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 100.prim_prince_test.821144889
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/100.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/101.prim_prince_test.2893639251
Short name T93
Test name
Test status
Simulation time 1480164666 ps
CPU time 28.01 seconds
Started Sep 11 10:03:29 AM UTC 24
Finished Sep 11 10:04:05 AM UTC 24
Peak memory 154556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2893639251 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 101.prim_prince_test.2893639251
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/101.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/102.prim_prince_test.1721289961
Short name T92
Test name
Test status
Simulation time 1220176889 ps
CPU time 24.53 seconds
Started Sep 11 10:03:29 AM UTC 24
Finished Sep 11 10:04:00 AM UTC 24
Peak memory 154556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1721289961 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 102.prim_prince_test.1721289961
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/102.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/103.prim_prince_test.3412615451
Short name T96
Test name
Test status
Simulation time 1834033407 ps
CPU time 35.45 seconds
Started Sep 11 10:03:29 AM UTC 24
Finished Sep 11 10:04:14 AM UTC 24
Peak memory 154580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3412615451 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 103.prim_prince_test.3412615451
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/103.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/104.prim_prince_test.2048954330
Short name T99
Test name
Test status
Simulation time 1980103475 ps
CPU time 37.74 seconds
Started Sep 11 10:03:32 AM UTC 24
Finished Sep 11 10:04:21 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2048954330 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 104.prim_prince_test.2048954330
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/104.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/105.prim_prince_test.810010096
Short name T101
Test name
Test status
Simulation time 2029245497 ps
CPU time 39.9 seconds
Started Sep 11 10:03:32 AM UTC 24
Finished Sep 11 10:04:23 AM UTC 24
Peak memory 154592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=810010096 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 105.prim_prince_test.810010096
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/105.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/106.prim_prince_test.4085551683
Short name T118
Test name
Test status
Simulation time 3187635157 ps
CPU time 62.47 seconds
Started Sep 11 10:03:37 AM UTC 24
Finished Sep 11 10:04:56 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4085551683 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 106.prim_prince_test.4085551683
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/106.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/107.prim_prince_test.4050753186
Short name T105
Test name
Test status
Simulation time 2212271794 ps
CPU time 44.03 seconds
Started Sep 11 10:03:38 AM UTC 24
Finished Sep 11 10:04:34 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4050753186 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 107.prim_prince_test.4050753186
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/107.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/108.prim_prince_test.2330858210
Short name T113
Test name
Test status
Simulation time 2813728393 ps
CPU time 53.21 seconds
Started Sep 11 10:03:40 AM UTC 24
Finished Sep 11 10:04:49 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2330858210 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 108.prim_prince_test.2330858210
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/108.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/109.prim_prince_test.494178828
Short name T119
Test name
Test status
Simulation time 3100639656 ps
CPU time 61.83 seconds
Started Sep 11 10:03:42 AM UTC 24
Finished Sep 11 10:05:00 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=494178828 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 109.prim_prince_test.494178828
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/109.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/11.prim_prince_test.2888585881
Short name T11
Test name
Test status
Simulation time 1918300755 ps
CPU time 38.46 seconds
Started Sep 11 09:59:56 AM UTC 24
Finished Sep 11 10:00:55 AM UTC 24
Peak memory 154592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2888585881 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 11.prim_prince_test.2888585881
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/11.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/110.prim_prince_test.2343347091
Short name T123
Test name
Test status
Simulation time 3499056062 ps
CPU time 67.82 seconds
Started Sep 11 10:03:44 AM UTC 24
Finished Sep 11 10:05:10 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2343347091 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 110.prim_prince_test.2343347091
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/110.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/111.prim_prince_test.3591280846
Short name T110
Test name
Test status
Simulation time 2388388575 ps
CPU time 44.52 seconds
Started Sep 11 10:03:47 AM UTC 24
Finished Sep 11 10:04:45 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3591280846 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 111.prim_prince_test.3591280846
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/111.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/112.prim_prince_test.2947763107
Short name T109
Test name
Test status
Simulation time 2117834385 ps
CPU time 41.69 seconds
Started Sep 11 10:03:48 AM UTC 24
Finished Sep 11 10:04:42 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2947763107 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 112.prim_prince_test.2947763107
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/112.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/113.prim_prince_test.2904328191
Short name T116
Test name
Test status
Simulation time 2494568926 ps
CPU time 47.15 seconds
Started Sep 11 10:03:51 AM UTC 24
Finished Sep 11 10:04:51 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2904328191 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 113.prim_prince_test.2904328191
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/113.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/114.prim_prince_test.909422028
Short name T102
Test name
Test status
Simulation time 1322359347 ps
CPU time 26.07 seconds
Started Sep 11 10:03:54 AM UTC 24
Finished Sep 11 10:04:27 AM UTC 24
Peak memory 154592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=909422028 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 114.prim_prince_test.909422028
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/114.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/115.prim_prince_test.78734380
Short name T120
Test name
Test status
Simulation time 2851544741 ps
CPU time 55.32 seconds
Started Sep 11 10:03:56 AM UTC 24
Finished Sep 11 10:05:06 AM UTC 24
Peak memory 154656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=78734380 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 115.prim_prince_test.78734380
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/115.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/116.prim_prince_test.269502892
Short name T125
Test name
Test status
Simulation time 3177462909 ps
CPU time 59.48 seconds
Started Sep 11 10:03:56 AM UTC 24
Finished Sep 11 10:05:12 AM UTC 24
Peak memory 154656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=269502892 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 116.prim_prince_test.269502892
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/116.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/117.prim_prince_test.4160695750
Short name T108
Test name
Test status
Simulation time 1592124202 ps
CPU time 30.77 seconds
Started Sep 11 10:04:01 AM UTC 24
Finished Sep 11 10:04:41 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4160695750 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 117.prim_prince_test.4160695750
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/117.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/118.prim_prince_test.3977481748
Short name T114
Test name
Test status
Simulation time 1757039747 ps
CPU time 33.5 seconds
Started Sep 11 10:04:06 AM UTC 24
Finished Sep 11 10:04:49 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3977481748 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 118.prim_prince_test.3977481748
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/118.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/119.prim_prince_test.2955716643
Short name T106
Test name
Test status
Simulation time 1015276162 ps
CPU time 19.74 seconds
Started Sep 11 10:04:09 AM UTC 24
Finished Sep 11 10:04:35 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2955716643 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 119.prim_prince_test.2955716643
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/119.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/12.prim_prince_test.136089454
Short name T3
Test name
Test status
Simulation time 1190271499 ps
CPU time 23.55 seconds
Started Sep 11 09:59:56 AM UTC 24
Finished Sep 11 10:00:28 AM UTC 24
Peak memory 154592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=136089454 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 12.prim_prince_test.136089454
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/12.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/120.prim_prince_test.3341308788
Short name T127
Test name
Test status
Simulation time 2924274066 ps
CPU time 54.22 seconds
Started Sep 11 10:04:12 AM UTC 24
Finished Sep 11 10:05:22 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3341308788 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 120.prim_prince_test.3341308788
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/120.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/121.prim_prince_test.4090145297
Short name T107
Test name
Test status
Simulation time 777702820 ps
CPU time 15.58 seconds
Started Sep 11 10:04:15 AM UTC 24
Finished Sep 11 10:04:35 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4090145297 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 121.prim_prince_test.4090145297
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/121.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/122.prim_prince_test.190445690
Short name T131
Test name
Test status
Simulation time 3220437680 ps
CPU time 59 seconds
Started Sep 11 10:04:16 AM UTC 24
Finished Sep 11 10:05:32 AM UTC 24
Peak memory 154656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=190445690 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 122.prim_prince_test.190445690
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/122.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/123.prim_prince_test.347104909
Short name T133
Test name
Test status
Simulation time 3259876527 ps
CPU time 63.18 seconds
Started Sep 11 10:04:21 AM UTC 24
Finished Sep 11 10:05:41 AM UTC 24
Peak memory 154656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=347104909 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 123.prim_prince_test.347104909
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/123.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/124.prim_prince_test.2777278877
Short name T132
Test name
Test status
Simulation time 3109143010 ps
CPU time 58.15 seconds
Started Sep 11 10:04:21 AM UTC 24
Finished Sep 11 10:05:36 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2777278877 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 124.prim_prince_test.2777278877
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/124.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/125.prim_prince_test.3811427646
Short name T130
Test name
Test status
Simulation time 2836438482 ps
CPU time 54.01 seconds
Started Sep 11 10:04:23 AM UTC 24
Finished Sep 11 10:05:32 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3811427646 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 125.prim_prince_test.3811427646
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/125.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/126.prim_prince_test.2505295468
Short name T121
Test name
Test status
Simulation time 1729614108 ps
CPU time 33.53 seconds
Started Sep 11 10:04:24 AM UTC 24
Finished Sep 11 10:05:07 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2505295468 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 126.prim_prince_test.2505295468
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/126.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/127.prim_prince_test.2896908621
Short name T129
Test name
Test status
Simulation time 2456450155 ps
CPU time 47.71 seconds
Started Sep 11 10:04:28 AM UTC 24
Finished Sep 11 10:05:29 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2896908621 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 127.prim_prince_test.2896908621
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/127.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/128.prim_prince_test.2116480977
Short name T115
Test name
Test status
Simulation time 766975963 ps
CPU time 15.03 seconds
Started Sep 11 10:04:31 AM UTC 24
Finished Sep 11 10:04:51 AM UTC 24
Peak memory 154340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2116480977 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 128.prim_prince_test.2116480977
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/128.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/129.prim_prince_test.1044137136
Short name T122
Test name
Test status
Simulation time 1281013608 ps
CPU time 25.29 seconds
Started Sep 11 10:04:35 AM UTC 24
Finished Sep 11 10:05:07 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1044137136 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 129.prim_prince_test.1044137136
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/129.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/13.prim_prince_test.2886218688
Short name T16
Test name
Test status
Simulation time 2982290059 ps
CPU time 59.06 seconds
Started Sep 11 09:59:56 AM UTC 24
Finished Sep 11 10:01:13 AM UTC 24
Peak memory 154656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2886218688 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 13.prim_prince_test.2886218688
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/13.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/130.prim_prince_test.2689241353
Short name T126
Test name
Test status
Simulation time 1808087262 ps
CPU time 35.51 seconds
Started Sep 11 10:04:35 AM UTC 24
Finished Sep 11 10:05:20 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2689241353 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 130.prim_prince_test.2689241353
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/130.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/131.prim_prince_test.2802527508
Short name T128
Test name
Test status
Simulation time 2152381789 ps
CPU time 40.4 seconds
Started Sep 11 10:04:36 AM UTC 24
Finished Sep 11 10:05:28 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2802527508 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 131.prim_prince_test.2802527508
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/131.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/132.prim_prince_test.1293916851
Short name T145
Test name
Test status
Simulation time 3566480153 ps
CPU time 68.17 seconds
Started Sep 11 10:04:36 AM UTC 24
Finished Sep 11 10:06:03 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1293916851 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 132.prim_prince_test.1293916851
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/132.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/133.prim_prince_test.3519008835
Short name T141
Test name
Test status
Simulation time 3338956523 ps
CPU time 62.51 seconds
Started Sep 11 10:04:41 AM UTC 24
Finished Sep 11 10:06:01 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3519008835 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 133.prim_prince_test.3519008835
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/133.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/134.prim_prince_test.2677637466
Short name T124
Test name
Test status
Simulation time 1130342752 ps
CPU time 21.57 seconds
Started Sep 11 10:04:42 AM UTC 24
Finished Sep 11 10:05:10 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2677637466 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 134.prim_prince_test.2677637466
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/134.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/135.prim_prince_test.2382546213
Short name T138
Test name
Test status
Simulation time 2883764895 ps
CPU time 56.76 seconds
Started Sep 11 10:04:45 AM UTC 24
Finished Sep 11 10:05:57 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2382546213 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 135.prim_prince_test.2382546213
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/135.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/136.prim_prince_test.281660381
Short name T137
Test name
Test status
Simulation time 2780747712 ps
CPU time 54.59 seconds
Started Sep 11 10:04:47 AM UTC 24
Finished Sep 11 10:05:57 AM UTC 24
Peak memory 154656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=281660381 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 136.prim_prince_test.281660381
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/136.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/137.prim_prince_test.1818657666
Short name T150
Test name
Test status
Simulation time 3565834363 ps
CPU time 66.96 seconds
Started Sep 11 10:04:49 AM UTC 24
Finished Sep 11 10:06:14 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1818657666 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 137.prim_prince_test.1818657666
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/137.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/138.prim_prince_test.1143021596
Short name T146
Test name
Test status
Simulation time 3213385003 ps
CPU time 62.3 seconds
Started Sep 11 10:04:50 AM UTC 24
Finished Sep 11 10:06:09 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1143021596 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 138.prim_prince_test.1143021596
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/138.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/139.prim_prince_test.2609370399
Short name T144
Test name
Test status
Simulation time 2965682072 ps
CPU time 57.04 seconds
Started Sep 11 10:04:50 AM UTC 24
Finished Sep 11 10:06:02 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2609370399 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 139.prim_prince_test.2609370399
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/139.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/14.prim_prince_test.985631066
Short name T25
Test name
Test status
Simulation time 3680991604 ps
CPU time 71.95 seconds
Started Sep 11 09:59:57 AM UTC 24
Finished Sep 11 10:01:30 AM UTC 24
Peak memory 154656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=985631066 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 14.prim_prince_test.985631066
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/14.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/140.prim_prince_test.3768511023
Short name T136
Test name
Test status
Simulation time 2553338560 ps
CPU time 51.07 seconds
Started Sep 11 10:04:52 AM UTC 24
Finished Sep 11 10:05:56 AM UTC 24
Peak memory 154356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3768511023 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 140.prim_prince_test.3768511023
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/140.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/141.prim_prince_test.1828792300
Short name T135
Test name
Test status
Simulation time 2258465102 ps
CPU time 41.72 seconds
Started Sep 11 10:04:52 AM UTC 24
Finished Sep 11 10:05:46 AM UTC 24
Peak memory 154276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1828792300 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 141.prim_prince_test.1828792300
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/141.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/142.prim_prince_test.2295869550
Short name T142
Test name
Test status
Simulation time 2703326029 ps
CPU time 53.7 seconds
Started Sep 11 10:04:53 AM UTC 24
Finished Sep 11 10:06:01 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2295869550 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 142.prim_prince_test.2295869550
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/142.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/143.prim_prince_test.3568529754
Short name T149
Test name
Test status
Simulation time 2947724324 ps
CPU time 59.2 seconds
Started Sep 11 10:04:57 AM UTC 24
Finished Sep 11 10:06:12 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3568529754 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 143.prim_prince_test.3568529754
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/143.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/144.prim_prince_test.3632948761
Short name T143
Test name
Test status
Simulation time 2407726720 ps
CPU time 47.91 seconds
Started Sep 11 10:05:01 AM UTC 24
Finished Sep 11 10:06:02 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3632948761 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 144.prim_prince_test.3632948761
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/144.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/145.prim_prince_test.4017543984
Short name T139
Test name
Test status
Simulation time 2123381015 ps
CPU time 41.11 seconds
Started Sep 11 10:05:07 AM UTC 24
Finished Sep 11 10:06:00 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4017543984 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 145.prim_prince_test.4017543984
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/145.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/146.prim_prince_test.1256185340
Short name T134
Test name
Test status
Simulation time 1429477413 ps
CPU time 28.27 seconds
Started Sep 11 10:05:07 AM UTC 24
Finished Sep 11 10:05:44 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1256185340 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 146.prim_prince_test.1256185340
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/146.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/147.prim_prince_test.1180385419
Short name T140
Test name
Test status
Simulation time 2065575254 ps
CPU time 41.22 seconds
Started Sep 11 10:05:08 AM UTC 24
Finished Sep 11 10:06:01 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1180385419 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 147.prim_prince_test.1180385419
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/147.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/148.prim_prince_test.1159113771
Short name T148
Test name
Test status
Simulation time 2349563131 ps
CPU time 47.31 seconds
Started Sep 11 10:05:12 AM UTC 24
Finished Sep 11 10:06:12 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1159113771 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 148.prim_prince_test.1159113771
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/148.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/149.prim_prince_test.2663994206
Short name T153
Test name
Test status
Simulation time 2789991721 ps
CPU time 54.87 seconds
Started Sep 11 10:05:12 AM UTC 24
Finished Sep 11 10:06:21 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2663994206 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 149.prim_prince_test.2663994206
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/149.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/15.prim_prince_test.673515516
Short name T21
Test name
Test status
Simulation time 3254973163 ps
CPU time 65.36 seconds
Started Sep 11 09:59:57 AM UTC 24
Finished Sep 11 10:01:21 AM UTC 24
Peak memory 154656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=673515516 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 15.prim_prince_test.673515516
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/15.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/150.prim_prince_test.2905429834
Short name T152
Test name
Test status
Simulation time 2663889110 ps
CPU time 52.91 seconds
Started Sep 11 10:05:13 AM UTC 24
Finished Sep 11 10:06:20 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2905429834 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 150.prim_prince_test.2905429834
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/150.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/151.prim_prince_test.384352553
Short name T157
Test name
Test status
Simulation time 2777068967 ps
CPU time 51.98 seconds
Started Sep 11 10:05:18 AM UTC 24
Finished Sep 11 10:06:25 AM UTC 24
Peak memory 154656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=384352553 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 151.prim_prince_test.384352553
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/151.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/152.prim_prince_test.4115870296
Short name T151
Test name
Test status
Simulation time 2134833722 ps
CPU time 42.89 seconds
Started Sep 11 10:05:21 AM UTC 24
Finished Sep 11 10:06:16 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4115870296 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 152.prim_prince_test.4115870296
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/152.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/153.prim_prince_test.134404055
Short name T163
Test name
Test status
Simulation time 3281595323 ps
CPU time 64.41 seconds
Started Sep 11 10:05:23 AM UTC 24
Finished Sep 11 10:06:45 AM UTC 24
Peak memory 156112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=134404055 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 153.prim_prince_test.134404055
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/153.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/154.prim_prince_test.1424766963
Short name T147
Test name
Test status
Simulation time 1688216112 ps
CPU time 32.42 seconds
Started Sep 11 10:05:29 AM UTC 24
Finished Sep 11 10:06:11 AM UTC 24
Peak memory 154540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1424766963 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 154.prim_prince_test.1424766963
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/154.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/155.prim_prince_test.1810644974
Short name T161
Test name
Test status
Simulation time 2723072933 ps
CPU time 50.46 seconds
Started Sep 11 10:05:29 AM UTC 24
Finished Sep 11 10:06:35 AM UTC 24
Peak memory 154644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1810644974 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 155.prim_prince_test.1810644974
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/155.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/156.prim_prince_test.80669345
Short name T154
Test name
Test status
Simulation time 2089844490 ps
CPU time 39.13 seconds
Started Sep 11 10:05:33 AM UTC 24
Finished Sep 11 10:06:23 AM UTC 24
Peak memory 154592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=80669345 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 156.prim_prince_test.80669345
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/156.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/157.prim_prince_test.3701910478
Short name T159
Test name
Test status
Simulation time 2116317007 ps
CPU time 42.2 seconds
Started Sep 11 10:05:34 AM UTC 24
Finished Sep 11 10:06:27 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3701910478 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 157.prim_prince_test.3701910478
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/157.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/158.prim_prince_test.3088353670
Short name T173
Test name
Test status
Simulation time 3695718258 ps
CPU time 72.68 seconds
Started Sep 11 10:05:37 AM UTC 24
Finished Sep 11 10:07:09 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3088353670 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 158.prim_prince_test.3088353670
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/158.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/159.prim_prince_test.3553557300
Short name T165
Test name
Test status
Simulation time 2615779083 ps
CPU time 50.81 seconds
Started Sep 11 10:05:42 AM UTC 24
Finished Sep 11 10:06:47 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3553557300 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 159.prim_prince_test.3553557300
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/159.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/16.prim_prince_test.1145610934
Short name T12
Test name
Test status
Simulation time 2358469056 ps
CPU time 46.44 seconds
Started Sep 11 09:59:57 AM UTC 24
Finished Sep 11 10:00:58 AM UTC 24
Peak memory 154656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1145610934 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 16.prim_prince_test.1145610934
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/16.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/160.prim_prince_test.1084639700
Short name T166
Test name
Test status
Simulation time 2690415300 ps
CPU time 54.04 seconds
Started Sep 11 10:05:44 AM UTC 24
Finished Sep 11 10:06:52 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1084639700 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 160.prim_prince_test.1084639700
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/160.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/161.prim_prince_test.1265226245
Short name T160
Test name
Test status
Simulation time 1718378427 ps
CPU time 32.17 seconds
Started Sep 11 10:05:46 AM UTC 24
Finished Sep 11 10:06:28 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1265226245 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 161.prim_prince_test.1265226245
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/161.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/162.prim_prince_test.3743047334
Short name T158
Test name
Test status
Simulation time 1053938998 ps
CPU time 21.81 seconds
Started Sep 11 10:05:57 AM UTC 24
Finished Sep 11 10:06:25 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3743047334 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 162.prim_prince_test.3743047334
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/162.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/163.prim_prince_test.2658028243
Short name T155
Test name
Test status
Simulation time 1031194086 ps
CPU time 20.48 seconds
Started Sep 11 10:05:57 AM UTC 24
Finished Sep 11 10:06:24 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2658028243 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 163.prim_prince_test.2658028243
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/163.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/164.prim_prince_test.3943269210
Short name T178
Test name
Test status
Simulation time 3238596798 ps
CPU time 60.46 seconds
Started Sep 11 10:05:58 AM UTC 24
Finished Sep 11 10:07:16 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3943269210 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 164.prim_prince_test.3943269210
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/164.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/165.prim_prince_test.4263908792
Short name T177
Test name
Test status
Simulation time 2801714876 ps
CPU time 56.4 seconds
Started Sep 11 10:06:00 AM UTC 24
Finished Sep 11 10:07:11 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4263908792 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 165.prim_prince_test.4263908792
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/165.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/166.prim_prince_test.2277327312
Short name T176
Test name
Test status
Simulation time 2782894411 ps
CPU time 53.63 seconds
Started Sep 11 10:06:02 AM UTC 24
Finished Sep 11 10:07:10 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2277327312 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 166.prim_prince_test.2277327312
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/166.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/167.prim_prince_test.1417641679
Short name T179
Test name
Test status
Simulation time 3135510308 ps
CPU time 59.59 seconds
Started Sep 11 10:06:02 AM UTC 24
Finished Sep 11 10:07:18 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1417641679 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 167.prim_prince_test.1417641679
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/167.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/168.prim_prince_test.2198600247
Short name T182
Test name
Test status
Simulation time 3194036116 ps
CPU time 60.98 seconds
Started Sep 11 10:06:03 AM UTC 24
Finished Sep 11 10:07:21 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2198600247 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 168.prim_prince_test.2198600247
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/168.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/169.prim_prince_test.768638523
Short name T171
Test name
Test status
Simulation time 2683935102 ps
CPU time 50.27 seconds
Started Sep 11 10:06:03 AM UTC 24
Finished Sep 11 10:07:07 AM UTC 24
Peak memory 154656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=768638523 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 169.prim_prince_test.768638523
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/169.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/17.prim_prince_test.1890735650
Short name T8
Test name
Test status
Simulation time 1582637298 ps
CPU time 31.95 seconds
Started Sep 11 09:59:57 AM UTC 24
Finished Sep 11 10:00:39 AM UTC 24
Peak memory 154592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1890735650 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 17.prim_prince_test.1890735650
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/17.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/170.prim_prince_test.3347752872
Short name T184
Test name
Test status
Simulation time 3610363021 ps
CPU time 69.16 seconds
Started Sep 11 10:06:03 AM UTC 24
Finished Sep 11 10:07:31 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3347752872 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 170.prim_prince_test.3347752872
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/170.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/171.prim_prince_test.1183810679
Short name T156
Test name
Test status
Simulation time 815548975 ps
CPU time 16.09 seconds
Started Sep 11 10:06:04 AM UTC 24
Finished Sep 11 10:06:25 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1183810679 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 171.prim_prince_test.1183810679
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/171.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/172.prim_prince_test.3056900623
Short name T187
Test name
Test status
Simulation time 3332068396 ps
CPU time 67.17 seconds
Started Sep 11 10:06:10 AM UTC 24
Finished Sep 11 10:07:34 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3056900623 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 172.prim_prince_test.3056900623
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/172.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/173.prim_prince_test.2070211084
Short name T188
Test name
Test status
Simulation time 3423456086 ps
CPU time 66.08 seconds
Started Sep 11 10:06:12 AM UTC 24
Finished Sep 11 10:07:36 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2070211084 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 173.prim_prince_test.2070211084
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/173.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/174.prim_prince_test.945452485
Short name T183
Test name
Test status
Simulation time 2696858502 ps
CPU time 54.54 seconds
Started Sep 11 10:06:12 AM UTC 24
Finished Sep 11 10:07:21 AM UTC 24
Peak memory 154656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=945452485 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 174.prim_prince_test.945452485
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/174.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/175.prim_prince_test.802231869
Short name T180
Test name
Test status
Simulation time 2619256633 ps
CPU time 52.73 seconds
Started Sep 11 10:06:13 AM UTC 24
Finished Sep 11 10:07:20 AM UTC 24
Peak memory 154656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=802231869 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 175.prim_prince_test.802231869
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/175.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/176.prim_prince_test.3227625564
Short name T162
Test name
Test status
Simulation time 1094863216 ps
CPU time 21.09 seconds
Started Sep 11 10:06:15 AM UTC 24
Finished Sep 11 10:06:43 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3227625564 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 176.prim_prince_test.3227625564
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/176.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/177.prim_prince_test.2224338379
Short name T167
Test name
Test status
Simulation time 1734666689 ps
CPU time 32.26 seconds
Started Sep 11 10:06:17 AM UTC 24
Finished Sep 11 10:06:58 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2224338379 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 177.prim_prince_test.2224338379
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/177.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/178.prim_prince_test.696936257
Short name T194
Test name
Test status
Simulation time 3609812571 ps
CPU time 70 seconds
Started Sep 11 10:06:21 AM UTC 24
Finished Sep 11 10:07:50 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=696936257 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 178.prim_prince_test.696936257
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/178.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/179.prim_prince_test.2491403269
Short name T175
Test name
Test status
Simulation time 1926026953 ps
CPU time 38.95 seconds
Started Sep 11 10:06:21 AM UTC 24
Finished Sep 11 10:07:10 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2491403269 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 179.prim_prince_test.2491403269
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/179.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/18.prim_prince_test.720185309
Short name T20
Test name
Test status
Simulation time 2899016967 ps
CPU time 57.57 seconds
Started Sep 11 09:59:58 AM UTC 24
Finished Sep 11 10:01:20 AM UTC 24
Peak memory 154656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=720185309 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 18.prim_prince_test.720185309
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/18.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/180.prim_prince_test.2857141152
Short name T192
Test name
Test status
Simulation time 3121442678 ps
CPU time 63.5 seconds
Started Sep 11 10:06:22 AM UTC 24
Finished Sep 11 10:07:41 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2857141152 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 180.prim_prince_test.2857141152
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/180.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/181.prim_prince_test.1546187397
Short name T168
Test name
Test status
Simulation time 1360272766 ps
CPU time 27.14 seconds
Started Sep 11 10:06:24 AM UTC 24
Finished Sep 11 10:06:59 AM UTC 24
Peak memory 156040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1546187397 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 181.prim_prince_test.1546187397
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/181.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/182.prim_prince_test.1739661751
Short name T164
Test name
Test status
Simulation time 789307797 ps
CPU time 15.15 seconds
Started Sep 11 10:06:25 AM UTC 24
Finished Sep 11 10:06:45 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1739661751 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 182.prim_prince_test.1739661751
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/182.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/183.prim_prince_test.4129432915
Short name T189
Test name
Test status
Simulation time 2876586586 ps
CPU time 54.74 seconds
Started Sep 11 10:06:26 AM UTC 24
Finished Sep 11 10:07:37 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4129432915 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 183.prim_prince_test.4129432915
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/183.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/184.prim_prince_test.522769515
Short name T172
Test name
Test status
Simulation time 1584373952 ps
CPU time 32.78 seconds
Started Sep 11 10:06:26 AM UTC 24
Finished Sep 11 10:07:08 AM UTC 24
Peak memory 154592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=522769515 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 184.prim_prince_test.522769515
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/184.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/185.prim_prince_test.3048906094
Short name T185
Test name
Test status
Simulation time 2612646461 ps
CPU time 50.22 seconds
Started Sep 11 10:06:26 AM UTC 24
Finished Sep 11 10:07:31 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3048906094 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 185.prim_prince_test.3048906094
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/185.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/186.prim_prince_test.3008879374
Short name T169
Test name
Test status
Simulation time 1418664919 ps
CPU time 29.37 seconds
Started Sep 11 10:06:29 AM UTC 24
Finished Sep 11 10:07:06 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3008879374 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 186.prim_prince_test.3008879374
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/186.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/187.prim_prince_test.2136398534
Short name T170
Test name
Test status
Simulation time 1499729236 ps
CPU time 30.31 seconds
Started Sep 11 10:06:29 AM UTC 24
Finished Sep 11 10:07:07 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2136398534 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 187.prim_prince_test.2136398534
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/187.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/188.prim_prince_test.3106389858
Short name T195
Test name
Test status
Simulation time 2943458539 ps
CPU time 58.9 seconds
Started Sep 11 10:06:36 AM UTC 24
Finished Sep 11 10:07:50 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3106389858 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 188.prim_prince_test.3106389858
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/188.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/189.prim_prince_test.1375161061
Short name T186
Test name
Test status
Simulation time 1885011258 ps
CPU time 37.81 seconds
Started Sep 11 10:06:44 AM UTC 24
Finished Sep 11 10:07:32 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1375161061 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 189.prim_prince_test.1375161061
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/189.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/19.prim_prince_test.1702435214
Short name T17
Test name
Test status
Simulation time 2711816111 ps
CPU time 54.27 seconds
Started Sep 11 09:59:58 AM UTC 24
Finished Sep 11 10:01:15 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1702435214 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 19.prim_prince_test.1702435214
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/19.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/190.prim_prince_test.2229555533
Short name T204
Test name
Test status
Simulation time 3384297210 ps
CPU time 68.35 seconds
Started Sep 11 10:06:46 AM UTC 24
Finished Sep 11 10:08:12 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2229555533 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 190.prim_prince_test.2229555533
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/190.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/191.prim_prince_test.1291727536
Short name T200
Test name
Test status
Simulation time 2852817051 ps
CPU time 57.63 seconds
Started Sep 11 10:06:46 AM UTC 24
Finished Sep 11 10:07:59 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1291727536 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 191.prim_prince_test.1291727536
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/191.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/192.prim_prince_test.1323422356
Short name T174
Test name
Test status
Simulation time 793418797 ps
CPU time 16.01 seconds
Started Sep 11 10:06:48 AM UTC 24
Finished Sep 11 10:07:09 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1323422356 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 192.prim_prince_test.1323422356
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/192.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/193.prim_prince_test.1279170365
Short name T191
Test name
Test status
Simulation time 1825994996 ps
CPU time 35.95 seconds
Started Sep 11 10:06:53 AM UTC 24
Finished Sep 11 10:07:39 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1279170365 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 193.prim_prince_test.1279170365
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/193.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/194.prim_prince_test.3148322341
Short name T181
Test name
Test status
Simulation time 785901232 ps
CPU time 16.43 seconds
Started Sep 11 10:06:59 AM UTC 24
Finished Sep 11 10:07:20 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3148322341 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 194.prim_prince_test.3148322341
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/194.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/195.prim_prince_test.1365278360
Short name T197
Test name
Test status
Simulation time 2127976461 ps
CPU time 43.64 seconds
Started Sep 11 10:06:59 AM UTC 24
Finished Sep 11 10:07:54 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1365278360 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 195.prim_prince_test.1365278360
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/195.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/196.prim_prince_test.3263210201
Short name T214
Test name
Test status
Simulation time 3412507495 ps
CPU time 65 seconds
Started Sep 11 10:07:06 AM UTC 24
Finished Sep 11 10:08:29 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3263210201 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 196.prim_prince_test.3263210201
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/196.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/197.prim_prince_test.4082219574
Short name T218
Test name
Test status
Simulation time 3585894817 ps
CPU time 68.65 seconds
Started Sep 11 10:07:08 AM UTC 24
Finished Sep 11 10:08:35 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4082219574 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 197.prim_prince_test.4082219574
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/197.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/198.prim_prince_test.2332931718
Short name T199
Test name
Test status
Simulation time 1904879057 ps
CPU time 39.36 seconds
Started Sep 11 10:07:09 AM UTC 24
Finished Sep 11 10:07:58 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2332931718 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 198.prim_prince_test.2332931718
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/198.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/199.prim_prince_test.4169508604
Short name T201
Test name
Test status
Simulation time 2093679776 ps
CPU time 40.13 seconds
Started Sep 11 10:07:09 AM UTC 24
Finished Sep 11 10:08:00 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4169508604 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 199.prim_prince_test.4169508604
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/199.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/2.prim_prince_test.3908910910
Short name T7
Test name
Test status
Simulation time 1604182180 ps
CPU time 32.47 seconds
Started Sep 11 09:59:56 AM UTC 24
Finished Sep 11 10:00:39 AM UTC 24
Peak memory 154528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3908910910 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 2.prim_prince_test.3908910910
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/2.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/20.prim_prince_test.1790313990
Short name T24
Test name
Test status
Simulation time 3213807420 ps
CPU time 63.44 seconds
Started Sep 11 09:59:59 AM UTC 24
Finished Sep 11 10:01:27 AM UTC 24
Peak memory 154656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1790313990 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 20.prim_prince_test.1790313990
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/20.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/200.prim_prince_test.3087261273
Short name T215
Test name
Test status
Simulation time 3184375564 ps
CPU time 63.27 seconds
Started Sep 11 10:07:10 AM UTC 24
Finished Sep 11 10:08:30 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3087261273 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 200.prim_prince_test.3087261273
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/200.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/201.prim_prince_test.1571121301
Short name T196
Test name
Test status
Simulation time 1676823119 ps
CPU time 33.31 seconds
Started Sep 11 10:07:10 AM UTC 24
Finished Sep 11 10:07:52 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1571121301 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 201.prim_prince_test.1571121301
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/201.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/202.prim_prince_test.2087117089
Short name T203
Test name
Test status
Simulation time 2107643668 ps
CPU time 43.45 seconds
Started Sep 11 10:07:11 AM UTC 24
Finished Sep 11 10:08:06 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2087117089 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 202.prim_prince_test.2087117089
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/202.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/203.prim_prince_test.2635145517
Short name T198
Test name
Test status
Simulation time 1787343106 ps
CPU time 34.49 seconds
Started Sep 11 10:07:11 AM UTC 24
Finished Sep 11 10:07:56 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2635145517 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 203.prim_prince_test.2635145517
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/203.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/204.prim_prince_test.2477155633
Short name T193
Test name
Test status
Simulation time 1193980475 ps
CPU time 25 seconds
Started Sep 11 10:07:12 AM UTC 24
Finished Sep 11 10:07:44 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2477155633 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 204.prim_prince_test.2477155633
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/204.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/205.prim_prince_test.1814848477
Short name T190
Test name
Test status
Simulation time 842709658 ps
CPU time 17.46 seconds
Started Sep 11 10:07:16 AM UTC 24
Finished Sep 11 10:07:39 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1814848477 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 205.prim_prince_test.1814848477
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/205.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/206.prim_prince_test.2352140557
Short name T207
Test name
Test status
Simulation time 2295562339 ps
CPU time 46.44 seconds
Started Sep 11 10:07:18 AM UTC 24
Finished Sep 11 10:08:17 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2352140557 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 206.prim_prince_test.2352140557
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/206.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/207.prim_prince_test.3490598153
Short name T202
Test name
Test status
Simulation time 1751474012 ps
CPU time 33.33 seconds
Started Sep 11 10:07:21 AM UTC 24
Finished Sep 11 10:08:04 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3490598153 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 207.prim_prince_test.3490598153
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/207.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/208.prim_prince_test.3029058188
Short name T217
Test name
Test status
Simulation time 2785356080 ps
CPU time 55.84 seconds
Started Sep 11 10:07:22 AM UTC 24
Finished Sep 11 10:08:32 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3029058188 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 208.prim_prince_test.3029058188
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/208.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/209.prim_prince_test.4080227999
Short name T225
Test name
Test status
Simulation time 3678326028 ps
CPU time 70.3 seconds
Started Sep 11 10:07:22 AM UTC 24
Finished Sep 11 10:08:52 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4080227999 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 209.prim_prince_test.4080227999
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/209.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/21.prim_prince_test.3378762643
Short name T10
Test name
Test status
Simulation time 1816012804 ps
CPU time 37.54 seconds
Started Sep 11 10:00:02 AM UTC 24
Finished Sep 11 10:00:53 AM UTC 24
Peak memory 154592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3378762643 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 21.prim_prince_test.3378762643
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/21.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/210.prim_prince_test.983514256
Short name T222
Test name
Test status
Simulation time 3398077753 ps
CPU time 63.2 seconds
Started Sep 11 10:07:22 AM UTC 24
Finished Sep 11 10:08:43 AM UTC 24
Peak memory 154656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=983514256 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 210.prim_prince_test.983514256
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/210.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/211.prim_prince_test.2337830337
Short name T230
Test name
Test status
Simulation time 3409528655 ps
CPU time 64.7 seconds
Started Sep 11 10:07:32 AM UTC 24
Finished Sep 11 10:08:55 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2337830337 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 211.prim_prince_test.2337830337
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/211.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/212.prim_prince_test.574537293
Short name T213
Test name
Test status
Simulation time 2300279632 ps
CPU time 43.82 seconds
Started Sep 11 10:07:32 AM UTC 24
Finished Sep 11 10:08:29 AM UTC 24
Peak memory 154656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=574537293 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 212.prim_prince_test.574537293
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/212.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/213.prim_prince_test.1883397390
Short name T232
Test name
Test status
Simulation time 3522968057 ps
CPU time 69.94 seconds
Started Sep 11 10:07:33 AM UTC 24
Finished Sep 11 10:09:01 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1883397390 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 213.prim_prince_test.1883397390
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/213.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/214.prim_prince_test.275823050
Short name T219
Test name
Test status
Simulation time 2502989911 ps
CPU time 50.68 seconds
Started Sep 11 10:07:35 AM UTC 24
Finished Sep 11 10:08:39 AM UTC 24
Peak memory 154656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=275823050 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 214.prim_prince_test.275823050
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/214.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/215.prim_prince_test.984865659
Short name T205
Test name
Test status
Simulation time 1432880123 ps
CPU time 27.77 seconds
Started Sep 11 10:07:37 AM UTC 24
Finished Sep 11 10:08:13 AM UTC 24
Peak memory 154592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=984865659 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 215.prim_prince_test.984865659
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/215.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/216.prim_prince_test.750950883
Short name T224
Test name
Test status
Simulation time 2976462998 ps
CPU time 57.33 seconds
Started Sep 11 10:07:37 AM UTC 24
Finished Sep 11 10:08:51 AM UTC 24
Peak memory 154656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=750950883 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 216.prim_prince_test.750950883
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/216.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/217.prim_prince_test.1034211128
Short name T221
Test name
Test status
Simulation time 2456547754 ps
CPU time 48.5 seconds
Started Sep 11 10:07:40 AM UTC 24
Finished Sep 11 10:08:41 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1034211128 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 217.prim_prince_test.1034211128
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/217.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/218.prim_prince_test.454079503
Short name T220
Test name
Test status
Simulation time 2357090978 ps
CPU time 47.37 seconds
Started Sep 11 10:07:40 AM UTC 24
Finished Sep 11 10:08:40 AM UTC 24
Peak memory 154656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=454079503 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 218.prim_prince_test.454079503
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/218.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/219.prim_prince_test.183319864
Short name T208
Test name
Test status
Simulation time 1554625111 ps
CPU time 29.04 seconds
Started Sep 11 10:07:42 AM UTC 24
Finished Sep 11 10:08:20 AM UTC 24
Peak memory 154592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=183319864 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 219.prim_prince_test.183319864
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/219.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/22.prim_prince_test.270458204
Short name T26
Test name
Test status
Simulation time 2831577998 ps
CPU time 56.18 seconds
Started Sep 11 10:00:20 AM UTC 24
Finished Sep 11 10:01:32 AM UTC 24
Peak memory 154656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=270458204 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 22.prim_prince_test.270458204
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/22.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/220.prim_prince_test.1149112171
Short name T206
Test name
Test status
Simulation time 1131095228 ps
CPU time 22 seconds
Started Sep 11 10:07:45 AM UTC 24
Finished Sep 11 10:08:14 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1149112171 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 220.prim_prince_test.1149112171
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/220.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/221.prim_prince_test.2425332529
Short name T210
Test name
Test status
Simulation time 1155425159 ps
CPU time 23.49 seconds
Started Sep 11 10:07:50 AM UTC 24
Finished Sep 11 10:08:20 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2425332529 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 221.prim_prince_test.2425332529
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/221.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/222.prim_prince_test.4288781012
Short name T227
Test name
Test status
Simulation time 2452157258 ps
CPU time 49.03 seconds
Started Sep 11 10:07:51 AM UTC 24
Finished Sep 11 10:08:53 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4288781012 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 222.prim_prince_test.4288781012
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/222.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/223.prim_prince_test.1475768822
Short name T242
Test name
Test status
Simulation time 3257477394 ps
CPU time 62.91 seconds
Started Sep 11 10:07:53 AM UTC 24
Finished Sep 11 10:09:13 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1475768822 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 223.prim_prince_test.1475768822
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/223.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/224.prim_prince_test.1788836324
Short name T216
Test name
Test status
Simulation time 1409047384 ps
CPU time 27.35 seconds
Started Sep 11 10:07:55 AM UTC 24
Finished Sep 11 10:08:31 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1788836324 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 224.prim_prince_test.1788836324
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/224.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/225.prim_prince_test.430796999
Short name T212
Test name
Test status
Simulation time 1181183742 ps
CPU time 23.9 seconds
Started Sep 11 10:07:56 AM UTC 24
Finished Sep 11 10:08:27 AM UTC 24
Peak memory 154592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=430796999 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 225.prim_prince_test.430796999
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/225.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/226.prim_prince_test.2836783903
Short name T209
Test name
Test status
Simulation time 776451950 ps
CPU time 15.35 seconds
Started Sep 11 10:08:00 AM UTC 24
Finished Sep 11 10:08:20 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2836783903 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 226.prim_prince_test.2836783903
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/226.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/227.prim_prince_test.4064500228
Short name T211
Test name
Test status
Simulation time 1020097685 ps
CPU time 20.61 seconds
Started Sep 11 10:08:00 AM UTC 24
Finished Sep 11 10:08:26 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4064500228 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 227.prim_prince_test.4064500228
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/227.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/228.prim_prince_test.332262195
Short name T240
Test name
Test status
Simulation time 2776356183 ps
CPU time 54.41 seconds
Started Sep 11 10:08:01 AM UTC 24
Finished Sep 11 10:09:10 AM UTC 24
Peak memory 154656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=332262195 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 228.prim_prince_test.332262195
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/228.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/229.prim_prince_test.266371114
Short name T246
Test name
Test status
Simulation time 3127810054 ps
CPU time 62.09 seconds
Started Sep 11 10:08:04 AM UTC 24
Finished Sep 11 10:09:23 AM UTC 24
Peak memory 154656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=266371114 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 229.prim_prince_test.266371114
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/229.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/23.prim_prince_test.1821396907
Short name T18
Test name
Test status
Simulation time 2015239832 ps
CPU time 40.61 seconds
Started Sep 11 10:00:24 AM UTC 24
Finished Sep 11 10:01:16 AM UTC 24
Peak memory 154592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1821396907 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 23.prim_prince_test.1821396907
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/23.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/230.prim_prince_test.2057727873
Short name T226
Test name
Test status
Simulation time 3651181570 ps
CPU time 68.1 seconds
Started Sep 11 10:08:07 AM UTC 24
Finished Sep 11 10:09:34 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2057727873 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 230.prim_prince_test.2057727873
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/230.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/231.prim_prince_test.1598017297
Short name T233
Test name
Test status
Simulation time 1970059812 ps
CPU time 38.43 seconds
Started Sep 11 10:08:13 AM UTC 24
Finished Sep 11 10:09:02 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1598017297 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 231.prim_prince_test.1598017297
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/231.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/232.prim_prince_test.2380557893
Short name T235
Test name
Test status
Simulation time 2050324074 ps
CPU time 40.3 seconds
Started Sep 11 10:08:14 AM UTC 24
Finished Sep 11 10:09:06 AM UTC 24
Peak memory 154488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2380557893 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 232.prim_prince_test.2380557893
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/232.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/233.prim_prince_test.1000482325
Short name T241
Test name
Test status
Simulation time 2349024997 ps
CPU time 44.77 seconds
Started Sep 11 10:08:14 AM UTC 24
Finished Sep 11 10:09:12 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1000482325 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 233.prim_prince_test.1000482325
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/233.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/234.prim_prince_test.3418888906
Short name T229
Test name
Test status
Simulation time 1467798795 ps
CPU time 29.07 seconds
Started Sep 11 10:08:18 AM UTC 24
Finished Sep 11 10:08:55 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3418888906 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 234.prim_prince_test.3418888906
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/234.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/235.prim_prince_test.1121924974
Short name T223
Test name
Test status
Simulation time 1144284967 ps
CPU time 23.08 seconds
Started Sep 11 10:08:21 AM UTC 24
Finished Sep 11 10:08:51 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1121924974 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 235.prim_prince_test.1121924974
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/235.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/236.prim_prince_test.2606004718
Short name T231
Test name
Test status
Simulation time 1613254514 ps
CPU time 31.06 seconds
Started Sep 11 10:08:21 AM UTC 24
Finished Sep 11 10:09:01 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2606004718 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 236.prim_prince_test.2606004718
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/236.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/237.prim_prince_test.4051918134
Short name T248
Test name
Test status
Simulation time 2712504513 ps
CPU time 51.42 seconds
Started Sep 11 10:08:21 AM UTC 24
Finished Sep 11 10:09:27 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4051918134 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 237.prim_prince_test.4051918134
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/237.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/238.prim_prince_test.2648511237
Short name T245
Test name
Test status
Simulation time 2013682115 ps
CPU time 39.72 seconds
Started Sep 11 10:08:27 AM UTC 24
Finished Sep 11 10:09:18 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2648511237 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 238.prim_prince_test.2648511237
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/238.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/239.prim_prince_test.2128458795
Short name T259
Test name
Test status
Simulation time 3351612787 ps
CPU time 64.91 seconds
Started Sep 11 10:08:28 AM UTC 24
Finished Sep 11 10:09:50 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2128458795 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 239.prim_prince_test.2128458795
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/239.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/24.prim_prince_test.962472671
Short name T15
Test name
Test status
Simulation time 1466878924 ps
CPU time 29.08 seconds
Started Sep 11 10:00:29 AM UTC 24
Finished Sep 11 10:01:07 AM UTC 24
Peak memory 154592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=962472671 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 24.prim_prince_test.962472671
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/24.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/240.prim_prince_test.1913692144
Short name T234
Test name
Test status
Simulation time 1275721923 ps
CPU time 25.56 seconds
Started Sep 11 10:08:29 AM UTC 24
Finished Sep 11 10:09:02 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1913692144 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 240.prim_prince_test.1913692144
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/240.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/241.prim_prince_test.3727174961
Short name T237
Test name
Test status
Simulation time 1456180274 ps
CPU time 28.74 seconds
Started Sep 11 10:08:31 AM UTC 24
Finished Sep 11 10:09:07 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3727174961 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 241.prim_prince_test.3727174961
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/241.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/242.prim_prince_test.705357537
Short name T228
Test name
Test status
Simulation time 883354556 ps
CPU time 17.71 seconds
Started Sep 11 10:08:31 AM UTC 24
Finished Sep 11 10:08:54 AM UTC 24
Peak memory 154592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=705357537 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 242.prim_prince_test.705357537
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/242.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/243.prim_prince_test.78134865
Short name T247
Test name
Test status
Simulation time 2101111510 ps
CPU time 41.35 seconds
Started Sep 11 10:08:32 AM UTC 24
Finished Sep 11 10:09:24 AM UTC 24
Peak memory 154592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=78134865 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 243.prim_prince_test.78134865
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/243.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/244.prim_prince_test.1013802533
Short name T236
Test name
Test status
Simulation time 1353523937 ps
CPU time 26.83 seconds
Started Sep 11 10:08:33 AM UTC 24
Finished Sep 11 10:09:07 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1013802533 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 244.prim_prince_test.1013802533
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/244.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/245.prim_prince_test.3418444412
Short name T249
Test name
Test status
Simulation time 2170950635 ps
CPU time 41.3 seconds
Started Sep 11 10:08:36 AM UTC 24
Finished Sep 11 10:09:29 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3418444412 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 245.prim_prince_test.3418444412
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/245.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/246.prim_prince_test.3224103965
Short name T238
Test name
Test status
Simulation time 1068504918 ps
CPU time 21.59 seconds
Started Sep 11 10:08:40 AM UTC 24
Finished Sep 11 10:09:08 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3224103965 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 246.prim_prince_test.3224103965
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/246.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/247.prim_prince_test.3242504222
Short name T260
Test name
Test status
Simulation time 2944270134 ps
CPU time 55.5 seconds
Started Sep 11 10:08:40 AM UTC 24
Finished Sep 11 10:09:51 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3242504222 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 247.prim_prince_test.3242504222
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/247.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/248.prim_prince_test.3430765193
Short name T239
Test name
Test status
Simulation time 1006390571 ps
CPU time 20.03 seconds
Started Sep 11 10:08:42 AM UTC 24
Finished Sep 11 10:09:08 AM UTC 24
Peak memory 154580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3430765193 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 248.prim_prince_test.3430765193
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/248.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/249.prim_prince_test.3177839155
Short name T271
Test name
Test status
Simulation time 3458013995 ps
CPU time 69.08 seconds
Started Sep 11 10:08:43 AM UTC 24
Finished Sep 11 10:10:10 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3177839155 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 249.prim_prince_test.3177839155
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/249.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/25.prim_prince_test.3909147817
Short name T36
Test name
Test status
Simulation time 3408666357 ps
CPU time 66.81 seconds
Started Sep 11 10:00:30 AM UTC 24
Finished Sep 11 10:01:55 AM UTC 24
Peak memory 154656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3909147817 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 25.prim_prince_test.3909147817
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/25.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/250.prim_prince_test.189950956
Short name T276
Test name
Test status
Simulation time 3577692974 ps
CPU time 68.49 seconds
Started Sep 11 10:08:52 AM UTC 24
Finished Sep 11 10:10:18 AM UTC 24
Peak memory 154656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=189950956 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 250.prim_prince_test.189950956
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/250.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/251.prim_prince_test.4006668299
Short name T244
Test name
Test status
Simulation time 996027215 ps
CPU time 19.83 seconds
Started Sep 11 10:08:52 AM UTC 24
Finished Sep 11 10:09:17 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4006668299 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 251.prim_prince_test.4006668299
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/251.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/252.prim_prince_test.3927731707
Short name T251
Test name
Test status
Simulation time 1717903501 ps
CPU time 32.93 seconds
Started Sep 11 10:08:53 AM UTC 24
Finished Sep 11 10:09:35 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3927731707 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 252.prim_prince_test.3927731707
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/252.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/253.prim_prince_test.1081224940
Short name T243
Test name
Test status
Simulation time 826721358 ps
CPU time 16.95 seconds
Started Sep 11 10:08:54 AM UTC 24
Finished Sep 11 10:09:16 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1081224940 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 253.prim_prince_test.1081224940
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/253.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/254.prim_prince_test.620680887
Short name T269
Test name
Test status
Simulation time 3144542776 ps
CPU time 58.73 seconds
Started Sep 11 10:08:54 AM UTC 24
Finished Sep 11 10:10:09 AM UTC 24
Peak memory 154656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=620680887 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 254.prim_prince_test.620680887
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/254.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/255.prim_prince_test.1138478355
Short name T253
Test name
Test status
Simulation time 1621355288 ps
CPU time 31.76 seconds
Started Sep 11 10:08:55 AM UTC 24
Finished Sep 11 10:09:36 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1138478355 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 255.prim_prince_test.1138478355
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/255.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/256.prim_prince_test.1060877404
Short name T254
Test name
Test status
Simulation time 1648530261 ps
CPU time 32.35 seconds
Started Sep 11 10:08:56 AM UTC 24
Finished Sep 11 10:09:37 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1060877404 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 256.prim_prince_test.1060877404
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/256.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/257.prim_prince_test.2286410183
Short name T265
Test name
Test status
Simulation time 2300180700 ps
CPU time 45.32 seconds
Started Sep 11 10:09:01 AM UTC 24
Finished Sep 11 10:09:59 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2286410183 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 257.prim_prince_test.2286410183
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/257.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/258.prim_prince_test.24382709
Short name T275
Test name
Test status
Simulation time 2790175608 ps
CPU time 55.94 seconds
Started Sep 11 10:09:02 AM UTC 24
Finished Sep 11 10:10:13 AM UTC 24
Peak memory 154656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=24382709 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 258.prim_prince_test.24382709
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/258.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/259.prim_prince_test.2164473580
Short name T266
Test name
Test status
Simulation time 2271529911 ps
CPU time 44.77 seconds
Started Sep 11 10:09:04 AM UTC 24
Finished Sep 11 10:10:00 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2164473580 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 259.prim_prince_test.2164473580
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/259.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/26.prim_prince_test.2872150227
Short name T29
Test name
Test status
Simulation time 2664263402 ps
CPU time 54.02 seconds
Started Sep 11 10:00:33 AM UTC 24
Finished Sep 11 10:01:42 AM UTC 24
Peak memory 154656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2872150227 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 26.prim_prince_test.2872150227
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/26.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/260.prim_prince_test.752749011
Short name T262
Test name
Test status
Simulation time 2031348422 ps
CPU time 38.01 seconds
Started Sep 11 10:09:04 AM UTC 24
Finished Sep 11 10:09:52 AM UTC 24
Peak memory 154592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=752749011 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 260.prim_prince_test.752749011
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/260.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/261.prim_prince_test.3593295148
Short name T285
Test name
Test status
Simulation time 3668395722 ps
CPU time 72.22 seconds
Started Sep 11 10:09:07 AM UTC 24
Finished Sep 11 10:10:38 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3593295148 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 261.prim_prince_test.3593295148
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/261.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/262.prim_prince_test.3635885839
Short name T250
Test name
Test status
Simulation time 999813188 ps
CPU time 19.87 seconds
Started Sep 11 10:09:08 AM UTC 24
Finished Sep 11 10:09:34 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3635885839 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 262.prim_prince_test.3635885839
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/262.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/263.prim_prince_test.1617371595
Short name T252
Test name
Test status
Simulation time 1064506177 ps
CPU time 21.18 seconds
Started Sep 11 10:09:08 AM UTC 24
Finished Sep 11 10:09:35 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1617371595 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 263.prim_prince_test.1617371595
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/263.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/264.prim_prince_test.3062042284
Short name T264
Test name
Test status
Simulation time 1753040070 ps
CPU time 35.37 seconds
Started Sep 11 10:09:09 AM UTC 24
Finished Sep 11 10:09:54 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3062042284 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 264.prim_prince_test.3062042284
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/264.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/265.prim_prince_test.2031206390
Short name T258
Test name
Test status
Simulation time 1598972428 ps
CPU time 31.74 seconds
Started Sep 11 10:09:09 AM UTC 24
Finished Sep 11 10:09:50 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2031206390 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 265.prim_prince_test.2031206390
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/265.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/266.prim_prince_test.2674251608
Short name T270
Test name
Test status
Simulation time 2389532438 ps
CPU time 46.48 seconds
Started Sep 11 10:09:10 AM UTC 24
Finished Sep 11 10:10:09 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2674251608 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 266.prim_prince_test.2674251608
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/266.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/267.prim_prince_test.1143292467
Short name T284
Test name
Test status
Simulation time 3415166395 ps
CPU time 66.78 seconds
Started Sep 11 10:09:12 AM UTC 24
Finished Sep 11 10:10:36 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1143292467 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 267.prim_prince_test.1143292467
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/267.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/268.prim_prince_test.1883449571
Short name T256
Test name
Test status
Simulation time 1097363519 ps
CPU time 22.37 seconds
Started Sep 11 10:09:15 AM UTC 24
Finished Sep 11 10:09:43 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1883449571 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 268.prim_prince_test.1883449571
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/268.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/269.prim_prince_test.1763141153
Short name T263
Test name
Test status
Simulation time 1482155266 ps
CPU time 28.46 seconds
Started Sep 11 10:09:17 AM UTC 24
Finished Sep 11 10:09:53 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1763141153 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 269.prim_prince_test.1763141153
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/269.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/27.prim_prince_test.1894867709
Short name T35
Test name
Test status
Simulation time 2983101479 ps
CPU time 59.9 seconds
Started Sep 11 10:00:39 AM UTC 24
Finished Sep 11 10:01:55 AM UTC 24
Peak memory 154656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1894867709 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 27.prim_prince_test.1894867709
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/27.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/270.prim_prince_test.4071705735
Short name T279
Test name
Test status
Simulation time 2787002183 ps
CPU time 54.74 seconds
Started Sep 11 10:09:18 AM UTC 24
Finished Sep 11 10:10:27 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4071705735 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 270.prim_prince_test.4071705735
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/270.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/271.prim_prince_test.3668123455
Short name T255
Test name
Test status
Simulation time 890856428 ps
CPU time 18.38 seconds
Started Sep 11 10:09:19 AM UTC 24
Finished Sep 11 10:09:42 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3668123455 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 271.prim_prince_test.3668123455
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/271.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/272.prim_prince_test.1116531444
Short name T268
Test name
Test status
Simulation time 1527018115 ps
CPU time 29.28 seconds
Started Sep 11 10:09:24 AM UTC 24
Finished Sep 11 10:10:01 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1116531444 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 272.prim_prince_test.1116531444
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/272.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/273.prim_prince_test.534023686
Short name T257
Test name
Test status
Simulation time 864784765 ps
CPU time 17.58 seconds
Started Sep 11 10:09:25 AM UTC 24
Finished Sep 11 10:09:48 AM UTC 24
Peak memory 154592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=534023686 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 273.prim_prince_test.534023686
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/273.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/274.prim_prince_test.2466737461
Short name T261
Test name
Test status
Simulation time 1032486925 ps
CPU time 19.71 seconds
Started Sep 11 10:09:25 AM UTC 24
Finished Sep 11 10:09:51 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2466737461 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 274.prim_prince_test.2466737461
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/274.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/275.prim_prince_test.2349027766
Short name T292
Test name
Test status
Simulation time 3577860371 ps
CPU time 67.78 seconds
Started Sep 11 10:09:27 AM UTC 24
Finished Sep 11 10:10:53 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2349027766 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 275.prim_prince_test.2349027766
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/275.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/276.prim_prince_test.920763008
Short name T288
Test name
Test status
Simulation time 3316319468 ps
CPU time 61.59 seconds
Started Sep 11 10:09:30 AM UTC 24
Finished Sep 11 10:10:48 AM UTC 24
Peak memory 154656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=920763008 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 276.prim_prince_test.920763008
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/276.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/277.prim_prince_test.2952438913
Short name T280
Test name
Test status
Simulation time 2080802920 ps
CPU time 41.16 seconds
Started Sep 11 10:09:35 AM UTC 24
Finished Sep 11 10:10:27 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2952438913 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 277.prim_prince_test.2952438913
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/277.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/278.prim_prince_test.853618847
Short name T272
Test name
Test status
Simulation time 1345285984 ps
CPU time 26.97 seconds
Started Sep 11 10:09:36 AM UTC 24
Finished Sep 11 10:10:10 AM UTC 24
Peak memory 154592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=853618847 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 278.prim_prince_test.853618847
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/278.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/279.prim_prince_test.2318548276
Short name T267
Test name
Test status
Simulation time 948199513 ps
CPU time 19.21 seconds
Started Sep 11 10:09:36 AM UTC 24
Finished Sep 11 10:10:01 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2318548276 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 279.prim_prince_test.2318548276
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/279.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/28.prim_prince_test.2987857435
Short name T14
Test name
Test status
Simulation time 859912116 ps
CPU time 17.49 seconds
Started Sep 11 10:00:39 AM UTC 24
Finished Sep 11 10:01:02 AM UTC 24
Peak memory 154592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2987857435 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 28.prim_prince_test.2987857435
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/28.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/280.prim_prince_test.1763063558
Short name T291
Test name
Test status
Simulation time 2972015273 ps
CPU time 58.25 seconds
Started Sep 11 10:09:36 AM UTC 24
Finished Sep 11 10:10:49 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1763063558 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 280.prim_prince_test.1763063558
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/280.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/281.prim_prince_test.2161780409
Short name T300
Test name
Test status
Simulation time 3586178988 ps
CPU time 68.16 seconds
Started Sep 11 10:09:36 AM UTC 24
Finished Sep 11 10:11:02 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2161780409 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 281.prim_prince_test.2161780409
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/281.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/282.prim_prince_test.3670114411
Short name T301
Test name
Test status
Simulation time 3568745430 ps
CPU time 67.26 seconds
Started Sep 11 10:09:38 AM UTC 24
Finished Sep 11 10:11:03 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3670114411 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 282.prim_prince_test.3670114411
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/282.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/283.prim_prince_test.234423571
Short name T273
Test name
Test status
Simulation time 1150276988 ps
CPU time 23.13 seconds
Started Sep 11 10:09:41 AM UTC 24
Finished Sep 11 10:10:11 AM UTC 24
Peak memory 154592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=234423571 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 283.prim_prince_test.234423571
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/283.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/284.prim_prince_test.3750748796
Short name T290
Test name
Test status
Simulation time 2646233871 ps
CPU time 52 seconds
Started Sep 11 10:09:44 AM UTC 24
Finished Sep 11 10:10:49 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3750748796 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 284.prim_prince_test.3750748796
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/284.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/285.prim_prince_test.2441657644
Short name T287
Test name
Test status
Simulation time 2602236343 ps
CPU time 51.07 seconds
Started Sep 11 10:09:44 AM UTC 24
Finished Sep 11 10:10:48 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2441657644 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 285.prim_prince_test.2441657644
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/285.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/286.prim_prince_test.3908714007
Short name T289
Test name
Test status
Simulation time 2427518301 ps
CPU time 47.42 seconds
Started Sep 11 10:09:49 AM UTC 24
Finished Sep 11 10:10:48 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3908714007 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 286.prim_prince_test.3908714007
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/286.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/287.prim_prince_test.3714807430
Short name T274
Test name
Test status
Simulation time 875418106 ps
CPU time 16.52 seconds
Started Sep 11 10:09:50 AM UTC 24
Finished Sep 11 10:10:12 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3714807430 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 287.prim_prince_test.3714807430
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/287.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/288.prim_prince_test.3735549534
Short name T283
Test name
Test status
Simulation time 1770539953 ps
CPU time 34.04 seconds
Started Sep 11 10:09:51 AM UTC 24
Finished Sep 11 10:10:35 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3735549534 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 288.prim_prince_test.3735549534
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/288.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/289.prim_prince_test.480563226
Short name T299
Test name
Test status
Simulation time 2942848049 ps
CPU time 54.56 seconds
Started Sep 11 10:09:52 AM UTC 24
Finished Sep 11 10:11:02 AM UTC 24
Peak memory 154656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=480563226 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 289.prim_prince_test.480563226
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/289.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/29.prim_prince_test.1662524496
Short name T19
Test name
Test status
Simulation time 1445230163 ps
CPU time 29.43 seconds
Started Sep 11 10:00:40 AM UTC 24
Finished Sep 11 10:01:18 AM UTC 24
Peak memory 154592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1662524496 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 29.prim_prince_test.1662524496
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/29.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/290.prim_prince_test.3091214699
Short name T297
Test name
Test status
Simulation time 2748687539 ps
CPU time 53.61 seconds
Started Sep 11 10:09:52 AM UTC 24
Finished Sep 11 10:11:00 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3091214699 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 290.prim_prince_test.3091214699
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/290.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/291.prim_prince_test.2243151579
Short name T309
Test name
Test status
Simulation time 3328588385 ps
CPU time 62.05 seconds
Started Sep 11 10:09:53 AM UTC 24
Finished Sep 11 10:11:12 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2243151579 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 291.prim_prince_test.2243151579
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/291.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/292.prim_prince_test.1635197585
Short name T278
Test name
Test status
Simulation time 1214423446 ps
CPU time 23.25 seconds
Started Sep 11 10:09:55 AM UTC 24
Finished Sep 11 10:10:25 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1635197585 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 292.prim_prince_test.1635197585
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/292.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/293.prim_prince_test.4141910083
Short name T277
Test name
Test status
Simulation time 1045450380 ps
CPU time 20.88 seconds
Started Sep 11 10:09:55 AM UTC 24
Finished Sep 11 10:10:21 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4141910083 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 293.prim_prince_test.4141910083
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/293.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/294.prim_prince_test.3209397818
Short name T310
Test name
Test status
Simulation time 3181165436 ps
CPU time 59.72 seconds
Started Sep 11 10:10:00 AM UTC 24
Finished Sep 11 10:11:16 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3209397818 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 294.prim_prince_test.3209397818
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/294.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/295.prim_prince_test.172258805
Short name T304
Test name
Test status
Simulation time 2625938263 ps
CPU time 52.18 seconds
Started Sep 11 10:10:01 AM UTC 24
Finished Sep 11 10:11:06 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=172258805 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 295.prim_prince_test.172258805
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/295.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/296.prim_prince_test.862701987
Short name T302
Test name
Test status
Simulation time 2549495740 ps
CPU time 49.46 seconds
Started Sep 11 10:10:02 AM UTC 24
Finished Sep 11 10:11:04 AM UTC 24
Peak memory 154656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=862701987 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 296.prim_prince_test.862701987
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/296.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/297.prim_prince_test.3496352668
Short name T281
Test name
Test status
Simulation time 1068118611 ps
CPU time 21.03 seconds
Started Sep 11 10:10:02 AM UTC 24
Finished Sep 11 10:10:29 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3496352668 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 297.prim_prince_test.3496352668
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/297.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/298.prim_prince_test.677680863
Short name T307
Test name
Test status
Simulation time 2494533654 ps
CPU time 48.31 seconds
Started Sep 11 10:10:10 AM UTC 24
Finished Sep 11 10:11:12 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=677680863 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 298.prim_prince_test.677680863
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/298.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/299.prim_prince_test.1791648558
Short name T303
Test name
Test status
Simulation time 2175122445 ps
CPU time 43.26 seconds
Started Sep 11 10:10:10 AM UTC 24
Finished Sep 11 10:11:05 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1791648558 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 299.prim_prince_test.1791648558
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/299.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/3.prim_prince_test.1929204177
Short name T2
Test name
Test status
Simulation time 939337850 ps
CPU time 19.83 seconds
Started Sep 11 09:59:56 AM UTC 24
Finished Sep 11 10:00:23 AM UTC 24
Peak memory 154592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1929204177 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 3.prim_prince_test.1929204177
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/3.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/30.prim_prince_test.1574685056
Short name T46
Test name
Test status
Simulation time 3486575892 ps
CPU time 68.92 seconds
Started Sep 11 10:00:52 AM UTC 24
Finished Sep 11 10:02:20 AM UTC 24
Peak memory 156112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1574685056 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 30.prim_prince_test.1574685056
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/30.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/300.prim_prince_test.3692535571
Short name T293
Test name
Test status
Simulation time 1744611779 ps
CPU time 34.19 seconds
Started Sep 11 10:10:10 AM UTC 24
Finished Sep 11 10:10:54 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3692535571 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 300.prim_prince_test.3692535571
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/300.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/301.prim_prince_test.21375609
Short name T282
Test name
Test status
Simulation time 769087266 ps
CPU time 15.13 seconds
Started Sep 11 10:10:12 AM UTC 24
Finished Sep 11 10:10:31 AM UTC 24
Peak memory 154564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21375609 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 301.prim_prince_test.21375609
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/301.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/302.prim_prince_test.1723547668
Short name T286
Test name
Test status
Simulation time 1337719821 ps
CPU time 25.29 seconds
Started Sep 11 10:10:12 AM UTC 24
Finished Sep 11 10:10:44 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1723547668 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 302.prim_prince_test.1723547668
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/302.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/303.prim_prince_test.210069192
Short name T305
Test name
Test status
Simulation time 2174670752 ps
CPU time 42.82 seconds
Started Sep 11 10:10:13 AM UTC 24
Finished Sep 11 10:11:07 AM UTC 24
Peak memory 154656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=210069192 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 303.prim_prince_test.210069192
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/303.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/304.prim_prince_test.855703602
Short name T306
Test name
Test status
Simulation time 2310209794 ps
CPU time 44.37 seconds
Started Sep 11 10:10:14 AM UTC 24
Finished Sep 11 10:11:10 AM UTC 24
Peak memory 154656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=855703602 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 304.prim_prince_test.855703602
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/304.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/305.prim_prince_test.2051969056
Short name T319
Test name
Test status
Simulation time 3416604457 ps
CPU time 64.38 seconds
Started Sep 11 10:10:19 AM UTC 24
Finished Sep 11 10:11:41 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2051969056 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 305.prim_prince_test.2051969056
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/305.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/306.prim_prince_test.3518916160
Short name T308
Test name
Test status
Simulation time 2034522665 ps
CPU time 38.93 seconds
Started Sep 11 10:10:22 AM UTC 24
Finished Sep 11 10:11:12 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3518916160 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 306.prim_prince_test.3518916160
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/306.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/307.prim_prince_test.1370913447
Short name T313
Test name
Test status
Simulation time 2148408250 ps
CPU time 42.46 seconds
Started Sep 11 10:10:25 AM UTC 24
Finished Sep 11 10:11:19 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1370913447 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 307.prim_prince_test.1370913447
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/307.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/308.prim_prince_test.4016709024
Short name T296
Test name
Test status
Simulation time 1217329471 ps
CPU time 24 seconds
Started Sep 11 10:10:28 AM UTC 24
Finished Sep 11 10:10:58 AM UTC 24
Peak memory 154364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4016709024 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 308.prim_prince_test.4016709024
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/308.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/309.prim_prince_test.2792800179
Short name T295
Test name
Test status
Simulation time 1133971424 ps
CPU time 22.55 seconds
Started Sep 11 10:10:28 AM UTC 24
Finished Sep 11 10:10:57 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2792800179 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 309.prim_prince_test.2792800179
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/309.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/31.prim_prince_test.1710314237
Short name T42
Test name
Test status
Simulation time 3199153788 ps
CPU time 61.34 seconds
Started Sep 11 10:00:54 AM UTC 24
Finished Sep 11 10:02:13 AM UTC 24
Peak memory 154656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1710314237 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 31.prim_prince_test.1710314237
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/31.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/310.prim_prince_test.2979189202
Short name T294
Test name
Test status
Simulation time 980377174 ps
CPU time 19.24 seconds
Started Sep 11 10:10:30 AM UTC 24
Finished Sep 11 10:10:56 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2979189202 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 310.prim_prince_test.2979189202
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/310.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/311.prim_prince_test.428595773
Short name T317
Test name
Test status
Simulation time 2271417692 ps
CPU time 45.16 seconds
Started Sep 11 10:10:33 AM UTC 24
Finished Sep 11 10:11:30 AM UTC 24
Peak memory 154656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=428595773 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 311.prim_prince_test.428595773
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/311.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/312.prim_prince_test.3047984979
Short name T298
Test name
Test status
Simulation time 1001285332 ps
CPU time 20.1 seconds
Started Sep 11 10:10:35 AM UTC 24
Finished Sep 11 10:11:01 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3047984979 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 312.prim_prince_test.3047984979
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/312.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/313.prim_prince_test.302631853
Short name T314
Test name
Test status
Simulation time 1764145846 ps
CPU time 34.27 seconds
Started Sep 11 10:10:37 AM UTC 24
Finished Sep 11 10:11:21 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=302631853 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 313.prim_prince_test.302631853
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/313.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/314.prim_prince_test.4249540966
Short name T318
Test name
Test status
Simulation time 2563028561 ps
CPU time 48.99 seconds
Started Sep 11 10:10:38 AM UTC 24
Finished Sep 11 10:11:41 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4249540966 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 314.prim_prince_test.4249540966
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/314.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/315.prim_prince_test.186533363
Short name T328
Test name
Test status
Simulation time 2750565229 ps
CPU time 51.83 seconds
Started Sep 11 10:10:46 AM UTC 24
Finished Sep 11 10:11:52 AM UTC 24
Peak memory 154656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=186533363 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 315.prim_prince_test.186533363
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/315.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/316.prim_prince_test.3011398741
Short name T315
Test name
Test status
Simulation time 1528593177 ps
CPU time 30.53 seconds
Started Sep 11 10:10:49 AM UTC 24
Finished Sep 11 10:11:27 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3011398741 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 316.prim_prince_test.3011398741
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/316.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/317.prim_prince_test.1703726091
Short name T322
Test name
Test status
Simulation time 2228524696 ps
CPU time 43.64 seconds
Started Sep 11 10:10:49 AM UTC 24
Finished Sep 11 10:11:44 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1703726091 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 317.prim_prince_test.1703726091
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/317.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/318.prim_prince_test.3225922695
Short name T332
Test name
Test status
Simulation time 2687271468 ps
CPU time 52.81 seconds
Started Sep 11 10:10:50 AM UTC 24
Finished Sep 11 10:11:57 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3225922695 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 318.prim_prince_test.3225922695
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/318.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/319.prim_prince_test.1055134403
Short name T329
Test name
Test status
Simulation time 2545795311 ps
CPU time 50.42 seconds
Started Sep 11 10:10:50 AM UTC 24
Finished Sep 11 10:11:53 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1055134403 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 319.prim_prince_test.1055134403
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/319.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/32.prim_prince_test.3058491805
Short name T44
Test name
Test status
Simulation time 3310045220 ps
CPU time 62.65 seconds
Started Sep 11 10:00:56 AM UTC 24
Finished Sep 11 10:02:17 AM UTC 24
Peak memory 154656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3058491805 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 32.prim_prince_test.3058491805
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/32.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/320.prim_prince_test.3004543462
Short name T320
Test name
Test status
Simulation time 2173581092 ps
CPU time 42.06 seconds
Started Sep 11 10:10:50 AM UTC 24
Finished Sep 11 10:11:43 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3004543462 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 320.prim_prince_test.3004543462
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/320.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/321.prim_prince_test.964562636
Short name T312
Test name
Test status
Simulation time 960543414 ps
CPU time 18.72 seconds
Started Sep 11 10:10:54 AM UTC 24
Finished Sep 11 10:11:19 AM UTC 24
Peak memory 154592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=964562636 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 321.prim_prince_test.964562636
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/321.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/322.prim_prince_test.3285863101
Short name T311
Test name
Test status
Simulation time 819999936 ps
CPU time 16.75 seconds
Started Sep 11 10:10:54 AM UTC 24
Finished Sep 11 10:11:16 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3285863101 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 322.prim_prince_test.3285863101
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/322.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/323.prim_prince_test.2562528823
Short name T335
Test name
Test status
Simulation time 2611847232 ps
CPU time 50.43 seconds
Started Sep 11 10:10:57 AM UTC 24
Finished Sep 11 10:12:00 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2562528823 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 323.prim_prince_test.2562528823
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/323.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/324.prim_prince_test.4247606176
Short name T321
Test name
Test status
Simulation time 1890773728 ps
CPU time 35.93 seconds
Started Sep 11 10:10:58 AM UTC 24
Finished Sep 11 10:11:44 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4247606176 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 324.prim_prince_test.4247606176
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/324.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/325.prim_prince_test.3011599058
Short name T340
Test name
Test status
Simulation time 3468595786 ps
CPU time 64.79 seconds
Started Sep 11 10:10:59 AM UTC 24
Finished Sep 11 10:12:21 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3011599058 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 325.prim_prince_test.3011599058
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/325.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/326.prim_prince_test.54911026
Short name T331
Test name
Test status
Simulation time 2193480918 ps
CPU time 42.21 seconds
Started Sep 11 10:11:01 AM UTC 24
Finished Sep 11 10:11:55 AM UTC 24
Peak memory 154656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=54911026 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 326.prim_prince_test.54911026
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/326.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/327.prim_prince_test.112504618
Short name T326
Test name
Test status
Simulation time 1961487466 ps
CPU time 38.7 seconds
Started Sep 11 10:11:02 AM UTC 24
Finished Sep 11 10:11:51 AM UTC 24
Peak memory 154592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=112504618 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 327.prim_prince_test.112504618
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/327.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/328.prim_prince_test.2877312409
Short name T339
Test name
Test status
Simulation time 2998406887 ps
CPU time 57.27 seconds
Started Sep 11 10:11:03 AM UTC 24
Finished Sep 11 10:12:16 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2877312409 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 328.prim_prince_test.2877312409
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/328.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/329.prim_prince_test.493436715
Short name T347
Test name
Test status
Simulation time 3587851374 ps
CPU time 70.26 seconds
Started Sep 11 10:11:03 AM UTC 24
Finished Sep 11 10:12:31 AM UTC 24
Peak memory 154656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=493436715 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 329.prim_prince_test.493436715
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/329.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/33.prim_prince_test.3663660642
Short name T28
Test name
Test status
Simulation time 1583808171 ps
CPU time 30.46 seconds
Started Sep 11 10:00:58 AM UTC 24
Finished Sep 11 10:01:38 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3663660642 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 33.prim_prince_test.3663660642
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/33.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/330.prim_prince_test.2340333523
Short name T323
Test name
Test status
Simulation time 1647668529 ps
CPU time 33.2 seconds
Started Sep 11 10:11:04 AM UTC 24
Finished Sep 11 10:11:47 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2340333523 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 330.prim_prince_test.2340333523
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/330.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/331.prim_prince_test.2636582033
Short name T316
Test name
Test status
Simulation time 826445283 ps
CPU time 16.68 seconds
Started Sep 11 10:11:06 AM UTC 24
Finished Sep 11 10:11:27 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2636582033 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 331.prim_prince_test.2636582033
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/331.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/332.prim_prince_test.2829979409
Short name T341
Test name
Test status
Simulation time 3208826143 ps
CPU time 59.92 seconds
Started Sep 11 10:11:06 AM UTC 24
Finished Sep 11 10:12:22 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2829979409 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 332.prim_prince_test.2829979409
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/332.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/333.prim_prince_test.3051418663
Short name T327
Test name
Test status
Simulation time 1765571875 ps
CPU time 35.28 seconds
Started Sep 11 10:11:07 AM UTC 24
Finished Sep 11 10:11:52 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3051418663 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 333.prim_prince_test.3051418663
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/333.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/334.prim_prince_test.3864488889
Short name T325
Test name
Test status
Simulation time 1636246804 ps
CPU time 32.38 seconds
Started Sep 11 10:11:08 AM UTC 24
Finished Sep 11 10:11:49 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3864488889 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 334.prim_prince_test.3864488889
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/334.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/335.prim_prince_test.1633239661
Short name T349
Test name
Test status
Simulation time 3422663921 ps
CPU time 64.85 seconds
Started Sep 11 10:11:11 AM UTC 24
Finished Sep 11 10:12:33 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1633239661 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 335.prim_prince_test.1633239661
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/335.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/336.prim_prince_test.612723964
Short name T338
Test name
Test status
Simulation time 2559950587 ps
CPU time 48.37 seconds
Started Sep 11 10:11:12 AM UTC 24
Finished Sep 11 10:12:14 AM UTC 24
Peak memory 154656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=612723964 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 336.prim_prince_test.612723964
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/336.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/337.prim_prince_test.4019740707
Short name T324
Test name
Test status
Simulation time 1383709936 ps
CPU time 26.73 seconds
Started Sep 11 10:11:12 AM UTC 24
Finished Sep 11 10:11:47 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4019740707 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 337.prim_prince_test.4019740707
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/337.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/338.prim_prince_test.3390266648
Short name T330
Test name
Test status
Simulation time 1652756906 ps
CPU time 31.36 seconds
Started Sep 11 10:11:13 AM UTC 24
Finished Sep 11 10:11:54 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3390266648 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 338.prim_prince_test.3390266648
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/338.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/339.prim_prince_test.1418912085
Short name T334
Test name
Test status
Simulation time 1716301753 ps
CPU time 33.99 seconds
Started Sep 11 10:11:17 AM UTC 24
Finished Sep 11 10:11:59 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1418912085 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 339.prim_prince_test.1418912085
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/339.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/34.prim_prince_test.1445089163
Short name T31
Test name
Test status
Simulation time 1702395097 ps
CPU time 32.33 seconds
Started Sep 11 10:01:01 AM UTC 24
Finished Sep 11 10:01:44 AM UTC 24
Peak memory 154592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1445089163 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 34.prim_prince_test.1445089163
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/34.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/340.prim_prince_test.422569385
Short name T348
Test name
Test status
Simulation time 3120154278 ps
CPU time 60.56 seconds
Started Sep 11 10:11:17 AM UTC 24
Finished Sep 11 10:12:33 AM UTC 24
Peak memory 154656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=422569385 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 340.prim_prince_test.422569385
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/340.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/341.prim_prince_test.1662455654
Short name T336
Test name
Test status
Simulation time 1647529443 ps
CPU time 32.4 seconds
Started Sep 11 10:11:20 AM UTC 24
Finished Sep 11 10:12:01 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1662455654 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 341.prim_prince_test.1662455654
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/341.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/342.prim_prince_test.3859850818
Short name T333
Test name
Test status
Simulation time 1566234056 ps
CPU time 30.63 seconds
Started Sep 11 10:11:20 AM UTC 24
Finished Sep 11 10:11:59 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3859850818 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 342.prim_prince_test.3859850818
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/342.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/343.prim_prince_test.3632148843
Short name T353
Test name
Test status
Simulation time 3103002495 ps
CPU time 60.33 seconds
Started Sep 11 10:11:22 AM UTC 24
Finished Sep 11 10:12:38 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3632148843 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 343.prim_prince_test.3632148843
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/343.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/344.prim_prince_test.4005591313
Short name T358
Test name
Test status
Simulation time 3135805126 ps
CPU time 61.25 seconds
Started Sep 11 10:11:28 AM UTC 24
Finished Sep 11 10:12:45 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4005591313 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 344.prim_prince_test.4005591313
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/344.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/345.prim_prince_test.753136398
Short name T355
Test name
Test status
Simulation time 2870964141 ps
CPU time 56.69 seconds
Started Sep 11 10:11:28 AM UTC 24
Finished Sep 11 10:12:39 AM UTC 24
Peak memory 154656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=753136398 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 345.prim_prince_test.753136398
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/345.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/346.prim_prince_test.3295710694
Short name T345
Test name
Test status
Simulation time 2423722773 ps
CPU time 47.22 seconds
Started Sep 11 10:11:31 AM UTC 24
Finished Sep 11 10:12:30 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3295710694 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 346.prim_prince_test.3295710694
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/346.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/347.prim_prince_test.4150598821
Short name T367
Test name
Test status
Simulation time 3555776358 ps
CPU time 69.4 seconds
Started Sep 11 10:11:42 AM UTC 24
Finished Sep 11 10:13:09 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4150598821 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 347.prim_prince_test.4150598821
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/347.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/348.prim_prince_test.3152461606
Short name T362
Test name
Test status
Simulation time 3080437031 ps
CPU time 58.13 seconds
Started Sep 11 10:11:42 AM UTC 24
Finished Sep 11 10:12:56 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3152461606 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 348.prim_prince_test.3152461606
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/348.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/349.prim_prince_test.277275043
Short name T368
Test name
Test status
Simulation time 3541739865 ps
CPU time 66.83 seconds
Started Sep 11 10:11:44 AM UTC 24
Finished Sep 11 10:13:09 AM UTC 24
Peak memory 154656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=277275043 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 349.prim_prince_test.277275043
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/349.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/35.prim_prince_test.1170282557
Short name T39
Test name
Test status
Simulation time 2354694240 ps
CPU time 45.43 seconds
Started Sep 11 10:01:02 AM UTC 24
Finished Sep 11 10:02:01 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1170282557 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 35.prim_prince_test.1170282557
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/35.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/350.prim_prince_test.3063932834
Short name T337
Test name
Test status
Simulation time 932787273 ps
CPU time 18.67 seconds
Started Sep 11 10:11:44 AM UTC 24
Finished Sep 11 10:12:08 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3063932834 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 350.prim_prince_test.3063932834
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/350.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/351.prim_prince_test.1913968679
Short name T346
Test name
Test status
Simulation time 1827292708 ps
CPU time 36.06 seconds
Started Sep 11 10:11:45 AM UTC 24
Finished Sep 11 10:12:31 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1913968679 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 351.prim_prince_test.1913968679
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/351.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/352.prim_prince_test.341291703
Short name T360
Test name
Test status
Simulation time 2554301995 ps
CPU time 49.35 seconds
Started Sep 11 10:11:47 AM UTC 24
Finished Sep 11 10:12:50 AM UTC 24
Peak memory 154656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=341291703 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 352.prim_prince_test.341291703
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/352.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/353.prim_prince_test.3240317485
Short name T359
Test name
Test status
Simulation time 2375993967 ps
CPU time 45.68 seconds
Started Sep 11 10:11:47 AM UTC 24
Finished Sep 11 10:12:45 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3240317485 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 353.prim_prince_test.3240317485
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/353.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/354.prim_prince_test.1722000175
Short name T374
Test name
Test status
Simulation time 3579280691 ps
CPU time 69.02 seconds
Started Sep 11 10:11:50 AM UTC 24
Finished Sep 11 10:13:16 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1722000175 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 354.prim_prince_test.1722000175
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/354.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/355.prim_prince_test.874228346
Short name T361
Test name
Test status
Simulation time 2561824428 ps
CPU time 47.45 seconds
Started Sep 11 10:11:52 AM UTC 24
Finished Sep 11 10:12:52 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=874228346 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 355.prim_prince_test.874228346
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/355.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/356.prim_prince_test.2779818815
Short name T343
Test name
Test status
Simulation time 1218302125 ps
CPU time 24.1 seconds
Started Sep 11 10:11:53 AM UTC 24
Finished Sep 11 10:12:24 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2779818815 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 356.prim_prince_test.2779818815
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/356.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/357.prim_prince_test.576504659
Short name T342
Test name
Test status
Simulation time 1197824130 ps
CPU time 23.43 seconds
Started Sep 11 10:11:53 AM UTC 24
Finished Sep 11 10:12:23 AM UTC 24
Peak memory 154592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=576504659 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 357.prim_prince_test.576504659
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/357.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/358.prim_prince_test.2140935635
Short name T369
Test name
Test status
Simulation time 3020818169 ps
CPU time 59.76 seconds
Started Sep 11 10:11:54 AM UTC 24
Finished Sep 11 10:13:09 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2140935635 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 358.prim_prince_test.2140935635
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/358.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/359.prim_prince_test.3279292191
Short name T364
Test name
Test status
Simulation time 2911705609 ps
CPU time 56.67 seconds
Started Sep 11 10:11:54 AM UTC 24
Finished Sep 11 10:13:05 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3279292191 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 359.prim_prince_test.3279292191
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/359.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/36.prim_prince_test.2654336232
Short name T32
Test name
Test status
Simulation time 1551328587 ps
CPU time 30.58 seconds
Started Sep 11 10:01:06 AM UTC 24
Finished Sep 11 10:01:45 AM UTC 24
Peak memory 154592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2654336232 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 36.prim_prince_test.2654336232
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/36.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/360.prim_prince_test.3258844161
Short name T370
Test name
Test status
Simulation time 3151756066 ps
CPU time 61.47 seconds
Started Sep 11 10:11:55 AM UTC 24
Finished Sep 11 10:13:12 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3258844161 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 360.prim_prince_test.3258844161
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/360.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/361.prim_prince_test.1870862809
Short name T352
Test name
Test status
Simulation time 1531664725 ps
CPU time 29.79 seconds
Started Sep 11 10:11:58 AM UTC 24
Finished Sep 11 10:12:35 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1870862809 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 361.prim_prince_test.1870862809
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/361.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/362.prim_prince_test.2109847077
Short name T356
Test name
Test status
Simulation time 1726005034 ps
CPU time 32.7 seconds
Started Sep 11 10:12:00 AM UTC 24
Finished Sep 11 10:12:42 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2109847077 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 362.prim_prince_test.2109847077
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/362.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/363.prim_prince_test.554714913
Short name T354
Test name
Test status
Simulation time 1470174930 ps
CPU time 29.03 seconds
Started Sep 11 10:12:01 AM UTC 24
Finished Sep 11 10:12:38 AM UTC 24
Peak memory 154588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=554714913 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 363.prim_prince_test.554714913
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/363.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/364.prim_prince_test.573572154
Short name T344
Test name
Test status
Simulation time 1121657352 ps
CPU time 22.04 seconds
Started Sep 11 10:12:01 AM UTC 24
Finished Sep 11 10:12:29 AM UTC 24
Peak memory 154592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=573572154 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 364.prim_prince_test.573572154
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/364.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/365.prim_prince_test.614054564
Short name T350
Test name
Test status
Simulation time 1307027822 ps
CPU time 25.63 seconds
Started Sep 11 10:12:02 AM UTC 24
Finished Sep 11 10:12:35 AM UTC 24
Peak memory 154592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=614054564 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 365.prim_prince_test.614054564
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/365.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/366.prim_prince_test.258727349
Short name T373
Test name
Test status
Simulation time 2788659840 ps
CPU time 52.57 seconds
Started Sep 11 10:12:09 AM UTC 24
Finished Sep 11 10:13:16 AM UTC 24
Peak memory 154656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=258727349 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 366.prim_prince_test.258727349
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/366.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/367.prim_prince_test.408289108
Short name T351
Test name
Test status
Simulation time 803262921 ps
CPU time 16.04 seconds
Started Sep 11 10:12:14 AM UTC 24
Finished Sep 11 10:12:35 AM UTC 24
Peak memory 154592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=408289108 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 367.prim_prince_test.408289108
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/367.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/368.prim_prince_test.1394241669
Short name T383
Test name
Test status
Simulation time 3517796971 ps
CPU time 67.89 seconds
Started Sep 11 10:12:17 AM UTC 24
Finished Sep 11 10:13:42 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1394241669 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 368.prim_prince_test.1394241669
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/368.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/369.prim_prince_test.3411680705
Short name T379
Test name
Test status
Simulation time 2902524458 ps
CPU time 56.31 seconds
Started Sep 11 10:12:23 AM UTC 24
Finished Sep 11 10:13:34 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3411680705 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 369.prim_prince_test.3411680705
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/369.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/37.prim_prince_test.4031783032
Short name T40
Test name
Test status
Simulation time 2249311148 ps
CPU time 44.42 seconds
Started Sep 11 10:01:08 AM UTC 24
Finished Sep 11 10:02:04 AM UTC 24
Peak memory 154656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4031783032 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 37.prim_prince_test.4031783032
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/37.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/370.prim_prince_test.1725909375
Short name T390
Test name
Test status
Simulation time 3732327962 ps
CPU time 72.6 seconds
Started Sep 11 10:12:23 AM UTC 24
Finished Sep 11 10:13:54 AM UTC 24
Peak memory 154416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1725909375 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 370.prim_prince_test.1725909375
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/370.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/371.prim_prince_test.61400202
Short name T357
Test name
Test status
Simulation time 797106917 ps
CPU time 16.03 seconds
Started Sep 11 10:12:23 AM UTC 24
Finished Sep 11 10:12:44 AM UTC 24
Peak memory 154272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=61400202 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 371.prim_prince_test.61400202
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/371.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/372.prim_prince_test.2607880522
Short name T365
Test name
Test status
Simulation time 1726861426 ps
CPU time 33.78 seconds
Started Sep 11 10:12:24 AM UTC 24
Finished Sep 11 10:13:07 AM UTC 24
Peak memory 154524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2607880522 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 372.prim_prince_test.2607880522
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/372.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/373.prim_prince_test.1508912354
Short name T375
Test name
Test status
Simulation time 2201615830 ps
CPU time 42.64 seconds
Started Sep 11 10:12:24 AM UTC 24
Finished Sep 11 10:13:18 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1508912354 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 373.prim_prince_test.1508912354
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/373.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/374.prim_prince_test.3201929468
Short name T386
Test name
Test status
Simulation time 3133974936 ps
CPU time 59.87 seconds
Started Sep 11 10:12:31 AM UTC 24
Finished Sep 11 10:13:46 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3201929468 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 374.prim_prince_test.3201929468
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/374.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/375.prim_prince_test.3753330323
Short name T380
Test name
Test status
Simulation time 2603600113 ps
CPU time 50.7 seconds
Started Sep 11 10:12:32 AM UTC 24
Finished Sep 11 10:13:36 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3753330323 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 375.prim_prince_test.3753330323
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/375.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/376.prim_prince_test.2330247628
Short name T388
Test name
Test status
Simulation time 3185148344 ps
CPU time 61.09 seconds
Started Sep 11 10:12:32 AM UTC 24
Finished Sep 11 10:13:49 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2330247628 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 376.prim_prince_test.2330247628
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/376.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/377.prim_prince_test.3271213887
Short name T372
Test name
Test status
Simulation time 1696383280 ps
CPU time 33.07 seconds
Started Sep 11 10:12:32 AM UTC 24
Finished Sep 11 10:13:14 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3271213887 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 377.prim_prince_test.3271213887
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/377.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/378.prim_prince_test.4043741121
Short name T391
Test name
Test status
Simulation time 3504075717 ps
CPU time 65.25 seconds
Started Sep 11 10:12:33 AM UTC 24
Finished Sep 11 10:13:56 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4043741121 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 378.prim_prince_test.4043741121
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/378.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/379.prim_prince_test.2944837842
Short name T393
Test name
Test status
Simulation time 3501124017 ps
CPU time 67.54 seconds
Started Sep 11 10:12:34 AM UTC 24
Finished Sep 11 10:14:00 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2944837842 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 379.prim_prince_test.2944837842
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/379.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/38.prim_prince_test.1770015551
Short name T52
Test name
Test status
Simulation time 3054903046 ps
CPU time 58.5 seconds
Started Sep 11 10:01:15 AM UTC 24
Finished Sep 11 10:02:30 AM UTC 24
Peak memory 154032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1770015551 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 38.prim_prince_test.1770015551
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/38.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/380.prim_prince_test.347619709
Short name T378
Test name
Test status
Simulation time 2027465660 ps
CPU time 38.12 seconds
Started Sep 11 10:12:35 AM UTC 24
Finished Sep 11 10:13:24 AM UTC 24
Peak memory 154592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=347619709 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 380.prim_prince_test.347619709
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/380.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/381.prim_prince_test.3008850692
Short name T384
Test name
Test status
Simulation time 2666751489 ps
CPU time 52.15 seconds
Started Sep 11 10:12:37 AM UTC 24
Finished Sep 11 10:13:42 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3008850692 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 381.prim_prince_test.3008850692
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/381.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/382.prim_prince_test.767910319
Short name T366
Test name
Test status
Simulation time 1222523071 ps
CPU time 24.62 seconds
Started Sep 11 10:12:37 AM UTC 24
Finished Sep 11 10:13:08 AM UTC 24
Peak memory 154592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=767910319 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 382.prim_prince_test.767910319
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/382.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/383.prim_prince_test.2292049315
Short name T389
Test name
Test status
Simulation time 3114532152 ps
CPU time 58.39 seconds
Started Sep 11 10:12:39 AM UTC 24
Finished Sep 11 10:13:53 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2292049315 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 383.prim_prince_test.2292049315
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/383.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/384.prim_prince_test.2752636322
Short name T394
Test name
Test status
Simulation time 3346694966 ps
CPU time 65.16 seconds
Started Sep 11 10:12:39 AM UTC 24
Finished Sep 11 10:14:00 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2752636322 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 384.prim_prince_test.2752636322
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/384.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/385.prim_prince_test.1966184194
Short name T363
Test name
Test status
Simulation time 806454631 ps
CPU time 15.98 seconds
Started Sep 11 10:12:40 AM UTC 24
Finished Sep 11 10:13:01 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1966184194 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 385.prim_prince_test.1966184194
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/385.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/386.prim_prince_test.69179669
Short name T397
Test name
Test status
Simulation time 3398062454 ps
CPU time 64.1 seconds
Started Sep 11 10:12:42 AM UTC 24
Finished Sep 11 10:14:03 AM UTC 24
Peak memory 154656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=69179669 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 386.prim_prince_test.69179669
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/386.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/387.prim_prince_test.3650801814
Short name T382
Test name
Test status
Simulation time 2239066479 ps
CPU time 43.28 seconds
Started Sep 11 10:12:44 AM UTC 24
Finished Sep 11 10:13:39 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3650801814 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 387.prim_prince_test.3650801814
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/387.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/388.prim_prince_test.4178876539
Short name T377
Test name
Test status
Simulation time 1399054538 ps
CPU time 27.41 seconds
Started Sep 11 10:12:46 AM UTC 24
Finished Sep 11 10:13:21 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4178876539 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 388.prim_prince_test.4178876539
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/388.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/389.prim_prince_test.3196142203
Short name T376
Test name
Test status
Simulation time 1389153504 ps
CPU time 26.44 seconds
Started Sep 11 10:12:46 AM UTC 24
Finished Sep 11 10:13:21 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3196142203 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 389.prim_prince_test.3196142203
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/389.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/39.prim_prince_test.2348778258
Short name T33
Test name
Test status
Simulation time 1363330000 ps
CPU time 26.08 seconds
Started Sep 11 10:01:15 AM UTC 24
Finished Sep 11 10:01:49 AM UTC 24
Peak memory 153972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2348778258 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 39.prim_prince_test.2348778258
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/39.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/390.prim_prince_test.746769499
Short name T371
Test name
Test status
Simulation time 926136188 ps
CPU time 18.13 seconds
Started Sep 11 10:12:50 AM UTC 24
Finished Sep 11 10:13:14 AM UTC 24
Peak memory 154592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=746769499 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 390.prim_prince_test.746769499
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/390.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/391.prim_prince_test.1805829068
Short name T395
Test name
Test status
Simulation time 2848091447 ps
CPU time 53.93 seconds
Started Sep 11 10:12:53 AM UTC 24
Finished Sep 11 10:14:02 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1805829068 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 391.prim_prince_test.1805829068
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/391.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/392.prim_prince_test.2230632606
Short name T401
Test name
Test status
Simulation time 3345013142 ps
CPU time 62.73 seconds
Started Sep 11 10:12:56 AM UTC 24
Finished Sep 11 10:14:16 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2230632606 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 392.prim_prince_test.2230632606
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/392.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/393.prim_prince_test.1638621110
Short name T406
Test name
Test status
Simulation time 3392457420 ps
CPU time 65.96 seconds
Started Sep 11 10:13:02 AM UTC 24
Finished Sep 11 10:14:25 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1638621110 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 393.prim_prince_test.1638621110
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/393.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/394.prim_prince_test.2502254786
Short name T398
Test name
Test status
Simulation time 2428414594 ps
CPU time 46.1 seconds
Started Sep 11 10:13:07 AM UTC 24
Finished Sep 11 10:14:05 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2502254786 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 394.prim_prince_test.2502254786
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/394.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/395.prim_prince_test.1214719422
Short name T408
Test name
Test status
Simulation time 3275718525 ps
CPU time 61.94 seconds
Started Sep 11 10:13:09 AM UTC 24
Finished Sep 11 10:14:27 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1214719422 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 395.prim_prince_test.1214719422
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/395.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/396.prim_prince_test.264504167
Short name T385
Test name
Test status
Simulation time 1454134114 ps
CPU time 28.01 seconds
Started Sep 11 10:13:09 AM UTC 24
Finished Sep 11 10:13:45 AM UTC 24
Peak memory 154592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=264504167 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 396.prim_prince_test.264504167
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/396.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/397.prim_prince_test.3372761631
Short name T410
Test name
Test status
Simulation time 3228796351 ps
CPU time 63.66 seconds
Started Sep 11 10:13:10 AM UTC 24
Finished Sep 11 10:14:30 AM UTC 24
Peak memory 154388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3372761631 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 397.prim_prince_test.3372761631
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/397.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/398.prim_prince_test.3462618701
Short name T402
Test name
Test status
Simulation time 2716201935 ps
CPU time 52.45 seconds
Started Sep 11 10:13:10 AM UTC 24
Finished Sep 11 10:14:16 AM UTC 24
Peak memory 154452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3462618701 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 398.prim_prince_test.3462618701
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/398.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/399.prim_prince_test.3738003982
Short name T411
Test name
Test status
Simulation time 3250074258 ps
CPU time 63.79 seconds
Started Sep 11 10:13:10 AM UTC 24
Finished Sep 11 10:14:30 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3738003982 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 399.prim_prince_test.3738003982
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/399.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/4.prim_prince_test.1122332567
Short name T23
Test name
Test status
Simulation time 3418881774 ps
CPU time 68.98 seconds
Started Sep 11 09:59:56 AM UTC 24
Finished Sep 11 10:01:25 AM UTC 24
Peak memory 154656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1122332567 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 4.prim_prince_test.1122332567
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/4.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/40.prim_prince_test.3961674825
Short name T41
Test name
Test status
Simulation time 1954815083 ps
CPU time 38.92 seconds
Started Sep 11 10:01:16 AM UTC 24
Finished Sep 11 10:02:06 AM UTC 24
Peak memory 154592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3961674825 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 40.prim_prince_test.3961674825
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/40.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/400.prim_prince_test.2125886601
Short name T387
Test name
Test status
Simulation time 1412029604 ps
CPU time 26.95 seconds
Started Sep 11 10:13:13 AM UTC 24
Finished Sep 11 10:13:48 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2125886601 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 400.prim_prince_test.2125886601
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/400.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/401.prim_prince_test.2471596232
Short name T405
Test name
Test status
Simulation time 2869012946 ps
CPU time 55.93 seconds
Started Sep 11 10:13:15 AM UTC 24
Finished Sep 11 10:14:25 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2471596232 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 401.prim_prince_test.2471596232
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/401.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/402.prim_prince_test.2309099681
Short name T418
Test name
Test status
Simulation time 3572094020 ps
CPU time 69.26 seconds
Started Sep 11 10:13:16 AM UTC 24
Finished Sep 11 10:14:42 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2309099681 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 402.prim_prince_test.2309099681
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/402.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/403.prim_prince_test.3477714547
Short name T381
Test name
Test status
Simulation time 847619317 ps
CPU time 16.83 seconds
Started Sep 11 10:13:17 AM UTC 24
Finished Sep 11 10:13:39 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3477714547 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 403.prim_prince_test.3477714547
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/403.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/404.prim_prince_test.4211690109
Short name T400
Test name
Test status
Simulation time 2120006042 ps
CPU time 41.24 seconds
Started Sep 11 10:13:17 AM UTC 24
Finished Sep 11 10:14:09 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4211690109 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 404.prim_prince_test.4211690109
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/404.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/405.prim_prince_test.1043203696
Short name T413
Test name
Test status
Simulation time 3313236026 ps
CPU time 61.98 seconds
Started Sep 11 10:13:19 AM UTC 24
Finished Sep 11 10:14:38 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1043203696 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 405.prim_prince_test.1043203696
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/405.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/406.prim_prince_test.2757071034
Short name T399
Test name
Test status
Simulation time 1813291199 ps
CPU time 36.38 seconds
Started Sep 11 10:13:21 AM UTC 24
Finished Sep 11 10:14:07 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2757071034 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 406.prim_prince_test.2757071034
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/406.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/407.prim_prince_test.451968325
Short name T392
Test name
Test status
Simulation time 1389229532 ps
CPU time 27.57 seconds
Started Sep 11 10:13:23 AM UTC 24
Finished Sep 11 10:13:58 AM UTC 24
Peak memory 154592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=451968325 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 407.prim_prince_test.451968325
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/407.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/408.prim_prince_test.1023982595
Short name T396
Test name
Test status
Simulation time 1561650024 ps
CPU time 30.13 seconds
Started Sep 11 10:13:25 AM UTC 24
Finished Sep 11 10:14:03 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1023982595 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 408.prim_prince_test.1023982595
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/408.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/409.prim_prince_test.3306074183
Short name T419
Test name
Test status
Simulation time 3277912840 ps
CPU time 61.42 seconds
Started Sep 11 10:13:25 AM UTC 24
Finished Sep 11 10:14:43 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3306074183 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 409.prim_prince_test.3306074183
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/409.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/41.prim_prince_test.309316506
Short name T38
Test name
Test status
Simulation time 1760052468 ps
CPU time 33.32 seconds
Started Sep 11 10:01:17 AM UTC 24
Finished Sep 11 10:02:00 AM UTC 24
Peak memory 154592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=309316506 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 41.prim_prince_test.309316506
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/41.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/410.prim_prince_test.1495128015
Short name T407
Test name
Test status
Simulation time 2083442551 ps
CPU time 40.64 seconds
Started Sep 11 10:13:34 AM UTC 24
Finished Sep 11 10:14:25 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1495128015 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 410.prim_prince_test.1495128015
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/410.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/411.prim_prince_test.1883664230
Short name T417
Test name
Test status
Simulation time 2632228031 ps
CPU time 51.4 seconds
Started Sep 11 10:13:37 AM UTC 24
Finished Sep 11 10:14:42 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1883664230 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 411.prim_prince_test.1883664230
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/411.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/412.prim_prince_test.2188396547
Short name T424
Test name
Test status
Simulation time 2985750797 ps
CPU time 58.18 seconds
Started Sep 11 10:13:39 AM UTC 24
Finished Sep 11 10:14:52 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2188396547 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 412.prim_prince_test.2188396547
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/412.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/413.prim_prince_test.4005554574
Short name T433
Test name
Test status
Simulation time 3705360530 ps
CPU time 68.58 seconds
Started Sep 11 10:13:41 AM UTC 24
Finished Sep 11 10:15:07 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4005554574 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 413.prim_prince_test.4005554574
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/413.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/414.prim_prince_test.1442222848
Short name T403
Test name
Test status
Simulation time 1435267169 ps
CPU time 27.66 seconds
Started Sep 11 10:13:43 AM UTC 24
Finished Sep 11 10:14:18 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1442222848 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 414.prim_prince_test.1442222848
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/414.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/415.prim_prince_test.497137008
Short name T420
Test name
Test status
Simulation time 2475310779 ps
CPU time 47.57 seconds
Started Sep 11 10:13:43 AM UTC 24
Finished Sep 11 10:14:43 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=497137008 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 415.prim_prince_test.497137008
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/415.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/416.prim_prince_test.3326594999
Short name T404
Test name
Test status
Simulation time 1550106841 ps
CPU time 30.35 seconds
Started Sep 11 10:13:45 AM UTC 24
Finished Sep 11 10:14:24 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3326594999 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 416.prim_prince_test.3326594999
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/416.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/417.prim_prince_test.1144908585
Short name T437
Test name
Test status
Simulation time 3656384115 ps
CPU time 68.07 seconds
Started Sep 11 10:13:47 AM UTC 24
Finished Sep 11 10:15:13 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1144908585 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 417.prim_prince_test.1144908585
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/417.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/418.prim_prince_test.1013796986
Short name T421
Test name
Test status
Simulation time 2248372215 ps
CPU time 43.8 seconds
Started Sep 11 10:13:48 AM UTC 24
Finished Sep 11 10:14:43 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1013796986 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 418.prim_prince_test.1013796986
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/418.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/419.prim_prince_test.1710881933
Short name T412
Test name
Test status
Simulation time 1707453894 ps
CPU time 32.36 seconds
Started Sep 11 10:13:50 AM UTC 24
Finished Sep 11 10:14:31 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1710881933 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 419.prim_prince_test.1710881933
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/419.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/42.prim_prince_test.2635224006
Short name T30
Test name
Test status
Simulation time 893111180 ps
CPU time 17.83 seconds
Started Sep 11 10:01:19 AM UTC 24
Finished Sep 11 10:01:42 AM UTC 24
Peak memory 154592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2635224006 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 42.prim_prince_test.2635224006
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/42.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/420.prim_prince_test.3303870988
Short name T442
Test name
Test status
Simulation time 3616467451 ps
CPU time 70.88 seconds
Started Sep 11 10:13:54 AM UTC 24
Finished Sep 11 10:15:22 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3303870988 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 420.prim_prince_test.3303870988
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/420.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/421.prim_prince_test.1901260098
Short name T439
Test name
Test status
Simulation time 3374641868 ps
CPU time 65.47 seconds
Started Sep 11 10:13:55 AM UTC 24
Finished Sep 11 10:15:17 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1901260098 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 421.prim_prince_test.1901260098
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/421.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/422.prim_prince_test.824446180
Short name T415
Test name
Test status
Simulation time 1665748105 ps
CPU time 32.71 seconds
Started Sep 11 10:13:57 AM UTC 24
Finished Sep 11 10:14:39 AM UTC 24
Peak memory 154592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=824446180 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 422.prim_prince_test.824446180
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/422.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/423.prim_prince_test.1977360064
Short name T427
Test name
Test status
Simulation time 2546389698 ps
CPU time 48.49 seconds
Started Sep 11 10:13:58 AM UTC 24
Finished Sep 11 10:14:59 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1977360064 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 423.prim_prince_test.1977360064
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/423.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/424.prim_prince_test.1613960059
Short name T435
Test name
Test status
Simulation time 3025355922 ps
CPU time 57.72 seconds
Started Sep 11 10:14:00 AM UTC 24
Finished Sep 11 10:15:13 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1613960059 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 424.prim_prince_test.1613960059
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/424.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/425.prim_prince_test.3470510644
Short name T414
Test name
Test status
Simulation time 1531475872 ps
CPU time 28.74 seconds
Started Sep 11 10:14:02 AM UTC 24
Finished Sep 11 10:14:39 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3470510644 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 425.prim_prince_test.3470510644
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/425.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/426.prim_prince_test.3018572139
Short name T409
Test name
Test status
Simulation time 1001290919 ps
CPU time 19.36 seconds
Started Sep 11 10:14:03 AM UTC 24
Finished Sep 11 10:14:28 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3018572139 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 426.prim_prince_test.3018572139
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/426.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/427.prim_prince_test.1375263629
Short name T436
Test name
Test status
Simulation time 2797606544 ps
CPU time 55.11 seconds
Started Sep 11 10:14:04 AM UTC 24
Finished Sep 11 10:15:13 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1375263629 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 427.prim_prince_test.1375263629
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/427.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/428.prim_prince_test.1983308347
Short name T445
Test name
Test status
Simulation time 3685419474 ps
CPU time 68.17 seconds
Started Sep 11 10:14:04 AM UTC 24
Finished Sep 11 10:15:30 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1983308347 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 428.prim_prince_test.1983308347
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/428.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/429.prim_prince_test.16190451
Short name T446
Test name
Test status
Simulation time 3612637798 ps
CPU time 66.81 seconds
Started Sep 11 10:14:06 AM UTC 24
Finished Sep 11 10:15:31 AM UTC 24
Peak memory 154656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16190451 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 429.prim_prince_test.16190451
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/429.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/43.prim_prince_test.1356137578
Short name T34
Test name
Test status
Simulation time 1189088574 ps
CPU time 23.57 seconds
Started Sep 11 10:01:21 AM UTC 24
Finished Sep 11 10:01:52 AM UTC 24
Peak memory 154588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1356137578 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 43.prim_prince_test.1356137578
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/43.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/430.prim_prince_test.1318301892
Short name T438
Test name
Test status
Simulation time 2760040051 ps
CPU time 52.67 seconds
Started Sep 11 10:14:07 AM UTC 24
Finished Sep 11 10:15:14 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1318301892 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 430.prim_prince_test.1318301892
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/430.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/431.prim_prince_test.1887391476
Short name T416
Test name
Test status
Simulation time 1208703910 ps
CPU time 22.81 seconds
Started Sep 11 10:14:10 AM UTC 24
Finished Sep 11 10:14:39 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1887391476 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 431.prim_prince_test.1887391476
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/431.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/432.prim_prince_test.875775888
Short name T432
Test name
Test status
Simulation time 1996895184 ps
CPU time 39.31 seconds
Started Sep 11 10:14:17 AM UTC 24
Finished Sep 11 10:15:06 AM UTC 24
Peak memory 154592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=875775888 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 432.prim_prince_test.875775888
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/432.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/433.prim_prince_test.3698945355
Short name T434
Test name
Test status
Simulation time 2145407031 ps
CPU time 40.7 seconds
Started Sep 11 10:14:17 AM UTC 24
Finished Sep 11 10:15:08 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3698945355 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 433.prim_prince_test.3698945355
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/433.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/434.prim_prince_test.1578247770
Short name T422
Test name
Test status
Simulation time 1204643548 ps
CPU time 22.7 seconds
Started Sep 11 10:14:19 AM UTC 24
Finished Sep 11 10:14:49 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1578247770 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 434.prim_prince_test.1578247770
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/434.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/435.prim_prince_test.2384298786
Short name T428
Test name
Test status
Simulation time 1440647785 ps
CPU time 27.36 seconds
Started Sep 11 10:14:25 AM UTC 24
Finished Sep 11 10:15:00 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2384298786 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 435.prim_prince_test.2384298786
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/435.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/436.prim_prince_test.745184085
Short name T426
Test name
Test status
Simulation time 1184682942 ps
CPU time 23.24 seconds
Started Sep 11 10:14:26 AM UTC 24
Finished Sep 11 10:14:55 AM UTC 24
Peak memory 154592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=745184085 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 436.prim_prince_test.745184085
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/436.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/437.prim_prince_test.2382369839
Short name T425
Test name
Test status
Simulation time 1092527821 ps
CPU time 21.32 seconds
Started Sep 11 10:14:26 AM UTC 24
Finished Sep 11 10:14:53 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2382369839 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 437.prim_prince_test.2382369839
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/437.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/438.prim_prince_test.2098766614
Short name T458
Test name
Test status
Simulation time 3657201458 ps
CPU time 70.48 seconds
Started Sep 11 10:14:27 AM UTC 24
Finished Sep 11 10:15:55 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2098766614 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 438.prim_prince_test.2098766614
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/438.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/439.prim_prince_test.2955096834
Short name T447
Test name
Test status
Simulation time 2675495051 ps
CPU time 52.09 seconds
Started Sep 11 10:14:27 AM UTC 24
Finished Sep 11 10:15:32 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2955096834 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 439.prim_prince_test.2955096834
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/439.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/44.prim_prince_test.2095910326
Short name T37
Test name
Test status
Simulation time 1455708968 ps
CPU time 29.25 seconds
Started Sep 11 10:01:21 AM UTC 24
Finished Sep 11 10:01:59 AM UTC 24
Peak memory 154592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2095910326 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 44.prim_prince_test.2095910326
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/44.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/440.prim_prince_test.1121881216
Short name T430
Test name
Test status
Simulation time 1468350841 ps
CPU time 28.38 seconds
Started Sep 11 10:14:28 AM UTC 24
Finished Sep 11 10:15:04 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1121881216 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 440.prim_prince_test.1121881216
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/440.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/441.prim_prince_test.1247889065
Short name T453
Test name
Test status
Simulation time 3355663497 ps
CPU time 61.59 seconds
Started Sep 11 10:14:29 AM UTC 24
Finished Sep 11 10:15:47 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1247889065 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 441.prim_prince_test.1247889065
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/441.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/442.prim_prince_test.2411424878
Short name T455
Test name
Test status
Simulation time 3255224027 ps
CPU time 62.98 seconds
Started Sep 11 10:14:30 AM UTC 24
Finished Sep 11 10:15:49 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2411424878 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 442.prim_prince_test.2411424878
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/442.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/443.prim_prince_test.286461297
Short name T423
Test name
Test status
Simulation time 772750957 ps
CPU time 15.37 seconds
Started Sep 11 10:14:30 AM UTC 24
Finished Sep 11 10:14:50 AM UTC 24
Peak memory 154592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=286461297 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 443.prim_prince_test.286461297
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/443.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/444.prim_prince_test.3163542924
Short name T456
Test name
Test status
Simulation time 3455152051 ps
CPU time 62.95 seconds
Started Sep 11 10:14:32 AM UTC 24
Finished Sep 11 10:15:52 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3163542924 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 444.prim_prince_test.3163542924
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/444.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/445.prim_prince_test.468494774
Short name T465
Test name
Test status
Simulation time 3608401249 ps
CPU time 68.52 seconds
Started Sep 11 10:14:39 AM UTC 24
Finished Sep 11 10:16:05 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=468494774 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 445.prim_prince_test.468494774
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/445.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/446.prim_prince_test.2097238154
Short name T429
Test name
Test status
Simulation time 904036019 ps
CPU time 17.76 seconds
Started Sep 11 10:14:40 AM UTC 24
Finished Sep 11 10:15:03 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2097238154 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 446.prim_prince_test.2097238154
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/446.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/447.prim_prince_test.1222028413
Short name T448
Test name
Test status
Simulation time 2231772659 ps
CPU time 41.33 seconds
Started Sep 11 10:14:40 AM UTC 24
Finished Sep 11 10:15:33 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1222028413 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 447.prim_prince_test.1222028413
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/447.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/448.prim_prince_test.2926838934
Short name T464
Test name
Test status
Simulation time 3512896998 ps
CPU time 67.34 seconds
Started Sep 11 10:14:40 AM UTC 24
Finished Sep 11 10:16:05 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2926838934 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 448.prim_prince_test.2926838934
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/448.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/449.prim_prince_test.614190056
Short name T431
Test name
Test status
Simulation time 914419313 ps
CPU time 17.83 seconds
Started Sep 11 10:14:43 AM UTC 24
Finished Sep 11 10:15:05 AM UTC 24
Peak memory 154592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=614190056 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 449.prim_prince_test.614190056
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/449.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/45.prim_prince_test.995704181
Short name T43
Test name
Test status
Simulation time 2000459851 ps
CPU time 40.21 seconds
Started Sep 11 10:01:24 AM UTC 24
Finished Sep 11 10:02:15 AM UTC 24
Peak memory 154592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=995704181 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 45.prim_prince_test.995704181
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/45.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/450.prim_prince_test.2150765980
Short name T461
Test name
Test status
Simulation time 3117326579 ps
CPU time 61.07 seconds
Started Sep 11 10:14:44 AM UTC 24
Finished Sep 11 10:16:00 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2150765980 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 450.prim_prince_test.2150765980
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/450.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/451.prim_prince_test.3918047225
Short name T462
Test name
Test status
Simulation time 3365658774 ps
CPU time 62.01 seconds
Started Sep 11 10:14:44 AM UTC 24
Finished Sep 11 10:16:03 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3918047225 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 451.prim_prince_test.3918047225
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/451.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/452.prim_prince_test.974548177
Short name T449
Test name
Test status
Simulation time 2117461407 ps
CPU time 41.05 seconds
Started Sep 11 10:14:44 AM UTC 24
Finished Sep 11 10:15:36 AM UTC 24
Peak memory 154592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=974548177 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 452.prim_prince_test.974548177
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/452.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/453.prim_prince_test.2394992964
Short name T444
Test name
Test status
Simulation time 1704151271 ps
CPU time 33.24 seconds
Started Sep 11 10:14:44 AM UTC 24
Finished Sep 11 10:15:26 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2394992964 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 453.prim_prince_test.2394992964
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/453.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/454.prim_prince_test.3366997582
Short name T441
Test name
Test status
Simulation time 1320093021 ps
CPU time 24.47 seconds
Started Sep 11 10:14:49 AM UTC 24
Finished Sep 11 10:15:21 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3366997582 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 454.prim_prince_test.3366997582
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/454.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/455.prim_prince_test.1977984258
Short name T469
Test name
Test status
Simulation time 3113252123 ps
CPU time 61.37 seconds
Started Sep 11 10:14:52 AM UTC 24
Finished Sep 11 10:16:08 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1977984258 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 455.prim_prince_test.1977984258
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/455.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/456.prim_prince_test.1468090451
Short name T450
Test name
Test status
Simulation time 1911057098 ps
CPU time 36.57 seconds
Started Sep 11 10:14:53 AM UTC 24
Finished Sep 11 10:15:39 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1468090451 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 456.prim_prince_test.1468090451
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/456.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/457.prim_prince_test.130560014
Short name T443
Test name
Test status
Simulation time 1258772410 ps
CPU time 22.97 seconds
Started Sep 11 10:14:54 AM UTC 24
Finished Sep 11 10:15:24 AM UTC 24
Peak memory 154592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=130560014 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 457.prim_prince_test.130560014
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/457.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/458.prim_prince_test.3397452046
Short name T440
Test name
Test status
Simulation time 906564755 ps
CPU time 17.68 seconds
Started Sep 11 10:14:56 AM UTC 24
Finished Sep 11 10:15:19 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3397452046 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 458.prim_prince_test.3397452046
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/458.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/459.prim_prince_test.3211377538
Short name T452
Test name
Test status
Simulation time 1882265846 ps
CPU time 37.32 seconds
Started Sep 11 10:15:00 AM UTC 24
Finished Sep 11 10:15:47 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3211377538 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 459.prim_prince_test.3211377538
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/459.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/46.prim_prince_test.725394942
Short name T51
Test name
Test status
Simulation time 2514803618 ps
CPU time 48.66 seconds
Started Sep 11 10:01:25 AM UTC 24
Finished Sep 11 10:02:28 AM UTC 24
Peak memory 154656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=725394942 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 46.prim_prince_test.725394942
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/46.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/460.prim_prince_test.3387600170
Short name T475
Test name
Test status
Simulation time 3334541393 ps
CPU time 63.02 seconds
Started Sep 11 10:15:01 AM UTC 24
Finished Sep 11 10:16:21 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3387600170 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 460.prim_prince_test.3387600170
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/460.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/461.prim_prince_test.3961129207
Short name T467
Test name
Test status
Simulation time 2513485658 ps
CPU time 49.96 seconds
Started Sep 11 10:15:04 AM UTC 24
Finished Sep 11 10:16:06 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3961129207 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 461.prim_prince_test.3961129207
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/461.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/462.prim_prince_test.4024413271
Short name T454
Test name
Test status
Simulation time 1734676840 ps
CPU time 34.48 seconds
Started Sep 11 10:15:05 AM UTC 24
Finished Sep 11 10:15:48 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4024413271 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 462.prim_prince_test.4024413271
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/462.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/463.prim_prince_test.2561789957
Short name T466
Test name
Test status
Simulation time 2387887799 ps
CPU time 47.1 seconds
Started Sep 11 10:15:06 AM UTC 24
Finished Sep 11 10:16:05 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2561789957 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 463.prim_prince_test.2561789957
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/463.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/464.prim_prince_test.3930898453
Short name T474
Test name
Test status
Simulation time 2969094224 ps
CPU time 58.45 seconds
Started Sep 11 10:15:07 AM UTC 24
Finished Sep 11 10:16:20 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3930898453 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 464.prim_prince_test.3930898453
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/464.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/465.prim_prince_test.671423561
Short name T457
Test name
Test status
Simulation time 1893608424 ps
CPU time 36.49 seconds
Started Sep 11 10:15:08 AM UTC 24
Finished Sep 11 10:15:55 AM UTC 24
Peak memory 154592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=671423561 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 465.prim_prince_test.671423561
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/465.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/466.prim_prince_test.1373249645
Short name T488
Test name
Test status
Simulation time 3573209856 ps
CPU time 66.73 seconds
Started Sep 11 10:15:09 AM UTC 24
Finished Sep 11 10:16:34 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1373249645 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 466.prim_prince_test.1373249645
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/466.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/467.prim_prince_test.4225789789
Short name T472
Test name
Test status
Simulation time 2435711022 ps
CPU time 47.82 seconds
Started Sep 11 10:15:14 AM UTC 24
Finished Sep 11 10:16:14 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4225789789 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 467.prim_prince_test.4225789789
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/467.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/468.prim_prince_test.3734874764
Short name T451
Test name
Test status
Simulation time 1050223617 ps
CPU time 19.89 seconds
Started Sep 11 10:15:14 AM UTC 24
Finished Sep 11 10:15:40 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3734874764 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 468.prim_prince_test.3734874764
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/468.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/469.prim_prince_test.1814828497
Short name T485
Test name
Test status
Simulation time 3120953702 ps
CPU time 60.76 seconds
Started Sep 11 10:15:15 AM UTC 24
Finished Sep 11 10:16:32 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1814828497 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 469.prim_prince_test.1814828497
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/469.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/47.prim_prince_test.3706002245
Short name T45
Test name
Test status
Simulation time 1936279729 ps
CPU time 38.48 seconds
Started Sep 11 10:01:28 AM UTC 24
Finished Sep 11 10:02:18 AM UTC 24
Peak memory 154592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3706002245 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 47.prim_prince_test.3706002245
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/47.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/470.prim_prince_test.46053240
Short name T468
Test name
Test status
Simulation time 2063033281 ps
CPU time 40.05 seconds
Started Sep 11 10:15:15 AM UTC 24
Finished Sep 11 10:16:06 AM UTC 24
Peak memory 154592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=46053240 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 470.prim_prince_test.46053240
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/470.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/471.prim_prince_test.4125813988
Short name T459
Test name
Test status
Simulation time 1643445262 ps
CPU time 30.9 seconds
Started Sep 11 10:15:17 AM UTC 24
Finished Sep 11 10:15:57 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4125813988 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 471.prim_prince_test.4125813988
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/471.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/472.prim_prince_test.2715705928
Short name T473
Test name
Test status
Simulation time 2262305750 ps
CPU time 44.06 seconds
Started Sep 11 10:15:19 AM UTC 24
Finished Sep 11 10:16:15 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2715705928 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 472.prim_prince_test.2715705928
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/472.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/473.prim_prince_test.348878600
Short name T471
Test name
Test status
Simulation time 2053427898 ps
CPU time 37.74 seconds
Started Sep 11 10:15:22 AM UTC 24
Finished Sep 11 10:16:10 AM UTC 24
Peak memory 154592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=348878600 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 473.prim_prince_test.348878600
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/473.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/474.prim_prince_test.3268467839
Short name T493
Test name
Test status
Simulation time 3152603317 ps
CPU time 61.68 seconds
Started Sep 11 10:15:23 AM UTC 24
Finished Sep 11 10:16:40 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3268467839 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 474.prim_prince_test.3268467839
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/474.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/475.prim_prince_test.3883551271
Short name T484
Test name
Test status
Simulation time 2576598921 ps
CPU time 50.33 seconds
Started Sep 11 10:15:25 AM UTC 24
Finished Sep 11 10:16:29 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3883551271 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 475.prim_prince_test.3883551271
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/475.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/476.prim_prince_test.45302134
Short name T495
Test name
Test status
Simulation time 3350507334 ps
CPU time 62.61 seconds
Started Sep 11 10:15:27 AM UTC 24
Finished Sep 11 10:16:47 AM UTC 24
Peak memory 154656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=45302134 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 476.prim_prince_test.45302134
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/476.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/477.prim_prince_test.2052381496
Short name T497
Test name
Test status
Simulation time 3720616815 ps
CPU time 69.5 seconds
Started Sep 11 10:15:31 AM UTC 24
Finished Sep 11 10:17:01 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2052381496 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 477.prim_prince_test.2052381496
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/477.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/478.prim_prince_test.4158331905
Short name T490
Test name
Test status
Simulation time 2604633489 ps
CPU time 50.97 seconds
Started Sep 11 10:15:33 AM UTC 24
Finished Sep 11 10:16:37 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4158331905 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 478.prim_prince_test.4158331905
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/478.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/479.prim_prince_test.946799970
Short name T487
Test name
Test status
Simulation time 2492651775 ps
CPU time 48.19 seconds
Started Sep 11 10:15:33 AM UTC 24
Finished Sep 11 10:16:33 AM UTC 24
Peak memory 154656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=946799970 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 479.prim_prince_test.946799970
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/479.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/48.prim_prince_test.1804023755
Short name T54
Test name
Test status
Simulation time 2497589040 ps
CPU time 47.34 seconds
Started Sep 11 10:01:31 AM UTC 24
Finished Sep 11 10:02:33 AM UTC 24
Peak memory 154656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1804023755 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 48.prim_prince_test.1804023755
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/48.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/480.prim_prince_test.1495336457
Short name T491
Test name
Test status
Simulation time 2790113928 ps
CPU time 51.62 seconds
Started Sep 11 10:15:34 AM UTC 24
Finished Sep 11 10:16:40 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1495336457 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 480.prim_prince_test.1495336457
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/480.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/481.prim_prince_test.3445554068
Short name T460
Test name
Test status
Simulation time 836732348 ps
CPU time 16.57 seconds
Started Sep 11 10:15:37 AM UTC 24
Finished Sep 11 10:15:59 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3445554068 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 481.prim_prince_test.3445554068
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/481.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/482.prim_prince_test.459642135
Short name T463
Test name
Test status
Simulation time 887210287 ps
CPU time 17.58 seconds
Started Sep 11 10:15:40 AM UTC 24
Finished Sep 11 10:16:03 AM UTC 24
Peak memory 154592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=459642135 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 482.prim_prince_test.459642135
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/482.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/483.prim_prince_test.892860190
Short name T477
Test name
Test status
Simulation time 1728860201 ps
CPU time 33.95 seconds
Started Sep 11 10:15:40 AM UTC 24
Finished Sep 11 10:16:23 AM UTC 24
Peak memory 154592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=892860190 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 483.prim_prince_test.892860190
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/483.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/484.prim_prince_test.3556769622
Short name T483
Test name
Test status
Simulation time 1578809801 ps
CPU time 31.38 seconds
Started Sep 11 10:15:49 AM UTC 24
Finished Sep 11 10:16:28 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3556769622 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 484.prim_prince_test.3556769622
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/484.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/485.prim_prince_test.4113226969
Short name T470
Test name
Test status
Simulation time 778691483 ps
CPU time 15.09 seconds
Started Sep 11 10:15:49 AM UTC 24
Finished Sep 11 10:16:08 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4113226969 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 485.prim_prince_test.4113226969
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/485.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/486.prim_prince_test.940680164
Short name T496
Test name
Test status
Simulation time 2648415504 ps
CPU time 52.96 seconds
Started Sep 11 10:15:49 AM UTC 24
Finished Sep 11 10:16:56 AM UTC 24
Peak memory 154656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=940680164 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 486.prim_prince_test.940680164
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/486.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/487.prim_prince_test.3003880389
Short name T482
Test name
Test status
Simulation time 1579605404 ps
CPU time 29.25 seconds
Started Sep 11 10:15:50 AM UTC 24
Finished Sep 11 10:16:28 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3003880389 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 487.prim_prince_test.3003880389
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/487.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/488.prim_prince_test.2914358232
Short name T494
Test name
Test status
Simulation time 2025438363 ps
CPU time 40.25 seconds
Started Sep 11 10:15:53 AM UTC 24
Finished Sep 11 10:16:44 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2914358232 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 488.prim_prince_test.2914358232
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/488.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/489.prim_prince_test.3886108484
Short name T489
Test name
Test status
Simulation time 1598599910 ps
CPU time 31.24 seconds
Started Sep 11 10:15:55 AM UTC 24
Finished Sep 11 10:16:35 AM UTC 24
Peak memory 154576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3886108484 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 489.prim_prince_test.3886108484
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/489.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/49.prim_prince_test.2994623940
Short name T62
Test name
Test status
Simulation time 3606164810 ps
CPU time 67.72 seconds
Started Sep 11 10:01:32 AM UTC 24
Finished Sep 11 10:03:00 AM UTC 24
Peak memory 154656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2994623940 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 49.prim_prince_test.2994623940
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/49.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/490.prim_prince_test.3073842813
Short name T480
Test name
Test status
Simulation time 1195642493 ps
CPU time 22.79 seconds
Started Sep 11 10:15:55 AM UTC 24
Finished Sep 11 10:16:25 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3073842813 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 490.prim_prince_test.3073842813
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/490.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/491.prim_prince_test.1704039164
Short name T499
Test name
Test status
Simulation time 3254071455 ps
CPU time 67.2 seconds
Started Sep 11 10:15:58 AM UTC 24
Finished Sep 11 10:17:24 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1704039164 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 491.prim_prince_test.1704039164
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/491.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/492.prim_prince_test.3664262837
Short name T476
Test name
Test status
Simulation time 885689704 ps
CPU time 18.36 seconds
Started Sep 11 10:16:00 AM UTC 24
Finished Sep 11 10:16:23 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3664262837 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 492.prim_prince_test.3664262837
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/492.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/493.prim_prince_test.2494719190
Short name T478
Test name
Test status
Simulation time 861277845 ps
CPU time 17.44 seconds
Started Sep 11 10:16:01 AM UTC 24
Finished Sep 11 10:16:24 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2494719190 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 493.prim_prince_test.2494719190
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/493.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/494.prim_prince_test.2320679108
Short name T498
Test name
Test status
Simulation time 2950700699 ps
CPU time 57.92 seconds
Started Sep 11 10:16:04 AM UTC 24
Finished Sep 11 10:17:19 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2320679108 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 494.prim_prince_test.2320679108
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/494.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/495.prim_prince_test.4179860225
Short name T492
Test name
Test status
Simulation time 1425465756 ps
CPU time 28.16 seconds
Started Sep 11 10:16:04 AM UTC 24
Finished Sep 11 10:16:40 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4179860225 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 495.prim_prince_test.4179860225
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/495.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/496.prim_prince_test.886526391
Short name T481
Test name
Test status
Simulation time 827461264 ps
CPU time 16.34 seconds
Started Sep 11 10:16:06 AM UTC 24
Finished Sep 11 10:16:27 AM UTC 24
Peak memory 154356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=886526391 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 496.prim_prince_test.886526391
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/496.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/497.prim_prince_test.868004807
Short name T479
Test name
Test status
Simulation time 769958080 ps
CPU time 14.47 seconds
Started Sep 11 10:16:06 AM UTC 24
Finished Sep 11 10:16:25 AM UTC 24
Peak memory 154436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=868004807 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 497.prim_prince_test.868004807
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/497.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/498.prim_prince_test.2595693841
Short name T500
Test name
Test status
Simulation time 3156674911 ps
CPU time 61.43 seconds
Started Sep 11 10:16:06 AM UTC 24
Finished Sep 11 10:17:26 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2595693841 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 498.prim_prince_test.2595693841
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/498.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/499.prim_prince_test.3038788536
Short name T486
Test name
Test status
Simulation time 989410782 ps
CPU time 20.02 seconds
Started Sep 11 10:16:07 AM UTC 24
Finished Sep 11 10:16:33 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3038788536 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 499.prim_prince_test.3038788536
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/499.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/5.prim_prince_test.1560004015
Short name T5
Test name
Test status
Simulation time 1341247055 ps
CPU time 27.31 seconds
Started Sep 11 09:59:56 AM UTC 24
Finished Sep 11 10:00:32 AM UTC 24
Peak memory 154592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1560004015 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 5.prim_prince_test.1560004015
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/5.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/50.prim_prince_test.3468496230
Short name T56
Test name
Test status
Simulation time 2750929374 ps
CPU time 53.65 seconds
Started Sep 11 10:01:33 AM UTC 24
Finished Sep 11 10:02:41 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3468496230 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 50.prim_prince_test.3468496230
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/50.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/51.prim_prince_test.1772116501
Short name T47
Test name
Test status
Simulation time 1659109989 ps
CPU time 33.46 seconds
Started Sep 11 10:01:39 AM UTC 24
Finished Sep 11 10:02:21 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1772116501 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 51.prim_prince_test.1772116501
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/51.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/52.prim_prince_test.2028602174
Short name T71
Test name
Test status
Simulation time 3560362789 ps
CPU time 67.21 seconds
Started Sep 11 10:01:43 AM UTC 24
Finished Sep 11 10:03:10 AM UTC 24
Peak memory 154644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2028602174 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 52.prim_prince_test.2028602174
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/52.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/53.prim_prince_test.3481628620
Short name T69
Test name
Test status
Simulation time 3379833623 ps
CPU time 66.62 seconds
Started Sep 11 10:01:44 AM UTC 24
Finished Sep 11 10:03:08 AM UTC 24
Peak memory 154656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3481628620 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 53.prim_prince_test.3481628620
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/53.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/54.prim_prince_test.986591461
Short name T49
Test name
Test status
Simulation time 1532833790 ps
CPU time 29.38 seconds
Started Sep 11 10:01:45 AM UTC 24
Finished Sep 11 10:02:23 AM UTC 24
Peak memory 154592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=986591461 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 54.prim_prince_test.986591461
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/54.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/55.prim_prince_test.3168455959
Short name T48
Test name
Test status
Simulation time 1404338884 ps
CPU time 28.15 seconds
Started Sep 11 10:01:46 AM UTC 24
Finished Sep 11 10:02:22 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3168455959 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 55.prim_prince_test.3168455959
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/55.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/56.prim_prince_test.1719916217
Short name T53
Test name
Test status
Simulation time 1640141145 ps
CPU time 31.41 seconds
Started Sep 11 10:01:50 AM UTC 24
Finished Sep 11 10:02:31 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1719916217 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 56.prim_prince_test.1719916217
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/56.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/57.prim_prince_test.1847404572
Short name T50
Test name
Test status
Simulation time 1266929918 ps
CPU time 25.35 seconds
Started Sep 11 10:01:52 AM UTC 24
Finished Sep 11 10:02:25 AM UTC 24
Peak memory 154592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1847404572 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 57.prim_prince_test.1847404572
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/57.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/58.prim_prince_test.739382055
Short name T61
Test name
Test status
Simulation time 2731045587 ps
CPU time 51.18 seconds
Started Sep 11 10:01:52 AM UTC 24
Finished Sep 11 10:02:59 AM UTC 24
Peak memory 154656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=739382055 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 58.prim_prince_test.739382055
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/58.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/59.prim_prince_test.2098500148
Short name T63
Test name
Test status
Simulation time 2608657951 ps
CPU time 49.11 seconds
Started Sep 11 10:01:56 AM UTC 24
Finished Sep 11 10:03:00 AM UTC 24
Peak memory 154656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2098500148 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 59.prim_prince_test.2098500148
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/59.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/6.prim_prince_test.3641508604
Short name T13
Test name
Test status
Simulation time 2432743622 ps
CPU time 49.85 seconds
Started Sep 11 09:59:56 AM UTC 24
Finished Sep 11 10:01:01 AM UTC 24
Peak memory 154656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3641508604 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 6.prim_prince_test.3641508604
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/6.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/60.prim_prince_test.1487418968
Short name T78
Test name
Test status
Simulation time 3658192070 ps
CPU time 72.46 seconds
Started Sep 11 10:01:56 AM UTC 24
Finished Sep 11 10:03:28 AM UTC 24
Peak memory 154656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1487418968 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 60.prim_prince_test.1487418968
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/60.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/61.prim_prince_test.379576580
Short name T57
Test name
Test status
Simulation time 1935613278 ps
CPU time 38.15 seconds
Started Sep 11 10:01:59 AM UTC 24
Finished Sep 11 10:02:48 AM UTC 24
Peak memory 154592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=379576580 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 61.prim_prince_test.379576580
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/61.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/62.prim_prince_test.2592546253
Short name T75
Test name
Test status
Simulation time 3471202782 ps
CPU time 67.86 seconds
Started Sep 11 10:02:01 AM UTC 24
Finished Sep 11 10:03:27 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2592546253 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 62.prim_prince_test.2592546253
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/62.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/63.prim_prince_test.3782633213
Short name T76
Test name
Test status
Simulation time 3385916132 ps
CPU time 67.61 seconds
Started Sep 11 10:02:02 AM UTC 24
Finished Sep 11 10:03:27 AM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3782633213 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 63.prim_prince_test.3782633213
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/63.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/64.prim_prince_test.564451097
Short name T64
Test name
Test status
Simulation time 2274209795 ps
CPU time 43.99 seconds
Started Sep 11 10:02:06 AM UTC 24
Finished Sep 11 10:03:02 AM UTC 24
Peak memory 154656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=564451097 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 64.prim_prince_test.564451097
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/64.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/65.prim_prince_test.3235663887
Short name T74
Test name
Test status
Simulation time 3134412769 ps
CPU time 61.94 seconds
Started Sep 11 10:02:07 AM UTC 24
Finished Sep 11 10:03:26 AM UTC 24
Peak memory 154656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3235663887 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 65.prim_prince_test.3235663887
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/65.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/66.prim_prince_test.4080663165
Short name T79
Test name
Test status
Simulation time 3184907022 ps
CPU time 59.68 seconds
Started Sep 11 10:02:14 AM UTC 24
Finished Sep 11 10:03:31 AM UTC 24
Peak memory 154656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4080663165 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 66.prim_prince_test.4080663165
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/66.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/67.prim_prince_test.751903210
Short name T55
Test name
Test status
Simulation time 907329227 ps
CPU time 18.22 seconds
Started Sep 11 10:02:16 AM UTC 24
Finished Sep 11 10:02:40 AM UTC 24
Peak memory 154592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=751903210 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 67.prim_prince_test.751903210
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/67.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/68.prim_prince_test.3172455395
Short name T59
Test name
Test status
Simulation time 1529293328 ps
CPU time 30.27 seconds
Started Sep 11 10:02:18 AM UTC 24
Finished Sep 11 10:02:57 AM UTC 24
Peak memory 154592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3172455395 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 68.prim_prince_test.3172455395
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/68.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/69.prim_prince_test.4057266761
Short name T81
Test name
Test status
Simulation time 3065961457 ps
CPU time 61.82 seconds
Started Sep 11 10:02:18 AM UTC 24
Finished Sep 11 10:03:36 AM UTC 24
Peak memory 154656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4057266761 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 69.prim_prince_test.4057266761
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/69.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/7.prim_prince_test.518528721
Short name T1
Test name
Test status
Simulation time 798595045 ps
CPU time 16.83 seconds
Started Sep 11 09:59:56 AM UTC 24
Finished Sep 11 10:00:19 AM UTC 24
Peak memory 154652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=518528721 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 7.prim_prince_test.518528721
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/7.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/70.prim_prince_test.2525371816
Short name T67
Test name
Test status
Simulation time 1810383049 ps
CPU time 34.24 seconds
Started Sep 11 10:02:20 AM UTC 24
Finished Sep 11 10:03:05 AM UTC 24
Peak memory 154592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2525371816 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 70.prim_prince_test.2525371816
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/70.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/71.prim_prince_test.2558505542
Short name T83
Test name
Test status
Simulation time 3124015368 ps
CPU time 60.25 seconds
Started Sep 11 10:02:22 AM UTC 24
Finished Sep 11 10:03:39 AM UTC 24
Peak memory 154656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2558505542 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 71.prim_prince_test.2558505542
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/71.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/72.prim_prince_test.3797705072
Short name T70
Test name
Test status
Simulation time 1843840141 ps
CPU time 36.11 seconds
Started Sep 11 10:02:23 AM UTC 24
Finished Sep 11 10:03:10 AM UTC 24
Peak memory 156048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3797705072 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 72.prim_prince_test.3797705072
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/72.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/73.prim_prince_test.423787632
Short name T65
Test name
Test status
Simulation time 1486650308 ps
CPU time 29.61 seconds
Started Sep 11 10:02:24 AM UTC 24
Finished Sep 11 10:03:02 AM UTC 24
Peak memory 154592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=423787632 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 73.prim_prince_test.423787632
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/73.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/74.prim_prince_test.4063803909
Short name T60
Test name
Test status
Simulation time 1298967507 ps
CPU time 24.27 seconds
Started Sep 11 10:02:25 AM UTC 24
Finished Sep 11 10:02:57 AM UTC 24
Peak memory 154592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4063803909 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 74.prim_prince_test.4063803909
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/74.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/75.prim_prince_test.2670992360
Short name T89
Test name
Test status
Simulation time 3494757610 ps
CPU time 65.76 seconds
Started Sep 11 10:02:28 AM UTC 24
Finished Sep 11 10:03:53 AM UTC 24
Peak memory 154656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2670992360 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 75.prim_prince_test.2670992360
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/75.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/76.prim_prince_test.3366328946
Short name T58
Test name
Test status
Simulation time 781410705 ps
CPU time 15.04 seconds
Started Sep 11 10:02:31 AM UTC 24
Finished Sep 11 10:02:50 AM UTC 24
Peak memory 154592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3366328946 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 76.prim_prince_test.3366328946
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/76.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/77.prim_prince_test.2647732759
Short name T77
Test name
Test status
Simulation time 2217869346 ps
CPU time 43.89 seconds
Started Sep 11 10:02:32 AM UTC 24
Finished Sep 11 10:03:28 AM UTC 24
Peak memory 154656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2647732759 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 77.prim_prince_test.2647732759
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/77.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/78.prim_prince_test.3944908819
Short name T66
Test name
Test status
Simulation time 1198001633 ps
CPU time 22.98 seconds
Started Sep 11 10:02:34 AM UTC 24
Finished Sep 11 10:03:04 AM UTC 24
Peak memory 154592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3944908819 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 78.prim_prince_test.3944908819
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/78.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/79.prim_prince_test.1861770892
Short name T91
Test name
Test status
Simulation time 2980796954 ps
CPU time 58.17 seconds
Started Sep 11 10:02:41 AM UTC 24
Finished Sep 11 10:03:55 AM UTC 24
Peak memory 154656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1861770892 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 79.prim_prince_test.1861770892
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/79.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/8.prim_prince_test.3659572189
Short name T22
Test name
Test status
Simulation time 3339434998 ps
CPU time 68.06 seconds
Started Sep 11 09:59:56 AM UTC 24
Finished Sep 11 10:01:24 AM UTC 24
Peak memory 154656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3659572189 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 8.prim_prince_test.3659572189
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/8.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/80.prim_prince_test.1226615920
Short name T68
Test name
Test status
Simulation time 1027478904 ps
CPU time 19.8 seconds
Started Sep 11 10:02:42 AM UTC 24
Finished Sep 11 10:03:08 AM UTC 24
Peak memory 154592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1226615920 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 80.prim_prince_test.1226615920
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/80.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/81.prim_prince_test.4003196042
Short name T84
Test name
Test status
Simulation time 2054141386 ps
CPU time 41.13 seconds
Started Sep 11 10:02:49 AM UTC 24
Finished Sep 11 10:03:41 AM UTC 24
Peak memory 154592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4003196042 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 81.prim_prince_test.4003196042
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/81.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/82.prim_prince_test.4282605249
Short name T80
Test name
Test status
Simulation time 1576737781 ps
CPU time 31.48 seconds
Started Sep 11 10:02:51 AM UTC 24
Finished Sep 11 10:03:31 AM UTC 24
Peak memory 154592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4282605249 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 82.prim_prince_test.4282605249
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/82.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/83.prim_prince_test.1000997433
Short name T73
Test name
Test status
Simulation time 995440943 ps
CPU time 18.94 seconds
Started Sep 11 10:02:58 AM UTC 24
Finished Sep 11 10:03:23 AM UTC 24
Peak memory 154592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1000997433 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 83.prim_prince_test.1000997433
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/83.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/84.prim_prince_test.3629868797
Short name T72
Test name
Test status
Simulation time 836384031 ps
CPU time 16.36 seconds
Started Sep 11 10:02:58 AM UTC 24
Finished Sep 11 10:03:20 AM UTC 24
Peak memory 154592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3629868797 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 84.prim_prince_test.3629868797
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/84.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/85.prim_prince_test.4152330610
Short name T100
Test name
Test status
Simulation time 3401558903 ps
CPU time 63.62 seconds
Started Sep 11 10:02:59 AM UTC 24
Finished Sep 11 10:04:21 AM UTC 24
Peak memory 154656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4152330610 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 85.prim_prince_test.4152330610
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/85.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/86.prim_prince_test.2335557956
Short name T98
Test name
Test status
Simulation time 3205222205 ps
CPU time 63.47 seconds
Started Sep 11 10:03:00 AM UTC 24
Finished Sep 11 10:04:21 AM UTC 24
Peak memory 154656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2335557956 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 86.prim_prince_test.2335557956
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/86.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/87.prim_prince_test.4020561109
Short name T82
Test name
Test status
Simulation time 1418999197 ps
CPU time 29.03 seconds
Started Sep 11 10:03:00 AM UTC 24
Finished Sep 11 10:03:37 AM UTC 24
Peak memory 154592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4020561109 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 87.prim_prince_test.4020561109
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/87.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/88.prim_prince_test.563866109
Short name T95
Test name
Test status
Simulation time 2670536259 ps
CPU time 53.52 seconds
Started Sep 11 10:03:03 AM UTC 24
Finished Sep 11 10:04:11 AM UTC 24
Peak memory 154656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=563866109 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 88.prim_prince_test.563866109
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/88.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/89.prim_prince_test.3590016655
Short name T103
Test name
Test status
Simulation time 3508984404 ps
CPU time 68.5 seconds
Started Sep 11 10:03:03 AM UTC 24
Finished Sep 11 10:04:30 AM UTC 24
Peak memory 154656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3590016655 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 89.prim_prince_test.3590016655
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/89.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/9.prim_prince_test.3307097297
Short name T27
Test name
Test status
Simulation time 3715757470 ps
CPU time 74 seconds
Started Sep 11 09:59:56 AM UTC 24
Finished Sep 11 10:01:32 AM UTC 24
Peak memory 154656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3307097297 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 9.prim_prince_test.3307097297
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/9.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/90.prim_prince_test.3691906796
Short name T85
Test name
Test status
Simulation time 1462327275 ps
CPU time 29.95 seconds
Started Sep 11 10:03:05 AM UTC 24
Finished Sep 11 10:03:43 AM UTC 24
Peak memory 154592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3691906796 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 90.prim_prince_test.3691906796
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/90.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/91.prim_prince_test.2646578545
Short name T88
Test name
Test status
Simulation time 1776397522 ps
CPU time 35 seconds
Started Sep 11 10:03:05 AM UTC 24
Finished Sep 11 10:03:50 AM UTC 24
Peak memory 154584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2646578545 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 91.prim_prince_test.2646578545
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/91.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/92.prim_prince_test.4137603256
Short name T87
Test name
Test status
Simulation time 1637912264 ps
CPU time 33.06 seconds
Started Sep 11 10:03:06 AM UTC 24
Finished Sep 11 10:03:48 AM UTC 24
Peak memory 154592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4137603256 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 92.prim_prince_test.4137603256
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/92.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/93.prim_prince_test.3945036879
Short name T97
Test name
Test status
Simulation time 2611999043 ps
CPU time 52.27 seconds
Started Sep 11 10:03:09 AM UTC 24
Finished Sep 11 10:04:15 AM UTC 24
Peak memory 154656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3945036879 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 93.prim_prince_test.3945036879
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/93.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/94.prim_prince_test.118722262
Short name T94
Test name
Test status
Simulation time 2413736690 ps
CPU time 45.98 seconds
Started Sep 11 10:03:09 AM UTC 24
Finished Sep 11 10:04:08 AM UTC 24
Peak memory 154656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=118722262 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 94.prim_prince_test.118722262
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/94.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/95.prim_prince_test.1210709375
Short name T90
Test name
Test status
Simulation time 1774779717 ps
CPU time 34.4 seconds
Started Sep 11 10:03:10 AM UTC 24
Finished Sep 11 10:03:55 AM UTC 24
Peak memory 154592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1210709375 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 95.prim_prince_test.1210709375
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/95.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/96.prim_prince_test.1056516968
Short name T86
Test name
Test status
Simulation time 1440989609 ps
CPU time 27.77 seconds
Started Sep 11 10:03:10 AM UTC 24
Finished Sep 11 10:03:46 AM UTC 24
Peak memory 154592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1056516968 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 96.prim_prince_test.1056516968
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/96.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/97.prim_prince_test.2146854977
Short name T112
Test name
Test status
Simulation time 3595542041 ps
CPU time 67.84 seconds
Started Sep 11 10:03:20 AM UTC 24
Finished Sep 11 10:04:48 AM UTC 24
Peak memory 154656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2146854977 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 97.prim_prince_test.2146854977
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/97.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/98.prim_prince_test.1439081455
Short name T104
Test name
Test status
Simulation time 2765710677 ps
CPU time 54.21 seconds
Started Sep 11 10:03:24 AM UTC 24
Finished Sep 11 10:04:34 AM UTC 24
Peak memory 154656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1439081455 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 98.prim_prince_test.1439081455
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/98.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default/99.prim_prince_test.712797210
Short name T111
Test name
Test status
Simulation time 3311698268 ps
CPU time 62.18 seconds
Started Sep 11 10:03:26 AM UTC 24
Finished Sep 11 10:04:47 AM UTC 24
Peak memory 154656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=712797210 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 99.prim_prince_test.712797210
Directory /workspaces/repo/scratch/os_regression_2024_09_10/prim_prince-sim-vcs/99.prim_prince_test/latest
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