| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 | 100.00 | 100.00 | 100.00 | 100.00 |
| T251 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/266.prim_prince_test.2513822362 | Sep 18 09:54:43 AM UTC 24 | Sep 18 09:55:15 AM UTC 24 | 1318117209 ps | ||
| T252 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/239.prim_prince_test.1009292889 | Sep 18 09:54:02 AM UTC 24 | Sep 18 09:55:16 AM UTC 24 | 3139586342 ps | ||
| T253 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/238.prim_prince_test.4124360366 | Sep 18 09:54:02 AM UTC 24 | Sep 18 09:55:16 AM UTC 24 | 3235006984 ps | ||
| T254 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/251.prim_prince_test.891305754 | Sep 18 09:54:20 AM UTC 24 | Sep 18 09:55:25 AM UTC 24 | 2730279399 ps | ||
| T255 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/275.prim_prince_test.2984002687 | Sep 18 09:54:58 AM UTC 24 | Sep 18 09:55:26 AM UTC 24 | 1108307647 ps | ||
| T256 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/258.prim_prince_test.2476503925 | Sep 18 09:54:34 AM UTC 24 | Sep 18 09:55:27 AM UTC 24 | 2208120680 ps | ||
| T257 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/235.prim_prince_test.3591392841 | Sep 18 09:53:59 AM UTC 24 | Sep 18 09:55:28 AM UTC 24 | 3696054090 ps | ||
| T258 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/270.prim_prince_test.3921055451 | Sep 18 09:54:48 AM UTC 24 | Sep 18 09:55:30 AM UTC 24 | 1723337296 ps | ||
| T259 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/253.prim_prince_test.684209163 | Sep 18 09:54:24 AM UTC 24 | Sep 18 09:55:31 AM UTC 24 | 2823875468 ps | ||
| T260 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/247.prim_prince_test.4283435129 | Sep 18 09:54:15 AM UTC 24 | Sep 18 09:55:34 AM UTC 24 | 3365405847 ps | ||
| T261 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/285.prim_prince_test.2604791963 | Sep 18 09:55:17 AM UTC 24 | Sep 18 09:55:36 AM UTC 24 | 752572549 ps | ||
| T262 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/254.prim_prince_test.3551065409 | Sep 18 09:54:25 AM UTC 24 | Sep 18 09:55:38 AM UTC 24 | 3073940465 ps | ||
| T263 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/265.prim_prince_test.1599975166 | Sep 18 09:54:41 AM UTC 24 | Sep 18 09:55:41 AM UTC 24 | 2466586410 ps | ||
| T264 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/284.prim_prince_test.1136339998 | Sep 18 09:55:17 AM UTC 24 | Sep 18 09:55:46 AM UTC 24 | 1173721243 ps | ||
| T265 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/259.prim_prince_test.3565349963 | Sep 18 09:54:38 AM UTC 24 | Sep 18 09:55:46 AM UTC 24 | 2884267734 ps | ||
| T266 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/255.prim_prince_test.882411336 | Sep 18 09:54:25 AM UTC 24 | Sep 18 09:55:48 AM UTC 24 | 3451776218 ps | ||
| T267 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/256.prim_prince_test.343913594 | Sep 18 09:54:30 AM UTC 24 | Sep 18 09:55:49 AM UTC 24 | 3307236206 ps | ||
| T268 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/262.prim_prince_test.2716155962 | Sep 18 09:54:41 AM UTC 24 | Sep 18 09:55:51 AM UTC 24 | 3001452455 ps | ||
| T269 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/260.prim_prince_test.696874701 | Sep 18 09:54:38 AM UTC 24 | Sep 18 09:55:51 AM UTC 24 | 3038088289 ps | ||
| T270 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/257.prim_prince_test.3731882837 | Sep 18 09:54:32 AM UTC 24 | Sep 18 09:55:52 AM UTC 24 | 3430346608 ps | ||
| T271 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/289.prim_prince_test.2777357715 | Sep 18 09:55:28 AM UTC 24 | Sep 18 09:55:52 AM UTC 24 | 962966082 ps | ||
| T272 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/261.prim_prince_test.526744218 | Sep 18 09:54:39 AM UTC 24 | Sep 18 09:55:53 AM UTC 24 | 3173049550 ps | ||
| T273 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/278.prim_prince_test.3880336166 | Sep 18 09:55:07 AM UTC 24 | Sep 18 09:55:53 AM UTC 24 | 1964684518 ps | ||
| T274 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/267.prim_prince_test.3944388650 | Sep 18 09:54:47 AM UTC 24 | Sep 18 09:55:58 AM UTC 24 | 2999808517 ps | ||
| T275 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/264.prim_prince_test.270715373 | Sep 18 09:54:41 AM UTC 24 | Sep 18 09:55:59 AM UTC 24 | 3332738609 ps | ||
| T276 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/273.prim_prince_test.3160951180 | Sep 18 09:54:54 AM UTC 24 | Sep 18 09:56:00 AM UTC 24 | 2741001439 ps | ||
| T277 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/276.prim_prince_test.1416820513 | Sep 18 09:55:01 AM UTC 24 | Sep 18 09:56:01 AM UTC 24 | 2497623413 ps | ||
| T278 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/269.prim_prince_test.3520974672 | Sep 18 09:54:47 AM UTC 24 | Sep 18 09:56:01 AM UTC 24 | 3185174694 ps | ||
| T279 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/282.prim_prince_test.640388582 | Sep 18 09:55:11 AM UTC 24 | Sep 18 09:56:02 AM UTC 24 | 2065444876 ps | ||
| T280 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/271.prim_prince_test.1630650274 | Sep 18 09:54:50 AM UTC 24 | Sep 18 09:56:08 AM UTC 24 | 3258575690 ps | ||
| T281 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/287.prim_prince_test.2986199297 | Sep 18 09:55:26 AM UTC 24 | Sep 18 09:56:08 AM UTC 24 | 1722922273 ps | ||
| T282 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/295.prim_prince_test.4073242809 | Sep 18 09:55:39 AM UTC 24 | Sep 18 09:56:09 AM UTC 24 | 1227066135 ps | ||
| T283 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/288.prim_prince_test.812696051 | Sep 18 09:55:26 AM UTC 24 | Sep 18 09:56:10 AM UTC 24 | 1792922044 ps | ||
| T284 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/296.prim_prince_test.3226342623 | Sep 18 09:55:42 AM UTC 24 | Sep 18 09:56:11 AM UTC 24 | 1192872549 ps | ||
| T285 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/281.prim_prince_test.3262515274 | Sep 18 09:55:09 AM UTC 24 | Sep 18 09:56:12 AM UTC 24 | 2581793636 ps | ||
| T286 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/291.prim_prince_test.3076929888 | Sep 18 09:55:30 AM UTC 24 | Sep 18 09:56:12 AM UTC 24 | 1712773412 ps | ||
| T287 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/272.prim_prince_test.3113239769 | Sep 18 09:54:50 AM UTC 24 | Sep 18 09:56:13 AM UTC 24 | 3600238183 ps | ||
| T288 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/301.prim_prince_test.3204923674 | Sep 18 09:55:52 AM UTC 24 | Sep 18 09:56:16 AM UTC 24 | 976678112 ps | ||
| T289 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/274.prim_prince_test.2091220462 | Sep 18 09:54:58 AM UTC 24 | Sep 18 09:56:19 AM UTC 24 | 3455052022 ps | ||
| T290 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/283.prim_prince_test.1922656066 | Sep 18 09:55:15 AM UTC 24 | Sep 18 09:56:19 AM UTC 24 | 2650697674 ps | ||
| T291 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/303.prim_prince_test.165404202 | Sep 18 09:55:53 AM UTC 24 | Sep 18 09:56:20 AM UTC 24 | 1077072460 ps | ||
| T292 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/304.prim_prince_test.3445439996 | Sep 18 09:55:53 AM UTC 24 | Sep 18 09:56:21 AM UTC 24 | 1123820184 ps | ||
| T293 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/292.prim_prince_test.268628930 | Sep 18 09:55:32 AM UTC 24 | Sep 18 09:56:21 AM UTC 24 | 1964992409 ps | ||
| T294 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/299.prim_prince_test.2751434950 | Sep 18 09:55:48 AM UTC 24 | Sep 18 09:56:24 AM UTC 24 | 1446802246 ps | ||
| T295 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/277.prim_prince_test.2188062067 | Sep 18 09:55:03 AM UTC 24 | Sep 18 09:56:28 AM UTC 24 | 3635963288 ps | ||
| T296 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/286.prim_prince_test.3789498480 | Sep 18 09:55:18 AM UTC 24 | Sep 18 09:56:31 AM UTC 24 | 3048117337 ps | ||
| T297 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/317.prim_prince_test.3517617126 | Sep 18 09:56:12 AM UTC 24 | Sep 18 09:56:31 AM UTC 24 | 778780427 ps | ||
| T298 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/309.prim_prince_test.658143001 | Sep 18 09:56:01 AM UTC 24 | Sep 18 09:56:31 AM UTC 24 | 1281587774 ps | ||
| T299 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/314.prim_prince_test.4192741410 | Sep 18 09:56:09 AM UTC 24 | Sep 18 09:56:33 AM UTC 24 | 964914096 ps | ||
| T300 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/279.prim_prince_test.791039931 | Sep 18 09:55:08 AM UTC 24 | Sep 18 09:56:34 AM UTC 24 | 3710328881 ps | ||
| T301 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/302.prim_prince_test.1867098639 | Sep 18 09:55:52 AM UTC 24 | Sep 18 09:56:34 AM UTC 24 | 1798256531 ps | ||
| T302 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/280.prim_prince_test.3471627627 | Sep 18 09:55:09 AM UTC 24 | Sep 18 09:56:35 AM UTC 24 | 3685619801 ps | ||
| T303 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/293.prim_prince_test.750436862 | Sep 18 09:55:35 AM UTC 24 | Sep 18 09:56:39 AM UTC 24 | 2675598071 ps | ||
| T304 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/300.prim_prince_test.422074281 | Sep 18 09:55:49 AM UTC 24 | Sep 18 09:56:41 AM UTC 24 | 2103536357 ps | ||
| T305 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/325.prim_prince_test.3332003808 | Sep 18 09:56:22 AM UTC 24 | Sep 18 09:56:42 AM UTC 24 | 780562190 ps | ||
| T306 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/298.prim_prince_test.4025730392 | Sep 18 09:55:47 AM UTC 24 | Sep 18 09:56:42 AM UTC 24 | 2282821850 ps | ||
| T307 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/313.prim_prince_test.2576135047 | Sep 18 09:56:09 AM UTC 24 | Sep 18 09:56:44 AM UTC 24 | 1400665672 ps | ||
| T308 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/290.prim_prince_test.4213492039 | Sep 18 09:55:29 AM UTC 24 | Sep 18 09:56:48 AM UTC 24 | 3389567528 ps | ||
| T309 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/308.prim_prince_test.1967529097 | Sep 18 09:56:00 AM UTC 24 | Sep 18 09:56:48 AM UTC 24 | 2012988049 ps | ||
| T310 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/306.prim_prince_test.1992376390 | Sep 18 09:55:54 AM UTC 24 | Sep 18 09:56:51 AM UTC 24 | 2412199835 ps | ||
| T311 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/294.prim_prince_test.509107272 | Sep 18 09:55:37 AM UTC 24 | Sep 18 09:56:52 AM UTC 24 | 3115743476 ps | ||
| T312 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/297.prim_prince_test.3853728319 | Sep 18 09:55:47 AM UTC 24 | Sep 18 09:56:52 AM UTC 24 | 2767998520 ps | ||
| T313 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/310.prim_prince_test.163573775 | Sep 18 09:56:02 AM UTC 24 | Sep 18 09:56:52 AM UTC 24 | 2075810825 ps | ||
| T314 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/326.prim_prince_test.2762607030 | Sep 18 09:56:23 AM UTC 24 | Sep 18 09:56:55 AM UTC 24 | 1318998705 ps | ||
| T315 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/312.prim_prince_test.3906905457 | Sep 18 09:56:03 AM UTC 24 | Sep 18 09:56:55 AM UTC 24 | 2202559908 ps | ||
| T316 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/332.prim_prince_test.3196540071 | Sep 18 09:56:34 AM UTC 24 | Sep 18 09:56:56 AM UTC 24 | 913366342 ps | ||
| T317 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/322.prim_prince_test.4125020427 | Sep 18 09:56:19 AM UTC 24 | Sep 18 09:57:01 AM UTC 24 | 1695744964 ps | ||
| T318 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/327.prim_prince_test.976698896 | Sep 18 09:56:25 AM UTC 24 | Sep 18 09:57:03 AM UTC 24 | 1544869733 ps | ||
| T319 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/346.prim_prince_test.2371887603 | Sep 18 09:56:53 AM UTC 24 | Sep 18 09:57:11 AM UTC 24 | 760375425 ps | ||
| T320 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/315.prim_prince_test.3160457899 | Sep 18 09:56:09 AM UTC 24 | Sep 18 09:57:12 AM UTC 24 | 2569249873 ps | ||
| T321 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/338.prim_prince_test.1687442171 | Sep 18 09:56:43 AM UTC 24 | Sep 18 09:57:17 AM UTC 24 | 1447173175 ps | ||
| T322 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/320.prim_prince_test.2955302742 | Sep 18 09:56:14 AM UTC 24 | Sep 18 09:57:17 AM UTC 24 | 2668626418 ps | ||
| T323 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/330.prim_prince_test.1546612410 | Sep 18 09:56:33 AM UTC 24 | Sep 18 09:57:18 AM UTC 24 | 1963602601 ps | ||
| T324 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/307.prim_prince_test.1789248248 | Sep 18 09:55:59 AM UTC 24 | Sep 18 09:57:20 AM UTC 24 | 3387733676 ps | ||
| T325 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/305.prim_prince_test.453902336 | Sep 18 09:55:53 AM UTC 24 | Sep 18 09:57:20 AM UTC 24 | 3661187294 ps | ||
| T326 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/311.prim_prince_test.1510321223 | Sep 18 09:56:02 AM UTC 24 | Sep 18 09:57:21 AM UTC 24 | 3321542099 ps | ||
| T327 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/318.prim_prince_test.722890556 | Sep 18 09:56:13 AM UTC 24 | Sep 18 09:57:22 AM UTC 24 | 2897071280 ps | ||
| T328 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/316.prim_prince_test.1485826007 | Sep 18 09:56:11 AM UTC 24 | Sep 18 09:57:23 AM UTC 24 | 3037552979 ps | ||
| T329 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/351.prim_prince_test.2724519462 | Sep 18 09:57:03 AM UTC 24 | Sep 18 09:57:24 AM UTC 24 | 798569134 ps | ||
| T330 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/331.prim_prince_test.4095937243 | Sep 18 09:56:33 AM UTC 24 | Sep 18 09:57:24 AM UTC 24 | 2193580891 ps | ||
| T331 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/336.prim_prince_test.893512278 | Sep 18 09:56:40 AM UTC 24 | Sep 18 09:57:24 AM UTC 24 | 1791346849 ps | ||
| T332 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/339.prim_prince_test.4260214087 | Sep 18 09:56:43 AM UTC 24 | Sep 18 09:57:25 AM UTC 24 | 1718719652 ps | ||
| T333 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/321.prim_prince_test.571809713 | Sep 18 09:56:17 AM UTC 24 | Sep 18 09:57:26 AM UTC 24 | 2874908988 ps | ||
| T334 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/319.prim_prince_test.4214699835 | Sep 18 09:56:13 AM UTC 24 | Sep 18 09:57:28 AM UTC 24 | 3122603048 ps | ||
| T335 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/340.prim_prince_test.2938350775 | Sep 18 09:56:45 AM UTC 24 | Sep 18 09:57:37 AM UTC 24 | 2117335381 ps | ||
| T336 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/342.prim_prince_test.572138423 | Sep 18 09:56:49 AM UTC 24 | Sep 18 09:57:38 AM UTC 24 | 2069122367 ps | ||
| T337 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/349.prim_prince_test.3105553513 | Sep 18 09:56:57 AM UTC 24 | Sep 18 09:57:41 AM UTC 24 | 1813950486 ps | ||
| T338 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/324.prim_prince_test.1240949571 | Sep 18 09:56:21 AM UTC 24 | Sep 18 09:57:41 AM UTC 24 | 3454089280 ps | ||
| T339 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/345.prim_prince_test.3255514217 | Sep 18 09:56:53 AM UTC 24 | Sep 18 09:57:44 AM UTC 24 | 2118925560 ps | ||
| T340 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/328.prim_prince_test.2807813775 | Sep 18 09:56:28 AM UTC 24 | Sep 18 09:57:44 AM UTC 24 | 3122532872 ps | ||
| T341 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/348.prim_prince_test.3403023648 | Sep 18 09:56:56 AM UTC 24 | Sep 18 09:57:45 AM UTC 24 | 2064433001 ps | ||
| T342 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/341.prim_prince_test.3341801290 | Sep 18 09:56:49 AM UTC 24 | Sep 18 09:57:45 AM UTC 24 | 2307970555 ps | ||
| T343 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/329.prim_prince_test.1139772402 | Sep 18 09:56:33 AM UTC 24 | Sep 18 09:57:46 AM UTC 24 | 3142191313 ps | ||
| T344 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/355.prim_prince_test.245440762 | Sep 18 09:57:19 AM UTC 24 | Sep 18 09:57:49 AM UTC 24 | 1194428434 ps | ||
| T345 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/344.prim_prince_test.1620032976 | Sep 18 09:56:52 AM UTC 24 | Sep 18 09:57:50 AM UTC 24 | 2436496745 ps | ||
| T346 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/323.prim_prince_test.4053040890 | Sep 18 09:56:21 AM UTC 24 | Sep 18 09:57:50 AM UTC 24 | 3733629638 ps | ||
| T347 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/333.prim_prince_test.637163083 | Sep 18 09:56:35 AM UTC 24 | Sep 18 09:57:51 AM UTC 24 | 3179995010 ps | ||
| T348 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/364.prim_prince_test.217196770 | Sep 18 09:57:25 AM UTC 24 | Sep 18 09:57:51 AM UTC 24 | 1050795861 ps | ||
| T349 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/360.prim_prince_test.2840182736 | Sep 18 09:57:24 AM UTC 24 | Sep 18 09:57:52 AM UTC 24 | 1144051913 ps | ||
| T350 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/335.prim_prince_test.2573925172 | Sep 18 09:56:36 AM UTC 24 | Sep 18 09:57:53 AM UTC 24 | 3186711262 ps | ||
| T351 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/337.prim_prince_test.4174271133 | Sep 18 09:56:42 AM UTC 24 | Sep 18 09:57:55 AM UTC 24 | 2987120994 ps | ||
| T352 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/358.prim_prince_test.4228504645 | Sep 18 09:57:21 AM UTC 24 | Sep 18 09:57:56 AM UTC 24 | 1462960911 ps | ||
| T353 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/366.prim_prince_test.612285242 | Sep 18 09:57:27 AM UTC 24 | Sep 18 09:57:59 AM UTC 24 | 1308467827 ps | ||
| T354 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/343.prim_prince_test.2308951558 | Sep 18 09:56:52 AM UTC 24 | Sep 18 09:58:00 AM UTC 24 | 2860233082 ps | ||
| T355 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/334.prim_prince_test.2635198933 | Sep 18 09:56:35 AM UTC 24 | Sep 18 09:58:00 AM UTC 24 | 3664979052 ps | ||
| T356 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/367.prim_prince_test.1092516717 | Sep 18 09:57:29 AM UTC 24 | Sep 18 09:58:02 AM UTC 24 | 1376336156 ps | ||
| T357 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/361.prim_prince_test.3041494116 | Sep 18 09:57:24 AM UTC 24 | Sep 18 09:58:04 AM UTC 24 | 1727922631 ps | ||
| T358 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/354.prim_prince_test.3979533092 | Sep 18 09:57:18 AM UTC 24 | Sep 18 09:58:06 AM UTC 24 | 1955463062 ps | ||
| T359 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/353.prim_prince_test.1019369517 | Sep 18 09:57:14 AM UTC 24 | Sep 18 09:58:09 AM UTC 24 | 2346063701 ps | ||
| T360 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/352.prim_prince_test.4153657577 | Sep 18 09:57:12 AM UTC 24 | Sep 18 09:58:10 AM UTC 24 | 2400124012 ps | ||
| T361 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/375.prim_prince_test.1774022985 | Sep 18 09:57:47 AM UTC 24 | Sep 18 09:58:12 AM UTC 24 | 1025535679 ps | ||
| T362 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/362.prim_prince_test.779804778 | Sep 18 09:57:25 AM UTC 24 | Sep 18 09:58:14 AM UTC 24 | 2060288697 ps | ||
| T363 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/350.prim_prince_test.767003876 | Sep 18 09:57:02 AM UTC 24 | Sep 18 09:58:15 AM UTC 24 | 2971491210 ps | ||
| T364 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/376.prim_prince_test.985161841 | Sep 18 09:57:47 AM UTC 24 | Sep 18 09:58:15 AM UTC 24 | 1198686767 ps | ||
| T365 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/357.prim_prince_test.2913207385 | Sep 18 09:57:21 AM UTC 24 | Sep 18 09:58:16 AM UTC 24 | 2307887225 ps | ||
| T366 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/347.prim_prince_test.2969128524 | Sep 18 09:56:56 AM UTC 24 | Sep 18 09:58:17 AM UTC 24 | 3399978825 ps | ||
| T367 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/379.prim_prince_test.2519241592 | Sep 18 09:57:52 AM UTC 24 | Sep 18 09:58:20 AM UTC 24 | 1124280198 ps | ||
| T368 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/359.prim_prince_test.7625987 | Sep 18 09:57:22 AM UTC 24 | Sep 18 09:58:21 AM UTC 24 | 2399993010 ps | ||
| T369 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/377.prim_prince_test.1835700781 | Sep 18 09:57:47 AM UTC 24 | Sep 18 09:58:22 AM UTC 24 | 1460924752 ps | ||
| T370 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/382.prim_prince_test.857730411 | Sep 18 09:57:53 AM UTC 24 | Sep 18 09:58:24 AM UTC 24 | 1225167099 ps | ||
| T371 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/365.prim_prince_test.1051948644 | Sep 18 09:57:26 AM UTC 24 | Sep 18 09:58:29 AM UTC 24 | 2648412015 ps | ||
| T372 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/380.prim_prince_test.1013228549 | Sep 18 09:57:52 AM UTC 24 | Sep 18 09:58:31 AM UTC 24 | 1582423466 ps | ||
| T373 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/381.prim_prince_test.1344051122 | Sep 18 09:57:52 AM UTC 24 | Sep 18 09:58:33 AM UTC 24 | 1707090576 ps | ||
| T374 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/371.prim_prince_test.224518284 | Sep 18 09:57:41 AM UTC 24 | Sep 18 09:58:36 AM UTC 24 | 2240729579 ps | ||
| T375 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/392.prim_prince_test.29046999 | Sep 18 09:58:07 AM UTC 24 | Sep 18 09:58:37 AM UTC 24 | 1227617037 ps | ||
| T376 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/356.prim_prince_test.2743834955 | Sep 18 09:57:19 AM UTC 24 | Sep 18 09:58:38 AM UTC 24 | 3272605620 ps | ||
| T377 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/394.prim_prince_test.3384434092 | Sep 18 09:58:10 AM UTC 24 | Sep 18 09:58:38 AM UTC 24 | 1108706107 ps | ||
| T378 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/395.prim_prince_test.254625879 | Sep 18 09:58:13 AM UTC 24 | Sep 18 09:58:41 AM UTC 24 | 1127656670 ps | ||
| T379 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/373.prim_prince_test.1668365161 | Sep 18 09:57:45 AM UTC 24 | Sep 18 09:58:42 AM UTC 24 | 2373488953 ps | ||
| T380 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/400.prim_prince_test.1913608877 | Sep 18 09:58:17 AM UTC 24 | Sep 18 09:58:44 AM UTC 24 | 1097904980 ps | ||
| T381 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/363.prim_prince_test.1638280110 | Sep 18 09:57:25 AM UTC 24 | Sep 18 09:58:46 AM UTC 24 | 3389365528 ps | ||
| T382 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/370.prim_prince_test.1527818906 | Sep 18 09:57:39 AM UTC 24 | Sep 18 09:58:53 AM UTC 24 | 3133390998 ps | ||
| T383 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/369.prim_prince_test.1499479730 | Sep 18 09:57:38 AM UTC 24 | Sep 18 09:58:54 AM UTC 24 | 3139252206 ps | ||
| T384 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/397.prim_prince_test.1254568122 | Sep 18 09:58:16 AM UTC 24 | Sep 18 09:58:57 AM UTC 24 | 1641862727 ps | ||
| T385 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/409.prim_prince_test.1380653643 | Sep 18 09:58:38 AM UTC 24 | Sep 18 09:58:57 AM UTC 24 | 759888109 ps | ||
| T386 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/368.prim_prince_test.4210820950 | Sep 18 09:57:33 AM UTC 24 | Sep 18 09:58:57 AM UTC 24 | 3581539915 ps | ||
| T387 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/388.prim_prince_test.3757951976 | Sep 18 09:58:01 AM UTC 24 | Sep 18 09:58:58 AM UTC 24 | 2438979387 ps | ||
| T388 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/385.prim_prince_test.1421444984 | Sep 18 09:57:55 AM UTC 24 | Sep 18 09:59:00 AM UTC 24 | 2696168351 ps | ||
| T389 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/408.prim_prince_test.3865375641 | Sep 18 09:58:38 AM UTC 24 | Sep 18 09:59:00 AM UTC 24 | 897369507 ps | ||
| T390 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/396.prim_prince_test.1455885397 | Sep 18 09:58:15 AM UTC 24 | Sep 18 09:59:02 AM UTC 24 | 2018502492 ps | ||
| T391 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/401.prim_prince_test.2721425188 | Sep 18 09:58:21 AM UTC 24 | Sep 18 09:59:03 AM UTC 24 | 1708070843 ps | ||
| T392 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/390.prim_prince_test.1811036472 | Sep 18 09:58:03 AM UTC 24 | Sep 18 09:59:03 AM UTC 24 | 2454252680 ps | ||
| T393 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/384.prim_prince_test.2818739423 | Sep 18 09:57:54 AM UTC 24 | Sep 18 09:59:03 AM UTC 24 | 2944760844 ps | ||
| T394 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/372.prim_prince_test.681156366 | Sep 18 09:57:42 AM UTC 24 | Sep 18 09:59:05 AM UTC 24 | 3408543573 ps | ||
| T395 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/386.prim_prince_test.701058228 | Sep 18 09:57:57 AM UTC 24 | Sep 18 09:59:05 AM UTC 24 | 2882328142 ps | ||
| T396 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/407.prim_prince_test.1131230174 | Sep 18 09:58:34 AM UTC 24 | Sep 18 09:59:05 AM UTC 24 | 1236707619 ps | ||
| T397 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/391.prim_prince_test.242513851 | Sep 18 09:58:05 AM UTC 24 | Sep 18 09:59:06 AM UTC 24 | 2592382380 ps | ||
| T398 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/389.prim_prince_test.4288050049 | Sep 18 09:58:02 AM UTC 24 | Sep 18 09:59:07 AM UTC 24 | 2702455705 ps | ||
| T399 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/398.prim_prince_test.2151955187 | Sep 18 09:58:16 AM UTC 24 | Sep 18 09:59:08 AM UTC 24 | 2193378814 ps | ||
| T400 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/404.prim_prince_test.431865216 | Sep 18 09:58:25 AM UTC 24 | Sep 18 09:59:08 AM UTC 24 | 1760347840 ps | ||
| T401 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/374.prim_prince_test.2140967615 | Sep 18 09:57:45 AM UTC 24 | Sep 18 09:59:08 AM UTC 24 | 3468491552 ps | ||
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| T405 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/383.prim_prince_test.3210694080 | Sep 18 09:57:53 AM UTC 24 | Sep 18 09:59:20 AM UTC 24 | 3596967471 ps | ||
| T406 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/406.prim_prince_test.3688650311 | Sep 18 09:58:31 AM UTC 24 | Sep 18 09:59:20 AM UTC 24 | 2012868360 ps | ||
| T407 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/403.prim_prince_test.667927409 | Sep 18 09:58:23 AM UTC 24 | Sep 18 09:59:21 AM UTC 24 | 2395318713 ps | ||
| T408 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/418.prim_prince_test.1776145820 | Sep 18 09:58:59 AM UTC 24 | Sep 18 09:59:28 AM UTC 24 | 1195281110 ps | ||
| T409 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/414.prim_prince_test.2876104839 | Sep 18 09:58:45 AM UTC 24 | Sep 18 09:59:30 AM UTC 24 | 1893349178 ps | ||
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| T412 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/393.prim_prince_test.1347958784 | Sep 18 09:58:09 AM UTC 24 | Sep 18 09:59:36 AM UTC 24 | 3719932873 ps | ||
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| T415 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/411.prim_prince_test.2852819240 | Sep 18 09:58:39 AM UTC 24 | Sep 18 09:59:38 AM UTC 24 | 2530958399 ps | ||
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| T438 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/423.prim_prince_test.3346683186 | Sep 18 09:59:01 AM UTC 24 | Sep 18 10:00:11 AM UTC 24 | 2919703893 ps | ||
| T439 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/445.prim_prince_test.4026597875 | Sep 18 09:59:34 AM UTC 24 | Sep 18 10:00:13 AM UTC 24 | 1617377128 ps | ||
| T440 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/421.prim_prince_test.3934592706 | Sep 18 09:58:59 AM UTC 24 | Sep 18 10:00:15 AM UTC 24 | 3157835587 ps | ||
| T441 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/438.prim_prince_test.1885226735 | Sep 18 09:59:18 AM UTC 24 | Sep 18 10:00:15 AM UTC 24 | 2434697602 ps | ||
| T442 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/432.prim_prince_test.3950806601 | Sep 18 09:59:07 AM UTC 24 | Sep 18 10:00:16 AM UTC 24 | 2955395721 ps | ||
| T443 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/440.prim_prince_test.1720361963 | Sep 18 09:59:21 AM UTC 24 | Sep 18 10:00:21 AM UTC 24 | 2475508029 ps | ||
| T444 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/430.prim_prince_test.2903651693 | Sep 18 09:59:06 AM UTC 24 | Sep 18 10:00:22 AM UTC 24 | 3221205444 ps | ||
| T445 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/426.prim_prince_test.3067920679 | Sep 18 09:59:05 AM UTC 24 | Sep 18 10:00:22 AM UTC 24 | 3182630982 ps | ||
| T446 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/449.prim_prince_test.100895948 | Sep 18 09:59:39 AM UTC 24 | Sep 18 10:00:25 AM UTC 24 | 1844484060 ps | ||
| T447 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/443.prim_prince_test.975650414 | Sep 18 09:59:31 AM UTC 24 | Sep 18 10:00:25 AM UTC 24 | 2228250489 ps | ||
| T448 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/460.prim_prince_test.721732 | Sep 18 09:59:57 AM UTC 24 | Sep 18 10:00:26 AM UTC 24 | 1164299298 ps | ||
| T449 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/459.prim_prince_test.3274363527 | Sep 18 09:59:57 AM UTC 24 | Sep 18 10:00:30 AM UTC 24 | 1311628387 ps | ||
| T450 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/447.prim_prince_test.2649518436 | Sep 18 09:59:38 AM UTC 24 | Sep 18 10:00:31 AM UTC 24 | 2234537162 ps | ||
| T451 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/462.prim_prince_test.378026203 | Sep 18 10:00:01 AM UTC 24 | Sep 18 10:00:32 AM UTC 24 | 1079696779 ps | ||
| T452 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/452.prim_prince_test.777334905 | Sep 18 09:59:43 AM UTC 24 | Sep 18 10:00:35 AM UTC 24 | 2190189154 ps | ||
| T453 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/450.prim_prince_test.1875370516 | Sep 18 09:59:41 AM UTC 24 | Sep 18 10:00:36 AM UTC 24 | 2285393708 ps | ||
| T454 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/470.prim_prince_test.2208766317 | Sep 18 10:00:10 AM UTC 24 | Sep 18 10:00:39 AM UTC 24 | 1142334187 ps | ||
| T455 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/476.prim_prince_test.3831608251 | Sep 18 10:00:17 AM UTC 24 | Sep 18 10:00:42 AM UTC 24 | 995227053 ps | ||
| T456 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/444.prim_prince_test.556999516 | Sep 18 09:59:34 AM UTC 24 | Sep 18 10:00:44 AM UTC 24 | 2975424450 ps | ||
| T457 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/454.prim_prince_test.2768355367 | Sep 18 09:59:46 AM UTC 24 | Sep 18 10:00:44 AM UTC 24 | 2365077132 ps | ||
| T458 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/451.prim_prince_test.4018426172 | Sep 18 09:59:41 AM UTC 24 | Sep 18 10:00:44 AM UTC 24 | 2703342262 ps | ||
| T459 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/473.prim_prince_test.3646981105 | Sep 18 10:00:13 AM UTC 24 | Sep 18 10:00:45 AM UTC 24 | 1251385675 ps | ||
| T460 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/466.prim_prince_test.565145825 | Sep 18 10:00:08 AM UTC 24 | Sep 18 10:00:45 AM UTC 24 | 1481403304 ps | ||
| T461 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/472.prim_prince_test.587335117 | Sep 18 10:00:12 AM UTC 24 | Sep 18 10:00:45 AM UTC 24 | 1334310449 ps | ||
| T462 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/477.prim_prince_test.2294696096 | Sep 18 10:00:17 AM UTC 24 | Sep 18 10:00:47 AM UTC 24 | 1223339836 ps | ||
| T463 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/441.prim_prince_test.4052907117 | Sep 18 09:59:22 AM UTC 24 | Sep 18 10:00:51 AM UTC 24 | 3753987466 ps | ||
| T464 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/479.prim_prince_test.2979326584 | Sep 18 10:00:21 AM UTC 24 | Sep 18 10:00:53 AM UTC 24 | 1263195201 ps | ||
| T465 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/448.prim_prince_test.2793799013 | Sep 18 09:59:39 AM UTC 24 | Sep 18 10:00:54 AM UTC 24 | 3186805587 ps | ||
| T466 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/458.prim_prince_test.2950265063 | Sep 18 09:59:56 AM UTC 24 | Sep 18 10:00:55 AM UTC 24 | 2407683158 ps | ||
| T467 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/474.prim_prince_test.2174835612 | Sep 18 10:00:14 AM UTC 24 | Sep 18 10:00:55 AM UTC 24 | 1695820893 ps | ||
| T468 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/463.prim_prince_test.2224154823 | Sep 18 10:00:02 AM UTC 24 | Sep 18 10:00:56 AM UTC 24 | 2068417340 ps | ||
| T469 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/455.prim_prince_test.1369919740 | Sep 18 09:59:50 AM UTC 24 | Sep 18 10:00:59 AM UTC 24 | 2923797581 ps | ||
| T470 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/457.prim_prince_test.2234725206 | Sep 18 09:59:55 AM UTC 24 | Sep 18 10:00:59 AM UTC 24 | 2608206790 ps | ||
| T471 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/486.prim_prince_test.1247424632 | Sep 18 10:00:31 AM UTC 24 | Sep 18 10:01:00 AM UTC 24 | 1169593002 ps | ||
| T472 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/456.prim_prince_test.1427677704 | Sep 18 09:59:50 AM UTC 24 | Sep 18 10:01:05 AM UTC 24 | 3181041781 ps | ||
| T473 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/491.prim_prince_test.2715244115 | Sep 18 10:00:39 AM UTC 24 | Sep 18 10:01:05 AM UTC 24 | 1048107286 ps | ||
| T474 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/467.prim_prince_test.1728235496 | Sep 18 10:00:08 AM UTC 24 | Sep 18 10:01:06 AM UTC 24 | 2347629475 ps | ||
| T475 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/464.prim_prince_test.335507341 | Sep 18 10:00:08 AM UTC 24 | Sep 18 10:01:07 AM UTC 24 | 2427346458 ps | ||
| T476 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/483.prim_prince_test.3249899608 | Sep 18 10:00:26 AM UTC 24 | Sep 18 10:01:08 AM UTC 24 | 1753021425 ps | ||
| T477 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/480.prim_prince_test.573312997 | Sep 18 10:00:23 AM UTC 24 | Sep 18 10:01:09 AM UTC 24 | 1874068491 ps | ||
| T478 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/488.prim_prince_test.4174291993 | Sep 18 10:00:36 AM UTC 24 | Sep 18 10:01:10 AM UTC 24 | 1362127880 ps | ||
| T479 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/499.prim_prince_test.3037055055 | Sep 18 10:00:49 AM UTC 24 | Sep 18 10:01:11 AM UTC 24 | 868961261 ps | ||
| T480 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/465.prim_prince_test.643247524 | Sep 18 10:00:08 AM UTC 24 | Sep 18 10:01:11 AM UTC 24 | 2652360152 ps | ||
| T481 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/461.prim_prince_test.3454604491 | Sep 18 09:59:57 AM UTC 24 | Sep 18 10:01:11 AM UTC 24 | 2999318387 ps | ||
| T482 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/471.prim_prince_test.3805406403 | Sep 18 10:00:11 AM UTC 24 | Sep 18 10:01:15 AM UTC 24 | 2675113834 ps | ||
| T483 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/493.prim_prince_test.1335421297 | Sep 18 10:00:45 AM UTC 24 | Sep 18 10:01:19 AM UTC 24 | 1349311296 ps | ||
| T484 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/469.prim_prince_test.2021314743 | Sep 18 10:00:08 AM UTC 24 | Sep 18 10:01:19 AM UTC 24 | 2920928957 ps | ||
| T485 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/475.prim_prince_test.1784262176 | Sep 18 10:00:16 AM UTC 24 | Sep 18 10:01:28 AM UTC 24 | 2907559473 ps | ||
| T486 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/482.prim_prince_test.1367231447 | Sep 18 10:00:26 AM UTC 24 | Sep 18 10:01:28 AM UTC 24 | 2490396538 ps | ||
| T487 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/468.prim_prince_test.3896414739 | Sep 18 10:00:08 AM UTC 24 | Sep 18 10:01:30 AM UTC 24 | 3323873473 ps | ||
| T488 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/498.prim_prince_test.515027626 | Sep 18 10:00:47 AM UTC 24 | Sep 18 10:01:33 AM UTC 24 | 1961666890 ps | ||
| T489 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/495.prim_prince_test.3134031123 | Sep 18 10:00:45 AM UTC 24 | Sep 18 10:01:35 AM UTC 24 | 2051835464 ps | ||
| T490 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/487.prim_prince_test.1139124058 | Sep 18 10:00:34 AM UTC 24 | Sep 18 10:01:35 AM UTC 24 | 2535751443 ps | ||
| T491 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/484.prim_prince_test.2980108493 | Sep 18 10:00:26 AM UTC 24 | Sep 18 10:01:36 AM UTC 24 | 2968932549 ps | ||
| T492 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/485.prim_prince_test.1445935961 | Sep 18 10:00:30 AM UTC 24 | Sep 18 10:01:41 AM UTC 24 | 2942278351 ps | ||
| T493 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/497.prim_prince_test.4069024444 | Sep 18 10:00:47 AM UTC 24 | Sep 18 10:01:43 AM UTC 24 | 2130835108 ps | ||
| T494 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/478.prim_prince_test.1609619467 | Sep 18 10:00:21 AM UTC 24 | Sep 18 10:01:45 AM UTC 24 | 3466676524 ps | ||
| T495 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/494.prim_prince_test.3207041403 | Sep 18 10:00:45 AM UTC 24 | Sep 18 10:01:48 AM UTC 24 | 2564342302 ps | ||
| T496 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/481.prim_prince_test.1194622895 | Sep 18 10:00:24 AM UTC 24 | Sep 18 10:01:59 AM UTC 24 | 3694383697 ps | ||
| T497 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/490.prim_prince_test.298889880 | Sep 18 10:00:37 AM UTC 24 | Sep 18 10:02:00 AM UTC 24 | 3324193287 ps | ||
| T498 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/489.prim_prince_test.2153474360 | Sep 18 10:00:36 AM UTC 24 | Sep 18 10:02:05 AM UTC 24 | 3484068310 ps | ||
| T499 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/492.prim_prince_test.237953757 | Sep 18 10:00:42 AM UTC 24 | Sep 18 10:02:13 AM UTC 24 | 3601702891 ps | ||
| T500 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/496.prim_prince_test.285180337 | Sep 18 10:00:46 AM UTC 24 | Sep 18 10:02:25 AM UTC 24 | 3645591138 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/0.prim_prince_test.491044415 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 2416915901 ps |
| CPU time | 47.68 seconds |
| Started | Sep 18 09:46:28 AM UTC 24 |
| Finished | Sep 18 09:47:30 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=491044415 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 0.prim_prince_test.491044415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/0.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/1.prim_prince_test.4280492799 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 901991859 ps |
| CPU time | 19.04 seconds |
| Started | Sep 18 09:46:29 AM UTC 24 |
| Finished | Sep 18 09:46:54 AM UTC 24 |
| Peak memory | 154648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4280492799 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 1.prim_prince_test.4280492799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/1.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/10.prim_prince_test.1266308154 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 1652266732 ps |
| CPU time | 33.26 seconds |
| Started | Sep 18 09:46:31 AM UTC 24 |
| Finished | Sep 18 09:47:15 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1266308154 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 10.prim_prince_test.1266308154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/10.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/100.prim_prince_test.490432367 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 1625388424 ps |
| CPU time | 30.76 seconds |
| Started | Sep 18 09:50:06 AM UTC 24 |
| Finished | Sep 18 09:50:46 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=490432367 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 100.prim_prince_test.490432367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/100.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/101.prim_prince_test.284333211 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 3701984702 ps |
| CPU time | 68.01 seconds |
| Started | Sep 18 09:50:12 AM UTC 24 |
| Finished | Sep 18 09:51:40 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=284333211 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 101.prim_prince_test.284333211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/101.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/102.prim_prince_test.2601281775 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 2471684919 ps |
| CPU time | 48.1 seconds |
| Started | Sep 18 09:50:12 AM UTC 24 |
| Finished | Sep 18 09:51:13 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2601281775 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 102.prim_prince_test.2601281775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/102.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/103.prim_prince_test.3854235087 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 1120560723 ps |
| CPU time | 21.91 seconds |
| Started | Sep 18 09:50:12 AM UTC 24 |
| Finished | Sep 18 09:50:41 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3854235087 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 103.prim_prince_test.3854235087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/103.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/104.prim_prince_test.3319735094 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 2782061735 ps |
| CPU time | 52.17 seconds |
| Started | Sep 18 09:50:16 AM UTC 24 |
| Finished | Sep 18 09:51:23 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3319735094 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 104.prim_prince_test.3319735094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/104.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/105.prim_prince_test.2958974961 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 2119054692 ps |
| CPU time | 39.74 seconds |
| Started | Sep 18 09:50:16 AM UTC 24 |
| Finished | Sep 18 09:51:07 AM UTC 24 |
| Peak memory | 154588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2958974961 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 105.prim_prince_test.2958974961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/105.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/106.prim_prince_test.2085891799 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 2014167847 ps |
| CPU time | 38.32 seconds |
| Started | Sep 18 09:50:18 AM UTC 24 |
| Finished | Sep 18 09:51:07 AM UTC 24 |
| Peak memory | 154588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2085891799 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 106.prim_prince_test.2085891799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/106.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/107.prim_prince_test.4029212410 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 3443544471 ps |
| CPU time | 63.48 seconds |
| Started | Sep 18 09:50:19 AM UTC 24 |
| Finished | Sep 18 09:51:40 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4029212410 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 107.prim_prince_test.4029212410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/107.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/108.prim_prince_test.791429079 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 3672342962 ps |
| CPU time | 69.05 seconds |
| Started | Sep 18 09:50:20 AM UTC 24 |
| Finished | Sep 18 09:51:48 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=791429079 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 108.prim_prince_test.791429079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/108.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/109.prim_prince_test.2443117501 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 796632523 ps |
| CPU time | 15.68 seconds |
| Started | Sep 18 09:50:23 AM UTC 24 |
| Finished | Sep 18 09:50:44 AM UTC 24 |
| Peak memory | 154588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2443117501 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 109.prim_prince_test.2443117501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/109.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/11.prim_prince_test.4227123807 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 3401743230 ps |
| CPU time | 67.68 seconds |
| Started | Sep 18 09:46:31 AM UTC 24 |
| Finished | Sep 18 09:47:59 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4227123807 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 11.prim_prince_test.4227123807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/11.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/110.prim_prince_test.1740838757 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 881353149 ps |
| CPU time | 17.33 seconds |
| Started | Sep 18 09:50:23 AM UTC 24 |
| Finished | Sep 18 09:50:46 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1740838757 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 110.prim_prince_test.1740838757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/110.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/111.prim_prince_test.890971989 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 2399002393 ps |
| CPU time | 44.34 seconds |
| Started | Sep 18 09:50:25 AM UTC 24 |
| Finished | Sep 18 09:51:22 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=890971989 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 111.prim_prince_test.890971989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/111.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/112.prim_prince_test.629074050 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 1430100208 ps |
| CPU time | 27.4 seconds |
| Started | Sep 18 09:50:26 AM UTC 24 |
| Finished | Sep 18 09:51:01 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=629074050 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 112.prim_prince_test.629074050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/112.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/113.prim_prince_test.2925741355 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 3293588708 ps |
| CPU time | 64.08 seconds |
| Started | Sep 18 09:50:27 AM UTC 24 |
| Finished | Sep 18 09:51:48 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2925741355 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 113.prim_prince_test.2925741355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/113.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/114.prim_prince_test.2900097492 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 2579909160 ps |
| CPU time | 49.78 seconds |
| Started | Sep 18 09:50:28 AM UTC 24 |
| Finished | Sep 18 09:51:32 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2900097492 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 114.prim_prince_test.2900097492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/114.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/115.prim_prince_test.977346050 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 1428896159 ps |
| CPU time | 28.47 seconds |
| Started | Sep 18 09:50:34 AM UTC 24 |
| Finished | Sep 18 09:51:11 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=977346050 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 115.prim_prince_test.977346050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/115.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/116.prim_prince_test.3646238274 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 1475145964 ps |
| CPU time | 28.52 seconds |
| Started | Sep 18 09:50:36 AM UTC 24 |
| Finished | Sep 18 09:51:13 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3646238274 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 116.prim_prince_test.3646238274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/116.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/117.prim_prince_test.83523619 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 762783602 ps |
| CPU time | 14.96 seconds |
| Started | Sep 18 09:50:36 AM UTC 24 |
| Finished | Sep 18 09:50:56 AM UTC 24 |
| Peak memory | 154588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=83523619 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 117.prim_prince_test.83523619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/117.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/118.prim_prince_test.2957570262 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 2913500912 ps |
| CPU time | 56.75 seconds |
| Started | Sep 18 09:50:42 AM UTC 24 |
| Finished | Sep 18 09:51:53 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2957570262 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 118.prim_prince_test.2957570262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/118.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/119.prim_prince_test.1469579918 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 3474898200 ps |
| CPU time | 65.57 seconds |
| Started | Sep 18 09:50:43 AM UTC 24 |
| Finished | Sep 18 09:52:06 AM UTC 24 |
| Peak memory | 154652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1469579918 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 119.prim_prince_test.1469579918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/119.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/12.prim_prince_test.4127566340 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 2436098962 ps |
| CPU time | 48.07 seconds |
| Started | Sep 18 09:46:31 AM UTC 24 |
| Finished | Sep 18 09:47:34 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4127566340 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 12.prim_prince_test.4127566340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/12.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/120.prim_prince_test.1515565396 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 2603895496 ps |
| CPU time | 47.85 seconds |
| Started | Sep 18 09:50:43 AM UTC 24 |
| Finished | Sep 18 09:51:44 AM UTC 24 |
| Peak memory | 154652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1515565396 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 120.prim_prince_test.1515565396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/120.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/121.prim_prince_test.3786873428 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 986090180 ps |
| CPU time | 19.81 seconds |
| Started | Sep 18 09:50:44 AM UTC 24 |
| Finished | Sep 18 09:51:09 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3786873428 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 121.prim_prince_test.3786873428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/121.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/122.prim_prince_test.208176942 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 1870860252 ps |
| CPU time | 35.64 seconds |
| Started | Sep 18 09:50:45 AM UTC 24 |
| Finished | Sep 18 09:51:30 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=208176942 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 122.prim_prince_test.208176942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/122.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/123.prim_prince_test.3014031172 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 2975646891 ps |
| CPU time | 56.48 seconds |
| Started | Sep 18 09:50:45 AM UTC 24 |
| Finished | Sep 18 09:51:57 AM UTC 24 |
| Peak memory | 154652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3014031172 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 123.prim_prince_test.3014031172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/123.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/124.prim_prince_test.192122730 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 1263888077 ps |
| CPU time | 25.44 seconds |
| Started | Sep 18 09:50:47 AM UTC 24 |
| Finished | Sep 18 09:51:20 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=192122730 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 124.prim_prince_test.192122730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/124.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/125.prim_prince_test.1161064512 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 2567446325 ps |
| CPU time | 47.36 seconds |
| Started | Sep 18 09:50:47 AM UTC 24 |
| Finished | Sep 18 09:51:48 AM UTC 24 |
| Peak memory | 154652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1161064512 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 125.prim_prince_test.1161064512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/125.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/126.prim_prince_test.3577081710 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 2174019874 ps |
| CPU time | 41.16 seconds |
| Started | Sep 18 09:50:56 AM UTC 24 |
| Finished | Sep 18 09:51:49 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3577081710 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 126.prim_prince_test.3577081710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/126.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/127.prim_prince_test.3686093788 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 2261323175 ps |
| CPU time | 44.28 seconds |
| Started | Sep 18 09:50:56 AM UTC 24 |
| Finished | Sep 18 09:51:52 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3686093788 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 127.prim_prince_test.3686093788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/127.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/128.prim_prince_test.2433082526 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 1462677531 ps |
| CPU time | 28.59 seconds |
| Started | Sep 18 09:50:57 AM UTC 24 |
| Finished | Sep 18 09:51:34 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2433082526 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 128.prim_prince_test.2433082526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/128.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/129.prim_prince_test.1840204940 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 990610764 ps |
| CPU time | 19.39 seconds |
| Started | Sep 18 09:51:02 AM UTC 24 |
| Finished | Sep 18 09:51:27 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1840204940 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 129.prim_prince_test.1840204940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/129.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/13.prim_prince_test.1020028537 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 2219301658 ps |
| CPU time | 45.33 seconds |
| Started | Sep 18 09:46:31 AM UTC 24 |
| Finished | Sep 18 09:47:31 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1020028537 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 13.prim_prince_test.1020028537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/13.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/130.prim_prince_test.313321158 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 1885395330 ps |
| CPU time | 35 seconds |
| Started | Sep 18 09:51:04 AM UTC 24 |
| Finished | Sep 18 09:51:50 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=313321158 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 130.prim_prince_test.313321158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/130.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/131.prim_prince_test.2250399237 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 3237317549 ps |
| CPU time | 62.59 seconds |
| Started | Sep 18 09:51:07 AM UTC 24 |
| Finished | Sep 18 09:52:27 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2250399237 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 131.prim_prince_test.2250399237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/131.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/132.prim_prince_test.161330427 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 2828865263 ps |
| CPU time | 54.61 seconds |
| Started | Sep 18 09:51:08 AM UTC 24 |
| Finished | Sep 18 09:52:17 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=161330427 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 132.prim_prince_test.161330427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/132.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/133.prim_prince_test.1578338512 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 2557678690 ps |
| CPU time | 47.26 seconds |
| Started | Sep 18 09:51:10 AM UTC 24 |
| Finished | Sep 18 09:52:10 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1578338512 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 133.prim_prince_test.1578338512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/133.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/134.prim_prince_test.258129724 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 3238736774 ps |
| CPU time | 63.37 seconds |
| Started | Sep 18 09:51:11 AM UTC 24 |
| Finished | Sep 18 09:52:31 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=258129724 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 134.prim_prince_test.258129724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/134.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/135.prim_prince_test.2026900875 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 2682297818 ps |
| CPU time | 52 seconds |
| Started | Sep 18 09:51:11 AM UTC 24 |
| Finished | Sep 18 09:52:17 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2026900875 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 135.prim_prince_test.2026900875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/135.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/136.prim_prince_test.2493397482 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 968149818 ps |
| CPU time | 19 seconds |
| Started | Sep 18 09:51:12 AM UTC 24 |
| Finished | Sep 18 09:51:37 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2493397482 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 136.prim_prince_test.2493397482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/136.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/137.prim_prince_test.2773033722 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 3105408902 ps |
| CPU time | 59.71 seconds |
| Started | Sep 18 09:51:14 AM UTC 24 |
| Finished | Sep 18 09:52:29 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2773033722 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 137.prim_prince_test.2773033722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/137.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/138.prim_prince_test.746577762 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 3498506289 ps |
| CPU time | 67.74 seconds |
| Started | Sep 18 09:51:14 AM UTC 24 |
| Finished | Sep 18 09:52:39 AM UTC 24 |
| Peak memory | 154652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=746577762 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 138.prim_prince_test.746577762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/138.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/139.prim_prince_test.612560049 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 1124004737 ps |
| CPU time | 21.26 seconds |
| Started | Sep 18 09:51:18 AM UTC 24 |
| Finished | Sep 18 09:51:46 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=612560049 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 139.prim_prince_test.612560049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/139.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/14.prim_prince_test.2701486310 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 1111594151 ps |
| CPU time | 22.42 seconds |
| Started | Sep 18 09:46:32 AM UTC 24 |
| Finished | Sep 18 09:47:02 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2701486310 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 14.prim_prince_test.2701486310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/14.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/140.prim_prince_test.4290141383 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 1567210625 ps |
| CPU time | 28.78 seconds |
| Started | Sep 18 09:51:20 AM UTC 24 |
| Finished | Sep 18 09:51:58 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4290141383 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 140.prim_prince_test.4290141383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/140.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/141.prim_prince_test.3611210591 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 1863312649 ps |
| CPU time | 36.54 seconds |
| Started | Sep 18 09:51:21 AM UTC 24 |
| Finished | Sep 18 09:52:08 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3611210591 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 141.prim_prince_test.3611210591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/141.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/142.prim_prince_test.2017454509 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 3647051698 ps |
| CPU time | 68.44 seconds |
| Started | Sep 18 09:51:23 AM UTC 24 |
| Finished | Sep 18 09:52:51 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2017454509 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 142.prim_prince_test.2017454509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/142.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/143.prim_prince_test.4234041459 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 2871984786 ps |
| CPU time | 53.6 seconds |
| Started | Sep 18 09:51:23 AM UTC 24 |
| Finished | Sep 18 09:52:32 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4234041459 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 143.prim_prince_test.4234041459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/143.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/144.prim_prince_test.2380239943 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 1427918505 ps |
| CPU time | 26.38 seconds |
| Started | Sep 18 09:51:24 AM UTC 24 |
| Finished | Sep 18 09:51:58 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2380239943 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 144.prim_prince_test.2380239943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/144.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/145.prim_prince_test.2568083168 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 1050378167 ps |
| CPU time | 19.92 seconds |
| Started | Sep 18 09:51:29 AM UTC 24 |
| Finished | Sep 18 09:51:55 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2568083168 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 145.prim_prince_test.2568083168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/145.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/146.prim_prince_test.1099924207 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 769597055 ps |
| CPU time | 15.18 seconds |
| Started | Sep 18 09:51:30 AM UTC 24 |
| Finished | Sep 18 09:51:50 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1099924207 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 146.prim_prince_test.1099924207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/146.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/147.prim_prince_test.995817394 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 1071826427 ps |
| CPU time | 21.04 seconds |
| Started | Sep 18 09:51:32 AM UTC 24 |
| Finished | Sep 18 09:51:59 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=995817394 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 147.prim_prince_test.995817394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/147.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/148.prim_prince_test.2923206545 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 1757970110 ps |
| CPU time | 34.74 seconds |
| Started | Sep 18 09:51:33 AM UTC 24 |
| Finished | Sep 18 09:52:17 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2923206545 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 148.prim_prince_test.2923206545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/148.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/149.prim_prince_test.169415793 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 3019458537 ps |
| CPU time | 58.08 seconds |
| Started | Sep 18 09:51:35 AM UTC 24 |
| Finished | Sep 18 09:52:48 AM UTC 24 |
| Peak memory | 156104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=169415793 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 149.prim_prince_test.169415793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/149.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/15.prim_prince_test.2492988559 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 1977573191 ps |
| CPU time | 39.98 seconds |
| Started | Sep 18 09:46:32 AM UTC 24 |
| Finished | Sep 18 09:47:24 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2492988559 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 15.prim_prince_test.2492988559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/15.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/150.prim_prince_test.2128628361 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 2379347632 ps |
| CPU time | 44.39 seconds |
| Started | Sep 18 09:51:37 AM UTC 24 |
| Finished | Sep 18 09:52:34 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2128628361 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 150.prim_prince_test.2128628361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/150.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/151.prim_prince_test.1999576443 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 1931522368 ps |
| CPU time | 38.32 seconds |
| Started | Sep 18 09:51:40 AM UTC 24 |
| Finished | Sep 18 09:52:29 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1999576443 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 151.prim_prince_test.1999576443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/151.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/152.prim_prince_test.3480436569 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 1372003751 ps |
| CPU time | 25.24 seconds |
| Started | Sep 18 09:51:41 AM UTC 24 |
| Finished | Sep 18 09:52:14 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3480436569 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 152.prim_prince_test.3480436569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/152.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/153.prim_prince_test.102920602 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 2096745197 ps |
| CPU time | 40.84 seconds |
| Started | Sep 18 09:51:45 AM UTC 24 |
| Finished | Sep 18 09:52:37 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=102920602 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 153.prim_prince_test.102920602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/153.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/154.prim_prince_test.4009440087 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 995561890 ps |
| CPU time | 18.73 seconds |
| Started | Sep 18 09:51:46 AM UTC 24 |
| Finished | Sep 18 09:52:11 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4009440087 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 154.prim_prince_test.4009440087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/154.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/155.prim_prince_test.1822555480 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 2257621235 ps |
| CPU time | 43.7 seconds |
| Started | Sep 18 09:51:48 AM UTC 24 |
| Finished | Sep 18 09:52:44 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1822555480 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 155.prim_prince_test.1822555480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/155.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/156.prim_prince_test.3489802380 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 2942206190 ps |
| CPU time | 56.44 seconds |
| Started | Sep 18 09:51:49 AM UTC 24 |
| Finished | Sep 18 09:53:00 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3489802380 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 156.prim_prince_test.3489802380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/156.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/157.prim_prince_test.2874946761 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 2560492399 ps |
| CPU time | 46.36 seconds |
| Started | Sep 18 09:51:50 AM UTC 24 |
| Finished | Sep 18 09:52:49 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2874946761 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 157.prim_prince_test.2874946761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/157.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/158.prim_prince_test.325649312 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 1231582100 ps |
| CPU time | 24.41 seconds |
| Started | Sep 18 09:51:50 AM UTC 24 |
| Finished | Sep 18 09:52:21 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=325649312 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 158.prim_prince_test.325649312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/158.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/159.prim_prince_test.733618622 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 1701825411 ps |
| CPU time | 33.55 seconds |
| Started | Sep 18 09:51:51 AM UTC 24 |
| Finished | Sep 18 09:52:34 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=733618622 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 159.prim_prince_test.733618622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/159.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/16.prim_prince_test.1774812956 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 881943732 ps |
| CPU time | 18.03 seconds |
| Started | Sep 18 09:46:50 AM UTC 24 |
| Finished | Sep 18 09:47:15 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1774812956 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 16.prim_prince_test.1774812956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/16.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/160.prim_prince_test.3286352730 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 1041542594 ps |
| CPU time | 20.39 seconds |
| Started | Sep 18 09:51:51 AM UTC 24 |
| Finished | Sep 18 09:52:18 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3286352730 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 160.prim_prince_test.3286352730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/160.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/161.prim_prince_test.3965170761 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 1979014744 ps |
| CPU time | 36.6 seconds |
| Started | Sep 18 09:51:53 AM UTC 24 |
| Finished | Sep 18 09:52:41 AM UTC 24 |
| Peak memory | 154588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3965170761 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 161.prim_prince_test.3965170761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/161.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/162.prim_prince_test.3222970827 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 1444928522 ps |
| CPU time | 28.84 seconds |
| Started | Sep 18 09:51:55 AM UTC 24 |
| Finished | Sep 18 09:52:32 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3222970827 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 162.prim_prince_test.3222970827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/162.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/163.prim_prince_test.3221087137 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 3268613575 ps |
| CPU time | 59.99 seconds |
| Started | Sep 18 09:51:56 AM UTC 24 |
| Finished | Sep 18 09:53:13 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3221087137 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 163.prim_prince_test.3221087137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/163.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/164.prim_prince_test.4052764218 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 3457605714 ps |
| CPU time | 66.86 seconds |
| Started | Sep 18 09:51:58 AM UTC 24 |
| Finished | Sep 18 09:53:23 AM UTC 24 |
| Peak memory | 154652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4052764218 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 164.prim_prince_test.4052764218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/164.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/165.prim_prince_test.29160762 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 1703151370 ps |
| CPU time | 31.56 seconds |
| Started | Sep 18 09:51:58 AM UTC 24 |
| Finished | Sep 18 09:52:39 AM UTC 24 |
| Peak memory | 154588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29160762 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 165.prim_prince_test.29160762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/165.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/166.prim_prince_test.1181378637 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 3507033372 ps |
| CPU time | 63.67 seconds |
| Started | Sep 18 09:51:58 AM UTC 24 |
| Finished | Sep 18 09:53:20 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1181378637 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 166.prim_prince_test.1181378637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/166.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/167.prim_prince_test.3110130549 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 3428002352 ps |
| CPU time | 62.6 seconds |
| Started | Sep 18 09:51:59 AM UTC 24 |
| Finished | Sep 18 09:53:20 AM UTC 24 |
| Peak memory | 154652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3110130549 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 167.prim_prince_test.3110130549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/167.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/168.prim_prince_test.2428860238 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 1481637244 ps |
| CPU time | 27.58 seconds |
| Started | Sep 18 09:52:05 AM UTC 24 |
| Finished | Sep 18 09:52:40 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2428860238 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 168.prim_prince_test.2428860238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/168.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/169.prim_prince_test.3422204558 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 1371354415 ps |
| CPU time | 25.37 seconds |
| Started | Sep 18 09:52:07 AM UTC 24 |
| Finished | Sep 18 09:52:40 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3422204558 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 169.prim_prince_test.3422204558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/169.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/17.prim_prince_test.3731710859 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 2234431749 ps |
| CPU time | 44.82 seconds |
| Started | Sep 18 09:46:55 AM UTC 24 |
| Finished | Sep 18 09:47:52 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3731710859 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 17.prim_prince_test.3731710859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/17.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/170.prim_prince_test.3150996626 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 1944340402 ps |
| CPU time | 36.49 seconds |
| Started | Sep 18 09:52:09 AM UTC 24 |
| Finished | Sep 18 09:52:56 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3150996626 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 170.prim_prince_test.3150996626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/170.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/171.prim_prince_test.630662113 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 2377687390 ps |
| CPU time | 43.59 seconds |
| Started | Sep 18 09:52:11 AM UTC 24 |
| Finished | Sep 18 09:53:07 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=630662113 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 171.prim_prince_test.630662113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/171.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/172.prim_prince_test.3921356723 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 1193505304 ps |
| CPU time | 23.45 seconds |
| Started | Sep 18 09:52:12 AM UTC 24 |
| Finished | Sep 18 09:52:42 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3921356723 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 172.prim_prince_test.3921356723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/172.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/173.prim_prince_test.3366287473 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 1547087104 ps |
| CPU time | 28.72 seconds |
| Started | Sep 18 09:52:15 AM UTC 24 |
| Finished | Sep 18 09:52:52 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3366287473 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 173.prim_prince_test.3366287473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/173.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/174.prim_prince_test.2767680258 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 2838608999 ps |
| CPU time | 55.41 seconds |
| Started | Sep 18 09:52:17 AM UTC 24 |
| Finished | Sep 18 09:53:27 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2767680258 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 174.prim_prince_test.2767680258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/174.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/175.prim_prince_test.702963642 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 840187646 ps |
| CPU time | 16.8 seconds |
| Started | Sep 18 09:52:17 AM UTC 24 |
| Finished | Sep 18 09:52:39 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=702963642 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 175.prim_prince_test.702963642 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/175.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/176.prim_prince_test.3675092210 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 2381201542 ps |
| CPU time | 43.59 seconds |
| Started | Sep 18 09:52:18 AM UTC 24 |
| Finished | Sep 18 09:53:14 AM UTC 24 |
| Peak memory | 154652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3675092210 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 176.prim_prince_test.3675092210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/176.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/177.prim_prince_test.2934378128 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 1638281029 ps |
| CPU time | 31.96 seconds |
| Started | Sep 18 09:52:19 AM UTC 24 |
| Finished | Sep 18 09:53:00 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2934378128 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 177.prim_prince_test.2934378128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/177.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/178.prim_prince_test.2411440831 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 2388993481 ps |
| CPU time | 46.25 seconds |
| Started | Sep 18 09:52:21 AM UTC 24 |
| Finished | Sep 18 09:53:20 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2411440831 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 178.prim_prince_test.2411440831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/178.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/179.prim_prince_test.3602918369 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 772474451 ps |
| CPU time | 15.42 seconds |
| Started | Sep 18 09:52:24 AM UTC 24 |
| Finished | Sep 18 09:52:45 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3602918369 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 179.prim_prince_test.3602918369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/179.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/18.prim_prince_test.1189415204 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 1662851360 ps |
| CPU time | 32.76 seconds |
| Started | Sep 18 09:47:03 AM UTC 24 |
| Finished | Sep 18 09:47:45 AM UTC 24 |
| Peak memory | 154336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1189415204 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 18.prim_prince_test.1189415204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/18.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/180.prim_prince_test.3681641439 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 2142991059 ps |
| CPU time | 41.94 seconds |
| Started | Sep 18 09:52:28 AM UTC 24 |
| Finished | Sep 18 09:53:21 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3681641439 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 180.prim_prince_test.3681641439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/180.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/181.prim_prince_test.1396410703 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 1067363808 ps |
| CPU time | 20.6 seconds |
| Started | Sep 18 09:52:30 AM UTC 24 |
| Finished | Sep 18 09:52:56 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1396410703 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 181.prim_prince_test.1396410703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/181.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/182.prim_prince_test.3117043518 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 2736704738 ps |
| CPU time | 50.64 seconds |
| Started | Sep 18 09:52:31 AM UTC 24 |
| Finished | Sep 18 09:53:36 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3117043518 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 182.prim_prince_test.3117043518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/182.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/183.prim_prince_test.3025552358 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 2192021100 ps |
| CPU time | 42.51 seconds |
| Started | Sep 18 09:52:32 AM UTC 24 |
| Finished | Sep 18 09:53:26 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3025552358 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 183.prim_prince_test.3025552358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/183.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/184.prim_prince_test.3197869882 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 3443927371 ps |
| CPU time | 66.72 seconds |
| Started | Sep 18 09:52:33 AM UTC 24 |
| Finished | Sep 18 09:53:57 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3197869882 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 184.prim_prince_test.3197869882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/184.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/185.prim_prince_test.3535170366 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 3072985347 ps |
| CPU time | 58.31 seconds |
| Started | Sep 18 09:52:33 AM UTC 24 |
| Finished | Sep 18 09:53:47 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3535170366 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 185.prim_prince_test.3535170366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/185.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/186.prim_prince_test.981230508 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 2751686867 ps |
| CPU time | 50.03 seconds |
| Started | Sep 18 09:52:35 AM UTC 24 |
| Finished | Sep 18 09:53:40 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=981230508 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 186.prim_prince_test.981230508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/186.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/187.prim_prince_test.2570440466 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 1062138936 ps |
| CPU time | 20.99 seconds |
| Started | Sep 18 09:52:35 AM UTC 24 |
| Finished | Sep 18 09:53:02 AM UTC 24 |
| Peak memory | 154588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2570440466 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 187.prim_prince_test.2570440466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/187.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/188.prim_prince_test.3507221728 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 2674160284 ps |
| CPU time | 49.02 seconds |
| Started | Sep 18 09:52:38 AM UTC 24 |
| Finished | Sep 18 09:53:41 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3507221728 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 188.prim_prince_test.3507221728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/188.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/189.prim_prince_test.3309364119 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 1821005961 ps |
| CPU time | 35.6 seconds |
| Started | Sep 18 09:52:39 AM UTC 24 |
| Finished | Sep 18 09:53:25 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3309364119 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 189.prim_prince_test.3309364119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/189.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/19.prim_prince_test.3201245921 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 2131645888 ps |
| CPU time | 41.82 seconds |
| Started | Sep 18 09:47:03 AM UTC 24 |
| Finished | Sep 18 09:47:57 AM UTC 24 |
| Peak memory | 154340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3201245921 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 19.prim_prince_test.3201245921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/19.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/190.prim_prince_test.3700620161 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 808491334 ps |
| CPU time | 15.52 seconds |
| Started | Sep 18 09:52:41 AM UTC 24 |
| Finished | Sep 18 09:53:01 AM UTC 24 |
| Peak memory | 154588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3700620161 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 190.prim_prince_test.3700620161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/190.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/191.prim_prince_test.2495910834 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 1394115269 ps |
| CPU time | 27.26 seconds |
| Started | Sep 18 09:52:41 AM UTC 24 |
| Finished | Sep 18 09:53:15 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2495910834 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 191.prim_prince_test.2495910834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/191.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/192.prim_prince_test.2411736434 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 3393655126 ps |
| CPU time | 65.27 seconds |
| Started | Sep 18 09:52:41 AM UTC 24 |
| Finished | Sep 18 09:54:03 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2411736434 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 192.prim_prince_test.2411736434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/192.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/193.prim_prince_test.2197806848 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 3476822217 ps |
| CPU time | 61.96 seconds |
| Started | Sep 18 09:52:42 AM UTC 24 |
| Finished | Sep 18 09:54:02 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2197806848 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 193.prim_prince_test.2197806848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/193.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/194.prim_prince_test.1313914254 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 3463274359 ps |
| CPU time | 66.59 seconds |
| Started | Sep 18 09:52:42 AM UTC 24 |
| Finished | Sep 18 09:54:06 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1313914254 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 194.prim_prince_test.1313914254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/194.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/195.prim_prince_test.2162692432 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 3594024557 ps |
| CPU time | 67.38 seconds |
| Started | Sep 18 09:52:43 AM UTC 24 |
| Finished | Sep 18 09:54:09 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2162692432 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 195.prim_prince_test.2162692432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/195.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/196.prim_prince_test.3963828183 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 2215726336 ps |
| CPU time | 41.61 seconds |
| Started | Sep 18 09:52:45 AM UTC 24 |
| Finished | Sep 18 09:53:38 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3963828183 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 196.prim_prince_test.3963828183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/196.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/197.prim_prince_test.911607717 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 2518902240 ps |
| CPU time | 48.75 seconds |
| Started | Sep 18 09:52:45 AM UTC 24 |
| Finished | Sep 18 09:53:47 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=911607717 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 197.prim_prince_test.911607717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/197.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/198.prim_prince_test.4020612181 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 1741250495 ps |
| CPU time | 34.15 seconds |
| Started | Sep 18 09:52:49 AM UTC 24 |
| Finished | Sep 18 09:53:33 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4020612181 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 198.prim_prince_test.4020612181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/198.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/199.prim_prince_test.593012391 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 3562521531 ps |
| CPU time | 68.07 seconds |
| Started | Sep 18 09:52:50 AM UTC 24 |
| Finished | Sep 18 09:54:17 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=593012391 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 199.prim_prince_test.593012391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/199.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/2.prim_prince_test.3512476638 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 2906095508 ps |
| CPU time | 57.43 seconds |
| Started | Sep 18 09:46:29 AM UTC 24 |
| Finished | Sep 18 09:47:43 AM UTC 24 |
| Peak memory | 154368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3512476638 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 2.prim_prince_test.3512476638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/2.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/20.prim_prince_test.187076170 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 2923905338 ps |
| CPU time | 56.98 seconds |
| Started | Sep 18 09:47:04 AM UTC 24 |
| Finished | Sep 18 09:48:18 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=187076170 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 20.prim_prince_test.187076170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/20.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/200.prim_prince_test.2221362602 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 2148041561 ps |
| CPU time | 42.05 seconds |
| Started | Sep 18 09:52:51 AM UTC 24 |
| Finished | Sep 18 09:53:45 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2221362602 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 200.prim_prince_test.2221362602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/200.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/201.prim_prince_test.3395634075 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 2963029835 ps |
| CPU time | 53.84 seconds |
| Started | Sep 18 09:52:52 AM UTC 24 |
| Finished | Sep 18 09:54:02 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3395634075 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 201.prim_prince_test.3395634075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/201.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/202.prim_prince_test.2679194413 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 3583049845 ps |
| CPU time | 69.18 seconds |
| Started | Sep 18 09:52:57 AM UTC 24 |
| Finished | Sep 18 09:54:24 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2679194413 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 202.prim_prince_test.2679194413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/202.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/203.prim_prince_test.567738693 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 1414964335 ps |
| CPU time | 26.41 seconds |
| Started | Sep 18 09:52:58 AM UTC 24 |
| Finished | Sep 18 09:53:32 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=567738693 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 203.prim_prince_test.567738693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/203.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/204.prim_prince_test.1650931033 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 1733154420 ps |
| CPU time | 32.42 seconds |
| Started | Sep 18 09:53:01 AM UTC 24 |
| Finished | Sep 18 09:53:43 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1650931033 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 204.prim_prince_test.1650931033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/204.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/205.prim_prince_test.2554776019 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 2985743697 ps |
| CPU time | 57.45 seconds |
| Started | Sep 18 09:53:01 AM UTC 24 |
| Finished | Sep 18 09:54:14 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2554776019 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 205.prim_prince_test.2554776019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/205.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/206.prim_prince_test.4090587082 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 2478836463 ps |
| CPU time | 46.44 seconds |
| Started | Sep 18 09:53:02 AM UTC 24 |
| Finished | Sep 18 09:54:01 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4090587082 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 206.prim_prince_test.4090587082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/206.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/207.prim_prince_test.1137741209 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 2224873187 ps |
| CPU time | 43.01 seconds |
| Started | Sep 18 09:53:03 AM UTC 24 |
| Finished | Sep 18 09:53:58 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1137741209 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 207.prim_prince_test.1137741209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/207.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/208.prim_prince_test.3724212326 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 928684136 ps |
| CPU time | 18.38 seconds |
| Started | Sep 18 09:53:08 AM UTC 24 |
| Finished | Sep 18 09:53:32 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3724212326 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 208.prim_prince_test.3724212326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/208.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/209.prim_prince_test.4276269685 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 2673721192 ps |
| CPU time | 51.9 seconds |
| Started | Sep 18 09:53:13 AM UTC 24 |
| Finished | Sep 18 09:54:19 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4276269685 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 209.prim_prince_test.4276269685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/209.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/21.prim_prince_test.1122352416 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 3060073588 ps |
| CPU time | 59.95 seconds |
| Started | Sep 18 09:47:06 AM UTC 24 |
| Finished | Sep 18 09:48:23 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1122352416 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 21.prim_prince_test.1122352416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/21.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/210.prim_prince_test.314659617 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 1389689731 ps |
| CPU time | 27.07 seconds |
| Started | Sep 18 09:53:15 AM UTC 24 |
| Finished | Sep 18 09:53:50 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=314659617 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 210.prim_prince_test.314659617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/210.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/211.prim_prince_test.1264822791 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 1830901012 ps |
| CPU time | 34.99 seconds |
| Started | Sep 18 09:53:17 AM UTC 24 |
| Finished | Sep 18 09:54:01 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1264822791 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 211.prim_prince_test.1264822791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/211.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/212.prim_prince_test.1761266087 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 1158412411 ps |
| CPU time | 22.68 seconds |
| Started | Sep 18 09:53:21 AM UTC 24 |
| Finished | Sep 18 09:53:50 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1761266087 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 212.prim_prince_test.1761266087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/212.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/213.prim_prince_test.3761439859 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 2666720351 ps |
| CPU time | 48.4 seconds |
| Started | Sep 18 09:53:21 AM UTC 24 |
| Finished | Sep 18 09:54:23 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3761439859 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 213.prim_prince_test.3761439859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/213.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/214.prim_prince_test.3835581476 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 3138634073 ps |
| CPU time | 60.36 seconds |
| Started | Sep 18 09:53:21 AM UTC 24 |
| Finished | Sep 18 09:54:37 AM UTC 24 |
| Peak memory | 154652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3835581476 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 214.prim_prince_test.3835581476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/214.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/215.prim_prince_test.4259819272 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 2608050010 ps |
| CPU time | 47.59 seconds |
| Started | Sep 18 09:53:22 AM UTC 24 |
| Finished | Sep 18 09:54:23 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4259819272 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 215.prim_prince_test.4259819272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/215.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/216.prim_prince_test.1003484483 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 3215850106 ps |
| CPU time | 59.48 seconds |
| Started | Sep 18 09:53:23 AM UTC 24 |
| Finished | Sep 18 09:54:40 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1003484483 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 216.prim_prince_test.1003484483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/216.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/217.prim_prince_test.662162170 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 3325459221 ps |
| CPU time | 60.37 seconds |
| Started | Sep 18 09:53:25 AM UTC 24 |
| Finished | Sep 18 09:54:43 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=662162170 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 217.prim_prince_test.662162170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/217.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/218.prim_prince_test.3934005795 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 3279342830 ps |
| CPU time | 62 seconds |
| Started | Sep 18 09:53:26 AM UTC 24 |
| Finished | Sep 18 09:54:45 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3934005795 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 218.prim_prince_test.3934005795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/218.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/219.prim_prince_test.3631486245 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 1674464623 ps |
| CPU time | 32.23 seconds |
| Started | Sep 18 09:53:28 AM UTC 24 |
| Finished | Sep 18 09:54:10 AM UTC 24 |
| Peak memory | 154588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3631486245 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 219.prim_prince_test.3631486245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/219.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/22.prim_prince_test.1299804829 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 3180608344 ps |
| CPU time | 61.26 seconds |
| Started | Sep 18 09:47:07 AM UTC 24 |
| Finished | Sep 18 09:48:27 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1299804829 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 22.prim_prince_test.1299804829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/22.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/220.prim_prince_test.2682358513 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 1735989592 ps |
| CPU time | 32.11 seconds |
| Started | Sep 18 09:53:33 AM UTC 24 |
| Finished | Sep 18 09:54:14 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2682358513 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 220.prim_prince_test.2682358513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/220.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/221.prim_prince_test.1241120592 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 2550512667 ps |
| CPU time | 47.73 seconds |
| Started | Sep 18 09:53:33 AM UTC 24 |
| Finished | Sep 18 09:54:34 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1241120592 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 221.prim_prince_test.1241120592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/221.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/222.prim_prince_test.2107585903 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 1159652291 ps |
| CPU time | 22.74 seconds |
| Started | Sep 18 09:53:34 AM UTC 24 |
| Finished | Sep 18 09:54:03 AM UTC 24 |
| Peak memory | 154588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2107585903 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 222.prim_prince_test.2107585903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/222.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/223.prim_prince_test.3677306689 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 2601605938 ps |
| CPU time | 49.8 seconds |
| Started | Sep 18 09:53:37 AM UTC 24 |
| Finished | Sep 18 09:54:40 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3677306689 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 223.prim_prince_test.3677306689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/223.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/224.prim_prince_test.590391493 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 2863824009 ps |
| CPU time | 52.22 seconds |
| Started | Sep 18 09:53:39 AM UTC 24 |
| Finished | Sep 18 09:54:46 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=590391493 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 224.prim_prince_test.590391493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/224.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/225.prim_prince_test.113423386 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 1578120191 ps |
| CPU time | 30.49 seconds |
| Started | Sep 18 09:53:40 AM UTC 24 |
| Finished | Sep 18 09:54:19 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=113423386 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 225.prim_prince_test.113423386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/225.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/226.prim_prince_test.1513269811 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 3657201937 ps |
| CPU time | 67.21 seconds |
| Started | Sep 18 09:53:42 AM UTC 24 |
| Finished | Sep 18 09:55:08 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1513269811 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 226.prim_prince_test.1513269811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/226.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/227.prim_prince_test.90506088 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 1248981760 ps |
| CPU time | 24.69 seconds |
| Started | Sep 18 09:53:43 AM UTC 24 |
| Finished | Sep 18 09:54:15 AM UTC 24 |
| Peak memory | 154588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=90506088 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 227.prim_prince_test.90506088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/227.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/228.prim_prince_test.452573370 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 1843399388 ps |
| CPU time | 34.47 seconds |
| Started | Sep 18 09:53:45 AM UTC 24 |
| Finished | Sep 18 09:54:30 AM UTC 24 |
| Peak memory | 154588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=452573370 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 228.prim_prince_test.452573370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/228.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/229.prim_prince_test.972128028 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 831527614 ps |
| CPU time | 16.4 seconds |
| Started | Sep 18 09:53:47 AM UTC 24 |
| Finished | Sep 18 09:54:09 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=972128028 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 229.prim_prince_test.972128028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/229.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/23.prim_prince_test.1421452495 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 2406976540 ps |
| CPU time | 48.1 seconds |
| Started | Sep 18 09:47:14 AM UTC 24 |
| Finished | Sep 18 09:48:16 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1421452495 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 23.prim_prince_test.1421452495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/23.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/230.prim_prince_test.1325135941 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 2192948790 ps |
| CPU time | 40.63 seconds |
| Started | Sep 18 09:53:48 AM UTC 24 |
| Finished | Sep 18 09:54:40 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1325135941 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 230.prim_prince_test.1325135941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/230.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/231.prim_prince_test.1067260257 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 1918933156 ps |
| CPU time | 36.69 seconds |
| Started | Sep 18 09:53:51 AM UTC 24 |
| Finished | Sep 18 09:54:38 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1067260257 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 231.prim_prince_test.1067260257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/231.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/232.prim_prince_test.4105277408 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 1677769446 ps |
| CPU time | 31.24 seconds |
| Started | Sep 18 09:53:51 AM UTC 24 |
| Finished | Sep 18 09:54:31 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4105277408 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 232.prim_prince_test.4105277408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/232.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/233.prim_prince_test.1440366030 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 1070238443 ps |
| CPU time | 20.39 seconds |
| Started | Sep 18 09:53:58 AM UTC 24 |
| Finished | Sep 18 09:54:24 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1440366030 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 233.prim_prince_test.1440366030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/233.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/234.prim_prince_test.518945574 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 2040205477 ps |
| CPU time | 39.1 seconds |
| Started | Sep 18 09:53:58 AM UTC 24 |
| Finished | Sep 18 09:54:47 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=518945574 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 234.prim_prince_test.518945574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/234.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/235.prim_prince_test.3591392841 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 3696054090 ps |
| CPU time | 71.09 seconds |
| Started | Sep 18 09:53:59 AM UTC 24 |
| Finished | Sep 18 09:55:28 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3591392841 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 235.prim_prince_test.3591392841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/235.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/236.prim_prince_test.1922106216 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 1912046103 ps |
| CPU time | 37.11 seconds |
| Started | Sep 18 09:54:02 AM UTC 24 |
| Finished | Sep 18 09:54:49 AM UTC 24 |
| Peak memory | 156044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1922106216 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 236.prim_prince_test.1922106216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/236.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/237.prim_prince_test.3684157018 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 1457983798 ps |
| CPU time | 26.82 seconds |
| Started | Sep 18 09:54:02 AM UTC 24 |
| Finished | Sep 18 09:54:37 AM UTC 24 |
| Peak memory | 154588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3684157018 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 237.prim_prince_test.3684157018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/237.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/238.prim_prince_test.4124360366 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 3235006984 ps |
| CPU time | 57.74 seconds |
| Started | Sep 18 09:54:02 AM UTC 24 |
| Finished | Sep 18 09:55:16 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4124360366 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 238.prim_prince_test.4124360366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/238.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/239.prim_prince_test.1009292889 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 3139586342 ps |
| CPU time | 57.73 seconds |
| Started | Sep 18 09:54:02 AM UTC 24 |
| Finished | Sep 18 09:55:16 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1009292889 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 239.prim_prince_test.1009292889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/239.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/24.prim_prince_test.3458939210 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 3620711172 ps |
| CPU time | 70.52 seconds |
| Started | Sep 18 09:47:15 AM UTC 24 |
| Finished | Sep 18 09:48:45 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3458939210 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 24.prim_prince_test.3458939210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/24.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/240.prim_prince_test.2669876409 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 2187045689 ps |
| CPU time | 42.68 seconds |
| Started | Sep 18 09:54:04 AM UTC 24 |
| Finished | Sep 18 09:54:57 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2669876409 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 240.prim_prince_test.2669876409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/240.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/241.prim_prince_test.1262508606 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 2701331139 ps |
| CPU time | 51.5 seconds |
| Started | Sep 18 09:54:04 AM UTC 24 |
| Finished | Sep 18 09:55:09 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1262508606 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 241.prim_prince_test.1262508606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/241.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/242.prim_prince_test.3123694205 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 2954264521 ps |
| CPU time | 53.23 seconds |
| Started | Sep 18 09:54:07 AM UTC 24 |
| Finished | Sep 18 09:55:15 AM UTC 24 |
| Peak memory | 154652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3123694205 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 242.prim_prince_test.3123694205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/242.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/243.prim_prince_test.1522605570 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 2106469588 ps |
| CPU time | 39.15 seconds |
| Started | Sep 18 09:54:10 AM UTC 24 |
| Finished | Sep 18 09:55:00 AM UTC 24 |
| Peak memory | 154588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1522605570 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 243.prim_prince_test.1522605570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/243.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/244.prim_prince_test.2098102574 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 1431746060 ps |
| CPU time | 28.01 seconds |
| Started | Sep 18 09:54:10 AM UTC 24 |
| Finished | Sep 18 09:54:45 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2098102574 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 244.prim_prince_test.2098102574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/244.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/245.prim_prince_test.3149161757 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 2103666677 ps |
| CPU time | 40.31 seconds |
| Started | Sep 18 09:54:11 AM UTC 24 |
| Finished | Sep 18 09:55:02 AM UTC 24 |
| Peak memory | 154588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3149161757 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 245.prim_prince_test.3149161757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/245.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/246.prim_prince_test.3251931831 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 2307751992 ps |
| CPU time | 44.13 seconds |
| Started | Sep 18 09:54:14 AM UTC 24 |
| Finished | Sep 18 09:55:10 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3251931831 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 246.prim_prince_test.3251931831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/246.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/247.prim_prince_test.4283435129 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 3365405847 ps |
| CPU time | 62.01 seconds |
| Started | Sep 18 09:54:15 AM UTC 24 |
| Finished | Sep 18 09:55:34 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4283435129 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 247.prim_prince_test.4283435129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/247.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/248.prim_prince_test.1154368404 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 1725107249 ps |
| CPU time | 31.59 seconds |
| Started | Sep 18 09:54:16 AM UTC 24 |
| Finished | Sep 18 09:54:57 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1154368404 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 248.prim_prince_test.1154368404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/248.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/249.prim_prince_test.822844249 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 911870594 ps |
| CPU time | 17.63 seconds |
| Started | Sep 18 09:54:17 AM UTC 24 |
| Finished | Sep 18 09:54:40 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=822844249 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 249.prim_prince_test.822844249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/249.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/25.prim_prince_test.1827609073 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 1341228956 ps |
| CPU time | 25.91 seconds |
| Started | Sep 18 09:47:15 AM UTC 24 |
| Finished | Sep 18 09:47:50 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1827609073 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 25.prim_prince_test.1827609073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/25.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/250.prim_prince_test.2987382123 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 1213535710 ps |
| CPU time | 23.24 seconds |
| Started | Sep 18 09:54:20 AM UTC 24 |
| Finished | Sep 18 09:54:49 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2987382123 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 250.prim_prince_test.2987382123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/250.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/251.prim_prince_test.891305754 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 2730279399 ps |
| CPU time | 51.93 seconds |
| Started | Sep 18 09:54:20 AM UTC 24 |
| Finished | Sep 18 09:55:25 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=891305754 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 251.prim_prince_test.891305754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/251.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/252.prim_prince_test.199956709 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 1198537400 ps |
| CPU time | 23.01 seconds |
| Started | Sep 18 09:54:24 AM UTC 24 |
| Finished | Sep 18 09:54:53 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=199956709 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 252.prim_prince_test.199956709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/252.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/253.prim_prince_test.684209163 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 2823875468 ps |
| CPU time | 53.51 seconds |
| Started | Sep 18 09:54:24 AM UTC 24 |
| Finished | Sep 18 09:55:31 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=684209163 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 253.prim_prince_test.684209163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/253.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/254.prim_prince_test.3551065409 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 3073940465 ps |
| CPU time | 57.36 seconds |
| Started | Sep 18 09:54:25 AM UTC 24 |
| Finished | Sep 18 09:55:38 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3551065409 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 254.prim_prince_test.3551065409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/254.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/255.prim_prince_test.882411336 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 3451776218 ps |
| CPU time | 65.79 seconds |
| Started | Sep 18 09:54:25 AM UTC 24 |
| Finished | Sep 18 09:55:48 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=882411336 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 255.prim_prince_test.882411336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/255.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/256.prim_prince_test.343913594 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 3307236206 ps |
| CPU time | 62.25 seconds |
| Started | Sep 18 09:54:30 AM UTC 24 |
| Finished | Sep 18 09:55:49 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=343913594 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 256.prim_prince_test.343913594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/256.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/257.prim_prince_test.3731882837 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 3430346608 ps |
| CPU time | 61.96 seconds |
| Started | Sep 18 09:54:32 AM UTC 24 |
| Finished | Sep 18 09:55:52 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3731882837 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 257.prim_prince_test.3731882837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/257.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/258.prim_prince_test.2476503925 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 2208120680 ps |
| CPU time | 41.84 seconds |
| Started | Sep 18 09:54:34 AM UTC 24 |
| Finished | Sep 18 09:55:27 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2476503925 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 258.prim_prince_test.2476503925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/258.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/259.prim_prince_test.3565349963 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 2884267734 ps |
| CPU time | 54.05 seconds |
| Started | Sep 18 09:54:38 AM UTC 24 |
| Finished | Sep 18 09:55:46 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3565349963 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 259.prim_prince_test.3565349963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/259.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/26.prim_prince_test.3499446753 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 1803079012 ps |
| CPU time | 35.34 seconds |
| Started | Sep 18 09:47:24 AM UTC 24 |
| Finished | Sep 18 09:48:10 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3499446753 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 26.prim_prince_test.3499446753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/26.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/260.prim_prince_test.696874701 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 3038088289 ps |
| CPU time | 58.18 seconds |
| Started | Sep 18 09:54:38 AM UTC 24 |
| Finished | Sep 18 09:55:51 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=696874701 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 260.prim_prince_test.696874701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/260.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/261.prim_prince_test.526744218 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 3173049550 ps |
| CPU time | 57.62 seconds |
| Started | Sep 18 09:54:39 AM UTC 24 |
| Finished | Sep 18 09:55:53 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=526744218 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 261.prim_prince_test.526744218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/261.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/262.prim_prince_test.2716155962 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 3001452455 ps |
| CPU time | 54.59 seconds |
| Started | Sep 18 09:54:41 AM UTC 24 |
| Finished | Sep 18 09:55:51 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2716155962 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 262.prim_prince_test.2716155962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/262.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/263.prim_prince_test.4145751151 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 1007018598 ps |
| CPU time | 19.14 seconds |
| Started | Sep 18 09:54:41 AM UTC 24 |
| Finished | Sep 18 09:55:06 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4145751151 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 263.prim_prince_test.4145751151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/263.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/264.prim_prince_test.270715373 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 3332738609 ps |
| CPU time | 60.78 seconds |
| Started | Sep 18 09:54:41 AM UTC 24 |
| Finished | Sep 18 09:55:59 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=270715373 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 264.prim_prince_test.270715373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/264.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/265.prim_prince_test.1599975166 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 2466586410 ps |
| CPU time | 47.49 seconds |
| Started | Sep 18 09:54:41 AM UTC 24 |
| Finished | Sep 18 09:55:41 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1599975166 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 265.prim_prince_test.1599975166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/265.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/266.prim_prince_test.2513822362 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 1318117209 ps |
| CPU time | 24.65 seconds |
| Started | Sep 18 09:54:43 AM UTC 24 |
| Finished | Sep 18 09:55:15 AM UTC 24 |
| Peak memory | 154588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2513822362 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 266.prim_prince_test.2513822362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/266.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/267.prim_prince_test.3944388650 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 2999808517 ps |
| CPU time | 56.89 seconds |
| Started | Sep 18 09:54:47 AM UTC 24 |
| Finished | Sep 18 09:55:58 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3944388650 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 267.prim_prince_test.3944388650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/267.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/268.prim_prince_test.1855895194 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 806147441 ps |
| CPU time | 15.55 seconds |
| Started | Sep 18 09:54:47 AM UTC 24 |
| Finished | Sep 18 09:55:07 AM UTC 24 |
| Peak memory | 154588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1855895194 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 268.prim_prince_test.1855895194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/268.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/269.prim_prince_test.3520974672 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 3185174694 ps |
| CPU time | 58.56 seconds |
| Started | Sep 18 09:54:47 AM UTC 24 |
| Finished | Sep 18 09:56:01 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3520974672 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 269.prim_prince_test.3520974672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/269.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/27.prim_prince_test.3762687997 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 1412011442 ps |
| CPU time | 28.57 seconds |
| Started | Sep 18 09:47:24 AM UTC 24 |
| Finished | Sep 18 09:48:01 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3762687997 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 27.prim_prince_test.3762687997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/27.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/270.prim_prince_test.3921055451 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 1723337296 ps |
| CPU time | 32.95 seconds |
| Started | Sep 18 09:54:48 AM UTC 24 |
| Finished | Sep 18 09:55:30 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3921055451 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 270.prim_prince_test.3921055451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/270.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/271.prim_prince_test.1630650274 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 3258575690 ps |
| CPU time | 62 seconds |
| Started | Sep 18 09:54:50 AM UTC 24 |
| Finished | Sep 18 09:56:08 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1630650274 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 271.prim_prince_test.1630650274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/271.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/272.prim_prince_test.3113239769 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 3600238183 ps |
| CPU time | 65.14 seconds |
| Started | Sep 18 09:54:50 AM UTC 24 |
| Finished | Sep 18 09:56:13 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3113239769 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 272.prim_prince_test.3113239769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/272.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/273.prim_prince_test.3160951180 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 2741001439 ps |
| CPU time | 52.22 seconds |
| Started | Sep 18 09:54:54 AM UTC 24 |
| Finished | Sep 18 09:56:00 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3160951180 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 273.prim_prince_test.3160951180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/273.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/274.prim_prince_test.2091220462 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 3455052022 ps |
| CPU time | 63.19 seconds |
| Started | Sep 18 09:54:58 AM UTC 24 |
| Finished | Sep 18 09:56:19 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2091220462 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 274.prim_prince_test.2091220462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/274.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/275.prim_prince_test.2984002687 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 1108307647 ps |
| CPU time | 21 seconds |
| Started | Sep 18 09:54:58 AM UTC 24 |
| Finished | Sep 18 09:55:26 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2984002687 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 275.prim_prince_test.2984002687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/275.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/276.prim_prince_test.1416820513 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 2497623413 ps |
| CPU time | 47.96 seconds |
| Started | Sep 18 09:55:01 AM UTC 24 |
| Finished | Sep 18 09:56:01 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1416820513 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 276.prim_prince_test.1416820513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/276.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/277.prim_prince_test.2188062067 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 3635963288 ps |
| CPU time | 66.78 seconds |
| Started | Sep 18 09:55:03 AM UTC 24 |
| Finished | Sep 18 09:56:28 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2188062067 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 277.prim_prince_test.2188062067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/277.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/278.prim_prince_test.3880336166 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 1964684518 ps |
| CPU time | 36.12 seconds |
| Started | Sep 18 09:55:07 AM UTC 24 |
| Finished | Sep 18 09:55:53 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3880336166 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 278.prim_prince_test.3880336166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/278.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/279.prim_prince_test.791039931 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 3710328881 ps |
| CPU time | 67.44 seconds |
| Started | Sep 18 09:55:08 AM UTC 24 |
| Finished | Sep 18 09:56:34 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=791039931 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 279.prim_prince_test.791039931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/279.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/28.prim_prince_test.3348205171 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 3675189540 ps |
| CPU time | 72.45 seconds |
| Started | Sep 18 09:47:25 AM UTC 24 |
| Finished | Sep 18 09:48:57 AM UTC 24 |
| Peak memory | 156116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3348205171 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 28.prim_prince_test.3348205171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/28.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/280.prim_prince_test.3471627627 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 3685619801 ps |
| CPU time | 67.82 seconds |
| Started | Sep 18 09:55:09 AM UTC 24 |
| Finished | Sep 18 09:56:35 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3471627627 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 280.prim_prince_test.3471627627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/280.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/281.prim_prince_test.3262515274 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 2581793636 ps |
| CPU time | 49.86 seconds |
| Started | Sep 18 09:55:09 AM UTC 24 |
| Finished | Sep 18 09:56:12 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3262515274 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 281.prim_prince_test.3262515274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/281.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/282.prim_prince_test.640388582 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 2065444876 ps |
| CPU time | 39.74 seconds |
| Started | Sep 18 09:55:11 AM UTC 24 |
| Finished | Sep 18 09:56:02 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=640388582 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 282.prim_prince_test.640388582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/282.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/283.prim_prince_test.1922656066 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 2650697674 ps |
| CPU time | 50.27 seconds |
| Started | Sep 18 09:55:15 AM UTC 24 |
| Finished | Sep 18 09:56:19 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1922656066 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 283.prim_prince_test.1922656066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/283.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/284.prim_prince_test.1136339998 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 1173721243 ps |
| CPU time | 22.78 seconds |
| Started | Sep 18 09:55:17 AM UTC 24 |
| Finished | Sep 18 09:55:46 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1136339998 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 284.prim_prince_test.1136339998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/284.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/285.prim_prince_test.2604791963 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 752572549 ps |
| CPU time | 14.84 seconds |
| Started | Sep 18 09:55:17 AM UTC 24 |
| Finished | Sep 18 09:55:36 AM UTC 24 |
| Peak memory | 154588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2604791963 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 285.prim_prince_test.2604791963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/285.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/286.prim_prince_test.3789498480 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 3048117337 ps |
| CPU time | 57.52 seconds |
| Started | Sep 18 09:55:18 AM UTC 24 |
| Finished | Sep 18 09:56:31 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3789498480 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 286.prim_prince_test.3789498480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/286.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/287.prim_prince_test.2986199297 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 1722922273 ps |
| CPU time | 33.39 seconds |
| Started | Sep 18 09:55:26 AM UTC 24 |
| Finished | Sep 18 09:56:08 AM UTC 24 |
| Peak memory | 154588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2986199297 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 287.prim_prince_test.2986199297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/287.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/288.prim_prince_test.812696051 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 1792922044 ps |
| CPU time | 34.45 seconds |
| Started | Sep 18 09:55:26 AM UTC 24 |
| Finished | Sep 18 09:56:10 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=812696051 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 288.prim_prince_test.812696051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/288.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/289.prim_prince_test.2777357715 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 962966082 ps |
| CPU time | 18.6 seconds |
| Started | Sep 18 09:55:28 AM UTC 24 |
| Finished | Sep 18 09:55:52 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2777357715 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 289.prim_prince_test.2777357715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/289.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/29.prim_prince_test.2857151825 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 3731496149 ps |
| CPU time | 72.57 seconds |
| Started | Sep 18 09:47:30 AM UTC 24 |
| Finished | Sep 18 09:49:03 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2857151825 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 29.prim_prince_test.2857151825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/29.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/290.prim_prince_test.4213492039 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 3389567528 ps |
| CPU time | 61.55 seconds |
| Started | Sep 18 09:55:29 AM UTC 24 |
| Finished | Sep 18 09:56:48 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4213492039 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 290.prim_prince_test.4213492039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/290.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/291.prim_prince_test.3076929888 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 1712773412 ps |
| CPU time | 33.02 seconds |
| Started | Sep 18 09:55:30 AM UTC 24 |
| Finished | Sep 18 09:56:12 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3076929888 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 291.prim_prince_test.3076929888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/291.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/292.prim_prince_test.268628930 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 1964992409 ps |
| CPU time | 38.69 seconds |
| Started | Sep 18 09:55:32 AM UTC 24 |
| Finished | Sep 18 09:56:21 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=268628930 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 292.prim_prince_test.268628930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/292.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/293.prim_prince_test.750436862 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 2675598071 ps |
| CPU time | 51.12 seconds |
| Started | Sep 18 09:55:35 AM UTC 24 |
| Finished | Sep 18 09:56:39 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=750436862 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 293.prim_prince_test.750436862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/293.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/294.prim_prince_test.509107272 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 3115743476 ps |
| CPU time | 59.1 seconds |
| Started | Sep 18 09:55:37 AM UTC 24 |
| Finished | Sep 18 09:56:52 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=509107272 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 294.prim_prince_test.509107272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/294.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/295.prim_prince_test.4073242809 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 1227066135 ps |
| CPU time | 22.8 seconds |
| Started | Sep 18 09:55:39 AM UTC 24 |
| Finished | Sep 18 09:56:09 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4073242809 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 295.prim_prince_test.4073242809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/295.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/296.prim_prince_test.3226342623 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 1192872549 ps |
| CPU time | 22.72 seconds |
| Started | Sep 18 09:55:42 AM UTC 24 |
| Finished | Sep 18 09:56:11 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3226342623 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 296.prim_prince_test.3226342623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/296.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/297.prim_prince_test.3853728319 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 2767998520 ps |
| CPU time | 50.46 seconds |
| Started | Sep 18 09:55:47 AM UTC 24 |
| Finished | Sep 18 09:56:52 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3853728319 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 297.prim_prince_test.3853728319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/297.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/298.prim_prince_test.4025730392 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 2282821850 ps |
| CPU time | 43.14 seconds |
| Started | Sep 18 09:55:47 AM UTC 24 |
| Finished | Sep 18 09:56:42 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4025730392 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 298.prim_prince_test.4025730392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/298.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/299.prim_prince_test.2751434950 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 1446802246 ps |
| CPU time | 28.06 seconds |
| Started | Sep 18 09:55:48 AM UTC 24 |
| Finished | Sep 18 09:56:24 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2751434950 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 299.prim_prince_test.2751434950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/299.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/3.prim_prince_test.2351955521 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 1276044436 ps |
| CPU time | 27.12 seconds |
| Started | Sep 18 09:46:29 AM UTC 24 |
| Finished | Sep 18 09:47:05 AM UTC 24 |
| Peak memory | 154584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2351955521 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 3.prim_prince_test.2351955521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/3.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/30.prim_prince_test.3493233822 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 1004745822 ps |
| CPU time | 20.01 seconds |
| Started | Sep 18 09:47:30 AM UTC 24 |
| Finished | Sep 18 09:47:57 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3493233822 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 30.prim_prince_test.3493233822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/30.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/300.prim_prince_test.422074281 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 2103536357 ps |
| CPU time | 41.14 seconds |
| Started | Sep 18 09:55:49 AM UTC 24 |
| Finished | Sep 18 09:56:41 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=422074281 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 300.prim_prince_test.422074281 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/300.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/301.prim_prince_test.3204923674 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 976678112 ps |
| CPU time | 19.03 seconds |
| Started | Sep 18 09:55:52 AM UTC 24 |
| Finished | Sep 18 09:56:16 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3204923674 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 301.prim_prince_test.3204923674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/301.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/302.prim_prince_test.1867098639 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 1798256531 ps |
| CPU time | 33.13 seconds |
| Started | Sep 18 09:55:52 AM UTC 24 |
| Finished | Sep 18 09:56:34 AM UTC 24 |
| Peak memory | 154588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1867098639 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 302.prim_prince_test.1867098639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/302.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/303.prim_prince_test.165404202 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 1077072460 ps |
| CPU time | 20.87 seconds |
| Started | Sep 18 09:55:53 AM UTC 24 |
| Finished | Sep 18 09:56:20 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=165404202 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 303.prim_prince_test.165404202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/303.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/304.prim_prince_test.3445439996 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 1123820184 ps |
| CPU time | 21.49 seconds |
| Started | Sep 18 09:55:53 AM UTC 24 |
| Finished | Sep 18 09:56:21 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3445439996 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 304.prim_prince_test.3445439996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/304.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/305.prim_prince_test.453902336 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 3661187294 ps |
| CPU time | 69.08 seconds |
| Started | Sep 18 09:55:53 AM UTC 24 |
| Finished | Sep 18 09:57:20 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=453902336 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 305.prim_prince_test.453902336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/305.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/306.prim_prince_test.1992376390 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 2412199835 ps |
| CPU time | 44.08 seconds |
| Started | Sep 18 09:55:54 AM UTC 24 |
| Finished | Sep 18 09:56:51 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1992376390 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 306.prim_prince_test.1992376390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/306.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/307.prim_prince_test.1789248248 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 3387733676 ps |
| CPU time | 63.49 seconds |
| Started | Sep 18 09:55:59 AM UTC 24 |
| Finished | Sep 18 09:57:20 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1789248248 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 307.prim_prince_test.1789248248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/307.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/308.prim_prince_test.1967529097 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 2012988049 ps |
| CPU time | 38.38 seconds |
| Started | Sep 18 09:56:00 AM UTC 24 |
| Finished | Sep 18 09:56:48 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1967529097 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 308.prim_prince_test.1967529097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/308.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/309.prim_prince_test.658143001 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 1281587774 ps |
| CPU time | 23.79 seconds |
| Started | Sep 18 09:56:01 AM UTC 24 |
| Finished | Sep 18 09:56:31 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=658143001 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 309.prim_prince_test.658143001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/309.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/31.prim_prince_test.492765631 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 1808467548 ps |
| CPU time | 36.01 seconds |
| Started | Sep 18 09:47:31 AM UTC 24 |
| Finished | Sep 18 09:48:18 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=492765631 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 31.prim_prince_test.492765631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/31.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/310.prim_prince_test.163573775 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 2075810825 ps |
| CPU time | 39.53 seconds |
| Started | Sep 18 09:56:02 AM UTC 24 |
| Finished | Sep 18 09:56:52 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=163573775 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 310.prim_prince_test.163573775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/310.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/311.prim_prince_test.1510321223 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 3321542099 ps |
| CPU time | 63.12 seconds |
| Started | Sep 18 09:56:02 AM UTC 24 |
| Finished | Sep 18 09:57:21 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1510321223 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 311.prim_prince_test.1510321223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/311.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/312.prim_prince_test.3906905457 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 2202559908 ps |
| CPU time | 40.77 seconds |
| Started | Sep 18 09:56:03 AM UTC 24 |
| Finished | Sep 18 09:56:55 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3906905457 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 312.prim_prince_test.3906905457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/312.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/313.prim_prince_test.2576135047 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 1400665672 ps |
| CPU time | 27.41 seconds |
| Started | Sep 18 09:56:09 AM UTC 24 |
| Finished | Sep 18 09:56:44 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2576135047 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 313.prim_prince_test.2576135047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/313.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/314.prim_prince_test.4192741410 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 964914096 ps |
| CPU time | 18.23 seconds |
| Started | Sep 18 09:56:09 AM UTC 24 |
| Finished | Sep 18 09:56:33 AM UTC 24 |
| Peak memory | 154504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4192741410 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 314.prim_prince_test.4192741410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/314.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/315.prim_prince_test.3160457899 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 2569249873 ps |
| CPU time | 49.85 seconds |
| Started | Sep 18 09:56:09 AM UTC 24 |
| Finished | Sep 18 09:57:12 AM UTC 24 |
| Peak memory | 154616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3160457899 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 315.prim_prince_test.3160457899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/315.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/316.prim_prince_test.1485826007 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 3037552979 ps |
| CPU time | 57.51 seconds |
| Started | Sep 18 09:56:11 AM UTC 24 |
| Finished | Sep 18 09:57:23 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1485826007 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 316.prim_prince_test.1485826007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/316.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/317.prim_prince_test.3517617126 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 778780427 ps |
| CPU time | 15.08 seconds |
| Started | Sep 18 09:56:12 AM UTC 24 |
| Finished | Sep 18 09:56:31 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3517617126 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 317.prim_prince_test.3517617126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/317.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/318.prim_prince_test.722890556 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 2897071280 ps |
| CPU time | 54.83 seconds |
| Started | Sep 18 09:56:13 AM UTC 24 |
| Finished | Sep 18 09:57:22 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=722890556 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 318.prim_prince_test.722890556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/318.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/319.prim_prince_test.4214699835 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 3122603048 ps |
| CPU time | 59.3 seconds |
| Started | Sep 18 09:56:13 AM UTC 24 |
| Finished | Sep 18 09:57:28 AM UTC 24 |
| Peak memory | 154652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4214699835 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 319.prim_prince_test.4214699835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/319.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/32.prim_prince_test.1048196794 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 2945856129 ps |
| CPU time | 58.16 seconds |
| Started | Sep 18 09:47:34 AM UTC 24 |
| Finished | Sep 18 09:48:49 AM UTC 24 |
| Peak memory | 154660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1048196794 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 32.prim_prince_test.1048196794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/32.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/320.prim_prince_test.2955302742 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 2668626418 ps |
| CPU time | 49.93 seconds |
| Started | Sep 18 09:56:14 AM UTC 24 |
| Finished | Sep 18 09:57:17 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2955302742 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 320.prim_prince_test.2955302742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/320.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/321.prim_prince_test.571809713 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 2874908988 ps |
| CPU time | 54.66 seconds |
| Started | Sep 18 09:56:17 AM UTC 24 |
| Finished | Sep 18 09:57:26 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=571809713 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 321.prim_prince_test.571809713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/321.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/322.prim_prince_test.4125020427 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 1695744964 ps |
| CPU time | 32.85 seconds |
| Started | Sep 18 09:56:19 AM UTC 24 |
| Finished | Sep 18 09:57:01 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4125020427 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 322.prim_prince_test.4125020427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/322.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/323.prim_prince_test.4053040890 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 3733629638 ps |
| CPU time | 71.49 seconds |
| Started | Sep 18 09:56:21 AM UTC 24 |
| Finished | Sep 18 09:57:50 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4053040890 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 323.prim_prince_test.4053040890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/323.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/324.prim_prince_test.1240949571 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 3454089280 ps |
| CPU time | 63.05 seconds |
| Started | Sep 18 09:56:21 AM UTC 24 |
| Finished | Sep 18 09:57:41 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1240949571 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 324.prim_prince_test.1240949571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/324.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/325.prim_prince_test.3332003808 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 780562190 ps |
| CPU time | 15.53 seconds |
| Started | Sep 18 09:56:22 AM UTC 24 |
| Finished | Sep 18 09:56:42 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3332003808 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 325.prim_prince_test.3332003808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/325.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/326.prim_prince_test.2762607030 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 1318998705 ps |
| CPU time | 24.59 seconds |
| Started | Sep 18 09:56:23 AM UTC 24 |
| Finished | Sep 18 09:56:55 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2762607030 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 326.prim_prince_test.2762607030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/326.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/327.prim_prince_test.976698896 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 1544869733 ps |
| CPU time | 29.67 seconds |
| Started | Sep 18 09:56:25 AM UTC 24 |
| Finished | Sep 18 09:57:03 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=976698896 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 327.prim_prince_test.976698896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/327.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/328.prim_prince_test.2807813775 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 3122532872 ps |
| CPU time | 60.21 seconds |
| Started | Sep 18 09:56:28 AM UTC 24 |
| Finished | Sep 18 09:57:44 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2807813775 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 328.prim_prince_test.2807813775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/328.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/329.prim_prince_test.1139772402 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 3142191313 ps |
| CPU time | 57.75 seconds |
| Started | Sep 18 09:56:33 AM UTC 24 |
| Finished | Sep 18 09:57:46 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1139772402 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 329.prim_prince_test.1139772402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/329.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/33.prim_prince_test.1802423427 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 2530370712 ps |
| CPU time | 49.71 seconds |
| Started | Sep 18 09:47:36 AM UTC 24 |
| Finished | Sep 18 09:48:39 AM UTC 24 |
| Peak memory | 154652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1802423427 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 33.prim_prince_test.1802423427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/33.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/330.prim_prince_test.1546612410 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 1963602601 ps |
| CPU time | 35.68 seconds |
| Started | Sep 18 09:56:33 AM UTC 24 |
| Finished | Sep 18 09:57:18 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1546612410 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 330.prim_prince_test.1546612410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/330.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/331.prim_prince_test.4095937243 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 2193580891 ps |
| CPU time | 40.32 seconds |
| Started | Sep 18 09:56:33 AM UTC 24 |
| Finished | Sep 18 09:57:24 AM UTC 24 |
| Peak memory | 154652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4095937243 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 331.prim_prince_test.4095937243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/331.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/332.prim_prince_test.3196540071 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 913366342 ps |
| CPU time | 17.41 seconds |
| Started | Sep 18 09:56:34 AM UTC 24 |
| Finished | Sep 18 09:56:56 AM UTC 24 |
| Peak memory | 154588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3196540071 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 332.prim_prince_test.3196540071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/332.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/333.prim_prince_test.637163083 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 3179995010 ps |
| CPU time | 60.31 seconds |
| Started | Sep 18 09:56:35 AM UTC 24 |
| Finished | Sep 18 09:57:51 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=637163083 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 333.prim_prince_test.637163083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/333.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/334.prim_prince_test.2635198933 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 3664979052 ps |
| CPU time | 67.12 seconds |
| Started | Sep 18 09:56:35 AM UTC 24 |
| Finished | Sep 18 09:58:00 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2635198933 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 334.prim_prince_test.2635198933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/334.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/335.prim_prince_test.2573925172 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 3186711262 ps |
| CPU time | 61.18 seconds |
| Started | Sep 18 09:56:36 AM UTC 24 |
| Finished | Sep 18 09:57:53 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2573925172 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 335.prim_prince_test.2573925172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/335.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/336.prim_prince_test.893512278 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 1791346849 ps |
| CPU time | 34.78 seconds |
| Started | Sep 18 09:56:40 AM UTC 24 |
| Finished | Sep 18 09:57:24 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=893512278 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 336.prim_prince_test.893512278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/336.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/337.prim_prince_test.4174271133 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 2987120994 ps |
| CPU time | 57.34 seconds |
| Started | Sep 18 09:56:42 AM UTC 24 |
| Finished | Sep 18 09:57:55 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4174271133 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 337.prim_prince_test.4174271133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/337.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/338.prim_prince_test.1687442171 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 1447173175 ps |
| CPU time | 26.92 seconds |
| Started | Sep 18 09:56:43 AM UTC 24 |
| Finished | Sep 18 09:57:17 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1687442171 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 338.prim_prince_test.1687442171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/338.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/339.prim_prince_test.4260214087 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 1718719652 ps |
| CPU time | 33.71 seconds |
| Started | Sep 18 09:56:43 AM UTC 24 |
| Finished | Sep 18 09:57:25 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4260214087 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 339.prim_prince_test.4260214087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/339.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/34.prim_prince_test.1008305684 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 2833162873 ps |
| CPU time | 56.1 seconds |
| Started | Sep 18 09:47:40 AM UTC 24 |
| Finished | Sep 18 09:48:51 AM UTC 24 |
| Peak memory | 154652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1008305684 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 34.prim_prince_test.1008305684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/34.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/340.prim_prince_test.2938350775 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 2117335381 ps |
| CPU time | 41.31 seconds |
| Started | Sep 18 09:56:45 AM UTC 24 |
| Finished | Sep 18 09:57:37 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2938350775 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 340.prim_prince_test.2938350775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/340.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/341.prim_prince_test.3341801290 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 2307970555 ps |
| CPU time | 44.83 seconds |
| Started | Sep 18 09:56:49 AM UTC 24 |
| Finished | Sep 18 09:57:45 AM UTC 24 |
| Peak memory | 154652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3341801290 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 341.prim_prince_test.3341801290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/341.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/342.prim_prince_test.572138423 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 2069122367 ps |
| CPU time | 38.13 seconds |
| Started | Sep 18 09:56:49 AM UTC 24 |
| Finished | Sep 18 09:57:38 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=572138423 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 342.prim_prince_test.572138423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/342.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/343.prim_prince_test.2308951558 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 2860233082 ps |
| CPU time | 52.68 seconds |
| Started | Sep 18 09:56:52 AM UTC 24 |
| Finished | Sep 18 09:58:00 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2308951558 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 343.prim_prince_test.2308951558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/343.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/344.prim_prince_test.1620032976 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 2436496745 ps |
| CPU time | 45.26 seconds |
| Started | Sep 18 09:56:52 AM UTC 24 |
| Finished | Sep 18 09:57:50 AM UTC 24 |
| Peak memory | 154652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1620032976 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 344.prim_prince_test.1620032976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/344.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/345.prim_prince_test.3255514217 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 2118925560 ps |
| CPU time | 40.08 seconds |
| Started | Sep 18 09:56:53 AM UTC 24 |
| Finished | Sep 18 09:57:44 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3255514217 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 345.prim_prince_test.3255514217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/345.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/346.prim_prince_test.2371887603 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 760375425 ps |
| CPU time | 14.24 seconds |
| Started | Sep 18 09:56:53 AM UTC 24 |
| Finished | Sep 18 09:57:11 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2371887603 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 346.prim_prince_test.2371887603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/346.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/347.prim_prince_test.2969128524 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 3399978825 ps |
| CPU time | 64.31 seconds |
| Started | Sep 18 09:56:56 AM UTC 24 |
| Finished | Sep 18 09:58:17 AM UTC 24 |
| Peak memory | 154652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2969128524 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 347.prim_prince_test.2969128524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/347.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/348.prim_prince_test.3403023648 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 2064433001 ps |
| CPU time | 38.97 seconds |
| Started | Sep 18 09:56:56 AM UTC 24 |
| Finished | Sep 18 09:57:45 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3403023648 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 348.prim_prince_test.3403023648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/348.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/349.prim_prince_test.3105553513 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 1813950486 ps |
| CPU time | 34.11 seconds |
| Started | Sep 18 09:56:57 AM UTC 24 |
| Finished | Sep 18 09:57:41 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3105553513 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 349.prim_prince_test.3105553513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/349.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/35.prim_prince_test.3774281799 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 3262488685 ps |
| CPU time | 62.09 seconds |
| Started | Sep 18 09:47:44 AM UTC 24 |
| Finished | Sep 18 09:49:04 AM UTC 24 |
| Peak memory | 154596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3774281799 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 35.prim_prince_test.3774281799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/35.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/350.prim_prince_test.767003876 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 2971491210 ps |
| CPU time | 57.77 seconds |
| Started | Sep 18 09:57:02 AM UTC 24 |
| Finished | Sep 18 09:58:15 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=767003876 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 350.prim_prince_test.767003876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/350.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/351.prim_prince_test.2724519462 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 798569134 ps |
| CPU time | 16.16 seconds |
| Started | Sep 18 09:57:03 AM UTC 24 |
| Finished | Sep 18 09:57:24 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2724519462 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 351.prim_prince_test.2724519462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/351.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/352.prim_prince_test.4153657577 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 2400124012 ps |
| CPU time | 45.17 seconds |
| Started | Sep 18 09:57:12 AM UTC 24 |
| Finished | Sep 18 09:58:10 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4153657577 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 352.prim_prince_test.4153657577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/352.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/353.prim_prince_test.1019369517 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 2346063701 ps |
| CPU time | 42.98 seconds |
| Started | Sep 18 09:57:14 AM UTC 24 |
| Finished | Sep 18 09:58:09 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1019369517 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 353.prim_prince_test.1019369517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/353.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/354.prim_prince_test.3979533092 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 1955463062 ps |
| CPU time | 38.06 seconds |
| Started | Sep 18 09:57:18 AM UTC 24 |
| Finished | Sep 18 09:58:06 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3979533092 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 354.prim_prince_test.3979533092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/354.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/355.prim_prince_test.245440762 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 1194428434 ps |
| CPU time | 23.03 seconds |
| Started | Sep 18 09:57:19 AM UTC 24 |
| Finished | Sep 18 09:57:49 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=245440762 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 355.prim_prince_test.245440762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/355.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/356.prim_prince_test.2743834955 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 3272605620 ps |
| CPU time | 62.34 seconds |
| Started | Sep 18 09:57:19 AM UTC 24 |
| Finished | Sep 18 09:58:38 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2743834955 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 356.prim_prince_test.2743834955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/356.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/357.prim_prince_test.2913207385 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 2307887225 ps |
| CPU time | 42.76 seconds |
| Started | Sep 18 09:57:21 AM UTC 24 |
| Finished | Sep 18 09:58:16 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2913207385 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 357.prim_prince_test.2913207385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/357.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/358.prim_prince_test.4228504645 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 1462960911 ps |
| CPU time | 26.79 seconds |
| Started | Sep 18 09:57:21 AM UTC 24 |
| Finished | Sep 18 09:57:56 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4228504645 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 358.prim_prince_test.4228504645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/358.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/359.prim_prince_test.7625987 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 2399993010 ps |
| CPU time | 46.11 seconds |
| Started | Sep 18 09:57:22 AM UTC 24 |
| Finished | Sep 18 09:58:21 AM UTC 24 |
| Peak memory | 154652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7625987 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 359.prim_prince_test.7625987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/359.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/36.prim_prince_test.888167220 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 2097977782 ps |
| CPU time | 41.37 seconds |
| Started | Sep 18 09:47:44 AM UTC 24 |
| Finished | Sep 18 09:48:37 AM UTC 24 |
| Peak memory | 154556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=888167220 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 36.prim_prince_test.888167220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/36.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/360.prim_prince_test.2840182736 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 1144051913 ps |
| CPU time | 21.56 seconds |
| Started | Sep 18 09:57:24 AM UTC 24 |
| Finished | Sep 18 09:57:52 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2840182736 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 360.prim_prince_test.2840182736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/360.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/361.prim_prince_test.3041494116 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 1727922631 ps |
| CPU time | 31.23 seconds |
| Started | Sep 18 09:57:24 AM UTC 24 |
| Finished | Sep 18 09:58:04 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3041494116 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 361.prim_prince_test.3041494116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/361.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/362.prim_prince_test.779804778 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 2060288697 ps |
| CPU time | 37.88 seconds |
| Started | Sep 18 09:57:25 AM UTC 24 |
| Finished | Sep 18 09:58:14 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=779804778 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 362.prim_prince_test.779804778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/362.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/363.prim_prince_test.1638280110 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 3389365528 ps |
| CPU time | 64.6 seconds |
| Started | Sep 18 09:57:25 AM UTC 24 |
| Finished | Sep 18 09:58:46 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1638280110 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 363.prim_prince_test.1638280110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/363.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/364.prim_prince_test.217196770 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 1050795861 ps |
| CPU time | 20.41 seconds |
| Started | Sep 18 09:57:25 AM UTC 24 |
| Finished | Sep 18 09:57:51 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=217196770 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 364.prim_prince_test.217196770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/364.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/365.prim_prince_test.1051948644 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 2648412015 ps |
| CPU time | 48.87 seconds |
| Started | Sep 18 09:57:26 AM UTC 24 |
| Finished | Sep 18 09:58:29 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1051948644 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 365.prim_prince_test.1051948644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/365.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/366.prim_prince_test.612285242 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 1308467827 ps |
| CPU time | 24.9 seconds |
| Started | Sep 18 09:57:27 AM UTC 24 |
| Finished | Sep 18 09:57:59 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=612285242 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 366.prim_prince_test.612285242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/366.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/367.prim_prince_test.1092516717 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 1376336156 ps |
| CPU time | 26.12 seconds |
| Started | Sep 18 09:57:29 AM UTC 24 |
| Finished | Sep 18 09:58:02 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1092516717 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 367.prim_prince_test.1092516717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/367.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/368.prim_prince_test.4210820950 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 3581539915 ps |
| CPU time | 66.99 seconds |
| Started | Sep 18 09:57:33 AM UTC 24 |
| Finished | Sep 18 09:58:57 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4210820950 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 368.prim_prince_test.4210820950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/368.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/369.prim_prince_test.1499479730 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 3139252206 ps |
| CPU time | 60.62 seconds |
| Started | Sep 18 09:57:38 AM UTC 24 |
| Finished | Sep 18 09:58:54 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1499479730 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 369.prim_prince_test.1499479730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/369.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/37.prim_prince_test.2852155760 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 1935982012 ps |
| CPU time | 37.86 seconds |
| Started | Sep 18 09:47:46 AM UTC 24 |
| Finished | Sep 18 09:48:34 AM UTC 24 |
| Peak memory | 154596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2852155760 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 37.prim_prince_test.2852155760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/37.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/370.prim_prince_test.1527818906 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 3133390998 ps |
| CPU time | 58.45 seconds |
| Started | Sep 18 09:57:39 AM UTC 24 |
| Finished | Sep 18 09:58:53 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1527818906 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 370.prim_prince_test.1527818906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/370.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/371.prim_prince_test.224518284 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 2240729579 ps |
| CPU time | 43.78 seconds |
| Started | Sep 18 09:57:41 AM UTC 24 |
| Finished | Sep 18 09:58:36 AM UTC 24 |
| Peak memory | 154648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=224518284 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 371.prim_prince_test.224518284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/371.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/372.prim_prince_test.681156366 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 3408543573 ps |
| CPU time | 66.08 seconds |
| Started | Sep 18 09:57:42 AM UTC 24 |
| Finished | Sep 18 09:59:05 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=681156366 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 372.prim_prince_test.681156366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/372.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/373.prim_prince_test.1668365161 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 2373488953 ps |
| CPU time | 45.71 seconds |
| Started | Sep 18 09:57:45 AM UTC 24 |
| Finished | Sep 18 09:58:42 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1668365161 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 373.prim_prince_test.1668365161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/373.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/374.prim_prince_test.2140967615 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 3468491552 ps |
| CPU time | 66.82 seconds |
| Started | Sep 18 09:57:45 AM UTC 24 |
| Finished | Sep 18 09:59:08 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2140967615 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 374.prim_prince_test.2140967615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/374.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/375.prim_prince_test.1774022985 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 1025535679 ps |
| CPU time | 19.56 seconds |
| Started | Sep 18 09:57:47 AM UTC 24 |
| Finished | Sep 18 09:58:12 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1774022985 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 375.prim_prince_test.1774022985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/375.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/376.prim_prince_test.985161841 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 1198686767 ps |
| CPU time | 21.9 seconds |
| Started | Sep 18 09:57:47 AM UTC 24 |
| Finished | Sep 18 09:58:15 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=985161841 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 376.prim_prince_test.985161841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/376.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/377.prim_prince_test.1835700781 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 1460924752 ps |
| CPU time | 27.24 seconds |
| Started | Sep 18 09:57:47 AM UTC 24 |
| Finished | Sep 18 09:58:22 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1835700781 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 377.prim_prince_test.1835700781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/377.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/378.prim_prince_test.2307827176 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 3532520423 ps |
| CPU time | 64.85 seconds |
| Started | Sep 18 09:57:49 AM UTC 24 |
| Finished | Sep 18 09:59:12 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2307827176 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 378.prim_prince_test.2307827176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/378.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/379.prim_prince_test.2519241592 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 1124280198 ps |
| CPU time | 22.08 seconds |
| Started | Sep 18 09:57:52 AM UTC 24 |
| Finished | Sep 18 09:58:20 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2519241592 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 379.prim_prince_test.2519241592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/379.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/38.prim_prince_test.352509412 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 2079946528 ps |
| CPU time | 40.15 seconds |
| Started | Sep 18 09:47:50 AM UTC 24 |
| Finished | Sep 18 09:48:42 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=352509412 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 38.prim_prince_test.352509412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/38.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/380.prim_prince_test.1013228549 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 1582423466 ps |
| CPU time | 31 seconds |
| Started | Sep 18 09:57:52 AM UTC 24 |
| Finished | Sep 18 09:58:31 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1013228549 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 380.prim_prince_test.1013228549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/380.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/381.prim_prince_test.1344051122 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 1707090576 ps |
| CPU time | 32.69 seconds |
| Started | Sep 18 09:57:52 AM UTC 24 |
| Finished | Sep 18 09:58:33 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1344051122 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 381.prim_prince_test.1344051122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/381.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/382.prim_prince_test.857730411 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 1225167099 ps |
| CPU time | 24 seconds |
| Started | Sep 18 09:57:53 AM UTC 24 |
| Finished | Sep 18 09:58:24 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=857730411 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 382.prim_prince_test.857730411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/382.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/383.prim_prince_test.3210694080 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 3596967471 ps |
| CPU time | 69.09 seconds |
| Started | Sep 18 09:57:53 AM UTC 24 |
| Finished | Sep 18 09:59:20 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3210694080 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 383.prim_prince_test.3210694080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/383.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/384.prim_prince_test.2818739423 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 2944760844 ps |
| CPU time | 54.04 seconds |
| Started | Sep 18 09:57:54 AM UTC 24 |
| Finished | Sep 18 09:59:03 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2818739423 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 384.prim_prince_test.2818739423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/384.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/385.prim_prince_test.1421444984 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 2696168351 ps |
| CPU time | 50.11 seconds |
| Started | Sep 18 09:57:55 AM UTC 24 |
| Finished | Sep 18 09:59:00 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1421444984 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 385.prim_prince_test.1421444984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/385.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/386.prim_prince_test.701058228 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 2882328142 ps |
| CPU time | 52.89 seconds |
| Started | Sep 18 09:57:57 AM UTC 24 |
| Finished | Sep 18 09:59:05 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=701058228 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 386.prim_prince_test.701058228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/386.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/387.prim_prince_test.1043561660 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 3046476440 ps |
| CPU time | 55.62 seconds |
| Started | Sep 18 09:58:01 AM UTC 24 |
| Finished | Sep 18 09:59:12 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1043561660 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 387.prim_prince_test.1043561660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/387.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/388.prim_prince_test.3757951976 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 2438979387 ps |
| CPU time | 44.35 seconds |
| Started | Sep 18 09:58:01 AM UTC 24 |
| Finished | Sep 18 09:58:58 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3757951976 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 388.prim_prince_test.3757951976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/388.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/389.prim_prince_test.4288050049 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 2702455705 ps |
| CPU time | 51.22 seconds |
| Started | Sep 18 09:58:02 AM UTC 24 |
| Finished | Sep 18 09:59:07 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4288050049 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 389.prim_prince_test.4288050049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/389.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/39.prim_prince_test.1386796898 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 2393483620 ps |
| CPU time | 46.51 seconds |
| Started | Sep 18 09:47:52 AM UTC 24 |
| Finished | Sep 18 09:48:52 AM UTC 24 |
| Peak memory | 154660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1386796898 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 39.prim_prince_test.1386796898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/39.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/390.prim_prince_test.1811036472 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 2454252680 ps |
| CPU time | 47.83 seconds |
| Started | Sep 18 09:58:03 AM UTC 24 |
| Finished | Sep 18 09:59:03 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1811036472 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 390.prim_prince_test.1811036472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/390.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/391.prim_prince_test.242513851 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 2592382380 ps |
| CPU time | 47.42 seconds |
| Started | Sep 18 09:58:05 AM UTC 24 |
| Finished | Sep 18 09:59:06 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=242513851 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 391.prim_prince_test.242513851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/391.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/392.prim_prince_test.29046999 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 1227617037 ps |
| CPU time | 22.71 seconds |
| Started | Sep 18 09:58:07 AM UTC 24 |
| Finished | Sep 18 09:58:37 AM UTC 24 |
| Peak memory | 154588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29046999 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 392.prim_prince_test.29046999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/392.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/393.prim_prince_test.1347958784 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 3719932873 ps |
| CPU time | 67.88 seconds |
| Started | Sep 18 09:58:09 AM UTC 24 |
| Finished | Sep 18 09:59:36 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1347958784 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 393.prim_prince_test.1347958784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/393.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/394.prim_prince_test.3384434092 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 1108706107 ps |
| CPU time | 21.16 seconds |
| Started | Sep 18 09:58:10 AM UTC 24 |
| Finished | Sep 18 09:58:38 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3384434092 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 394.prim_prince_test.3384434092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/394.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/395.prim_prince_test.254625879 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 1127656670 ps |
| CPU time | 22.12 seconds |
| Started | Sep 18 09:58:13 AM UTC 24 |
| Finished | Sep 18 09:58:41 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=254625879 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 395.prim_prince_test.254625879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/395.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/396.prim_prince_test.1455885397 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 2018502492 ps |
| CPU time | 36.97 seconds |
| Started | Sep 18 09:58:15 AM UTC 24 |
| Finished | Sep 18 09:59:02 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1455885397 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 396.prim_prince_test.1455885397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/396.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/397.prim_prince_test.1254568122 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 1641862727 ps |
| CPU time | 32 seconds |
| Started | Sep 18 09:58:16 AM UTC 24 |
| Finished | Sep 18 09:58:57 AM UTC 24 |
| Peak memory | 154484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1254568122 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 397.prim_prince_test.1254568122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/397.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/398.prim_prince_test.2151955187 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 2193378814 ps |
| CPU time | 39.84 seconds |
| Started | Sep 18 09:58:16 AM UTC 24 |
| Finished | Sep 18 09:59:08 AM UTC 24 |
| Peak memory | 154528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2151955187 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 398.prim_prince_test.2151955187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/398.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/399.prim_prince_test.446407015 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 3612418670 ps |
| CPU time | 69.31 seconds |
| Started | Sep 18 09:58:17 AM UTC 24 |
| Finished | Sep 18 09:59:44 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=446407015 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 399.prim_prince_test.446407015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/399.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/4.prim_prince_test.3766409351 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 2029769612 ps |
| CPU time | 41.98 seconds |
| Started | Sep 18 09:46:29 AM UTC 24 |
| Finished | Sep 18 09:47:24 AM UTC 24 |
| Peak memory | 154584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3766409351 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 4.prim_prince_test.3766409351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/4.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/40.prim_prince_test.483364720 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 3199249389 ps |
| CPU time | 62.06 seconds |
| Started | Sep 18 09:47:53 AM UTC 24 |
| Finished | Sep 18 09:49:12 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=483364720 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 40.prim_prince_test.483364720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/40.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/400.prim_prince_test.1913608877 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 1097904980 ps |
| CPU time | 20.62 seconds |
| Started | Sep 18 09:58:17 AM UTC 24 |
| Finished | Sep 18 09:58:44 AM UTC 24 |
| Peak memory | 154588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1913608877 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 400.prim_prince_test.1913608877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/400.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/401.prim_prince_test.2721425188 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 1708070843 ps |
| CPU time | 33.27 seconds |
| Started | Sep 18 09:58:21 AM UTC 24 |
| Finished | Sep 18 09:59:03 AM UTC 24 |
| Peak memory | 154588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2721425188 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 401.prim_prince_test.2721425188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/401.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/402.prim_prince_test.2877419324 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 2917075824 ps |
| CPU time | 56.46 seconds |
| Started | Sep 18 09:58:22 AM UTC 24 |
| Finished | Sep 18 09:59:33 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2877419324 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 402.prim_prince_test.2877419324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/402.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/403.prim_prince_test.667927409 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 2395318713 ps |
| CPU time | 46.13 seconds |
| Started | Sep 18 09:58:23 AM UTC 24 |
| Finished | Sep 18 09:59:21 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=667927409 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 403.prim_prince_test.667927409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/403.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/404.prim_prince_test.431865216 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 1760347840 ps |
| CPU time | 33.85 seconds |
| Started | Sep 18 09:58:25 AM UTC 24 |
| Finished | Sep 18 09:59:08 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=431865216 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 404.prim_prince_test.431865216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/404.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/405.prim_prince_test.2322827228 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 3640781224 ps |
| CPU time | 69.72 seconds |
| Started | Sep 18 09:58:29 AM UTC 24 |
| Finished | Sep 18 09:59:57 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2322827228 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 405.prim_prince_test.2322827228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/405.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/406.prim_prince_test.3688650311 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 2012868360 ps |
| CPU time | 38.74 seconds |
| Started | Sep 18 09:58:31 AM UTC 24 |
| Finished | Sep 18 09:59:20 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3688650311 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 406.prim_prince_test.3688650311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/406.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/407.prim_prince_test.1131230174 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 1236707619 ps |
| CPU time | 24.31 seconds |
| Started | Sep 18 09:58:34 AM UTC 24 |
| Finished | Sep 18 09:59:05 AM UTC 24 |
| Peak memory | 154584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1131230174 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 407.prim_prince_test.1131230174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/407.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/408.prim_prince_test.3865375641 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 897369507 ps |
| CPU time | 16.92 seconds |
| Started | Sep 18 09:58:38 AM UTC 24 |
| Finished | Sep 18 09:59:00 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3865375641 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 408.prim_prince_test.3865375641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/408.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/409.prim_prince_test.1380653643 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 759888109 ps |
| CPU time | 15.07 seconds |
| Started | Sep 18 09:58:38 AM UTC 24 |
| Finished | Sep 18 09:58:57 AM UTC 24 |
| Peak memory | 154588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1380653643 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 409.prim_prince_test.1380653643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/409.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/41.prim_prince_test.1238833417 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 1241652015 ps |
| CPU time | 24.55 seconds |
| Started | Sep 18 09:47:56 AM UTC 24 |
| Finished | Sep 18 09:48:28 AM UTC 24 |
| Peak memory | 154596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1238833417 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 41.prim_prince_test.1238833417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/41.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/410.prim_prince_test.4132875761 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 1541998537 ps |
| CPU time | 29.79 seconds |
| Started | Sep 18 09:58:39 AM UTC 24 |
| Finished | Sep 18 09:59:17 AM UTC 24 |
| Peak memory | 154588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4132875761 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 410.prim_prince_test.4132875761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/410.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/411.prim_prince_test.2852819240 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 2530958399 ps |
| CPU time | 46.4 seconds |
| Started | Sep 18 09:58:39 AM UTC 24 |
| Finished | Sep 18 09:59:38 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2852819240 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 411.prim_prince_test.2852819240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/411.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/412.prim_prince_test.1249595254 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 3456424573 ps |
| CPU time | 66.13 seconds |
| Started | Sep 18 09:58:42 AM UTC 24 |
| Finished | Sep 18 10:00:05 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1249595254 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 412.prim_prince_test.1249595254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/412.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/413.prim_prince_test.518448698 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 3409833857 ps |
| CPU time | 62.96 seconds |
| Started | Sep 18 09:58:44 AM UTC 24 |
| Finished | Sep 18 10:00:03 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=518448698 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 413.prim_prince_test.518448698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/413.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/414.prim_prince_test.2876104839 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 1893349178 ps |
| CPU time | 36.04 seconds |
| Started | Sep 18 09:58:45 AM UTC 24 |
| Finished | Sep 18 09:59:30 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2876104839 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 414.prim_prince_test.2876104839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/414.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/415.prim_prince_test.46246207 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 2077989909 ps |
| CPU time | 39.79 seconds |
| Started | Sep 18 09:58:48 AM UTC 24 |
| Finished | Sep 18 09:59:38 AM UTC 24 |
| Peak memory | 154588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=46246207 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 415.prim_prince_test.46246207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/415.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/416.prim_prince_test.598643443 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 2956354574 ps |
| CPU time | 55 seconds |
| Started | Sep 18 09:58:54 AM UTC 24 |
| Finished | Sep 18 10:00:04 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=598643443 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 416.prim_prince_test.598643443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/416.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/417.prim_prince_test.106457266 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 2130549671 ps |
| CPU time | 38.81 seconds |
| Started | Sep 18 09:58:55 AM UTC 24 |
| Finished | Sep 18 09:59:45 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=106457266 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 417.prim_prince_test.106457266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/417.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/418.prim_prince_test.1776145820 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 1195281110 ps |
| CPU time | 22.94 seconds |
| Started | Sep 18 09:58:59 AM UTC 24 |
| Finished | Sep 18 09:59:28 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1776145820 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 418.prim_prince_test.1776145820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/418.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/419.prim_prince_test.918080510 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 2398489343 ps |
| CPU time | 44.23 seconds |
| Started | Sep 18 09:58:59 AM UTC 24 |
| Finished | Sep 18 09:59:55 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=918080510 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 419.prim_prince_test.918080510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/419.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/42.prim_prince_test.2886545495 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 2078544398 ps |
| CPU time | 39.9 seconds |
| Started | Sep 18 09:47:58 AM UTC 24 |
| Finished | Sep 18 09:48:50 AM UTC 24 |
| Peak memory | 154596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2886545495 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 42.prim_prince_test.2886545495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/42.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/420.prim_prince_test.3491568016 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 2371563047 ps |
| CPU time | 43.11 seconds |
| Started | Sep 18 09:58:59 AM UTC 24 |
| Finished | Sep 18 09:59:54 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3491568016 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 420.prim_prince_test.3491568016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/420.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/421.prim_prince_test.3934592706 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 3157835587 ps |
| CPU time | 60.46 seconds |
| Started | Sep 18 09:58:59 AM UTC 24 |
| Finished | Sep 18 10:00:15 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3934592706 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 421.prim_prince_test.3934592706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/421.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/422.prim_prince_test.2870182960 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 1607546945 ps |
| CPU time | 29.84 seconds |
| Started | Sep 18 09:59:01 AM UTC 24 |
| Finished | Sep 18 09:59:39 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2870182960 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 422.prim_prince_test.2870182960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/422.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/423.prim_prince_test.3346683186 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 2919703893 ps |
| CPU time | 55.9 seconds |
| Started | Sep 18 09:59:01 AM UTC 24 |
| Finished | Sep 18 10:00:11 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3346683186 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 423.prim_prince_test.3346683186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/423.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/424.prim_prince_test.117748639 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 2201131861 ps |
| CPU time | 41.54 seconds |
| Started | Sep 18 09:59:03 AM UTC 24 |
| Finished | Sep 18 09:59:56 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=117748639 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 424.prim_prince_test.117748639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/424.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/425.prim_prince_test.3591187700 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 1847555239 ps |
| CPU time | 35.62 seconds |
| Started | Sep 18 09:59:03 AM UTC 24 |
| Finished | Sep 18 09:59:48 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3591187700 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 425.prim_prince_test.3591187700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/425.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/426.prim_prince_test.3067920679 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 3182630982 ps |
| CPU time | 61.85 seconds |
| Started | Sep 18 09:59:05 AM UTC 24 |
| Finished | Sep 18 10:00:22 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3067920679 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 426.prim_prince_test.3067920679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/426.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/427.prim_prince_test.237482490 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 2359692285 ps |
| CPU time | 43.57 seconds |
| Started | Sep 18 09:59:05 AM UTC 24 |
| Finished | Sep 18 10:00:00 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=237482490 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 427.prim_prince_test.237482490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/427.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/428.prim_prince_test.305099444 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 2254808350 ps |
| CPU time | 41.85 seconds |
| Started | Sep 18 09:59:06 AM UTC 24 |
| Finished | Sep 18 10:00:00 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=305099444 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 428.prim_prince_test.305099444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/428.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/429.prim_prince_test.2349367224 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 1048903079 ps |
| CPU time | 20.65 seconds |
| Started | Sep 18 09:59:06 AM UTC 24 |
| Finished | Sep 18 09:59:33 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2349367224 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 429.prim_prince_test.2349367224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/429.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/43.prim_prince_test.3355916904 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 3384137474 ps |
| CPU time | 65.47 seconds |
| Started | Sep 18 09:47:58 AM UTC 24 |
| Finished | Sep 18 09:49:21 AM UTC 24 |
| Peak memory | 154660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3355916904 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 43.prim_prince_test.3355916904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/43.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/430.prim_prince_test.2903651693 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 3221205444 ps |
| CPU time | 59.57 seconds |
| Started | Sep 18 09:59:06 AM UTC 24 |
| Finished | Sep 18 10:00:22 AM UTC 24 |
| Peak memory | 154652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2903651693 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 430.prim_prince_test.2903651693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/430.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/431.prim_prince_test.1056491014 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 2629354572 ps |
| CPU time | 50.38 seconds |
| Started | Sep 18 09:59:06 AM UTC 24 |
| Finished | Sep 18 10:00:10 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1056491014 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 431.prim_prince_test.1056491014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/431.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/432.prim_prince_test.3950806601 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 2955395721 ps |
| CPU time | 53.36 seconds |
| Started | Sep 18 09:59:07 AM UTC 24 |
| Finished | Sep 18 10:00:16 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3950806601 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 432.prim_prince_test.3950806601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/432.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/433.prim_prince_test.3471381870 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 1963426729 ps |
| CPU time | 37.94 seconds |
| Started | Sep 18 09:59:09 AM UTC 24 |
| Finished | Sep 18 09:59:57 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3471381870 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 433.prim_prince_test.3471381870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/433.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/434.prim_prince_test.1291430905 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 1273488595 ps |
| CPU time | 24.78 seconds |
| Started | Sep 18 09:59:09 AM UTC 24 |
| Finished | Sep 18 09:59:40 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1291430905 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 434.prim_prince_test.1291430905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/434.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/435.prim_prince_test.3038009334 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 1590558647 ps |
| CPU time | 29.87 seconds |
| Started | Sep 18 09:59:10 AM UTC 24 |
| Finished | Sep 18 09:59:48 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3038009334 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 435.prim_prince_test.3038009334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/435.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/436.prim_prince_test.873088048 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 994836234 ps |
| CPU time | 19.17 seconds |
| Started | Sep 18 09:59:12 AM UTC 24 |
| Finished | Sep 18 09:59:37 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=873088048 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 436.prim_prince_test.873088048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/436.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/437.prim_prince_test.75123545 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 2286102136 ps |
| CPU time | 44.03 seconds |
| Started | Sep 18 09:59:13 AM UTC 24 |
| Finished | Sep 18 10:00:09 AM UTC 24 |
| Peak memory | 154652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=75123545 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 437.prim_prince_test.75123545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/437.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/438.prim_prince_test.1885226735 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 2434697602 ps |
| CPU time | 45.34 seconds |
| Started | Sep 18 09:59:18 AM UTC 24 |
| Finished | Sep 18 10:00:15 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1885226735 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 438.prim_prince_test.1885226735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/438.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/439.prim_prince_test.3099336278 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 838161486 ps |
| CPU time | 15.86 seconds |
| Started | Sep 18 09:59:21 AM UTC 24 |
| Finished | Sep 18 09:59:42 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3099336278 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 439.prim_prince_test.3099336278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/439.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/44.prim_prince_test.1603210529 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 3588214946 ps |
| CPU time | 69.28 seconds |
| Started | Sep 18 09:47:59 AM UTC 24 |
| Finished | Sep 18 09:49:27 AM UTC 24 |
| Peak memory | 154660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1603210529 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 44.prim_prince_test.1603210529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/44.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/440.prim_prince_test.1720361963 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 2475508029 ps |
| CPU time | 47.11 seconds |
| Started | Sep 18 09:59:21 AM UTC 24 |
| Finished | Sep 18 10:00:21 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1720361963 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 440.prim_prince_test.1720361963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/440.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/441.prim_prince_test.4052907117 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 3753987466 ps |
| CPU time | 70.51 seconds |
| Started | Sep 18 09:59:22 AM UTC 24 |
| Finished | Sep 18 10:00:51 AM UTC 24 |
| Peak memory | 154652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4052907117 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 441.prim_prince_test.4052907117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/441.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/442.prim_prince_test.4118803775 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 1531777133 ps |
| CPU time | 29.36 seconds |
| Started | Sep 18 09:59:29 AM UTC 24 |
| Finished | Sep 18 10:00:07 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4118803775 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 442.prim_prince_test.4118803775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/442.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/443.prim_prince_test.975650414 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 2228250489 ps |
| CPU time | 42.6 seconds |
| Started | Sep 18 09:59:31 AM UTC 24 |
| Finished | Sep 18 10:00:25 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=975650414 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 443.prim_prince_test.975650414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/443.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/444.prim_prince_test.556999516 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 2975424450 ps |
| CPU time | 54.9 seconds |
| Started | Sep 18 09:59:34 AM UTC 24 |
| Finished | Sep 18 10:00:44 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=556999516 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 444.prim_prince_test.556999516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/444.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/445.prim_prince_test.4026597875 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 1617377128 ps |
| CPU time | 30.54 seconds |
| Started | Sep 18 09:59:34 AM UTC 24 |
| Finished | Sep 18 10:00:13 AM UTC 24 |
| Peak memory | 154588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4026597875 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 445.prim_prince_test.4026597875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/445.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/446.prim_prince_test.4232317395 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 1058376372 ps |
| CPU time | 21.04 seconds |
| Started | Sep 18 09:59:37 AM UTC 24 |
| Finished | Sep 18 10:00:04 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4232317395 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 446.prim_prince_test.4232317395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/446.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/447.prim_prince_test.2649518436 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 2234537162 ps |
| CPU time | 41.31 seconds |
| Started | Sep 18 09:59:38 AM UTC 24 |
| Finished | Sep 18 10:00:31 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2649518436 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 447.prim_prince_test.2649518436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/447.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/448.prim_prince_test.2793799013 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 3186805587 ps |
| CPU time | 57.99 seconds |
| Started | Sep 18 09:59:39 AM UTC 24 |
| Finished | Sep 18 10:00:54 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2793799013 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 448.prim_prince_test.2793799013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/448.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/449.prim_prince_test.100895948 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 1844484060 ps |
| CPU time | 35.79 seconds |
| Started | Sep 18 09:59:39 AM UTC 24 |
| Finished | Sep 18 10:00:25 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=100895948 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 449.prim_prince_test.100895948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/449.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/45.prim_prince_test.2617172372 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 3466861305 ps |
| CPU time | 66.54 seconds |
| Started | Sep 18 09:47:59 AM UTC 24 |
| Finished | Sep 18 09:49:25 AM UTC 24 |
| Peak memory | 154660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2617172372 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 45.prim_prince_test.2617172372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/45.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/450.prim_prince_test.1875370516 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 2285393708 ps |
| CPU time | 43.37 seconds |
| Started | Sep 18 09:59:41 AM UTC 24 |
| Finished | Sep 18 10:00:36 AM UTC 24 |
| Peak memory | 156108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1875370516 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 450.prim_prince_test.1875370516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/450.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/451.prim_prince_test.4018426172 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 2703342262 ps |
| CPU time | 49.31 seconds |
| Started | Sep 18 09:59:41 AM UTC 24 |
| Finished | Sep 18 10:00:44 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4018426172 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 451.prim_prince_test.4018426172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/451.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/452.prim_prince_test.777334905 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 2190189154 ps |
| CPU time | 40.71 seconds |
| Started | Sep 18 09:59:43 AM UTC 24 |
| Finished | Sep 18 10:00:35 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=777334905 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 452.prim_prince_test.777334905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/452.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/453.prim_prince_test.1088128717 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 802054384 ps |
| CPU time | 16.03 seconds |
| Started | Sep 18 09:59:45 AM UTC 24 |
| Finished | Sep 18 10:00:06 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1088128717 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 453.prim_prince_test.1088128717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/453.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/454.prim_prince_test.2768355367 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 2365077132 ps |
| CPU time | 45.45 seconds |
| Started | Sep 18 09:59:46 AM UTC 24 |
| Finished | Sep 18 10:00:44 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2768355367 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 454.prim_prince_test.2768355367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/454.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/455.prim_prince_test.1369919740 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 2923797581 ps |
| CPU time | 53.81 seconds |
| Started | Sep 18 09:59:50 AM UTC 24 |
| Finished | Sep 18 10:00:59 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1369919740 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 455.prim_prince_test.1369919740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/455.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/456.prim_prince_test.1427677704 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 3181041781 ps |
| CPU time | 59 seconds |
| Started | Sep 18 09:59:50 AM UTC 24 |
| Finished | Sep 18 10:01:05 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1427677704 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 456.prim_prince_test.1427677704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/456.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/457.prim_prince_test.2234725206 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 2608206790 ps |
| CPU time | 50.76 seconds |
| Started | Sep 18 09:59:55 AM UTC 24 |
| Finished | Sep 18 10:00:59 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2234725206 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 457.prim_prince_test.2234725206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/457.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/458.prim_prince_test.2950265063 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 2407683158 ps |
| CPU time | 46.51 seconds |
| Started | Sep 18 09:59:56 AM UTC 24 |
| Finished | Sep 18 10:00:55 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2950265063 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 458.prim_prince_test.2950265063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/458.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/459.prim_prince_test.3274363527 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 1311628387 ps |
| CPU time | 25.23 seconds |
| Started | Sep 18 09:59:57 AM UTC 24 |
| Finished | Sep 18 10:00:30 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3274363527 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 459.prim_prince_test.3274363527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/459.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/46.prim_prince_test.2269629986 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 2075272142 ps |
| CPU time | 40.07 seconds |
| Started | Sep 18 09:48:02 AM UTC 24 |
| Finished | Sep 18 09:48:54 AM UTC 24 |
| Peak memory | 154596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2269629986 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 46.prim_prince_test.2269629986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/46.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/460.prim_prince_test.721732 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 1164299298 ps |
| CPU time | 21.85 seconds |
| Started | Sep 18 09:59:57 AM UTC 24 |
| Finished | Sep 18 10:00:26 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=721732 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 460.prim_prince_test.721732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/460.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/461.prim_prince_test.3454604491 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 2999318387 ps |
| CPU time | 59.03 seconds |
| Started | Sep 18 09:59:57 AM UTC 24 |
| Finished | Sep 18 10:01:11 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3454604491 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 461.prim_prince_test.3454604491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/461.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/462.prim_prince_test.378026203 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 1079696779 ps |
| CPU time | 21.12 seconds |
| Started | Sep 18 10:00:01 AM UTC 24 |
| Finished | Sep 18 10:00:32 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=378026203 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 462.prim_prince_test.378026203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/462.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/463.prim_prince_test.2224154823 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 2068417340 ps |
| CPU time | 39.23 seconds |
| Started | Sep 18 10:00:02 AM UTC 24 |
| Finished | Sep 18 10:00:56 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2224154823 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 463.prim_prince_test.2224154823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/463.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/464.prim_prince_test.335507341 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 2427346458 ps |
| CPU time | 46.3 seconds |
| Started | Sep 18 10:00:08 AM UTC 24 |
| Finished | Sep 18 10:01:07 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=335507341 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 464.prim_prince_test.335507341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/464.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/465.prim_prince_test.643247524 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 2652360152 ps |
| CPU time | 48.81 seconds |
| Started | Sep 18 10:00:08 AM UTC 24 |
| Finished | Sep 18 10:01:11 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=643247524 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 465.prim_prince_test.643247524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/465.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/466.prim_prince_test.565145825 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 1481403304 ps |
| CPU time | 28.78 seconds |
| Started | Sep 18 10:00:08 AM UTC 24 |
| Finished | Sep 18 10:00:45 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=565145825 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 466.prim_prince_test.565145825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/466.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/467.prim_prince_test.1728235496 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 2347629475 ps |
| CPU time | 44.99 seconds |
| Started | Sep 18 10:00:08 AM UTC 24 |
| Finished | Sep 18 10:01:06 AM UTC 24 |
| Peak memory | 154416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1728235496 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 467.prim_prince_test.1728235496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/467.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/468.prim_prince_test.3896414739 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 3323873473 ps |
| CPU time | 64.64 seconds |
| Started | Sep 18 10:00:08 AM UTC 24 |
| Finished | Sep 18 10:01:30 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3896414739 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 468.prim_prince_test.3896414739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/468.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/469.prim_prince_test.2021314743 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 2920928957 ps |
| CPU time | 56.19 seconds |
| Started | Sep 18 10:00:08 AM UTC 24 |
| Finished | Sep 18 10:01:19 AM UTC 24 |
| Peak memory | 154456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2021314743 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 469.prim_prince_test.2021314743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/469.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/47.prim_prince_test.105148524 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 1794935029 ps |
| CPU time | 34.42 seconds |
| Started | Sep 18 09:48:12 AM UTC 24 |
| Finished | Sep 18 09:48:56 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=105148524 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 47.prim_prince_test.105148524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/47.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/470.prim_prince_test.2208766317 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 1142334187 ps |
| CPU time | 22.05 seconds |
| Started | Sep 18 10:00:10 AM UTC 24 |
| Finished | Sep 18 10:00:39 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2208766317 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 470.prim_prince_test.2208766317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/470.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/471.prim_prince_test.3805406403 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 2675113834 ps |
| CPU time | 49.22 seconds |
| Started | Sep 18 10:00:11 AM UTC 24 |
| Finished | Sep 18 10:01:15 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3805406403 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 471.prim_prince_test.3805406403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/471.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/472.prim_prince_test.587335117 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 1334310449 ps |
| CPU time | 25.24 seconds |
| Started | Sep 18 10:00:12 AM UTC 24 |
| Finished | Sep 18 10:00:45 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=587335117 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 472.prim_prince_test.587335117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/472.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/473.prim_prince_test.3646981105 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 1251385675 ps |
| CPU time | 23.9 seconds |
| Started | Sep 18 10:00:13 AM UTC 24 |
| Finished | Sep 18 10:00:45 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3646981105 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 473.prim_prince_test.3646981105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/473.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/474.prim_prince_test.2174835612 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 1695820893 ps |
| CPU time | 31.39 seconds |
| Started | Sep 18 10:00:14 AM UTC 24 |
| Finished | Sep 18 10:00:55 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2174835612 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 474.prim_prince_test.2174835612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/474.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/475.prim_prince_test.1784262176 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 2907559473 ps |
| CPU time | 57.26 seconds |
| Started | Sep 18 10:00:16 AM UTC 24 |
| Finished | Sep 18 10:01:28 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1784262176 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 475.prim_prince_test.1784262176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/475.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/476.prim_prince_test.3831608251 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 995227053 ps |
| CPU time | 19.33 seconds |
| Started | Sep 18 10:00:17 AM UTC 24 |
| Finished | Sep 18 10:00:42 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3831608251 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 476.prim_prince_test.3831608251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/476.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/477.prim_prince_test.2294696096 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 1223339836 ps |
| CPU time | 23.64 seconds |
| Started | Sep 18 10:00:17 AM UTC 24 |
| Finished | Sep 18 10:00:47 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2294696096 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 477.prim_prince_test.2294696096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/477.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/478.prim_prince_test.1609619467 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 3466676524 ps |
| CPU time | 64.95 seconds |
| Started | Sep 18 10:00:21 AM UTC 24 |
| Finished | Sep 18 10:01:45 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1609619467 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 478.prim_prince_test.1609619467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/478.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/479.prim_prince_test.2979326584 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 1263195201 ps |
| CPU time | 24.26 seconds |
| Started | Sep 18 10:00:21 AM UTC 24 |
| Finished | Sep 18 10:00:53 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2979326584 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 479.prim_prince_test.2979326584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/479.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/48.prim_prince_test.2909439713 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 2808032275 ps |
| CPU time | 54.49 seconds |
| Started | Sep 18 09:48:13 AM UTC 24 |
| Finished | Sep 18 09:49:22 AM UTC 24 |
| Peak memory | 154660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2909439713 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 48.prim_prince_test.2909439713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/48.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/480.prim_prince_test.573312997 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 1874068491 ps |
| CPU time | 35.48 seconds |
| Started | Sep 18 10:00:23 AM UTC 24 |
| Finished | Sep 18 10:01:09 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=573312997 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 480.prim_prince_test.573312997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/480.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/481.prim_prince_test.1194622895 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 3694383697 ps |
| CPU time | 74.04 seconds |
| Started | Sep 18 10:00:24 AM UTC 24 |
| Finished | Sep 18 10:01:59 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1194622895 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 481.prim_prince_test.1194622895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/481.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/482.prim_prince_test.1367231447 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 2490396538 ps |
| CPU time | 49.12 seconds |
| Started | Sep 18 10:00:26 AM UTC 24 |
| Finished | Sep 18 10:01:28 AM UTC 24 |
| Peak memory | 154660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1367231447 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 482.prim_prince_test.1367231447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/482.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/483.prim_prince_test.3249899608 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 1753021425 ps |
| CPU time | 32.98 seconds |
| Started | Sep 18 10:00:26 AM UTC 24 |
| Finished | Sep 18 10:01:08 AM UTC 24 |
| Peak memory | 154596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3249899608 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 483.prim_prince_test.3249899608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/483.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/484.prim_prince_test.2980108493 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 2968932549 ps |
| CPU time | 54.34 seconds |
| Started | Sep 18 10:00:26 AM UTC 24 |
| Finished | Sep 18 10:01:36 AM UTC 24 |
| Peak memory | 154660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2980108493 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 484.prim_prince_test.2980108493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/484.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/485.prim_prince_test.1445935961 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 2942278351 ps |
| CPU time | 55.11 seconds |
| Started | Sep 18 10:00:30 AM UTC 24 |
| Finished | Sep 18 10:01:41 AM UTC 24 |
| Peak memory | 154660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1445935961 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 485.prim_prince_test.1445935961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/485.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/486.prim_prince_test.1247424632 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 1169593002 ps |
| CPU time | 21.78 seconds |
| Started | Sep 18 10:00:31 AM UTC 24 |
| Finished | Sep 18 10:01:00 AM UTC 24 |
| Peak memory | 154584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1247424632 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 486.prim_prince_test.1247424632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/486.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/487.prim_prince_test.1139124058 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 2535751443 ps |
| CPU time | 48.04 seconds |
| Started | Sep 18 10:00:34 AM UTC 24 |
| Finished | Sep 18 10:01:35 AM UTC 24 |
| Peak memory | 154660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1139124058 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 487.prim_prince_test.1139124058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/487.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/488.prim_prince_test.4174291993 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 1362127880 ps |
| CPU time | 26.41 seconds |
| Started | Sep 18 10:00:36 AM UTC 24 |
| Finished | Sep 18 10:01:10 AM UTC 24 |
| Peak memory | 154564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4174291993 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 488.prim_prince_test.4174291993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/488.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/489.prim_prince_test.2153474360 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 3484068310 ps |
| CPU time | 69.34 seconds |
| Started | Sep 18 10:00:36 AM UTC 24 |
| Finished | Sep 18 10:02:05 AM UTC 24 |
| Peak memory | 154660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2153474360 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 489.prim_prince_test.2153474360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/489.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/49.prim_prince_test.4033141635 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 2759999407 ps |
| CPU time | 52.99 seconds |
| Started | Sep 18 09:48:17 AM UTC 24 |
| Finished | Sep 18 09:49:24 AM UTC 24 |
| Peak memory | 154660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4033141635 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 49.prim_prince_test.4033141635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/49.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/490.prim_prince_test.298889880 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 3324193287 ps |
| CPU time | 63.73 seconds |
| Started | Sep 18 10:00:37 AM UTC 24 |
| Finished | Sep 18 10:02:00 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=298889880 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 490.prim_prince_test.298889880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/490.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/491.prim_prince_test.2715244115 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 1048107286 ps |
| CPU time | 20.17 seconds |
| Started | Sep 18 10:00:39 AM UTC 24 |
| Finished | Sep 18 10:01:05 AM UTC 24 |
| Peak memory | 154596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2715244115 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 491.prim_prince_test.2715244115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/491.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/492.prim_prince_test.237953757 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 3601702891 ps |
| CPU time | 69.16 seconds |
| Started | Sep 18 10:00:42 AM UTC 24 |
| Finished | Sep 18 10:02:13 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=237953757 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 492.prim_prince_test.237953757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/492.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/493.prim_prince_test.1335421297 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 1349311296 ps |
| CPU time | 27.1 seconds |
| Started | Sep 18 10:00:45 AM UTC 24 |
| Finished | Sep 18 10:01:19 AM UTC 24 |
| Peak memory | 154596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1335421297 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 493.prim_prince_test.1335421297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/493.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/494.prim_prince_test.3207041403 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 2564342302 ps |
| CPU time | 48.53 seconds |
| Started | Sep 18 10:00:45 AM UTC 24 |
| Finished | Sep 18 10:01:48 AM UTC 24 |
| Peak memory | 154660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3207041403 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 494.prim_prince_test.3207041403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/494.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/495.prim_prince_test.3134031123 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 2051835464 ps |
| CPU time | 38.4 seconds |
| Started | Sep 18 10:00:45 AM UTC 24 |
| Finished | Sep 18 10:01:35 AM UTC 24 |
| Peak memory | 154596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3134031123 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 495.prim_prince_test.3134031123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/495.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/496.prim_prince_test.285180337 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 3645591138 ps |
| CPU time | 74.56 seconds |
| Started | Sep 18 10:00:46 AM UTC 24 |
| Finished | Sep 18 10:02:25 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=285180337 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 496.prim_prince_test.285180337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/496.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/497.prim_prince_test.4069024444 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 2130835108 ps |
| CPU time | 44.01 seconds |
| Started | Sep 18 10:00:47 AM UTC 24 |
| Finished | Sep 18 10:01:43 AM UTC 24 |
| Peak memory | 154596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4069024444 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 497.prim_prince_test.4069024444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/497.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/498.prim_prince_test.515027626 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 1961666890 ps |
| CPU time | 35.8 seconds |
| Started | Sep 18 10:00:47 AM UTC 24 |
| Finished | Sep 18 10:01:33 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=515027626 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 498.prim_prince_test.515027626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/498.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/499.prim_prince_test.3037055055 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 868961261 ps |
| CPU time | 16.69 seconds |
| Started | Sep 18 10:00:49 AM UTC 24 |
| Finished | Sep 18 10:01:11 AM UTC 24 |
| Peak memory | 154588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3037055055 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 499.prim_prince_test.3037055055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/499.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/5.prim_prince_test.3239901388 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 1254589414 ps |
| CPU time | 25.57 seconds |
| Started | Sep 18 09:46:29 AM UTC 24 |
| Finished | Sep 18 09:47:03 AM UTC 24 |
| Peak memory | 154584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3239901388 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 5.prim_prince_test.3239901388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/5.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/50.prim_prince_test.411304819 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 3279896423 ps |
| CPU time | 63.44 seconds |
| Started | Sep 18 09:48:19 AM UTC 24 |
| Finished | Sep 18 09:49:39 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=411304819 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 50.prim_prince_test.411304819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/50.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/51.prim_prince_test.1271846414 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 1641340977 ps |
| CPU time | 32.67 seconds |
| Started | Sep 18 09:48:19 AM UTC 24 |
| Finished | Sep 18 09:49:01 AM UTC 24 |
| Peak memory | 154596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1271846414 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 51.prim_prince_test.1271846414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/51.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/52.prim_prince_test.1892289389 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 1952658921 ps |
| CPU time | 37.75 seconds |
| Started | Sep 18 09:48:24 AM UTC 24 |
| Finished | Sep 18 09:49:12 AM UTC 24 |
| Peak memory | 154596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1892289389 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 52.prim_prince_test.1892289389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/52.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/53.prim_prince_test.3989512523 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 2573250351 ps |
| CPU time | 48.3 seconds |
| Started | Sep 18 09:48:28 AM UTC 24 |
| Finished | Sep 18 09:49:30 AM UTC 24 |
| Peak memory | 154660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3989512523 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 53.prim_prince_test.3989512523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/53.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/54.prim_prince_test.2276244922 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 2281819443 ps |
| CPU time | 44.27 seconds |
| Started | Sep 18 09:48:29 AM UTC 24 |
| Finished | Sep 18 09:49:26 AM UTC 24 |
| Peak memory | 154660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2276244922 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 54.prim_prince_test.2276244922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/54.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/55.prim_prince_test.3570044166 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 2269952456 ps |
| CPU time | 42.84 seconds |
| Started | Sep 18 09:48:33 AM UTC 24 |
| Finished | Sep 18 09:49:28 AM UTC 24 |
| Peak memory | 154660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3570044166 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 55.prim_prince_test.3570044166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/55.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/56.prim_prince_test.1382516605 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 1962175679 ps |
| CPU time | 37.22 seconds |
| Started | Sep 18 09:48:35 AM UTC 24 |
| Finished | Sep 18 09:49:23 AM UTC 24 |
| Peak memory | 154596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1382516605 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 56.prim_prince_test.1382516605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/56.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/57.prim_prince_test.3764115285 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 2415104614 ps |
| CPU time | 47 seconds |
| Started | Sep 18 09:48:37 AM UTC 24 |
| Finished | Sep 18 09:49:37 AM UTC 24 |
| Peak memory | 154660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3764115285 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 57.prim_prince_test.3764115285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/57.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/58.prim_prince_test.3842548800 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 3082621582 ps |
| CPU time | 59.46 seconds |
| Started | Sep 18 09:48:40 AM UTC 24 |
| Finished | Sep 18 09:49:56 AM UTC 24 |
| Peak memory | 154660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3842548800 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 58.prim_prince_test.3842548800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/58.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/59.prim_prince_test.1594944960 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 2816181602 ps |
| CPU time | 54.98 seconds |
| Started | Sep 18 09:48:42 AM UTC 24 |
| Finished | Sep 18 09:49:53 AM UTC 24 |
| Peak memory | 154660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1594944960 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 59.prim_prince_test.1594944960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/59.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/6.prim_prince_test.3996235207 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 1332266314 ps |
| CPU time | 27.5 seconds |
| Started | Sep 18 09:46:30 AM UTC 24 |
| Finished | Sep 18 09:47:06 AM UTC 24 |
| Peak memory | 154584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3996235207 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 6.prim_prince_test.3996235207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/6.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/60.prim_prince_test.3056959378 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 2728487945 ps |
| CPU time | 52.47 seconds |
| Started | Sep 18 09:48:46 AM UTC 24 |
| Finished | Sep 18 09:49:54 AM UTC 24 |
| Peak memory | 154660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3056959378 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 60.prim_prince_test.3056959378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/60.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/61.prim_prince_test.205314201 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 1894206282 ps |
| CPU time | 36.91 seconds |
| Started | Sep 18 09:48:49 AM UTC 24 |
| Finished | Sep 18 09:49:37 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=205314201 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 61.prim_prince_test.205314201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/61.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/62.prim_prince_test.393337930 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 2509530659 ps |
| CPU time | 48.38 seconds |
| Started | Sep 18 09:48:51 AM UTC 24 |
| Finished | Sep 18 09:49:53 AM UTC 24 |
| Peak memory | 154652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=393337930 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 62.prim_prince_test.393337930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/62.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/63.prim_prince_test.3922398954 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 3399048077 ps |
| CPU time | 65.99 seconds |
| Started | Sep 18 09:48:51 AM UTC 24 |
| Finished | Sep 18 09:50:15 AM UTC 24 |
| Peak memory | 154660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3922398954 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 63.prim_prince_test.3922398954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/63.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/64.prim_prince_test.4165103026 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 1887990958 ps |
| CPU time | 35.66 seconds |
| Started | Sep 18 09:48:52 AM UTC 24 |
| Finished | Sep 18 09:49:38 AM UTC 24 |
| Peak memory | 154596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4165103026 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 64.prim_prince_test.4165103026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/64.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/65.prim_prince_test.3228942354 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 2465564738 ps |
| CPU time | 47.34 seconds |
| Started | Sep 18 09:48:53 AM UTC 24 |
| Finished | Sep 18 09:49:54 AM UTC 24 |
| Peak memory | 154660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3228942354 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 65.prim_prince_test.3228942354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/65.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/66.prim_prince_test.3047072443 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 2185514112 ps |
| CPU time | 41.15 seconds |
| Started | Sep 18 09:48:55 AM UTC 24 |
| Finished | Sep 18 09:49:48 AM UTC 24 |
| Peak memory | 154660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3047072443 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 66.prim_prince_test.3047072443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/66.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/67.prim_prince_test.2750812091 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 2538349133 ps |
| CPU time | 46.85 seconds |
| Started | Sep 18 09:48:57 AM UTC 24 |
| Finished | Sep 18 09:49:58 AM UTC 24 |
| Peak memory | 154660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2750812091 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 67.prim_prince_test.2750812091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/67.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/68.prim_prince_test.2874567105 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 1878026312 ps |
| CPU time | 35.02 seconds |
| Started | Sep 18 09:48:58 AM UTC 24 |
| Finished | Sep 18 09:49:44 AM UTC 24 |
| Peak memory | 154596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2874567105 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 68.prim_prince_test.2874567105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/68.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/69.prim_prince_test.72074741 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 2866939408 ps |
| CPU time | 55.45 seconds |
| Started | Sep 18 09:49:01 AM UTC 24 |
| Finished | Sep 18 09:50:12 AM UTC 24 |
| Peak memory | 154648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=72074741 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 69.prim_prince_test.72074741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/69.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/7.prim_prince_test.1425579546 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 2309168687 ps |
| CPU time | 45.8 seconds |
| Started | Sep 18 09:46:30 AM UTC 24 |
| Finished | Sep 18 09:47:30 AM UTC 24 |
| Peak memory | 154648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1425579546 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 7.prim_prince_test.1425579546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/7.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/70.prim_prince_test.78385620 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 2237059926 ps |
| CPU time | 42.7 seconds |
| Started | Sep 18 09:49:04 AM UTC 24 |
| Finished | Sep 18 09:49:59 AM UTC 24 |
| Peak memory | 154648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=78385620 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 70.prim_prince_test.78385620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/70.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/71.prim_prince_test.2285811881 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 2995034490 ps |
| CPU time | 57.78 seconds |
| Started | Sep 18 09:49:05 AM UTC 24 |
| Finished | Sep 18 09:50:19 AM UTC 24 |
| Peak memory | 154660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2285811881 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 71.prim_prince_test.2285811881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/71.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/72.prim_prince_test.945869578 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 1039810639 ps |
| CPU time | 20.37 seconds |
| Started | Sep 18 09:49:12 AM UTC 24 |
| Finished | Sep 18 09:49:39 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=945869578 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 72.prim_prince_test.945869578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/72.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/73.prim_prince_test.3480733840 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 2814456060 ps |
| CPU time | 54.31 seconds |
| Started | Sep 18 09:49:13 AM UTC 24 |
| Finished | Sep 18 09:50:23 AM UTC 24 |
| Peak memory | 154660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3480733840 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 73.prim_prince_test.3480733840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/73.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/74.prim_prince_test.338236002 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 2639151372 ps |
| CPU time | 49.39 seconds |
| Started | Sep 18 09:49:22 AM UTC 24 |
| Finished | Sep 18 09:50:26 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=338236002 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 74.prim_prince_test.338236002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/74.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/75.prim_prince_test.2075051083 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 2120547251 ps |
| CPU time | 41.74 seconds |
| Started | Sep 18 09:49:23 AM UTC 24 |
| Finished | Sep 18 09:50:17 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2075051083 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 75.prim_prince_test.2075051083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/75.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/76.prim_prince_test.3441452952 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 804956189 ps |
| CPU time | 15.37 seconds |
| Started | Sep 18 09:49:25 AM UTC 24 |
| Finished | Sep 18 09:49:45 AM UTC 24 |
| Peak memory | 154572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3441452952 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 76.prim_prince_test.3441452952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/76.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/77.prim_prince_test.393036059 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 2228368748 ps |
| CPU time | 41.36 seconds |
| Started | Sep 18 09:49:25 AM UTC 24 |
| Finished | Sep 18 09:50:18 AM UTC 24 |
| Peak memory | 154628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=393036059 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 77.prim_prince_test.393036059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/77.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/78.prim_prince_test.519773884 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 3135471930 ps |
| CPU time | 61.06 seconds |
| Started | Sep 18 09:49:26 AM UTC 24 |
| Finished | Sep 18 09:50:43 AM UTC 24 |
| Peak memory | 156108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=519773884 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 78.prim_prince_test.519773884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/78.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/79.prim_prince_test.4109296823 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 3118999909 ps |
| CPU time | 57.88 seconds |
| Started | Sep 18 09:49:27 AM UTC 24 |
| Finished | Sep 18 09:50:42 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4109296823 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 79.prim_prince_test.4109296823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/79.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/8.prim_prince_test.1953620848 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 3288704686 ps |
| CPU time | 65.51 seconds |
| Started | Sep 18 09:46:31 AM UTC 24 |
| Finished | Sep 18 09:47:56 AM UTC 24 |
| Peak memory | 154648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1953620848 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 8.prim_prince_test.1953620848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/8.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/80.prim_prince_test.1106010352 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 1089775043 ps |
| CPU time | 21.59 seconds |
| Started | Sep 18 09:49:28 AM UTC 24 |
| Finished | Sep 18 09:49:56 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1106010352 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 80.prim_prince_test.1106010352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/80.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/81.prim_prince_test.667253252 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 854188132 ps |
| CPU time | 16.96 seconds |
| Started | Sep 18 09:49:29 AM UTC 24 |
| Finished | Sep 18 09:49:51 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=667253252 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 81.prim_prince_test.667253252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/81.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/82.prim_prince_test.2915164749 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 1360339086 ps |
| CPU time | 26.62 seconds |
| Started | Sep 18 09:49:31 AM UTC 24 |
| Finished | Sep 18 09:50:05 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2915164749 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 82.prim_prince_test.2915164749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/82.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/83.prim_prince_test.3022590002 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 1982006818 ps |
| CPU time | 38.71 seconds |
| Started | Sep 18 09:49:38 AM UTC 24 |
| Finished | Sep 18 09:50:28 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3022590002 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 83.prim_prince_test.3022590002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/83.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/84.prim_prince_test.2596629217 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 1445133974 ps |
| CPU time | 28.32 seconds |
| Started | Sep 18 09:49:38 AM UTC 24 |
| Finished | Sep 18 09:50:15 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2596629217 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 84.prim_prince_test.2596629217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/84.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/85.prim_prince_test.1983517241 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 3511708417 ps |
| CPU time | 66.31 seconds |
| Started | Sep 18 09:49:39 AM UTC 24 |
| Finished | Sep 18 09:51:04 AM UTC 24 |
| Peak memory | 154376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1983517241 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 85.prim_prince_test.1983517241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/85.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/86.prim_prince_test.517730614 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 2173363197 ps |
| CPU time | 42.24 seconds |
| Started | Sep 18 09:49:39 AM UTC 24 |
| Finished | Sep 18 09:50:33 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=517730614 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 86.prim_prince_test.517730614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/86.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/87.prim_prince_test.872046669 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 1236969369 ps |
| CPU time | 24.35 seconds |
| Started | Sep 18 09:49:40 AM UTC 24 |
| Finished | Sep 18 09:50:12 AM UTC 24 |
| Peak memory | 154592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=872046669 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 87.prim_prince_test.872046669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/87.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/88.prim_prince_test.3197291502 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 2364405031 ps |
| CPU time | 44.67 seconds |
| Started | Sep 18 09:49:44 AM UTC 24 |
| Finished | Sep 18 09:50:42 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3197291502 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 88.prim_prince_test.3197291502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/88.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/89.prim_prince_test.2260626597 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 2818008760 ps |
| CPU time | 54.82 seconds |
| Started | Sep 18 09:49:45 AM UTC 24 |
| Finished | Sep 18 09:50:55 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2260626597 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 89.prim_prince_test.2260626597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/89.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/9.prim_prince_test.968806211 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 2551685929 ps |
| CPU time | 51.82 seconds |
| Started | Sep 18 09:46:31 AM UTC 24 |
| Finished | Sep 18 09:47:39 AM UTC 24 |
| Peak memory | 154656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=968806211 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 9.prim_prince_test.968806211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/9.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/90.prim_prince_test.1148514168 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 3414743047 ps |
| CPU time | 63.04 seconds |
| Started | Sep 18 09:49:48 AM UTC 24 |
| Finished | Sep 18 09:51:10 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1148514168 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 90.prim_prince_test.1148514168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/90.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/91.prim_prince_test.3052892104 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 2552082544 ps |
| CPU time | 50.09 seconds |
| Started | Sep 18 09:49:52 AM UTC 24 |
| Finished | Sep 18 09:50:55 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3052892104 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 91.prim_prince_test.3052892104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/91.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/92.prim_prince_test.4045509950 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 1701412517 ps |
| CPU time | 32.01 seconds |
| Started | Sep 18 09:49:54 AM UTC 24 |
| Finished | Sep 18 09:50:35 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4045509950 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 92.prim_prince_test.4045509950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/92.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/93.prim_prince_test.3779876294 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 3421853815 ps |
| CPU time | 65.52 seconds |
| Started | Sep 18 09:49:54 AM UTC 24 |
| Finished | Sep 18 09:51:17 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3779876294 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 93.prim_prince_test.3779876294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/93.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/94.prim_prince_test.3602648964 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 3556961554 ps |
| CPU time | 67.61 seconds |
| Started | Sep 18 09:49:55 AM UTC 24 |
| Finished | Sep 18 09:51:21 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3602648964 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 94.prim_prince_test.3602648964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/94.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/95.prim_prince_test.2774366704 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 1648163552 ps |
| CPU time | 31.63 seconds |
| Started | Sep 18 09:49:55 AM UTC 24 |
| Finished | Sep 18 09:50:36 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2774366704 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 95.prim_prince_test.2774366704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/95.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/96.prim_prince_test.2468816233 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 1105522992 ps |
| CPU time | 21.31 seconds |
| Started | Sep 18 09:49:57 AM UTC 24 |
| Finished | Sep 18 09:50:25 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2468816233 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 96.prim_prince_test.2468816233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/96.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/97.prim_prince_test.1095762971 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 1905103426 ps |
| CPU time | 37.04 seconds |
| Started | Sep 18 09:49:57 AM UTC 24 |
| Finished | Sep 18 09:50:44 AM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1095762971 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 97.prim_prince_test.1095762971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/97.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/98.prim_prince_test.3207424065 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 3563808267 ps |
| CPU time | 65.72 seconds |
| Started | Sep 18 09:49:58 AM UTC 24 |
| Finished | Sep 18 09:51:22 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3207424065 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 98.prim_prince_test.3207424065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/98.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default/99.prim_prince_test.1983422124 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 3637869502 ps |
| CPU time | 69.94 seconds |
| Started | Sep 18 09:50:00 AM UTC 24 |
| Finished | Sep 18 09:51:29 AM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1983422124 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 99.prim_prince_test.1983422124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_prince-sim-vcs/99.prim_prince_test/latest |
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