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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Total test records in report: 500
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html
T251 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/244.prim_prince_test.3042062340 Sep 24 04:32:14 AM UTC 24 Sep 24 04:33:33 AM UTC 24 3318138599 ps
T252 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/240.prim_prince_test.3973509416 Sep 24 04:32:07 AM UTC 24 Sep 24 04:33:35 AM UTC 24 3621189792 ps
T253 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/261.prim_prince_test.1510359679 Sep 24 04:32:57 AM UTC 24 Sep 24 04:33:38 AM UTC 24 1689399440 ps
T254 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/251.prim_prince_test.1607933311 Sep 24 04:32:37 AM UTC 24 Sep 24 04:33:39 AM UTC 24 2590406060 ps
T255 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/248.prim_prince_test.774170465 Sep 24 04:32:35 AM UTC 24 Sep 24 04:33:43 AM UTC 24 2865386322 ps
T256 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/269.prim_prince_test.1919689325 Sep 24 04:33:14 AM UTC 24 Sep 24 04:33:44 AM UTC 24 1202340464 ps
T257 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/271.prim_prince_test.17364411 Sep 24 04:33:17 AM UTC 24 Sep 24 04:33:46 AM UTC 24 1105399172 ps
T258 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/263.prim_prince_test.2504645768 Sep 24 04:33:04 AM UTC 24 Sep 24 04:33:46 AM UTC 24 1728796108 ps
T259 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/255.prim_prince_test.3783240840 Sep 24 04:32:46 AM UTC 24 Sep 24 04:33:48 AM UTC 24 2536540753 ps
T260 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/247.prim_prince_test.3110980577 Sep 24 04:32:31 AM UTC 24 Sep 24 04:33:50 AM UTC 24 3370942996 ps
T261 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/262.prim_prince_test.3412392398 Sep 24 04:33:01 AM UTC 24 Sep 24 04:33:50 AM UTC 24 1961323243 ps
T262 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/256.prim_prince_test.2199994533 Sep 24 04:32:46 AM UTC 24 Sep 24 04:33:51 AM UTC 24 2692507910 ps
T263 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/265.prim_prince_test.3167899339 Sep 24 04:33:06 AM UTC 24 Sep 24 04:33:59 AM UTC 24 2232418674 ps
T264 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/253.prim_prince_test.4156625570 Sep 24 04:32:40 AM UTC 24 Sep 24 04:34:01 AM UTC 24 3431559382 ps
T265 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/254.prim_prince_test.2068657186 Sep 24 04:32:43 AM UTC 24 Sep 24 04:34:01 AM UTC 24 3141732120 ps
T266 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/267.prim_prince_test.1696748197 Sep 24 04:33:11 AM UTC 24 Sep 24 04:34:03 AM UTC 24 2126987554 ps
T267 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/270.prim_prince_test.3618052666 Sep 24 04:33:16 AM UTC 24 Sep 24 04:34:05 AM UTC 24 1957261474 ps
T268 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/257.prim_prince_test.1085037816 Sep 24 04:32:46 AM UTC 24 Sep 24 04:34:05 AM UTC 24 3352622356 ps
T269 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/259.prim_prince_test.3489412757 Sep 24 04:32:53 AM UTC 24 Sep 24 04:34:05 AM UTC 24 2928557299 ps
T270 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/285.prim_prince_test.1076551533 Sep 24 04:33:47 AM UTC 24 Sep 24 04:34:07 AM UTC 24 755868258 ps
T271 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/276.prim_prince_test.2380528019 Sep 24 04:33:22 AM UTC 24 Sep 24 04:34:07 AM UTC 24 1835808162 ps
T272 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/280.prim_prince_test.3076619852 Sep 24 04:33:39 AM UTC 24 Sep 24 04:34:10 AM UTC 24 1291828076 ps
T273 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/279.prim_prince_test.3770017910 Sep 24 04:33:35 AM UTC 24 Sep 24 04:34:11 AM UTC 24 1416813932 ps
T274 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/264.prim_prince_test.981178821 Sep 24 04:33:05 AM UTC 24 Sep 24 04:34:12 AM UTC 24 2750706512 ps
T275 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/281.prim_prince_test.2074451561 Sep 24 04:33:40 AM UTC 24 Sep 24 04:34:13 AM UTC 24 1351626573 ps
T276 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/268.prim_prince_test.4248206561 Sep 24 04:33:13 AM UTC 24 Sep 24 04:34:14 AM UTC 24 2558035094 ps
T277 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/272.prim_prince_test.3040460020 Sep 24 04:33:19 AM UTC 24 Sep 24 04:34:24 AM UTC 24 2713439532 ps
T278 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/289.prim_prince_test.2150456123 Sep 24 04:33:52 AM UTC 24 Sep 24 04:34:26 AM UTC 24 1399961295 ps
T279 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/266.prim_prince_test.2266832892 Sep 24 04:33:10 AM UTC 24 Sep 24 04:34:28 AM UTC 24 3341422321 ps
T280 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/275.prim_prince_test.2440483338 Sep 24 04:33:22 AM UTC 24 Sep 24 04:34:32 AM UTC 24 2945471033 ps
T281 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/274.prim_prince_test.3590788610 Sep 24 04:33:20 AM UTC 24 Sep 24 04:34:33 AM UTC 24 3065041778 ps
T282 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/295.prim_prince_test.3127186489 Sep 24 04:34:05 AM UTC 24 Sep 24 04:34:37 AM UTC 24 1282578277 ps
T283 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/282.prim_prince_test.4287443865 Sep 24 04:33:44 AM UTC 24 Sep 24 04:34:37 AM UTC 24 2199486420 ps
T284 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/300.prim_prince_test.2194051536 Sep 24 04:34:12 AM UTC 24 Sep 24 04:34:38 AM UTC 24 1027916124 ps
T285 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/273.prim_prince_test.4208586268 Sep 24 04:33:20 AM UTC 24 Sep 24 04:34:38 AM UTC 24 3283647733 ps
T286 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/277.prim_prince_test.3902549171 Sep 24 04:33:24 AM UTC 24 Sep 24 04:34:39 AM UTC 24 3166285345 ps
T287 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/303.prim_prince_test.2669165524 Sep 24 04:34:14 AM UTC 24 Sep 24 04:34:43 AM UTC 24 1145450652 ps
T288 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/283.prim_prince_test.2581594237 Sep 24 04:33:45 AM UTC 24 Sep 24 04:34:53 AM UTC 24 2874055618 ps
T289 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/298.prim_prince_test.1331552787 Sep 24 04:34:09 AM UTC 24 Sep 24 04:34:55 AM UTC 24 1875092085 ps
T290 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/287.prim_prince_test.2454558119 Sep 24 04:33:50 AM UTC 24 Sep 24 04:34:57 AM UTC 24 2709038816 ps
T291 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/284.prim_prince_test.3417685816 Sep 24 04:33:46 AM UTC 24 Sep 24 04:34:58 AM UTC 24 2982877799 ps
T292 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/301.prim_prince_test.2628164894 Sep 24 04:34:13 AM UTC 24 Sep 24 04:34:58 AM UTC 24 1851991515 ps
T293 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/299.prim_prince_test.4235999107 Sep 24 04:34:11 AM UTC 24 Sep 24 04:35:00 AM UTC 24 2046041139 ps
T294 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/278.prim_prince_test.178516318 Sep 24 04:33:34 AM UTC 24 Sep 24 04:35:02 AM UTC 24 3699226783 ps
T295 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/286.prim_prince_test.340110505 Sep 24 04:33:49 AM UTC 24 Sep 24 04:35:03 AM UTC 24 3067303089 ps
T296 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/302.prim_prince_test.2890596656 Sep 24 04:34:13 AM UTC 24 Sep 24 04:35:04 AM UTC 24 2103122025 ps
T297 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/292.prim_prince_test.2098922796 Sep 24 04:34:02 AM UTC 24 Sep 24 04:35:05 AM UTC 24 2555023163 ps
T298 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/294.prim_prince_test.2672763591 Sep 24 04:34:05 AM UTC 24 Sep 24 04:35:05 AM UTC 24 2423649670 ps
T299 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/291.prim_prince_test.548177508 Sep 24 04:34:02 AM UTC 24 Sep 24 04:35:05 AM UTC 24 2639261804 ps
T300 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/297.prim_prince_test.3496530238 Sep 24 04:34:08 AM UTC 24 Sep 24 04:35:07 AM UTC 24 2406869130 ps
T301 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/288.prim_prince_test.1144479075 Sep 24 04:33:51 AM UTC 24 Sep 24 04:35:09 AM UTC 24 3321673992 ps
T302 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/290.prim_prince_test.2173284470 Sep 24 04:34:00 AM UTC 24 Sep 24 04:35:11 AM UTC 24 3021970325 ps
T303 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/293.prim_prince_test.986424652 Sep 24 04:34:03 AM UTC 24 Sep 24 04:35:12 AM UTC 24 2824406549 ps
T304 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/313.prim_prince_test.804250161 Sep 24 04:34:41 AM UTC 24 Sep 24 04:35:13 AM UTC 24 1281247815 ps
T305 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/312.prim_prince_test.3431597693 Sep 24 04:34:40 AM UTC 24 Sep 24 04:35:13 AM UTC 24 1378833216 ps
T306 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/309.prim_prince_test.2887301071 Sep 24 04:34:37 AM UTC 24 Sep 24 04:35:15 AM UTC 24 1497703140 ps
T307 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/311.prim_prince_test.1142681844 Sep 24 04:34:39 AM UTC 24 Sep 24 04:35:19 AM UTC 24 1673799483 ps
T308 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/319.prim_prince_test.3296508861 Sep 24 04:34:59 AM UTC 24 Sep 24 04:35:19 AM UTC 24 811368760 ps
T309 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/296.prim_prince_test.980260659 Sep 24 04:34:07 AM UTC 24 Sep 24 04:35:20 AM UTC 24 3114971863 ps
T310 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/316.prim_prince_test.4028027448 Sep 24 04:34:56 AM UTC 24 Sep 24 04:35:23 AM UTC 24 1099102832 ps
T311 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/305.prim_prince_test.1811878127 Sep 24 04:34:27 AM UTC 24 Sep 24 04:35:27 AM UTC 24 2463332463 ps
T312 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/323.prim_prince_test.327742945 Sep 24 04:35:05 AM UTC 24 Sep 24 04:35:28 AM UTC 24 889011451 ps
T313 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/321.prim_prince_test.3753653761 Sep 24 04:35:03 AM UTC 24 Sep 24 04:35:32 AM UTC 24 1157719283 ps
T314 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/320.prim_prince_test.4097007200 Sep 24 04:35:01 AM UTC 24 Sep 24 04:35:32 AM UTC 24 1267364117 ps
T315 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/308.prim_prince_test.858846691 Sep 24 04:34:34 AM UTC 24 Sep 24 04:35:34 AM UTC 24 2517399569 ps
T316 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/310.prim_prince_test.2784859023 Sep 24 04:34:38 AM UTC 24 Sep 24 04:35:38 AM UTC 24 2461921637 ps
T317 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/307.prim_prince_test.3960115889 Sep 24 04:34:33 AM UTC 24 Sep 24 04:35:39 AM UTC 24 2684799300 ps
T318 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/318.prim_prince_test.2968888162 Sep 24 04:34:59 AM UTC 24 Sep 24 04:35:44 AM UTC 24 1877330556 ps
T319 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/332.prim_prince_test.1655041973 Sep 24 04:35:14 AM UTC 24 Sep 24 04:35:46 AM UTC 24 1305824183 ps
T320 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/322.prim_prince_test.215542896 Sep 24 04:35:04 AM UTC 24 Sep 24 04:35:48 AM UTC 24 1777962306 ps
T321 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/317.prim_prince_test.421155280 Sep 24 04:34:57 AM UTC 24 Sep 24 04:35:48 AM UTC 24 2098909801 ps
T322 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/306.prim_prince_test.3738779560 Sep 24 04:34:29 AM UTC 24 Sep 24 04:35:49 AM UTC 24 3323311996 ps
T323 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/304.prim_prince_test.669104656 Sep 24 04:34:25 AM UTC 24 Sep 24 04:35:49 AM UTC 24 3494459556 ps
T324 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/329.prim_prince_test.1887982098 Sep 24 04:35:12 AM UTC 24 Sep 24 04:35:50 AM UTC 24 1566006601 ps
T325 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/340.prim_prince_test.2370904486 Sep 24 04:35:33 AM UTC 24 Sep 24 04:35:54 AM UTC 24 853928282 ps
T326 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/315.prim_prince_test.3048897871 Sep 24 04:34:54 AM UTC 24 Sep 24 04:35:56 AM UTC 24 2612164528 ps
T327 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/341.prim_prince_test.270529792 Sep 24 04:35:33 AM UTC 24 Sep 24 04:35:59 AM UTC 24 1032441352 ps
T328 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/327.prim_prince_test.2328090105 Sep 24 04:35:08 AM UTC 24 Sep 24 04:36:02 AM UTC 24 2212326325 ps
T329 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/343.prim_prince_test.198618222 Sep 24 04:35:39 AM UTC 24 Sep 24 04:36:02 AM UTC 24 863787945 ps
T330 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/314.prim_prince_test.2982804393 Sep 24 04:34:44 AM UTC 24 Sep 24 04:36:02 AM UTC 24 3240298700 ps
T331 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/330.prim_prince_test.165415253 Sep 24 04:35:13 AM UTC 24 Sep 24 04:36:06 AM UTC 24 2191003495 ps
T332 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/344.prim_prince_test.1581914018 Sep 24 04:35:40 AM UTC 24 Sep 24 04:36:06 AM UTC 24 1007846754 ps
T333 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/328.prim_prince_test.2784414887 Sep 24 04:35:10 AM UTC 24 Sep 24 04:36:09 AM UTC 24 2381926979 ps
T334 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/335.prim_prince_test.1854873639 Sep 24 04:35:20 AM UTC 24 Sep 24 04:36:10 AM UTC 24 2108898413 ps
T335 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/334.prim_prince_test.1581323194 Sep 24 04:35:20 AM UTC 24 Sep 24 04:36:11 AM UTC 24 2156287473 ps
T336 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/326.prim_prince_test.599277357 Sep 24 04:35:07 AM UTC 24 Sep 24 04:36:12 AM UTC 24 2641906819 ps
T337 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/349.prim_prince_test.80000911 Sep 24 04:35:50 AM UTC 24 Sep 24 04:36:13 AM UTC 24 872610182 ps
T338 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/324.prim_prince_test.1363166910 Sep 24 04:35:05 AM UTC 24 Sep 24 04:36:14 AM UTC 24 2881382262 ps
T339 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/331.prim_prince_test.2293398197 Sep 24 04:35:13 AM UTC 24 Sep 24 04:36:17 AM UTC 24 2591668914 ps
T340 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/338.prim_prince_test.2492615377 Sep 24 04:35:28 AM UTC 24 Sep 24 04:36:21 AM UTC 24 2155863500 ps
T341 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/325.prim_prince_test.1749283145 Sep 24 04:35:05 AM UTC 24 Sep 24 04:36:32 AM UTC 24 3613445621 ps
T342 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/347.prim_prince_test.1899182136 Sep 24 04:35:49 AM UTC 24 Sep 24 04:36:32 AM UTC 24 1753940576 ps
T343 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/354.prim_prince_test.3038945926 Sep 24 04:36:00 AM UTC 24 Sep 24 04:36:34 AM UTC 24 1340123579 ps
T344 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/337.prim_prince_test.3668170639 Sep 24 04:35:24 AM UTC 24 Sep 24 04:36:35 AM UTC 24 2994172541 ps
T345 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/346.prim_prince_test.3732526191 Sep 24 04:35:47 AM UTC 24 Sep 24 04:36:37 AM UTC 24 2050165461 ps
T346 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/363.prim_prince_test.3377199354 Sep 24 04:36:13 AM UTC 24 Sep 24 04:36:39 AM UTC 24 1023793620 ps
T347 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/353.prim_prince_test.216920888 Sep 24 04:35:57 AM UTC 24 Sep 24 04:36:40 AM UTC 24 1742806965 ps
T348 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/333.prim_prince_test.1084476359 Sep 24 04:35:16 AM UTC 24 Sep 24 04:36:40 AM UTC 24 3562778877 ps
T349 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/339.prim_prince_test.295757144 Sep 24 04:35:29 AM UTC 24 Sep 24 04:36:41 AM UTC 24 2894046080 ps
T350 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/336.prim_prince_test.3923589752 Sep 24 04:35:21 AM UTC 24 Sep 24 04:36:44 AM UTC 24 3486636364 ps
T351 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/342.prim_prince_test.994952263 Sep 24 04:35:35 AM UTC 24 Sep 24 04:36:45 AM UTC 24 2900155752 ps
T352 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/360.prim_prince_test.3347212985 Sep 24 04:36:09 AM UTC 24 Sep 24 04:36:45 AM UTC 24 1442569284 ps
T353 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/348.prim_prince_test.1347683682 Sep 24 04:35:49 AM UTC 24 Sep 24 04:36:53 AM UTC 24 2642063662 ps
T354 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/351.prim_prince_test.142542989 Sep 24 04:35:51 AM UTC 24 Sep 24 04:36:54 AM UTC 24 2596709973 ps
T355 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/352.prim_prince_test.1676886631 Sep 24 04:35:55 AM UTC 24 Sep 24 04:36:54 AM UTC 24 2459896229 ps
T356 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/369.prim_prince_test.295633880 Sep 24 04:36:33 AM UTC 24 Sep 24 04:36:55 AM UTC 24 890193154 ps
T357 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/367.prim_prince_test.2457786097 Sep 24 04:36:22 AM UTC 24 Sep 24 04:36:57 AM UTC 24 1400985199 ps
T358 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/345.prim_prince_test.178376515 Sep 24 04:35:44 AM UTC 24 Sep 24 04:37:00 AM UTC 24 3085892809 ps
T359 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/359.prim_prince_test.426441981 Sep 24 04:36:07 AM UTC 24 Sep 24 04:37:01 AM UTC 24 2238717096 ps
T360 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/350.prim_prince_test.766272680 Sep 24 04:35:50 AM UTC 24 Sep 24 04:37:04 AM UTC 24 2990331949 ps
T361 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/364.prim_prince_test.133604916 Sep 24 04:36:13 AM UTC 24 Sep 24 04:37:05 AM UTC 24 2121682184 ps
T362 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/373.prim_prince_test.419193248 Sep 24 04:36:39 AM UTC 24 Sep 24 04:37:08 AM UTC 24 1156961395 ps
T363 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/357.prim_prince_test.3267762258 Sep 24 04:36:04 AM UTC 24 Sep 24 04:37:14 AM UTC 24 2880134616 ps
T364 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/372.prim_prince_test.2957814522 Sep 24 04:36:37 AM UTC 24 Sep 24 04:37:15 AM UTC 24 1555868953 ps
T365 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/365.prim_prince_test.2909609105 Sep 24 04:36:15 AM UTC 24 Sep 24 04:37:19 AM UTC 24 2635997477 ps
T366 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/355.prim_prince_test.1802429290 Sep 24 04:36:03 AM UTC 24 Sep 24 04:37:23 AM UTC 24 3258210508 ps
T367 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/358.prim_prince_test.3098797262 Sep 24 04:36:06 AM UTC 24 Sep 24 04:37:23 AM UTC 24 3240921605 ps
T368 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/356.prim_prince_test.939405819 Sep 24 04:36:03 AM UTC 24 Sep 24 04:37:24 AM UTC 24 3420365728 ps
T369 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/380.prim_prince_test.141848445 Sep 24 04:36:53 AM UTC 24 Sep 24 04:37:25 AM UTC 24 1275806965 ps
T370 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/375.prim_prince_test.2167659592 Sep 24 04:36:42 AM UTC 24 Sep 24 04:37:26 AM UTC 24 1832927501 ps
T371 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/361.prim_prince_test.3382370938 Sep 24 04:36:12 AM UTC 24 Sep 24 04:37:27 AM UTC 24 3176311271 ps
T372 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/370.prim_prince_test.1989121787 Sep 24 04:36:35 AM UTC 24 Sep 24 04:37:28 AM UTC 24 2169228972 ps
T373 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/379.prim_prince_test.3766878051 Sep 24 04:36:46 AM UTC 24 Sep 24 04:37:29 AM UTC 24 1757682134 ps
T374 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/381.prim_prince_test.1278243598 Sep 24 04:36:55 AM UTC 24 Sep 24 04:37:34 AM UTC 24 1567866801 ps
T375 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/385.prim_prince_test.2529743916 Sep 24 04:37:00 AM UTC 24 Sep 24 04:37:35 AM UTC 24 1425526937 ps
T376 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/382.prim_prince_test.901033647 Sep 24 04:36:55 AM UTC 24 Sep 24 04:37:40 AM UTC 24 1886199136 ps
T377 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/366.prim_prince_test.3153777201 Sep 24 04:36:18 AM UTC 24 Sep 24 04:37:42 AM UTC 24 3531553081 ps
T378 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/362.prim_prince_test.2446047684 Sep 24 04:36:13 AM UTC 24 Sep 24 04:37:42 AM UTC 24 3646953009 ps
T379 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/368.prim_prince_test.286816471 Sep 24 04:36:33 AM UTC 24 Sep 24 04:37:42 AM UTC 24 2865937462 ps
T380 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/377.prim_prince_test.2385603951 Sep 24 04:36:45 AM UTC 24 Sep 24 04:37:45 AM UTC 24 2504725062 ps
T381 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/383.prim_prince_test.4251075854 Sep 24 04:36:56 AM UTC 24 Sep 24 04:37:46 AM UTC 24 2109961243 ps
T382 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/396.prim_prince_test.441477543 Sep 24 04:37:27 AM UTC 24 Sep 24 04:37:51 AM UTC 24 957848181 ps
T383 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/399.prim_prince_test.3087543566 Sep 24 04:37:29 AM UTC 24 Sep 24 04:37:54 AM UTC 24 949374151 ps
T384 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/371.prim_prince_test.948551438 Sep 24 04:36:36 AM UTC 24 Sep 24 04:37:55 AM UTC 24 3322568994 ps
T385 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/378.prim_prince_test.1631832164 Sep 24 04:36:46 AM UTC 24 Sep 24 04:37:58 AM UTC 24 3007881418 ps
T386 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/374.prim_prince_test.1078600542 Sep 24 04:36:41 AM UTC 24 Sep 24 04:37:59 AM UTC 24 3324568849 ps
T387 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/403.prim_prince_test.2291115713 Sep 24 04:37:41 AM UTC 24 Sep 24 04:38:02 AM UTC 24 812500500 ps
T388 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/376.prim_prince_test.3062867460 Sep 24 04:36:42 AM UTC 24 Sep 24 04:38:04 AM UTC 24 3482966279 ps
T389 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/388.prim_prince_test.3566132768 Sep 24 04:37:06 AM UTC 24 Sep 24 04:38:05 AM UTC 24 2371138894 ps
T390 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/389.prim_prince_test.1219982620 Sep 24 04:37:09 AM UTC 24 Sep 24 04:38:08 AM UTC 24 2368790255 ps
T391 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/402.prim_prince_test.3473917696 Sep 24 04:37:37 AM UTC 24 Sep 24 04:38:08 AM UTC 24 1252432400 ps
T392 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/387.prim_prince_test.3353417423 Sep 24 04:37:04 AM UTC 24 Sep 24 04:38:13 AM UTC 24 2891140745 ps
T393 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/407.prim_prince_test.3715437083 Sep 24 04:37:46 AM UTC 24 Sep 24 04:38:13 AM UTC 24 1109993437 ps
T394 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/406.prim_prince_test.2540267775 Sep 24 04:37:43 AM UTC 24 Sep 24 04:38:14 AM UTC 24 1193041905 ps
T395 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/384.prim_prince_test.2036734835 Sep 24 04:36:58 AM UTC 24 Sep 24 04:38:14 AM UTC 24 3104841841 ps
T396 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/390.prim_prince_test.1379037008 Sep 24 04:37:15 AM UTC 24 Sep 24 04:38:17 AM UTC 24 2477446059 ps
T397 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/397.prim_prince_test.3264523021 Sep 24 04:37:27 AM UTC 24 Sep 24 04:38:19 AM UTC 24 2120836356 ps
T398 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/409.prim_prince_test.1005605898 Sep 24 04:37:52 AM UTC 24 Sep 24 04:38:20 AM UTC 24 1098457208 ps
T399 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/405.prim_prince_test.1324554716 Sep 24 04:37:43 AM UTC 24 Sep 24 04:38:20 AM UTC 24 1442749923 ps
T400 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/393.prim_prince_test.581219658 Sep 24 04:37:23 AM UTC 24 Sep 24 04:38:21 AM UTC 24 2392044510 ps
T401 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/400.prim_prince_test.2128038774 Sep 24 04:37:29 AM UTC 24 Sep 24 04:38:23 AM UTC 24 2207184063 ps
T402 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/398.prim_prince_test.1687653648 Sep 24 04:37:28 AM UTC 24 Sep 24 04:38:26 AM UTC 24 2416029382 ps
T403 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/386.prim_prince_test.668271218 Sep 24 04:37:02 AM UTC 24 Sep 24 04:38:27 AM UTC 24 3570959360 ps
T404 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/395.prim_prince_test.3995626323 Sep 24 04:37:26 AM UTC 24 Sep 24 04:38:27 AM UTC 24 2549964821 ps
T405 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/391.prim_prince_test.3898830856 Sep 24 04:37:16 AM UTC 24 Sep 24 04:38:31 AM UTC 24 3025784264 ps
T406 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/394.prim_prince_test.3641796175 Sep 24 04:37:24 AM UTC 24 Sep 24 04:38:34 AM UTC 24 2901970231 ps
T407 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/392.prim_prince_test.2638036918 Sep 24 04:37:20 AM UTC 24 Sep 24 04:38:35 AM UTC 24 3153595748 ps
T408 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/415.prim_prince_test.3964991044 Sep 24 04:38:05 AM UTC 24 Sep 24 04:38:37 AM UTC 24 1289708825 ps
T409 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/421.prim_prince_test.3120454288 Sep 24 04:38:15 AM UTC 24 Sep 24 04:38:41 AM UTC 24 1046070791 ps
T410 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/426.prim_prince_test.3504316546 Sep 24 04:38:21 AM UTC 24 Sep 24 04:38:42 AM UTC 24 849325336 ps
T411 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/410.prim_prince_test.3823178814 Sep 24 04:37:55 AM UTC 24 Sep 24 04:38:42 AM UTC 24 1879552184 ps
T412 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/401.prim_prince_test.2724790849 Sep 24 04:37:35 AM UTC 24 Sep 24 04:38:43 AM UTC 24 2817699871 ps
T413 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/429.prim_prince_test.25089599 Sep 24 04:38:27 AM UTC 24 Sep 24 04:38:49 AM UTC 24 866133586 ps
T414 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/425.prim_prince_test.929351709 Sep 24 04:38:21 AM UTC 24 Sep 24 04:38:52 AM UTC 24 1278182153 ps
T415 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/408.prim_prince_test.3710844360 Sep 24 04:37:48 AM UTC 24 Sep 24 04:38:56 AM UTC 24 2851592155 ps
T416 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/420.prim_prince_test.2940551137 Sep 24 04:38:14 AM UTC 24 Sep 24 04:38:58 AM UTC 24 1778684495 ps
T417 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/411.prim_prince_test.2006612741 Sep 24 04:37:55 AM UTC 24 Sep 24 04:38:58 AM UTC 24 2615752314 ps
T418 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/419.prim_prince_test.2281776014 Sep 24 04:38:14 AM UTC 24 Sep 24 04:39:00 AM UTC 24 1889880604 ps
T419 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/422.prim_prince_test.819159063 Sep 24 04:38:15 AM UTC 24 Sep 24 04:39:06 AM UTC 24 2086669440 ps
T420 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/430.prim_prince_test.3126908137 Sep 24 04:38:27 AM UTC 24 Sep 24 04:39:09 AM UTC 24 1699661331 ps
T421 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/428.prim_prince_test.3631485337 Sep 24 04:38:24 AM UTC 24 Sep 24 04:39:09 AM UTC 24 1869376506 ps
T422 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/413.prim_prince_test.3125263519 Sep 24 04:38:01 AM UTC 24 Sep 24 04:39:12 AM UTC 24 3006241806 ps
T423 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/418.prim_prince_test.1007032087 Sep 24 04:38:09 AM UTC 24 Sep 24 04:39:13 AM UTC 24 2641578166 ps
T424 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/404.prim_prince_test.3585650848 Sep 24 04:37:42 AM UTC 24 Sep 24 04:39:14 AM UTC 24 3699066955 ps
T425 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/414.prim_prince_test.3786429655 Sep 24 04:38:03 AM UTC 24 Sep 24 04:39:14 AM UTC 24 2860331091 ps
T426 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/416.prim_prince_test.2791845472 Sep 24 04:38:05 AM UTC 24 Sep 24 04:39:19 AM UTC 24 3068588486 ps
T427 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/427.prim_prince_test.1921784424 Sep 24 04:38:22 AM UTC 24 Sep 24 04:39:22 AM UTC 24 2403177534 ps
T428 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/412.prim_prince_test.1237133833 Sep 24 04:37:59 AM UTC 24 Sep 24 04:39:23 AM UTC 24 3506353838 ps
T429 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/437.prim_prince_test.2747472385 Sep 24 04:38:43 AM UTC 24 Sep 24 04:39:23 AM UTC 24 1663185053 ps
T430 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/431.prim_prince_test.2839305330 Sep 24 04:38:27 AM UTC 24 Sep 24 04:39:27 AM UTC 24 2477518607 ps
T431 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/445.prim_prince_test.411249520 Sep 24 04:39:01 AM UTC 24 Sep 24 04:39:31 AM UTC 24 1146202892 ps
T432 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/444.prim_prince_test.2204782291 Sep 24 04:38:59 AM UTC 24 Sep 24 04:39:31 AM UTC 24 1250927076 ps
T433 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/417.prim_prince_test.3537982914 Sep 24 04:38:08 AM UTC 24 Sep 24 04:39:38 AM UTC 24 3605276543 ps
T434 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/434.prim_prince_test.1119326588 Sep 24 04:38:36 AM UTC 24 Sep 24 04:39:39 AM UTC 24 2647151628 ps
T435 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/440.prim_prince_test.3489989811 Sep 24 04:38:50 AM UTC 24 Sep 24 04:39:40 AM UTC 24 2072693562 ps
T436 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/439.prim_prince_test.2562369697 Sep 24 04:38:44 AM UTC 24 Sep 24 04:39:42 AM UTC 24 2403407379 ps
T437 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/435.prim_prince_test.2709518149 Sep 24 04:38:38 AM UTC 24 Sep 24 04:39:42 AM UTC 24 2525860833 ps
T438 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/454.prim_prince_test.3940082146 Sep 24 04:39:24 AM UTC 24 Sep 24 04:39:45 AM UTC 24 836087134 ps
T439 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/424.prim_prince_test.1303350075 Sep 24 04:38:20 AM UTC 24 Sep 24 04:39:45 AM UTC 24 3559718952 ps
T440 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/423.prim_prince_test.952683714 Sep 24 04:38:18 AM UTC 24 Sep 24 04:39:46 AM UTC 24 3703908396 ps
T441 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/432.prim_prince_test.2180789527 Sep 24 04:38:32 AM UTC 24 Sep 24 04:39:47 AM UTC 24 3193628661 ps
T442 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/433.prim_prince_test.3192346186 Sep 24 04:38:35 AM UTC 24 Sep 24 04:39:50 AM UTC 24 3183334994 ps
T443 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/438.prim_prince_test.776334908 Sep 24 04:38:43 AM UTC 24 Sep 24 04:39:54 AM UTC 24 2970794799 ps
T444 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/448.prim_prince_test.1315799707 Sep 24 04:39:10 AM UTC 24 Sep 24 04:39:54 AM UTC 24 1795720701 ps
T445 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/458.prim_prince_test.3511134885 Sep 24 04:39:32 AM UTC 24 Sep 24 04:39:55 AM UTC 24 854741588 ps
T446 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/451.prim_prince_test.872835686 Sep 24 04:39:15 AM UTC 24 Sep 24 04:39:55 AM UTC 24 1603352145 ps
T447 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/447.prim_prince_test.2971056708 Sep 24 04:39:09 AM UTC 24 Sep 24 04:39:58 AM UTC 24 1999777115 ps
T448 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/443.prim_prince_test.1292640257 Sep 24 04:38:59 AM UTC 24 Sep 24 04:40:01 AM UTC 24 2482033835 ps
T449 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/446.prim_prince_test.558856429 Sep 24 04:39:07 AM UTC 24 Sep 24 04:40:06 AM UTC 24 2442433142 ps
T450 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/436.prim_prince_test.3161801806 Sep 24 04:38:42 AM UTC 24 Sep 24 04:40:07 AM UTC 24 3548503230 ps
T451 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/450.prim_prince_test.2466834831 Sep 24 04:39:15 AM UTC 24 Sep 24 04:40:08 AM UTC 24 2215295739 ps
T452 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/455.prim_prince_test.639658163 Sep 24 04:39:24 AM UTC 24 Sep 24 04:40:08 AM UTC 24 1842209191 ps
T453 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/459.prim_prince_test.4099650824 Sep 24 04:39:32 AM UTC 24 Sep 24 04:40:11 AM UTC 24 1502476148 ps
T454 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/441.prim_prince_test.125771065 Sep 24 04:38:53 AM UTC 24 Sep 24 04:40:13 AM UTC 24 3324935201 ps
T455 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/467.prim_prince_test.2761666884 Sep 24 04:39:47 AM UTC 24 Sep 24 04:40:14 AM UTC 24 1102153319 ps
T456 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/442.prim_prince_test.3257095405 Sep 24 04:38:56 AM UTC 24 Sep 24 04:40:15 AM UTC 24 3290486330 ps
T457 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/468.prim_prince_test.2316839796 Sep 24 04:39:48 AM UTC 24 Sep 24 04:40:17 AM UTC 24 1192787784 ps
T458 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/449.prim_prince_test.130601782 Sep 24 04:39:13 AM UTC 24 Sep 24 04:40:17 AM UTC 24 2641845586 ps
T459 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/453.prim_prince_test.3952759577 Sep 24 04:39:20 AM UTC 24 Sep 24 04:40:21 AM UTC 24 2511029460 ps
T460 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/474.prim_prince_test.2608797828 Sep 24 04:39:59 AM UTC 24 Sep 24 04:40:23 AM UTC 24 944221976 ps
T461 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/462.prim_prince_test.4002257303 Sep 24 04:39:41 AM UTC 24 Sep 24 04:40:24 AM UTC 24 1771646587 ps
T462 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/464.prim_prince_test.2549225657 Sep 24 04:39:43 AM UTC 24 Sep 24 04:40:32 AM UTC 24 1999796532 ps
T463 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/452.prim_prince_test.3465950700 Sep 24 04:39:15 AM UTC 24 Sep 24 04:40:32 AM UTC 24 3177056071 ps
T464 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/479.prim_prince_test.3373955976 Sep 24 04:40:10 AM UTC 24 Sep 24 04:40:34 AM UTC 24 962265115 ps
T465 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/457.prim_prince_test.3331869883 Sep 24 04:39:29 AM UTC 24 Sep 24 04:40:39 AM UTC 24 2974645906 ps
T466 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/484.prim_prince_test.3094070030 Sep 24 04:40:18 AM UTC 24 Sep 24 04:40:43 AM UTC 24 999988577 ps
T467 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/461.prim_prince_test.3305104032 Sep 24 04:39:41 AM UTC 24 Sep 24 04:40:43 AM UTC 24 2587457003 ps
T468 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/473.prim_prince_test.2984758848 Sep 24 04:39:57 AM UTC 24 Sep 24 04:40:43 AM UTC 24 1861455189 ps
T469 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/478.prim_prince_test.825729973 Sep 24 04:40:10 AM UTC 24 Sep 24 04:40:46 AM UTC 24 1429268525 ps
T470 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/477.prim_prince_test.59942315 Sep 24 04:40:08 AM UTC 24 Sep 24 04:40:47 AM UTC 24 1576107389 ps
T471 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/472.prim_prince_test.4232711067 Sep 24 04:39:56 AM UTC 24 Sep 24 04:40:49 AM UTC 24 2180751123 ps
T472 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/456.prim_prince_test.3946353131 Sep 24 04:39:24 AM UTC 24 Sep 24 04:40:50 AM UTC 24 3527566762 ps
T473 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/471.prim_prince_test.3613065230 Sep 24 04:39:55 AM UTC 24 Sep 24 04:40:52 AM UTC 24 2373013648 ps
T474 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/466.prim_prince_test.1349254188 Sep 24 04:39:46 AM UTC 24 Sep 24 04:40:53 AM UTC 24 2788083024 ps
T475 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/469.prim_prince_test.784834696 Sep 24 04:39:51 AM UTC 24 Sep 24 04:40:55 AM UTC 24 2619454358 ps
T476 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/463.prim_prince_test.2493721769 Sep 24 04:39:43 AM UTC 24 Sep 24 04:41:01 AM UTC 24 3299990272 ps
T477 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/476.prim_prince_test.3340301942 Sep 24 04:40:06 AM UTC 24 Sep 24 04:41:01 AM UTC 24 2248404245 ps
T478 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/488.prim_prince_test.3422274140 Sep 24 04:40:25 AM UTC 24 Sep 24 04:41:06 AM UTC 24 1698502203 ps
T479 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/460.prim_prince_test.1646512029 Sep 24 04:39:38 AM UTC 24 Sep 24 04:41:07 AM UTC 24 3679721890 ps
T480 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/498.prim_prince_test.236534095 Sep 24 04:40:50 AM UTC 24 Sep 24 04:41:10 AM UTC 24 797523533 ps
T481 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/481.prim_prince_test.2320423367 Sep 24 04:40:13 AM UTC 24 Sep 24 04:41:11 AM UTC 24 2417434670 ps
T482 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/465.prim_prince_test.4197986140 Sep 24 04:39:45 AM UTC 24 Sep 24 04:41:14 AM UTC 24 3726662532 ps
T483 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/489.prim_prince_test.3879413140 Sep 24 04:40:33 AM UTC 24 Sep 24 04:41:14 AM UTC 24 1683674096 ps
T484 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/480.prim_prince_test.2291629188 Sep 24 04:40:12 AM UTC 24 Sep 24 04:41:14 AM UTC 24 2536765620 ps
T485 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/494.prim_prince_test.3132646126 Sep 24 04:40:44 AM UTC 24 Sep 24 04:41:15 AM UTC 24 1237759281 ps
T486 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/475.prim_prince_test.2688600948 Sep 24 04:40:02 AM UTC 24 Sep 24 04:41:18 AM UTC 24 3146836355 ps
T487 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/487.prim_prince_test.1848489243 Sep 24 04:40:25 AM UTC 24 Sep 24 04:41:19 AM UTC 24 2160552905 ps
T488 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/470.prim_prince_test.2625763341 Sep 24 04:39:54 AM UTC 24 Sep 24 04:41:24 AM UTC 24 3634788758 ps
T489 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/485.prim_prince_test.3374929705 Sep 24 04:40:18 AM UTC 24 Sep 24 04:41:27 AM UTC 24 2886972560 ps
T490 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/492.prim_prince_test.1129549366 Sep 24 04:40:40 AM UTC 24 Sep 24 04:41:28 AM UTC 24 1951635069 ps
T491 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/486.prim_prince_test.3283065535 Sep 24 04:40:21 AM UTC 24 Sep 24 04:41:29 AM UTC 24 2766418323 ps
T492 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/493.prim_prince_test.3116739167 Sep 24 04:40:44 AM UTC 24 Sep 24 04:41:34 AM UTC 24 1954982206 ps
T493 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/483.prim_prince_test.2912714879 Sep 24 04:40:17 AM UTC 24 Sep 24 04:41:39 AM UTC 24 3395073962 ps
T494 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/482.prim_prince_test.2506733266 Sep 24 04:40:16 AM UTC 24 Sep 24 04:41:41 AM UTC 24 3539925461 ps
T495 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/491.prim_prince_test.562202909 Sep 24 04:40:35 AM UTC 24 Sep 24 04:41:44 AM UTC 24 2792339192 ps
T496 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/490.prim_prince_test.2771684388 Sep 24 04:40:33 AM UTC 24 Sep 24 04:41:59 AM UTC 24 3538903130 ps
T497 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/495.prim_prince_test.3015792949 Sep 24 04:40:44 AM UTC 24 Sep 24 04:41:59 AM UTC 24 2995848533 ps
T498 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/499.prim_prince_test.643740183 Sep 24 04:40:51 AM UTC 24 Sep 24 04:42:01 AM UTC 24 2746455968 ps
T499 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/497.prim_prince_test.2766442219 Sep 24 04:40:47 AM UTC 24 Sep 24 04:42:14 AM UTC 24 3526915584 ps
T500 /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/496.prim_prince_test.2968025156 Sep 24 04:40:46 AM UTC 24 Sep 24 04:42:14 AM UTC 24 3607643282 ps

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/0.prim_prince_test.1294707095
Short name T4
Test name
Test status
Simulation time 1894493745 ps
CPU time 35.2 seconds
Started Sep 24 04:24:08 AM UTC 24
Finished Sep 24 04:24:54 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1294707095 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 0.prim_prince_test.1294707095
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/0.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/1.prim_prince_test.3697306536
Short name T1
Test name
Test status
Simulation time 1036255689 ps
CPU time 19.93 seconds
Started Sep 24 04:24:09 AM UTC 24
Finished Sep 24 04:24:35 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3697306536 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 1.prim_prince_test.3697306536
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/1.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/10.prim_prince_test.4063208335
Short name T3
Test name
Test status
Simulation time 1548970720 ps
CPU time 29.81 seconds
Started Sep 24 04:24:13 AM UTC 24
Finished Sep 24 04:24:51 AM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4063208335 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 10.prim_prince_test.4063208335
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/10.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/100.prim_prince_test.986428758
Short name T84
Test name
Test status
Simulation time 845751601 ps
CPU time 15.91 seconds
Started Sep 24 04:27:41 AM UTC 24
Finished Sep 24 04:28:03 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=986428758 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 100.prim_prince_test.986428758
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/100.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/101.prim_prince_test.369024162
Short name T107
Test name
Test status
Simulation time 2466382838 ps
CPU time 47.59 seconds
Started Sep 24 04:27:44 AM UTC 24
Finished Sep 24 04:28:46 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=369024162 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 101.prim_prince_test.369024162
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/101.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/102.prim_prince_test.762284802
Short name T114
Test name
Test status
Simulation time 3187917654 ps
CPU time 62.37 seconds
Started Sep 24 04:27:46 AM UTC 24
Finished Sep 24 04:29:06 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=762284802 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 102.prim_prince_test.762284802
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/102.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/103.prim_prince_test.611293484
Short name T97
Test name
Test status
Simulation time 1717355548 ps
CPU time 33.76 seconds
Started Sep 24 04:27:48 AM UTC 24
Finished Sep 24 04:28:32 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=611293484 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 103.prim_prince_test.611293484
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/103.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/104.prim_prince_test.2483982237
Short name T104
Test name
Test status
Simulation time 1958433069 ps
CPU time 38.58 seconds
Started Sep 24 04:27:48 AM UTC 24
Finished Sep 24 04:28:38 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2483982237 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 104.prim_prince_test.2483982237
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/104.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/105.prim_prince_test.3961257715
Short name T108
Test name
Test status
Simulation time 2322081052 ps
CPU time 43.14 seconds
Started Sep 24 04:27:50 AM UTC 24
Finished Sep 24 04:28:46 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3961257715 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 105.prim_prince_test.3961257715
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/105.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/106.prim_prince_test.4137918989
Short name T103
Test name
Test status
Simulation time 1648721138 ps
CPU time 32.59 seconds
Started Sep 24 04:27:54 AM UTC 24
Finished Sep 24 04:28:36 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4137918989 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 106.prim_prince_test.4137918989
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/106.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/107.prim_prince_test.2250322706
Short name T116
Test name
Test status
Simulation time 3080084482 ps
CPU time 56.86 seconds
Started Sep 24 04:27:57 AM UTC 24
Finished Sep 24 04:29:12 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2250322706 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 107.prim_prince_test.2250322706
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/107.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/108.prim_prince_test.3283694841
Short name T106
Test name
Test status
Simulation time 1760205737 ps
CPU time 34.77 seconds
Started Sep 24 04:27:57 AM UTC 24
Finished Sep 24 04:28:43 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3283694841 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 108.prim_prince_test.3283694841
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/108.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/109.prim_prince_test.1306544627
Short name T111
Test name
Test status
Simulation time 2226332991 ps
CPU time 43.74 seconds
Started Sep 24 04:27:59 AM UTC 24
Finished Sep 24 04:28:56 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1306544627 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 109.prim_prince_test.1306544627
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/109.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/11.prim_prince_test.3304025519
Short name T21
Test name
Test status
Simulation time 3396614585 ps
CPU time 62.72 seconds
Started Sep 24 04:24:18 AM UTC 24
Finished Sep 24 04:25:39 AM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3304025519 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 11.prim_prince_test.3304025519
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/11.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/110.prim_prince_test.3132079773
Short name T118
Test name
Test status
Simulation time 2940917960 ps
CPU time 56.11 seconds
Started Sep 24 04:28:04 AM UTC 24
Finished Sep 24 04:29:16 AM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3132079773 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 110.prim_prince_test.3132079773
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/110.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/111.prim_prince_test.2057374773
Short name T124
Test name
Test status
Simulation time 3238725269 ps
CPU time 63.37 seconds
Started Sep 24 04:28:06 AM UTC 24
Finished Sep 24 04:29:27 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2057374773 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 111.prim_prince_test.2057374773
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/111.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/112.prim_prince_test.190766882
Short name T109
Test name
Test status
Simulation time 1626383184 ps
CPU time 32.32 seconds
Started Sep 24 04:28:08 AM UTC 24
Finished Sep 24 04:28:49 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=190766882 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 112.prim_prince_test.190766882
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/112.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/113.prim_prince_test.532097954
Short name T96
Test name
Test status
Simulation time 802443653 ps
CPU time 15.06 seconds
Started Sep 24 04:28:09 AM UTC 24
Finished Sep 24 04:28:29 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=532097954 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 113.prim_prince_test.532097954
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/113.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/114.prim_prince_test.535374146
Short name T125
Test name
Test status
Simulation time 3234746920 ps
CPU time 59.68 seconds
Started Sep 24 04:28:11 AM UTC 24
Finished Sep 24 04:29:28 AM UTC 24
Peak memory 155048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=535374146 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 114.prim_prince_test.535374146
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/114.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/115.prim_prince_test.3538170121
Short name T113
Test name
Test status
Simulation time 1853921973 ps
CPU time 34.53 seconds
Started Sep 24 04:28:14 AM UTC 24
Finished Sep 24 04:28:59 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3538170121 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 115.prim_prince_test.3538170121
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/115.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/116.prim_prince_test.2757227419
Short name T98
Test name
Test status
Simulation time 755506180 ps
CPU time 14.25 seconds
Started Sep 24 04:28:14 AM UTC 24
Finished Sep 24 04:28:33 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2757227419 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 116.prim_prince_test.2757227419
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/116.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/117.prim_prince_test.225449053
Short name T137
Test name
Test status
Simulation time 3634980075 ps
CPU time 67.24 seconds
Started Sep 24 04:28:18 AM UTC 24
Finished Sep 24 04:29:45 AM UTC 24
Peak memory 154864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=225449053 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 117.prim_prince_test.225449053
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/117.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/118.prim_prince_test.355735680
Short name T121
Test name
Test status
Simulation time 2712663001 ps
CPU time 50.54 seconds
Started Sep 24 04:28:18 AM UTC 24
Finished Sep 24 04:29:24 AM UTC 24
Peak memory 154888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=355735680 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 118.prim_prince_test.355735680
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/118.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/119.prim_prince_test.3585477690
Short name T119
Test name
Test status
Simulation time 2210873717 ps
CPU time 43.21 seconds
Started Sep 24 04:28:21 AM UTC 24
Finished Sep 24 04:29:17 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3585477690 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 119.prim_prince_test.3585477690
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/119.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/12.prim_prince_test.2769514996
Short name T2
Test name
Test status
Simulation time 1120204575 ps
CPU time 21.47 seconds
Started Sep 24 04:24:20 AM UTC 24
Finished Sep 24 04:24:48 AM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2769514996 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 12.prim_prince_test.2769514996
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/12.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/120.prim_prince_test.416573578
Short name T138
Test name
Test status
Simulation time 3491317570 ps
CPU time 64.23 seconds
Started Sep 24 04:28:22 AM UTC 24
Finished Sep 24 04:29:46 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=416573578 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 120.prim_prince_test.416573578
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/120.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/121.prim_prince_test.1295649777
Short name T139
Test name
Test status
Simulation time 3524741929 ps
CPU time 65.39 seconds
Started Sep 24 04:28:23 AM UTC 24
Finished Sep 24 04:29:48 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1295649777 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 121.prim_prince_test.1295649777
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/121.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/122.prim_prince_test.3265484411
Short name T112
Test name
Test status
Simulation time 1115812897 ps
CPU time 21.27 seconds
Started Sep 24 04:28:29 AM UTC 24
Finished Sep 24 04:28:58 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3265484411 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 122.prim_prince_test.3265484411
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/122.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/123.prim_prince_test.416189739
Short name T122
Test name
Test status
Simulation time 2084307165 ps
CPU time 40.51 seconds
Started Sep 24 04:28:33 AM UTC 24
Finished Sep 24 04:29:25 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=416189739 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 123.prim_prince_test.416189739
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/123.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/124.prim_prince_test.988173332
Short name T120
Test name
Test status
Simulation time 1880664345 ps
CPU time 36.78 seconds
Started Sep 24 04:28:34 AM UTC 24
Finished Sep 24 04:29:21 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=988173332 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 124.prim_prince_test.988173332
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/124.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/125.prim_prince_test.4193334384
Short name T129
Test name
Test status
Simulation time 2408500437 ps
CPU time 46.41 seconds
Started Sep 24 04:28:35 AM UTC 24
Finished Sep 24 04:29:34 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4193334384 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 125.prim_prince_test.4193334384
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/125.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/126.prim_prince_test.2473179373
Short name T126
Test name
Test status
Simulation time 2203986746 ps
CPU time 41.72 seconds
Started Sep 24 04:28:36 AM UTC 24
Finished Sep 24 04:29:30 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2473179373 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 126.prim_prince_test.2473179373
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/126.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/127.prim_prince_test.3205384150
Short name T141
Test name
Test status
Simulation time 2988319940 ps
CPU time 58.55 seconds
Started Sep 24 04:28:37 AM UTC 24
Finished Sep 24 04:29:52 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3205384150 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 127.prim_prince_test.3205384150
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/127.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/128.prim_prince_test.1949775968
Short name T117
Test name
Test status
Simulation time 1507457344 ps
CPU time 29.76 seconds
Started Sep 24 04:28:37 AM UTC 24
Finished Sep 24 04:29:15 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1949775968 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 128.prim_prince_test.1949775968
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/128.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/129.prim_prince_test.1787052920
Short name T143
Test name
Test status
Simulation time 3129980920 ps
CPU time 60.16 seconds
Started Sep 24 04:28:37 AM UTC 24
Finished Sep 24 04:29:54 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1787052920 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 129.prim_prince_test.1787052920
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/129.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/13.prim_prince_test.3195410879
Short name T5
Test name
Test status
Simulation time 1413666744 ps
CPU time 26.99 seconds
Started Sep 24 04:24:20 AM UTC 24
Finished Sep 24 04:24:55 AM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3195410879 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 13.prim_prince_test.3195410879
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/13.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/130.prim_prince_test.2817033365
Short name T148
Test name
Test status
Simulation time 3546776922 ps
CPU time 68.94 seconds
Started Sep 24 04:28:37 AM UTC 24
Finished Sep 24 04:30:05 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2817033365 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 130.prim_prince_test.2817033365
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/130.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/131.prim_prince_test.503316963
Short name T145
Test name
Test status
Simulation time 3282833161 ps
CPU time 61.29 seconds
Started Sep 24 04:28:38 AM UTC 24
Finished Sep 24 04:29:57 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=503316963 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 131.prim_prince_test.503316963
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/131.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/132.prim_prince_test.2450332149
Short name T132
Test name
Test status
Simulation time 2374511009 ps
CPU time 43.84 seconds
Started Sep 24 04:28:43 AM UTC 24
Finished Sep 24 04:29:40 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2450332149 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 132.prim_prince_test.2450332149
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/132.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/133.prim_prince_test.222951459
Short name T115
Test name
Test status
Simulation time 1059662098 ps
CPU time 20.14 seconds
Started Sep 24 04:28:43 AM UTC 24
Finished Sep 24 04:29:10 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=222951459 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 133.prim_prince_test.222951459
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/133.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/134.prim_prince_test.1437534824
Short name T127
Test name
Test status
Simulation time 1820807515 ps
CPU time 33.98 seconds
Started Sep 24 04:28:46 AM UTC 24
Finished Sep 24 04:29:31 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1437534824 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 134.prim_prince_test.1437534824
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/134.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/135.prim_prince_test.1971571453
Short name T133
Test name
Test status
Simulation time 2214066630 ps
CPU time 40.95 seconds
Started Sep 24 04:28:48 AM UTC 24
Finished Sep 24 04:29:41 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1971571453 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 135.prim_prince_test.1971571453
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/135.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/136.prim_prince_test.2784650782
Short name T123
Test name
Test status
Simulation time 1380609343 ps
CPU time 27.01 seconds
Started Sep 24 04:28:51 AM UTC 24
Finished Sep 24 04:29:26 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2784650782 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 136.prim_prince_test.2784650782
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/136.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/137.prim_prince_test.3861430220
Short name T151
Test name
Test status
Simulation time 3125700544 ps
CPU time 57.13 seconds
Started Sep 24 04:28:54 AM UTC 24
Finished Sep 24 04:30:08 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3861430220 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 137.prim_prince_test.3861430220
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/137.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/138.prim_prince_test.1211380182
Short name T134
Test name
Test status
Simulation time 1750889789 ps
CPU time 34.22 seconds
Started Sep 24 04:28:57 AM UTC 24
Finished Sep 24 04:29:41 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1211380182 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 138.prim_prince_test.1211380182
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/138.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/139.prim_prince_test.1104959242
Short name T147
Test name
Test status
Simulation time 2594950697 ps
CPU time 50.13 seconds
Started Sep 24 04:28:59 AM UTC 24
Finished Sep 24 04:30:04 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1104959242 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 139.prim_prince_test.1104959242
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/139.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/14.prim_prince_test.3493684771
Short name T9
Test name
Test status
Simulation time 1637489391 ps
CPU time 30.55 seconds
Started Sep 24 04:24:21 AM UTC 24
Finished Sep 24 04:25:01 AM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3493684771 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 14.prim_prince_test.3493684771
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/14.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/140.prim_prince_test.3319894322
Short name T130
Test name
Test status
Simulation time 1526800818 ps
CPU time 28.94 seconds
Started Sep 24 04:29:00 AM UTC 24
Finished Sep 24 04:29:38 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3319894322 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 140.prim_prince_test.3319894322
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/140.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/141.prim_prince_test.927386934
Short name T128
Test name
Test status
Simulation time 966320020 ps
CPU time 19.21 seconds
Started Sep 24 04:29:07 AM UTC 24
Finished Sep 24 04:29:32 AM UTC 24
Peak memory 156340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=927386934 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 141.prim_prince_test.927386934
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/141.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/142.prim_prince_test.797292487
Short name T142
Test name
Test status
Simulation time 1638082077 ps
CPU time 31.14 seconds
Started Sep 24 04:29:11 AM UTC 24
Finished Sep 24 04:29:52 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=797292487 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 142.prim_prince_test.797292487
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/142.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/143.prim_prince_test.558061988
Short name T140
Test name
Test status
Simulation time 1566672678 ps
CPU time 29.47 seconds
Started Sep 24 04:29:12 AM UTC 24
Finished Sep 24 04:29:51 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=558061988 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 143.prim_prince_test.558061988
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/143.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/144.prim_prince_test.1807349964
Short name T131
Test name
Test status
Simulation time 875644637 ps
CPU time 17.51 seconds
Started Sep 24 04:29:16 AM UTC 24
Finished Sep 24 04:29:40 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1807349964 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 144.prim_prince_test.1807349964
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/144.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/145.prim_prince_test.1543415086
Short name T135
Test name
Test status
Simulation time 1026859656 ps
CPU time 20.54 seconds
Started Sep 24 04:29:16 AM UTC 24
Finished Sep 24 04:29:43 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1543415086 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 145.prim_prince_test.1543415086
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/145.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/146.prim_prince_test.3259033822
Short name T164
Test name
Test status
Simulation time 3352508271 ps
CPU time 61.88 seconds
Started Sep 24 04:29:17 AM UTC 24
Finished Sep 24 04:30:38 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3259033822 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 146.prim_prince_test.3259033822
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/146.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/147.prim_prince_test.228746470
Short name T136
Test name
Test status
Simulation time 890269454 ps
CPU time 17.71 seconds
Started Sep 24 04:29:22 AM UTC 24
Finished Sep 24 04:29:45 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=228746470 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 147.prim_prince_test.228746470
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/147.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/148.prim_prince_test.851446771
Short name T168
Test name
Test status
Simulation time 3235548313 ps
CPU time 60.44 seconds
Started Sep 24 04:29:25 AM UTC 24
Finished Sep 24 04:30:43 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=851446771 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 148.prim_prince_test.851446771
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/148.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/149.prim_prince_test.1019277131
Short name T171
Test name
Test status
Simulation time 3283219839 ps
CPU time 61.3 seconds
Started Sep 24 04:29:26 AM UTC 24
Finished Sep 24 04:30:45 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1019277131 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 149.prim_prince_test.1019277131
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/149.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/15.prim_prince_test.2397217006
Short name T25
Test name
Test status
Simulation time 3652088189 ps
CPU time 68.14 seconds
Started Sep 24 04:24:26 AM UTC 24
Finished Sep 24 04:25:54 AM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2397217006 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 15.prim_prince_test.2397217006
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/15.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/150.prim_prince_test.2696832019
Short name T144
Test name
Test status
Simulation time 1128223890 ps
CPU time 21.28 seconds
Started Sep 24 04:29:27 AM UTC 24
Finished Sep 24 04:29:55 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2696832019 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 150.prim_prince_test.2696832019
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/150.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/151.prim_prince_test.1626044944
Short name T149
Test name
Test status
Simulation time 1530519562 ps
CPU time 29.52 seconds
Started Sep 24 04:29:28 AM UTC 24
Finished Sep 24 04:30:06 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1626044944 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 151.prim_prince_test.1626044944
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/151.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/152.prim_prince_test.2205676744
Short name T146
Test name
Test status
Simulation time 1305425956 ps
CPU time 24.4 seconds
Started Sep 24 04:29:29 AM UTC 24
Finished Sep 24 04:30:01 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2205676744 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 152.prim_prince_test.2205676744
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/152.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/153.prim_prince_test.299024198
Short name T163
Test name
Test status
Simulation time 2756575201 ps
CPU time 50.83 seconds
Started Sep 24 04:29:30 AM UTC 24
Finished Sep 24 04:30:36 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=299024198 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 153.prim_prince_test.299024198
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/153.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/154.prim_prince_test.1048809636
Short name T172
Test name
Test status
Simulation time 3162195823 ps
CPU time 57.88 seconds
Started Sep 24 04:29:31 AM UTC 24
Finished Sep 24 04:30:46 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1048809636 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 154.prim_prince_test.1048809636
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/154.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/155.prim_prince_test.3537565521
Short name T155
Test name
Test status
Simulation time 1805591981 ps
CPU time 33.38 seconds
Started Sep 24 04:29:33 AM UTC 24
Finished Sep 24 04:30:17 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3537565521 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 155.prim_prince_test.3537565521
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/155.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/156.prim_prince_test.1703659998
Short name T160
Test name
Test status
Simulation time 2408108480 ps
CPU time 44.88 seconds
Started Sep 24 04:29:35 AM UTC 24
Finished Sep 24 04:30:34 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1703659998 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 156.prim_prince_test.1703659998
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/156.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/157.prim_prince_test.1383530235
Short name T177
Test name
Test status
Simulation time 3319099152 ps
CPU time 63.9 seconds
Started Sep 24 04:29:38 AM UTC 24
Finished Sep 24 04:31:00 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1383530235 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 157.prim_prince_test.1383530235
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/157.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/158.prim_prince_test.974033332
Short name T157
Test name
Test status
Simulation time 1969257136 ps
CPU time 37.03 seconds
Started Sep 24 04:29:41 AM UTC 24
Finished Sep 24 04:30:29 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=974033332 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 158.prim_prince_test.974033332
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/158.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/159.prim_prince_test.1661023599
Short name T178
Test name
Test status
Simulation time 3197796717 ps
CPU time 61.67 seconds
Started Sep 24 04:29:42 AM UTC 24
Finished Sep 24 04:31:01 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1661023599 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 159.prim_prince_test.1661023599
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/159.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/16.prim_prince_test.2604630892
Short name T6
Test name
Test status
Simulation time 1028523503 ps
CPU time 19.49 seconds
Started Sep 24 04:24:30 AM UTC 24
Finished Sep 24 04:24:56 AM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2604630892 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 16.prim_prince_test.2604630892
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/16.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/160.prim_prince_test.3966260277
Short name T152
Test name
Test status
Simulation time 1057659055 ps
CPU time 20.16 seconds
Started Sep 24 04:29:42 AM UTC 24
Finished Sep 24 04:30:08 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3966260277 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 160.prim_prince_test.3966260277
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/160.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/161.prim_prince_test.4292789404
Short name T166
Test name
Test status
Simulation time 2465769522 ps
CPU time 45.73 seconds
Started Sep 24 04:29:42 AM UTC 24
Finished Sep 24 04:30:41 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4292789404 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 161.prim_prince_test.4292789404
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/161.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/162.prim_prince_test.3895685507
Short name T154
Test name
Test status
Simulation time 1012123424 ps
CPU time 19.53 seconds
Started Sep 24 04:29:44 AM UTC 24
Finished Sep 24 04:30:10 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3895685507 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 162.prim_prince_test.3895685507
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/162.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/163.prim_prince_test.487923524
Short name T159
Test name
Test status
Simulation time 1886028171 ps
CPU time 36.04 seconds
Started Sep 24 04:29:46 AM UTC 24
Finished Sep 24 04:30:33 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=487923524 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 163.prim_prince_test.487923524
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/163.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/164.prim_prince_test.4255643433
Short name T153
Test name
Test status
Simulation time 917739553 ps
CPU time 17.48 seconds
Started Sep 24 04:29:46 AM UTC 24
Finished Sep 24 04:30:09 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4255643433 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 164.prim_prince_test.4255643433
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/164.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/165.prim_prince_test.4140084327
Short name T150
Test name
Test status
Simulation time 851548136 ps
CPU time 15.95 seconds
Started Sep 24 04:29:46 AM UTC 24
Finished Sep 24 04:30:07 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4140084327 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 165.prim_prince_test.4140084327
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/165.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/166.prim_prince_test.2548080268
Short name T173
Test name
Test status
Simulation time 2322362551 ps
CPU time 44.4 seconds
Started Sep 24 04:29:49 AM UTC 24
Finished Sep 24 04:30:46 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2548080268 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 166.prim_prince_test.2548080268
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/166.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/167.prim_prince_test.2510003686
Short name T170
Test name
Test status
Simulation time 2165787081 ps
CPU time 41.48 seconds
Started Sep 24 04:29:51 AM UTC 24
Finished Sep 24 04:30:45 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2510003686 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 167.prim_prince_test.2510003686
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/167.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/168.prim_prince_test.799755558
Short name T175
Test name
Test status
Simulation time 2722094387 ps
CPU time 49.93 seconds
Started Sep 24 04:29:53 AM UTC 24
Finished Sep 24 04:30:57 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=799755558 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 168.prim_prince_test.799755558
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/168.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/169.prim_prince_test.3840970568
Short name T185
Test name
Test status
Simulation time 3574411726 ps
CPU time 66.57 seconds
Started Sep 24 04:29:53 AM UTC 24
Finished Sep 24 04:31:18 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3840970568 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 169.prim_prince_test.3840970568
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/169.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/17.prim_prince_test.3110857837
Short name T18
Test name
Test status
Simulation time 2430751328 ps
CPU time 45.28 seconds
Started Sep 24 04:24:36 AM UTC 24
Finished Sep 24 04:25:35 AM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3110857837 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 17.prim_prince_test.3110857837
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/17.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/170.prim_prince_test.647153892
Short name T158
Test name
Test status
Simulation time 1570484650 ps
CPU time 29.02 seconds
Started Sep 24 04:29:55 AM UTC 24
Finished Sep 24 04:30:33 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=647153892 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 170.prim_prince_test.647153892
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/170.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/171.prim_prince_test.713773621
Short name T165
Test name
Test status
Simulation time 1769259642 ps
CPU time 34.1 seconds
Started Sep 24 04:29:56 AM UTC 24
Finished Sep 24 04:30:40 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=713773621 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 171.prim_prince_test.713773621
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/171.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/172.prim_prince_test.2503830878
Short name T174
Test name
Test status
Simulation time 2410992611 ps
CPU time 45.2 seconds
Started Sep 24 04:29:58 AM UTC 24
Finished Sep 24 04:30:56 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2503830878 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 172.prim_prince_test.2503830878
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/172.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/173.prim_prince_test.1766223512
Short name T156
Test name
Test status
Simulation time 816511697 ps
CPU time 15.99 seconds
Started Sep 24 04:30:02 AM UTC 24
Finished Sep 24 04:30:23 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1766223512 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 173.prim_prince_test.1766223512
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/173.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/174.prim_prince_test.1008975194
Short name T167
Test name
Test status
Simulation time 1557430889 ps
CPU time 28.66 seconds
Started Sep 24 04:30:05 AM UTC 24
Finished Sep 24 04:30:43 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1008975194 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 174.prim_prince_test.1008975194
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/174.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/175.prim_prince_test.2843889354
Short name T186
Test name
Test status
Simulation time 3030610702 ps
CPU time 59.31 seconds
Started Sep 24 04:30:06 AM UTC 24
Finished Sep 24 04:31:22 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2843889354 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 175.prim_prince_test.2843889354
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/175.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/176.prim_prince_test.2576136862
Short name T161
Test name
Test status
Simulation time 1092499549 ps
CPU time 21.21 seconds
Started Sep 24 04:30:07 AM UTC 24
Finished Sep 24 04:30:35 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2576136862 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 176.prim_prince_test.2576136862
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/176.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/177.prim_prince_test.2349362410
Short name T182
Test name
Test status
Simulation time 2647549674 ps
CPU time 50.18 seconds
Started Sep 24 04:30:08 AM UTC 24
Finished Sep 24 04:31:13 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2349362410 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 177.prim_prince_test.2349362410
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/177.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/178.prim_prince_test.73011962
Short name T162
Test name
Test status
Simulation time 1018883950 ps
CPU time 20.03 seconds
Started Sep 24 04:30:09 AM UTC 24
Finished Sep 24 04:30:36 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=73011962 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 178.prim_prince_test.73011962
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/178.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/179.prim_prince_test.1066832918
Short name T188
Test name
Test status
Simulation time 3309120922 ps
CPU time 60.21 seconds
Started Sep 24 04:30:09 AM UTC 24
Finished Sep 24 04:31:28 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1066832918 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 179.prim_prince_test.1066832918
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/179.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/18.prim_prince_test.1495873398
Short name T27
Test name
Test status
Simulation time 3435290639 ps
CPU time 64.49 seconds
Started Sep 24 04:24:39 AM UTC 24
Finished Sep 24 04:26:02 AM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1495873398 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 18.prim_prince_test.1495873398
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/18.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/180.prim_prince_test.3528301491
Short name T169
Test name
Test status
Simulation time 1328712092 ps
CPU time 25.95 seconds
Started Sep 24 04:30:11 AM UTC 24
Finished Sep 24 04:30:44 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3528301491 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 180.prim_prince_test.3528301491
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/180.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/181.prim_prince_test.2683530058
Short name T184
Test name
Test status
Simulation time 2810101865 ps
CPU time 51.63 seconds
Started Sep 24 04:30:11 AM UTC 24
Finished Sep 24 04:31:18 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2683530058 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 181.prim_prince_test.2683530058
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/181.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/182.prim_prince_test.2673859373
Short name T190
Test name
Test status
Simulation time 3266999015 ps
CPU time 61.6 seconds
Started Sep 24 04:30:18 AM UTC 24
Finished Sep 24 04:31:37 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2673859373 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 182.prim_prince_test.2673859373
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/182.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/183.prim_prince_test.4253930896
Short name T181
Test name
Test status
Simulation time 1827443382 ps
CPU time 35.15 seconds
Started Sep 24 04:30:24 AM UTC 24
Finished Sep 24 04:31:10 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4253930896 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 183.prim_prince_test.4253930896
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/183.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/184.prim_prince_test.3197152985
Short name T189
Test name
Test status
Simulation time 2306022319 ps
CPU time 44.79 seconds
Started Sep 24 04:30:30 AM UTC 24
Finished Sep 24 04:31:28 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3197152985 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 184.prim_prince_test.3197152985
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/184.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/185.prim_prince_test.1868405949
Short name T183
Test name
Test status
Simulation time 1678715808 ps
CPU time 31.09 seconds
Started Sep 24 04:30:34 AM UTC 24
Finished Sep 24 04:31:15 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1868405949 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 185.prim_prince_test.1868405949
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/185.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/186.prim_prince_test.38945705
Short name T180
Test name
Test status
Simulation time 1257563254 ps
CPU time 25.02 seconds
Started Sep 24 04:30:34 AM UTC 24
Finished Sep 24 04:31:07 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38945705 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 186.prim_prince_test.38945705
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/186.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/187.prim_prince_test.1388531071
Short name T198
Test name
Test status
Simulation time 2898873317 ps
CPU time 57.17 seconds
Started Sep 24 04:30:34 AM UTC 24
Finished Sep 24 04:31:48 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1388531071 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 187.prim_prince_test.1388531071
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/187.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/188.prim_prince_test.2745234503
Short name T179
Test name
Test status
Simulation time 1134960862 ps
CPU time 21.6 seconds
Started Sep 24 04:30:35 AM UTC 24
Finished Sep 24 04:31:04 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2745234503 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 188.prim_prince_test.2745234503
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/188.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/189.prim_prince_test.333556556
Short name T213
Test name
Test status
Simulation time 3728329338 ps
CPU time 68.38 seconds
Started Sep 24 04:30:36 AM UTC 24
Finished Sep 24 04:32:05 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=333556556 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 189.prim_prince_test.333556556
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/189.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/19.prim_prince_test.2822911169
Short name T17
Test name
Test status
Simulation time 2157462384 ps
CPU time 39.54 seconds
Started Sep 24 04:24:40 AM UTC 24
Finished Sep 24 04:25:32 AM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2822911169 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 19.prim_prince_test.2822911169
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/19.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/190.prim_prince_test.2473057473
Short name T176
Test name
Test status
Simulation time 788121240 ps
CPU time 15.58 seconds
Started Sep 24 04:30:38 AM UTC 24
Finished Sep 24 04:30:58 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2473057473 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 190.prim_prince_test.2473057473
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/190.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/191.prim_prince_test.2475226490
Short name T214
Test name
Test status
Simulation time 3561331897 ps
CPU time 69.56 seconds
Started Sep 24 04:30:39 AM UTC 24
Finished Sep 24 04:32:08 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2475226490 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 191.prim_prince_test.2475226490
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/191.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/192.prim_prince_test.1776209986
Short name T204
Test name
Test status
Simulation time 3341241338 ps
CPU time 61.67 seconds
Started Sep 24 04:30:41 AM UTC 24
Finished Sep 24 04:32:01 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1776209986 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 192.prim_prince_test.1776209986
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/192.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/193.prim_prince_test.1332087290
Short name T195
Test name
Test status
Simulation time 2531132359 ps
CPU time 47.61 seconds
Started Sep 24 04:30:42 AM UTC 24
Finished Sep 24 04:31:44 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1332087290 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 193.prim_prince_test.1332087290
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/193.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/194.prim_prince_test.4039125586
Short name T209
Test name
Test status
Simulation time 3315526688 ps
CPU time 60.96 seconds
Started Sep 24 04:30:44 AM UTC 24
Finished Sep 24 04:32:04 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4039125586 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 194.prim_prince_test.4039125586
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/194.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/195.prim_prince_test.2696737147
Short name T191
Test name
Test status
Simulation time 2096907041 ps
CPU time 41.5 seconds
Started Sep 24 04:30:44 AM UTC 24
Finished Sep 24 04:31:38 AM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2696737147 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 195.prim_prince_test.2696737147
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/195.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/196.prim_prince_test.2513071935
Short name T187
Test name
Test status
Simulation time 1554217219 ps
CPU time 30.92 seconds
Started Sep 24 04:30:45 AM UTC 24
Finished Sep 24 04:31:26 AM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2513071935 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 196.prim_prince_test.2513071935
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/196.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/197.prim_prince_test.2537379884
Short name T201
Test name
Test status
Simulation time 2723013632 ps
CPU time 52.2 seconds
Started Sep 24 04:30:45 AM UTC 24
Finished Sep 24 04:31:53 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2537379884 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 197.prim_prince_test.2537379884
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/197.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/198.prim_prince_test.2977770512
Short name T202
Test name
Test status
Simulation time 2757618611 ps
CPU time 52.69 seconds
Started Sep 24 04:30:46 AM UTC 24
Finished Sep 24 04:31:55 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2977770512 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 198.prim_prince_test.2977770512
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/198.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/199.prim_prince_test.29485049
Short name T210
Test name
Test status
Simulation time 3235589484 ps
CPU time 59.1 seconds
Started Sep 24 04:30:47 AM UTC 24
Finished Sep 24 04:32:05 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29485049 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 199.prim_prince_test.29485049
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/199.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/2.prim_prince_test.2786367591
Short name T12
Test name
Test status
Simulation time 2526807648 ps
CPU time 47.53 seconds
Started Sep 24 04:24:09 AM UTC 24
Finished Sep 24 04:25:10 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2786367591 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 2.prim_prince_test.2786367591
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/2.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/20.prim_prince_test.46038871
Short name T29
Test name
Test status
Simulation time 3154419946 ps
CPU time 58.54 seconds
Started Sep 24 04:24:48 AM UTC 24
Finished Sep 24 04:26:04 AM UTC 24
Peak memory 155048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=46038871 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 20.prim_prince_test.46038871
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/20.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/200.prim_prince_test.557598503
Short name T193
Test name
Test status
Simulation time 2024508855 ps
CPU time 40.12 seconds
Started Sep 24 04:30:48 AM UTC 24
Finished Sep 24 04:31:39 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=557598503 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 200.prim_prince_test.557598503
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/200.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/201.prim_prince_test.86635904
Short name T196
Test name
Test status
Simulation time 1826142359 ps
CPU time 36.51 seconds
Started Sep 24 04:30:58 AM UTC 24
Finished Sep 24 04:31:45 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=86635904 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 201.prim_prince_test.86635904
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/201.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/202.prim_prince_test.1737549980
Short name T217
Test name
Test status
Simulation time 3013464116 ps
CPU time 58.22 seconds
Started Sep 24 04:30:59 AM UTC 24
Finished Sep 24 04:32:13 AM UTC 24
Peak memory 154204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1737549980 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 202.prim_prince_test.1737549980
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/202.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/203.prim_prince_test.829817728
Short name T192
Test name
Test status
Simulation time 1546079518 ps
CPU time 30.22 seconds
Started Sep 24 04:30:59 AM UTC 24
Finished Sep 24 04:31:38 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=829817728 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 203.prim_prince_test.829817728
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/203.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/204.prim_prince_test.3827495941
Short name T206
Test name
Test status
Simulation time 2486704412 ps
CPU time 47.69 seconds
Started Sep 24 04:31:01 AM UTC 24
Finished Sep 24 04:32:03 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3827495941 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 204.prim_prince_test.3827495941
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/204.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/205.prim_prince_test.3684796337
Short name T203
Test name
Test status
Simulation time 2357277080 ps
CPU time 43.78 seconds
Started Sep 24 04:31:02 AM UTC 24
Finished Sep 24 04:31:59 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3684796337 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 205.prim_prince_test.3684796337
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/205.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/206.prim_prince_test.3899060307
Short name T211
Test name
Test status
Simulation time 2403919143 ps
CPU time 46.3 seconds
Started Sep 24 04:31:05 AM UTC 24
Finished Sep 24 04:32:05 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3899060307 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 206.prim_prince_test.3899060307
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/206.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/207.prim_prince_test.177686644
Short name T212
Test name
Test status
Simulation time 2253840159 ps
CPU time 44.09 seconds
Started Sep 24 04:31:08 AM UTC 24
Finished Sep 24 04:32:05 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=177686644 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 207.prim_prince_test.177686644
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/207.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/208.prim_prince_test.2644714775
Short name T199
Test name
Test status
Simulation time 1549996817 ps
CPU time 28.82 seconds
Started Sep 24 04:31:10 AM UTC 24
Finished Sep 24 04:31:48 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2644714775 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 208.prim_prince_test.2644714775
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/208.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/209.prim_prince_test.447229066
Short name T194
Test name
Test status
Simulation time 1079735287 ps
CPU time 21.71 seconds
Started Sep 24 04:31:14 AM UTC 24
Finished Sep 24 04:31:43 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=447229066 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 209.prim_prince_test.447229066
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/209.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/21.prim_prince_test.198868073
Short name T13
Test name
Test status
Simulation time 1248641693 ps
CPU time 23.22 seconds
Started Sep 24 04:24:53 AM UTC 24
Finished Sep 24 04:25:23 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=198868073 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 21.prim_prince_test.198868073
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/21.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/210.prim_prince_test.2765917646
Short name T218
Test name
Test status
Simulation time 2500543011 ps
CPU time 48.19 seconds
Started Sep 24 04:31:17 AM UTC 24
Finished Sep 24 04:32:18 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2765917646 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 210.prim_prince_test.2765917646
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/210.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/211.prim_prince_test.716803041
Short name T197
Test name
Test status
Simulation time 1047395800 ps
CPU time 21.17 seconds
Started Sep 24 04:31:19 AM UTC 24
Finished Sep 24 04:31:46 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=716803041 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 211.prim_prince_test.716803041
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/211.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/212.prim_prince_test.1889765414
Short name T226
Test name
Test status
Simulation time 3313518103 ps
CPU time 61.22 seconds
Started Sep 24 04:31:20 AM UTC 24
Finished Sep 24 04:32:39 AM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1889765414 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 212.prim_prince_test.1889765414
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/212.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/213.prim_prince_test.2949669571
Short name T215
Test name
Test status
Simulation time 1780093529 ps
CPU time 34.8 seconds
Started Sep 24 04:31:23 AM UTC 24
Finished Sep 24 04:32:08 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2949669571 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 213.prim_prince_test.2949669571
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/213.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/214.prim_prince_test.1781911254
Short name T200
Test name
Test status
Simulation time 836035127 ps
CPU time 16.91 seconds
Started Sep 24 04:31:26 AM UTC 24
Finished Sep 24 04:31:49 AM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1781911254 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 214.prim_prince_test.1781911254
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/214.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/215.prim_prince_test.629324160
Short name T222
Test name
Test status
Simulation time 2833318961 ps
CPU time 51.87 seconds
Started Sep 24 04:31:28 AM UTC 24
Finished Sep 24 04:32:35 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=629324160 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 215.prim_prince_test.629324160
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/215.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/216.prim_prince_test.834148487
Short name T207
Test name
Test status
Simulation time 1298580789 ps
CPU time 25.76 seconds
Started Sep 24 04:31:29 AM UTC 24
Finished Sep 24 04:32:03 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=834148487 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 216.prim_prince_test.834148487
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/216.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/217.prim_prince_test.62953510
Short name T205
Test name
Test status
Simulation time 882113774 ps
CPU time 17.32 seconds
Started Sep 24 04:31:38 AM UTC 24
Finished Sep 24 04:32:01 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=62953510 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 217.prim_prince_test.62953510
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/217.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/218.prim_prince_test.4209084034
Short name T223
Test name
Test status
Simulation time 2388550435 ps
CPU time 43.9 seconds
Started Sep 24 04:31:38 AM UTC 24
Finished Sep 24 04:32:36 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4209084034 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 218.prim_prince_test.4209084034
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/218.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/219.prim_prince_test.12677553
Short name T208
Test name
Test status
Simulation time 957658291 ps
CPU time 18.52 seconds
Started Sep 24 04:31:39 AM UTC 24
Finished Sep 24 04:32:03 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=12677553 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 219.prim_prince_test.12677553
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/219.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/22.prim_prince_test.3947327310
Short name T16
Test name
Test status
Simulation time 1432726657 ps
CPU time 27.97 seconds
Started Sep 24 04:24:55 AM UTC 24
Finished Sep 24 04:25:31 AM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3947327310 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 22.prim_prince_test.3947327310
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/22.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/220.prim_prince_test.2794302999
Short name T236
Test name
Test status
Simulation time 3456381266 ps
CPU time 64.05 seconds
Started Sep 24 04:31:41 AM UTC 24
Finished Sep 24 04:33:03 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2794302999 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 220.prim_prince_test.2794302999
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/220.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/221.prim_prince_test.1868956051
Short name T240
Test name
Test status
Simulation time 3554574504 ps
CPU time 67.12 seconds
Started Sep 24 04:31:44 AM UTC 24
Finished Sep 24 04:33:10 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1868956051 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 221.prim_prince_test.1868956051
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/221.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/222.prim_prince_test.2345727985
Short name T216
Test name
Test status
Simulation time 1163496452 ps
CPU time 21.51 seconds
Started Sep 24 04:31:45 AM UTC 24
Finished Sep 24 04:32:13 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2345727985 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 222.prim_prince_test.2345727985
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/222.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/223.prim_prince_test.3301504941
Short name T243
Test name
Test status
Simulation time 3734127449 ps
CPU time 69.24 seconds
Started Sep 24 04:31:46 AM UTC 24
Finished Sep 24 04:33:15 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3301504941 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 223.prim_prince_test.3301504941
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/223.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/224.prim_prince_test.1018151272
Short name T235
Test name
Test status
Simulation time 3089663426 ps
CPU time 56.43 seconds
Started Sep 24 04:31:47 AM UTC 24
Finished Sep 24 04:33:00 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1018151272 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 224.prim_prince_test.1018151272
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/224.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/225.prim_prince_test.1617019049
Short name T238
Test name
Test status
Simulation time 3142693143 ps
CPU time 59.04 seconds
Started Sep 24 04:31:48 AM UTC 24
Finished Sep 24 04:33:04 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1617019049 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 225.prim_prince_test.1617019049
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/225.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/226.prim_prince_test.1581223680
Short name T241
Test name
Test status
Simulation time 3432073984 ps
CPU time 63.91 seconds
Started Sep 24 04:31:49 AM UTC 24
Finished Sep 24 04:33:12 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1581223680 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 226.prim_prince_test.1581223680
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/226.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/227.prim_prince_test.1673925821
Short name T232
Test name
Test status
Simulation time 2598264653 ps
CPU time 48.46 seconds
Started Sep 24 04:31:49 AM UTC 24
Finished Sep 24 04:32:52 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1673925821 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 227.prim_prince_test.1673925821
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/227.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/228.prim_prince_test.593185259
Short name T231
Test name
Test status
Simulation time 2219714767 ps
CPU time 40.85 seconds
Started Sep 24 04:31:53 AM UTC 24
Finished Sep 24 04:32:47 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=593185259 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 228.prim_prince_test.593185259
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/228.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/229.prim_prince_test.962809893
Short name T221
Test name
Test status
Simulation time 1537977565 ps
CPU time 29.21 seconds
Started Sep 24 04:31:56 AM UTC 24
Finished Sep 24 04:32:34 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=962809893 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 229.prim_prince_test.962809893
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/229.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/23.prim_prince_test.901508272
Short name T22
Test name
Test status
Simulation time 1805140207 ps
CPU time 34.33 seconds
Started Sep 24 04:24:55 AM UTC 24
Finished Sep 24 04:25:39 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=901508272 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 23.prim_prince_test.901508272
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/23.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/230.prim_prince_test.3699256347
Short name T229
Test name
Test status
Simulation time 1890697854 ps
CPU time 34.51 seconds
Started Sep 24 04:32:00 AM UTC 24
Finished Sep 24 04:32:45 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3699256347 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 230.prim_prince_test.3699256347
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/230.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/231.prim_prince_test.1244939322
Short name T220
Test name
Test status
Simulation time 1083500329 ps
CPU time 20.19 seconds
Started Sep 24 04:32:02 AM UTC 24
Finished Sep 24 04:32:29 AM UTC 24
Peak memory 154968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1244939322 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 231.prim_prince_test.1244939322
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/231.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/232.prim_prince_test.220311411
Short name T219
Test name
Test status
Simulation time 794848754 ps
CPU time 15.17 seconds
Started Sep 24 04:32:02 AM UTC 24
Finished Sep 24 04:32:23 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=220311411 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 232.prim_prince_test.220311411
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/232.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/233.prim_prince_test.2000665053
Short name T224
Test name
Test status
Simulation time 1333252968 ps
CPU time 25.07 seconds
Started Sep 24 04:32:03 AM UTC 24
Finished Sep 24 04:32:36 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2000665053 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 233.prim_prince_test.2000665053
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/233.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/234.prim_prince_test.2374335769
Short name T247
Test name
Test status
Simulation time 3174457928 ps
CPU time 57.6 seconds
Started Sep 24 04:32:03 AM UTC 24
Finished Sep 24 04:33:19 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2374335769 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 234.prim_prince_test.2374335769
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/234.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/235.prim_prince_test.2186607842
Short name T230
Test name
Test status
Simulation time 1711291441 ps
CPU time 31.83 seconds
Started Sep 24 04:32:03 AM UTC 24
Finished Sep 24 04:32:45 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2186607842 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 235.prim_prince_test.2186607842
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/235.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/236.prim_prince_test.1781802018
Short name T248
Test name
Test status
Simulation time 3172464641 ps
CPU time 59.1 seconds
Started Sep 24 04:32:04 AM UTC 24
Finished Sep 24 04:33:21 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1781802018 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 236.prim_prince_test.1781802018
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/236.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/237.prim_prince_test.160053554
Short name T225
Test name
Test status
Simulation time 1322918047 ps
CPU time 24.83 seconds
Started Sep 24 04:32:06 AM UTC 24
Finished Sep 24 04:32:38 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=160053554 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 237.prim_prince_test.160053554
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/237.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/238.prim_prince_test.4263548098
Short name T228
Test name
Test status
Simulation time 1622386503 ps
CPU time 29.76 seconds
Started Sep 24 04:32:06 AM UTC 24
Finished Sep 24 04:32:45 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4263548098 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 238.prim_prince_test.4263548098
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/238.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/239.prim_prince_test.3602527112
Short name T234
Test name
Test status
Simulation time 2143599202 ps
CPU time 38.82 seconds
Started Sep 24 04:32:06 AM UTC 24
Finished Sep 24 04:32:57 AM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3602527112 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 239.prim_prince_test.3602527112
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/239.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/24.prim_prince_test.1276967903
Short name T26
Test name
Test status
Simulation time 2494096412 ps
CPU time 46.15 seconds
Started Sep 24 04:24:56 AM UTC 24
Finished Sep 24 04:25:56 AM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1276967903 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 24.prim_prince_test.1276967903
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/24.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/240.prim_prince_test.3973509416
Short name T252
Test name
Test status
Simulation time 3621189792 ps
CPU time 68.47 seconds
Started Sep 24 04:32:07 AM UTC 24
Finished Sep 24 04:33:35 AM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3973509416 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 240.prim_prince_test.3973509416
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/240.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/241.prim_prince_test.3908814479
Short name T244
Test name
Test status
Simulation time 2851410286 ps
CPU time 52.49 seconds
Started Sep 24 04:32:09 AM UTC 24
Finished Sep 24 04:33:17 AM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3908814479 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 241.prim_prince_test.3908814479
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/241.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/242.prim_prince_test.2960765129
Short name T242
Test name
Test status
Simulation time 2658798178 ps
CPU time 49.22 seconds
Started Sep 24 04:32:09 AM UTC 24
Finished Sep 24 04:33:13 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2960765129 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 242.prim_prince_test.2960765129
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/242.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/243.prim_prince_test.1701937080
Short name T227
Test name
Test status
Simulation time 1137430648 ps
CPU time 21.28 seconds
Started Sep 24 04:32:14 AM UTC 24
Finished Sep 24 04:32:42 AM UTC 24
Peak memory 154964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1701937080 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 243.prim_prince_test.1701937080
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/243.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/244.prim_prince_test.3042062340
Short name T251
Test name
Test status
Simulation time 3318138599 ps
CPU time 60.58 seconds
Started Sep 24 04:32:14 AM UTC 24
Finished Sep 24 04:33:33 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3042062340 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 244.prim_prince_test.3042062340
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/244.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/245.prim_prince_test.1002339344
Short name T246
Test name
Test status
Simulation time 2395897705 ps
CPU time 45.74 seconds
Started Sep 24 04:32:19 AM UTC 24
Finished Sep 24 04:33:18 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1002339344 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 245.prim_prince_test.1002339344
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/245.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/246.prim_prince_test.2445733677
Short name T233
Test name
Test status
Simulation time 1261750855 ps
CPU time 23.15 seconds
Started Sep 24 04:32:23 AM UTC 24
Finished Sep 24 04:32:54 AM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2445733677 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 246.prim_prince_test.2445733677
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/246.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/247.prim_prince_test.3110980577
Short name T260
Test name
Test status
Simulation time 3370942996 ps
CPU time 61.02 seconds
Started Sep 24 04:32:31 AM UTC 24
Finished Sep 24 04:33:50 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3110980577 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 247.prim_prince_test.3110980577
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/247.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/248.prim_prince_test.774170465
Short name T255
Test name
Test status
Simulation time 2865386322 ps
CPU time 52.07 seconds
Started Sep 24 04:32:35 AM UTC 24
Finished Sep 24 04:33:43 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=774170465 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 248.prim_prince_test.774170465
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/248.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/249.prim_prince_test.3238394870
Short name T237
Test name
Test status
Simulation time 1086175484 ps
CPU time 20.09 seconds
Started Sep 24 04:32:37 AM UTC 24
Finished Sep 24 04:33:04 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3238394870 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 249.prim_prince_test.3238394870
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/249.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/25.prim_prince_test.3218088931
Short name T19
Test name
Test status
Simulation time 1512326704 ps
CPU time 29.63 seconds
Started Sep 24 04:24:57 AM UTC 24
Finished Sep 24 04:25:35 AM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3218088931 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 25.prim_prince_test.3218088931
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/25.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/250.prim_prince_test.3240346746
Short name T245
Test name
Test status
Simulation time 1667628665 ps
CPU time 30.64 seconds
Started Sep 24 04:32:37 AM UTC 24
Finished Sep 24 04:33:17 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3240346746 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 250.prim_prince_test.3240346746
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/250.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/251.prim_prince_test.1607933311
Short name T254
Test name
Test status
Simulation time 2590406060 ps
CPU time 47.52 seconds
Started Sep 24 04:32:37 AM UTC 24
Finished Sep 24 04:33:39 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1607933311 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 251.prim_prince_test.1607933311
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/251.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/252.prim_prince_test.605352893
Short name T250
Test name
Test status
Simulation time 1809870054 ps
CPU time 34.08 seconds
Started Sep 24 04:32:39 AM UTC 24
Finished Sep 24 04:33:23 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=605352893 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 252.prim_prince_test.605352893
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/252.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/253.prim_prince_test.4156625570
Short name T264
Test name
Test status
Simulation time 3431559382 ps
CPU time 62.02 seconds
Started Sep 24 04:32:40 AM UTC 24
Finished Sep 24 04:34:01 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4156625570 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 253.prim_prince_test.4156625570
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/253.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/254.prim_prince_test.2068657186
Short name T265
Test name
Test status
Simulation time 3141732120 ps
CPU time 60.37 seconds
Started Sep 24 04:32:43 AM UTC 24
Finished Sep 24 04:34:01 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2068657186 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 254.prim_prince_test.2068657186
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/254.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/255.prim_prince_test.3783240840
Short name T259
Test name
Test status
Simulation time 2536540753 ps
CPU time 48.85 seconds
Started Sep 24 04:32:46 AM UTC 24
Finished Sep 24 04:33:48 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3783240840 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 255.prim_prince_test.3783240840
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/255.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/256.prim_prince_test.2199994533
Short name T262
Test name
Test status
Simulation time 2692507910 ps
CPU time 50.44 seconds
Started Sep 24 04:32:46 AM UTC 24
Finished Sep 24 04:33:51 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2199994533 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 256.prim_prince_test.2199994533
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/256.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/257.prim_prince_test.1085037816
Short name T268
Test name
Test status
Simulation time 3352622356 ps
CPU time 60.81 seconds
Started Sep 24 04:32:46 AM UTC 24
Finished Sep 24 04:34:05 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1085037816 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 257.prim_prince_test.1085037816
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/257.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/258.prim_prince_test.2104180194
Short name T239
Test name
Test status
Simulation time 841256800 ps
CPU time 15.71 seconds
Started Sep 24 04:32:48 AM UTC 24
Finished Sep 24 04:33:09 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2104180194 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 258.prim_prince_test.2104180194
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/258.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/259.prim_prince_test.3489412757
Short name T269
Test name
Test status
Simulation time 2928557299 ps
CPU time 56.31 seconds
Started Sep 24 04:32:53 AM UTC 24
Finished Sep 24 04:34:05 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3489412757 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 259.prim_prince_test.3489412757
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/259.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/26.prim_prince_test.93942172
Short name T33
Test name
Test status
Simulation time 3294494432 ps
CPU time 61.35 seconds
Started Sep 24 04:24:58 AM UTC 24
Finished Sep 24 04:26:17 AM UTC 24
Peak memory 155048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=93942172 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 26.prim_prince_test.93942172
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/26.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/260.prim_prince_test.3107176560
Short name T249
Test name
Test status
Simulation time 1032846613 ps
CPU time 19.54 seconds
Started Sep 24 04:32:55 AM UTC 24
Finished Sep 24 04:33:21 AM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3107176560 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 260.prim_prince_test.3107176560
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/260.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/261.prim_prince_test.1510359679
Short name T253
Test name
Test status
Simulation time 1689399440 ps
CPU time 31.25 seconds
Started Sep 24 04:32:57 AM UTC 24
Finished Sep 24 04:33:38 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1510359679 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 261.prim_prince_test.1510359679
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/261.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/262.prim_prince_test.3412392398
Short name T261
Test name
Test status
Simulation time 1961323243 ps
CPU time 37.46 seconds
Started Sep 24 04:33:01 AM UTC 24
Finished Sep 24 04:33:50 AM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3412392398 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 262.prim_prince_test.3412392398
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/262.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/263.prim_prince_test.2504645768
Short name T258
Test name
Test status
Simulation time 1728796108 ps
CPU time 31.8 seconds
Started Sep 24 04:33:04 AM UTC 24
Finished Sep 24 04:33:46 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2504645768 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 263.prim_prince_test.2504645768
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/263.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/264.prim_prince_test.981178821
Short name T274
Test name
Test status
Simulation time 2750706512 ps
CPU time 52.27 seconds
Started Sep 24 04:33:05 AM UTC 24
Finished Sep 24 04:34:12 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=981178821 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 264.prim_prince_test.981178821
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/264.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/265.prim_prince_test.3167899339
Short name T263
Test name
Test status
Simulation time 2232418674 ps
CPU time 41.34 seconds
Started Sep 24 04:33:06 AM UTC 24
Finished Sep 24 04:33:59 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3167899339 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 265.prim_prince_test.3167899339
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/265.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/266.prim_prince_test.2266832892
Short name T279
Test name
Test status
Simulation time 3341422321 ps
CPU time 60.35 seconds
Started Sep 24 04:33:10 AM UTC 24
Finished Sep 24 04:34:28 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2266832892 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 266.prim_prince_test.2266832892
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/266.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/267.prim_prince_test.1696748197
Short name T266
Test name
Test status
Simulation time 2126987554 ps
CPU time 40.17 seconds
Started Sep 24 04:33:11 AM UTC 24
Finished Sep 24 04:34:03 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1696748197 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 267.prim_prince_test.1696748197
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/267.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/268.prim_prince_test.4248206561
Short name T276
Test name
Test status
Simulation time 2558035094 ps
CPU time 46.61 seconds
Started Sep 24 04:33:13 AM UTC 24
Finished Sep 24 04:34:14 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4248206561 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 268.prim_prince_test.4248206561
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/268.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/269.prim_prince_test.1919689325
Short name T256
Test name
Test status
Simulation time 1202340464 ps
CPU time 23.01 seconds
Started Sep 24 04:33:14 AM UTC 24
Finished Sep 24 04:33:44 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1919689325 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 269.prim_prince_test.1919689325
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/269.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/27.prim_prince_test.398269902
Short name T31
Test name
Test status
Simulation time 2801657871 ps
CPU time 52.64 seconds
Started Sep 24 04:25:01 AM UTC 24
Finished Sep 24 04:26:09 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=398269902 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 27.prim_prince_test.398269902
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/27.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/270.prim_prince_test.3618052666
Short name T267
Test name
Test status
Simulation time 1957261474 ps
CPU time 37.39 seconds
Started Sep 24 04:33:16 AM UTC 24
Finished Sep 24 04:34:05 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3618052666 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 270.prim_prince_test.3618052666
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/270.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/271.prim_prince_test.17364411
Short name T257
Test name
Test status
Simulation time 1105399172 ps
CPU time 21.48 seconds
Started Sep 24 04:33:17 AM UTC 24
Finished Sep 24 04:33:46 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=17364411 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 271.prim_prince_test.17364411
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/271.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/272.prim_prince_test.3040460020
Short name T277
Test name
Test status
Simulation time 2713439532 ps
CPU time 50.48 seconds
Started Sep 24 04:33:19 AM UTC 24
Finished Sep 24 04:34:24 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3040460020 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 272.prim_prince_test.3040460020
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/272.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/273.prim_prince_test.4208586268
Short name T285
Test name
Test status
Simulation time 3283647733 ps
CPU time 60.73 seconds
Started Sep 24 04:33:20 AM UTC 24
Finished Sep 24 04:34:38 AM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4208586268 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 273.prim_prince_test.4208586268
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/273.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/274.prim_prince_test.3590788610
Short name T281
Test name
Test status
Simulation time 3065041778 ps
CPU time 56.66 seconds
Started Sep 24 04:33:20 AM UTC 24
Finished Sep 24 04:34:33 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3590788610 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 274.prim_prince_test.3590788610
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/274.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/275.prim_prince_test.2440483338
Short name T280
Test name
Test status
Simulation time 2945471033 ps
CPU time 53.73 seconds
Started Sep 24 04:33:22 AM UTC 24
Finished Sep 24 04:34:32 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2440483338 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 275.prim_prince_test.2440483338
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/275.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/276.prim_prince_test.2380528019
Short name T271
Test name
Test status
Simulation time 1835808162 ps
CPU time 34.87 seconds
Started Sep 24 04:33:22 AM UTC 24
Finished Sep 24 04:34:07 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2380528019 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 276.prim_prince_test.2380528019
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/276.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/277.prim_prince_test.3902549171
Short name T286
Test name
Test status
Simulation time 3166285345 ps
CPU time 58.27 seconds
Started Sep 24 04:33:24 AM UTC 24
Finished Sep 24 04:34:39 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3902549171 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 277.prim_prince_test.3902549171
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/277.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/278.prim_prince_test.178516318
Short name T294
Test name
Test status
Simulation time 3699226783 ps
CPU time 67.2 seconds
Started Sep 24 04:33:34 AM UTC 24
Finished Sep 24 04:35:02 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=178516318 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 278.prim_prince_test.178516318
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/278.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/279.prim_prince_test.3770017910
Short name T273
Test name
Test status
Simulation time 1416813932 ps
CPU time 26.12 seconds
Started Sep 24 04:33:35 AM UTC 24
Finished Sep 24 04:34:11 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3770017910 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 279.prim_prince_test.3770017910
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/279.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/28.prim_prince_test.493999550
Short name T30
Test name
Test status
Simulation time 2550438480 ps
CPU time 49.44 seconds
Started Sep 24 04:25:02 AM UTC 24
Finished Sep 24 04:26:05 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=493999550 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 28.prim_prince_test.493999550
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/28.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/280.prim_prince_test.3076619852
Short name T272
Test name
Test status
Simulation time 1291828076 ps
CPU time 24.27 seconds
Started Sep 24 04:33:39 AM UTC 24
Finished Sep 24 04:34:10 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3076619852 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 280.prim_prince_test.3076619852
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/280.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/281.prim_prince_test.2074451561
Short name T275
Test name
Test status
Simulation time 1351626573 ps
CPU time 25.14 seconds
Started Sep 24 04:33:40 AM UTC 24
Finished Sep 24 04:34:13 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2074451561 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 281.prim_prince_test.2074451561
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/281.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/282.prim_prince_test.4287443865
Short name T283
Test name
Test status
Simulation time 2199486420 ps
CPU time 40.97 seconds
Started Sep 24 04:33:44 AM UTC 24
Finished Sep 24 04:34:37 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4287443865 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 282.prim_prince_test.4287443865
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/282.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/283.prim_prince_test.2581594237
Short name T288
Test name
Test status
Simulation time 2874055618 ps
CPU time 52.05 seconds
Started Sep 24 04:33:45 AM UTC 24
Finished Sep 24 04:34:53 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2581594237 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 283.prim_prince_test.2581594237
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/283.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/284.prim_prince_test.3417685816
Short name T291
Test name
Test status
Simulation time 2982877799 ps
CPU time 54.8 seconds
Started Sep 24 04:33:46 AM UTC 24
Finished Sep 24 04:34:58 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3417685816 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 284.prim_prince_test.3417685816
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/284.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/285.prim_prince_test.1076551533
Short name T270
Test name
Test status
Simulation time 755868258 ps
CPU time 14.53 seconds
Started Sep 24 04:33:47 AM UTC 24
Finished Sep 24 04:34:07 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1076551533 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 285.prim_prince_test.1076551533
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/285.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/286.prim_prince_test.340110505
Short name T295
Test name
Test status
Simulation time 3067303089 ps
CPU time 56.95 seconds
Started Sep 24 04:33:49 AM UTC 24
Finished Sep 24 04:35:03 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=340110505 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 286.prim_prince_test.340110505
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/286.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/287.prim_prince_test.2454558119
Short name T290
Test name
Test status
Simulation time 2709038816 ps
CPU time 51.23 seconds
Started Sep 24 04:33:50 AM UTC 24
Finished Sep 24 04:34:57 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2454558119 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 287.prim_prince_test.2454558119
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/287.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/288.prim_prince_test.1144479075
Short name T301
Test name
Test status
Simulation time 3321673992 ps
CPU time 60.73 seconds
Started Sep 24 04:33:51 AM UTC 24
Finished Sep 24 04:35:09 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1144479075 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 288.prim_prince_test.1144479075
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/288.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/289.prim_prince_test.2150456123
Short name T278
Test name
Test status
Simulation time 1399961295 ps
CPU time 25.75 seconds
Started Sep 24 04:33:52 AM UTC 24
Finished Sep 24 04:34:26 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2150456123 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 289.prim_prince_test.2150456123
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/289.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/29.prim_prince_test.1250395198
Short name T24
Test name
Test status
Simulation time 1944441232 ps
CPU time 35.84 seconds
Started Sep 24 04:25:07 AM UTC 24
Finished Sep 24 04:25:53 AM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1250395198 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 29.prim_prince_test.1250395198
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/29.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/290.prim_prince_test.2173284470
Short name T302
Test name
Test status
Simulation time 3021970325 ps
CPU time 54.74 seconds
Started Sep 24 04:34:00 AM UTC 24
Finished Sep 24 04:35:11 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2173284470 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 290.prim_prince_test.2173284470
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/290.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/291.prim_prince_test.548177508
Short name T299
Test name
Test status
Simulation time 2639261804 ps
CPU time 48.45 seconds
Started Sep 24 04:34:02 AM UTC 24
Finished Sep 24 04:35:05 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=548177508 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 291.prim_prince_test.548177508
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/291.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/292.prim_prince_test.2098922796
Short name T297
Test name
Test status
Simulation time 2555023163 ps
CPU time 48.57 seconds
Started Sep 24 04:34:02 AM UTC 24
Finished Sep 24 04:35:05 AM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2098922796 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 292.prim_prince_test.2098922796
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/292.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/293.prim_prince_test.986424652
Short name T303
Test name
Test status
Simulation time 2824406549 ps
CPU time 53.63 seconds
Started Sep 24 04:34:03 AM UTC 24
Finished Sep 24 04:35:12 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=986424652 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 293.prim_prince_test.986424652
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/293.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/294.prim_prince_test.2672763591
Short name T298
Test name
Test status
Simulation time 2423649670 ps
CPU time 45.91 seconds
Started Sep 24 04:34:05 AM UTC 24
Finished Sep 24 04:35:05 AM UTC 24
Peak memory 154960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2672763591 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 294.prim_prince_test.2672763591
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/294.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/295.prim_prince_test.3127186489
Short name T282
Test name
Test status
Simulation time 1282578277 ps
CPU time 23.81 seconds
Started Sep 24 04:34:05 AM UTC 24
Finished Sep 24 04:34:37 AM UTC 24
Peak memory 154908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3127186489 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 295.prim_prince_test.3127186489
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/295.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/296.prim_prince_test.980260659
Short name T309
Test name
Test status
Simulation time 3114971863 ps
CPU time 56.53 seconds
Started Sep 24 04:34:07 AM UTC 24
Finished Sep 24 04:35:20 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=980260659 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 296.prim_prince_test.980260659
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/296.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/297.prim_prince_test.3496530238
Short name T300
Test name
Test status
Simulation time 2406869130 ps
CPU time 45.51 seconds
Started Sep 24 04:34:08 AM UTC 24
Finished Sep 24 04:35:07 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3496530238 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 297.prim_prince_test.3496530238
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/297.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/298.prim_prince_test.1331552787
Short name T289
Test name
Test status
Simulation time 1875092085 ps
CPU time 35.8 seconds
Started Sep 24 04:34:09 AM UTC 24
Finished Sep 24 04:34:55 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1331552787 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 298.prim_prince_test.1331552787
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/298.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/299.prim_prince_test.4235999107
Short name T293
Test name
Test status
Simulation time 2046041139 ps
CPU time 37.69 seconds
Started Sep 24 04:34:11 AM UTC 24
Finished Sep 24 04:35:00 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4235999107 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 299.prim_prince_test.4235999107
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/299.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/3.prim_prince_test.2119442626
Short name T10
Test name
Test status
Simulation time 2311743816 ps
CPU time 43.59 seconds
Started Sep 24 04:24:10 AM UTC 24
Finished Sep 24 04:25:07 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2119442626 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 3.prim_prince_test.2119442626
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/3.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/30.prim_prince_test.3567690603
Short name T40
Test name
Test status
Simulation time 3329323886 ps
CPU time 61.52 seconds
Started Sep 24 04:25:08 AM UTC 24
Finished Sep 24 04:26:27 AM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3567690603 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 30.prim_prince_test.3567690603
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/30.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/300.prim_prince_test.2194051536
Short name T284
Test name
Test status
Simulation time 1027916124 ps
CPU time 19.7 seconds
Started Sep 24 04:34:12 AM UTC 24
Finished Sep 24 04:34:38 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2194051536 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 300.prim_prince_test.2194051536
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/300.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/301.prim_prince_test.2628164894
Short name T292
Test name
Test status
Simulation time 1851991515 ps
CPU time 33.91 seconds
Started Sep 24 04:34:13 AM UTC 24
Finished Sep 24 04:34:58 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2628164894 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 301.prim_prince_test.2628164894
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/301.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/302.prim_prince_test.2890596656
Short name T296
Test name
Test status
Simulation time 2103122025 ps
CPU time 39.28 seconds
Started Sep 24 04:34:13 AM UTC 24
Finished Sep 24 04:35:04 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2890596656 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 302.prim_prince_test.2890596656
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/302.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/303.prim_prince_test.2669165524
Short name T287
Test name
Test status
Simulation time 1145450652 ps
CPU time 21.85 seconds
Started Sep 24 04:34:14 AM UTC 24
Finished Sep 24 04:34:43 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2669165524 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 303.prim_prince_test.2669165524
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/303.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/304.prim_prince_test.669104656
Short name T323
Test name
Test status
Simulation time 3494459556 ps
CPU time 65.52 seconds
Started Sep 24 04:34:25 AM UTC 24
Finished Sep 24 04:35:49 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=669104656 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 304.prim_prince_test.669104656
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/304.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/305.prim_prince_test.1811878127
Short name T311
Test name
Test status
Simulation time 2463332463 ps
CPU time 46.57 seconds
Started Sep 24 04:34:27 AM UTC 24
Finished Sep 24 04:35:27 AM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1811878127 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 305.prim_prince_test.1811878127
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/305.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/306.prim_prince_test.3738779560
Short name T322
Test name
Test status
Simulation time 3323311996 ps
CPU time 62.18 seconds
Started Sep 24 04:34:29 AM UTC 24
Finished Sep 24 04:35:49 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3738779560 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 306.prim_prince_test.3738779560
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/306.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/307.prim_prince_test.3960115889
Short name T317
Test name
Test status
Simulation time 2684799300 ps
CPU time 51.16 seconds
Started Sep 24 04:34:33 AM UTC 24
Finished Sep 24 04:35:39 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3960115889 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 307.prim_prince_test.3960115889
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/307.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/308.prim_prince_test.858846691
Short name T315
Test name
Test status
Simulation time 2517399569 ps
CPU time 45.72 seconds
Started Sep 24 04:34:34 AM UTC 24
Finished Sep 24 04:35:34 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=858846691 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 308.prim_prince_test.858846691
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/308.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/309.prim_prince_test.2887301071
Short name T306
Test name
Test status
Simulation time 1497703140 ps
CPU time 28.79 seconds
Started Sep 24 04:34:37 AM UTC 24
Finished Sep 24 04:35:15 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2887301071 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 309.prim_prince_test.2887301071
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/309.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/31.prim_prince_test.212322948
Short name T45
Test name
Test status
Simulation time 3573719756 ps
CPU time 69.19 seconds
Started Sep 24 04:25:11 AM UTC 24
Finished Sep 24 04:26:39 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=212322948 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 31.prim_prince_test.212322948
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/31.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/310.prim_prince_test.2784859023
Short name T316
Test name
Test status
Simulation time 2461921637 ps
CPU time 46.14 seconds
Started Sep 24 04:34:38 AM UTC 24
Finished Sep 24 04:35:38 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2784859023 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 310.prim_prince_test.2784859023
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/310.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/311.prim_prince_test.1142681844
Short name T307
Test name
Test status
Simulation time 1673799483 ps
CPU time 30.94 seconds
Started Sep 24 04:34:39 AM UTC 24
Finished Sep 24 04:35:19 AM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1142681844 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 311.prim_prince_test.1142681844
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/311.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/312.prim_prince_test.3431597693
Short name T305
Test name
Test status
Simulation time 1378833216 ps
CPU time 25.57 seconds
Started Sep 24 04:34:40 AM UTC 24
Finished Sep 24 04:35:13 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3431597693 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 312.prim_prince_test.3431597693
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/312.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/313.prim_prince_test.804250161
Short name T304
Test name
Test status
Simulation time 1281247815 ps
CPU time 24.41 seconds
Started Sep 24 04:34:41 AM UTC 24
Finished Sep 24 04:35:13 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=804250161 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 313.prim_prince_test.804250161
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/313.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/314.prim_prince_test.2982804393
Short name T330
Test name
Test status
Simulation time 3240298700 ps
CPU time 60.93 seconds
Started Sep 24 04:34:44 AM UTC 24
Finished Sep 24 04:36:02 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2982804393 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 314.prim_prince_test.2982804393
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/314.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/315.prim_prince_test.3048897871
Short name T326
Test name
Test status
Simulation time 2612164528 ps
CPU time 47.67 seconds
Started Sep 24 04:34:54 AM UTC 24
Finished Sep 24 04:35:56 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3048897871 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 315.prim_prince_test.3048897871
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/315.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/316.prim_prince_test.4028027448
Short name T310
Test name
Test status
Simulation time 1099102832 ps
CPU time 20.35 seconds
Started Sep 24 04:34:56 AM UTC 24
Finished Sep 24 04:35:23 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4028027448 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 316.prim_prince_test.4028027448
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/316.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/317.prim_prince_test.421155280
Short name T321
Test name
Test status
Simulation time 2098909801 ps
CPU time 38.87 seconds
Started Sep 24 04:34:57 AM UTC 24
Finished Sep 24 04:35:48 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=421155280 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 317.prim_prince_test.421155280
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/317.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/318.prim_prince_test.2968888162
Short name T318
Test name
Test status
Simulation time 1877330556 ps
CPU time 34.34 seconds
Started Sep 24 04:34:59 AM UTC 24
Finished Sep 24 04:35:44 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2968888162 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 318.prim_prince_test.2968888162
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/318.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/319.prim_prince_test.3296508861
Short name T308
Test name
Test status
Simulation time 811368760 ps
CPU time 15.51 seconds
Started Sep 24 04:34:59 AM UTC 24
Finished Sep 24 04:35:19 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3296508861 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 319.prim_prince_test.3296508861
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/319.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/32.prim_prince_test.945965501
Short name T32
Test name
Test status
Simulation time 2642051599 ps
CPU time 49.61 seconds
Started Sep 24 04:25:11 AM UTC 24
Finished Sep 24 04:26:15 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=945965501 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 32.prim_prince_test.945965501
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/32.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/320.prim_prince_test.4097007200
Short name T314
Test name
Test status
Simulation time 1267364117 ps
CPU time 23.61 seconds
Started Sep 24 04:35:01 AM UTC 24
Finished Sep 24 04:35:32 AM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4097007200 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 320.prim_prince_test.4097007200
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/320.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/321.prim_prince_test.3753653761
Short name T313
Test name
Test status
Simulation time 1157719283 ps
CPU time 21.72 seconds
Started Sep 24 04:35:03 AM UTC 24
Finished Sep 24 04:35:32 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3753653761 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 321.prim_prince_test.3753653761
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/321.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/322.prim_prince_test.215542896
Short name T320
Test name
Test status
Simulation time 1777962306 ps
CPU time 33.52 seconds
Started Sep 24 04:35:04 AM UTC 24
Finished Sep 24 04:35:48 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=215542896 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 322.prim_prince_test.215542896
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/322.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/323.prim_prince_test.327742945
Short name T312
Test name
Test status
Simulation time 889011451 ps
CPU time 17.38 seconds
Started Sep 24 04:35:05 AM UTC 24
Finished Sep 24 04:35:28 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=327742945 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 323.prim_prince_test.327742945
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/323.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/324.prim_prince_test.1363166910
Short name T338
Test name
Test status
Simulation time 2881382262 ps
CPU time 52.86 seconds
Started Sep 24 04:35:05 AM UTC 24
Finished Sep 24 04:36:14 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1363166910 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 324.prim_prince_test.1363166910
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/324.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/325.prim_prince_test.1749283145
Short name T341
Test name
Test status
Simulation time 3613445621 ps
CPU time 66.59 seconds
Started Sep 24 04:35:05 AM UTC 24
Finished Sep 24 04:36:32 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1749283145 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 325.prim_prince_test.1749283145
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/325.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/326.prim_prince_test.599277357
Short name T336
Test name
Test status
Simulation time 2641906819 ps
CPU time 50.76 seconds
Started Sep 24 04:35:07 AM UTC 24
Finished Sep 24 04:36:12 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=599277357 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 326.prim_prince_test.599277357
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/326.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/327.prim_prince_test.2328090105
Short name T328
Test name
Test status
Simulation time 2212326325 ps
CPU time 41.5 seconds
Started Sep 24 04:35:08 AM UTC 24
Finished Sep 24 04:36:02 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2328090105 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 327.prim_prince_test.2328090105
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/327.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/328.prim_prince_test.2784414887
Short name T333
Test name
Test status
Simulation time 2381926979 ps
CPU time 45.79 seconds
Started Sep 24 04:35:10 AM UTC 24
Finished Sep 24 04:36:09 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2784414887 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 328.prim_prince_test.2784414887
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/328.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/329.prim_prince_test.1887982098
Short name T324
Test name
Test status
Simulation time 1566006601 ps
CPU time 28.74 seconds
Started Sep 24 04:35:12 AM UTC 24
Finished Sep 24 04:35:50 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1887982098 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 329.prim_prince_test.1887982098
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/329.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/33.prim_prince_test.3786855843
Short name T23
Test name
Test status
Simulation time 1160097856 ps
CPU time 23.09 seconds
Started Sep 24 04:25:13 AM UTC 24
Finished Sep 24 04:25:43 AM UTC 24
Peak memory 154960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3786855843 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 33.prim_prince_test.3786855843
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/33.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/330.prim_prince_test.165415253
Short name T331
Test name
Test status
Simulation time 2191003495 ps
CPU time 40.07 seconds
Started Sep 24 04:35:13 AM UTC 24
Finished Sep 24 04:36:06 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=165415253 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 330.prim_prince_test.165415253
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/330.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/331.prim_prince_test.2293398197
Short name T339
Test name
Test status
Simulation time 2591668914 ps
CPU time 49.82 seconds
Started Sep 24 04:35:13 AM UTC 24
Finished Sep 24 04:36:17 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2293398197 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 331.prim_prince_test.2293398197
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/331.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/332.prim_prince_test.1655041973
Short name T319
Test name
Test status
Simulation time 1305824183 ps
CPU time 24.32 seconds
Started Sep 24 04:35:14 AM UTC 24
Finished Sep 24 04:35:46 AM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1655041973 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 332.prim_prince_test.1655041973
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/332.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/333.prim_prince_test.1084476359
Short name T348
Test name
Test status
Simulation time 3562778877 ps
CPU time 65.38 seconds
Started Sep 24 04:35:16 AM UTC 24
Finished Sep 24 04:36:40 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1084476359 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 333.prim_prince_test.1084476359
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/333.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/334.prim_prince_test.1581323194
Short name T335
Test name
Test status
Simulation time 2156287473 ps
CPU time 39.41 seconds
Started Sep 24 04:35:20 AM UTC 24
Finished Sep 24 04:36:11 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1581323194 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 334.prim_prince_test.1581323194
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/334.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/335.prim_prince_test.1854873639
Short name T334
Test name
Test status
Simulation time 2108898413 ps
CPU time 38.61 seconds
Started Sep 24 04:35:20 AM UTC 24
Finished Sep 24 04:36:10 AM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1854873639 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 335.prim_prince_test.1854873639
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/335.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/336.prim_prince_test.3923589752
Short name T350
Test name
Test status
Simulation time 3486636364 ps
CPU time 63.73 seconds
Started Sep 24 04:35:21 AM UTC 24
Finished Sep 24 04:36:44 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3923589752 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 336.prim_prince_test.3923589752
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/336.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/337.prim_prince_test.3668170639
Short name T344
Test name
Test status
Simulation time 2994172541 ps
CPU time 54.4 seconds
Started Sep 24 04:35:24 AM UTC 24
Finished Sep 24 04:36:35 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3668170639 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 337.prim_prince_test.3668170639
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/337.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/338.prim_prince_test.2492615377
Short name T340
Test name
Test status
Simulation time 2155863500 ps
CPU time 40.92 seconds
Started Sep 24 04:35:28 AM UTC 24
Finished Sep 24 04:36:21 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2492615377 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 338.prim_prince_test.2492615377
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/338.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/339.prim_prince_test.295757144
Short name T349
Test name
Test status
Simulation time 2894046080 ps
CPU time 55.5 seconds
Started Sep 24 04:35:29 AM UTC 24
Finished Sep 24 04:36:41 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=295757144 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 339.prim_prince_test.295757144
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/339.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/34.prim_prince_test.2208604577
Short name T39
Test name
Test status
Simulation time 2818371125 ps
CPU time 52.2 seconds
Started Sep 24 04:25:19 AM UTC 24
Finished Sep 24 04:26:27 AM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2208604577 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 34.prim_prince_test.2208604577
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/34.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/340.prim_prince_test.2370904486
Short name T325
Test name
Test status
Simulation time 853928282 ps
CPU time 16.01 seconds
Started Sep 24 04:35:33 AM UTC 24
Finished Sep 24 04:35:54 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2370904486 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 340.prim_prince_test.2370904486
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/340.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/341.prim_prince_test.270529792
Short name T327
Test name
Test status
Simulation time 1032441352 ps
CPU time 19.51 seconds
Started Sep 24 04:35:33 AM UTC 24
Finished Sep 24 04:35:59 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=270529792 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 341.prim_prince_test.270529792
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/341.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/342.prim_prince_test.994952263
Short name T351
Test name
Test status
Simulation time 2900155752 ps
CPU time 53.83 seconds
Started Sep 24 04:35:35 AM UTC 24
Finished Sep 24 04:36:45 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=994952263 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 342.prim_prince_test.994952263
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/342.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/343.prim_prince_test.198618222
Short name T329
Test name
Test status
Simulation time 863787945 ps
CPU time 17.09 seconds
Started Sep 24 04:35:39 AM UTC 24
Finished Sep 24 04:36:02 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=198618222 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 343.prim_prince_test.198618222
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/343.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/344.prim_prince_test.1581914018
Short name T332
Test name
Test status
Simulation time 1007846754 ps
CPU time 19.97 seconds
Started Sep 24 04:35:40 AM UTC 24
Finished Sep 24 04:36:06 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1581914018 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 344.prim_prince_test.1581914018
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/344.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/345.prim_prince_test.178376515
Short name T358
Test name
Test status
Simulation time 3085892809 ps
CPU time 58.24 seconds
Started Sep 24 04:35:44 AM UTC 24
Finished Sep 24 04:37:00 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=178376515 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 345.prim_prince_test.178376515
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/345.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/346.prim_prince_test.3732526191
Short name T345
Test name
Test status
Simulation time 2050165461 ps
CPU time 37.47 seconds
Started Sep 24 04:35:47 AM UTC 24
Finished Sep 24 04:36:37 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3732526191 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 346.prim_prince_test.3732526191
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/346.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/347.prim_prince_test.1899182136
Short name T342
Test name
Test status
Simulation time 1753940576 ps
CPU time 32.58 seconds
Started Sep 24 04:35:49 AM UTC 24
Finished Sep 24 04:36:32 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1899182136 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 347.prim_prince_test.1899182136
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/347.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/348.prim_prince_test.1347683682
Short name T353
Test name
Test status
Simulation time 2642063662 ps
CPU time 48.83 seconds
Started Sep 24 04:35:49 AM UTC 24
Finished Sep 24 04:36:53 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1347683682 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 348.prim_prince_test.1347683682
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/348.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/349.prim_prince_test.80000911
Short name T337
Test name
Test status
Simulation time 872610182 ps
CPU time 16.73 seconds
Started Sep 24 04:35:50 AM UTC 24
Finished Sep 24 04:36:13 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=80000911 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 349.prim_prince_test.80000911
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/349.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/35.prim_prince_test.3891522034
Short name T50
Test name
Test status
Simulation time 3627710577 ps
CPU time 66.97 seconds
Started Sep 24 04:25:24 AM UTC 24
Finished Sep 24 04:26:51 AM UTC 24
Peak memory 155032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3891522034 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 35.prim_prince_test.3891522034
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/35.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/350.prim_prince_test.766272680
Short name T360
Test name
Test status
Simulation time 2990331949 ps
CPU time 57.34 seconds
Started Sep 24 04:35:50 AM UTC 24
Finished Sep 24 04:37:04 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=766272680 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 350.prim_prince_test.766272680
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/350.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/351.prim_prince_test.142542989
Short name T354
Test name
Test status
Simulation time 2596709973 ps
CPU time 48.04 seconds
Started Sep 24 04:35:51 AM UTC 24
Finished Sep 24 04:36:54 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=142542989 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 351.prim_prince_test.142542989
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/351.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/352.prim_prince_test.1676886631
Short name T355
Test name
Test status
Simulation time 2459896229 ps
CPU time 45.13 seconds
Started Sep 24 04:35:55 AM UTC 24
Finished Sep 24 04:36:54 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1676886631 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 352.prim_prince_test.1676886631
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/352.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/353.prim_prince_test.216920888
Short name T347
Test name
Test status
Simulation time 1742806965 ps
CPU time 32.24 seconds
Started Sep 24 04:35:57 AM UTC 24
Finished Sep 24 04:36:40 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=216920888 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 353.prim_prince_test.216920888
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/353.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/354.prim_prince_test.3038945926
Short name T343
Test name
Test status
Simulation time 1340123579 ps
CPU time 26.3 seconds
Started Sep 24 04:36:00 AM UTC 24
Finished Sep 24 04:36:34 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3038945926 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 354.prim_prince_test.3038945926
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/354.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/355.prim_prince_test.1802429290
Short name T366
Test name
Test status
Simulation time 3258210508 ps
CPU time 62.31 seconds
Started Sep 24 04:36:03 AM UTC 24
Finished Sep 24 04:37:23 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1802429290 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 355.prim_prince_test.1802429290
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/355.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/356.prim_prince_test.939405819
Short name T368
Test name
Test status
Simulation time 3420365728 ps
CPU time 62.85 seconds
Started Sep 24 04:36:03 AM UTC 24
Finished Sep 24 04:37:24 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=939405819 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 356.prim_prince_test.939405819
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/356.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/357.prim_prince_test.3267762258
Short name T363
Test name
Test status
Simulation time 2880134616 ps
CPU time 54.69 seconds
Started Sep 24 04:36:04 AM UTC 24
Finished Sep 24 04:37:14 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3267762258 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 357.prim_prince_test.3267762258
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/357.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/358.prim_prince_test.3098797262
Short name T367
Test name
Test status
Simulation time 3240921605 ps
CPU time 59.29 seconds
Started Sep 24 04:36:06 AM UTC 24
Finished Sep 24 04:37:23 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3098797262 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 358.prim_prince_test.3098797262
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/358.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/359.prim_prince_test.426441981
Short name T359
Test name
Test status
Simulation time 2238717096 ps
CPU time 41.34 seconds
Started Sep 24 04:36:07 AM UTC 24
Finished Sep 24 04:37:01 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=426441981 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 359.prim_prince_test.426441981
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/359.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/36.prim_prince_test.660043822
Short name T34
Test name
Test status
Simulation time 2100350046 ps
CPU time 41.1 seconds
Started Sep 24 04:25:24 AM UTC 24
Finished Sep 24 04:26:17 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=660043822 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 36.prim_prince_test.660043822
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/36.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/360.prim_prince_test.3347212985
Short name T352
Test name
Test status
Simulation time 1442569284 ps
CPU time 27.61 seconds
Started Sep 24 04:36:09 AM UTC 24
Finished Sep 24 04:36:45 AM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3347212985 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 360.prim_prince_test.3347212985
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/360.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/361.prim_prince_test.3382370938
Short name T371
Test name
Test status
Simulation time 3176311271 ps
CPU time 58.32 seconds
Started Sep 24 04:36:12 AM UTC 24
Finished Sep 24 04:37:27 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3382370938 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 361.prim_prince_test.3382370938
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/361.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/362.prim_prince_test.2446047684
Short name T378
Test name
Test status
Simulation time 3646953009 ps
CPU time 69.15 seconds
Started Sep 24 04:36:13 AM UTC 24
Finished Sep 24 04:37:42 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2446047684 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 362.prim_prince_test.2446047684
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/362.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/363.prim_prince_test.3377199354
Short name T346
Test name
Test status
Simulation time 1023793620 ps
CPU time 19.34 seconds
Started Sep 24 04:36:13 AM UTC 24
Finished Sep 24 04:36:39 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3377199354 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 363.prim_prince_test.3377199354
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/363.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/364.prim_prince_test.133604916
Short name T361
Test name
Test status
Simulation time 2121682184 ps
CPU time 39.69 seconds
Started Sep 24 04:36:13 AM UTC 24
Finished Sep 24 04:37:05 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=133604916 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 364.prim_prince_test.133604916
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/364.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/365.prim_prince_test.2909609105
Short name T365
Test name
Test status
Simulation time 2635997477 ps
CPU time 49.75 seconds
Started Sep 24 04:36:15 AM UTC 24
Finished Sep 24 04:37:19 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2909609105 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 365.prim_prince_test.2909609105
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/365.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/366.prim_prince_test.3153777201
Short name T377
Test name
Test status
Simulation time 3531553081 ps
CPU time 64.23 seconds
Started Sep 24 04:36:18 AM UTC 24
Finished Sep 24 04:37:42 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3153777201 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 366.prim_prince_test.3153777201
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/366.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/367.prim_prince_test.2457786097
Short name T357
Test name
Test status
Simulation time 1400985199 ps
CPU time 26.25 seconds
Started Sep 24 04:36:22 AM UTC 24
Finished Sep 24 04:36:57 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2457786097 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 367.prim_prince_test.2457786097
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/367.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/368.prim_prince_test.286816471
Short name T379
Test name
Test status
Simulation time 2865937462 ps
CPU time 53.46 seconds
Started Sep 24 04:36:33 AM UTC 24
Finished Sep 24 04:37:42 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=286816471 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 368.prim_prince_test.286816471
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/368.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/369.prim_prince_test.295633880
Short name T356
Test name
Test status
Simulation time 890193154 ps
CPU time 16.5 seconds
Started Sep 24 04:36:33 AM UTC 24
Finished Sep 24 04:36:55 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=295633880 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 369.prim_prince_test.295633880
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/369.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/37.prim_prince_test.3207511170
Short name T43
Test name
Test status
Simulation time 2786453401 ps
CPU time 53.9 seconds
Started Sep 24 04:25:26 AM UTC 24
Finished Sep 24 04:26:35 AM UTC 24
Peak memory 155028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3207511170 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 37.prim_prince_test.3207511170
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/37.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/370.prim_prince_test.1989121787
Short name T372
Test name
Test status
Simulation time 2169228972 ps
CPU time 41.09 seconds
Started Sep 24 04:36:35 AM UTC 24
Finished Sep 24 04:37:28 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1989121787 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 370.prim_prince_test.1989121787
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/370.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/371.prim_prince_test.948551438
Short name T384
Test name
Test status
Simulation time 3322568994 ps
CPU time 60.51 seconds
Started Sep 24 04:36:36 AM UTC 24
Finished Sep 24 04:37:55 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=948551438 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 371.prim_prince_test.948551438
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/371.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/372.prim_prince_test.2957814522
Short name T364
Test name
Test status
Simulation time 1555868953 ps
CPU time 28.82 seconds
Started Sep 24 04:36:37 AM UTC 24
Finished Sep 24 04:37:15 AM UTC 24
Peak memory 154968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2957814522 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 372.prim_prince_test.2957814522
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/372.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/373.prim_prince_test.419193248
Short name T362
Test name
Test status
Simulation time 1156961395 ps
CPU time 21.75 seconds
Started Sep 24 04:36:39 AM UTC 24
Finished Sep 24 04:37:08 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=419193248 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 373.prim_prince_test.419193248
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/373.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/374.prim_prince_test.1078600542
Short name T386
Test name
Test status
Simulation time 3324568849 ps
CPU time 60.63 seconds
Started Sep 24 04:36:41 AM UTC 24
Finished Sep 24 04:37:59 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1078600542 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 374.prim_prince_test.1078600542
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/374.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/375.prim_prince_test.2167659592
Short name T370
Test name
Test status
Simulation time 1832927501 ps
CPU time 33.63 seconds
Started Sep 24 04:36:42 AM UTC 24
Finished Sep 24 04:37:26 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2167659592 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 375.prim_prince_test.2167659592
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/375.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/376.prim_prince_test.3062867460
Short name T388
Test name
Test status
Simulation time 3482966279 ps
CPU time 63.43 seconds
Started Sep 24 04:36:42 AM UTC 24
Finished Sep 24 04:38:04 AM UTC 24
Peak memory 155032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3062867460 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 376.prim_prince_test.3062867460
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/376.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/377.prim_prince_test.2385603951
Short name T380
Test name
Test status
Simulation time 2504725062 ps
CPU time 45.79 seconds
Started Sep 24 04:36:45 AM UTC 24
Finished Sep 24 04:37:45 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2385603951 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 377.prim_prince_test.2385603951
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/377.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/378.prim_prince_test.1631832164
Short name T385
Test name
Test status
Simulation time 3007881418 ps
CPU time 55.54 seconds
Started Sep 24 04:36:46 AM UTC 24
Finished Sep 24 04:37:58 AM UTC 24
Peak memory 154884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1631832164 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 378.prim_prince_test.1631832164
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/378.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/379.prim_prince_test.3766878051
Short name T373
Test name
Test status
Simulation time 1757682134 ps
CPU time 32.24 seconds
Started Sep 24 04:36:46 AM UTC 24
Finished Sep 24 04:37:29 AM UTC 24
Peak memory 154728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3766878051 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 379.prim_prince_test.3766878051
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/379.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/38.prim_prince_test.3202408949
Short name T44
Test name
Test status
Simulation time 2806955919 ps
CPU time 54.56 seconds
Started Sep 24 04:25:28 AM UTC 24
Finished Sep 24 04:26:37 AM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3202408949 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 38.prim_prince_test.3202408949
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/38.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/380.prim_prince_test.141848445
Short name T369
Test name
Test status
Simulation time 1275806965 ps
CPU time 24.52 seconds
Started Sep 24 04:36:53 AM UTC 24
Finished Sep 24 04:37:25 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=141848445 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 380.prim_prince_test.141848445
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/380.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/381.prim_prince_test.1278243598
Short name T374
Test name
Test status
Simulation time 1567866801 ps
CPU time 30.39 seconds
Started Sep 24 04:36:55 AM UTC 24
Finished Sep 24 04:37:34 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1278243598 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 381.prim_prince_test.1278243598
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/381.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/382.prim_prince_test.901033647
Short name T376
Test name
Test status
Simulation time 1886199136 ps
CPU time 34.44 seconds
Started Sep 24 04:36:55 AM UTC 24
Finished Sep 24 04:37:40 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=901033647 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 382.prim_prince_test.901033647
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/382.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/383.prim_prince_test.4251075854
Short name T381
Test name
Test status
Simulation time 2109961243 ps
CPU time 38.56 seconds
Started Sep 24 04:36:56 AM UTC 24
Finished Sep 24 04:37:46 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4251075854 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 383.prim_prince_test.4251075854
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/383.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/384.prim_prince_test.2036734835
Short name T395
Test name
Test status
Simulation time 3104841841 ps
CPU time 59.34 seconds
Started Sep 24 04:36:58 AM UTC 24
Finished Sep 24 04:38:14 AM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2036734835 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 384.prim_prince_test.2036734835
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/384.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/385.prim_prince_test.2529743916
Short name T375
Test name
Test status
Simulation time 1425526937 ps
CPU time 26.69 seconds
Started Sep 24 04:37:00 AM UTC 24
Finished Sep 24 04:37:35 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2529743916 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 385.prim_prince_test.2529743916
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/385.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/386.prim_prince_test.668271218
Short name T403
Test name
Test status
Simulation time 3570959360 ps
CPU time 65.09 seconds
Started Sep 24 04:37:02 AM UTC 24
Finished Sep 24 04:38:27 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=668271218 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 386.prim_prince_test.668271218
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/386.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/387.prim_prince_test.3353417423
Short name T392
Test name
Test status
Simulation time 2891140745 ps
CPU time 52.4 seconds
Started Sep 24 04:37:04 AM UTC 24
Finished Sep 24 04:38:13 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3353417423 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 387.prim_prince_test.3353417423
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/387.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/388.prim_prince_test.3566132768
Short name T389
Test name
Test status
Simulation time 2371138894 ps
CPU time 45.86 seconds
Started Sep 24 04:37:06 AM UTC 24
Finished Sep 24 04:38:05 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3566132768 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 388.prim_prince_test.3566132768
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/388.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/389.prim_prince_test.1219982620
Short name T390
Test name
Test status
Simulation time 2368790255 ps
CPU time 45.64 seconds
Started Sep 24 04:37:09 AM UTC 24
Finished Sep 24 04:38:08 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1219982620 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 389.prim_prince_test.1219982620
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/389.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/39.prim_prince_test.1265710913
Short name T49
Test name
Test status
Simulation time 3326921103 ps
CPU time 64.68 seconds
Started Sep 24 04:25:28 AM UTC 24
Finished Sep 24 04:26:50 AM UTC 24
Peak memory 155028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1265710913 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 39.prim_prince_test.1265710913
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/39.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/390.prim_prince_test.1379037008
Short name T396
Test name
Test status
Simulation time 2477446059 ps
CPU time 47.57 seconds
Started Sep 24 04:37:15 AM UTC 24
Finished Sep 24 04:38:17 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1379037008 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 390.prim_prince_test.1379037008
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/390.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/391.prim_prince_test.3898830856
Short name T405
Test name
Test status
Simulation time 3025784264 ps
CPU time 57.65 seconds
Started Sep 24 04:37:16 AM UTC 24
Finished Sep 24 04:38:31 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3898830856 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 391.prim_prince_test.3898830856
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/391.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/392.prim_prince_test.2638036918
Short name T407
Test name
Test status
Simulation time 3153595748 ps
CPU time 57.55 seconds
Started Sep 24 04:37:20 AM UTC 24
Finished Sep 24 04:38:35 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2638036918 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 392.prim_prince_test.2638036918
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/392.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/393.prim_prince_test.581219658
Short name T400
Test name
Test status
Simulation time 2392044510 ps
CPU time 43.94 seconds
Started Sep 24 04:37:23 AM UTC 24
Finished Sep 24 04:38:21 AM UTC 24
Peak memory 155048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=581219658 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 393.prim_prince_test.581219658
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/393.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/394.prim_prince_test.3641796175
Short name T406
Test name
Test status
Simulation time 2901970231 ps
CPU time 54.09 seconds
Started Sep 24 04:37:24 AM UTC 24
Finished Sep 24 04:38:34 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3641796175 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 394.prim_prince_test.3641796175
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/394.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/395.prim_prince_test.3995626323
Short name T404
Test name
Test status
Simulation time 2549964821 ps
CPU time 46.54 seconds
Started Sep 24 04:37:26 AM UTC 24
Finished Sep 24 04:38:27 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3995626323 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 395.prim_prince_test.3995626323
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/395.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/396.prim_prince_test.441477543
Short name T382
Test name
Test status
Simulation time 957848181 ps
CPU time 17.99 seconds
Started Sep 24 04:37:27 AM UTC 24
Finished Sep 24 04:37:51 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=441477543 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 396.prim_prince_test.441477543
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/396.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/397.prim_prince_test.3264523021
Short name T397
Test name
Test status
Simulation time 2120836356 ps
CPU time 40.07 seconds
Started Sep 24 04:37:27 AM UTC 24
Finished Sep 24 04:38:19 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3264523021 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 397.prim_prince_test.3264523021
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/397.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/398.prim_prince_test.1687653648
Short name T402
Test name
Test status
Simulation time 2416029382 ps
CPU time 44.5 seconds
Started Sep 24 04:37:28 AM UTC 24
Finished Sep 24 04:38:26 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1687653648 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 398.prim_prince_test.1687653648
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/398.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/399.prim_prince_test.3087543566
Short name T383
Test name
Test status
Simulation time 949374151 ps
CPU time 18.76 seconds
Started Sep 24 04:37:29 AM UTC 24
Finished Sep 24 04:37:54 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3087543566 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 399.prim_prince_test.3087543566
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/399.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/4.prim_prince_test.237831627
Short name T15
Test name
Test status
Simulation time 3248100218 ps
CPU time 59.48 seconds
Started Sep 24 04:24:10 AM UTC 24
Finished Sep 24 04:25:27 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=237831627 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 4.prim_prince_test.237831627
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/4.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/40.prim_prince_test.2410701110
Short name T48
Test name
Test status
Simulation time 3036466034 ps
CPU time 56.54 seconds
Started Sep 24 04:25:32 AM UTC 24
Finished Sep 24 04:26:45 AM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2410701110 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 40.prim_prince_test.2410701110
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/40.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/400.prim_prince_test.2128038774
Short name T401
Test name
Test status
Simulation time 2207184063 ps
CPU time 40.6 seconds
Started Sep 24 04:37:29 AM UTC 24
Finished Sep 24 04:38:23 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2128038774 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 400.prim_prince_test.2128038774
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/400.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/401.prim_prince_test.2724790849
Short name T412
Test name
Test status
Simulation time 2817699871 ps
CPU time 52.48 seconds
Started Sep 24 04:37:35 AM UTC 24
Finished Sep 24 04:38:43 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2724790849 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 401.prim_prince_test.2724790849
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/401.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/402.prim_prince_test.3473917696
Short name T391
Test name
Test status
Simulation time 1252432400 ps
CPU time 24.08 seconds
Started Sep 24 04:37:37 AM UTC 24
Finished Sep 24 04:38:08 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3473917696 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 402.prim_prince_test.3473917696
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/402.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/403.prim_prince_test.2291115713
Short name T387
Test name
Test status
Simulation time 812500500 ps
CPU time 15.81 seconds
Started Sep 24 04:37:41 AM UTC 24
Finished Sep 24 04:38:02 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2291115713 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 403.prim_prince_test.2291115713
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/403.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/404.prim_prince_test.3585650848
Short name T424
Test name
Test status
Simulation time 3699066955 ps
CPU time 71.39 seconds
Started Sep 24 04:37:42 AM UTC 24
Finished Sep 24 04:39:14 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3585650848 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 404.prim_prince_test.3585650848
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/404.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/405.prim_prince_test.1324554716
Short name T399
Test name
Test status
Simulation time 1442749923 ps
CPU time 27.98 seconds
Started Sep 24 04:37:43 AM UTC 24
Finished Sep 24 04:38:20 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1324554716 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 405.prim_prince_test.1324554716
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/405.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/406.prim_prince_test.2540267775
Short name T394
Test name
Test status
Simulation time 1193041905 ps
CPU time 23.08 seconds
Started Sep 24 04:37:43 AM UTC 24
Finished Sep 24 04:38:14 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2540267775 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 406.prim_prince_test.2540267775
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/406.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/407.prim_prince_test.3715437083
Short name T393
Test name
Test status
Simulation time 1109993437 ps
CPU time 20.7 seconds
Started Sep 24 04:37:46 AM UTC 24
Finished Sep 24 04:38:13 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3715437083 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 407.prim_prince_test.3715437083
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/407.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/408.prim_prince_test.3710844360
Short name T415
Test name
Test status
Simulation time 2851592155 ps
CPU time 52.25 seconds
Started Sep 24 04:37:48 AM UTC 24
Finished Sep 24 04:38:56 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3710844360 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 408.prim_prince_test.3710844360
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/408.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/409.prim_prince_test.1005605898
Short name T398
Test name
Test status
Simulation time 1098457208 ps
CPU time 20.91 seconds
Started Sep 24 04:37:52 AM UTC 24
Finished Sep 24 04:38:20 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1005605898 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 409.prim_prince_test.1005605898
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/409.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/41.prim_prince_test.790150663
Short name T36
Test name
Test status
Simulation time 1807270652 ps
CPU time 35.24 seconds
Started Sep 24 04:25:34 AM UTC 24
Finished Sep 24 04:26:19 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=790150663 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 41.prim_prince_test.790150663
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/41.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/410.prim_prince_test.3823178814
Short name T411
Test name
Test status
Simulation time 1879552184 ps
CPU time 35.93 seconds
Started Sep 24 04:37:55 AM UTC 24
Finished Sep 24 04:38:42 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3823178814 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 410.prim_prince_test.3823178814
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/410.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/411.prim_prince_test.2006612741
Short name T417
Test name
Test status
Simulation time 2615752314 ps
CPU time 47.97 seconds
Started Sep 24 04:37:55 AM UTC 24
Finished Sep 24 04:38:58 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2006612741 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 411.prim_prince_test.2006612741
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/411.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/412.prim_prince_test.1237133833
Short name T428
Test name
Test status
Simulation time 3506353838 ps
CPU time 64.32 seconds
Started Sep 24 04:37:59 AM UTC 24
Finished Sep 24 04:39:23 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1237133833 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 412.prim_prince_test.1237133833
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/412.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/413.prim_prince_test.3125263519
Short name T422
Test name
Test status
Simulation time 3006241806 ps
CPU time 55.23 seconds
Started Sep 24 04:38:01 AM UTC 24
Finished Sep 24 04:39:12 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3125263519 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 413.prim_prince_test.3125263519
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/413.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/414.prim_prince_test.3786429655
Short name T425
Test name
Test status
Simulation time 2860331091 ps
CPU time 55.67 seconds
Started Sep 24 04:38:03 AM UTC 24
Finished Sep 24 04:39:14 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3786429655 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 414.prim_prince_test.3786429655
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/414.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/415.prim_prince_test.3964991044
Short name T408
Test name
Test status
Simulation time 1289708825 ps
CPU time 24.77 seconds
Started Sep 24 04:38:05 AM UTC 24
Finished Sep 24 04:38:37 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3964991044 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 415.prim_prince_test.3964991044
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/415.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/416.prim_prince_test.2791845472
Short name T426
Test name
Test status
Simulation time 3068588486 ps
CPU time 57.08 seconds
Started Sep 24 04:38:05 AM UTC 24
Finished Sep 24 04:39:19 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2791845472 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 416.prim_prince_test.2791845472
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/416.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/417.prim_prince_test.3537982914
Short name T433
Test name
Test status
Simulation time 3605276543 ps
CPU time 69.98 seconds
Started Sep 24 04:38:08 AM UTC 24
Finished Sep 24 04:39:38 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3537982914 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 417.prim_prince_test.3537982914
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/417.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/418.prim_prince_test.1007032087
Short name T423
Test name
Test status
Simulation time 2641578166 ps
CPU time 49.3 seconds
Started Sep 24 04:38:09 AM UTC 24
Finished Sep 24 04:39:13 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1007032087 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 418.prim_prince_test.1007032087
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/418.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/419.prim_prince_test.2281776014
Short name T418
Test name
Test status
Simulation time 1889880604 ps
CPU time 35.24 seconds
Started Sep 24 04:38:14 AM UTC 24
Finished Sep 24 04:39:00 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2281776014 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 419.prim_prince_test.2281776014
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/419.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/42.prim_prince_test.2233025130
Short name T28
Test name
Test status
Simulation time 1050609833 ps
CPU time 21.18 seconds
Started Sep 24 04:25:36 AM UTC 24
Finished Sep 24 04:26:03 AM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2233025130 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 42.prim_prince_test.2233025130
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/42.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/420.prim_prince_test.2940551137
Short name T416
Test name
Test status
Simulation time 1778684495 ps
CPU time 33.89 seconds
Started Sep 24 04:38:14 AM UTC 24
Finished Sep 24 04:38:58 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2940551137 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 420.prim_prince_test.2940551137
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/420.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/421.prim_prince_test.3120454288
Short name T409
Test name
Test status
Simulation time 1046070791 ps
CPU time 20.24 seconds
Started Sep 24 04:38:15 AM UTC 24
Finished Sep 24 04:38:41 AM UTC 24
Peak memory 154920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3120454288 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 421.prim_prince_test.3120454288
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/421.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/422.prim_prince_test.819159063
Short name T419
Test name
Test status
Simulation time 2086669440 ps
CPU time 39.36 seconds
Started Sep 24 04:38:15 AM UTC 24
Finished Sep 24 04:39:06 AM UTC 24
Peak memory 154956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=819159063 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 422.prim_prince_test.819159063
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/422.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/423.prim_prince_test.952683714
Short name T440
Test name
Test status
Simulation time 3703908396 ps
CPU time 67.41 seconds
Started Sep 24 04:38:18 AM UTC 24
Finished Sep 24 04:39:46 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=952683714 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 423.prim_prince_test.952683714
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/423.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/424.prim_prince_test.1303350075
Short name T439
Test name
Test status
Simulation time 3559718952 ps
CPU time 65.21 seconds
Started Sep 24 04:38:20 AM UTC 24
Finished Sep 24 04:39:45 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1303350075 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 424.prim_prince_test.1303350075
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/424.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/425.prim_prince_test.929351709
Short name T414
Test name
Test status
Simulation time 1278182153 ps
CPU time 23.77 seconds
Started Sep 24 04:38:21 AM UTC 24
Finished Sep 24 04:38:52 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=929351709 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 425.prim_prince_test.929351709
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/425.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/426.prim_prince_test.3504316546
Short name T410
Test name
Test status
Simulation time 849325336 ps
CPU time 15.67 seconds
Started Sep 24 04:38:21 AM UTC 24
Finished Sep 24 04:38:42 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3504316546 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 426.prim_prince_test.3504316546
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/426.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/427.prim_prince_test.1921784424
Short name T427
Test name
Test status
Simulation time 2403177534 ps
CPU time 47.17 seconds
Started Sep 24 04:38:22 AM UTC 24
Finished Sep 24 04:39:22 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1921784424 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 427.prim_prince_test.1921784424
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/427.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/428.prim_prince_test.3631485337
Short name T421
Test name
Test status
Simulation time 1869376506 ps
CPU time 34.35 seconds
Started Sep 24 04:38:24 AM UTC 24
Finished Sep 24 04:39:09 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3631485337 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 428.prim_prince_test.3631485337
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/428.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/429.prim_prince_test.25089599
Short name T413
Test name
Test status
Simulation time 866133586 ps
CPU time 16.09 seconds
Started Sep 24 04:38:27 AM UTC 24
Finished Sep 24 04:38:49 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25089599 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 429.prim_prince_test.25089599
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/429.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/43.prim_prince_test.915120069
Short name T51
Test name
Test status
Simulation time 3255337509 ps
CPU time 59.82 seconds
Started Sep 24 04:25:36 AM UTC 24
Finished Sep 24 04:26:53 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=915120069 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 43.prim_prince_test.915120069
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/43.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/430.prim_prince_test.3126908137
Short name T420
Test name
Test status
Simulation time 1699661331 ps
CPU time 31.41 seconds
Started Sep 24 04:38:27 AM UTC 24
Finished Sep 24 04:39:09 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3126908137 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 430.prim_prince_test.3126908137
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/430.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/431.prim_prince_test.2839305330
Short name T430
Test name
Test status
Simulation time 2477518607 ps
CPU time 46.27 seconds
Started Sep 24 04:38:27 AM UTC 24
Finished Sep 24 04:39:27 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2839305330 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 431.prim_prince_test.2839305330
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/431.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/432.prim_prince_test.2180789527
Short name T441
Test name
Test status
Simulation time 3193628661 ps
CPU time 58.14 seconds
Started Sep 24 04:38:32 AM UTC 24
Finished Sep 24 04:39:47 AM UTC 24
Peak memory 155032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2180789527 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 432.prim_prince_test.2180789527
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/432.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/433.prim_prince_test.3192346186
Short name T442
Test name
Test status
Simulation time 3183334994 ps
CPU time 58.3 seconds
Started Sep 24 04:38:35 AM UTC 24
Finished Sep 24 04:39:50 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3192346186 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 433.prim_prince_test.3192346186
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/433.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/434.prim_prince_test.1119326588
Short name T434
Test name
Test status
Simulation time 2647151628 ps
CPU time 48.38 seconds
Started Sep 24 04:38:36 AM UTC 24
Finished Sep 24 04:39:39 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1119326588 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 434.prim_prince_test.1119326588
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/434.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/435.prim_prince_test.2709518149
Short name T437
Test name
Test status
Simulation time 2525860833 ps
CPU time 49.34 seconds
Started Sep 24 04:38:38 AM UTC 24
Finished Sep 24 04:39:42 AM UTC 24
Peak memory 155032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2709518149 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 435.prim_prince_test.2709518149
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/435.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/436.prim_prince_test.3161801806
Short name T450
Test name
Test status
Simulation time 3548503230 ps
CPU time 65.06 seconds
Started Sep 24 04:38:42 AM UTC 24
Finished Sep 24 04:40:07 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3161801806 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 436.prim_prince_test.3161801806
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/436.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/437.prim_prince_test.2747472385
Short name T429
Test name
Test status
Simulation time 1663185053 ps
CPU time 30.78 seconds
Started Sep 24 04:38:43 AM UTC 24
Finished Sep 24 04:39:23 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2747472385 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 437.prim_prince_test.2747472385
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/437.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/438.prim_prince_test.776334908
Short name T443
Test name
Test status
Simulation time 2970794799 ps
CPU time 54.76 seconds
Started Sep 24 04:38:43 AM UTC 24
Finished Sep 24 04:39:54 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=776334908 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 438.prim_prince_test.776334908
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/438.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/439.prim_prince_test.2562369697
Short name T436
Test name
Test status
Simulation time 2403407379 ps
CPU time 44.32 seconds
Started Sep 24 04:38:44 AM UTC 24
Finished Sep 24 04:39:42 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2562369697 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 439.prim_prince_test.2562369697
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/439.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/44.prim_prince_test.999689240
Short name T35
Test name
Test status
Simulation time 1623687467 ps
CPU time 30.5 seconds
Started Sep 24 04:25:39 AM UTC 24
Finished Sep 24 04:26:19 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=999689240 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 44.prim_prince_test.999689240
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/44.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/440.prim_prince_test.3489989811
Short name T435
Test name
Test status
Simulation time 2072693562 ps
CPU time 38.07 seconds
Started Sep 24 04:38:50 AM UTC 24
Finished Sep 24 04:39:40 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3489989811 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 440.prim_prince_test.3489989811
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/440.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/441.prim_prince_test.125771065
Short name T454
Test name
Test status
Simulation time 3324935201 ps
CPU time 60.93 seconds
Started Sep 24 04:38:53 AM UTC 24
Finished Sep 24 04:40:13 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=125771065 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 441.prim_prince_test.125771065
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/441.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/442.prim_prince_test.3257095405
Short name T456
Test name
Test status
Simulation time 3290486330 ps
CPU time 60.6 seconds
Started Sep 24 04:38:56 AM UTC 24
Finished Sep 24 04:40:15 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3257095405 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 442.prim_prince_test.3257095405
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/442.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/443.prim_prince_test.1292640257
Short name T448
Test name
Test status
Simulation time 2482033835 ps
CPU time 48.46 seconds
Started Sep 24 04:38:59 AM UTC 24
Finished Sep 24 04:40:01 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1292640257 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 443.prim_prince_test.1292640257
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/443.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/444.prim_prince_test.2204782291
Short name T432
Test name
Test status
Simulation time 1250927076 ps
CPU time 24.9 seconds
Started Sep 24 04:38:59 AM UTC 24
Finished Sep 24 04:39:31 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2204782291 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 444.prim_prince_test.2204782291
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/444.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/445.prim_prince_test.411249520
Short name T431
Test name
Test status
Simulation time 1146202892 ps
CPU time 22.96 seconds
Started Sep 24 04:39:01 AM UTC 24
Finished Sep 24 04:39:31 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=411249520 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 445.prim_prince_test.411249520
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/445.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/446.prim_prince_test.558856429
Short name T449
Test name
Test status
Simulation time 2442433142 ps
CPU time 45.04 seconds
Started Sep 24 04:39:07 AM UTC 24
Finished Sep 24 04:40:06 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=558856429 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 446.prim_prince_test.558856429
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/446.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/447.prim_prince_test.2971056708
Short name T447
Test name
Test status
Simulation time 1999777115 ps
CPU time 37.13 seconds
Started Sep 24 04:39:09 AM UTC 24
Finished Sep 24 04:39:58 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2971056708 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 447.prim_prince_test.2971056708
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/447.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/448.prim_prince_test.1315799707
Short name T444
Test name
Test status
Simulation time 1795720701 ps
CPU time 33.22 seconds
Started Sep 24 04:39:10 AM UTC 24
Finished Sep 24 04:39:54 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1315799707 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 448.prim_prince_test.1315799707
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/448.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/449.prim_prince_test.130601782
Short name T458
Test name
Test status
Simulation time 2641845586 ps
CPU time 48.77 seconds
Started Sep 24 04:39:13 AM UTC 24
Finished Sep 24 04:40:17 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=130601782 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 449.prim_prince_test.130601782
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/449.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/45.prim_prince_test.1875223202
Short name T47
Test name
Test status
Simulation time 2621520133 ps
CPU time 48.51 seconds
Started Sep 24 04:25:40 AM UTC 24
Finished Sep 24 04:26:43 AM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1875223202 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 45.prim_prince_test.1875223202
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/45.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/450.prim_prince_test.2466834831
Short name T451
Test name
Test status
Simulation time 2215295739 ps
CPU time 40.73 seconds
Started Sep 24 04:39:15 AM UTC 24
Finished Sep 24 04:40:08 AM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2466834831 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 450.prim_prince_test.2466834831
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/450.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/451.prim_prince_test.872835686
Short name T446
Test name
Test status
Simulation time 1603352145 ps
CPU time 30.97 seconds
Started Sep 24 04:39:15 AM UTC 24
Finished Sep 24 04:39:55 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=872835686 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 451.prim_prince_test.872835686
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/451.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/452.prim_prince_test.3465950700
Short name T463
Test name
Test status
Simulation time 3177056071 ps
CPU time 59.28 seconds
Started Sep 24 04:39:15 AM UTC 24
Finished Sep 24 04:40:32 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3465950700 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 452.prim_prince_test.3465950700
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/452.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/453.prim_prince_test.3952759577
Short name T459
Test name
Test status
Simulation time 2511029460 ps
CPU time 46.36 seconds
Started Sep 24 04:39:20 AM UTC 24
Finished Sep 24 04:40:21 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3952759577 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 453.prim_prince_test.3952759577
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/453.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/454.prim_prince_test.3940082146
Short name T438
Test name
Test status
Simulation time 836087134 ps
CPU time 15.85 seconds
Started Sep 24 04:39:24 AM UTC 24
Finished Sep 24 04:39:45 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3940082146 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 454.prim_prince_test.3940082146
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/454.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/455.prim_prince_test.639658163
Short name T452
Test name
Test status
Simulation time 1842209191 ps
CPU time 34.09 seconds
Started Sep 24 04:39:24 AM UTC 24
Finished Sep 24 04:40:08 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=639658163 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 455.prim_prince_test.639658163
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/455.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/456.prim_prince_test.3946353131
Short name T472
Test name
Test status
Simulation time 3527566762 ps
CPU time 67.2 seconds
Started Sep 24 04:39:24 AM UTC 24
Finished Sep 24 04:40:50 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3946353131 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 456.prim_prince_test.3946353131
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/456.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/457.prim_prince_test.3331869883
Short name T465
Test name
Test status
Simulation time 2974645906 ps
CPU time 54.12 seconds
Started Sep 24 04:39:29 AM UTC 24
Finished Sep 24 04:40:39 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3331869883 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 457.prim_prince_test.3331869883
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/457.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/458.prim_prince_test.3511134885
Short name T445
Test name
Test status
Simulation time 854741588 ps
CPU time 17.22 seconds
Started Sep 24 04:39:32 AM UTC 24
Finished Sep 24 04:39:55 AM UTC 24
Peak memory 154944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3511134885 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 458.prim_prince_test.3511134885
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/458.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/459.prim_prince_test.4099650824
Short name T453
Test name
Test status
Simulation time 1502476148 ps
CPU time 29.64 seconds
Started Sep 24 04:39:32 AM UTC 24
Finished Sep 24 04:40:11 AM UTC 24
Peak memory 154960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4099650824 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 459.prim_prince_test.4099650824
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/459.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/46.prim_prince_test.4277397902
Short name T41
Test name
Test status
Simulation time 2071244106 ps
CPU time 38.59 seconds
Started Sep 24 04:25:40 AM UTC 24
Finished Sep 24 04:26:30 AM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4277397902 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 46.prim_prince_test.4277397902
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/46.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/460.prim_prince_test.1646512029
Short name T479
Test name
Test status
Simulation time 3679721890 ps
CPU time 68.25 seconds
Started Sep 24 04:39:38 AM UTC 24
Finished Sep 24 04:41:07 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1646512029 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 460.prim_prince_test.1646512029
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/460.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/461.prim_prince_test.3305104032
Short name T467
Test name
Test status
Simulation time 2587457003 ps
CPU time 47.77 seconds
Started Sep 24 04:39:41 AM UTC 24
Finished Sep 24 04:40:43 AM UTC 24
Peak memory 154936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3305104032 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 461.prim_prince_test.3305104032
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/461.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/462.prim_prince_test.4002257303
Short name T461
Test name
Test status
Simulation time 1771646587 ps
CPU time 32.96 seconds
Started Sep 24 04:39:41 AM UTC 24
Finished Sep 24 04:40:24 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4002257303 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 462.prim_prince_test.4002257303
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/462.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/463.prim_prince_test.2493721769
Short name T476
Test name
Test status
Simulation time 3299990272 ps
CPU time 59.63 seconds
Started Sep 24 04:39:43 AM UTC 24
Finished Sep 24 04:41:01 AM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2493721769 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 463.prim_prince_test.2493721769
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/463.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/464.prim_prince_test.2549225657
Short name T462
Test name
Test status
Simulation time 1999796532 ps
CPU time 37.38 seconds
Started Sep 24 04:39:43 AM UTC 24
Finished Sep 24 04:40:32 AM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2549225657 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 464.prim_prince_test.2549225657
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/464.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/465.prim_prince_test.4197986140
Short name T482
Test name
Test status
Simulation time 3726662532 ps
CPU time 68.04 seconds
Started Sep 24 04:39:45 AM UTC 24
Finished Sep 24 04:41:14 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4197986140 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 465.prim_prince_test.4197986140
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/465.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/466.prim_prince_test.1349254188
Short name T474
Test name
Test status
Simulation time 2788083024 ps
CPU time 51.39 seconds
Started Sep 24 04:39:46 AM UTC 24
Finished Sep 24 04:40:53 AM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1349254188 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 466.prim_prince_test.1349254188
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/466.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/467.prim_prince_test.2761666884
Short name T455
Test name
Test status
Simulation time 1102153319 ps
CPU time 21.14 seconds
Started Sep 24 04:39:47 AM UTC 24
Finished Sep 24 04:40:14 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2761666884 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 467.prim_prince_test.2761666884
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/467.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/468.prim_prince_test.2316839796
Short name T457
Test name
Test status
Simulation time 1192787784 ps
CPU time 22.25 seconds
Started Sep 24 04:39:48 AM UTC 24
Finished Sep 24 04:40:17 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2316839796 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 468.prim_prince_test.2316839796
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/468.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/469.prim_prince_test.784834696
Short name T475
Test name
Test status
Simulation time 2619454358 ps
CPU time 49.3 seconds
Started Sep 24 04:39:51 AM UTC 24
Finished Sep 24 04:40:55 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=784834696 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 469.prim_prince_test.784834696
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/469.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/47.prim_prince_test.1260601996
Short name T59
Test name
Test status
Simulation time 3745302719 ps
CPU time 69.24 seconds
Started Sep 24 04:25:44 AM UTC 24
Finished Sep 24 04:27:13 AM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1260601996 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 47.prim_prince_test.1260601996
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/47.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/470.prim_prince_test.2625763341
Short name T488
Test name
Test status
Simulation time 3634788758 ps
CPU time 69.75 seconds
Started Sep 24 04:39:54 AM UTC 24
Finished Sep 24 04:41:24 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2625763341 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 470.prim_prince_test.2625763341
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/470.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/471.prim_prince_test.3613065230
Short name T473
Test name
Test status
Simulation time 2373013648 ps
CPU time 43.46 seconds
Started Sep 24 04:39:55 AM UTC 24
Finished Sep 24 04:40:52 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3613065230 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 471.prim_prince_test.3613065230
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/471.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/472.prim_prince_test.4232711067
Short name T471
Test name
Test status
Simulation time 2180751123 ps
CPU time 40.93 seconds
Started Sep 24 04:39:56 AM UTC 24
Finished Sep 24 04:40:49 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4232711067 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 472.prim_prince_test.4232711067
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/472.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/473.prim_prince_test.2984758848
Short name T468
Test name
Test status
Simulation time 1861455189 ps
CPU time 35.7 seconds
Started Sep 24 04:39:57 AM UTC 24
Finished Sep 24 04:40:43 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2984758848 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 473.prim_prince_test.2984758848
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/473.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/474.prim_prince_test.2608797828
Short name T460
Test name
Test status
Simulation time 944221976 ps
CPU time 18.6 seconds
Started Sep 24 04:39:59 AM UTC 24
Finished Sep 24 04:40:23 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2608797828 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 474.prim_prince_test.2608797828
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/474.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/475.prim_prince_test.2688600948
Short name T486
Test name
Test status
Simulation time 3146836355 ps
CPU time 58.18 seconds
Started Sep 24 04:40:02 AM UTC 24
Finished Sep 24 04:41:18 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2688600948 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 475.prim_prince_test.2688600948
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/475.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/476.prim_prince_test.3340301942
Short name T477
Test name
Test status
Simulation time 2248404245 ps
CPU time 42.47 seconds
Started Sep 24 04:40:06 AM UTC 24
Finished Sep 24 04:41:01 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3340301942 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 476.prim_prince_test.3340301942
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/476.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/477.prim_prince_test.59942315
Short name T470
Test name
Test status
Simulation time 1576107389 ps
CPU time 30.16 seconds
Started Sep 24 04:40:08 AM UTC 24
Finished Sep 24 04:40:47 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=59942315 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 477.prim_prince_test.59942315
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/477.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/478.prim_prince_test.825729973
Short name T469
Test name
Test status
Simulation time 1429268525 ps
CPU time 27.49 seconds
Started Sep 24 04:40:10 AM UTC 24
Finished Sep 24 04:40:46 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=825729973 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 478.prim_prince_test.825729973
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/478.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/479.prim_prince_test.3373955976
Short name T464
Test name
Test status
Simulation time 962265115 ps
CPU time 18.46 seconds
Started Sep 24 04:40:10 AM UTC 24
Finished Sep 24 04:40:34 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3373955976 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 479.prim_prince_test.3373955976
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/479.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/48.prim_prince_test.2250691473
Short name T55
Test name
Test status
Simulation time 3257295281 ps
CPU time 61.91 seconds
Started Sep 24 04:25:50 AM UTC 24
Finished Sep 24 04:27:09 AM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2250691473 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 48.prim_prince_test.2250691473
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/48.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/480.prim_prince_test.2291629188
Short name T484
Test name
Test status
Simulation time 2536765620 ps
CPU time 47.87 seconds
Started Sep 24 04:40:12 AM UTC 24
Finished Sep 24 04:41:14 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2291629188 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 480.prim_prince_test.2291629188
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/480.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/481.prim_prince_test.2320423367
Short name T481
Test name
Test status
Simulation time 2417434670 ps
CPU time 44.47 seconds
Started Sep 24 04:40:13 AM UTC 24
Finished Sep 24 04:41:11 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2320423367 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 481.prim_prince_test.2320423367
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/481.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/482.prim_prince_test.2506733266
Short name T494
Test name
Test status
Simulation time 3539925461 ps
CPU time 65.2 seconds
Started Sep 24 04:40:16 AM UTC 24
Finished Sep 24 04:41:41 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2506733266 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 482.prim_prince_test.2506733266
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/482.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/483.prim_prince_test.2912714879
Short name T493
Test name
Test status
Simulation time 3395073962 ps
CPU time 63.1 seconds
Started Sep 24 04:40:17 AM UTC 24
Finished Sep 24 04:41:39 AM UTC 24
Peak memory 155032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2912714879 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 483.prim_prince_test.2912714879
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/483.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/484.prim_prince_test.3094070030
Short name T466
Test name
Test status
Simulation time 999988577 ps
CPU time 18.37 seconds
Started Sep 24 04:40:18 AM UTC 24
Finished Sep 24 04:40:43 AM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3094070030 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 484.prim_prince_test.3094070030
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/484.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/485.prim_prince_test.3374929705
Short name T489
Test name
Test status
Simulation time 2886972560 ps
CPU time 52.75 seconds
Started Sep 24 04:40:18 AM UTC 24
Finished Sep 24 04:41:27 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3374929705 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 485.prim_prince_test.3374929705
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/485.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/486.prim_prince_test.3283065535
Short name T491
Test name
Test status
Simulation time 2766418323 ps
CPU time 51.57 seconds
Started Sep 24 04:40:21 AM UTC 24
Finished Sep 24 04:41:29 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3283065535 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 486.prim_prince_test.3283065535
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/486.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/487.prim_prince_test.1848489243
Short name T487
Test name
Test status
Simulation time 2160552905 ps
CPU time 41.94 seconds
Started Sep 24 04:40:25 AM UTC 24
Finished Sep 24 04:41:19 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1848489243 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 487.prim_prince_test.1848489243
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/487.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/488.prim_prince_test.3422274140
Short name T478
Test name
Test status
Simulation time 1698502203 ps
CPU time 31.38 seconds
Started Sep 24 04:40:25 AM UTC 24
Finished Sep 24 04:41:06 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3422274140 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 488.prim_prince_test.3422274140
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/488.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/489.prim_prince_test.3879413140
Short name T483
Test name
Test status
Simulation time 1683674096 ps
CPU time 30.82 seconds
Started Sep 24 04:40:33 AM UTC 24
Finished Sep 24 04:41:14 AM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3879413140 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 489.prim_prince_test.3879413140
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/489.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/49.prim_prince_test.2808433599
Short name T54
Test name
Test status
Simulation time 3094119465 ps
CPU time 58.47 seconds
Started Sep 24 04:25:54 AM UTC 24
Finished Sep 24 04:27:09 AM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2808433599 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 49.prim_prince_test.2808433599
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/49.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/490.prim_prince_test.2771684388
Short name T496
Test name
Test status
Simulation time 3538903130 ps
CPU time 65.19 seconds
Started Sep 24 04:40:33 AM UTC 24
Finished Sep 24 04:41:59 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2771684388 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 490.prim_prince_test.2771684388
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/490.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/491.prim_prince_test.562202909
Short name T495
Test name
Test status
Simulation time 2792339192 ps
CPU time 52.79 seconds
Started Sep 24 04:40:35 AM UTC 24
Finished Sep 24 04:41:44 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=562202909 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 491.prim_prince_test.562202909
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/491.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/492.prim_prince_test.1129549366
Short name T490
Test name
Test status
Simulation time 1951635069 ps
CPU time 35.95 seconds
Started Sep 24 04:40:40 AM UTC 24
Finished Sep 24 04:41:28 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1129549366 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 492.prim_prince_test.1129549366
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/492.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/493.prim_prince_test.3116739167
Short name T492
Test name
Test status
Simulation time 1954982206 ps
CPU time 38.07 seconds
Started Sep 24 04:40:44 AM UTC 24
Finished Sep 24 04:41:34 AM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3116739167 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 493.prim_prince_test.3116739167
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/493.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/494.prim_prince_test.3132646126
Short name T485
Test name
Test status
Simulation time 1237759281 ps
CPU time 23.05 seconds
Started Sep 24 04:40:44 AM UTC 24
Finished Sep 24 04:41:15 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3132646126 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 494.prim_prince_test.3132646126
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/494.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/495.prim_prince_test.3015792949
Short name T497
Test name
Test status
Simulation time 2995848533 ps
CPU time 57.25 seconds
Started Sep 24 04:40:44 AM UTC 24
Finished Sep 24 04:41:59 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3015792949 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 495.prim_prince_test.3015792949
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/495.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/496.prim_prince_test.2968025156
Short name T500
Test name
Test status
Simulation time 3607643282 ps
CPU time 66.5 seconds
Started Sep 24 04:40:46 AM UTC 24
Finished Sep 24 04:42:14 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2968025156 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 496.prim_prince_test.2968025156
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/496.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/497.prim_prince_test.2766442219
Short name T499
Test name
Test status
Simulation time 3526915584 ps
CPU time 65.53 seconds
Started Sep 24 04:40:47 AM UTC 24
Finished Sep 24 04:42:14 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2766442219 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 497.prim_prince_test.2766442219
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/497.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/498.prim_prince_test.236534095
Short name T480
Test name
Test status
Simulation time 797523533 ps
CPU time 14.96 seconds
Started Sep 24 04:40:50 AM UTC 24
Finished Sep 24 04:41:10 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=236534095 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 498.prim_prince_test.236534095
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/498.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/499.prim_prince_test.643740183
Short name T498
Test name
Test status
Simulation time 2746455968 ps
CPU time 53.82 seconds
Started Sep 24 04:40:51 AM UTC 24
Finished Sep 24 04:42:01 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=643740183 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 499.prim_prince_test.643740183
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/499.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/5.prim_prince_test.1261696491
Short name T8
Test name
Test status
Simulation time 2025910566 ps
CPU time 38.19 seconds
Started Sep 24 04:24:10 AM UTC 24
Finished Sep 24 04:25:00 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1261696491 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 5.prim_prince_test.1261696491
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/5.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/50.prim_prince_test.3184063223
Short name T37
Test name
Test status
Simulation time 1134768808 ps
CPU time 22.06 seconds
Started Sep 24 04:25:54 AM UTC 24
Finished Sep 24 04:26:23 AM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3184063223 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 50.prim_prince_test.3184063223
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/50.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/51.prim_prince_test.3691851218
Short name T42
Test name
Test status
Simulation time 1535708830 ps
CPU time 28.73 seconds
Started Sep 24 04:25:56 AM UTC 24
Finished Sep 24 04:26:34 AM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3691851218 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 51.prim_prince_test.3691851218
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/51.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/52.prim_prince_test.2086883823
Short name T64
Test name
Test status
Simulation time 3225239911 ps
CPU time 62.78 seconds
Started Sep 24 04:26:02 AM UTC 24
Finished Sep 24 04:27:22 AM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2086883823 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 52.prim_prince_test.2086883823
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/52.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/53.prim_prince_test.2198824754
Short name T38
Test name
Test status
Simulation time 862236738 ps
CPU time 16.79 seconds
Started Sep 24 04:26:05 AM UTC 24
Finished Sep 24 04:26:27 AM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2198824754 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 53.prim_prince_test.2198824754
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/53.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/54.prim_prince_test.3774590924
Short name T66
Test name
Test status
Simulation time 3235427833 ps
CPU time 62.85 seconds
Started Sep 24 04:26:05 AM UTC 24
Finished Sep 24 04:27:25 AM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3774590924 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 54.prim_prince_test.3774590924
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/54.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/55.prim_prince_test.2894575301
Short name T57
Test name
Test status
Simulation time 2755576492 ps
CPU time 50.83 seconds
Started Sep 24 04:26:06 AM UTC 24
Finished Sep 24 04:27:11 AM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2894575301 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 55.prim_prince_test.2894575301
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/55.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/56.prim_prince_test.967480693
Short name T52
Test name
Test status
Simulation time 2271406315 ps
CPU time 41.98 seconds
Started Sep 24 04:26:10 AM UTC 24
Finished Sep 24 04:27:04 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=967480693 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 56.prim_prince_test.967480693
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/56.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/57.prim_prince_test.2331750584
Short name T58
Test name
Test status
Simulation time 2352201897 ps
CPU time 43.83 seconds
Started Sep 24 04:26:16 AM UTC 24
Finished Sep 24 04:27:13 AM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2331750584 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 57.prim_prince_test.2331750584
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/57.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/58.prim_prince_test.627369211
Short name T62
Test name
Test status
Simulation time 2380702367 ps
CPU time 46.64 seconds
Started Sep 24 04:26:18 AM UTC 24
Finished Sep 24 04:27:18 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=627369211 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 58.prim_prince_test.627369211
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/58.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/59.prim_prince_test.4091101919
Short name T61
Test name
Test status
Simulation time 2348031827 ps
CPU time 45.81 seconds
Started Sep 24 04:26:18 AM UTC 24
Finished Sep 24 04:27:17 AM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4091101919 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 59.prim_prince_test.4091101919
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/59.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/6.prim_prince_test.1476362729
Short name T7
Test name
Test status
Simulation time 1850519817 ps
CPU time 34.99 seconds
Started Sep 24 04:24:12 AM UTC 24
Finished Sep 24 04:24:57 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1476362729 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 6.prim_prince_test.1476362729
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/6.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/60.prim_prince_test.69895356
Short name T46
Test name
Test status
Simulation time 887732910 ps
CPU time 16.68 seconds
Started Sep 24 04:26:19 AM UTC 24
Finished Sep 24 04:26:41 AM UTC 24
Peak memory 154984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=69895356 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 60.prim_prince_test.69895356
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/60.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/61.prim_prince_test.3349771395
Short name T56
Test name
Test status
Simulation time 2026890797 ps
CPU time 39.65 seconds
Started Sep 24 04:26:20 AM UTC 24
Finished Sep 24 04:27:11 AM UTC 24
Peak memory 154952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3349771395 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 61.prim_prince_test.3349771395
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/61.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/62.prim_prince_test.4097483141
Short name T70
Test name
Test status
Simulation time 2917979030 ps
CPU time 57.52 seconds
Started Sep 24 04:26:24 AM UTC 24
Finished Sep 24 04:27:37 AM UTC 24
Peak memory 156396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4097483141 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 62.prim_prince_test.4097483141
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/62.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/63.prim_prince_test.22046609
Short name T79
Test name
Test status
Simulation time 3257063809 ps
CPU time 64.18 seconds
Started Sep 24 04:26:27 AM UTC 24
Finished Sep 24 04:27:49 AM UTC 24
Peak memory 155048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22046609 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 63.prim_prince_test.22046609
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/63.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/64.prim_prince_test.117781295
Short name T67
Test name
Test status
Simulation time 2369417165 ps
CPU time 44.4 seconds
Started Sep 24 04:26:27 AM UTC 24
Finished Sep 24 04:27:25 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=117781295 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 64.prim_prince_test.117781295
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/64.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/65.prim_prince_test.2551365806
Short name T65
Test name
Test status
Simulation time 2325635312 ps
CPU time 43.13 seconds
Started Sep 24 04:26:28 AM UTC 24
Finished Sep 24 04:27:24 AM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2551365806 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 65.prim_prince_test.2551365806
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/65.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/66.prim_prince_test.2571722381
Short name T68
Test name
Test status
Simulation time 2316821351 ps
CPU time 45.79 seconds
Started Sep 24 04:26:31 AM UTC 24
Finished Sep 24 04:27:30 AM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2571722381 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 66.prim_prince_test.2571722381
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/66.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/67.prim_prince_test.2238724158
Short name T74
Test name
Test status
Simulation time 2690026190 ps
CPU time 51.02 seconds
Started Sep 24 04:26:34 AM UTC 24
Finished Sep 24 04:27:40 AM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2238724158 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 67.prim_prince_test.2238724158
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/67.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/68.prim_prince_test.1114327690
Short name T63
Test name
Test status
Simulation time 1862147871 ps
CPU time 34.87 seconds
Started Sep 24 04:26:37 AM UTC 24
Finished Sep 24 04:27:22 AM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1114327690 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 68.prim_prince_test.1114327690
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/68.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/69.prim_prince_test.3784204867
Short name T76
Test name
Test status
Simulation time 2736629948 ps
CPU time 50.73 seconds
Started Sep 24 04:26:38 AM UTC 24
Finished Sep 24 04:27:43 AM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3784204867 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 69.prim_prince_test.3784204867
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/69.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/7.prim_prince_test.4270848186
Short name T11
Test name
Test status
Simulation time 2270995501 ps
CPU time 43.41 seconds
Started Sep 24 04:24:12 AM UTC 24
Finished Sep 24 04:25:07 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4270848186 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 7.prim_prince_test.4270848186
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/7.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/70.prim_prince_test.3945632618
Short name T85
Test name
Test status
Simulation time 3537761957 ps
CPU time 66.04 seconds
Started Sep 24 04:26:40 AM UTC 24
Finished Sep 24 04:28:05 AM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3945632618 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 70.prim_prince_test.3945632618
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/70.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/71.prim_prince_test.2031810211
Short name T53
Test name
Test status
Simulation time 961097697 ps
CPU time 18.28 seconds
Started Sep 24 04:26:42 AM UTC 24
Finished Sep 24 04:27:06 AM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2031810211 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 71.prim_prince_test.2031810211
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/71.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/72.prim_prince_test.1119308531
Short name T60
Test name
Test status
Simulation time 1244792326 ps
CPU time 23.62 seconds
Started Sep 24 04:26:44 AM UTC 24
Finished Sep 24 04:27:15 AM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1119308531 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 72.prim_prince_test.1119308531
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/72.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/73.prim_prince_test.2415836836
Short name T81
Test name
Test status
Simulation time 2887128009 ps
CPU time 54.32 seconds
Started Sep 24 04:26:46 AM UTC 24
Finished Sep 24 04:27:56 AM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2415836836 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 73.prim_prince_test.2415836836
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/73.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/74.prim_prince_test.2289172084
Short name T71
Test name
Test status
Simulation time 1878200997 ps
CPU time 36.06 seconds
Started Sep 24 04:26:51 AM UTC 24
Finished Sep 24 04:27:37 AM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2289172084 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 74.prim_prince_test.2289172084
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/74.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/75.prim_prince_test.439351037
Short name T83
Test name
Test status
Simulation time 2785139585 ps
CPU time 51.32 seconds
Started Sep 24 04:26:52 AM UTC 24
Finished Sep 24 04:27:59 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=439351037 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 75.prim_prince_test.439351037
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/75.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/76.prim_prince_test.3026763188
Short name T91
Test name
Test status
Simulation time 3494665401 ps
CPU time 64.11 seconds
Started Sep 24 04:26:54 AM UTC 24
Finished Sep 24 04:28:17 AM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3026763188 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 76.prim_prince_test.3026763188
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/76.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/77.prim_prince_test.296537351
Short name T100
Test name
Test status
Simulation time 3737934205 ps
CPU time 69.4 seconds
Started Sep 24 04:27:05 AM UTC 24
Finished Sep 24 04:28:35 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=296537351 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 77.prim_prince_test.296537351
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/77.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/78.prim_prince_test.1942590491
Short name T87
Test name
Test status
Simulation time 2559039079 ps
CPU time 47.45 seconds
Started Sep 24 04:27:06 AM UTC 24
Finished Sep 24 04:28:08 AM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1942590491 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 78.prim_prince_test.1942590491
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/78.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/79.prim_prince_test.2583691853
Short name T75
Test name
Test status
Simulation time 1149121167 ps
CPU time 23.08 seconds
Started Sep 24 04:27:10 AM UTC 24
Finished Sep 24 04:27:40 AM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2583691853 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 79.prim_prince_test.2583691853
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/79.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/8.prim_prince_test.3103053293
Short name T20
Test name
Test status
Simulation time 3619048183 ps
CPU time 66.67 seconds
Started Sep 24 04:24:13 AM UTC 24
Finished Sep 24 04:25:38 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3103053293 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 8.prim_prince_test.3103053293
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/8.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/80.prim_prince_test.3385444108
Short name T73
Test name
Test status
Simulation time 1145528116 ps
CPU time 22.15 seconds
Started Sep 24 04:27:10 AM UTC 24
Finished Sep 24 04:27:39 AM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3385444108 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 80.prim_prince_test.3385444108
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/80.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/81.prim_prince_test.1290521035
Short name T93
Test name
Test status
Simulation time 2778947264 ps
CPU time 53.43 seconds
Started Sep 24 04:27:11 AM UTC 24
Finished Sep 24 04:28:20 AM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1290521035 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 81.prim_prince_test.1290521035
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/81.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/82.prim_prince_test.843533465
Short name T88
Test name
Test status
Simulation time 2303334335 ps
CPU time 45.27 seconds
Started Sep 24 04:27:13 AM UTC 24
Finished Sep 24 04:28:10 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=843533465 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 82.prim_prince_test.843533465
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/82.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/83.prim_prince_test.2637342960
Short name T69
Test name
Test status
Simulation time 862722330 ps
CPU time 17.33 seconds
Started Sep 24 04:27:14 AM UTC 24
Finished Sep 24 04:27:36 AM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2637342960 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 83.prim_prince_test.2637342960
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/83.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/84.prim_prince_test.2920326545
Short name T92
Test name
Test status
Simulation time 2556905949 ps
CPU time 48.71 seconds
Started Sep 24 04:27:15 AM UTC 24
Finished Sep 24 04:28:17 AM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2920326545 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 84.prim_prince_test.2920326545
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/84.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/85.prim_prince_test.3084196218
Short name T72
Test name
Test status
Simulation time 874068724 ps
CPU time 17.49 seconds
Started Sep 24 04:27:16 AM UTC 24
Finished Sep 24 04:27:39 AM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3084196218 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 85.prim_prince_test.3084196218
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/85.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/86.prim_prince_test.208862656
Short name T95
Test name
Test status
Simulation time 2652830568 ps
CPU time 50.06 seconds
Started Sep 24 04:27:18 AM UTC 24
Finished Sep 24 04:28:23 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=208862656 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 86.prim_prince_test.208862656
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/86.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/87.prim_prince_test.3438656307
Short name T78
Test name
Test status
Simulation time 1074782688 ps
CPU time 21.54 seconds
Started Sep 24 04:27:19 AM UTC 24
Finished Sep 24 04:27:47 AM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3438656307 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 87.prim_prince_test.3438656307
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/87.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/88.prim_prince_test.3269829212
Short name T105
Test name
Test status
Simulation time 3140618500 ps
CPU time 61.89 seconds
Started Sep 24 04:27:23 AM UTC 24
Finished Sep 24 04:28:42 AM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3269829212 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 88.prim_prince_test.3269829212
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/88.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/89.prim_prince_test.2335052225
Short name T101
Test name
Test status
Simulation time 2968227970 ps
CPU time 56.56 seconds
Started Sep 24 04:27:23 AM UTC 24
Finished Sep 24 04:28:36 AM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2335052225 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 89.prim_prince_test.2335052225
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/89.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/9.prim_prince_test.2905030093
Short name T14
Test name
Test status
Simulation time 2954720691 ps
CPU time 54.99 seconds
Started Sep 24 04:24:13 AM UTC 24
Finished Sep 24 04:25:24 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2905030093 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 9.prim_prince_test.2905030093
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/9.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/90.prim_prince_test.3406638763
Short name T94
Test name
Test status
Simulation time 2335138655 ps
CPU time 43.44 seconds
Started Sep 24 04:27:25 AM UTC 24
Finished Sep 24 04:28:22 AM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3406638763 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 90.prim_prince_test.3406638763
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/90.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/91.prim_prince_test.2433796778
Short name T80
Test name
Test status
Simulation time 1080432456 ps
CPU time 21.69 seconds
Started Sep 24 04:27:25 AM UTC 24
Finished Sep 24 04:27:53 AM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2433796778 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 91.prim_prince_test.2433796778
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/91.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/92.prim_prince_test.2189514108
Short name T77
Test name
Test status
Simulation time 801388640 ps
CPU time 16.31 seconds
Started Sep 24 04:27:25 AM UTC 24
Finished Sep 24 04:27:47 AM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2189514108 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 92.prim_prince_test.2189514108
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/92.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/93.prim_prince_test.1160686153
Short name T82
Test name
Test status
Simulation time 1008656762 ps
CPU time 19.02 seconds
Started Sep 24 04:27:31 AM UTC 24
Finished Sep 24 04:27:57 AM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1160686153 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 93.prim_prince_test.1160686153
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/93.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/94.prim_prince_test.3143633381
Short name T102
Test name
Test status
Simulation time 2432649835 ps
CPU time 44.81 seconds
Started Sep 24 04:27:37 AM UTC 24
Finished Sep 24 04:28:36 AM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3143633381 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 94.prim_prince_test.3143633381
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/94.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/95.prim_prince_test.3122707151
Short name T99
Test name
Test status
Simulation time 2315064901 ps
CPU time 42.71 seconds
Started Sep 24 04:27:38 AM UTC 24
Finished Sep 24 04:28:34 AM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3122707151 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 95.prim_prince_test.3122707151
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/95.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/96.prim_prince_test.1215274793
Short name T110
Test name
Test status
Simulation time 3113099014 ps
CPU time 57.21 seconds
Started Sep 24 04:27:38 AM UTC 24
Finished Sep 24 04:28:53 AM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1215274793 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 96.prim_prince_test.1215274793
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/96.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/97.prim_prince_test.2296988777
Short name T86
Test name
Test status
Simulation time 1069693434 ps
CPU time 20.28 seconds
Started Sep 24 04:27:40 AM UTC 24
Finished Sep 24 04:28:06 AM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2296988777 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 97.prim_prince_test.2296988777
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/97.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/98.prim_prince_test.2117116195
Short name T89
Test name
Test status
Simulation time 1233128050 ps
CPU time 24.26 seconds
Started Sep 24 04:27:41 AM UTC 24
Finished Sep 24 04:28:13 AM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2117116195 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 98.prim_prince_test.2117116195
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/98.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default/99.prim_prince_test.3319536013
Short name T90
Test name
Test status
Simulation time 1306942267 ps
CPU time 24.69 seconds
Started Sep 24 04:27:41 AM UTC 24
Finished Sep 24 04:28:14 AM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3319536013 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 99.prim_prince_test.3319536013
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_prince-sim-vcs/99.prim_prince_test/latest
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