| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 | 100.00 | 100.00 | 100.00 | 100.00 |
| T251 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/280.prim_prince_test.1792704244 | Oct 02 06:28:09 PM UTC 24 | Oct 02 06:28:30 PM UTC 24 | 822179526 ps | ||
| T252 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/278.prim_prince_test.869864688 | Oct 02 06:28:08 PM UTC 24 | Oct 02 06:28:31 PM UTC 24 | 866788311 ps | ||
| T253 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/274.prim_prince_test.969918175 | Oct 02 06:28:07 PM UTC 24 | Oct 02 06:28:34 PM UTC 24 | 1058139058 ps | ||
| T254 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/253.prim_prince_test.1262120207 | Oct 02 06:27:41 PM UTC 24 | Oct 02 06:28:34 PM UTC 24 | 2155522479 ps | ||
| T255 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/268.prim_prince_test.1925653361 | Oct 02 06:28:01 PM UTC 24 | Oct 02 06:28:34 PM UTC 24 | 1378644322 ps | ||
| T256 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/276.prim_prince_test.1374897747 | Oct 02 06:28:07 PM UTC 24 | Oct 02 06:28:35 PM UTC 24 | 1081950706 ps | ||
| T257 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/259.prim_prince_test.2751130589 | Oct 02 06:27:48 PM UTC 24 | Oct 02 06:28:35 PM UTC 24 | 1951072432 ps | ||
| T258 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/235.prim_prince_test.4125268227 | Oct 02 06:27:20 PM UTC 24 | Oct 02 06:28:37 PM UTC 24 | 3247289694 ps | ||
| T259 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/275.prim_prince_test.1296541791 | Oct 02 06:28:07 PM UTC 24 | Oct 02 06:28:38 PM UTC 24 | 1219951832 ps | ||
| T260 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/272.prim_prince_test.1870288084 | Oct 02 06:28:03 PM UTC 24 | Oct 02 06:28:40 PM UTC 24 | 1509704018 ps | ||
| T261 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/290.prim_prince_test.1381025246 | Oct 02 06:28:18 PM UTC 24 | Oct 02 06:28:42 PM UTC 24 | 903150355 ps | ||
| T262 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/236.prim_prince_test.1044394862 | Oct 02 06:27:20 PM UTC 24 | Oct 02 06:28:43 PM UTC 24 | 3337662224 ps | ||
| T263 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/266.prim_prince_test.3625076895 | Oct 02 06:27:59 PM UTC 24 | Oct 02 06:28:44 PM UTC 24 | 1864936428 ps | ||
| T264 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/264.prim_prince_test.604921345 | Oct 02 06:27:55 PM UTC 24 | Oct 02 06:28:44 PM UTC 24 | 1929882366 ps | ||
| T265 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/256.prim_prince_test.33735219 | Oct 02 06:27:47 PM UTC 24 | Oct 02 06:28:44 PM UTC 24 | 2370139401 ps | ||
| T266 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/245.prim_prince_test.2217207268 | Oct 02 06:27:28 PM UTC 24 | Oct 02 06:28:45 PM UTC 24 | 3048558824 ps | ||
| T267 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/277.prim_prince_test.776642443 | Oct 02 06:28:07 PM UTC 24 | Oct 02 06:28:45 PM UTC 24 | 1514550171 ps | ||
| T268 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/271.prim_prince_test.3987360817 | Oct 02 06:28:02 PM UTC 24 | Oct 02 06:28:48 PM UTC 24 | 1888931619 ps | ||
| T269 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/265.prim_prince_test.3443067085 | Oct 02 06:27:56 PM UTC 24 | Oct 02 06:28:48 PM UTC 24 | 2039874925 ps | ||
| T270 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/247.prim_prince_test.41344659 | Oct 02 06:27:35 PM UTC 24 | Oct 02 06:28:52 PM UTC 24 | 3203790352 ps | ||
| T271 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/260.prim_prince_test.1891823610 | Oct 02 06:27:49 PM UTC 24 | Oct 02 06:28:52 PM UTC 24 | 2587126835 ps | ||
| T272 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/258.prim_prince_test.2614700762 | Oct 02 06:27:47 PM UTC 24 | Oct 02 06:28:54 PM UTC 24 | 2859275581 ps | ||
| T273 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/295.prim_prince_test.2227112884 | Oct 02 06:28:27 PM UTC 24 | Oct 02 06:28:58 PM UTC 24 | 1184376900 ps | ||
| T274 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/301.prim_prince_test.398300722 | Oct 02 06:28:32 PM UTC 24 | Oct 02 06:28:59 PM UTC 24 | 1092305344 ps | ||
| T275 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/289.prim_prince_test.3486702811 | Oct 02 06:28:18 PM UTC 24 | Oct 02 06:29:00 PM UTC 24 | 1675098482 ps | ||
| T276 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/293.prim_prince_test.2698958217 | Oct 02 06:28:24 PM UTC 24 | Oct 02 06:29:00 PM UTC 24 | 1399290342 ps | ||
| T277 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/250.prim_prince_test.2764236797 | Oct 02 06:27:36 PM UTC 24 | Oct 02 06:29:01 PM UTC 24 | 3582344986 ps | ||
| T278 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/302.prim_prince_test.283303106 | Oct 02 06:28:35 PM UTC 24 | Oct 02 06:29:01 PM UTC 24 | 984208591 ps | ||
| T279 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/292.prim_prince_test.1247778738 | Oct 02 06:28:23 PM UTC 24 | Oct 02 06:29:02 PM UTC 24 | 1602676349 ps | ||
| T280 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/287.prim_prince_test.3118408767 | Oct 02 06:28:18 PM UTC 24 | Oct 02 06:29:02 PM UTC 24 | 1704894839 ps | ||
| T281 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/300.prim_prince_test.4082022825 | Oct 02 06:28:31 PM UTC 24 | Oct 02 06:29:05 PM UTC 24 | 1363131554 ps | ||
| T282 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/251.prim_prince_test.732406519 | Oct 02 06:27:37 PM UTC 24 | Oct 02 06:29:06 PM UTC 24 | 3701650569 ps | ||
| T283 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/283.prim_prince_test.37187535 | Oct 02 06:28:12 PM UTC 24 | Oct 02 06:29:07 PM UTC 24 | 2138366138 ps | ||
| T284 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/261.prim_prince_test.1238542834 | Oct 02 06:27:51 PM UTC 24 | Oct 02 06:29:08 PM UTC 24 | 3265832133 ps | ||
| T285 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/281.prim_prince_test.4199611004 | Oct 02 06:28:09 PM UTC 24 | Oct 02 06:29:09 PM UTC 24 | 2448563881 ps | ||
| T286 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/267.prim_prince_test.2959402268 | Oct 02 06:28:00 PM UTC 24 | Oct 02 06:29:09 PM UTC 24 | 2929204159 ps | ||
| T287 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/273.prim_prince_test.3810003798 | Oct 02 06:28:05 PM UTC 24 | Oct 02 06:29:10 PM UTC 24 | 2726121915 ps | ||
| T288 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/254.prim_prince_test.1724574546 | Oct 02 06:27:42 PM UTC 24 | Oct 02 06:29:11 PM UTC 24 | 3602483912 ps | ||
| T289 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/299.prim_prince_test.1844559861 | Oct 02 06:28:31 PM UTC 24 | Oct 02 06:29:12 PM UTC 24 | 1595122373 ps | ||
| T290 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/298.prim_prince_test.1987535391 | Oct 02 06:28:30 PM UTC 24 | Oct 02 06:29:13 PM UTC 24 | 1643843493 ps | ||
| T291 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/284.prim_prince_test.463140114 | Oct 02 06:28:13 PM UTC 24 | Oct 02 06:29:14 PM UTC 24 | 2429973887 ps | ||
| T292 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/279.prim_prince_test.1972936032 | Oct 02 06:28:08 PM UTC 24 | Oct 02 06:29:14 PM UTC 24 | 2766423954 ps | ||
| T293 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/306.prim_prince_test.3177075121 | Oct 02 06:28:36 PM UTC 24 | Oct 02 06:29:17 PM UTC 24 | 1575705189 ps | ||
| T294 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/314.prim_prince_test.1679162248 | Oct 02 06:28:45 PM UTC 24 | Oct 02 06:29:20 PM UTC 24 | 1355695255 ps | ||
| T295 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/270.prim_prince_test.1090175179 | Oct 02 06:28:02 PM UTC 24 | Oct 02 06:29:20 PM UTC 24 | 3218998511 ps | ||
| T296 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/309.prim_prince_test.3097915149 | Oct 02 06:28:41 PM UTC 24 | Oct 02 06:29:21 PM UTC 24 | 1660827197 ps | ||
| T297 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/263.prim_prince_test.1897056135 | Oct 02 06:27:54 PM UTC 24 | Oct 02 06:29:21 PM UTC 24 | 3500678517 ps | ||
| T298 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/262.prim_prince_test.3036016074 | Oct 02 06:27:51 PM UTC 24 | Oct 02 06:29:22 PM UTC 24 | 3700202615 ps | ||
| T299 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/269.prim_prince_test.951991053 | Oct 02 06:28:01 PM UTC 24 | Oct 02 06:29:22 PM UTC 24 | 3437083198 ps | ||
| T300 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/326.prim_prince_test.784580683 | Oct 02 06:29:01 PM UTC 24 | Oct 02 06:29:26 PM UTC 24 | 917769369 ps | ||
| T301 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/288.prim_prince_test.3021457528 | Oct 02 06:28:18 PM UTC 24 | Oct 02 06:29:27 PM UTC 24 | 2797632926 ps | ||
| T302 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/308.prim_prince_test.3125621890 | Oct 02 06:28:39 PM UTC 24 | Oct 02 06:29:29 PM UTC 24 | 1936356225 ps | ||
| T303 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/294.prim_prince_test.1117294041 | Oct 02 06:28:24 PM UTC 24 | Oct 02 06:29:29 PM UTC 24 | 2763228397 ps | ||
| T304 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/316.prim_prince_test.3305465160 | Oct 02 06:28:46 PM UTC 24 | Oct 02 06:29:31 PM UTC 24 | 1876010777 ps | ||
| T305 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/320.prim_prince_test.1047256464 | Oct 02 06:28:53 PM UTC 24 | Oct 02 06:29:34 PM UTC 24 | 1547515937 ps | ||
| T306 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/305.prim_prince_test.3876077126 | Oct 02 06:28:35 PM UTC 24 | Oct 02 06:29:34 PM UTC 24 | 2460084211 ps | ||
| T307 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/322.prim_prince_test.2728386330 | Oct 02 06:28:55 PM UTC 24 | Oct 02 06:29:36 PM UTC 24 | 1557978358 ps | ||
| T308 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/312.prim_prince_test.3634764764 | Oct 02 06:28:44 PM UTC 24 | Oct 02 06:29:36 PM UTC 24 | 2066281213 ps | ||
| T309 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/296.prim_prince_test.1019297642 | Oct 02 06:28:27 PM UTC 24 | Oct 02 06:29:37 PM UTC 24 | 2881508878 ps | ||
| T310 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/334.prim_prince_test.2891854906 | Oct 02 06:29:09 PM UTC 24 | Oct 02 06:29:38 PM UTC 24 | 1126935044 ps | ||
| T311 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/331.prim_prince_test.3220474218 | Oct 02 06:29:06 PM UTC 24 | Oct 02 06:29:41 PM UTC 24 | 1419410518 ps | ||
| T312 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/319.prim_prince_test.1029385897 | Oct 02 06:28:49 PM UTC 24 | Oct 02 06:29:41 PM UTC 24 | 2182669595 ps | ||
| T313 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/332.prim_prince_test.1235864637 | Oct 02 06:29:07 PM UTC 24 | Oct 02 06:29:41 PM UTC 24 | 1287642437 ps | ||
| T314 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/307.prim_prince_test.3150711851 | Oct 02 06:28:37 PM UTC 24 | Oct 02 06:29:41 PM UTC 24 | 2684429067 ps | ||
| T315 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/285.prim_prince_test.237641989 | Oct 02 06:28:15 PM UTC 24 | Oct 02 06:29:42 PM UTC 24 | 3683705426 ps | ||
| T316 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/304.prim_prince_test.4131427365 | Oct 02 06:28:35 PM UTC 24 | Oct 02 06:29:42 PM UTC 24 | 2836773029 ps | ||
| T317 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/286.prim_prince_test.2756369345 | Oct 02 06:28:17 PM UTC 24 | Oct 02 06:29:45 PM UTC 24 | 3703008547 ps | ||
| T318 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/297.prim_prince_test.3046891477 | Oct 02 06:28:29 PM UTC 24 | Oct 02 06:29:49 PM UTC 24 | 3226127387 ps | ||
| T319 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/291.prim_prince_test.3868022219 | Oct 02 06:28:21 PM UTC 24 | Oct 02 06:29:49 PM UTC 24 | 3519639498 ps | ||
| T320 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/310.prim_prince_test.3204286485 | Oct 02 06:28:41 PM UTC 24 | Oct 02 06:29:49 PM UTC 24 | 2690307838 ps | ||
| T321 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/318.prim_prince_test.1218785493 | Oct 02 06:28:49 PM UTC 24 | Oct 02 06:29:49 PM UTC 24 | 2540362045 ps | ||
| T322 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/335.prim_prince_test.906070776 | Oct 02 06:29:09 PM UTC 24 | Oct 02 06:29:50 PM UTC 24 | 1670574982 ps | ||
| T323 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/333.prim_prince_test.3002472487 | Oct 02 06:29:08 PM UTC 24 | Oct 02 06:30:05 PM UTC 24 | 2213184883 ps | ||
| T324 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/341.prim_prince_test.2736829022 | Oct 02 06:29:15 PM UTC 24 | Oct 02 06:29:52 PM UTC 24 | 1490222132 ps | ||
| T325 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/329.prim_prince_test.2061304040 | Oct 02 06:29:04 PM UTC 24 | Oct 02 06:29:54 PM UTC 24 | 1897698543 ps | ||
| T326 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/311.prim_prince_test.93239060 | Oct 02 06:28:43 PM UTC 24 | Oct 02 06:29:54 PM UTC 24 | 2804185666 ps | ||
| T327 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/352.prim_prince_test.420682507 | Oct 02 06:29:30 PM UTC 24 | Oct 02 06:29:57 PM UTC 24 | 1004573553 ps | ||
| T328 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/315.prim_prince_test.250819922 | Oct 02 06:28:46 PM UTC 24 | Oct 02 06:29:58 PM UTC 24 | 3047250830 ps | ||
| T329 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/356.prim_prince_test.2836676833 | Oct 02 06:29:35 PM UTC 24 | Oct 02 06:29:59 PM UTC 24 | 934208286 ps | ||
| T330 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/348.prim_prince_test.1241052657 | Oct 02 06:29:23 PM UTC 24 | Oct 02 06:29:59 PM UTC 24 | 1418579650 ps | ||
| T331 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/345.prim_prince_test.2371634204 | Oct 02 06:29:21 PM UTC 24 | Oct 02 06:30:02 PM UTC 24 | 1708001535 ps | ||
| T332 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/317.prim_prince_test.1564577134 | Oct 02 06:28:46 PM UTC 24 | Oct 02 06:30:03 PM UTC 24 | 3269858371 ps | ||
| T333 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/325.prim_prince_test.790239461 | Oct 02 06:29:01 PM UTC 24 | Oct 02 06:30:04 PM UTC 24 | 2381716924 ps | ||
| T334 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/303.prim_prince_test.1512192785 | Oct 02 06:28:35 PM UTC 24 | Oct 02 06:30:04 PM UTC 24 | 3425426867 ps | ||
| T335 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/340.prim_prince_test.2488976745 | Oct 02 06:29:14 PM UTC 24 | Oct 02 06:30:04 PM UTC 24 | 1926311418 ps | ||
| T336 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/336.prim_prince_test.3393278653 | Oct 02 06:29:10 PM UTC 24 | Oct 02 06:30:05 PM UTC 24 | 2069884176 ps | ||
| T337 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/337.prim_prince_test.2098855894 | Oct 02 06:29:12 PM UTC 24 | Oct 02 06:30:07 PM UTC 24 | 2176212576 ps | ||
| T338 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/342.prim_prince_test.1665956192 | Oct 02 06:29:15 PM UTC 24 | Oct 02 06:30:08 PM UTC 24 | 2018854253 ps | ||
| T339 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/347.prim_prince_test.2150269740 | Oct 02 06:29:23 PM UTC 24 | Oct 02 06:30:08 PM UTC 24 | 1855873585 ps | ||
| T340 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/324.prim_prince_test.1989855975 | Oct 02 06:29:00 PM UTC 24 | Oct 02 06:30:09 PM UTC 24 | 2837265029 ps | ||
| T341 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/361.prim_prince_test.3576569098 | Oct 02 06:29:39 PM UTC 24 | Oct 02 06:30:11 PM UTC 24 | 1173443214 ps | ||
| T342 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/371.prim_prince_test.3331527572 | Oct 02 06:29:50 PM UTC 24 | Oct 02 06:30:13 PM UTC 24 | 892389273 ps | ||
| T343 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/313.prim_prince_test.2193308765 | Oct 02 06:28:44 PM UTC 24 | Oct 02 06:30:13 PM UTC 24 | 3383877345 ps | ||
| T344 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/366.prim_prince_test.1749885532 | Oct 02 06:29:44 PM UTC 24 | Oct 02 06:30:14 PM UTC 24 | 1119500425 ps | ||
| T345 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/368.prim_prince_test.4162354803 | Oct 02 06:29:44 PM UTC 24 | Oct 02 06:30:16 PM UTC 24 | 1280778318 ps | ||
| T346 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/339.prim_prince_test.3081297973 | Oct 02 06:29:13 PM UTC 24 | Oct 02 06:30:16 PM UTC 24 | 2631487907 ps | ||
| T347 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/349.prim_prince_test.2942141534 | Oct 02 06:29:23 PM UTC 24 | Oct 02 06:30:18 PM UTC 24 | 2076848624 ps | ||
| T348 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/330.prim_prince_test.818226748 | Oct 02 06:29:04 PM UTC 24 | Oct 02 06:30:21 PM UTC 24 | 2968643631 ps | ||
| T349 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/328.prim_prince_test.2350713349 | Oct 02 06:29:02 PM UTC 24 | Oct 02 06:30:24 PM UTC 24 | 3391946536 ps | ||
| T350 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/363.prim_prince_test.2160656738 | Oct 02 06:29:42 PM UTC 24 | Oct 02 06:30:24 PM UTC 24 | 1710052228 ps | ||
| T351 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/343.prim_prince_test.4277394462 | Oct 02 06:29:18 PM UTC 24 | Oct 02 06:30:26 PM UTC 24 | 2567844139 ps | ||
| T352 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/323.prim_prince_test.3700847669 | Oct 02 06:28:58 PM UTC 24 | Oct 02 06:30:28 PM UTC 24 | 3440687255 ps | ||
| T353 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/321.prim_prince_test.1160797532 | Oct 02 06:28:53 PM UTC 24 | Oct 02 06:30:28 PM UTC 24 | 3741789171 ps | ||
| T354 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/346.prim_prince_test.3872788485 | Oct 02 06:29:22 PM UTC 24 | Oct 02 06:30:33 PM UTC 24 | 2948355242 ps | ||
| T355 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/388.prim_prince_test.923626355 | Oct 02 06:30:06 PM UTC 24 | Oct 02 06:30:34 PM UTC 24 | 1031045189 ps | ||
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| T357 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/370.prim_prince_test.4265986790 | Oct 02 06:29:50 PM UTC 24 | Oct 02 06:30:35 PM UTC 24 | 1870077931 ps | ||
| T358 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/374.prim_prince_test.2649979729 | Oct 02 06:29:52 PM UTC 24 | Oct 02 06:30:36 PM UTC 24 | 1773534551 ps | ||
| T359 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/373.prim_prince_test.3058057507 | Oct 02 06:29:50 PM UTC 24 | Oct 02 06:30:40 PM UTC 24 | 2003043448 ps | ||
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| T361 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/396.prim_prince_test.891248126 | Oct 02 06:30:14 PM UTC 24 | Oct 02 06:30:41 PM UTC 24 | 987760514 ps | ||
| T362 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/372.prim_prince_test.1573424376 | Oct 02 06:29:50 PM UTC 24 | Oct 02 06:30:42 PM UTC 24 | 2131147519 ps | ||
| T363 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/350.prim_prince_test.3734584604 | Oct 02 06:29:26 PM UTC 24 | Oct 02 06:30:43 PM UTC 24 | 3142866126 ps | ||
| T364 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/344.prim_prince_test.3553351765 | Oct 02 06:29:21 PM UTC 24 | Oct 02 06:30:43 PM UTC 24 | 3396163293 ps | ||
| T365 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/357.prim_prince_test.1837347461 | Oct 02 06:29:38 PM UTC 24 | Oct 02 06:30:43 PM UTC 24 | 2758795890 ps | ||
| T366 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/379.prim_prince_test.2190098589 | Oct 02 06:29:58 PM UTC 24 | Oct 02 06:30:45 PM UTC 24 | 1767746230 ps | ||
| T367 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/362.prim_prince_test.3343132446 | Oct 02 06:29:42 PM UTC 24 | Oct 02 06:30:46 PM UTC 24 | 2497388025 ps | ||
| T368 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/351.prim_prince_test.448983367 | Oct 02 06:29:27 PM UTC 24 | Oct 02 06:30:48 PM UTC 24 | 3327153002 ps | ||
| T369 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/402.prim_prince_test.1960262409 | Oct 02 06:30:22 PM UTC 24 | Oct 02 06:30:48 PM UTC 24 | 1007400266 ps | ||
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| T371 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/393.prim_prince_test.1760264592 | Oct 02 06:30:10 PM UTC 24 | Oct 02 06:30:52 PM UTC 24 | 1533094267 ps | ||
| T372 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/399.prim_prince_test.2028141589 | Oct 02 06:30:17 PM UTC 24 | Oct 02 06:30:53 PM UTC 24 | 1356380198 ps | ||
| T373 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/355.prim_prince_test.587483203 | Oct 02 06:29:35 PM UTC 24 | Oct 02 06:30:55 PM UTC 24 | 3260729888 ps | ||
| T374 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/407.prim_prince_test.2481228950 | Oct 02 06:30:29 PM UTC 24 | Oct 02 06:30:56 PM UTC 24 | 1042810989 ps | ||
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| T376 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/353.prim_prince_test.1021838285 | Oct 02 06:29:31 PM UTC 24 | Oct 02 06:30:59 PM UTC 24 | 3538875190 ps | ||
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| T378 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/411.prim_prince_test.1465882613 | Oct 02 06:30:36 PM UTC 24 | Oct 02 06:31:01 PM UTC 24 | 886814139 ps | ||
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| T380 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/414.prim_prince_test.236836207 | Oct 02 06:30:40 PM UTC 24 | Oct 02 06:31:03 PM UTC 24 | 788083572 ps | ||
| T381 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/413.prim_prince_test.2731394371 | Oct 02 06:30:37 PM UTC 24 | Oct 02 06:31:06 PM UTC 24 | 1045059713 ps | ||
| T382 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/354.prim_prince_test.4215794789 | Oct 02 06:29:32 PM UTC 24 | Oct 02 06:31:07 PM UTC 24 | 3744476845 ps | ||
| T383 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/376.prim_prince_test.2140184511 | Oct 02 06:29:53 PM UTC 24 | Oct 02 06:31:08 PM UTC 24 | 2987112164 ps | ||
| T384 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/422.prim_prince_test.2816776581 | Oct 02 06:30:47 PM UTC 24 | Oct 02 06:31:10 PM UTC 24 | 818244556 ps | ||
| T385 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/360.prim_prince_test.4249051320 | Oct 02 06:29:39 PM UTC 24 | Oct 02 06:31:10 PM UTC 24 | 3709783071 ps | ||
| T386 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/394.prim_prince_test.1616207743 | Oct 02 06:30:12 PM UTC 24 | Oct 02 06:31:11 PM UTC 24 | 2204967367 ps | ||
| T387 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/400.prim_prince_test.4119873314 | Oct 02 06:30:17 PM UTC 24 | Oct 02 06:31:11 PM UTC 24 | 2039732684 ps | ||
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| T391 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/404.prim_prince_test.1393821240 | Oct 02 06:30:25 PM UTC 24 | Oct 02 06:31:15 PM UTC 24 | 1944177999 ps | ||
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| T393 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/367.prim_prince_test.2540855438 | Oct 02 06:29:44 PM UTC 24 | Oct 02 06:31:16 PM UTC 24 | 3457117587 ps | ||
| T394 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/416.prim_prince_test.4160613213 | Oct 02 06:30:42 PM UTC 24 | Oct 02 06:31:17 PM UTC 24 | 1403391676 ps | ||
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| T437 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/449.prim_prince_test.4221998544 | Oct 02 06:31:18 PM UTC 24 | Oct 02 06:31:58 PM UTC 24 | 1504024588 ps | ||
| T438 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/446.prim_prince_test.2965166531 | Oct 02 06:31:15 PM UTC 24 | Oct 02 06:31:58 PM UTC 24 | 1628437295 ps | ||
| T439 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/415.prim_prince_test.801908669 | Oct 02 06:30:42 PM UTC 24 | Oct 02 06:31:59 PM UTC 24 | 3032909251 ps | ||
| T440 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/433.prim_prince_test.1974691305 | Oct 02 06:31:02 PM UTC 24 | Oct 02 06:32:02 PM UTC 24 | 2503341220 ps | ||
| T441 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/434.prim_prince_test.3180686296 | Oct 02 06:31:03 PM UTC 24 | Oct 02 06:32:03 PM UTC 24 | 2468769741 ps | ||
| T442 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/427.prim_prince_test.4026784989 | Oct 02 06:30:55 PM UTC 24 | Oct 02 06:32:04 PM UTC 24 | 2605547493 ps | ||
| T443 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/466.prim_prince_test.832960746 | Oct 02 06:31:28 PM UTC 24 | Oct 02 06:32:06 PM UTC 24 | 1570843837 ps | ||
| T444 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/436.prim_prince_test.3589946929 | Oct 02 06:31:07 PM UTC 24 | Oct 02 06:32:06 PM UTC 24 | 2314200903 ps | ||
| T445 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/462.prim_prince_test.504862087 | Oct 02 06:31:25 PM UTC 24 | Oct 02 06:32:07 PM UTC 24 | 1726138698 ps | ||
| T446 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/441.prim_prince_test.1597456657 | Oct 02 06:31:13 PM UTC 24 | Oct 02 06:32:07 PM UTC 24 | 2049072574 ps | ||
| T447 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/479.prim_prince_test.4192235868 | Oct 02 06:31:45 PM UTC 24 | Oct 02 06:32:08 PM UTC 24 | 822084675 ps | ||
| T448 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/412.prim_prince_test.2220114798 | Oct 02 06:30:36 PM UTC 24 | Oct 02 06:32:08 PM UTC 24 | 3595166098 ps | ||
| T449 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/425.prim_prince_test.1533183654 | Oct 02 06:30:51 PM UTC 24 | Oct 02 06:32:08 PM UTC 24 | 2943086178 ps | ||
| T450 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/428.prim_prince_test.3625052891 | Oct 02 06:30:56 PM UTC 24 | Oct 02 06:32:08 PM UTC 24 | 2968232477 ps | ||
| T451 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/467.prim_prince_test.3615916619 | Oct 02 06:31:28 PM UTC 24 | Oct 02 06:32:09 PM UTC 24 | 1559656467 ps | ||
| T452 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/451.prim_prince_test.3190919903 | Oct 02 06:31:19 PM UTC 24 | Oct 02 06:32:09 PM UTC 24 | 1891223223 ps | ||
| T453 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/482.prim_prince_test.349828714 | Oct 02 06:31:49 PM UTC 24 | Oct 02 06:32:09 PM UTC 24 | 818858929 ps | ||
| T454 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/426.prim_prince_test.1914377261 | Oct 02 06:30:52 PM UTC 24 | Oct 02 06:32:13 PM UTC 24 | 3372743716 ps | ||
| T455 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/471.prim_prince_test.1681652920 | Oct 02 06:31:34 PM UTC 24 | Oct 02 06:32:15 PM UTC 24 | 1649632667 ps | ||
| T456 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/448.prim_prince_test.3826654505 | Oct 02 06:31:16 PM UTC 24 | Oct 02 06:32:16 PM UTC 24 | 2353104295 ps | ||
| T457 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/470.prim_prince_test.342551504 | Oct 02 06:31:34 PM UTC 24 | Oct 02 06:32:16 PM UTC 24 | 1718242847 ps | ||
| T458 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/423.prim_prince_test.2741746119 | Oct 02 06:30:49 PM UTC 24 | Oct 02 06:32:16 PM UTC 24 | 3628562106 ps | ||
| T459 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/452.prim_prince_test.762415007 | Oct 02 06:31:19 PM UTC 24 | Oct 02 06:32:17 PM UTC 24 | 2223656200 ps | ||
| T460 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/490.prim_prince_test.988789045 | Oct 02 06:31:56 PM UTC 24 | Oct 02 06:32:17 PM UTC 24 | 843184375 ps | ||
| T461 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/447.prim_prince_test.3513803739 | Oct 02 06:31:16 PM UTC 24 | Oct 02 06:32:17 PM UTC 24 | 2412205072 ps | ||
| T462 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/450.prim_prince_test.4045396768 | Oct 02 06:31:18 PM UTC 24 | Oct 02 06:32:21 PM UTC 24 | 2495919500 ps | ||
| T463 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/459.prim_prince_test.1335072399 | Oct 02 06:31:23 PM UTC 24 | Oct 02 06:32:21 PM UTC 24 | 2253108848 ps | ||
| T464 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/457.prim_prince_test.3936407153 | Oct 02 06:31:21 PM UTC 24 | Oct 02 06:32:22 PM UTC 24 | 2522673849 ps | ||
| T465 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/456.prim_prince_test.1469756208 | Oct 02 06:31:21 PM UTC 24 | Oct 02 06:32:24 PM UTC 24 | 2619324357 ps | ||
| T466 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/461.prim_prince_test.3443764858 | Oct 02 06:31:25 PM UTC 24 | Oct 02 06:32:24 PM UTC 24 | 2347408459 ps | ||
| T467 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/481.prim_prince_test.3100528411 | Oct 02 06:31:45 PM UTC 24 | Oct 02 06:32:25 PM UTC 24 | 1666885076 ps | ||
| T468 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/478.prim_prince_test.236458006 | Oct 02 06:31:45 PM UTC 24 | Oct 02 06:32:26 PM UTC 24 | 1644200315 ps | ||
| T469 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/488.prim_prince_test.463387318 | Oct 02 06:31:56 PM UTC 24 | Oct 02 06:32:27 PM UTC 24 | 1190884915 ps | ||
| T470 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/480.prim_prince_test.1007492295 | Oct 02 06:31:45 PM UTC 24 | Oct 02 06:32:27 PM UTC 24 | 1701911094 ps | ||
| T471 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/497.prim_prince_test.1313507539 | Oct 02 06:32:01 PM UTC 24 | Oct 02 06:32:28 PM UTC 24 | 1161457188 ps | ||
| T472 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/454.prim_prince_test.3441525756 | Oct 02 06:31:21 PM UTC 24 | Oct 02 06:32:28 PM UTC 24 | 2608285002 ps | ||
| T473 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/442.prim_prince_test.187093940 | Oct 02 06:31:13 PM UTC 24 | Oct 02 06:32:30 PM UTC 24 | 3243255805 ps | ||
| T474 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/437.prim_prince_test.2197398852 | Oct 02 06:31:09 PM UTC 24 | Oct 02 06:32:31 PM UTC 24 | 3409380001 ps | ||
| T475 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/474.prim_prince_test.3458742504 | Oct 02 06:31:35 PM UTC 24 | Oct 02 06:32:32 PM UTC 24 | 2246090778 ps | ||
| T476 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/465.prim_prince_test.2069419295 | Oct 02 06:31:28 PM UTC 24 | Oct 02 06:32:32 PM UTC 24 | 2478595641 ps | ||
| T477 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/438.prim_prince_test.2972058894 | Oct 02 06:31:09 PM UTC 24 | Oct 02 06:32:32 PM UTC 24 | 3208407939 ps | ||
| T478 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/458.prim_prince_test.709903087 | Oct 02 06:31:23 PM UTC 24 | Oct 02 06:32:33 PM UTC 24 | 2814344893 ps | ||
| T479 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/477.prim_prince_test.3329842975 | Oct 02 06:31:38 PM UTC 24 | Oct 02 06:32:36 PM UTC 24 | 2276504970 ps | ||
| T480 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/487.prim_prince_test.3606825679 | Oct 02 06:31:55 PM UTC 24 | Oct 02 06:32:37 PM UTC 24 | 1757353160 ps | ||
| T481 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/499.prim_prince_test.668729471 | Oct 02 06:32:04 PM UTC 24 | Oct 02 06:32:37 PM UTC 24 | 1411454238 ps | ||
| T482 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/475.prim_prince_test.1115713582 | Oct 02 06:31:37 PM UTC 24 | Oct 02 06:32:37 PM UTC 24 | 2343755316 ps | ||
| T483 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/455.prim_prince_test.4238920758 | Oct 02 06:31:21 PM UTC 24 | Oct 02 06:32:38 PM UTC 24 | 3307571926 ps | ||
| T484 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/489.prim_prince_test.3096186374 | Oct 02 06:31:56 PM UTC 24 | Oct 02 06:32:40 PM UTC 24 | 1751120091 ps | ||
| T485 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/439.prim_prince_test.3358364123 | Oct 02 06:31:11 PM UTC 24 | Oct 02 06:32:40 PM UTC 24 | 3747574556 ps | ||
| T486 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/496.prim_prince_test.3858239319 | Oct 02 06:31:59 PM UTC 24 | Oct 02 06:32:41 PM UTC 24 | 1777700028 ps | ||
| T487 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/460.prim_prince_test.2718038607 | Oct 02 06:31:23 PM UTC 24 | Oct 02 06:32:41 PM UTC 24 | 3113164857 ps | ||
| T488 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/444.prim_prince_test.2061351288 | Oct 02 06:31:15 PM UTC 24 | Oct 02 06:32:43 PM UTC 24 | 3446310810 ps | ||
| T489 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/453.prim_prince_test.3317916876 | Oct 02 06:31:19 PM UTC 24 | Oct 02 06:32:43 PM UTC 24 | 3414850074 ps | ||
| T490 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/495.prim_prince_test.3441005815 | Oct 02 06:31:59 PM UTC 24 | Oct 02 06:32:45 PM UTC 24 | 2021341786 ps | ||
| T491 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/464.prim_prince_test.2455766755 | Oct 02 06:31:28 PM UTC 24 | Oct 02 06:32:47 PM UTC 24 | 3373500097 ps | ||
| T492 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/498.prim_prince_test.894398726 | Oct 02 06:32:04 PM UTC 24 | Oct 02 06:32:48 PM UTC 24 | 1978227885 ps | ||
| T493 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/494.prim_prince_test.1602292862 | Oct 02 06:31:59 PM UTC 24 | Oct 02 06:32:50 PM UTC 24 | 2106225446 ps | ||
| T494 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/491.prim_prince_test.2054038725 | Oct 02 06:31:58 PM UTC 24 | Oct 02 06:32:57 PM UTC 24 | 2449967334 ps | ||
| T495 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/493.prim_prince_test.367448277 | Oct 02 06:31:58 PM UTC 24 | Oct 02 06:33:10 PM UTC 24 | 2842472848 ps | ||
| T496 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/492.prim_prince_test.3296146625 | Oct 02 06:31:58 PM UTC 24 | Oct 02 06:33:13 PM UTC 24 | 3188351899 ps | ||
| T497 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/485.prim_prince_test.3412019723 | Oct 02 06:31:52 PM UTC 24 | Oct 02 06:33:14 PM UTC 24 | 3261662541 ps | ||
| T498 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/483.prim_prince_test.412714531 | Oct 02 06:31:49 PM UTC 24 | Oct 02 06:33:18 PM UTC 24 | 3510023807 ps | ||
| T499 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/486.prim_prince_test.1296867963 | Oct 02 06:31:53 PM UTC 24 | Oct 02 06:33:21 PM UTC 24 | 3369003402 ps | ||
| T500 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/484.prim_prince_test.3589355894 | Oct 02 06:31:51 PM UTC 24 | Oct 02 06:33:21 PM UTC 24 | 3549704133 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/10.prim_prince_test.4100679940 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 1231513925 ps |
| CPU time | 28 seconds |
| Started | Oct 02 06:21:42 PM UTC 24 |
| Finished | Oct 02 06:22:19 PM UTC 24 |
| Peak memory | 154972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4100679940 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 10.prim_prince_test.4100679940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/10.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/0.prim_prince_test.3723385479 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 2838629195 ps |
| CPU time | 59.88 seconds |
| Started | Oct 02 06:21:39 PM UTC 24 |
| Finished | Oct 02 06:22:59 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3723385479 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 0.prim_prince_test.3723385479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/0.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/1.prim_prince_test.2516690967 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 2639487993 ps |
| CPU time | 55.67 seconds |
| Started | Oct 02 06:21:39 PM UTC 24 |
| Finished | Oct 02 06:22:53 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2516690967 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 1.prim_prince_test.2516690967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/1.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/100.prim_prince_test.653715007 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 2220602188 ps |
| CPU time | 41.95 seconds |
| Started | Oct 02 06:24:22 PM UTC 24 |
| Finished | Oct 02 06:25:18 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=653715007 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 100.prim_prince_test.653715007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/100.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/101.prim_prince_test.813657489 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 1662867739 ps |
| CPU time | 30.67 seconds |
| Started | Oct 02 06:24:25 PM UTC 24 |
| Finished | Oct 02 06:25:05 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=813657489 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 101.prim_prince_test.813657489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/101.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/102.prim_prince_test.1081596666 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 2788723841 ps |
| CPU time | 58.82 seconds |
| Started | Oct 02 06:24:26 PM UTC 24 |
| Finished | Oct 02 06:25:40 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1081596666 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 102.prim_prince_test.1081596666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/102.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/103.prim_prince_test.438122441 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 2064816355 ps |
| CPU time | 43.4 seconds |
| Started | Oct 02 06:24:27 PM UTC 24 |
| Finished | Oct 02 06:25:22 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=438122441 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 103.prim_prince_test.438122441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/103.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/104.prim_prince_test.204443234 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 3101425022 ps |
| CPU time | 65.35 seconds |
| Started | Oct 02 06:24:27 PM UTC 24 |
| Finished | Oct 02 06:25:50 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=204443234 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 104.prim_prince_test.204443234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/104.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/105.prim_prince_test.3516662240 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 1227873225 ps |
| CPU time | 26.32 seconds |
| Started | Oct 02 06:24:29 PM UTC 24 |
| Finished | Oct 02 06:25:03 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3516662240 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 105.prim_prince_test.3516662240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/105.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/106.prim_prince_test.518087971 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 3182236423 ps |
| CPU time | 67.93 seconds |
| Started | Oct 02 06:24:31 PM UTC 24 |
| Finished | Oct 02 06:25:57 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=518087971 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 106.prim_prince_test.518087971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/106.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/107.prim_prince_test.606734694 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 2714215063 ps |
| CPU time | 51.43 seconds |
| Started | Oct 02 06:24:33 PM UTC 24 |
| Finished | Oct 02 06:25:40 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=606734694 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 107.prim_prince_test.606734694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/107.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/108.prim_prince_test.55723806 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 2348311808 ps |
| CPU time | 43.98 seconds |
| Started | Oct 02 06:24:36 PM UTC 24 |
| Finished | Oct 02 06:25:34 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=55723806 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 108.prim_prince_test.55723806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/108.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/109.prim_prince_test.1477389266 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 2712495663 ps |
| CPU time | 50.67 seconds |
| Started | Oct 02 06:24:37 PM UTC 24 |
| Finished | Oct 02 06:25:44 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1477389266 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 109.prim_prince_test.1477389266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/109.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/11.prim_prince_test.2260666926 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 1135234017 ps |
| CPU time | 25.73 seconds |
| Started | Oct 02 06:21:43 PM UTC 24 |
| Finished | Oct 02 06:22:18 PM UTC 24 |
| Peak memory | 154968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2260666926 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 11.prim_prince_test.2260666926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/11.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/110.prim_prince_test.1644210566 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 3612178325 ps |
| CPU time | 66.02 seconds |
| Started | Oct 02 06:24:37 PM UTC 24 |
| Finished | Oct 02 06:26:04 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1644210566 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 110.prim_prince_test.1644210566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/110.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/111.prim_prince_test.2182561078 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 3475693300 ps |
| CPU time | 63.63 seconds |
| Started | Oct 02 06:24:38 PM UTC 24 |
| Finished | Oct 02 06:26:02 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2182561078 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 111.prim_prince_test.2182561078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/111.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/112.prim_prince_test.3402269434 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 1112674398 ps |
| CPU time | 24.22 seconds |
| Started | Oct 02 06:24:39 PM UTC 24 |
| Finished | Oct 02 06:25:10 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3402269434 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 112.prim_prince_test.3402269434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/112.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/113.prim_prince_test.2242464933 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 3664618979 ps |
| CPU time | 68.75 seconds |
| Started | Oct 02 06:24:42 PM UTC 24 |
| Finished | Oct 02 06:26:11 PM UTC 24 |
| Peak memory | 155036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2242464933 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 113.prim_prince_test.2242464933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/113.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/114.prim_prince_test.716293815 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 3660495099 ps |
| CPU time | 76.89 seconds |
| Started | Oct 02 06:24:45 PM UTC 24 |
| Finished | Oct 02 06:26:22 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=716293815 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 114.prim_prince_test.716293815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/114.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/115.prim_prince_test.141372518 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 2259949189 ps |
| CPU time | 46.08 seconds |
| Started | Oct 02 06:24:46 PM UTC 24 |
| Finished | Oct 02 06:25:45 PM UTC 24 |
| Peak memory | 155036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=141372518 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 115.prim_prince_test.141372518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/115.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/116.prim_prince_test.3776478172 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 1914799618 ps |
| CPU time | 40.54 seconds |
| Started | Oct 02 06:24:51 PM UTC 24 |
| Finished | Oct 02 06:25:43 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3776478172 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 116.prim_prince_test.3776478172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/116.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/117.prim_prince_test.3820539621 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 3350460009 ps |
| CPU time | 62.06 seconds |
| Started | Oct 02 06:24:51 PM UTC 24 |
| Finished | Oct 02 06:26:12 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3820539621 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 117.prim_prince_test.3820539621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/117.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/118.prim_prince_test.116303505 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 849609405 ps |
| CPU time | 16.41 seconds |
| Started | Oct 02 06:24:53 PM UTC 24 |
| Finished | Oct 02 06:25:15 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=116303505 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 118.prim_prince_test.116303505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/118.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/119.prim_prince_test.1744215094 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 2438063784 ps |
| CPU time | 51.25 seconds |
| Started | Oct 02 06:24:53 PM UTC 24 |
| Finished | Oct 02 06:25:59 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1744215094 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 119.prim_prince_test.1744215094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/119.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/12.prim_prince_test.3987302696 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 832102726 ps |
| CPU time | 19.18 seconds |
| Started | Oct 02 06:21:43 PM UTC 24 |
| Finished | Oct 02 06:22:09 PM UTC 24 |
| Peak memory | 154972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3987302696 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 12.prim_prince_test.3987302696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/12.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/120.prim_prince_test.3677995984 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 3566098302 ps |
| CPU time | 66.82 seconds |
| Started | Oct 02 06:24:53 PM UTC 24 |
| Finished | Oct 02 06:26:20 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3677995984 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 120.prim_prince_test.3677995984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/120.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/121.prim_prince_test.863844862 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 1920763597 ps |
| CPU time | 37.45 seconds |
| Started | Oct 02 06:24:53 PM UTC 24 |
| Finished | Oct 02 06:25:42 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=863844862 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 121.prim_prince_test.863844862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/121.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/122.prim_prince_test.1048740394 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 2113116999 ps |
| CPU time | 39.74 seconds |
| Started | Oct 02 06:24:54 PM UTC 24 |
| Finished | Oct 02 06:25:47 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1048740394 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 122.prim_prince_test.1048740394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/122.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/123.prim_prince_test.2953467643 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 2615198613 ps |
| CPU time | 53.25 seconds |
| Started | Oct 02 06:24:56 PM UTC 24 |
| Finished | Oct 02 06:26:05 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2953467643 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 123.prim_prince_test.2953467643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/123.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/124.prim_prince_test.1945483034 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 3516861303 ps |
| CPU time | 69.03 seconds |
| Started | Oct 02 06:24:58 PM UTC 24 |
| Finished | Oct 02 06:26:26 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1945483034 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 124.prim_prince_test.1945483034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/124.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/125.prim_prince_test.2279175554 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 1622639867 ps |
| CPU time | 32.33 seconds |
| Started | Oct 02 06:25:01 PM UTC 24 |
| Finished | Oct 02 06:25:43 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2279175554 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 125.prim_prince_test.2279175554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/125.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/126.prim_prince_test.1514288832 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 2666765016 ps |
| CPU time | 54.12 seconds |
| Started | Oct 02 06:25:03 PM UTC 24 |
| Finished | Oct 02 06:26:12 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1514288832 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 126.prim_prince_test.1514288832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/126.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/127.prim_prince_test.1574928450 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 980834950 ps |
| CPU time | 19.11 seconds |
| Started | Oct 02 06:25:04 PM UTC 24 |
| Finished | Oct 02 06:25:30 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1574928450 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 127.prim_prince_test.1574928450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/127.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/128.prim_prince_test.1840769273 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 1815737725 ps |
| CPU time | 33.11 seconds |
| Started | Oct 02 06:25:05 PM UTC 24 |
| Finished | Oct 02 06:25:49 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1840769273 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 128.prim_prince_test.1840769273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/128.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/129.prim_prince_test.2778223464 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 871394217 ps |
| CPU time | 18.19 seconds |
| Started | Oct 02 06:25:06 PM UTC 24 |
| Finished | Oct 02 06:25:30 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2778223464 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 129.prim_prince_test.2778223464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/129.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/13.prim_prince_test.2598262114 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 1239065562 ps |
| CPU time | 27.86 seconds |
| Started | Oct 02 06:21:43 PM UTC 24 |
| Finished | Oct 02 06:22:21 PM UTC 24 |
| Peak memory | 154972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2598262114 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 13.prim_prince_test.2598262114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/13.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/130.prim_prince_test.3385161921 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 3259309600 ps |
| CPU time | 60.76 seconds |
| Started | Oct 02 06:25:06 PM UTC 24 |
| Finished | Oct 02 06:26:26 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3385161921 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 130.prim_prince_test.3385161921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/130.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/131.prim_prince_test.3261403767 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 894466310 ps |
| CPU time | 18.67 seconds |
| Started | Oct 02 06:25:09 PM UTC 24 |
| Finished | Oct 02 06:25:34 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3261403767 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 131.prim_prince_test.3261403767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/131.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/132.prim_prince_test.4003055958 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 3394979492 ps |
| CPU time | 64.44 seconds |
| Started | Oct 02 06:25:10 PM UTC 24 |
| Finished | Oct 02 06:26:34 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4003055958 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 132.prim_prince_test.4003055958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/132.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/133.prim_prince_test.2402391280 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 3382756669 ps |
| CPU time | 65.74 seconds |
| Started | Oct 02 06:25:11 PM UTC 24 |
| Finished | Oct 02 06:26:36 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2402391280 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 133.prim_prince_test.2402391280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/133.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/134.prim_prince_test.2666732150 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 824404040 ps |
| CPU time | 16.9 seconds |
| Started | Oct 02 06:25:11 PM UTC 24 |
| Finished | Oct 02 06:25:34 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2666732150 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 134.prim_prince_test.2666732150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/134.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/135.prim_prince_test.3115846552 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 982434645 ps |
| CPU time | 18.98 seconds |
| Started | Oct 02 06:25:12 PM UTC 24 |
| Finished | Oct 02 06:25:38 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3115846552 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 135.prim_prince_test.3115846552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/135.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/136.prim_prince_test.1318189023 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 2408072471 ps |
| CPU time | 46.37 seconds |
| Started | Oct 02 06:25:15 PM UTC 24 |
| Finished | Oct 02 06:26:15 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1318189023 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 136.prim_prince_test.1318189023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/136.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/137.prim_prince_test.3981444105 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 3656096411 ps |
| CPU time | 71.21 seconds |
| Started | Oct 02 06:25:16 PM UTC 24 |
| Finished | Oct 02 06:26:47 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3981444105 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 137.prim_prince_test.3981444105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/137.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/138.prim_prince_test.3494128744 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 1974679346 ps |
| CPU time | 37.49 seconds |
| Started | Oct 02 06:25:19 PM UTC 24 |
| Finished | Oct 02 06:26:08 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3494128744 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 138.prim_prince_test.3494128744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/138.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/139.prim_prince_test.2901220804 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 1173512642 ps |
| CPU time | 25.5 seconds |
| Started | Oct 02 06:25:23 PM UTC 24 |
| Finished | Oct 02 06:25:56 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2901220804 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 139.prim_prince_test.2901220804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/139.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/14.prim_prince_test.3218089488 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 2958469045 ps |
| CPU time | 62.3 seconds |
| Started | Oct 02 06:21:45 PM UTC 24 |
| Finished | Oct 02 06:23:07 PM UTC 24 |
| Peak memory | 155036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3218089488 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 14.prim_prince_test.3218089488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/14.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/140.prim_prince_test.1040461780 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 819726192 ps |
| CPU time | 17.2 seconds |
| Started | Oct 02 06:25:26 PM UTC 24 |
| Finished | Oct 02 06:25:49 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1040461780 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 140.prim_prince_test.1040461780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/140.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/141.prim_prince_test.3313454807 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 2628440719 ps |
| CPU time | 51.97 seconds |
| Started | Oct 02 06:25:30 PM UTC 24 |
| Finished | Oct 02 06:26:37 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3313454807 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 141.prim_prince_test.3313454807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/141.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/142.prim_prince_test.2164715690 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 1314631006 ps |
| CPU time | 28.03 seconds |
| Started | Oct 02 06:25:31 PM UTC 24 |
| Finished | Oct 02 06:26:07 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2164715690 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 142.prim_prince_test.2164715690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/142.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/143.prim_prince_test.3101239677 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 3348060122 ps |
| CPU time | 66.73 seconds |
| Started | Oct 02 06:25:31 PM UTC 24 |
| Finished | Oct 02 06:26:56 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3101239677 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 143.prim_prince_test.3101239677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/143.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/144.prim_prince_test.2578392371 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 3225018291 ps |
| CPU time | 66.09 seconds |
| Started | Oct 02 06:25:32 PM UTC 24 |
| Finished | Oct 02 06:26:56 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2578392371 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 144.prim_prince_test.2578392371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/144.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/145.prim_prince_test.1259836375 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 3183858079 ps |
| CPU time | 64.82 seconds |
| Started | Oct 02 06:25:33 PM UTC 24 |
| Finished | Oct 02 06:26:56 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1259836375 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 145.prim_prince_test.1259836375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/145.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/146.prim_prince_test.3509919807 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 1028023496 ps |
| CPU time | 19.65 seconds |
| Started | Oct 02 06:25:35 PM UTC 24 |
| Finished | Oct 02 06:26:01 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3509919807 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 146.prim_prince_test.3509919807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/146.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/147.prim_prince_test.3480643412 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 3697405401 ps |
| CPU time | 70.19 seconds |
| Started | Oct 02 06:25:35 PM UTC 24 |
| Finished | Oct 02 06:27:05 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3480643412 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 147.prim_prince_test.3480643412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/147.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/148.prim_prince_test.966245910 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 1889626087 ps |
| CPU time | 39.91 seconds |
| Started | Oct 02 06:25:35 PM UTC 24 |
| Finished | Oct 02 06:26:26 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=966245910 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 148.prim_prince_test.966245910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/148.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/149.prim_prince_test.3277059491 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 955135281 ps |
| CPU time | 21.16 seconds |
| Started | Oct 02 06:25:35 PM UTC 24 |
| Finished | Oct 02 06:26:02 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3277059491 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 149.prim_prince_test.3277059491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/149.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/15.prim_prince_test.2628416325 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 1876691123 ps |
| CPU time | 40.79 seconds |
| Started | Oct 02 06:21:50 PM UTC 24 |
| Finished | Oct 02 06:22:44 PM UTC 24 |
| Peak memory | 154972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2628416325 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 15.prim_prince_test.2628416325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/15.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/150.prim_prince_test.798281574 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 1471039817 ps |
| CPU time | 27.61 seconds |
| Started | Oct 02 06:25:39 PM UTC 24 |
| Finished | Oct 02 06:26:15 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=798281574 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 150.prim_prince_test.798281574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/150.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/151.prim_prince_test.556594126 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 1406197994 ps |
| CPU time | 29.92 seconds |
| Started | Oct 02 06:25:39 PM UTC 24 |
| Finished | Oct 02 06:26:17 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=556594126 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 151.prim_prince_test.556594126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/151.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/152.prim_prince_test.1156084358 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 810254928 ps |
| CPU time | 17.8 seconds |
| Started | Oct 02 06:25:41 PM UTC 24 |
| Finished | Oct 02 06:26:04 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1156084358 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 152.prim_prince_test.1156084358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/152.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/153.prim_prince_test.1746504897 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 1965031524 ps |
| CPU time | 36.57 seconds |
| Started | Oct 02 06:25:41 PM UTC 24 |
| Finished | Oct 02 06:26:29 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1746504897 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 153.prim_prince_test.1746504897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/153.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/154.prim_prince_test.3161910510 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 3192233373 ps |
| CPU time | 64.71 seconds |
| Started | Oct 02 06:25:41 PM UTC 24 |
| Finished | Oct 02 06:27:03 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3161910510 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 154.prim_prince_test.3161910510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/154.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/155.prim_prince_test.1447509221 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 3416970272 ps |
| CPU time | 62.3 seconds |
| Started | Oct 02 06:25:43 PM UTC 24 |
| Finished | Oct 02 06:27:04 PM UTC 24 |
| Peak memory | 154600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1447509221 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 155.prim_prince_test.1447509221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/155.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/156.prim_prince_test.164480108 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 1703047442 ps |
| CPU time | 31.37 seconds |
| Started | Oct 02 06:25:43 PM UTC 24 |
| Finished | Oct 02 06:26:25 PM UTC 24 |
| Peak memory | 154580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=164480108 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 156.prim_prince_test.164480108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/156.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/157.prim_prince_test.2053868382 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 2009451703 ps |
| CPU time | 41.45 seconds |
| Started | Oct 02 06:25:43 PM UTC 24 |
| Finished | Oct 02 06:26:36 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2053868382 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 157.prim_prince_test.2053868382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/157.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/158.prim_prince_test.2032789836 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 2644419972 ps |
| CPU time | 49.01 seconds |
| Started | Oct 02 06:25:44 PM UTC 24 |
| Finished | Oct 02 06:26:48 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2032789836 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 158.prim_prince_test.2032789836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/158.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/159.prim_prince_test.3608377682 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 2240108172 ps |
| CPU time | 40.96 seconds |
| Started | Oct 02 06:25:45 PM UTC 24 |
| Finished | Oct 02 06:26:38 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3608377682 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 159.prim_prince_test.3608377682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/159.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/16.prim_prince_test.3133795633 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 1031055727 ps |
| CPU time | 22.9 seconds |
| Started | Oct 02 06:21:59 PM UTC 24 |
| Finished | Oct 02 06:22:30 PM UTC 24 |
| Peak memory | 154972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3133795633 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 16.prim_prince_test.3133795633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/16.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/160.prim_prince_test.146260064 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 2100189882 ps |
| CPU time | 42.23 seconds |
| Started | Oct 02 06:25:46 PM UTC 24 |
| Finished | Oct 02 06:26:40 PM UTC 24 |
| Peak memory | 154972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=146260064 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 160.prim_prince_test.146260064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/160.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/161.prim_prince_test.4143174368 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 1276504453 ps |
| CPU time | 25.67 seconds |
| Started | Oct 02 06:25:48 PM UTC 24 |
| Finished | Oct 02 06:26:21 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4143174368 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 161.prim_prince_test.4143174368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/161.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/162.prim_prince_test.2001273586 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 1245958782 ps |
| CPU time | 23.56 seconds |
| Started | Oct 02 06:25:49 PM UTC 24 |
| Finished | Oct 02 06:26:20 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2001273586 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 162.prim_prince_test.2001273586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/162.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/163.prim_prince_test.558986120 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 3180979520 ps |
| CPU time | 58.82 seconds |
| Started | Oct 02 06:25:50 PM UTC 24 |
| Finished | Oct 02 06:27:06 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=558986120 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 163.prim_prince_test.558986120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/163.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/164.prim_prince_test.3235803972 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 2653256827 ps |
| CPU time | 49.53 seconds |
| Started | Oct 02 06:25:50 PM UTC 24 |
| Finished | Oct 02 06:26:54 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3235803972 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 164.prim_prince_test.3235803972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/164.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/165.prim_prince_test.523777207 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 2541783979 ps |
| CPU time | 50.19 seconds |
| Started | Oct 02 06:25:51 PM UTC 24 |
| Finished | Oct 02 06:26:55 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=523777207 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 165.prim_prince_test.523777207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/165.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/166.prim_prince_test.2608354747 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 1520954541 ps |
| CPU time | 28.31 seconds |
| Started | Oct 02 06:25:56 PM UTC 24 |
| Finished | Oct 02 06:26:33 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2608354747 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 166.prim_prince_test.2608354747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/166.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/167.prim_prince_test.1212362341 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 3213715955 ps |
| CPU time | 62.68 seconds |
| Started | Oct 02 06:25:57 PM UTC 24 |
| Finished | Oct 02 06:27:17 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1212362341 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 167.prim_prince_test.1212362341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/167.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/168.prim_prince_test.15999193 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 2926961125 ps |
| CPU time | 57.69 seconds |
| Started | Oct 02 06:25:58 PM UTC 24 |
| Finished | Oct 02 06:27:12 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15999193 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 168.prim_prince_test.15999193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/168.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/169.prim_prince_test.927834569 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 1132463006 ps |
| CPU time | 21.75 seconds |
| Started | Oct 02 06:25:59 PM UTC 24 |
| Finished | Oct 02 06:26:28 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=927834569 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 169.prim_prince_test.927834569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/169.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/17.prim_prince_test.3790663272 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 880333793 ps |
| CPU time | 19.22 seconds |
| Started | Oct 02 06:22:08 PM UTC 24 |
| Finished | Oct 02 06:22:35 PM UTC 24 |
| Peak memory | 154972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3790663272 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 17.prim_prince_test.3790663272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/17.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/170.prim_prince_test.798307015 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 2218972480 ps |
| CPU time | 40.52 seconds |
| Started | Oct 02 06:26:01 PM UTC 24 |
| Finished | Oct 02 06:26:54 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=798307015 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 170.prim_prince_test.798307015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/170.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/171.prim_prince_test.2259014445 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 1921098294 ps |
| CPU time | 37.91 seconds |
| Started | Oct 02 06:26:03 PM UTC 24 |
| Finished | Oct 02 06:26:51 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2259014445 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 171.prim_prince_test.2259014445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/171.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/172.prim_prince_test.1172926884 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 2780273271 ps |
| CPU time | 55.44 seconds |
| Started | Oct 02 06:26:03 PM UTC 24 |
| Finished | Oct 02 06:27:13 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1172926884 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 172.prim_prince_test.1172926884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/172.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/173.prim_prince_test.1911886583 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 1975107006 ps |
| CPU time | 36.13 seconds |
| Started | Oct 02 06:26:03 PM UTC 24 |
| Finished | Oct 02 06:26:50 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1911886583 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 173.prim_prince_test.1911886583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/173.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/174.prim_prince_test.3335946813 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 2673526154 ps |
| CPU time | 52.95 seconds |
| Started | Oct 02 06:26:05 PM UTC 24 |
| Finished | Oct 02 06:27:12 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3335946813 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 174.prim_prince_test.3335946813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/174.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/175.prim_prince_test.3754685446 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 3410630545 ps |
| CPU time | 62.86 seconds |
| Started | Oct 02 06:26:05 PM UTC 24 |
| Finished | Oct 02 06:27:26 PM UTC 24 |
| Peak memory | 154992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3754685446 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 175.prim_prince_test.3754685446 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/175.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/176.prim_prince_test.2780994263 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 3752914278 ps |
| CPU time | 68.5 seconds |
| Started | Oct 02 06:26:05 PM UTC 24 |
| Finished | Oct 02 06:27:33 PM UTC 24 |
| Peak memory | 155000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2780994263 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 176.prim_prince_test.2780994263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/176.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/177.prim_prince_test.4278132852 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 2927819910 ps |
| CPU time | 56.12 seconds |
| Started | Oct 02 06:26:08 PM UTC 24 |
| Finished | Oct 02 06:27:20 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4278132852 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 177.prim_prince_test.4278132852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/177.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/178.prim_prince_test.2617532862 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 3574035392 ps |
| CPU time | 65.63 seconds |
| Started | Oct 02 06:26:09 PM UTC 24 |
| Finished | Oct 02 06:27:34 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2617532862 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 178.prim_prince_test.2617532862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/178.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/179.prim_prince_test.809064248 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 3407923865 ps |
| CPU time | 67.58 seconds |
| Started | Oct 02 06:26:12 PM UTC 24 |
| Finished | Oct 02 06:27:38 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=809064248 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 179.prim_prince_test.809064248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/179.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/18.prim_prince_test.1368535509 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 1282924708 ps |
| CPU time | 27.55 seconds |
| Started | Oct 02 06:22:10 PM UTC 24 |
| Finished | Oct 02 06:22:46 PM UTC 24 |
| Peak memory | 154972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1368535509 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 18.prim_prince_test.1368535509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/18.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/180.prim_prince_test.1296246278 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 2845851527 ps |
| CPU time | 54.28 seconds |
| Started | Oct 02 06:26:12 PM UTC 24 |
| Finished | Oct 02 06:27:22 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1296246278 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 180.prim_prince_test.1296246278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/180.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/181.prim_prince_test.612229441 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 1242518481 ps |
| CPU time | 23.54 seconds |
| Started | Oct 02 06:26:14 PM UTC 24 |
| Finished | Oct 02 06:26:44 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=612229441 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 181.prim_prince_test.612229441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/181.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/182.prim_prince_test.4227914119 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 2598195954 ps |
| CPU time | 51.61 seconds |
| Started | Oct 02 06:26:16 PM UTC 24 |
| Finished | Oct 02 06:27:21 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4227914119 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 182.prim_prince_test.4227914119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/182.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/183.prim_prince_test.1307927495 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 2516471238 ps |
| CPU time | 46.62 seconds |
| Started | Oct 02 06:26:16 PM UTC 24 |
| Finished | Oct 02 06:27:16 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1307927495 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 183.prim_prince_test.1307927495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/183.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/184.prim_prince_test.3359757259 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 2607516562 ps |
| CPU time | 51.82 seconds |
| Started | Oct 02 06:26:18 PM UTC 24 |
| Finished | Oct 02 06:27:24 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3359757259 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 184.prim_prince_test.3359757259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/184.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/185.prim_prince_test.1308952544 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 2340615983 ps |
| CPU time | 45.92 seconds |
| Started | Oct 02 06:26:21 PM UTC 24 |
| Finished | Oct 02 06:27:19 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1308952544 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 185.prim_prince_test.1308952544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/185.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/186.prim_prince_test.2636331036 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 3573804006 ps |
| CPU time | 64.97 seconds |
| Started | Oct 02 06:26:21 PM UTC 24 |
| Finished | Oct 02 06:27:45 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2636331036 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 186.prim_prince_test.2636331036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/186.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/187.prim_prince_test.1595085833 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 2766646332 ps |
| CPU time | 50.35 seconds |
| Started | Oct 02 06:26:22 PM UTC 24 |
| Finished | Oct 02 06:27:27 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1595085833 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 187.prim_prince_test.1595085833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/187.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/188.prim_prince_test.1542424616 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 2006844753 ps |
| CPU time | 37.74 seconds |
| Started | Oct 02 06:26:23 PM UTC 24 |
| Finished | Oct 02 06:27:12 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1542424616 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 188.prim_prince_test.1542424616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/188.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/189.prim_prince_test.418766879 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 1327204387 ps |
| CPU time | 26 seconds |
| Started | Oct 02 06:26:25 PM UTC 24 |
| Finished | Oct 02 06:26:59 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=418766879 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 189.prim_prince_test.418766879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/189.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/19.prim_prince_test.1486499504 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 2959636856 ps |
| CPU time | 58.73 seconds |
| Started | Oct 02 06:22:12 PM UTC 24 |
| Finished | Oct 02 06:23:29 PM UTC 24 |
| Peak memory | 155036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1486499504 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 19.prim_prince_test.1486499504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/19.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/190.prim_prince_test.234338043 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 2981828790 ps |
| CPU time | 54.17 seconds |
| Started | Oct 02 06:26:26 PM UTC 24 |
| Finished | Oct 02 06:27:36 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=234338043 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 190.prim_prince_test.234338043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/190.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/191.prim_prince_test.1748731301 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 3660827949 ps |
| CPU time | 69.83 seconds |
| Started | Oct 02 06:26:27 PM UTC 24 |
| Finished | Oct 02 06:27:56 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1748731301 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 191.prim_prince_test.1748731301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/191.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/192.prim_prince_test.1381863207 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 2443392923 ps |
| CPU time | 44.85 seconds |
| Started | Oct 02 06:26:28 PM UTC 24 |
| Finished | Oct 02 06:27:26 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1381863207 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 192.prim_prince_test.1381863207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/192.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/193.prim_prince_test.1874002687 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 1592823147 ps |
| CPU time | 30.6 seconds |
| Started | Oct 02 06:26:29 PM UTC 24 |
| Finished | Oct 02 06:27:08 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1874002687 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 193.prim_prince_test.1874002687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/193.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/194.prim_prince_test.2907634989 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 2330733918 ps |
| CPU time | 43.99 seconds |
| Started | Oct 02 06:26:30 PM UTC 24 |
| Finished | Oct 02 06:27:27 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2907634989 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 194.prim_prince_test.2907634989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/194.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/195.prim_prince_test.1280029900 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 1290264895 ps |
| CPU time | 25.4 seconds |
| Started | Oct 02 06:26:31 PM UTC 24 |
| Finished | Oct 02 06:27:05 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1280029900 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 195.prim_prince_test.1280029900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/195.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/196.prim_prince_test.226647698 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 1396794781 ps |
| CPU time | 27.99 seconds |
| Started | Oct 02 06:26:34 PM UTC 24 |
| Finished | Oct 02 06:27:10 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=226647698 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 196.prim_prince_test.226647698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/196.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/197.prim_prince_test.3749779598 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 2375971385 ps |
| CPU time | 45.07 seconds |
| Started | Oct 02 06:26:35 PM UTC 24 |
| Finished | Oct 02 06:27:33 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3749779598 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 197.prim_prince_test.3749779598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/197.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/198.prim_prince_test.4164297491 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 765711189 ps |
| CPU time | 15.24 seconds |
| Started | Oct 02 06:26:37 PM UTC 24 |
| Finished | Oct 02 06:26:57 PM UTC 24 |
| Peak memory | 154596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4164297491 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 198.prim_prince_test.4164297491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/198.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/199.prim_prince_test.2266357637 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 1668240736 ps |
| CPU time | 32.95 seconds |
| Started | Oct 02 06:26:37 PM UTC 24 |
| Finished | Oct 02 06:27:20 PM UTC 24 |
| Peak memory | 154704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2266357637 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 199.prim_prince_test.2266357637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/199.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/2.prim_prince_test.3227279732 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 3522075232 ps |
| CPU time | 74.7 seconds |
| Started | Oct 02 06:21:40 PM UTC 24 |
| Finished | Oct 02 06:23:18 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3227279732 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 2.prim_prince_test.3227279732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/2.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/20.prim_prince_test.532781879 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 2444248802 ps |
| CPU time | 49.36 seconds |
| Started | Oct 02 06:22:13 PM UTC 24 |
| Finished | Oct 02 06:23:18 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=532781879 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 20.prim_prince_test.532781879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/20.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/200.prim_prince_test.2105295582 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 2976940600 ps |
| CPU time | 56 seconds |
| Started | Oct 02 06:26:39 PM UTC 24 |
| Finished | Oct 02 06:27:50 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2105295582 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 200.prim_prince_test.2105295582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/200.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/201.prim_prince_test.316683173 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 3679511959 ps |
| CPU time | 69.13 seconds |
| Started | Oct 02 06:26:39 PM UTC 24 |
| Finished | Oct 02 06:28:07 PM UTC 24 |
| Peak memory | 155036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=316683173 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 201.prim_prince_test.316683173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/201.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/202.prim_prince_test.2169721077 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 3324561923 ps |
| CPU time | 63.52 seconds |
| Started | Oct 02 06:26:41 PM UTC 24 |
| Finished | Oct 02 06:28:02 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2169721077 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 202.prim_prince_test.2169721077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/202.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/203.prim_prince_test.735163340 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 1169657792 ps |
| CPU time | 22.8 seconds |
| Started | Oct 02 06:26:41 PM UTC 24 |
| Finished | Oct 02 06:27:10 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=735163340 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 203.prim_prince_test.735163340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/203.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/204.prim_prince_test.456385859 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 2550460629 ps |
| CPU time | 47.06 seconds |
| Started | Oct 02 06:26:45 PM UTC 24 |
| Finished | Oct 02 06:27:46 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=456385859 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 204.prim_prince_test.456385859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/204.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/205.prim_prince_test.521257336 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 2502777789 ps |
| CPU time | 45.9 seconds |
| Started | Oct 02 06:26:48 PM UTC 24 |
| Finished | Oct 02 06:27:47 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=521257336 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 205.prim_prince_test.521257336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/205.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/206.prim_prince_test.2110570845 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 1030111256 ps |
| CPU time | 19.62 seconds |
| Started | Oct 02 06:26:49 PM UTC 24 |
| Finished | Oct 02 06:27:15 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2110570845 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 206.prim_prince_test.2110570845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/206.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/207.prim_prince_test.3398489792 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 1277675034 ps |
| CPU time | 25.18 seconds |
| Started | Oct 02 06:26:51 PM UTC 24 |
| Finished | Oct 02 06:27:24 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3398489792 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 207.prim_prince_test.3398489792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/207.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/208.prim_prince_test.1283667761 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 3137589795 ps |
| CPU time | 61.89 seconds |
| Started | Oct 02 06:26:52 PM UTC 24 |
| Finished | Oct 02 06:28:11 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1283667761 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 208.prim_prince_test.1283667761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/208.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/209.prim_prince_test.2269181628 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 1903253677 ps |
| CPU time | 35.13 seconds |
| Started | Oct 02 06:26:56 PM UTC 24 |
| Finished | Oct 02 06:27:41 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2269181628 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 209.prim_prince_test.2269181628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/209.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/21.prim_prince_test.978407510 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 2832193316 ps |
| CPU time | 57.46 seconds |
| Started | Oct 02 06:22:17 PM UTC 24 |
| Finished | Oct 02 06:23:32 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=978407510 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 21.prim_prince_test.978407510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/21.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/210.prim_prince_test.4063301764 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 2491342942 ps |
| CPU time | 49.29 seconds |
| Started | Oct 02 06:26:56 PM UTC 24 |
| Finished | Oct 02 06:27:58 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4063301764 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 210.prim_prince_test.4063301764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/210.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/211.prim_prince_test.3314107648 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 842710508 ps |
| CPU time | 16.88 seconds |
| Started | Oct 02 06:26:56 PM UTC 24 |
| Finished | Oct 02 06:27:18 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3314107648 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 211.prim_prince_test.3314107648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/211.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/212.prim_prince_test.1110668571 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 2525900847 ps |
| CPU time | 50.02 seconds |
| Started | Oct 02 06:26:57 PM UTC 24 |
| Finished | Oct 02 06:28:00 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1110668571 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 212.prim_prince_test.1110668571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/212.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/213.prim_prince_test.1246131489 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 1575614700 ps |
| CPU time | 29.21 seconds |
| Started | Oct 02 06:26:57 PM UTC 24 |
| Finished | Oct 02 06:27:35 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1246131489 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 213.prim_prince_test.1246131489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/213.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/214.prim_prince_test.3418222426 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 3652442135 ps |
| CPU time | 66.79 seconds |
| Started | Oct 02 06:26:57 PM UTC 24 |
| Finished | Oct 02 06:28:23 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3418222426 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 214.prim_prince_test.3418222426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/214.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/215.prim_prince_test.1440334168 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 1384167726 ps |
| CPU time | 26.86 seconds |
| Started | Oct 02 06:26:57 PM UTC 24 |
| Finished | Oct 02 06:27:32 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1440334168 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 215.prim_prince_test.1440334168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/215.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/216.prim_prince_test.421468450 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 2486124060 ps |
| CPU time | 49.16 seconds |
| Started | Oct 02 06:26:58 PM UTC 24 |
| Finished | Oct 02 06:28:01 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=421468450 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 216.prim_prince_test.421468450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/216.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/217.prim_prince_test.2357032441 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 2786390559 ps |
| CPU time | 52.78 seconds |
| Started | Oct 02 06:27:00 PM UTC 24 |
| Finished | Oct 02 06:28:08 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2357032441 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 217.prim_prince_test.2357032441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/217.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/218.prim_prince_test.4245628883 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 3218808791 ps |
| CPU time | 59 seconds |
| Started | Oct 02 06:27:04 PM UTC 24 |
| Finished | Oct 02 06:28:21 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4245628883 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 218.prim_prince_test.4245628883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/218.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/219.prim_prince_test.3210316439 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 1410081106 ps |
| CPU time | 26.17 seconds |
| Started | Oct 02 06:27:06 PM UTC 24 |
| Finished | Oct 02 06:27:40 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3210316439 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 219.prim_prince_test.3210316439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/219.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/22.prim_prince_test.2749829957 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 1545531927 ps |
| CPU time | 32.95 seconds |
| Started | Oct 02 06:22:18 PM UTC 24 |
| Finished | Oct 02 06:23:01 PM UTC 24 |
| Peak memory | 154972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2749829957 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 22.prim_prince_test.2749829957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/22.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/220.prim_prince_test.2811422047 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 2608404902 ps |
| CPU time | 51.96 seconds |
| Started | Oct 02 06:27:06 PM UTC 24 |
| Finished | Oct 02 06:28:11 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2811422047 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 220.prim_prince_test.2811422047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/220.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/221.prim_prince_test.320696376 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 2493822393 ps |
| CPU time | 46.48 seconds |
| Started | Oct 02 06:27:06 PM UTC 24 |
| Finished | Oct 02 06:28:06 PM UTC 24 |
| Peak memory | 155036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=320696376 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 221.prim_prince_test.320696376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/221.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/222.prim_prince_test.334926917 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 2121971046 ps |
| CPU time | 41.34 seconds |
| Started | Oct 02 06:27:07 PM UTC 24 |
| Finished | Oct 02 06:28:00 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=334926917 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 222.prim_prince_test.334926917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/222.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/223.prim_prince_test.4070714863 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 2994156273 ps |
| CPU time | 58.33 seconds |
| Started | Oct 02 06:27:09 PM UTC 24 |
| Finished | Oct 02 06:28:23 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4070714863 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 223.prim_prince_test.4070714863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/223.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/224.prim_prince_test.2654802327 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 2485073417 ps |
| CPU time | 46.03 seconds |
| Started | Oct 02 06:27:09 PM UTC 24 |
| Finished | Oct 02 06:28:08 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2654802327 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 224.prim_prince_test.2654802327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/224.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/225.prim_prince_test.3842829792 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 2527005569 ps |
| CPU time | 49.76 seconds |
| Started | Oct 02 06:27:11 PM UTC 24 |
| Finished | Oct 02 06:28:14 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3842829792 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 225.prim_prince_test.3842829792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/225.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/226.prim_prince_test.724486000 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 1797076550 ps |
| CPU time | 33.1 seconds |
| Started | Oct 02 06:27:11 PM UTC 24 |
| Finished | Oct 02 06:27:54 PM UTC 24 |
| Peak memory | 154972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=724486000 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 226.prim_prince_test.724486000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/226.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/227.prim_prince_test.2769986065 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 2723058893 ps |
| CPU time | 49.64 seconds |
| Started | Oct 02 06:27:12 PM UTC 24 |
| Finished | Oct 02 06:28:17 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2769986065 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 227.prim_prince_test.2769986065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/227.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/228.prim_prince_test.1253518630 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 2134809744 ps |
| CPU time | 41.05 seconds |
| Started | Oct 02 06:27:12 PM UTC 24 |
| Finished | Oct 02 06:28:05 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1253518630 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 228.prim_prince_test.1253518630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/228.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/229.prim_prince_test.1420383460 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 1502256039 ps |
| CPU time | 27.88 seconds |
| Started | Oct 02 06:27:14 PM UTC 24 |
| Finished | Oct 02 06:27:50 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1420383460 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 229.prim_prince_test.1420383460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/229.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/23.prim_prince_test.1379345353 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 3604532033 ps |
| CPU time | 69.94 seconds |
| Started | Oct 02 06:22:19 PM UTC 24 |
| Finished | Oct 02 06:23:51 PM UTC 24 |
| Peak memory | 155036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1379345353 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 23.prim_prince_test.1379345353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/23.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/230.prim_prince_test.3377151346 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 1285837155 ps |
| CPU time | 25.83 seconds |
| Started | Oct 02 06:27:15 PM UTC 24 |
| Finished | Oct 02 06:27:48 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3377151346 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 230.prim_prince_test.3377151346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/230.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/231.prim_prince_test.594459710 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 3013600194 ps |
| CPU time | 54.91 seconds |
| Started | Oct 02 06:27:16 PM UTC 24 |
| Finished | Oct 02 06:28:27 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=594459710 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 231.prim_prince_test.594459710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/231.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/232.prim_prince_test.1759809645 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 2398178933 ps |
| CPU time | 47.37 seconds |
| Started | Oct 02 06:27:17 PM UTC 24 |
| Finished | Oct 02 06:28:17 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1759809645 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 232.prim_prince_test.1759809645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/232.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/233.prim_prince_test.2041951795 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 2048416178 ps |
| CPU time | 37.75 seconds |
| Started | Oct 02 06:27:18 PM UTC 24 |
| Finished | Oct 02 06:28:07 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2041951795 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 233.prim_prince_test.2041951795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/233.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/234.prim_prince_test.3671467532 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 2453393431 ps |
| CPU time | 45.29 seconds |
| Started | Oct 02 06:27:19 PM UTC 24 |
| Finished | Oct 02 06:28:18 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3671467532 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 234.prim_prince_test.3671467532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/234.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/235.prim_prince_test.4125268227 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 3247289694 ps |
| CPU time | 59.24 seconds |
| Started | Oct 02 06:27:20 PM UTC 24 |
| Finished | Oct 02 06:28:37 PM UTC 24 |
| Peak memory | 154900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4125268227 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 235.prim_prince_test.4125268227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/235.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/236.prim_prince_test.1044394862 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 3337662224 ps |
| CPU time | 65.25 seconds |
| Started | Oct 02 06:27:20 PM UTC 24 |
| Finished | Oct 02 06:28:43 PM UTC 24 |
| Peak memory | 154844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1044394862 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 236.prim_prince_test.1044394862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/236.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/237.prim_prince_test.1125977907 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 925693657 ps |
| CPU time | 18.57 seconds |
| Started | Oct 02 06:27:21 PM UTC 24 |
| Finished | Oct 02 06:27:45 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1125977907 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 237.prim_prince_test.1125977907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/237.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/238.prim_prince_test.3820717912 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 1428524702 ps |
| CPU time | 26.91 seconds |
| Started | Oct 02 06:27:23 PM UTC 24 |
| Finished | Oct 02 06:27:57 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3820717912 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 238.prim_prince_test.3820717912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/238.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/239.prim_prince_test.2893593837 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 893747694 ps |
| CPU time | 17.97 seconds |
| Started | Oct 02 06:27:23 PM UTC 24 |
| Finished | Oct 02 06:27:46 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2893593837 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 239.prim_prince_test.2893593837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/239.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/24.prim_prince_test.1829365866 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 3055482472 ps |
| CPU time | 65.56 seconds |
| Started | Oct 02 06:22:19 PM UTC 24 |
| Finished | Oct 02 06:23:44 PM UTC 24 |
| Peak memory | 155036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1829365866 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 24.prim_prince_test.1829365866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/24.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/240.prim_prince_test.2160843528 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 2167567805 ps |
| CPU time | 39.73 seconds |
| Started | Oct 02 06:27:25 PM UTC 24 |
| Finished | Oct 02 06:28:16 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2160843528 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 240.prim_prince_test.2160843528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/240.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/241.prim_prince_test.1578076737 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 1511326172 ps |
| CPU time | 28.93 seconds |
| Started | Oct 02 06:27:25 PM UTC 24 |
| Finished | Oct 02 06:28:02 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1578076737 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 241.prim_prince_test.1578076737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/241.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/242.prim_prince_test.3462828479 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 2628260866 ps |
| CPU time | 48.34 seconds |
| Started | Oct 02 06:27:27 PM UTC 24 |
| Finished | Oct 02 06:28:29 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3462828479 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 242.prim_prince_test.3462828479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/242.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/243.prim_prince_test.3876691517 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 1599860531 ps |
| CPU time | 31.99 seconds |
| Started | Oct 02 06:27:27 PM UTC 24 |
| Finished | Oct 02 06:28:08 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3876691517 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 243.prim_prince_test.3876691517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/243.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/244.prim_prince_test.2847796446 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 2345942615 ps |
| CPU time | 46.96 seconds |
| Started | Oct 02 06:27:27 PM UTC 24 |
| Finished | Oct 02 06:28:27 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2847796446 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 244.prim_prince_test.2847796446 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/244.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/245.prim_prince_test.2217207268 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 3048558824 ps |
| CPU time | 60.51 seconds |
| Started | Oct 02 06:27:28 PM UTC 24 |
| Finished | Oct 02 06:28:45 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2217207268 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 245.prim_prince_test.2217207268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/245.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/246.prim_prince_test.2251887838 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 1752695384 ps |
| CPU time | 34.66 seconds |
| Started | Oct 02 06:27:32 PM UTC 24 |
| Finished | Oct 02 06:28:17 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2251887838 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 246.prim_prince_test.2251887838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/246.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/247.prim_prince_test.41344659 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 3203790352 ps |
| CPU time | 60.74 seconds |
| Started | Oct 02 06:27:35 PM UTC 24 |
| Finished | Oct 02 06:28:52 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41344659 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 247.prim_prince_test.41344659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/247.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/248.prim_prince_test.4268410411 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 1153651696 ps |
| CPU time | 22.99 seconds |
| Started | Oct 02 06:27:35 PM UTC 24 |
| Finished | Oct 02 06:28:04 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4268410411 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 248.prim_prince_test.4268410411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/248.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/249.prim_prince_test.2002484457 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 1272324517 ps |
| CPU time | 23.71 seconds |
| Started | Oct 02 06:27:35 PM UTC 24 |
| Finished | Oct 02 06:28:06 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2002484457 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 249.prim_prince_test.2002484457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/249.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/25.prim_prince_test.1812134686 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 3134178101 ps |
| CPU time | 61.85 seconds |
| Started | Oct 02 06:22:19 PM UTC 24 |
| Finished | Oct 02 06:23:41 PM UTC 24 |
| Peak memory | 155036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1812134686 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 25.prim_prince_test.1812134686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/25.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/250.prim_prince_test.2764236797 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 3582344986 ps |
| CPU time | 66.39 seconds |
| Started | Oct 02 06:27:36 PM UTC 24 |
| Finished | Oct 02 06:29:01 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2764236797 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 250.prim_prince_test.2764236797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/250.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/251.prim_prince_test.732406519 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 3701650569 ps |
| CPU time | 70.07 seconds |
| Started | Oct 02 06:27:37 PM UTC 24 |
| Finished | Oct 02 06:29:06 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=732406519 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 251.prim_prince_test.732406519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/251.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/252.prim_prince_test.2583467168 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 1104000574 ps |
| CPU time | 20.62 seconds |
| Started | Oct 02 06:27:39 PM UTC 24 |
| Finished | Oct 02 06:28:06 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2583467168 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 252.prim_prince_test.2583467168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/252.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/253.prim_prince_test.1262120207 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 2155522479 ps |
| CPU time | 41.15 seconds |
| Started | Oct 02 06:27:41 PM UTC 24 |
| Finished | Oct 02 06:28:34 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1262120207 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 253.prim_prince_test.1262120207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/253.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/254.prim_prince_test.1724574546 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 3602483912 ps |
| CPU time | 69.52 seconds |
| Started | Oct 02 06:27:42 PM UTC 24 |
| Finished | Oct 02 06:29:11 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1724574546 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 254.prim_prince_test.1724574546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/254.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/255.prim_prince_test.985894586 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 1506688478 ps |
| CPU time | 27.86 seconds |
| Started | Oct 02 06:27:45 PM UTC 24 |
| Finished | Oct 02 06:28:22 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=985894586 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 255.prim_prince_test.985894586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/255.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/256.prim_prince_test.33735219 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 2370139401 ps |
| CPU time | 45.27 seconds |
| Started | Oct 02 06:27:47 PM UTC 24 |
| Finished | Oct 02 06:28:44 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33735219 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 256.prim_prince_test.33735219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/256.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/257.prim_prince_test.4270809018 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 1695120958 ps |
| CPU time | 32.12 seconds |
| Started | Oct 02 06:27:47 PM UTC 24 |
| Finished | Oct 02 06:28:28 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4270809018 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 257.prim_prince_test.4270809018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/257.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/258.prim_prince_test.2614700762 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 2859275581 ps |
| CPU time | 52.44 seconds |
| Started | Oct 02 06:27:47 PM UTC 24 |
| Finished | Oct 02 06:28:54 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2614700762 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 258.prim_prince_test.2614700762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/258.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/259.prim_prince_test.2751130589 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 1951072432 ps |
| CPU time | 36.32 seconds |
| Started | Oct 02 06:27:48 PM UTC 24 |
| Finished | Oct 02 06:28:35 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2751130589 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 259.prim_prince_test.2751130589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/259.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/26.prim_prince_test.1830342005 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 3628213530 ps |
| CPU time | 72.97 seconds |
| Started | Oct 02 06:22:20 PM UTC 24 |
| Finished | Oct 02 06:23:55 PM UTC 24 |
| Peak memory | 155036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1830342005 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 26.prim_prince_test.1830342005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/26.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/260.prim_prince_test.1891823610 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 2587126835 ps |
| CPU time | 49.92 seconds |
| Started | Oct 02 06:27:49 PM UTC 24 |
| Finished | Oct 02 06:28:52 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1891823610 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 260.prim_prince_test.1891823610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/260.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/261.prim_prince_test.1238542834 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 3265832133 ps |
| CPU time | 59.84 seconds |
| Started | Oct 02 06:27:51 PM UTC 24 |
| Finished | Oct 02 06:29:08 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1238542834 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 261.prim_prince_test.1238542834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/261.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/262.prim_prince_test.3036016074 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 3700202615 ps |
| CPU time | 71.06 seconds |
| Started | Oct 02 06:27:51 PM UTC 24 |
| Finished | Oct 02 06:29:22 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3036016074 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 262.prim_prince_test.3036016074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/262.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/263.prim_prince_test.1897056135 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 3500678517 ps |
| CPU time | 68.93 seconds |
| Started | Oct 02 06:27:54 PM UTC 24 |
| Finished | Oct 02 06:29:21 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1897056135 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 263.prim_prince_test.1897056135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/263.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/264.prim_prince_test.604921345 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 1929882366 ps |
| CPU time | 38.14 seconds |
| Started | Oct 02 06:27:55 PM UTC 24 |
| Finished | Oct 02 06:28:44 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=604921345 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 264.prim_prince_test.604921345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/264.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/265.prim_prince_test.3443067085 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 2039874925 ps |
| CPU time | 40.41 seconds |
| Started | Oct 02 06:27:56 PM UTC 24 |
| Finished | Oct 02 06:28:48 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3443067085 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 265.prim_prince_test.3443067085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/265.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/266.prim_prince_test.3625076895 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 1864936428 ps |
| CPU time | 34.25 seconds |
| Started | Oct 02 06:27:59 PM UTC 24 |
| Finished | Oct 02 06:28:44 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3625076895 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 266.prim_prince_test.3625076895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/266.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/267.prim_prince_test.2959402268 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 2929204159 ps |
| CPU time | 53.82 seconds |
| Started | Oct 02 06:28:00 PM UTC 24 |
| Finished | Oct 02 06:29:09 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2959402268 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 267.prim_prince_test.2959402268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/267.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/268.prim_prince_test.1925653361 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 1378644322 ps |
| CPU time | 25.27 seconds |
| Started | Oct 02 06:28:01 PM UTC 24 |
| Finished | Oct 02 06:28:34 PM UTC 24 |
| Peak memory | 154972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1925653361 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 268.prim_prince_test.1925653361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/268.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/269.prim_prince_test.951991053 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 3437083198 ps |
| CPU time | 62.68 seconds |
| Started | Oct 02 06:28:01 PM UTC 24 |
| Finished | Oct 02 06:29:22 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=951991053 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 269.prim_prince_test.951991053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/269.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/27.prim_prince_test.1808897659 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 1362824367 ps |
| CPU time | 28.8 seconds |
| Started | Oct 02 06:22:21 PM UTC 24 |
| Finished | Oct 02 06:22:59 PM UTC 24 |
| Peak memory | 154972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1808897659 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 27.prim_prince_test.1808897659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/27.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/270.prim_prince_test.1090175179 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 3218998511 ps |
| CPU time | 60.52 seconds |
| Started | Oct 02 06:28:02 PM UTC 24 |
| Finished | Oct 02 06:29:20 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1090175179 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 270.prim_prince_test.1090175179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/270.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/271.prim_prince_test.3987360817 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 1888931619 ps |
| CPU time | 35.1 seconds |
| Started | Oct 02 06:28:02 PM UTC 24 |
| Finished | Oct 02 06:28:48 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3987360817 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 271.prim_prince_test.3987360817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/271.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/272.prim_prince_test.1870288084 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 1509704018 ps |
| CPU time | 27.62 seconds |
| Started | Oct 02 06:28:03 PM UTC 24 |
| Finished | Oct 02 06:28:40 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1870288084 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 272.prim_prince_test.1870288084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/272.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/273.prim_prince_test.3810003798 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 2726121915 ps |
| CPU time | 50.07 seconds |
| Started | Oct 02 06:28:05 PM UTC 24 |
| Finished | Oct 02 06:29:10 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3810003798 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 273.prim_prince_test.3810003798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/273.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/274.prim_prince_test.969918175 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 1058139058 ps |
| CPU time | 20.85 seconds |
| Started | Oct 02 06:28:07 PM UTC 24 |
| Finished | Oct 02 06:28:34 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=969918175 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 274.prim_prince_test.969918175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/274.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/275.prim_prince_test.1296541791 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 1219951832 ps |
| CPU time | 24.29 seconds |
| Started | Oct 02 06:28:07 PM UTC 24 |
| Finished | Oct 02 06:28:38 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1296541791 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 275.prim_prince_test.1296541791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/275.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/276.prim_prince_test.1374897747 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 1081950706 ps |
| CPU time | 21.45 seconds |
| Started | Oct 02 06:28:07 PM UTC 24 |
| Finished | Oct 02 06:28:35 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1374897747 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 276.prim_prince_test.1374897747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/276.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/277.prim_prince_test.776642443 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 1514550171 ps |
| CPU time | 29.55 seconds |
| Started | Oct 02 06:28:07 PM UTC 24 |
| Finished | Oct 02 06:28:45 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=776642443 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 277.prim_prince_test.776642443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/277.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/278.prim_prince_test.869864688 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 866788311 ps |
| CPU time | 17.42 seconds |
| Started | Oct 02 06:28:08 PM UTC 24 |
| Finished | Oct 02 06:28:31 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=869864688 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 278.prim_prince_test.869864688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/278.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/279.prim_prince_test.1972936032 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 2766423954 ps |
| CPU time | 50.7 seconds |
| Started | Oct 02 06:28:08 PM UTC 24 |
| Finished | Oct 02 06:29:14 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1972936032 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 279.prim_prince_test.1972936032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/279.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/28.prim_prince_test.397035281 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 3183690425 ps |
| CPU time | 60.32 seconds |
| Started | Oct 02 06:22:22 PM UTC 24 |
| Finished | Oct 02 06:23:43 PM UTC 24 |
| Peak memory | 155028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=397035281 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 28.prim_prince_test.397035281 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/28.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/280.prim_prince_test.1792704244 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 822179526 ps |
| CPU time | 15.45 seconds |
| Started | Oct 02 06:28:09 PM UTC 24 |
| Finished | Oct 02 06:28:30 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1792704244 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 280.prim_prince_test.1792704244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/280.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/281.prim_prince_test.4199611004 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 2448563881 ps |
| CPU time | 45.78 seconds |
| Started | Oct 02 06:28:09 PM UTC 24 |
| Finished | Oct 02 06:29:09 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4199611004 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 281.prim_prince_test.4199611004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/281.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/282.prim_prince_test.1597095818 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 810333415 ps |
| CPU time | 15.45 seconds |
| Started | Oct 02 06:28:09 PM UTC 24 |
| Finished | Oct 02 06:28:30 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1597095818 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 282.prim_prince_test.1597095818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/282.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/283.prim_prince_test.37187535 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 2138366138 ps |
| CPU time | 43.33 seconds |
| Started | Oct 02 06:28:12 PM UTC 24 |
| Finished | Oct 02 06:29:07 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37187535 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 283.prim_prince_test.37187535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/283.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/284.prim_prince_test.463140114 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 2429973887 ps |
| CPU time | 47.51 seconds |
| Started | Oct 02 06:28:13 PM UTC 24 |
| Finished | Oct 02 06:29:14 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=463140114 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 284.prim_prince_test.463140114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/284.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/285.prim_prince_test.237641989 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 3683705426 ps |
| CPU time | 67.37 seconds |
| Started | Oct 02 06:28:15 PM UTC 24 |
| Finished | Oct 02 06:29:42 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=237641989 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 285.prim_prince_test.237641989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/285.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/286.prim_prince_test.2756369345 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 3703008547 ps |
| CPU time | 68.46 seconds |
| Started | Oct 02 06:28:17 PM UTC 24 |
| Finished | Oct 02 06:29:45 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2756369345 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 286.prim_prince_test.2756369345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/286.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/287.prim_prince_test.3118408767 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 1704894839 ps |
| CPU time | 34.4 seconds |
| Started | Oct 02 06:28:18 PM UTC 24 |
| Finished | Oct 02 06:29:02 PM UTC 24 |
| Peak memory | 154792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3118408767 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 287.prim_prince_test.3118408767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/287.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/288.prim_prince_test.3021457528 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 2797632926 ps |
| CPU time | 53.14 seconds |
| Started | Oct 02 06:28:18 PM UTC 24 |
| Finished | Oct 02 06:29:27 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3021457528 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 288.prim_prince_test.3021457528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/288.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/289.prim_prince_test.3486702811 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 1675098482 ps |
| CPU time | 31.98 seconds |
| Started | Oct 02 06:28:18 PM UTC 24 |
| Finished | Oct 02 06:29:00 PM UTC 24 |
| Peak memory | 156336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3486702811 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 289.prim_prince_test.3486702811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/289.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/29.prim_prince_test.1407931570 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 3396251183 ps |
| CPU time | 72.39 seconds |
| Started | Oct 02 06:22:24 PM UTC 24 |
| Finished | Oct 02 06:23:57 PM UTC 24 |
| Peak memory | 155036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1407931570 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 29.prim_prince_test.1407931570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/29.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/290.prim_prince_test.1381025246 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 903150355 ps |
| CPU time | 17.84 seconds |
| Started | Oct 02 06:28:18 PM UTC 24 |
| Finished | Oct 02 06:28:42 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1381025246 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 290.prim_prince_test.1381025246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/290.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/291.prim_prince_test.3868022219 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 3519639498 ps |
| CPU time | 68.97 seconds |
| Started | Oct 02 06:28:21 PM UTC 24 |
| Finished | Oct 02 06:29:49 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3868022219 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 291.prim_prince_test.3868022219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/291.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/292.prim_prince_test.1247778738 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 1602676349 ps |
| CPU time | 30.26 seconds |
| Started | Oct 02 06:28:23 PM UTC 24 |
| Finished | Oct 02 06:29:02 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1247778738 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 292.prim_prince_test.1247778738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/292.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/293.prim_prince_test.2698958217 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 1399290342 ps |
| CPU time | 28.04 seconds |
| Started | Oct 02 06:28:24 PM UTC 24 |
| Finished | Oct 02 06:29:00 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2698958217 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 293.prim_prince_test.2698958217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/293.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/294.prim_prince_test.1117294041 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 2763228397 ps |
| CPU time | 50.67 seconds |
| Started | Oct 02 06:28:24 PM UTC 24 |
| Finished | Oct 02 06:29:29 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1117294041 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 294.prim_prince_test.1117294041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/294.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/295.prim_prince_test.2227112884 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 1184376900 ps |
| CPU time | 23.73 seconds |
| Started | Oct 02 06:28:27 PM UTC 24 |
| Finished | Oct 02 06:28:58 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2227112884 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 295.prim_prince_test.2227112884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/295.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/296.prim_prince_test.1019297642 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 2881508878 ps |
| CPU time | 54.12 seconds |
| Started | Oct 02 06:28:27 PM UTC 24 |
| Finished | Oct 02 06:29:37 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1019297642 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 296.prim_prince_test.1019297642 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/296.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/297.prim_prince_test.3046891477 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 3226127387 ps |
| CPU time | 62.59 seconds |
| Started | Oct 02 06:28:29 PM UTC 24 |
| Finished | Oct 02 06:29:49 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3046891477 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 297.prim_prince_test.3046891477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/297.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/298.prim_prince_test.1987535391 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 1643843493 ps |
| CPU time | 33.46 seconds |
| Started | Oct 02 06:28:30 PM UTC 24 |
| Finished | Oct 02 06:29:13 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1987535391 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 298.prim_prince_test.1987535391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/298.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/299.prim_prince_test.1844559861 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 1595122373 ps |
| CPU time | 32.38 seconds |
| Started | Oct 02 06:28:31 PM UTC 24 |
| Finished | Oct 02 06:29:12 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1844559861 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 299.prim_prince_test.1844559861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/299.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/3.prim_prince_test.2184530078 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 851574834 ps |
| CPU time | 19.93 seconds |
| Started | Oct 02 06:21:40 PM UTC 24 |
| Finished | Oct 02 06:22:07 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2184530078 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 3.prim_prince_test.2184530078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/3.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/30.prim_prince_test.3714977792 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 934240360 ps |
| CPU time | 20.14 seconds |
| Started | Oct 02 06:22:27 PM UTC 24 |
| Finished | Oct 02 06:22:53 PM UTC 24 |
| Peak memory | 154972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3714977792 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 30.prim_prince_test.3714977792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/30.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/300.prim_prince_test.4082022825 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 1363131554 ps |
| CPU time | 26.43 seconds |
| Started | Oct 02 06:28:31 PM UTC 24 |
| Finished | Oct 02 06:29:05 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4082022825 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 300.prim_prince_test.4082022825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/300.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/301.prim_prince_test.398300722 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 1092305344 ps |
| CPU time | 21.03 seconds |
| Started | Oct 02 06:28:32 PM UTC 24 |
| Finished | Oct 02 06:28:59 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=398300722 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 301.prim_prince_test.398300722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/301.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/302.prim_prince_test.283303106 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 984208591 ps |
| CPU time | 20.11 seconds |
| Started | Oct 02 06:28:35 PM UTC 24 |
| Finished | Oct 02 06:29:01 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=283303106 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 302.prim_prince_test.283303106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/302.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/303.prim_prince_test.1512192785 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 3425426867 ps |
| CPU time | 70.67 seconds |
| Started | Oct 02 06:28:35 PM UTC 24 |
| Finished | Oct 02 06:30:04 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1512192785 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 303.prim_prince_test.1512192785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/303.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/304.prim_prince_test.4131427365 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 2836773029 ps |
| CPU time | 52.01 seconds |
| Started | Oct 02 06:28:35 PM UTC 24 |
| Finished | Oct 02 06:29:42 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4131427365 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 304.prim_prince_test.4131427365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/304.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/305.prim_prince_test.3876077126 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 2460084211 ps |
| CPU time | 45.67 seconds |
| Started | Oct 02 06:28:35 PM UTC 24 |
| Finished | Oct 02 06:29:34 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3876077126 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 305.prim_prince_test.3876077126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/305.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/306.prim_prince_test.3177075121 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 1575705189 ps |
| CPU time | 31.73 seconds |
| Started | Oct 02 06:28:36 PM UTC 24 |
| Finished | Oct 02 06:29:17 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3177075121 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 306.prim_prince_test.3177075121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/306.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/307.prim_prince_test.3150711851 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 2684429067 ps |
| CPU time | 49.18 seconds |
| Started | Oct 02 06:28:37 PM UTC 24 |
| Finished | Oct 02 06:29:41 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3150711851 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 307.prim_prince_test.3150711851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/307.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/308.prim_prince_test.3125621890 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 1936356225 ps |
| CPU time | 39.5 seconds |
| Started | Oct 02 06:28:39 PM UTC 24 |
| Finished | Oct 02 06:29:29 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3125621890 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 308.prim_prince_test.3125621890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/308.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/309.prim_prince_test.3097915149 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 1660827197 ps |
| CPU time | 30.69 seconds |
| Started | Oct 02 06:28:41 PM UTC 24 |
| Finished | Oct 02 06:29:21 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3097915149 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 309.prim_prince_test.3097915149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/309.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/31.prim_prince_test.440374872 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 1701883182 ps |
| CPU time | 35.8 seconds |
| Started | Oct 02 06:22:29 PM UTC 24 |
| Finished | Oct 02 06:23:15 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=440374872 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 31.prim_prince_test.440374872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/31.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/310.prim_prince_test.3204286485 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 2690307838 ps |
| CPU time | 53.81 seconds |
| Started | Oct 02 06:28:41 PM UTC 24 |
| Finished | Oct 02 06:29:49 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3204286485 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 310.prim_prince_test.3204286485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/310.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/311.prim_prince_test.93239060 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 2804185666 ps |
| CPU time | 56.14 seconds |
| Started | Oct 02 06:28:43 PM UTC 24 |
| Finished | Oct 02 06:29:54 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=93239060 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 311.prim_prince_test.93239060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/311.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/312.prim_prince_test.3634764764 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 2066281213 ps |
| CPU time | 40.69 seconds |
| Started | Oct 02 06:28:44 PM UTC 24 |
| Finished | Oct 02 06:29:36 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3634764764 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 312.prim_prince_test.3634764764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/312.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/313.prim_prince_test.2193308765 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 3383877345 ps |
| CPU time | 70.47 seconds |
| Started | Oct 02 06:28:44 PM UTC 24 |
| Finished | Oct 02 06:30:13 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2193308765 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 313.prim_prince_test.2193308765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/313.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/314.prim_prince_test.1679162248 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 1355695255 ps |
| CPU time | 26.23 seconds |
| Started | Oct 02 06:28:45 PM UTC 24 |
| Finished | Oct 02 06:29:20 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1679162248 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 314.prim_prince_test.1679162248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/314.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/315.prim_prince_test.250819922 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 3047250830 ps |
| CPU time | 56.02 seconds |
| Started | Oct 02 06:28:46 PM UTC 24 |
| Finished | Oct 02 06:29:58 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=250819922 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 315.prim_prince_test.250819922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/315.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/316.prim_prince_test.3305465160 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 1876010777 ps |
| CPU time | 35.26 seconds |
| Started | Oct 02 06:28:46 PM UTC 24 |
| Finished | Oct 02 06:29:31 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3305465160 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 316.prim_prince_test.3305465160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/316.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/317.prim_prince_test.1564577134 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 3269858371 ps |
| CPU time | 59.49 seconds |
| Started | Oct 02 06:28:46 PM UTC 24 |
| Finished | Oct 02 06:30:03 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1564577134 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 317.prim_prince_test.1564577134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/317.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/318.prim_prince_test.1218785493 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 2540362045 ps |
| CPU time | 46.46 seconds |
| Started | Oct 02 06:28:49 PM UTC 24 |
| Finished | Oct 02 06:29:49 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1218785493 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 318.prim_prince_test.1218785493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/318.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/319.prim_prince_test.1029385897 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 2182669595 ps |
| CPU time | 39.73 seconds |
| Started | Oct 02 06:28:49 PM UTC 24 |
| Finished | Oct 02 06:29:41 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1029385897 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 319.prim_prince_test.1029385897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/319.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/32.prim_prince_test.3570875565 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 1552459672 ps |
| CPU time | 32.72 seconds |
| Started | Oct 02 06:22:31 PM UTC 24 |
| Finished | Oct 02 06:23:13 PM UTC 24 |
| Peak memory | 154972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3570875565 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 32.prim_prince_test.3570875565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/32.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/320.prim_prince_test.1047256464 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 1547515937 ps |
| CPU time | 32.16 seconds |
| Started | Oct 02 06:28:53 PM UTC 24 |
| Finished | Oct 02 06:29:34 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1047256464 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 320.prim_prince_test.1047256464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/320.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/321.prim_prince_test.1160797532 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 3741789171 ps |
| CPU time | 74.82 seconds |
| Started | Oct 02 06:28:53 PM UTC 24 |
| Finished | Oct 02 06:30:28 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1160797532 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 321.prim_prince_test.1160797532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/321.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/322.prim_prince_test.2728386330 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 1557978358 ps |
| CPU time | 32.17 seconds |
| Started | Oct 02 06:28:55 PM UTC 24 |
| Finished | Oct 02 06:29:36 PM UTC 24 |
| Peak memory | 156336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2728386330 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 322.prim_prince_test.2728386330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/322.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/323.prim_prince_test.3700847669 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 3440687255 ps |
| CPU time | 71.02 seconds |
| Started | Oct 02 06:28:58 PM UTC 24 |
| Finished | Oct 02 06:30:28 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3700847669 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 323.prim_prince_test.3700847669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/323.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/324.prim_prince_test.1989855975 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 2837265029 ps |
| CPU time | 53.71 seconds |
| Started | Oct 02 06:29:00 PM UTC 24 |
| Finished | Oct 02 06:30:09 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1989855975 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 324.prim_prince_test.1989855975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/324.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/325.prim_prince_test.790239461 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 2381716924 ps |
| CPU time | 49.62 seconds |
| Started | Oct 02 06:29:01 PM UTC 24 |
| Finished | Oct 02 06:30:04 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=790239461 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 325.prim_prince_test.790239461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/325.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/326.prim_prince_test.784580683 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 917769369 ps |
| CPU time | 19.14 seconds |
| Started | Oct 02 06:29:01 PM UTC 24 |
| Finished | Oct 02 06:29:26 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=784580683 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 326.prim_prince_test.784580683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/326.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/327.prim_prince_test.3397777020 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 3743826739 ps |
| CPU time | 78.29 seconds |
| Started | Oct 02 06:29:02 PM UTC 24 |
| Finished | Oct 02 06:30:41 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3397777020 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 327.prim_prince_test.3397777020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/327.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/328.prim_prince_test.2350713349 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 3391946536 ps |
| CPU time | 63.31 seconds |
| Started | Oct 02 06:29:02 PM UTC 24 |
| Finished | Oct 02 06:30:24 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2350713349 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 328.prim_prince_test.2350713349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/328.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/329.prim_prince_test.2061304040 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 1897698543 ps |
| CPU time | 39.44 seconds |
| Started | Oct 02 06:29:04 PM UTC 24 |
| Finished | Oct 02 06:29:54 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2061304040 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 329.prim_prince_test.2061304040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/329.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/33.prim_prince_test.501251298 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 3485953128 ps |
| CPU time | 73.58 seconds |
| Started | Oct 02 06:22:32 PM UTC 24 |
| Finished | Oct 02 06:24:06 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=501251298 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 33.prim_prince_test.501251298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/33.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/330.prim_prince_test.818226748 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 2968643631 ps |
| CPU time | 61.38 seconds |
| Started | Oct 02 06:29:04 PM UTC 24 |
| Finished | Oct 02 06:30:21 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=818226748 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 330.prim_prince_test.818226748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/330.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/331.prim_prince_test.3220474218 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 1419410518 ps |
| CPU time | 26.82 seconds |
| Started | Oct 02 06:29:06 PM UTC 24 |
| Finished | Oct 02 06:29:41 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3220474218 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 331.prim_prince_test.3220474218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/331.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/332.prim_prince_test.1235864637 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 1287642437 ps |
| CPU time | 26.7 seconds |
| Started | Oct 02 06:29:07 PM UTC 24 |
| Finished | Oct 02 06:29:41 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1235864637 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 332.prim_prince_test.1235864637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/332.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/333.prim_prince_test.3002472487 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 2213184883 ps |
| CPU time | 44.95 seconds |
| Started | Oct 02 06:29:08 PM UTC 24 |
| Finished | Oct 02 06:30:05 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3002472487 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 333.prim_prince_test.3002472487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/333.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/334.prim_prince_test.2891854906 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 1126935044 ps |
| CPU time | 21.73 seconds |
| Started | Oct 02 06:29:09 PM UTC 24 |
| Finished | Oct 02 06:29:38 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2891854906 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 334.prim_prince_test.2891854906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/334.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/335.prim_prince_test.906070776 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 1670574982 ps |
| CPU time | 31.62 seconds |
| Started | Oct 02 06:29:09 PM UTC 24 |
| Finished | Oct 02 06:29:50 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=906070776 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 335.prim_prince_test.906070776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/335.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/336.prim_prince_test.3393278653 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 2069884176 ps |
| CPU time | 43.01 seconds |
| Started | Oct 02 06:29:10 PM UTC 24 |
| Finished | Oct 02 06:30:05 PM UTC 24 |
| Peak memory | 156336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3393278653 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 336.prim_prince_test.3393278653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/336.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/337.prim_prince_test.2098855894 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 2176212576 ps |
| CPU time | 43.77 seconds |
| Started | Oct 02 06:29:12 PM UTC 24 |
| Finished | Oct 02 06:30:07 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2098855894 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 337.prim_prince_test.2098855894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/337.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/338.prim_prince_test.1894909998 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 3415653767 ps |
| CPU time | 64.31 seconds |
| Started | Oct 02 06:29:12 PM UTC 24 |
| Finished | Oct 02 06:30:34 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1894909998 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 338.prim_prince_test.1894909998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/338.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/339.prim_prince_test.3081297973 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 2631487907 ps |
| CPU time | 48.68 seconds |
| Started | Oct 02 06:29:13 PM UTC 24 |
| Finished | Oct 02 06:30:16 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3081297973 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 339.prim_prince_test.3081297973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/339.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/34.prim_prince_test.2112287582 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 1187664357 ps |
| CPU time | 22.73 seconds |
| Started | Oct 02 06:22:35 PM UTC 24 |
| Finished | Oct 02 06:23:05 PM UTC 24 |
| Peak memory | 154972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2112287582 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 34.prim_prince_test.2112287582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/34.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/340.prim_prince_test.2488976745 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 1926311418 ps |
| CPU time | 39.51 seconds |
| Started | Oct 02 06:29:14 PM UTC 24 |
| Finished | Oct 02 06:30:04 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2488976745 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 340.prim_prince_test.2488976745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/340.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/341.prim_prince_test.2736829022 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 1490222132 ps |
| CPU time | 28.11 seconds |
| Started | Oct 02 06:29:15 PM UTC 24 |
| Finished | Oct 02 06:29:52 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2736829022 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 341.prim_prince_test.2736829022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/341.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/342.prim_prince_test.1665956192 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 2018854253 ps |
| CPU time | 41.15 seconds |
| Started | Oct 02 06:29:15 PM UTC 24 |
| Finished | Oct 02 06:30:08 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1665956192 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 342.prim_prince_test.1665956192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/342.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/343.prim_prince_test.4277394462 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 2567844139 ps |
| CPU time | 53.35 seconds |
| Started | Oct 02 06:29:18 PM UTC 24 |
| Finished | Oct 02 06:30:26 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4277394462 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 343.prim_prince_test.4277394462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/343.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/344.prim_prince_test.3553351765 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 3396163293 ps |
| CPU time | 64.23 seconds |
| Started | Oct 02 06:29:21 PM UTC 24 |
| Finished | Oct 02 06:30:43 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3553351765 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 344.prim_prince_test.3553351765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/344.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/345.prim_prince_test.2371634204 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 1708001535 ps |
| CPU time | 31.27 seconds |
| Started | Oct 02 06:29:21 PM UTC 24 |
| Finished | Oct 02 06:30:02 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2371634204 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 345.prim_prince_test.2371634204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/345.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/346.prim_prince_test.3872788485 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 2948355242 ps |
| CPU time | 54.86 seconds |
| Started | Oct 02 06:29:22 PM UTC 24 |
| Finished | Oct 02 06:30:33 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3872788485 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 346.prim_prince_test.3872788485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/346.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/347.prim_prince_test.2150269740 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 1855873585 ps |
| CPU time | 34.96 seconds |
| Started | Oct 02 06:29:23 PM UTC 24 |
| Finished | Oct 02 06:30:08 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2150269740 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 347.prim_prince_test.2150269740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/347.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/348.prim_prince_test.1241052657 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 1418579650 ps |
| CPU time | 28.06 seconds |
| Started | Oct 02 06:29:23 PM UTC 24 |
| Finished | Oct 02 06:29:59 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1241052657 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 348.prim_prince_test.1241052657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/348.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/349.prim_prince_test.2942141534 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 2076848624 ps |
| CPU time | 43.19 seconds |
| Started | Oct 02 06:29:23 PM UTC 24 |
| Finished | Oct 02 06:30:18 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2942141534 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 349.prim_prince_test.2942141534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/349.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/35.prim_prince_test.689036493 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 1569550657 ps |
| CPU time | 31.38 seconds |
| Started | Oct 02 06:22:37 PM UTC 24 |
| Finished | Oct 02 06:23:18 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=689036493 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 35.prim_prince_test.689036493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/35.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/350.prim_prince_test.3734584604 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 3142866126 ps |
| CPU time | 59.3 seconds |
| Started | Oct 02 06:29:26 PM UTC 24 |
| Finished | Oct 02 06:30:43 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3734584604 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 350.prim_prince_test.3734584604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/350.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/351.prim_prince_test.448983367 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 3327153002 ps |
| CPU time | 62.41 seconds |
| Started | Oct 02 06:29:27 PM UTC 24 |
| Finished | Oct 02 06:30:48 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=448983367 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 351.prim_prince_test.448983367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/351.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/352.prim_prince_test.420682507 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 1004573553 ps |
| CPU time | 21.23 seconds |
| Started | Oct 02 06:29:30 PM UTC 24 |
| Finished | Oct 02 06:29:57 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=420682507 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 352.prim_prince_test.420682507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/352.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/353.prim_prince_test.1021838285 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 3538875190 ps |
| CPU time | 68.65 seconds |
| Started | Oct 02 06:29:31 PM UTC 24 |
| Finished | Oct 02 06:30:59 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1021838285 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 353.prim_prince_test.1021838285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/353.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/354.prim_prince_test.4215794789 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 3744476845 ps |
| CPU time | 74.86 seconds |
| Started | Oct 02 06:29:32 PM UTC 24 |
| Finished | Oct 02 06:31:07 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4215794789 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 354.prim_prince_test.4215794789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/354.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/355.prim_prince_test.587483203 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 3260729888 ps |
| CPU time | 61.87 seconds |
| Started | Oct 02 06:29:35 PM UTC 24 |
| Finished | Oct 02 06:30:55 PM UTC 24 |
| Peak memory | 155032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=587483203 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 355.prim_prince_test.587483203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/355.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/356.prim_prince_test.2836676833 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 934208286 ps |
| CPU time | 18.17 seconds |
| Started | Oct 02 06:29:35 PM UTC 24 |
| Finished | Oct 02 06:29:59 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2836676833 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 356.prim_prince_test.2836676833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/356.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/357.prim_prince_test.1837347461 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 2758795890 ps |
| CPU time | 50.6 seconds |
| Started | Oct 02 06:29:38 PM UTC 24 |
| Finished | Oct 02 06:30:43 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1837347461 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 357.prim_prince_test.1837347461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/357.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/358.prim_prince_test.1578106144 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 2988576525 ps |
| CPU time | 63.23 seconds |
| Started | Oct 02 06:29:38 PM UTC 24 |
| Finished | Oct 02 06:30:57 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1578106144 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 358.prim_prince_test.1578106144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/358.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/359.prim_prince_test.1846748084 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 3061364703 ps |
| CPU time | 56.16 seconds |
| Started | Oct 02 06:29:38 PM UTC 24 |
| Finished | Oct 02 06:30:51 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1846748084 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 359.prim_prince_test.1846748084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/359.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/36.prim_prince_test.305385203 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 1408341809 ps |
| CPU time | 28.76 seconds |
| Started | Oct 02 06:22:38 PM UTC 24 |
| Finished | Oct 02 06:23:16 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=305385203 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 36.prim_prince_test.305385203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/36.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/360.prim_prince_test.4249051320 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 3709783071 ps |
| CPU time | 70.58 seconds |
| Started | Oct 02 06:29:39 PM UTC 24 |
| Finished | Oct 02 06:31:10 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4249051320 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 360.prim_prince_test.4249051320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/360.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/361.prim_prince_test.3576569098 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 1173443214 ps |
| CPU time | 25.19 seconds |
| Started | Oct 02 06:29:39 PM UTC 24 |
| Finished | Oct 02 06:30:11 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3576569098 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 361.prim_prince_test.3576569098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/361.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/362.prim_prince_test.3343132446 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 2497388025 ps |
| CPU time | 49.68 seconds |
| Started | Oct 02 06:29:42 PM UTC 24 |
| Finished | Oct 02 06:30:46 PM UTC 24 |
| Peak memory | 155036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3343132446 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 362.prim_prince_test.3343132446 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/362.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/363.prim_prince_test.2160656738 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 1710052228 ps |
| CPU time | 31.94 seconds |
| Started | Oct 02 06:29:42 PM UTC 24 |
| Finished | Oct 02 06:30:24 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2160656738 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 363.prim_prince_test.2160656738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/363.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/364.prim_prince_test.2979135042 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 3635421602 ps |
| CPU time | 71.7 seconds |
| Started | Oct 02 06:29:42 PM UTC 24 |
| Finished | Oct 02 06:31:14 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2979135042 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 364.prim_prince_test.2979135042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/364.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/365.prim_prince_test.3731328947 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 3658542915 ps |
| CPU time | 71.73 seconds |
| Started | Oct 02 06:29:42 PM UTC 24 |
| Finished | Oct 02 06:31:14 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3731328947 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 365.prim_prince_test.3731328947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/365.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/366.prim_prince_test.1749885532 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 1119500425 ps |
| CPU time | 23.48 seconds |
| Started | Oct 02 06:29:44 PM UTC 24 |
| Finished | Oct 02 06:30:14 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1749885532 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 366.prim_prince_test.1749885532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/366.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/367.prim_prince_test.2540855438 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 3457117587 ps |
| CPU time | 72.9 seconds |
| Started | Oct 02 06:29:44 PM UTC 24 |
| Finished | Oct 02 06:31:16 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2540855438 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 367.prim_prince_test.2540855438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/367.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/368.prim_prince_test.4162354803 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 1280778318 ps |
| CPU time | 24.01 seconds |
| Started | Oct 02 06:29:44 PM UTC 24 |
| Finished | Oct 02 06:30:16 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4162354803 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 368.prim_prince_test.4162354803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/368.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/369.prim_prince_test.1201586614 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 3681976203 ps |
| CPU time | 72.82 seconds |
| Started | Oct 02 06:29:46 PM UTC 24 |
| Finished | Oct 02 06:31:19 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1201586614 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 369.prim_prince_test.1201586614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/369.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/37.prim_prince_test.2834923022 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 2767173032 ps |
| CPU time | 58.81 seconds |
| Started | Oct 02 06:22:40 PM UTC 24 |
| Finished | Oct 02 06:23:56 PM UTC 24 |
| Peak memory | 155036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2834923022 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 37.prim_prince_test.2834923022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/37.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/370.prim_prince_test.4265986790 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 1870077931 ps |
| CPU time | 34.36 seconds |
| Started | Oct 02 06:29:50 PM UTC 24 |
| Finished | Oct 02 06:30:35 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4265986790 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 370.prim_prince_test.4265986790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/370.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/371.prim_prince_test.3331527572 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 892389273 ps |
| CPU time | 17.18 seconds |
| Started | Oct 02 06:29:50 PM UTC 24 |
| Finished | Oct 02 06:30:13 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3331527572 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 371.prim_prince_test.3331527572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/371.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/372.prim_prince_test.1573424376 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 2131147519 ps |
| CPU time | 40.27 seconds |
| Started | Oct 02 06:29:50 PM UTC 24 |
| Finished | Oct 02 06:30:42 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1573424376 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 372.prim_prince_test.1573424376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/372.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/373.prim_prince_test.3058057507 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 2003043448 ps |
| CPU time | 37.94 seconds |
| Started | Oct 02 06:29:50 PM UTC 24 |
| Finished | Oct 02 06:30:40 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3058057507 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 373.prim_prince_test.3058057507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/373.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/374.prim_prince_test.2649979729 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 1773534551 ps |
| CPU time | 34.62 seconds |
| Started | Oct 02 06:29:52 PM UTC 24 |
| Finished | Oct 02 06:30:36 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2649979729 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 374.prim_prince_test.2649979729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/374.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/375.prim_prince_test.1864885470 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 3575049737 ps |
| CPU time | 69.7 seconds |
| Started | Oct 02 06:29:52 PM UTC 24 |
| Finished | Oct 02 06:31:21 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1864885470 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 375.prim_prince_test.1864885470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/375.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/376.prim_prince_test.2140184511 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 2987112164 ps |
| CPU time | 59.18 seconds |
| Started | Oct 02 06:29:53 PM UTC 24 |
| Finished | Oct 02 06:31:08 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2140184511 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 376.prim_prince_test.2140184511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/376.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/377.prim_prince_test.4025547188 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 3335600830 ps |
| CPU time | 62.56 seconds |
| Started | Oct 02 06:29:55 PM UTC 24 |
| Finished | Oct 02 06:31:16 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4025547188 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 377.prim_prince_test.4025547188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/377.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/378.prim_prince_test.3038919245 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 3499792666 ps |
| CPU time | 64.66 seconds |
| Started | Oct 02 06:29:55 PM UTC 24 |
| Finished | Oct 02 06:31:19 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3038919245 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 378.prim_prince_test.3038919245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/378.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/379.prim_prince_test.2190098589 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 1767746230 ps |
| CPU time | 36.34 seconds |
| Started | Oct 02 06:29:58 PM UTC 24 |
| Finished | Oct 02 06:30:45 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2190098589 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 379.prim_prince_test.2190098589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/379.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/38.prim_prince_test.3328698616 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 1087647055 ps |
| CPU time | 21.25 seconds |
| Started | Oct 02 06:22:45 PM UTC 24 |
| Finished | Oct 02 06:23:14 PM UTC 24 |
| Peak memory | 154972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3328698616 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 38.prim_prince_test.3328698616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/38.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/380.prim_prince_test.3329025937 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 3381069788 ps |
| CPU time | 62.67 seconds |
| Started | Oct 02 06:29:59 PM UTC 24 |
| Finished | Oct 02 06:31:21 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3329025937 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 380.prim_prince_test.3329025937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/380.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/381.prim_prince_test.1393873342 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 2267530032 ps |
| CPU time | 47.51 seconds |
| Started | Oct 02 06:30:01 PM UTC 24 |
| Finished | Oct 02 06:31:01 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1393873342 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 381.prim_prince_test.1393873342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/381.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/382.prim_prince_test.1236470350 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 3419791697 ps |
| CPU time | 67.1 seconds |
| Started | Oct 02 06:30:01 PM UTC 24 |
| Finished | Oct 02 06:31:26 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1236470350 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 382.prim_prince_test.1236470350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/382.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/383.prim_prince_test.2567414596 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 2970588162 ps |
| CPU time | 59.76 seconds |
| Started | Oct 02 06:30:03 PM UTC 24 |
| Finished | Oct 02 06:31:19 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2567414596 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 383.prim_prince_test.2567414596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/383.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/384.prim_prince_test.3545083508 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 2949284741 ps |
| CPU time | 57.79 seconds |
| Started | Oct 02 06:30:04 PM UTC 24 |
| Finished | Oct 02 06:31:18 PM UTC 24 |
| Peak memory | 156464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3545083508 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 384.prim_prince_test.3545083508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/384.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/385.prim_prince_test.3951219797 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 2942856565 ps |
| CPU time | 62.07 seconds |
| Started | Oct 02 06:30:05 PM UTC 24 |
| Finished | Oct 02 06:31:24 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3951219797 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 385.prim_prince_test.3951219797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/385.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/386.prim_prince_test.378168873 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 3120632177 ps |
| CPU time | 65.38 seconds |
| Started | Oct 02 06:30:05 PM UTC 24 |
| Finished | Oct 02 06:31:28 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=378168873 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 386.prim_prince_test.378168873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/386.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/387.prim_prince_test.2173448110 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 3599192252 ps |
| CPU time | 69 seconds |
| Started | Oct 02 06:30:05 PM UTC 24 |
| Finished | Oct 02 06:31:34 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2173448110 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 387.prim_prince_test.2173448110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/387.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/388.prim_prince_test.923626355 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 1031045189 ps |
| CPU time | 21.95 seconds |
| Started | Oct 02 06:30:06 PM UTC 24 |
| Finished | Oct 02 06:30:34 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=923626355 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 388.prim_prince_test.923626355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/388.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/389.prim_prince_test.1799441845 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 3012714791 ps |
| CPU time | 55.71 seconds |
| Started | Oct 02 06:30:07 PM UTC 24 |
| Finished | Oct 02 06:31:19 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1799441845 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 389.prim_prince_test.1799441845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/389.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/39.prim_prince_test.3906586521 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 3252754468 ps |
| CPU time | 66.81 seconds |
| Started | Oct 02 06:22:47 PM UTC 24 |
| Finished | Oct 02 06:24:13 PM UTC 24 |
| Peak memory | 155036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3906586521 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 39.prim_prince_test.3906586521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/39.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/390.prim_prince_test.2072514388 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 3463450585 ps |
| CPU time | 65.31 seconds |
| Started | Oct 02 06:30:08 PM UTC 24 |
| Finished | Oct 02 06:31:32 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2072514388 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 390.prim_prince_test.2072514388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/390.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/391.prim_prince_test.3065382972 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 3590929689 ps |
| CPU time | 75.66 seconds |
| Started | Oct 02 06:30:09 PM UTC 24 |
| Finished | Oct 02 06:31:44 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3065382972 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 391.prim_prince_test.3065382972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/391.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/392.prim_prince_test.1533110507 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 2188042164 ps |
| CPU time | 40.68 seconds |
| Started | Oct 02 06:30:09 PM UTC 24 |
| Finished | Oct 02 06:31:02 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1533110507 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 392.prim_prince_test.1533110507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/392.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/393.prim_prince_test.1760264592 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 1533094267 ps |
| CPU time | 32.5 seconds |
| Started | Oct 02 06:30:10 PM UTC 24 |
| Finished | Oct 02 06:30:52 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1760264592 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 393.prim_prince_test.1760264592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/393.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/394.prim_prince_test.1616207743 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 2204967367 ps |
| CPU time | 47.27 seconds |
| Started | Oct 02 06:30:12 PM UTC 24 |
| Finished | Oct 02 06:31:11 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1616207743 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 394.prim_prince_test.1616207743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/394.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/395.prim_prince_test.306289653 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 3479279104 ps |
| CPU time | 65.18 seconds |
| Started | Oct 02 06:30:12 PM UTC 24 |
| Finished | Oct 02 06:31:36 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=306289653 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 395.prim_prince_test.306289653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/395.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/396.prim_prince_test.891248126 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 987760514 ps |
| CPU time | 20.78 seconds |
| Started | Oct 02 06:30:14 PM UTC 24 |
| Finished | Oct 02 06:30:41 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=891248126 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 396.prim_prince_test.891248126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/396.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/397.prim_prince_test.2491049321 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 3355593271 ps |
| CPU time | 61.57 seconds |
| Started | Oct 02 06:30:14 PM UTC 24 |
| Finished | Oct 02 06:31:34 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2491049321 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 397.prim_prince_test.2491049321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/397.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/398.prim_prince_test.1222523032 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 3724091261 ps |
| CPU time | 68.17 seconds |
| Started | Oct 02 06:30:15 PM UTC 24 |
| Finished | Oct 02 06:31:44 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1222523032 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 398.prim_prince_test.1222523032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/398.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/399.prim_prince_test.2028141589 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 1356380198 ps |
| CPU time | 28.35 seconds |
| Started | Oct 02 06:30:17 PM UTC 24 |
| Finished | Oct 02 06:30:53 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2028141589 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 399.prim_prince_test.2028141589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/399.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/4.prim_prince_test.87374114 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 3480966642 ps |
| CPU time | 75.02 seconds |
| Started | Oct 02 06:21:40 PM UTC 24 |
| Finished | Oct 02 06:23:18 PM UTC 24 |
| Peak memory | 155036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=87374114 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 4.prim_prince_test.87374114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/4.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/40.prim_prince_test.3630986034 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 1502685305 ps |
| CPU time | 30.95 seconds |
| Started | Oct 02 06:22:48 PM UTC 24 |
| Finished | Oct 02 06:23:29 PM UTC 24 |
| Peak memory | 154972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3630986034 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 40.prim_prince_test.3630986034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/40.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/400.prim_prince_test.4119873314 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 2039732684 ps |
| CPU time | 42.87 seconds |
| Started | Oct 02 06:30:17 PM UTC 24 |
| Finished | Oct 02 06:31:11 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4119873314 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 400.prim_prince_test.4119873314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/400.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/401.prim_prince_test.4106701562 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 2834901320 ps |
| CPU time | 58.39 seconds |
| Started | Oct 02 06:30:19 PM UTC 24 |
| Finished | Oct 02 06:31:33 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4106701562 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 401.prim_prince_test.4106701562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/401.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/402.prim_prince_test.1960262409 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 1007400266 ps |
| CPU time | 19.77 seconds |
| Started | Oct 02 06:30:22 PM UTC 24 |
| Finished | Oct 02 06:30:48 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1960262409 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 402.prim_prince_test.1960262409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/402.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/403.prim_prince_test.1453857737 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 2739864003 ps |
| CPU time | 52.25 seconds |
| Started | Oct 02 06:30:25 PM UTC 24 |
| Finished | Oct 02 06:31:32 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1453857737 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 403.prim_prince_test.1453857737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/403.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/404.prim_prince_test.1393821240 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 1944177999 ps |
| CPU time | 39.04 seconds |
| Started | Oct 02 06:30:25 PM UTC 24 |
| Finished | Oct 02 06:31:15 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1393821240 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 404.prim_prince_test.1393821240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/404.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/405.prim_prince_test.2592004118 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 3669101893 ps |
| CPU time | 67.86 seconds |
| Started | Oct 02 06:30:27 PM UTC 24 |
| Finished | Oct 02 06:31:55 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2592004118 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 405.prim_prince_test.2592004118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/405.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/406.prim_prince_test.1117152112 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 2855050811 ps |
| CPU time | 58.6 seconds |
| Started | Oct 02 06:30:29 PM UTC 24 |
| Finished | Oct 02 06:31:44 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1117152112 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 406.prim_prince_test.1117152112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/406.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/407.prim_prince_test.2481228950 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 1042810989 ps |
| CPU time | 19.97 seconds |
| Started | Oct 02 06:30:29 PM UTC 24 |
| Finished | Oct 02 06:30:56 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2481228950 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 407.prim_prince_test.2481228950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/407.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/408.prim_prince_test.2776569841 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 2072180112 ps |
| CPU time | 42.19 seconds |
| Started | Oct 02 06:30:32 PM UTC 24 |
| Finished | Oct 02 06:31:26 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2776569841 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 408.prim_prince_test.2776569841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/408.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/409.prim_prince_test.580554340 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 1973862287 ps |
| CPU time | 41.46 seconds |
| Started | Oct 02 06:30:34 PM UTC 24 |
| Finished | Oct 02 06:31:26 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=580554340 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 409.prim_prince_test.580554340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/409.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/41.prim_prince_test.4147565736 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 1517641401 ps |
| CPU time | 28.96 seconds |
| Started | Oct 02 06:22:51 PM UTC 24 |
| Finished | Oct 02 06:23:30 PM UTC 24 |
| Peak memory | 154972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4147565736 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 41.prim_prince_test.4147565736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/41.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/410.prim_prince_test.1425341755 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 2121375299 ps |
| CPU time | 40.65 seconds |
| Started | Oct 02 06:30:35 PM UTC 24 |
| Finished | Oct 02 06:31:27 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1425341755 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 410.prim_prince_test.1425341755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/410.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/411.prim_prince_test.1465882613 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 886814139 ps |
| CPU time | 19.23 seconds |
| Started | Oct 02 06:30:36 PM UTC 24 |
| Finished | Oct 02 06:31:01 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1465882613 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 411.prim_prince_test.1465882613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/411.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/412.prim_prince_test.2220114798 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 3595166098 ps |
| CPU time | 72.68 seconds |
| Started | Oct 02 06:30:36 PM UTC 24 |
| Finished | Oct 02 06:32:08 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2220114798 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 412.prim_prince_test.2220114798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/412.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/413.prim_prince_test.2731394371 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 1045059713 ps |
| CPU time | 22.55 seconds |
| Started | Oct 02 06:30:37 PM UTC 24 |
| Finished | Oct 02 06:31:06 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2731394371 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 413.prim_prince_test.2731394371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/413.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/414.prim_prince_test.236836207 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 788083572 ps |
| CPU time | 16.96 seconds |
| Started | Oct 02 06:30:40 PM UTC 24 |
| Finished | Oct 02 06:31:03 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=236836207 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 414.prim_prince_test.236836207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/414.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/415.prim_prince_test.801908669 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 3032909251 ps |
| CPU time | 60.57 seconds |
| Started | Oct 02 06:30:42 PM UTC 24 |
| Finished | Oct 02 06:31:59 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=801908669 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 415.prim_prince_test.801908669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/415.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/416.prim_prince_test.4160613213 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 1403391676 ps |
| CPU time | 26.89 seconds |
| Started | Oct 02 06:30:42 PM UTC 24 |
| Finished | Oct 02 06:31:17 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4160613213 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 416.prim_prince_test.4160613213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/416.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/417.prim_prince_test.852698187 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 1115755160 ps |
| CPU time | 22.06 seconds |
| Started | Oct 02 06:30:43 PM UTC 24 |
| Finished | Oct 02 06:31:12 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=852698187 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 417.prim_prince_test.852698187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/417.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/418.prim_prince_test.2130550587 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 1910631026 ps |
| CPU time | 35.97 seconds |
| Started | Oct 02 06:30:44 PM UTC 24 |
| Finished | Oct 02 06:31:31 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2130550587 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 418.prim_prince_test.2130550587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/418.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/419.prim_prince_test.2077362874 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 1382787350 ps |
| CPU time | 25.98 seconds |
| Started | Oct 02 06:30:44 PM UTC 24 |
| Finished | Oct 02 06:31:18 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2077362874 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 419.prim_prince_test.2077362874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/419.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/42.prim_prince_test.1631671384 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 2743531212 ps |
| CPU time | 51.2 seconds |
| Started | Oct 02 06:22:53 PM UTC 24 |
| Finished | Oct 02 06:24:01 PM UTC 24 |
| Peak memory | 155036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1631671384 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 42.prim_prince_test.1631671384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/42.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/420.prim_prince_test.3905970478 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 2380189001 ps |
| CPU time | 50.52 seconds |
| Started | Oct 02 06:30:44 PM UTC 24 |
| Finished | Oct 02 06:31:48 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3905970478 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 420.prim_prince_test.3905970478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/420.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/421.prim_prince_test.3449424461 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 2769353438 ps |
| CPU time | 51.63 seconds |
| Started | Oct 02 06:30:45 PM UTC 24 |
| Finished | Oct 02 06:31:52 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3449424461 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 421.prim_prince_test.3449424461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/421.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/422.prim_prince_test.2816776581 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 818244556 ps |
| CPU time | 17.96 seconds |
| Started | Oct 02 06:30:47 PM UTC 24 |
| Finished | Oct 02 06:31:10 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2816776581 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 422.prim_prince_test.2816776581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/422.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/423.prim_prince_test.2741746119 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 3628562106 ps |
| CPU time | 67.37 seconds |
| Started | Oct 02 06:30:49 PM UTC 24 |
| Finished | Oct 02 06:32:16 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2741746119 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 423.prim_prince_test.2741746119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/423.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/424.prim_prince_test.4183750627 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 2457404685 ps |
| CPU time | 52.19 seconds |
| Started | Oct 02 06:30:49 PM UTC 24 |
| Finished | Oct 02 06:31:55 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4183750627 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 424.prim_prince_test.4183750627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/424.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/425.prim_prince_test.1533183654 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 2943086178 ps |
| CPU time | 60.71 seconds |
| Started | Oct 02 06:30:51 PM UTC 24 |
| Finished | Oct 02 06:32:08 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1533183654 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 425.prim_prince_test.1533183654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/425.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/426.prim_prince_test.1914377261 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 3372743716 ps |
| CPU time | 62.46 seconds |
| Started | Oct 02 06:30:52 PM UTC 24 |
| Finished | Oct 02 06:32:13 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1914377261 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 426.prim_prince_test.1914377261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/426.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/427.prim_prince_test.4026784989 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 2605547493 ps |
| CPU time | 54.4 seconds |
| Started | Oct 02 06:30:55 PM UTC 24 |
| Finished | Oct 02 06:32:04 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4026784989 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 427.prim_prince_test.4026784989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/427.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/428.prim_prince_test.3625052891 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 2968232477 ps |
| CPU time | 56.13 seconds |
| Started | Oct 02 06:30:56 PM UTC 24 |
| Finished | Oct 02 06:32:08 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3625052891 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 428.prim_prince_test.3625052891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/428.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/429.prim_prince_test.2326701823 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 884738689 ps |
| CPU time | 19.06 seconds |
| Started | Oct 02 06:30:57 PM UTC 24 |
| Finished | Oct 02 06:31:22 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2326701823 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 429.prim_prince_test.2326701823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/429.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/43.prim_prince_test.3749087765 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 2806150111 ps |
| CPU time | 57.2 seconds |
| Started | Oct 02 06:22:55 PM UTC 24 |
| Finished | Oct 02 06:24:08 PM UTC 24 |
| Peak memory | 155036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3749087765 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 43.prim_prince_test.3749087765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/43.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/430.prim_prince_test.894591146 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 762932213 ps |
| CPU time | 14.9 seconds |
| Started | Oct 02 06:30:58 PM UTC 24 |
| Finished | Oct 02 06:31:18 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=894591146 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 430.prim_prince_test.894591146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/430.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/431.prim_prince_test.1043067405 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 1436675790 ps |
| CPU time | 27.12 seconds |
| Started | Oct 02 06:30:59 PM UTC 24 |
| Finished | Oct 02 06:31:35 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1043067405 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 431.prim_prince_test.1043067405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/431.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/432.prim_prince_test.825342228 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 1909970939 ps |
| CPU time | 40.77 seconds |
| Started | Oct 02 06:31:02 PM UTC 24 |
| Finished | Oct 02 06:31:54 PM UTC 24 |
| Peak memory | 154972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=825342228 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 432.prim_prince_test.825342228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/432.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/433.prim_prince_test.1974691305 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 2503341220 ps |
| CPU time | 46.77 seconds |
| Started | Oct 02 06:31:02 PM UTC 24 |
| Finished | Oct 02 06:32:02 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1974691305 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 433.prim_prince_test.1974691305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/433.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/434.prim_prince_test.3180686296 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 2468769741 ps |
| CPU time | 46.75 seconds |
| Started | Oct 02 06:31:03 PM UTC 24 |
| Finished | Oct 02 06:32:03 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3180686296 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 434.prim_prince_test.3180686296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/434.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/435.prim_prince_test.2999195186 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 813287758 ps |
| CPU time | 15.77 seconds |
| Started | Oct 02 06:31:03 PM UTC 24 |
| Finished | Oct 02 06:31:24 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2999195186 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 435.prim_prince_test.2999195186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/435.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/436.prim_prince_test.3589946929 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 2314200903 ps |
| CPU time | 45.94 seconds |
| Started | Oct 02 06:31:07 PM UTC 24 |
| Finished | Oct 02 06:32:06 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3589946929 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 436.prim_prince_test.3589946929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/436.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/437.prim_prince_test.2197398852 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 3409380001 ps |
| CPU time | 64.3 seconds |
| Started | Oct 02 06:31:09 PM UTC 24 |
| Finished | Oct 02 06:32:31 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2197398852 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 437.prim_prince_test.2197398852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/437.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/438.prim_prince_test.2972058894 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 3208407939 ps |
| CPU time | 66.2 seconds |
| Started | Oct 02 06:31:09 PM UTC 24 |
| Finished | Oct 02 06:32:32 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2972058894 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 438.prim_prince_test.2972058894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/438.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/439.prim_prince_test.3358364123 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 3747574556 ps |
| CPU time | 69.27 seconds |
| Started | Oct 02 06:31:11 PM UTC 24 |
| Finished | Oct 02 06:32:40 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3358364123 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 439.prim_prince_test.3358364123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/439.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/44.prim_prince_test.1765761668 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 1928255826 ps |
| CPU time | 42.04 seconds |
| Started | Oct 02 06:22:55 PM UTC 24 |
| Finished | Oct 02 06:23:49 PM UTC 24 |
| Peak memory | 154972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1765761668 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 44.prim_prince_test.1765761668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/44.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/440.prim_prince_test.3906282563 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 971000738 ps |
| CPU time | 19.45 seconds |
| Started | Oct 02 06:31:11 PM UTC 24 |
| Finished | Oct 02 06:31:37 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3906282563 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 440.prim_prince_test.3906282563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/440.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/441.prim_prince_test.1597456657 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 2049072574 ps |
| CPU time | 42.65 seconds |
| Started | Oct 02 06:31:13 PM UTC 24 |
| Finished | Oct 02 06:32:07 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1597456657 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 441.prim_prince_test.1597456657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/441.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/442.prim_prince_test.187093940 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 3243255805 ps |
| CPU time | 59.47 seconds |
| Started | Oct 02 06:31:13 PM UTC 24 |
| Finished | Oct 02 06:32:30 PM UTC 24 |
| Peak memory | 155036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=187093940 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 442.prim_prince_test.187093940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/442.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/443.prim_prince_test.3206208244 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 1413425581 ps |
| CPU time | 27.27 seconds |
| Started | Oct 02 06:31:13 PM UTC 24 |
| Finished | Oct 02 06:31:48 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3206208244 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 443.prim_prince_test.3206208244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/443.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/444.prim_prince_test.2061351288 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 3446310810 ps |
| CPU time | 69.59 seconds |
| Started | Oct 02 06:31:15 PM UTC 24 |
| Finished | Oct 02 06:32:43 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2061351288 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 444.prim_prince_test.2061351288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/444.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/445.prim_prince_test.4101792813 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 1492179757 ps |
| CPU time | 27.38 seconds |
| Started | Oct 02 06:31:15 PM UTC 24 |
| Finished | Oct 02 06:31:51 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4101792813 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 445.prim_prince_test.4101792813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/445.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/446.prim_prince_test.2965166531 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 1628437295 ps |
| CPU time | 33.9 seconds |
| Started | Oct 02 06:31:15 PM UTC 24 |
| Finished | Oct 02 06:31:58 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2965166531 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 446.prim_prince_test.2965166531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/446.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/447.prim_prince_test.3513803739 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 2412205072 ps |
| CPU time | 47.75 seconds |
| Started | Oct 02 06:31:16 PM UTC 24 |
| Finished | Oct 02 06:32:17 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3513803739 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 447.prim_prince_test.3513803739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/447.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/448.prim_prince_test.3826654505 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 2353104295 ps |
| CPU time | 46.03 seconds |
| Started | Oct 02 06:31:16 PM UTC 24 |
| Finished | Oct 02 06:32:16 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3826654505 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 448.prim_prince_test.3826654505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/448.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/449.prim_prince_test.4221998544 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 1504024588 ps |
| CPU time | 31.34 seconds |
| Started | Oct 02 06:31:18 PM UTC 24 |
| Finished | Oct 02 06:31:58 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4221998544 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 449.prim_prince_test.4221998544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/449.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/45.prim_prince_test.3120166254 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 1200205745 ps |
| CPU time | 26.06 seconds |
| Started | Oct 02 06:22:59 PM UTC 24 |
| Finished | Oct 02 06:23:33 PM UTC 24 |
| Peak memory | 154972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3120166254 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 45.prim_prince_test.3120166254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/45.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/450.prim_prince_test.4045396768 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 2495919500 ps |
| CPU time | 49.34 seconds |
| Started | Oct 02 06:31:18 PM UTC 24 |
| Finished | Oct 02 06:32:21 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4045396768 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 450.prim_prince_test.4045396768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/450.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/451.prim_prince_test.3190919903 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 1891223223 ps |
| CPU time | 39.26 seconds |
| Started | Oct 02 06:31:19 PM UTC 24 |
| Finished | Oct 02 06:32:09 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3190919903 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 451.prim_prince_test.3190919903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/451.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/452.prim_prince_test.762415007 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 2223656200 ps |
| CPU time | 45.52 seconds |
| Started | Oct 02 06:31:19 PM UTC 24 |
| Finished | Oct 02 06:32:17 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=762415007 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 452.prim_prince_test.762415007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/452.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/453.prim_prince_test.3317916876 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 3414850074 ps |
| CPU time | 66.25 seconds |
| Started | Oct 02 06:31:19 PM UTC 24 |
| Finished | Oct 02 06:32:43 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3317916876 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 453.prim_prince_test.3317916876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/453.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/454.prim_prince_test.3441525756 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 2608285002 ps |
| CPU time | 53.11 seconds |
| Started | Oct 02 06:31:21 PM UTC 24 |
| Finished | Oct 02 06:32:28 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3441525756 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 454.prim_prince_test.3441525756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/454.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/455.prim_prince_test.4238920758 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 3307571926 ps |
| CPU time | 59.67 seconds |
| Started | Oct 02 06:31:21 PM UTC 24 |
| Finished | Oct 02 06:32:38 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4238920758 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 455.prim_prince_test.4238920758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/455.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/456.prim_prince_test.1469756208 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 2619324357 ps |
| CPU time | 48.47 seconds |
| Started | Oct 02 06:31:21 PM UTC 24 |
| Finished | Oct 02 06:32:24 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1469756208 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 456.prim_prince_test.1469756208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/456.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/457.prim_prince_test.3936407153 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 2522673849 ps |
| CPU time | 46.65 seconds |
| Started | Oct 02 06:31:21 PM UTC 24 |
| Finished | Oct 02 06:32:22 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3936407153 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 457.prim_prince_test.3936407153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/457.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/458.prim_prince_test.709903087 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 2814344893 ps |
| CPU time | 55.47 seconds |
| Started | Oct 02 06:31:23 PM UTC 24 |
| Finished | Oct 02 06:32:33 PM UTC 24 |
| Peak memory | 155036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=709903087 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 458.prim_prince_test.709903087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/458.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/459.prim_prince_test.1335072399 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 2253108848 ps |
| CPU time | 46.27 seconds |
| Started | Oct 02 06:31:23 PM UTC 24 |
| Finished | Oct 02 06:32:21 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1335072399 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 459.prim_prince_test.1335072399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/459.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/46.prim_prince_test.4267176490 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 1831150307 ps |
| CPU time | 35.3 seconds |
| Started | Oct 02 06:23:00 PM UTC 24 |
| Finished | Oct 02 06:23:46 PM UTC 24 |
| Peak memory | 154972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4267176490 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 46.prim_prince_test.4267176490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/46.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/460.prim_prince_test.2718038607 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 3113164857 ps |
| CPU time | 61.99 seconds |
| Started | Oct 02 06:31:23 PM UTC 24 |
| Finished | Oct 02 06:32:41 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2718038607 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 460.prim_prince_test.2718038607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/460.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/461.prim_prince_test.3443764858 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 2347408459 ps |
| CPU time | 46.41 seconds |
| Started | Oct 02 06:31:25 PM UTC 24 |
| Finished | Oct 02 06:32:24 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3443764858 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 461.prim_prince_test.3443764858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/461.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/462.prim_prince_test.504862087 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 1726138698 ps |
| CPU time | 31.92 seconds |
| Started | Oct 02 06:31:25 PM UTC 24 |
| Finished | Oct 02 06:32:07 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=504862087 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 462.prim_prince_test.504862087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/462.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/463.prim_prince_test.1815091138 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 812806543 ps |
| CPU time | 17.17 seconds |
| Started | Oct 02 06:31:28 PM UTC 24 |
| Finished | Oct 02 06:31:50 PM UTC 24 |
| Peak memory | 154940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1815091138 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 463.prim_prince_test.1815091138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/463.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/464.prim_prince_test.2455766755 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 3373500097 ps |
| CPU time | 61.07 seconds |
| Started | Oct 02 06:31:28 PM UTC 24 |
| Finished | Oct 02 06:32:47 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2455766755 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 464.prim_prince_test.2455766755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/464.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/465.prim_prince_test.2069419295 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 2478595641 ps |
| CPU time | 50.73 seconds |
| Started | Oct 02 06:31:28 PM UTC 24 |
| Finished | Oct 02 06:32:32 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2069419295 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 465.prim_prince_test.2069419295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/465.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/466.prim_prince_test.832960746 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 1570843837 ps |
| CPU time | 28.9 seconds |
| Started | Oct 02 06:31:28 PM UTC 24 |
| Finished | Oct 02 06:32:06 PM UTC 24 |
| Peak memory | 154916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=832960746 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 466.prim_prince_test.832960746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/466.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/467.prim_prince_test.3615916619 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 1559656467 ps |
| CPU time | 31.58 seconds |
| Started | Oct 02 06:31:28 PM UTC 24 |
| Finished | Oct 02 06:32:09 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3615916619 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 467.prim_prince_test.3615916619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/467.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/468.prim_prince_test.2437669906 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 999791446 ps |
| CPU time | 21.62 seconds |
| Started | Oct 02 06:31:29 PM UTC 24 |
| Finished | Oct 02 06:31:57 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2437669906 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 468.prim_prince_test.2437669906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/468.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/469.prim_prince_test.2908494684 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 793465981 ps |
| CPU time | 17.05 seconds |
| Started | Oct 02 06:31:32 PM UTC 24 |
| Finished | Oct 02 06:31:54 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2908494684 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 469.prim_prince_test.2908494684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/469.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/47.prim_prince_test.644184612 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 2724537770 ps |
| CPU time | 51.63 seconds |
| Started | Oct 02 06:23:00 PM UTC 24 |
| Finished | Oct 02 06:24:08 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=644184612 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 47.prim_prince_test.644184612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/47.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/470.prim_prince_test.342551504 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 1718242847 ps |
| CPU time | 32.82 seconds |
| Started | Oct 02 06:31:34 PM UTC 24 |
| Finished | Oct 02 06:32:16 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=342551504 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 470.prim_prince_test.342551504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/470.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/471.prim_prince_test.1681652920 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 1649632667 ps |
| CPU time | 31.77 seconds |
| Started | Oct 02 06:31:34 PM UTC 24 |
| Finished | Oct 02 06:32:15 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1681652920 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 471.prim_prince_test.1681652920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/471.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/472.prim_prince_test.2574312898 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 888080456 ps |
| CPU time | 17.15 seconds |
| Started | Oct 02 06:31:34 PM UTC 24 |
| Finished | Oct 02 06:31:57 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2574312898 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 472.prim_prince_test.2574312898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/472.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/473.prim_prince_test.361448359 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 800243424 ps |
| CPU time | 16.12 seconds |
| Started | Oct 02 06:31:35 PM UTC 24 |
| Finished | Oct 02 06:31:56 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=361448359 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 473.prim_prince_test.361448359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/473.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/474.prim_prince_test.3458742504 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 2246090778 ps |
| CPU time | 44.48 seconds |
| Started | Oct 02 06:31:35 PM UTC 24 |
| Finished | Oct 02 06:32:32 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3458742504 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 474.prim_prince_test.3458742504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/474.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/475.prim_prince_test.1115713582 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 2343755316 ps |
| CPU time | 47.84 seconds |
| Started | Oct 02 06:31:37 PM UTC 24 |
| Finished | Oct 02 06:32:37 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1115713582 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 475.prim_prince_test.1115713582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/475.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/476.prim_prince_test.3167472760 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 757708571 ps |
| CPU time | 14.65 seconds |
| Started | Oct 02 06:31:37 PM UTC 24 |
| Finished | Oct 02 06:31:56 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3167472760 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 476.prim_prince_test.3167472760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/476.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/477.prim_prince_test.3329842975 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 2276504970 ps |
| CPU time | 45.49 seconds |
| Started | Oct 02 06:31:38 PM UTC 24 |
| Finished | Oct 02 06:32:36 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3329842975 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 477.prim_prince_test.3329842975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/477.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/478.prim_prince_test.236458006 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 1644200315 ps |
| CPU time | 31.06 seconds |
| Started | Oct 02 06:31:45 PM UTC 24 |
| Finished | Oct 02 06:32:26 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=236458006 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 478.prim_prince_test.236458006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/478.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/479.prim_prince_test.4192235868 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 822084675 ps |
| CPU time | 17.23 seconds |
| Started | Oct 02 06:31:45 PM UTC 24 |
| Finished | Oct 02 06:32:08 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4192235868 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 479.prim_prince_test.4192235868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/479.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/48.prim_prince_test.2729703053 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 3003607640 ps |
| CPU time | 64.16 seconds |
| Started | Oct 02 06:23:02 PM UTC 24 |
| Finished | Oct 02 06:24:24 PM UTC 24 |
| Peak memory | 155036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2729703053 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 48.prim_prince_test.2729703053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/48.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/480.prim_prince_test.1007492295 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 1701911094 ps |
| CPU time | 32.3 seconds |
| Started | Oct 02 06:31:45 PM UTC 24 |
| Finished | Oct 02 06:32:27 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1007492295 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 480.prim_prince_test.1007492295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/480.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/481.prim_prince_test.3100528411 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 1666885076 ps |
| CPU time | 30.72 seconds |
| Started | Oct 02 06:31:45 PM UTC 24 |
| Finished | Oct 02 06:32:25 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3100528411 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 481.prim_prince_test.3100528411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/481.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/482.prim_prince_test.349828714 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 818858929 ps |
| CPU time | 15.44 seconds |
| Started | Oct 02 06:31:49 PM UTC 24 |
| Finished | Oct 02 06:32:09 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=349828714 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 482.prim_prince_test.349828714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/482.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/483.prim_prince_test.412714531 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 3510023807 ps |
| CPU time | 69.07 seconds |
| Started | Oct 02 06:31:49 PM UTC 24 |
| Finished | Oct 02 06:33:18 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=412714531 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 483.prim_prince_test.412714531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/483.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/484.prim_prince_test.3589355894 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 3549704133 ps |
| CPU time | 69.61 seconds |
| Started | Oct 02 06:31:51 PM UTC 24 |
| Finished | Oct 02 06:33:21 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3589355894 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 484.prim_prince_test.3589355894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/484.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/485.prim_prince_test.3412019723 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 3261662541 ps |
| CPU time | 63.55 seconds |
| Started | Oct 02 06:31:52 PM UTC 24 |
| Finished | Oct 02 06:33:14 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3412019723 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 485.prim_prince_test.3412019723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/485.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/486.prim_prince_test.1296867963 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 3369003402 ps |
| CPU time | 67.6 seconds |
| Started | Oct 02 06:31:53 PM UTC 24 |
| Finished | Oct 02 06:33:21 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1296867963 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 486.prim_prince_test.1296867963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/486.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/487.prim_prince_test.3606825679 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 1757353160 ps |
| CPU time | 32.6 seconds |
| Started | Oct 02 06:31:55 PM UTC 24 |
| Finished | Oct 02 06:32:37 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3606825679 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 487.prim_prince_test.3606825679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/487.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/488.prim_prince_test.463387318 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 1190884915 ps |
| CPU time | 23.82 seconds |
| Started | Oct 02 06:31:56 PM UTC 24 |
| Finished | Oct 02 06:32:27 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=463387318 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 488.prim_prince_test.463387318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/488.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/489.prim_prince_test.3096186374 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 1751120091 ps |
| CPU time | 34.5 seconds |
| Started | Oct 02 06:31:56 PM UTC 24 |
| Finished | Oct 02 06:32:40 PM UTC 24 |
| Peak memory | 154972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3096186374 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 489.prim_prince_test.3096186374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/489.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/49.prim_prince_test.2131736388 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 1750061126 ps |
| CPU time | 32.89 seconds |
| Started | Oct 02 06:23:03 PM UTC 24 |
| Finished | Oct 02 06:23:47 PM UTC 24 |
| Peak memory | 154972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2131736388 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 49.prim_prince_test.2131736388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/49.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/490.prim_prince_test.988789045 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 843184375 ps |
| CPU time | 15.89 seconds |
| Started | Oct 02 06:31:56 PM UTC 24 |
| Finished | Oct 02 06:32:17 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=988789045 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 490.prim_prince_test.988789045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/490.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/491.prim_prince_test.2054038725 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 2449967334 ps |
| CPU time | 45.95 seconds |
| Started | Oct 02 06:31:58 PM UTC 24 |
| Finished | Oct 02 06:32:57 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2054038725 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 491.prim_prince_test.2054038725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/491.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/492.prim_prince_test.3296146625 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 3188351899 ps |
| CPU time | 56.87 seconds |
| Started | Oct 02 06:31:58 PM UTC 24 |
| Finished | Oct 02 06:33:13 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3296146625 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 492.prim_prince_test.3296146625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/492.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/493.prim_prince_test.367448277 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 2842472848 ps |
| CPU time | 55.87 seconds |
| Started | Oct 02 06:31:58 PM UTC 24 |
| Finished | Oct 02 06:33:10 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=367448277 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 493.prim_prince_test.367448277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/493.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/494.prim_prince_test.1602292862 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 2106225446 ps |
| CPU time | 39.08 seconds |
| Started | Oct 02 06:31:59 PM UTC 24 |
| Finished | Oct 02 06:32:50 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1602292862 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 494.prim_prince_test.1602292862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/494.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/495.prim_prince_test.3441005815 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 2021341786 ps |
| CPU time | 35.22 seconds |
| Started | Oct 02 06:31:59 PM UTC 24 |
| Finished | Oct 02 06:32:45 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3441005815 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 495.prim_prince_test.3441005815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/495.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/496.prim_prince_test.3858239319 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 1777700028 ps |
| CPU time | 31.75 seconds |
| Started | Oct 02 06:31:59 PM UTC 24 |
| Finished | Oct 02 06:32:41 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3858239319 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 496.prim_prince_test.3858239319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/496.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/497.prim_prince_test.1313507539 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 1161457188 ps |
| CPU time | 21.04 seconds |
| Started | Oct 02 06:32:01 PM UTC 24 |
| Finished | Oct 02 06:32:28 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1313507539 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 497.prim_prince_test.1313507539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/497.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/498.prim_prince_test.894398726 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 1978227885 ps |
| CPU time | 33.84 seconds |
| Started | Oct 02 06:32:04 PM UTC 24 |
| Finished | Oct 02 06:32:48 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=894398726 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 498.prim_prince_test.894398726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/498.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/499.prim_prince_test.668729471 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 1411454238 ps |
| CPU time | 25.23 seconds |
| Started | Oct 02 06:32:04 PM UTC 24 |
| Finished | Oct 02 06:32:37 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=668729471 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 499.prim_prince_test.668729471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/499.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/5.prim_prince_test.963936900 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 1372651876 ps |
| CPU time | 30.51 seconds |
| Started | Oct 02 06:21:40 PM UTC 24 |
| Finished | Oct 02 06:22:21 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=963936900 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 5.prim_prince_test.963936900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/5.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/50.prim_prince_test.2423655660 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 3479527783 ps |
| CPU time | 70.33 seconds |
| Started | Oct 02 06:23:06 PM UTC 24 |
| Finished | Oct 02 06:24:37 PM UTC 24 |
| Peak memory | 155036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2423655660 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 50.prim_prince_test.2423655660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/50.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/51.prim_prince_test.2456977755 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 788519992 ps |
| CPU time | 17.31 seconds |
| Started | Oct 02 06:23:08 PM UTC 24 |
| Finished | Oct 02 06:23:31 PM UTC 24 |
| Peak memory | 154972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2456977755 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 51.prim_prince_test.2456977755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/51.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/52.prim_prince_test.3163442386 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 3009357750 ps |
| CPU time | 60.2 seconds |
| Started | Oct 02 06:23:10 PM UTC 24 |
| Finished | Oct 02 06:24:28 PM UTC 24 |
| Peak memory | 155036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3163442386 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 52.prim_prince_test.3163442386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/52.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/53.prim_prince_test.1451808307 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 2588838203 ps |
| CPU time | 54.6 seconds |
| Started | Oct 02 06:23:11 PM UTC 24 |
| Finished | Oct 02 06:24:21 PM UTC 24 |
| Peak memory | 155036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1451808307 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 53.prim_prince_test.1451808307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/53.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/54.prim_prince_test.808893802 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 2659333546 ps |
| CPU time | 49.33 seconds |
| Started | Oct 02 06:23:14 PM UTC 24 |
| Finished | Oct 02 06:24:20 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=808893802 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 54.prim_prince_test.808893802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/54.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/55.prim_prince_test.178652752 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 1767021889 ps |
| CPU time | 38.03 seconds |
| Started | Oct 02 06:23:14 PM UTC 24 |
| Finished | Oct 02 06:24:03 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=178652752 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 55.prim_prince_test.178652752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/55.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/56.prim_prince_test.153723455 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 3439758607 ps |
| CPU time | 67.43 seconds |
| Started | Oct 02 06:23:16 PM UTC 24 |
| Finished | Oct 02 06:24:44 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=153723455 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 56.prim_prince_test.153723455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/56.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/57.prim_prince_test.3697278336 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 3683618230 ps |
| CPU time | 67.56 seconds |
| Started | Oct 02 06:23:16 PM UTC 24 |
| Finished | Oct 02 06:24:45 PM UTC 24 |
| Peak memory | 155036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3697278336 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 57.prim_prince_test.3697278336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/57.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/58.prim_prince_test.63754014 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 2399992206 ps |
| CPU time | 48.46 seconds |
| Started | Oct 02 06:23:19 PM UTC 24 |
| Finished | Oct 02 06:24:21 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=63754014 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 58.prim_prince_test.63754014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/58.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/59.prim_prince_test.4009686559 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 2317803908 ps |
| CPU time | 46.3 seconds |
| Started | Oct 02 06:23:19 PM UTC 24 |
| Finished | Oct 02 06:24:19 PM UTC 24 |
| Peak memory | 155036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4009686559 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 59.prim_prince_test.4009686559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/59.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/6.prim_prince_test.2887313115 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 3272273559 ps |
| CPU time | 67.37 seconds |
| Started | Oct 02 06:21:40 PM UTC 24 |
| Finished | Oct 02 06:23:10 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2887313115 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 6.prim_prince_test.2887313115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/6.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/60.prim_prince_test.408789166 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 1079977536 ps |
| CPU time | 22.37 seconds |
| Started | Oct 02 06:23:19 PM UTC 24 |
| Finished | Oct 02 06:23:48 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=408789166 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 60.prim_prince_test.408789166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/60.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/61.prim_prince_test.2373386254 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 3639121196 ps |
| CPU time | 76.26 seconds |
| Started | Oct 02 06:23:20 PM UTC 24 |
| Finished | Oct 02 06:24:57 PM UTC 24 |
| Peak memory | 155036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2373386254 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 61.prim_prince_test.2373386254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/61.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/62.prim_prince_test.2744429720 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 1645450805 ps |
| CPU time | 34.72 seconds |
| Started | Oct 02 06:23:30 PM UTC 24 |
| Finished | Oct 02 06:24:15 PM UTC 24 |
| Peak memory | 154972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2744429720 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 62.prim_prince_test.2744429720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/62.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/63.prim_prince_test.4077221416 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 1550851122 ps |
| CPU time | 30.2 seconds |
| Started | Oct 02 06:23:30 PM UTC 24 |
| Finished | Oct 02 06:24:10 PM UTC 24 |
| Peak memory | 154972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4077221416 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 63.prim_prince_test.4077221416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/63.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/64.prim_prince_test.681389980 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 1007254466 ps |
| CPU time | 19.64 seconds |
| Started | Oct 02 06:23:31 PM UTC 24 |
| Finished | Oct 02 06:23:58 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=681389980 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 64.prim_prince_test.681389980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/64.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/65.prim_prince_test.2625851473 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 1339369279 ps |
| CPU time | 25.28 seconds |
| Started | Oct 02 06:23:31 PM UTC 24 |
| Finished | Oct 02 06:24:05 PM UTC 24 |
| Peak memory | 154972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2625851473 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 65.prim_prince_test.2625851473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/65.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/66.prim_prince_test.3571844065 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 1487598930 ps |
| CPU time | 28.33 seconds |
| Started | Oct 02 06:23:32 PM UTC 24 |
| Finished | Oct 02 06:24:10 PM UTC 24 |
| Peak memory | 154972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3571844065 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 66.prim_prince_test.3571844065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/66.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/67.prim_prince_test.4252832832 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 2254524914 ps |
| CPU time | 43.43 seconds |
| Started | Oct 02 06:23:33 PM UTC 24 |
| Finished | Oct 02 06:24:30 PM UTC 24 |
| Peak memory | 155036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4252832832 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 67.prim_prince_test.4252832832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/67.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/68.prim_prince_test.178531389 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 893393615 ps |
| CPU time | 19.06 seconds |
| Started | Oct 02 06:23:34 PM UTC 24 |
| Finished | Oct 02 06:23:59 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=178531389 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 68.prim_prince_test.178531389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/68.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/69.prim_prince_test.1392876146 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 852466088 ps |
| CPU time | 18.09 seconds |
| Started | Oct 02 06:23:35 PM UTC 24 |
| Finished | Oct 02 06:23:59 PM UTC 24 |
| Peak memory | 154972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1392876146 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 69.prim_prince_test.1392876146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/69.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/7.prim_prince_test.839498577 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 3181171325 ps |
| CPU time | 65.94 seconds |
| Started | Oct 02 06:21:41 PM UTC 24 |
| Finished | Oct 02 06:23:09 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=839498577 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 7.prim_prince_test.839498577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/7.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/70.prim_prince_test.1656253207 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 2176978060 ps |
| CPU time | 41.31 seconds |
| Started | Oct 02 06:23:41 PM UTC 24 |
| Finished | Oct 02 06:24:36 PM UTC 24 |
| Peak memory | 155036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1656253207 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 70.prim_prince_test.1656253207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/70.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/71.prim_prince_test.2493697174 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 2573520845 ps |
| CPU time | 53.27 seconds |
| Started | Oct 02 06:23:43 PM UTC 24 |
| Finished | Oct 02 06:24:52 PM UTC 24 |
| Peak memory | 155036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2493697174 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 71.prim_prince_test.2493697174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/71.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/72.prim_prince_test.3997319329 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 2067872869 ps |
| CPU time | 38.97 seconds |
| Started | Oct 02 06:23:45 PM UTC 24 |
| Finished | Oct 02 06:24:36 PM UTC 24 |
| Peak memory | 154972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3997319329 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 72.prim_prince_test.3997319329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/72.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/73.prim_prince_test.2256106560 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 2579267972 ps |
| CPU time | 49.96 seconds |
| Started | Oct 02 06:23:48 PM UTC 24 |
| Finished | Oct 02 06:24:53 PM UTC 24 |
| Peak memory | 155036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2256106560 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 73.prim_prince_test.2256106560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/73.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/74.prim_prince_test.3189097113 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 3493837779 ps |
| CPU time | 66.47 seconds |
| Started | Oct 02 06:23:48 PM UTC 24 |
| Finished | Oct 02 06:25:14 PM UTC 24 |
| Peak memory | 155036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3189097113 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 74.prim_prince_test.3189097113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/74.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/75.prim_prince_test.2378610628 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 3255786093 ps |
| CPU time | 60.68 seconds |
| Started | Oct 02 06:23:49 PM UTC 24 |
| Finished | Oct 02 06:25:08 PM UTC 24 |
| Peak memory | 155036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2378610628 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 75.prim_prince_test.2378610628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/75.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/76.prim_prince_test.2070934015 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 2771339664 ps |
| CPU time | 57.94 seconds |
| Started | Oct 02 06:23:50 PM UTC 24 |
| Finished | Oct 02 06:25:04 PM UTC 24 |
| Peak memory | 155036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2070934015 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 76.prim_prince_test.2070934015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/76.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/77.prim_prince_test.2836534907 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 1323923610 ps |
| CPU time | 27.62 seconds |
| Started | Oct 02 06:23:50 PM UTC 24 |
| Finished | Oct 02 06:24:26 PM UTC 24 |
| Peak memory | 154972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2836534907 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 77.prim_prince_test.2836534907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/77.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/78.prim_prince_test.3122620518 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 2733965760 ps |
| CPU time | 57.26 seconds |
| Started | Oct 02 06:23:52 PM UTC 24 |
| Finished | Oct 02 06:25:05 PM UTC 24 |
| Peak memory | 155036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3122620518 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 78.prim_prince_test.3122620518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/78.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/79.prim_prince_test.1689875932 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 3733858995 ps |
| CPU time | 74.89 seconds |
| Started | Oct 02 06:23:56 PM UTC 24 |
| Finished | Oct 02 06:25:32 PM UTC 24 |
| Peak memory | 155036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1689875932 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 79.prim_prince_test.1689875932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/79.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/8.prim_prince_test.70740794 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 2379163685 ps |
| CPU time | 52.16 seconds |
| Started | Oct 02 06:21:42 PM UTC 24 |
| Finished | Oct 02 06:22:50 PM UTC 24 |
| Peak memory | 154992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=70740794 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 8.prim_prince_test.70740794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/8.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/80.prim_prince_test.219724589 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 1434095412 ps |
| CPU time | 27.58 seconds |
| Started | Oct 02 06:23:56 PM UTC 24 |
| Finished | Oct 02 06:24:32 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=219724589 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 80.prim_prince_test.219724589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/80.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/81.prim_prince_test.377996015 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 2393759109 ps |
| CPU time | 44.47 seconds |
| Started | Oct 02 06:23:57 PM UTC 24 |
| Finished | Oct 02 06:24:56 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=377996015 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 81.prim_prince_test.377996015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/81.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/82.prim_prince_test.263469538 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 1560063973 ps |
| CPU time | 30.51 seconds |
| Started | Oct 02 06:23:57 PM UTC 24 |
| Finished | Oct 02 06:24:37 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=263469538 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 82.prim_prince_test.263469538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/82.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/83.prim_prince_test.2267849031 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 1488624105 ps |
| CPU time | 31.26 seconds |
| Started | Oct 02 06:23:57 PM UTC 24 |
| Finished | Oct 02 06:24:37 PM UTC 24 |
| Peak memory | 154972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2267849031 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 83.prim_prince_test.2267849031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/83.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/84.prim_prince_test.2462580772 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 2702934788 ps |
| CPU time | 56.92 seconds |
| Started | Oct 02 06:23:58 PM UTC 24 |
| Finished | Oct 02 06:25:11 PM UTC 24 |
| Peak memory | 155036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2462580772 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 84.prim_prince_test.2462580772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/84.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/85.prim_prince_test.2585269935 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 3585174106 ps |
| CPU time | 68.51 seconds |
| Started | Oct 02 06:24:00 PM UTC 24 |
| Finished | Oct 02 06:25:29 PM UTC 24 |
| Peak memory | 155036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2585269935 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 85.prim_prince_test.2585269935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/85.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/86.prim_prince_test.1749129283 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 3390778479 ps |
| CPU time | 71.46 seconds |
| Started | Oct 02 06:24:00 PM UTC 24 |
| Finished | Oct 02 06:25:31 PM UTC 24 |
| Peak memory | 155036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1749129283 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 86.prim_prince_test.1749129283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/86.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/87.prim_prince_test.1280081188 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 3594953419 ps |
| CPU time | 71.38 seconds |
| Started | Oct 02 06:24:02 PM UTC 24 |
| Finished | Oct 02 06:25:33 PM UTC 24 |
| Peak memory | 155036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1280081188 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 87.prim_prince_test.1280081188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/87.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/88.prim_prince_test.458400617 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 3530422001 ps |
| CPU time | 74.12 seconds |
| Started | Oct 02 06:24:04 PM UTC 24 |
| Finished | Oct 02 06:25:38 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=458400617 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 88.prim_prince_test.458400617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/88.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/89.prim_prince_test.1981463497 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 3732965311 ps |
| CPU time | 71.85 seconds |
| Started | Oct 02 06:24:07 PM UTC 24 |
| Finished | Oct 02 06:25:40 PM UTC 24 |
| Peak memory | 155036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1981463497 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 89.prim_prince_test.1981463497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/89.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/9.prim_prince_test.3571455159 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 1520518632 ps |
| CPU time | 34.06 seconds |
| Started | Oct 02 06:21:42 PM UTC 24 |
| Finished | Oct 02 06:22:28 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3571455159 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 9.prim_prince_test.3571455159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/9.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/90.prim_prince_test.3649629138 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 1743975767 ps |
| CPU time | 36.27 seconds |
| Started | Oct 02 06:24:07 PM UTC 24 |
| Finished | Oct 02 06:24:53 PM UTC 24 |
| Peak memory | 154972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3649629138 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 90.prim_prince_test.3649629138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/90.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/91.prim_prince_test.3948954159 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 2933008329 ps |
| CPU time | 59.35 seconds |
| Started | Oct 02 06:24:09 PM UTC 24 |
| Finished | Oct 02 06:25:25 PM UTC 24 |
| Peak memory | 155036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3948954159 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 91.prim_prince_test.3948954159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/91.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/92.prim_prince_test.2391446891 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 1490818261 ps |
| CPU time | 31.67 seconds |
| Started | Oct 02 06:24:09 PM UTC 24 |
| Finished | Oct 02 06:24:50 PM UTC 24 |
| Peak memory | 154972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2391446891 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 92.prim_prince_test.2391446891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/92.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/93.prim_prince_test.2567805044 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 1166950010 ps |
| CPU time | 22.59 seconds |
| Started | Oct 02 06:24:11 PM UTC 24 |
| Finished | Oct 02 06:24:41 PM UTC 24 |
| Peak memory | 154972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2567805044 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 93.prim_prince_test.2567805044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/93.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/94.prim_prince_test.2396705598 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 1608177093 ps |
| CPU time | 31.17 seconds |
| Started | Oct 02 06:24:11 PM UTC 24 |
| Finished | Oct 02 06:24:52 PM UTC 24 |
| Peak memory | 154972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2396705598 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 94.prim_prince_test.2396705598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/94.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/95.prim_prince_test.4020567174 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 2341637348 ps |
| CPU time | 44.18 seconds |
| Started | Oct 02 06:24:14 PM UTC 24 |
| Finished | Oct 02 06:25:12 PM UTC 24 |
| Peak memory | 155036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4020567174 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 95.prim_prince_test.4020567174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/95.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/96.prim_prince_test.473421552 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 1762467239 ps |
| CPU time | 33.28 seconds |
| Started | Oct 02 06:24:16 PM UTC 24 |
| Finished | Oct 02 06:25:00 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=473421552 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 96.prim_prince_test.473421552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/96.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/97.prim_prince_test.375709452 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 3458558552 ps |
| CPU time | 64.9 seconds |
| Started | Oct 02 06:24:19 PM UTC 24 |
| Finished | Oct 02 06:25:44 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=375709452 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 97.prim_prince_test.375709452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/97.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/98.prim_prince_test.3033160058 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 1858448938 ps |
| CPU time | 39.37 seconds |
| Started | Oct 02 06:24:20 PM UTC 24 |
| Finished | Oct 02 06:25:11 PM UTC 24 |
| Peak memory | 154972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3033160058 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 98.prim_prince_test.3033160058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/98.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default/99.prim_prince_test.129039143 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 1132924779 ps |
| CPU time | 22.3 seconds |
| Started | Oct 02 06:24:22 PM UTC 24 |
| Finished | Oct 02 06:24:52 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=129039143 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 99.prim_prince_test.129039143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_prince-sim-vcs/99.prim_prince_test/latest |
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