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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00 100.00


Total test records in report: 500
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html
T251 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/259.prim_prince_test.2682245631 Oct 09 02:11:52 AM UTC 24 Oct 09 02:12:43 AM UTC 24 2031644067 ps
T252 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/228.prim_prince_test.2839039920 Oct 09 02:11:16 AM UTC 24 Oct 09 02:12:43 AM UTC 24 3431585436 ps
T253 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/284.prim_prince_test.406670405 Oct 09 02:12:16 AM UTC 24 Oct 09 02:12:46 AM UTC 24 1205189491 ps
T254 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/274.prim_prince_test.2064230588 Oct 09 02:12:02 AM UTC 24 Oct 09 02:12:47 AM UTC 24 1876995435 ps
T255 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/271.prim_prince_test.956983614 Oct 09 02:11:58 AM UTC 24 Oct 09 02:12:50 AM UTC 24 1992981072 ps
T256 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/289.prim_prince_test.1708657773 Oct 09 02:12:27 AM UTC 24 Oct 09 02:12:50 AM UTC 24 837271457 ps
T257 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/229.prim_prince_test.2560186073 Oct 09 02:11:21 AM UTC 24 Oct 09 02:12:51 AM UTC 24 3554131714 ps
T258 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/263.prim_prince_test.2393569725 Oct 09 02:11:54 AM UTC 24 Oct 09 02:12:51 AM UTC 24 2177222518 ps
T259 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/285.prim_prince_test.3962121870 Oct 09 02:12:19 AM UTC 24 Oct 09 02:12:52 AM UTC 24 1340165226 ps
T260 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/281.prim_prince_test.1233687831 Oct 09 02:12:11 AM UTC 24 Oct 09 02:12:55 AM UTC 24 1660089876 ps
T261 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/272.prim_prince_test.3809886797 Oct 09 02:11:59 AM UTC 24 Oct 09 02:12:57 AM UTC 24 2189892779 ps
T262 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/287.prim_prince_test.2703248664 Oct 09 02:12:22 AM UTC 24 Oct 09 02:12:57 AM UTC 24 1330412871 ps
T263 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/295.prim_prince_test.3957043114 Oct 09 02:12:32 AM UTC 24 Oct 09 02:12:58 AM UTC 24 987038067 ps
T264 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/250.prim_prince_test.2415013973 Oct 09 02:11:46 AM UTC 24 Oct 09 02:12:59 AM UTC 24 2844153743 ps
T265 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/237.prim_prince_test.3627357610 Oct 09 02:11:28 AM UTC 24 Oct 09 02:13:04 AM UTC 24 3758240228 ps
T266 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/304.prim_prince_test.3365073749 Oct 09 02:12:39 AM UTC 24 Oct 09 02:13:04 AM UTC 24 908921705 ps
T267 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/303.prim_prince_test.437405734 Oct 09 02:12:39 AM UTC 24 Oct 09 02:13:04 AM UTC 24 907270166 ps
T268 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/258.prim_prince_test.1669072065 Oct 09 02:11:52 AM UTC 24 Oct 09 02:13:04 AM UTC 24 3042216541 ps
T269 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/265.prim_prince_test.2737583342 Oct 09 02:11:55 AM UTC 24 Oct 09 02:13:04 AM UTC 24 2948778260 ps
T270 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/260.prim_prince_test.2307814156 Oct 09 02:11:53 AM UTC 24 Oct 09 02:13:05 AM UTC 24 2975572056 ps
T271 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/262.prim_prince_test.2101819953 Oct 09 02:11:53 AM UTC 24 Oct 09 02:13:06 AM UTC 24 3020602846 ps
T272 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/276.prim_prince_test.3502133611 Oct 09 02:12:02 AM UTC 24 Oct 09 02:13:07 AM UTC 24 2521085061 ps
T273 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/299.prim_prince_test.878005436 Oct 09 02:12:36 AM UTC 24 Oct 09 02:13:08 AM UTC 24 1274809044 ps
T274 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/248.prim_prince_test.128850877 Oct 09 02:11:45 AM UTC 24 Oct 09 02:13:08 AM UTC 24 3542601642 ps
T275 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/246.prim_prince_test.4103271261 Oct 09 02:11:44 AM UTC 24 Oct 09 02:13:09 AM UTC 24 3553852365 ps
T276 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/252.prim_prince_test.1434868645 Oct 09 02:11:47 AM UTC 24 Oct 09 02:13:09 AM UTC 24 3254817891 ps
T277 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/268.prim_prince_test.2717677517 Oct 09 02:11:57 AM UTC 24 Oct 09 02:13:10 AM UTC 24 2947886358 ps
T278 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/244.prim_prince_test.3543040363 Oct 09 02:11:43 AM UTC 24 Oct 09 02:13:10 AM UTC 24 3628409239 ps
T279 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/254.prim_prince_test.2725195502 Oct 09 02:11:48 AM UTC 24 Oct 09 02:13:10 AM UTC 24 3295575699 ps
T280 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/266.prim_prince_test.3440315036 Oct 09 02:11:56 AM UTC 24 Oct 09 02:13:11 AM UTC 24 3132630691 ps
T281 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/264.prim_prince_test.1414882779 Oct 09 02:11:54 AM UTC 24 Oct 09 02:13:12 AM UTC 24 3111354199 ps
T282 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/253.prim_prince_test.4071989351 Oct 09 02:11:47 AM UTC 24 Oct 09 02:13:13 AM UTC 24 3345436313 ps
T283 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/270.prim_prince_test.2698144660 Oct 09 02:11:58 AM UTC 24 Oct 09 02:13:13 AM UTC 24 2913473283 ps
T284 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/302.prim_prince_test.2059340148 Oct 09 02:12:37 AM UTC 24 Oct 09 02:13:15 AM UTC 24 1462816759 ps
T285 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/257.prim_prince_test.2758329603 Oct 09 02:11:51 AM UTC 24 Oct 09 02:13:15 AM UTC 24 3505705890 ps
T286 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/314.prim_prince_test.2984893070 Oct 09 02:12:53 AM UTC 24 Oct 09 02:13:15 AM UTC 24 865547990 ps
T287 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/293.prim_prince_test.163855975 Oct 09 02:12:30 AM UTC 24 Oct 09 02:13:15 AM UTC 24 1730604430 ps
T288 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/255.prim_prince_test.3654332950 Oct 09 02:11:49 AM UTC 24 Oct 09 02:13:16 AM UTC 24 3535802782 ps
T289 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/309.prim_prince_test.1998683797 Oct 09 02:12:47 AM UTC 24 Oct 09 02:13:16 AM UTC 24 1083626720 ps
T290 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/316.prim_prince_test.3073401293 Oct 09 02:12:56 AM UTC 24 Oct 09 02:13:16 AM UTC 24 790807314 ps
T291 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/273.prim_prince_test.3080973651 Oct 09 02:11:59 AM UTC 24 Oct 09 02:13:17 AM UTC 24 3023901824 ps
T292 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/277.prim_prince_test.1821863605 Oct 09 02:12:03 AM UTC 24 Oct 09 02:13:19 AM UTC 24 3048269574 ps
T293 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/292.prim_prince_test.1133745321 Oct 09 02:12:30 AM UTC 24 Oct 09 02:13:21 AM UTC 24 1928587303 ps
T294 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/283.prim_prince_test.1496263753 Oct 09 02:12:14 AM UTC 24 Oct 09 02:13:22 AM UTC 24 2661876142 ps
T295 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/269.prim_prince_test.4266026069 Oct 09 02:11:58 AM UTC 24 Oct 09 02:13:23 AM UTC 24 3270068070 ps
T296 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/290.prim_prince_test.733343047 Oct 09 02:12:29 AM UTC 24 Oct 09 02:13:23 AM UTC 24 2103907791 ps
T297 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/312.prim_prince_test.3496469349 Oct 09 02:12:52 AM UTC 24 Oct 09 02:13:26 AM UTC 24 1384190204 ps
T298 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/307.prim_prince_test.4095998413 Oct 09 02:12:44 AM UTC 24 Oct 09 02:13:28 AM UTC 24 1828664278 ps
T299 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/301.prim_prince_test.1585718601 Oct 09 02:12:37 AM UTC 24 Oct 09 02:13:29 AM UTC 24 1991225769 ps
T300 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/294.prim_prince_test.814534000 Oct 09 02:12:31 AM UTC 24 Oct 09 02:13:31 AM UTC 24 2447392957 ps
T301 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/326.prim_prince_test.1547800547 Oct 09 02:13:07 AM UTC 24 Oct 09 02:13:31 AM UTC 24 924413084 ps
T302 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/331.prim_prince_test.34875594 Oct 09 02:13:10 AM UTC 24 Oct 09 02:13:33 AM UTC 24 858064723 ps
T303 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/288.prim_prince_test.96725948 Oct 09 02:12:26 AM UTC 24 Oct 09 02:13:34 AM UTC 24 2837822086 ps
T304 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/282.prim_prince_test.597188349 Oct 09 02:12:13 AM UTC 24 Oct 09 02:13:35 AM UTC 24 3491807158 ps
T305 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/278.prim_prince_test.3410000925 Oct 09 02:12:06 AM UTC 24 Oct 09 02:13:35 AM UTC 24 3514195828 ps
T306 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/308.prim_prince_test.3272702588 Oct 09 02:12:45 AM UTC 24 Oct 09 02:13:35 AM UTC 24 1942333972 ps
T307 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/338.prim_prince_test.975311203 Oct 09 02:13:14 AM UTC 24 Oct 09 02:13:36 AM UTC 24 834754167 ps
T308 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/339.prim_prince_test.2820779241 Oct 09 02:13:14 AM UTC 24 Oct 09 02:13:39 AM UTC 24 937183662 ps
T309 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/340.prim_prince_test.3834667455 Oct 09 02:13:15 AM UTC 24 Oct 09 02:13:41 AM UTC 24 1044142192 ps
T310 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/297.prim_prince_test.1029884146 Oct 09 02:12:34 AM UTC 24 Oct 09 02:13:41 AM UTC 24 2837473976 ps
T311 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/280.prim_prince_test.2880507787 Oct 09 02:12:10 AM UTC 24 Oct 09 02:13:44 AM UTC 24 3691252812 ps
T312 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/330.prim_prince_test.32233873 Oct 09 02:13:09 AM UTC 24 Oct 09 02:13:44 AM UTC 24 1373999148 ps
T313 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/286.prim_prince_test.2948611129 Oct 09 02:12:21 AM UTC 24 Oct 09 02:13:45 AM UTC 24 3516001355 ps
T314 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/344.prim_prince_test.1186937225 Oct 09 02:13:17 AM UTC 24 Oct 09 02:13:47 AM UTC 24 1179075241 ps
T315 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/313.prim_prince_test.2533577208 Oct 09 02:12:52 AM UTC 24 Oct 09 02:13:48 AM UTC 24 2184757420 ps
T316 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/320.prim_prince_test.3838616841 Oct 09 02:13:00 AM UTC 24 Oct 09 02:13:48 AM UTC 24 1907021603 ps
T317 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/319.prim_prince_test.2906549752 Oct 09 02:12:58 AM UTC 24 Oct 09 02:13:49 AM UTC 24 1973617889 ps
T318 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/318.prim_prince_test.1071041591 Oct 09 02:12:58 AM UTC 24 Oct 09 02:13:49 AM UTC 24 2117994237 ps
T319 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/298.prim_prince_test.3468059673 Oct 09 02:12:36 AM UTC 24 Oct 09 02:13:50 AM UTC 24 2921160719 ps
T320 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/296.prim_prince_test.2644607930 Oct 09 02:12:32 AM UTC 24 Oct 09 02:13:51 AM UTC 24 3156278336 ps
T321 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/291.prim_prince_test.1207762597 Oct 09 02:12:29 AM UTC 24 Oct 09 02:13:53 AM UTC 24 3385113473 ps
T322 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/323.prim_prince_test.2702677814 Oct 09 02:13:05 AM UTC 24 Oct 09 02:13:54 AM UTC 24 1959892475 ps
T323 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/342.prim_prince_test.3233578152 Oct 09 02:13:17 AM UTC 24 Oct 09 02:13:55 AM UTC 24 1495453504 ps
T324 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/321.prim_prince_test.2595779440 Oct 09 02:13:05 AM UTC 24 Oct 09 02:13:55 AM UTC 24 1982300333 ps
T325 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/355.prim_prince_test.1579602538 Oct 09 02:13:29 AM UTC 24 Oct 09 02:13:55 AM UTC 24 1038902601 ps
T326 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/322.prim_prince_test.3301343326 Oct 09 02:13:05 AM UTC 24 Oct 09 02:13:58 AM UTC 24 2099627616 ps
T327 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/337.prim_prince_test.1437811635 Oct 09 02:13:13 AM UTC 24 Oct 09 02:13:59 AM UTC 24 1878641998 ps
T328 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/317.prim_prince_test.866287093 Oct 09 02:12:57 AM UTC 24 Oct 09 02:14:02 AM UTC 24 2664955046 ps
T329 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/327.prim_prince_test.4240005332 Oct 09 02:13:07 AM UTC 24 Oct 09 02:14:02 AM UTC 24 2223301127 ps
T330 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/328.prim_prince_test.3986851314 Oct 09 02:13:08 AM UTC 24 Oct 09 02:14:03 AM UTC 24 2230587660 ps
T331 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/300.prim_prince_test.1492228464 Oct 09 02:12:37 AM UTC 24 Oct 09 02:14:03 AM UTC 24 3594943800 ps
T332 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/362.prim_prince_test.1672956294 Oct 09 02:13:36 AM UTC 24 Oct 09 02:14:03 AM UTC 24 1024940670 ps
T333 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/315.prim_prince_test.996016150 Oct 09 02:12:53 AM UTC 24 Oct 09 02:14:03 AM UTC 24 2894168565 ps
T334 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/348.prim_prince_test.1883017966 Oct 09 02:13:20 AM UTC 24 Oct 09 02:14:06 AM UTC 24 1812525130 ps
T335 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/305.prim_prince_test.804898684 Oct 09 02:12:44 AM UTC 24 Oct 09 02:14:07 AM UTC 24 3296771856 ps
T336 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/333.prim_prince_test.2023874143 Oct 09 02:13:12 AM UTC 24 Oct 09 02:14:09 AM UTC 24 2275659682 ps
T337 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/324.prim_prince_test.2933936610 Oct 09 02:13:05 AM UTC 24 Oct 09 02:14:09 AM UTC 24 2638202593 ps
T338 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/356.prim_prince_test.1845075071 Oct 09 02:13:32 AM UTC 24 Oct 09 02:14:09 AM UTC 24 1485030976 ps
T339 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/367.prim_prince_test.2607371339 Oct 09 02:13:45 AM UTC 24 Oct 09 02:14:10 AM UTC 24 955225690 ps
T340 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/336.prim_prince_test.216236208 Oct 09 02:13:12 AM UTC 24 Oct 09 02:14:10 AM UTC 24 2291356975 ps
T341 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/349.prim_prince_test.2993873060 Oct 09 02:13:21 AM UTC 24 Oct 09 02:14:11 AM UTC 24 1976108821 ps
T342 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/329.prim_prince_test.1435681830 Oct 09 02:13:09 AM UTC 24 Oct 09 02:14:12 AM UTC 24 2561358588 ps
T343 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/332.prim_prince_test.390123098 Oct 09 02:13:10 AM UTC 24 Oct 09 02:14:13 AM UTC 24 2614510811 ps
T344 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/350.prim_prince_test.2198598733 Oct 09 02:13:23 AM UTC 24 Oct 09 02:14:13 AM UTC 24 2001788889 ps
T345 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/310.prim_prince_test.4254808408 Oct 09 02:12:48 AM UTC 24 Oct 09 02:14:14 AM UTC 24 3389524120 ps
T346 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/306.prim_prince_test.241981267 Oct 09 02:12:44 AM UTC 24 Oct 09 02:14:14 AM UTC 24 3669734658 ps
T347 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/334.prim_prince_test.3362258321 Oct 09 02:13:12 AM UTC 24 Oct 09 02:14:16 AM UTC 24 2654362664 ps
T348 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/311.prim_prince_test.986332391 Oct 09 02:12:50 AM UTC 24 Oct 09 02:14:17 AM UTC 24 3564553943 ps
T349 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/351.prim_prince_test.3768820221 Oct 09 02:13:24 AM UTC 24 Oct 09 02:14:20 AM UTC 24 2243865511 ps
T350 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/363.prim_prince_test.1402088167 Oct 09 02:13:38 AM UTC 24 Oct 09 02:14:20 AM UTC 24 1666859116 ps
T351 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/341.prim_prince_test.1954320413 Oct 09 02:13:17 AM UTC 24 Oct 09 02:14:24 AM UTC 24 2763339160 ps
T352 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/375.prim_prince_test.2380793406 Oct 09 02:13:51 AM UTC 24 Oct 09 02:14:26 AM UTC 24 1300583496 ps
T353 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/369.prim_prince_test.2459258458 Oct 09 02:13:45 AM UTC 24 Oct 09 02:14:26 AM UTC 24 1572684789 ps
T354 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/358.prim_prince_test.4118472330 Oct 09 02:13:34 AM UTC 24 Oct 09 02:14:27 AM UTC 24 2195261258 ps
T355 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/366.prim_prince_test.1439551253 Oct 09 02:13:42 AM UTC 24 Oct 09 02:14:29 AM UTC 24 1922297692 ps
T356 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/335.prim_prince_test.2125434257 Oct 09 02:13:12 AM UTC 24 Oct 09 02:14:30 AM UTC 24 3226498021 ps
T357 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/357.prim_prince_test.1407617613 Oct 09 02:13:33 AM UTC 24 Oct 09 02:14:30 AM UTC 24 2357047760 ps
T358 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/381.prim_prince_test.1950354529 Oct 09 02:13:56 AM UTC 24 Oct 09 02:14:31 AM UTC 24 1300720658 ps
T359 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/353.prim_prince_test.1076324695 Oct 09 02:13:27 AM UTC 24 Oct 09 02:14:31 AM UTC 24 2530731945 ps
T360 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/386.prim_prince_test.680764394 Oct 09 02:14:04 AM UTC 24 Oct 09 02:14:31 AM UTC 24 994113538 ps
T361 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/387.prim_prince_test.2547344560 Oct 09 02:14:04 AM UTC 24 Oct 09 02:14:31 AM UTC 24 1008763791 ps
T362 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/345.prim_prince_test.2495920453 Oct 09 02:13:17 AM UTC 24 Oct 09 02:14:32 AM UTC 24 2960807433 ps
T363 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/325.prim_prince_test.4127550409 Oct 09 02:13:05 AM UTC 24 Oct 09 02:14:33 AM UTC 24 3574309658 ps
T364 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/368.prim_prince_test.3535659123 Oct 09 02:13:45 AM UTC 24 Oct 09 02:14:33 AM UTC 24 1912428539 ps
T365 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/365.prim_prince_test.3422396501 Oct 09 02:13:42 AM UTC 24 Oct 09 02:14:34 AM UTC 24 2109787399 ps
T366 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/346.prim_prince_test.311834128 Oct 09 02:13:17 AM UTC 24 Oct 09 02:14:35 AM UTC 24 3089592608 ps
T367 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/398.prim_prince_test.881002982 Oct 09 02:14:13 AM UTC 24 Oct 09 02:14:36 AM UTC 24 864192691 ps
T368 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/364.prim_prince_test.866928847 Oct 09 02:13:40 AM UTC 24 Oct 09 02:14:37 AM UTC 24 2310081602 ps
T369 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/402.prim_prince_test.3892499526 Oct 09 02:14:16 AM UTC 24 Oct 09 02:14:45 AM UTC 24 1126895799 ps
T370 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/372.prim_prince_test.216702145 Oct 09 02:13:49 AM UTC 24 Oct 09 02:14:46 AM UTC 24 2321561907 ps
T371 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/343.prim_prince_test.3325654271 Oct 09 02:13:17 AM UTC 24 Oct 09 02:14:47 AM UTC 24 3598495885 ps
T372 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/391.prim_prince_test.1250758989 Oct 09 02:14:09 AM UTC 24 Oct 09 02:14:48 AM UTC 24 1545342142 ps
T373 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/408.prim_prince_test.2561091110 Oct 09 02:14:27 AM UTC 24 Oct 09 02:14:49 AM UTC 24 819143852 ps
T374 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/370.prim_prince_test.106891466 Oct 09 02:13:49 AM UTC 24 Oct 09 02:14:51 AM UTC 24 2439497623 ps
T375 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/378.prim_prince_test.1988152425 Oct 09 02:13:56 AM UTC 24 Oct 09 02:14:51 AM UTC 24 2138772529 ps
T376 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/360.prim_prince_test.1169906613 Oct 09 02:13:36 AM UTC 24 Oct 09 02:14:52 AM UTC 24 3035936830 ps
T377 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/347.prim_prince_test.2143542984 Oct 09 02:13:18 AM UTC 24 Oct 09 02:14:52 AM UTC 24 3735499282 ps
T378 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/412.prim_prince_test.711062719 Oct 09 02:14:32 AM UTC 24 Oct 09 02:14:52 AM UTC 24 785870722 ps
T379 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/352.prim_prince_test.2961386420 Oct 09 02:13:24 AM UTC 24 Oct 09 02:14:53 AM UTC 24 3668481004 ps
T380 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/385.prim_prince_test.2121819631 Oct 09 02:14:04 AM UTC 24 Oct 09 02:14:53 AM UTC 24 1894165179 ps
T381 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/415.prim_prince_test.3114111625 Oct 09 02:14:32 AM UTC 24 Oct 09 02:14:53 AM UTC 24 795216267 ps
T382 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/361.prim_prince_test.844103409 Oct 09 02:13:36 AM UTC 24 Oct 09 02:14:54 AM UTC 24 3050479403 ps
T383 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/397.prim_prince_test.2894272167 Oct 09 02:14:13 AM UTC 24 Oct 09 02:14:55 AM UTC 24 1671640533 ps
T384 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/389.prim_prince_test.2652020521 Oct 09 02:14:04 AM UTC 24 Oct 09 02:14:55 AM UTC 24 2062021706 ps
T385 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/401.prim_prince_test.2472900645 Oct 09 02:14:16 AM UTC 24 Oct 09 02:14:57 AM UTC 24 1607328537 ps
T386 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/354.prim_prince_test.1086974425 Oct 09 02:13:28 AM UTC 24 Oct 09 02:14:57 AM UTC 24 3665966051 ps
T387 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/395.prim_prince_test.4007142949 Oct 09 02:14:10 AM UTC 24 Oct 09 02:15:00 AM UTC 24 1932895324 ps
T388 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/390.prim_prince_test.233988482 Oct 09 02:14:07 AM UTC 24 Oct 09 02:15:00 AM UTC 24 2085385651 ps
T389 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/409.prim_prince_test.2920407418 Oct 09 02:14:27 AM UTC 24 Oct 09 02:15:01 AM UTC 24 1315942151 ps
T390 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/376.prim_prince_test.1889978500 Oct 09 02:13:51 AM UTC 24 Oct 09 02:15:01 AM UTC 24 2808093903 ps
T391 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/416.prim_prince_test.3397718369 Oct 09 02:14:33 AM UTC 24 Oct 09 02:15:01 AM UTC 24 1107173665 ps
T392 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/371.prim_prince_test.1006453603 Oct 09 02:13:49 AM UTC 24 Oct 09 02:15:03 AM UTC 24 3012331636 ps
T393 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/359.prim_prince_test.1803815489 Oct 09 02:13:35 AM UTC 24 Oct 09 02:15:05 AM UTC 24 3710904010 ps
T394 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/411.prim_prince_test.1665366436 Oct 09 02:14:30 AM UTC 24 Oct 09 02:15:05 AM UTC 24 1409218961 ps
T395 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/373.prim_prince_test.3519115630 Oct 09 02:13:50 AM UTC 24 Oct 09 02:15:06 AM UTC 24 3013407164 ps
T396 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/377.prim_prince_test.2189013966 Oct 09 02:13:54 AM UTC 24 Oct 09 02:15:06 AM UTC 24 2948893817 ps
T397 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/382.prim_prince_test.687357499 Oct 09 02:13:58 AM UTC 24 Oct 09 02:15:09 AM UTC 24 2825787713 ps
T398 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/399.prim_prince_test.2394155795 Oct 09 02:14:14 AM UTC 24 Oct 09 02:15:10 AM UTC 24 2288349903 ps
T399 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/407.prim_prince_test.822684770 Oct 09 02:14:24 AM UTC 24 Oct 09 02:15:12 AM UTC 24 1907187271 ps
T400 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/374.prim_prince_test.93677575 Oct 09 02:13:50 AM UTC 24 Oct 09 02:15:16 AM UTC 24 3534923961 ps
T401 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/440.prim_prince_test.4189217962 Oct 09 02:14:56 AM UTC 24 Oct 09 02:15:16 AM UTC 24 796166213 ps
T402 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/406.prim_prince_test.3163845359 Oct 09 02:14:21 AM UTC 24 Oct 09 02:15:16 AM UTC 24 2239658271 ps
T403 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/431.prim_prince_test.1567180319 Oct 09 02:14:52 AM UTC 24 Oct 09 02:15:17 AM UTC 24 1002592894 ps
T404 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/379.prim_prince_test.4007879339 Oct 09 02:13:56 AM UTC 24 Oct 09 02:15:18 AM UTC 24 3278794085 ps
T405 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/429.prim_prince_test.2976991354 Oct 09 02:14:49 AM UTC 24 Oct 09 02:15:18 AM UTC 24 1153478627 ps
T406 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/380.prim_prince_test.48773613 Oct 09 02:13:56 AM UTC 24 Oct 09 02:15:19 AM UTC 24 3373133029 ps
T407 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/404.prim_prince_test.3336644657 Oct 09 02:14:18 AM UTC 24 Oct 09 02:15:19 AM UTC 24 2438793481 ps
T408 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/419.prim_prince_test.1934535924 Oct 09 02:14:35 AM UTC 24 Oct 09 02:15:19 AM UTC 24 1780383923 ps
T409 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/392.prim_prince_test.2740456578 Oct 09 02:14:10 AM UTC 24 Oct 09 02:15:20 AM UTC 24 2816630601 ps
T410 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/405.prim_prince_test.1691099164 Oct 09 02:14:21 AM UTC 24 Oct 09 02:15:20 AM UTC 24 2430377337 ps
T411 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/403.prim_prince_test.792057272 Oct 09 02:14:17 AM UTC 24 Oct 09 02:15:21 AM UTC 24 2594638919 ps
T412 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/384.prim_prince_test.3105650428 Oct 09 02:14:03 AM UTC 24 Oct 09 02:15:25 AM UTC 24 3331975760 ps
T413 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/396.prim_prince_test.1499776796 Oct 09 02:14:12 AM UTC 24 Oct 09 02:15:27 AM UTC 24 3047772439 ps
T414 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/445.prim_prince_test.2187824010 Oct 09 02:15:02 AM UTC 24 Oct 09 02:15:27 AM UTC 24 997080717 ps
T415 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/442.prim_prince_test.745998016 Oct 09 02:14:58 AM UTC 24 Oct 09 02:15:27 AM UTC 24 1174083195 ps
T416 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/383.prim_prince_test.2014497083 Oct 09 02:14:00 AM UTC 24 Oct 09 02:15:27 AM UTC 24 3534168993 ps
T417 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/444.prim_prince_test.4114469623 Oct 09 02:15:00 AM UTC 24 Oct 09 02:15:27 AM UTC 24 1084070595 ps
T418 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/410.prim_prince_test.1962314782 Oct 09 02:14:28 AM UTC 24 Oct 09 02:15:28 AM UTC 24 2420922845 ps
T419 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/394.prim_prince_test.1468693723 Oct 09 02:14:10 AM UTC 24 Oct 09 02:15:29 AM UTC 24 3216314597 ps
T420 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/422.prim_prince_test.4088301472 Oct 09 02:14:36 AM UTC 24 Oct 09 02:15:29 AM UTC 24 2174252479 ps
T421 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/435.prim_prince_test.189048076 Oct 09 02:14:54 AM UTC 24 Oct 09 02:15:30 AM UTC 24 1427034800 ps
T422 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/400.prim_prince_test.4216226176 Oct 09 02:14:14 AM UTC 24 Oct 09 02:15:31 AM UTC 24 3104829144 ps
T423 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/449.prim_prince_test.2798299988 Oct 09 02:15:05 AM UTC 24 Oct 09 02:15:31 AM UTC 24 1031406407 ps
T424 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/420.prim_prince_test.4037565055 Oct 09 02:14:35 AM UTC 24 Oct 09 02:15:34 AM UTC 24 2443633643 ps
T425 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/393.prim_prince_test.318745176 Oct 09 02:14:10 AM UTC 24 Oct 09 02:15:34 AM UTC 24 3413864566 ps
T426 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/454.prim_prince_test.873375709 Oct 09 02:15:11 AM UTC 24 Oct 09 02:15:35 AM UTC 24 982540910 ps
T427 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/388.prim_prince_test.276349387 Oct 09 02:14:04 AM UTC 24 Oct 09 02:15:36 AM UTC 24 3732050312 ps
T428 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/436.prim_prince_test.2118251800 Oct 09 02:14:54 AM UTC 24 Oct 09 02:15:36 AM UTC 24 1706919195 ps
T429 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/428.prim_prince_test.3131716481 Oct 09 02:14:49 AM UTC 24 Oct 09 02:15:37 AM UTC 24 1998742179 ps
T430 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/460.prim_prince_test.4095084114 Oct 09 02:15:18 AM UTC 24 Oct 09 02:15:38 AM UTC 24 770950582 ps
T431 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/456.prim_prince_test.2854312739 Oct 09 02:15:14 AM UTC 24 Oct 09 02:15:38 AM UTC 24 955120947 ps
T432 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/414.prim_prince_test.2636932554 Oct 09 02:14:32 AM UTC 24 Oct 09 02:15:40 AM UTC 24 2824503145 ps
T433 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/466.prim_prince_test.3860257518 Oct 09 02:15:21 AM UTC 24 Oct 09 02:15:41 AM UTC 24 762745332 ps
T434 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/417.prim_prince_test.544019045 Oct 09 02:14:33 AM UTC 24 Oct 09 02:15:41 AM UTC 24 2808175667 ps
T435 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/447.prim_prince_test.3421139935 Oct 09 02:15:02 AM UTC 24 Oct 09 02:15:41 AM UTC 24 1626215458 ps
T436 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/425.prim_prince_test.3706074181 Oct 09 02:14:47 AM UTC 24 Oct 09 02:15:42 AM UTC 24 2300460259 ps
T437 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/418.prim_prince_test.2083638926 Oct 09 02:14:33 AM UTC 24 Oct 09 02:15:43 AM UTC 24 2906500477 ps
T438 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/434.prim_prince_test.2963449932 Oct 09 02:14:54 AM UTC 24 Oct 09 02:15:44 AM UTC 24 2037432482 ps
T439 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/413.prim_prince_test.153096714 Oct 09 02:14:32 AM UTC 24 Oct 09 02:15:44 AM UTC 24 2994814706 ps
T440 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/441.prim_prince_test.2746753862 Oct 09 02:14:58 AM UTC 24 Oct 09 02:15:45 AM UTC 24 1932814152 ps
T441 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/457.prim_prince_test.3187899455 Oct 09 02:15:17 AM UTC 24 Oct 09 02:15:46 AM UTC 24 1155210783 ps
T442 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/423.prim_prince_test.3428891809 Oct 09 02:14:36 AM UTC 24 Oct 09 02:15:46 AM UTC 24 2883954465 ps
T443 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/463.prim_prince_test.1604717181 Oct 09 02:15:20 AM UTC 24 Oct 09 02:15:48 AM UTC 24 1149107761 ps
T444 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/427.prim_prince_test.3706427604 Oct 09 02:14:48 AM UTC 24 Oct 09 02:15:49 AM UTC 24 2546703895 ps
T445 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/448.prim_prince_test.4217765839 Oct 09 02:15:04 AM UTC 24 Oct 09 02:15:49 AM UTC 24 1873591903 ps
T446 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/433.prim_prince_test.2236145733 Oct 09 02:14:54 AM UTC 24 Oct 09 02:15:49 AM UTC 24 2271839079 ps
T447 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/473.prim_prince_test.2494484775 Oct 09 02:15:29 AM UTC 24 Oct 09 02:15:50 AM UTC 24 860039328 ps
T448 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/439.prim_prince_test.1929200822 Oct 09 02:14:56 AM UTC 24 Oct 09 02:15:56 AM UTC 24 2499012538 ps
T449 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/424.prim_prince_test.2211778490 Oct 09 02:14:38 AM UTC 24 Oct 09 02:15:57 AM UTC 24 3258513344 ps
T450 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/472.prim_prince_test.3310452081 Oct 09 02:15:29 AM UTC 24 Oct 09 02:15:57 AM UTC 24 1159171567 ps
T451 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/430.prim_prince_test.4259492750 Oct 09 02:14:52 AM UTC 24 Oct 09 02:15:58 AM UTC 24 2714875038 ps
T452 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/471.prim_prince_test.3827280648 Oct 09 02:15:28 AM UTC 24 Oct 09 02:15:58 AM UTC 24 1207343773 ps
T453 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/477.prim_prince_test.3422437761 Oct 09 02:15:30 AM UTC 24 Oct 09 02:15:59 AM UTC 24 1150530786 ps
T454 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/421.prim_prince_test.345321309 Oct 09 02:14:35 AM UTC 24 Oct 09 02:16:02 AM UTC 24 3601907862 ps
T455 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/458.prim_prince_test.3531612705 Oct 09 02:15:17 AM UTC 24 Oct 09 02:16:03 AM UTC 24 1890799261 ps
T456 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/452.prim_prince_test.151038772 Oct 09 02:15:08 AM UTC 24 Oct 09 02:16:04 AM UTC 24 2334428318 ps
T457 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/426.prim_prince_test.2201005397 Oct 09 02:14:47 AM UTC 24 Oct 09 02:16:05 AM UTC 24 3278829923 ps
T458 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/432.prim_prince_test.3371172002 Oct 09 02:14:54 AM UTC 24 Oct 09 02:16:05 AM UTC 24 2979368384 ps
T459 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/485.prim_prince_test.3836807419 Oct 09 02:15:37 AM UTC 24 Oct 09 02:16:05 AM UTC 24 1126721007 ps
T460 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/438.prim_prince_test.3648129241 Oct 09 02:14:56 AM UTC 24 Oct 09 02:16:06 AM UTC 24 2946157003 ps
T461 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/474.prim_prince_test.2490502301 Oct 09 02:15:29 AM UTC 24 Oct 09 02:16:07 AM UTC 24 1577171791 ps
T462 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/437.prim_prince_test.3243791872 Oct 09 02:14:54 AM UTC 24 Oct 09 02:16:08 AM UTC 24 3070828484 ps
T463 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/486.prim_prince_test.2988844884 Oct 09 02:15:39 AM UTC 24 Oct 09 02:16:11 AM UTC 24 1329311306 ps
T464 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/483.prim_prince_test.893070256 Oct 09 02:15:36 AM UTC 24 Oct 09 02:16:12 AM UTC 24 1460112928 ps
T465 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/462.prim_prince_test.469803105 Oct 09 02:15:20 AM UTC 24 Oct 09 02:16:15 AM UTC 24 2290127639 ps
T466 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/478.prim_prince_test.4169663768 Oct 09 02:15:30 AM UTC 24 Oct 09 02:16:18 AM UTC 24 1989261578 ps
T467 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/487.prim_prince_test.4201094110 Oct 09 02:15:39 AM UTC 24 Oct 09 02:16:18 AM UTC 24 1621738817 ps
T468 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/451.prim_prince_test.383954247 Oct 09 02:15:07 AM UTC 24 Oct 09 02:16:20 AM UTC 24 3069523604 ps
T469 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/476.prim_prince_test.2912454344 Oct 09 02:15:30 AM UTC 24 Oct 09 02:16:20 AM UTC 24 2063342238 ps
T470 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/446.prim_prince_test.1772540644 Oct 09 02:15:02 AM UTC 24 Oct 09 02:16:21 AM UTC 24 3305560342 ps
T471 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/490.prim_prince_test.622475278 Oct 09 02:15:41 AM UTC 24 Oct 09 02:16:22 AM UTC 24 1666714434 ps
T472 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/450.prim_prince_test.3672409277 Oct 09 02:15:07 AM UTC 24 Oct 09 02:16:23 AM UTC 24 3223124355 ps
T473 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/443.prim_prince_test.3763524765 Oct 09 02:15:00 AM UTC 24 Oct 09 02:16:23 AM UTC 24 3485230067 ps
T474 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/455.prim_prince_test.4064363524 Oct 09 02:15:13 AM UTC 24 Oct 09 02:16:25 AM UTC 24 3030973164 ps
T475 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/479.prim_prince_test.1598680037 Oct 09 02:15:31 AM UTC 24 Oct 09 02:16:26 AM UTC 24 2288877303 ps
T476 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/468.prim_prince_test.803235897 Oct 09 02:15:21 AM UTC 24 Oct 09 02:16:28 AM UTC 24 2788203234 ps
T477 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/465.prim_prince_test.2372171898 Oct 09 02:15:20 AM UTC 24 Oct 09 02:16:28 AM UTC 24 2852509072 ps
T478 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/469.prim_prince_test.2317633629 Oct 09 02:15:26 AM UTC 24 Oct 09 02:16:30 AM UTC 24 2722766449 ps
T479 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/464.prim_prince_test.2757739206 Oct 09 02:15:20 AM UTC 24 Oct 09 02:16:30 AM UTC 24 2963058451 ps
T480 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/489.prim_prince_test.196499783 Oct 09 02:15:41 AM UTC 24 Oct 09 02:16:33 AM UTC 24 2151066548 ps
T481 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/459.prim_prince_test.1558858678 Oct 09 02:15:18 AM UTC 24 Oct 09 02:16:35 AM UTC 24 3208885496 ps
T482 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/496.prim_prince_test.1049178098 Oct 09 02:15:46 AM UTC 24 Oct 09 02:16:35 AM UTC 24 2073648546 ps
T483 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/495.prim_prince_test.1491023554 Oct 09 02:15:44 AM UTC 24 Oct 09 02:16:38 AM UTC 24 2213430663 ps
T484 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/475.prim_prince_test.3635751909 Oct 09 02:15:29 AM UTC 24 Oct 09 02:16:39 AM UTC 24 2928823859 ps
T485 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/453.prim_prince_test.1666849722 Oct 09 02:15:10 AM UTC 24 Oct 09 02:16:39 AM UTC 24 3706305201 ps
T486 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/484.prim_prince_test.1099956713 Oct 09 02:15:37 AM UTC 24 Oct 09 02:16:40 AM UTC 24 2613131880 ps
T487 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/498.prim_prince_test.3942016602 Oct 09 02:15:47 AM UTC 24 Oct 09 02:16:42 AM UTC 24 2240559123 ps
T488 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/482.prim_prince_test.2330547772 Oct 09 02:15:35 AM UTC 24 Oct 09 02:16:43 AM UTC 24 2913619266 ps
T489 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/470.prim_prince_test.1805624465 Oct 09 02:15:28 AM UTC 24 Oct 09 02:16:44 AM UTC 24 3135327179 ps
T490 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/491.prim_prince_test.1029554669 Oct 09 02:15:43 AM UTC 24 Oct 09 02:16:45 AM UTC 24 2665583575 ps
T491 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/461.prim_prince_test.2008919435 Oct 09 02:15:20 AM UTC 24 Oct 09 02:16:47 AM UTC 24 3732420715 ps
T492 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/467.prim_prince_test.3076663602 Oct 09 02:15:21 AM UTC 24 Oct 09 02:16:47 AM UTC 24 3588948853 ps
T493 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/499.prim_prince_test.2966232036 Oct 09 02:15:47 AM UTC 24 Oct 09 02:16:51 AM UTC 24 2638393294 ps
T494 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/488.prim_prince_test.1243654334 Oct 09 02:15:39 AM UTC 24 Oct 09 02:16:51 AM UTC 24 3105497609 ps
T495 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/494.prim_prince_test.1295632701 Oct 09 02:15:44 AM UTC 24 Oct 09 02:16:52 AM UTC 24 2870432358 ps
T496 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/480.prim_prince_test.460145569 Oct 09 02:15:32 AM UTC 24 Oct 09 02:16:52 AM UTC 24 3442984896 ps
T497 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/481.prim_prince_test.2583024139 Oct 09 02:15:35 AM UTC 24 Oct 09 02:16:54 AM UTC 24 3250853552 ps
T498 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/493.prim_prince_test.3155628071 Oct 09 02:15:44 AM UTC 24 Oct 09 02:16:58 AM UTC 24 3170215951 ps
T499 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/492.prim_prince_test.3208845545 Oct 09 02:15:43 AM UTC 24 Oct 09 02:17:01 AM UTC 24 3398370710 ps
T500 /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/497.prim_prince_test.525774283 Oct 09 02:15:46 AM UTC 24 Oct 09 02:17:07 AM UTC 24 3489153274 ps

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/0.prim_prince_test.1209429032
Short name T1
Test name
Test status
Simulation time 795596447 ps
CPU time 12.1 seconds
Started Oct 09 02:07:22 AM UTC 24
Finished Oct 09 02:07:40 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1209429032 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 0.prim_prince_test.1209429032
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/0.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/1.prim_prince_test.2597725736
Short name T5
Test name
Test status
Simulation time 2243536387 ps
CPU time 33.68 seconds
Started Oct 09 02:07:22 AM UTC 24
Finished Oct 09 02:08:08 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2597725736 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 1.prim_prince_test.2597725736
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/1.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/10.prim_prince_test.3428499276
Short name T24
Test name
Test status
Simulation time 3015776236 ps
CPU time 50.73 seconds
Started Oct 09 02:07:34 AM UTC 24
Finished Oct 09 02:08:41 AM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3428499276 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 10.prim_prince_test.3428499276
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/10.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/100.prim_prince_test.56470208
Short name T107
Test name
Test status
Simulation time 2491273338 ps
CPU time 50.26 seconds
Started Oct 09 02:09:06 AM UTC 24
Finished Oct 09 02:10:10 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=56470208 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 100.prim_prince_test.56470208
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/100.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/101.prim_prince_test.315110706
Short name T103
Test name
Test status
Simulation time 2169300983 ps
CPU time 40.62 seconds
Started Oct 09 02:09:11 AM UTC 24
Finished Oct 09 02:10:04 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=315110706 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 101.prim_prince_test.315110706
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/101.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/102.prim_prince_test.2723004425
Short name T129
Test name
Test status
Simulation time 3394820405 ps
CPU time 65.91 seconds
Started Oct 09 02:09:12 AM UTC 24
Finished Oct 09 02:10:36 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2723004425 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 102.prim_prince_test.2723004425
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/102.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/103.prim_prince_test.298436497
Short name T82
Test name
Test status
Simulation time 958345436 ps
CPU time 19.59 seconds
Started Oct 09 02:09:14 AM UTC 24
Finished Oct 09 02:09:39 AM UTC 24
Peak memory 154968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=298436497 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 103.prim_prince_test.298436497
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/103.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/104.prim_prince_test.4292953310
Short name T119
Test name
Test status
Simulation time 2978224828 ps
CPU time 56.73 seconds
Started Oct 09 02:09:14 AM UTC 24
Finished Oct 09 02:10:27 AM UTC 24
Peak memory 154996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4292953310 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 104.prim_prince_test.4292953310
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/104.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/105.prim_prince_test.1717072640
Short name T87
Test name
Test status
Simulation time 1183034665 ps
CPU time 23.99 seconds
Started Oct 09 02:09:15 AM UTC 24
Finished Oct 09 02:09:45 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1717072640 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 105.prim_prince_test.1717072640
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/105.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/106.prim_prince_test.3885701993
Short name T106
Test name
Test status
Simulation time 1938118736 ps
CPU time 39.72 seconds
Started Oct 09 02:09:17 AM UTC 24
Finished Oct 09 02:10:07 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3885701993 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 106.prim_prince_test.3885701993
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/106.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/107.prim_prince_test.3897931916
Short name T137
Test name
Test status
Simulation time 3261936911 ps
CPU time 64.11 seconds
Started Oct 09 02:09:18 AM UTC 24
Finished Oct 09 02:10:39 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3897931916 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 107.prim_prince_test.3897931916
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/107.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/108.prim_prince_test.1497106126
Short name T81
Test name
Test status
Simulation time 761898450 ps
CPU time 15.72 seconds
Started Oct 09 02:09:18 AM UTC 24
Finished Oct 09 02:09:38 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1497106126 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 108.prim_prince_test.1497106126
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/108.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/109.prim_prince_test.2672705251
Short name T105
Test name
Test status
Simulation time 1806336976 ps
CPU time 36.82 seconds
Started Oct 09 02:09:19 AM UTC 24
Finished Oct 09 02:10:06 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2672705251 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 109.prim_prince_test.2672705251
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/109.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/11.prim_prince_test.1723910042
Short name T17
Test name
Test status
Simulation time 2791844521 ps
CPU time 46.76 seconds
Started Oct 09 02:07:34 AM UTC 24
Finished Oct 09 02:08:36 AM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1723910042 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 11.prim_prince_test.1723910042
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/11.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/110.prim_prince_test.3358154122
Short name T132
Test name
Test status
Simulation time 3259860666 ps
CPU time 61.72 seconds
Started Oct 09 02:09:19 AM UTC 24
Finished Oct 09 02:10:38 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3358154122 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 110.prim_prince_test.3358154122
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/110.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/111.prim_prince_test.2532128518
Short name T139
Test name
Test status
Simulation time 3282521204 ps
CPU time 67 seconds
Started Oct 09 02:09:20 AM UTC 24
Finished Oct 09 02:10:45 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2532128518 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 111.prim_prince_test.2532128518
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/111.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/112.prim_prince_test.3289390561
Short name T121
Test name
Test status
Simulation time 2634761096 ps
CPU time 54.02 seconds
Started Oct 09 02:09:20 AM UTC 24
Finished Oct 09 02:10:28 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3289390561 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 112.prim_prince_test.3289390561
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/112.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/113.prim_prince_test.3768439114
Short name T99
Test name
Test status
Simulation time 1553488656 ps
CPU time 31.97 seconds
Started Oct 09 02:09:21 AM UTC 24
Finished Oct 09 02:10:02 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3768439114 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 113.prim_prince_test.3768439114
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/113.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/114.prim_prince_test.3410757766
Short name T122
Test name
Test status
Simulation time 2802725427 ps
CPU time 54.01 seconds
Started Oct 09 02:09:21 AM UTC 24
Finished Oct 09 02:10:30 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3410757766 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 114.prim_prince_test.3410757766
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/114.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/115.prim_prince_test.66478907
Short name T88
Test name
Test status
Simulation time 879492838 ps
CPU time 18.26 seconds
Started Oct 09 02:09:22 AM UTC 24
Finished Oct 09 02:09:46 AM UTC 24
Peak memory 156336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=66478907 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 115.prim_prince_test.66478907
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/115.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/116.prim_prince_test.1705865155
Short name T131
Test name
Test status
Simulation time 2984138773 ps
CPU time 57.17 seconds
Started Oct 09 02:09:23 AM UTC 24
Finished Oct 09 02:10:37 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1705865155 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 116.prim_prince_test.1705865155
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/116.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/117.prim_prince_test.3864117069
Short name T138
Test name
Test status
Simulation time 3355105567 ps
CPU time 63.1 seconds
Started Oct 09 02:09:23 AM UTC 24
Finished Oct 09 02:10:45 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3864117069 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 117.prim_prince_test.3864117069
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/117.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/118.prim_prince_test.3831773940
Short name T142
Test name
Test status
Simulation time 3417576423 ps
CPU time 64.71 seconds
Started Oct 09 02:09:26 AM UTC 24
Finished Oct 09 02:10:50 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3831773940 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 118.prim_prince_test.3831773940
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/118.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/119.prim_prince_test.1671498627
Short name T91
Test name
Test status
Simulation time 959802990 ps
CPU time 18.33 seconds
Started Oct 09 02:09:27 AM UTC 24
Finished Oct 09 02:09:51 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1671498627 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 119.prim_prince_test.1671498627
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/119.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/12.prim_prince_test.2356982647
Short name T30
Test name
Test status
Simulation time 2886583652 ps
CPU time 51.45 seconds
Started Oct 09 02:07:39 AM UTC 24
Finished Oct 09 02:08:45 AM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2356982647 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 12.prim_prince_test.2356982647
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/12.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/120.prim_prince_test.2350563506
Short name T127
Test name
Test status
Simulation time 2597029809 ps
CPU time 53.49 seconds
Started Oct 09 02:09:27 AM UTC 24
Finished Oct 09 02:10:34 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2350563506 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 120.prim_prince_test.2350563506
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/120.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/121.prim_prince_test.3178967097
Short name T152
Test name
Test status
Simulation time 3625545121 ps
CPU time 74.11 seconds
Started Oct 09 02:09:27 AM UTC 24
Finished Oct 09 02:11:00 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3178967097 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 121.prim_prince_test.3178967097
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/121.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/122.prim_prince_test.3953014327
Short name T136
Test name
Test status
Simulation time 2762538341 ps
CPU time 57.13 seconds
Started Oct 09 02:09:27 AM UTC 24
Finished Oct 09 02:10:39 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3953014327 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 122.prim_prince_test.3953014327
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/122.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/123.prim_prince_test.2517395185
Short name T90
Test name
Test status
Simulation time 766401535 ps
CPU time 16.33 seconds
Started Oct 09 02:09:29 AM UTC 24
Finished Oct 09 02:09:50 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2517395185 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 123.prim_prince_test.2517395185
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/123.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/124.prim_prince_test.3447032627
Short name T146
Test name
Test status
Simulation time 3325541935 ps
CPU time 65.77 seconds
Started Oct 09 02:09:29 AM UTC 24
Finished Oct 09 02:10:52 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3447032627 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 124.prim_prince_test.3447032627
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/124.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/125.prim_prince_test.3376196611
Short name T141
Test name
Test status
Simulation time 3205834382 ps
CPU time 60.14 seconds
Started Oct 09 02:09:31 AM UTC 24
Finished Oct 09 02:10:48 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3376196611 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 125.prim_prince_test.3376196611
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/125.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/126.prim_prince_test.4106065139
Short name T111
Test name
Test status
Simulation time 1625635547 ps
CPU time 33.62 seconds
Started Oct 09 02:09:32 AM UTC 24
Finished Oct 09 02:10:15 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4106065139 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 126.prim_prince_test.4106065139
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/126.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/127.prim_prince_test.2903955474
Short name T100
Test name
Test status
Simulation time 1100470704 ps
CPU time 22.92 seconds
Started Oct 09 02:09:33 AM UTC 24
Finished Oct 09 02:10:03 AM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2903955474 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 127.prim_prince_test.2903955474
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/127.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/128.prim_prince_test.1444260063
Short name T135
Test name
Test status
Simulation time 2691457324 ps
CPU time 50.63 seconds
Started Oct 09 02:09:33 AM UTC 24
Finished Oct 09 02:10:39 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1444260063 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 128.prim_prince_test.1444260063
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/128.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/129.prim_prince_test.266718909
Short name T110
Test name
Test status
Simulation time 1502437206 ps
CPU time 31.4 seconds
Started Oct 09 02:09:33 AM UTC 24
Finished Oct 09 02:10:13 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=266718909 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 129.prim_prince_test.266718909
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/129.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/13.prim_prince_test.1679564516
Short name T44
Test name
Test status
Simulation time 3639349607 ps
CPU time 65.88 seconds
Started Oct 09 02:07:39 AM UTC 24
Finished Oct 09 02:09:04 AM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1679564516 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 13.prim_prince_test.1679564516
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/13.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/130.prim_prince_test.2133824447
Short name T114
Test name
Test status
Simulation time 1830785450 ps
CPU time 35.26 seconds
Started Oct 09 02:09:33 AM UTC 24
Finished Oct 09 02:10:19 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2133824447 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 130.prim_prince_test.2133824447
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/130.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/131.prim_prince_test.3764234027
Short name T96
Test name
Test status
Simulation time 1030143106 ps
CPU time 21.37 seconds
Started Oct 09 02:09:33 AM UTC 24
Finished Oct 09 02:10:01 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3764234027 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 131.prim_prince_test.3764234027
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/131.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/132.prim_prince_test.3760707497
Short name T123
Test name
Test status
Simulation time 2173762093 ps
CPU time 44.81 seconds
Started Oct 09 02:09:35 AM UTC 24
Finished Oct 09 02:10:32 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3760707497 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 132.prim_prince_test.3760707497
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/132.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/133.prim_prince_test.35273916
Short name T124
Test name
Test status
Simulation time 2183204529 ps
CPU time 44.25 seconds
Started Oct 09 02:09:37 AM UTC 24
Finished Oct 09 02:10:33 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=35273916 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 133.prim_prince_test.35273916
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/133.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/134.prim_prince_test.1105397419
Short name T108
Test name
Test status
Simulation time 1320424570 ps
CPU time 25.54 seconds
Started Oct 09 02:09:39 AM UTC 24
Finished Oct 09 02:10:12 AM UTC 24
Peak memory 154944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1105397419 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 134.prim_prince_test.1105397419
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/134.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/135.prim_prince_test.3620430027
Short name T165
Test name
Test status
Simulation time 3614571236 ps
CPU time 72.19 seconds
Started Oct 09 02:09:39 AM UTC 24
Finished Oct 09 02:11:10 AM UTC 24
Peak memory 154996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3620430027 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 135.prim_prince_test.3620430027
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/135.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/136.prim_prince_test.2387602131
Short name T157
Test name
Test status
Simulation time 3508461974 ps
CPU time 65.42 seconds
Started Oct 09 02:09:40 AM UTC 24
Finished Oct 09 02:11:04 AM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2387602131 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 136.prim_prince_test.2387602131
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/136.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/137.prim_prince_test.1687211876
Short name T162
Test name
Test status
Simulation time 3452232325 ps
CPU time 66.36 seconds
Started Oct 09 02:09:42 AM UTC 24
Finished Oct 09 02:11:07 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1687211876 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 137.prim_prince_test.1687211876
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/137.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/138.prim_prince_test.3085838979
Short name T155
Test name
Test status
Simulation time 3264253414 ps
CPU time 61.04 seconds
Started Oct 09 02:09:43 AM UTC 24
Finished Oct 09 02:11:02 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3085838979 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 138.prim_prince_test.3085838979
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/138.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/139.prim_prince_test.1585755082
Short name T144
Test name
Test status
Simulation time 2707314161 ps
CPU time 52.15 seconds
Started Oct 09 02:09:45 AM UTC 24
Finished Oct 09 02:10:52 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1585755082 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 139.prim_prince_test.1585755082
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/139.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/14.prim_prince_test.3594688996
Short name T8
Test name
Test status
Simulation time 1862149457 ps
CPU time 30.29 seconds
Started Oct 09 02:07:41 AM UTC 24
Finished Oct 09 02:08:21 AM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3594688996 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 14.prim_prince_test.3594688996
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/14.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/140.prim_prince_test.2730508854
Short name T173
Test name
Test status
Simulation time 3681602395 ps
CPU time 74.78 seconds
Started Oct 09 02:09:45 AM UTC 24
Finished Oct 09 02:11:19 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2730508854 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 140.prim_prince_test.2730508854
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/140.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/141.prim_prince_test.1127977095
Short name T149
Test name
Test status
Simulation time 2911953100 ps
CPU time 55.08 seconds
Started Oct 09 02:09:46 AM UTC 24
Finished Oct 09 02:10:57 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1127977095 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 141.prim_prince_test.1127977095
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/141.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/142.prim_prince_test.378317842
Short name T128
Test name
Test status
Simulation time 1866926781 ps
CPU time 38.4 seconds
Started Oct 09 02:09:46 AM UTC 24
Finished Oct 09 02:10:35 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=378317842 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 142.prim_prince_test.378317842
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/142.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/143.prim_prince_test.1504393851
Short name T176
Test name
Test status
Simulation time 3704941169 ps
CPU time 74.54 seconds
Started Oct 09 02:09:48 AM UTC 24
Finished Oct 09 02:11:22 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1504393851 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 143.prim_prince_test.1504393851
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/143.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/144.prim_prince_test.2374689602
Short name T143
Test name
Test status
Simulation time 2470030351 ps
CPU time 47.14 seconds
Started Oct 09 02:09:50 AM UTC 24
Finished Oct 09 02:10:51 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2374689602 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 144.prim_prince_test.2374689602
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/144.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/145.prim_prince_test.3238170715
Short name T113
Test name
Test status
Simulation time 982324158 ps
CPU time 19.16 seconds
Started Oct 09 02:09:52 AM UTC 24
Finished Oct 09 02:10:17 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3238170715 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 145.prim_prince_test.3238170715
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/145.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/146.prim_prince_test.1242224133
Short name T175
Test name
Test status
Simulation time 3551780429 ps
CPU time 70.47 seconds
Started Oct 09 02:09:53 AM UTC 24
Finished Oct 09 02:11:22 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1242224133 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 146.prim_prince_test.1242224133
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/146.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/147.prim_prince_test.1702794005
Short name T153
Test name
Test status
Simulation time 2555761345 ps
CPU time 48.39 seconds
Started Oct 09 02:09:58 AM UTC 24
Finished Oct 09 02:11:00 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1702794005 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 147.prim_prince_test.1702794005
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/147.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/148.prim_prince_test.532244023
Short name T177
Test name
Test status
Simulation time 3355402610 ps
CPU time 66.83 seconds
Started Oct 09 02:09:58 AM UTC 24
Finished Oct 09 02:11:22 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=532244023 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 148.prim_prince_test.532244023
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/148.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/149.prim_prince_test.119537583
Short name T133
Test name
Test status
Simulation time 1449271244 ps
CPU time 30.05 seconds
Started Oct 09 02:10:00 AM UTC 24
Finished Oct 09 02:10:38 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=119537583 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 149.prim_prince_test.119537583
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/149.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/15.prim_prince_test.2713606824
Short name T26
Test name
Test status
Simulation time 2626812656 ps
CPU time 47.18 seconds
Started Oct 09 02:07:42 AM UTC 24
Finished Oct 09 02:08:43 AM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2713606824 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 15.prim_prince_test.2713606824
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/15.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/150.prim_prince_test.3234653513
Short name T179
Test name
Test status
Simulation time 3389762731 ps
CPU time 63.42 seconds
Started Oct 09 02:10:02 AM UTC 24
Finished Oct 09 02:11:24 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3234653513 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 150.prim_prince_test.3234653513
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/150.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/151.prim_prince_test.3145609334
Short name T171
Test name
Test status
Simulation time 2856121944 ps
CPU time 57.62 seconds
Started Oct 09 02:10:02 AM UTC 24
Finished Oct 09 02:11:15 AM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3145609334 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 151.prim_prince_test.3145609334
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/151.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/152.prim_prince_test.1966632363
Short name T154
Test name
Test status
Simulation time 2423203362 ps
CPU time 45.87 seconds
Started Oct 09 02:10:02 AM UTC 24
Finished Oct 09 02:11:01 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1966632363 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 152.prim_prince_test.1966632363
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/152.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/153.prim_prince_test.2245263590
Short name T126
Test name
Test status
Simulation time 1211735886 ps
CPU time 23.3 seconds
Started Oct 09 02:10:03 AM UTC 24
Finished Oct 09 02:10:34 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2245263590 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 153.prim_prince_test.2245263590
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/153.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/154.prim_prince_test.3061986303
Short name T164
Test name
Test status
Simulation time 2537219140 ps
CPU time 50.01 seconds
Started Oct 09 02:10:03 AM UTC 24
Finished Oct 09 02:11:07 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3061986303 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 154.prim_prince_test.3061986303
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/154.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/155.prim_prince_test.2321955490
Short name T159
Test name
Test status
Simulation time 2494834354 ps
CPU time 47.2 seconds
Started Oct 09 02:10:03 AM UTC 24
Finished Oct 09 02:11:04 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2321955490 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 155.prim_prince_test.2321955490
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/155.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/156.prim_prince_test.2652140334
Short name T125
Test name
Test status
Simulation time 1126523855 ps
CPU time 23.39 seconds
Started Oct 09 02:10:03 AM UTC 24
Finished Oct 09 02:10:34 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2652140334 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 156.prim_prince_test.2652140334
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/156.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/157.prim_prince_test.1826992994
Short name T120
Test name
Test status
Simulation time 853684780 ps
CPU time 17.97 seconds
Started Oct 09 02:10:05 AM UTC 24
Finished Oct 09 02:10:28 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1826992994 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 157.prim_prince_test.1826992994
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/157.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/158.prim_prince_test.807270674
Short name T180
Test name
Test status
Simulation time 3220339608 ps
CPU time 62.21 seconds
Started Oct 09 02:10:06 AM UTC 24
Finished Oct 09 02:11:25 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=807270674 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 158.prim_prince_test.807270674
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/158.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/159.prim_prince_test.1141884601
Short name T163
Test name
Test status
Simulation time 2478304591 ps
CPU time 46.55 seconds
Started Oct 09 02:10:07 AM UTC 24
Finished Oct 09 02:11:07 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1141884601 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 159.prim_prince_test.1141884601
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/159.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/16.prim_prince_test.1113540863
Short name T9
Test name
Test status
Simulation time 1224054003 ps
CPU time 22.82 seconds
Started Oct 09 02:07:53 AM UTC 24
Finished Oct 09 02:08:23 AM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1113540863 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 16.prim_prince_test.1113540863
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/16.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/160.prim_prince_test.3620482452
Short name T134
Test name
Test status
Simulation time 1144041692 ps
CPU time 23.58 seconds
Started Oct 09 02:10:08 AM UTC 24
Finished Oct 09 02:10:38 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3620482452 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 160.prim_prince_test.3620482452
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/160.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/161.prim_prince_test.1109897411
Short name T169
Test name
Test status
Simulation time 2500786271 ps
CPU time 50.48 seconds
Started Oct 09 02:10:11 AM UTC 24
Finished Oct 09 02:11:15 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1109897411 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 161.prim_prince_test.1109897411
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/161.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/162.prim_prince_test.1108162562
Short name T151
Test name
Test status
Simulation time 1803138605 ps
CPU time 35.75 seconds
Started Oct 09 02:10:13 AM UTC 24
Finished Oct 09 02:10:59 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1108162562 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 162.prim_prince_test.1108162562
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/162.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/163.prim_prince_test.1689929388
Short name T130
Test name
Test status
Simulation time 861041275 ps
CPU time 17.82 seconds
Started Oct 09 02:10:13 AM UTC 24
Finished Oct 09 02:10:36 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1689929388 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 163.prim_prince_test.1689929388
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/163.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/164.prim_prince_test.2030311360
Short name T148
Test name
Test status
Simulation time 1612584338 ps
CPU time 33.34 seconds
Started Oct 09 02:10:13 AM UTC 24
Finished Oct 09 02:10:56 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2030311360 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 164.prim_prince_test.2030311360
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/164.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/165.prim_prince_test.1089619184
Short name T170
Test name
Test status
Simulation time 2368113873 ps
CPU time 47.62 seconds
Started Oct 09 02:10:14 AM UTC 24
Finished Oct 09 02:11:15 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1089619184 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 165.prim_prince_test.1089619184
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/165.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/166.prim_prince_test.1578947756
Short name T191
Test name
Test status
Simulation time 3520257977 ps
CPU time 68.8 seconds
Started Oct 09 02:10:16 AM UTC 24
Finished Oct 09 02:11:44 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1578947756 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 166.prim_prince_test.1578947756
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/166.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/167.prim_prince_test.1402713689
Short name T166
Test name
Test status
Simulation time 2052065562 ps
CPU time 41.83 seconds
Started Oct 09 02:10:17 AM UTC 24
Finished Oct 09 02:11:11 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1402713689 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 167.prim_prince_test.1402713689
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/167.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/168.prim_prince_test.1317100850
Short name T184
Test name
Test status
Simulation time 3022095801 ps
CPU time 58.22 seconds
Started Oct 09 02:10:18 AM UTC 24
Finished Oct 09 02:11:32 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1317100850 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 168.prim_prince_test.1317100850
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/168.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/169.prim_prince_test.3022150362
Short name T210
Test name
Test status
Simulation time 3721065578 ps
CPU time 74.43 seconds
Started Oct 09 02:10:20 AM UTC 24
Finished Oct 09 02:11:54 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3022150362 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 169.prim_prince_test.3022150362
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/169.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/17.prim_prince_test.2545999733
Short name T39
Test name
Test status
Simulation time 2617225659 ps
CPU time 48.07 seconds
Started Oct 09 02:07:56 AM UTC 24
Finished Oct 09 02:08:58 AM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2545999733 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 17.prim_prince_test.2545999733
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/17.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/170.prim_prince_test.3737146900
Short name T158
Test name
Test status
Simulation time 1935078989 ps
CPU time 38.15 seconds
Started Oct 09 02:10:23 AM UTC 24
Finished Oct 09 02:11:12 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3737146900 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 170.prim_prince_test.3737146900
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/170.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/171.prim_prince_test.241428831
Short name T140
Test name
Test status
Simulation time 758181392 ps
CPU time 14.86 seconds
Started Oct 09 02:10:25 AM UTC 24
Finished Oct 09 02:10:45 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=241428831 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 171.prim_prince_test.241428831
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/171.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/172.prim_prince_test.3732984165
Short name T147
Test name
Test status
Simulation time 999595236 ps
CPU time 20.93 seconds
Started Oct 09 02:10:26 AM UTC 24
Finished Oct 09 02:10:53 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3732984165 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 172.prim_prince_test.3732984165
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/172.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/173.prim_prince_test.3907673009
Short name T197
Test name
Test status
Simulation time 3272498368 ps
CPU time 62.07 seconds
Started Oct 09 02:10:26 AM UTC 24
Finished Oct 09 02:11:46 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3907673009 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 173.prim_prince_test.3907673009
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/173.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/174.prim_prince_test.4100448618
Short name T206
Test name
Test status
Simulation time 3450802048 ps
CPU time 66.16 seconds
Started Oct 09 02:10:27 AM UTC 24
Finished Oct 09 02:11:52 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4100448618 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 174.prim_prince_test.4100448618
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/174.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/175.prim_prince_test.4174086898
Short name T145
Test name
Test status
Simulation time 873761399 ps
CPU time 18.49 seconds
Started Oct 09 02:10:28 AM UTC 24
Finished Oct 09 02:10:52 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4174086898 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 175.prim_prince_test.4174086898
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/175.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/176.prim_prince_test.2936565930
Short name T160
Test name
Test status
Simulation time 1387856416 ps
CPU time 28.34 seconds
Started Oct 09 02:10:29 AM UTC 24
Finished Oct 09 02:11:06 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2936565930 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 176.prim_prince_test.2936565930
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/176.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/177.prim_prince_test.1983289280
Short name T199
Test name
Test status
Simulation time 3220414751 ps
CPU time 59.06 seconds
Started Oct 09 02:10:31 AM UTC 24
Finished Oct 09 02:11:48 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1983289280 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 177.prim_prince_test.1983289280
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/177.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/178.prim_prince_test.227098813
Short name T193
Test name
Test status
Simulation time 3009875573 ps
CPU time 55.5 seconds
Started Oct 09 02:10:33 AM UTC 24
Finished Oct 09 02:11:45 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=227098813 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 178.prim_prince_test.227098813
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/178.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/179.prim_prince_test.1008645270
Short name T213
Test name
Test status
Simulation time 3266450744 ps
CPU time 64.96 seconds
Started Oct 09 02:10:34 AM UTC 24
Finished Oct 09 02:11:56 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1008645270 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 179.prim_prince_test.1008645270
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/179.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/18.prim_prince_test.3602367131
Short name T16
Test name
Test status
Simulation time 1590923155 ps
CPU time 30.15 seconds
Started Oct 09 02:07:56 AM UTC 24
Finished Oct 09 02:08:35 AM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3602367131 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 18.prim_prince_test.3602367131
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/18.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/180.prim_prince_test.3540387943
Short name T214
Test name
Test status
Simulation time 3270974672 ps
CPU time 64.84 seconds
Started Oct 09 02:10:35 AM UTC 24
Finished Oct 09 02:11:57 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3540387943 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 180.prim_prince_test.3540387943
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/180.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/181.prim_prince_test.4043352951
Short name T172
Test name
Test status
Simulation time 1668496803 ps
CPU time 30.8 seconds
Started Oct 09 02:10:35 AM UTC 24
Finished Oct 09 02:11:15 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4043352951 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 181.prim_prince_test.4043352951
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/181.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/182.prim_prince_test.1690545920
Short name T181
Test name
Test status
Simulation time 2195640545 ps
CPU time 40.49 seconds
Started Oct 09 02:10:35 AM UTC 24
Finished Oct 09 02:11:27 AM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1690545920 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 182.prim_prince_test.1690545920
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/182.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/183.prim_prince_test.1260271561
Short name T201
Test name
Test status
Simulation time 2901972477 ps
CPU time 57.59 seconds
Started Oct 09 02:10:36 AM UTC 24
Finished Oct 09 02:11:49 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1260271561 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 183.prim_prince_test.1260271561
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/183.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/184.prim_prince_test.3897318483
Short name T205
Test name
Test status
Simulation time 2971937857 ps
CPU time 58.55 seconds
Started Oct 09 02:10:37 AM UTC 24
Finished Oct 09 02:11:51 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3897318483 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 184.prim_prince_test.3897318483
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/184.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/185.prim_prince_test.1442664215
Short name T150
Test name
Test status
Simulation time 786089856 ps
CPU time 15.58 seconds
Started Oct 09 02:10:37 AM UTC 24
Finished Oct 09 02:10:58 AM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1442664215 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 185.prim_prince_test.1442664215
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/185.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/186.prim_prince_test.1459856721
Short name T156
Test name
Test status
Simulation time 944203474 ps
CPU time 19 seconds
Started Oct 09 02:10:37 AM UTC 24
Finished Oct 09 02:11:02 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1459856721 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 186.prim_prince_test.1459856721
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/186.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/187.prim_prince_test.1182891985
Short name T189
Test name
Test status
Simulation time 2647224227 ps
CPU time 49.16 seconds
Started Oct 09 02:10:40 AM UTC 24
Finished Oct 09 02:11:43 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1182891985 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 187.prim_prince_test.1182891985
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/187.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/188.prim_prince_test.1919674672
Short name T167
Test name
Test status
Simulation time 1275274215 ps
CPU time 24.15 seconds
Started Oct 09 02:10:40 AM UTC 24
Finished Oct 09 02:11:11 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1919674672 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 188.prim_prince_test.1919674672
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/188.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/189.prim_prince_test.1774989405
Short name T212
Test name
Test status
Simulation time 3069635916 ps
CPU time 58.99 seconds
Started Oct 09 02:10:40 AM UTC 24
Finished Oct 09 02:11:55 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1774989405 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 189.prim_prince_test.1774989405
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/189.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/19.prim_prince_test.4093163105
Short name T67
Test name
Test status
Simulation time 3674384877 ps
CPU time 69.99 seconds
Started Oct 09 02:07:57 AM UTC 24
Finished Oct 09 02:09:26 AM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4093163105 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 19.prim_prince_test.4093163105
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/19.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/190.prim_prince_test.1907852962
Short name T228
Test name
Test status
Simulation time 3700489185 ps
CPU time 73.11 seconds
Started Oct 09 02:10:40 AM UTC 24
Finished Oct 09 02:12:12 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1907852962 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 190.prim_prince_test.1907852962
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/190.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/191.prim_prince_test.2604177890
Short name T188
Test name
Test status
Simulation time 2509667196 ps
CPU time 49.25 seconds
Started Oct 09 02:10:40 AM UTC 24
Finished Oct 09 02:11:43 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2604177890 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 191.prim_prince_test.2604177890
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/191.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/192.prim_prince_test.2868723075
Short name T186
Test name
Test status
Simulation time 2343921422 ps
CPU time 45.11 seconds
Started Oct 09 02:10:41 AM UTC 24
Finished Oct 09 02:11:39 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2868723075 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 192.prim_prince_test.2868723075
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/192.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/193.prim_prince_test.307283368
Short name T161
Test name
Test status
Simulation time 797400074 ps
CPU time 16.09 seconds
Started Oct 09 02:10:45 AM UTC 24
Finished Oct 09 02:11:06 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=307283368 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 193.prim_prince_test.307283368
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/193.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/194.prim_prince_test.1777518340
Short name T196
Test name
Test status
Simulation time 2403621229 ps
CPU time 46.88 seconds
Started Oct 09 02:10:45 AM UTC 24
Finished Oct 09 02:11:45 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1777518340 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 194.prim_prince_test.1777518340
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/194.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/195.prim_prince_test.25054173
Short name T168
Test name
Test status
Simulation time 1023043905 ps
CPU time 20.25 seconds
Started Oct 09 02:10:46 AM UTC 24
Finished Oct 09 02:11:12 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25054173 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 195.prim_prince_test.25054173
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/195.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/196.prim_prince_test.31960661
Short name T185
Test name
Test status
Simulation time 1866878185 ps
CPU time 34.36 seconds
Started Oct 09 02:10:49 AM UTC 24
Finished Oct 09 02:11:34 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31960661 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 196.prim_prince_test.31960661
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/196.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/197.prim_prince_test.2987331685
Short name T178
Test name
Test status
Simulation time 1272350425 ps
CPU time 25.26 seconds
Started Oct 09 02:10:50 AM UTC 24
Finished Oct 09 02:11:23 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2987331685 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 197.prim_prince_test.2987331685
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/197.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/198.prim_prince_test.3548274704
Short name T183
Test name
Test status
Simulation time 1618250504 ps
CPU time 30.11 seconds
Started Oct 09 02:10:53 AM UTC 24
Finished Oct 09 02:11:32 AM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3548274704 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 198.prim_prince_test.3548274704
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/198.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/199.prim_prince_test.4150303385
Short name T190
Test name
Test status
Simulation time 1966573315 ps
CPU time 39.08 seconds
Started Oct 09 02:10:54 AM UTC 24
Finished Oct 09 02:11:43 AM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4150303385 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 199.prim_prince_test.4150303385
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/199.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/2.prim_prince_test.3598088990
Short name T3
Test name
Test status
Simulation time 1451320659 ps
CPU time 21.78 seconds
Started Oct 09 02:07:24 AM UTC 24
Finished Oct 09 02:07:55 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3598088990 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 2.prim_prince_test.3598088990
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/2.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/20.prim_prince_test.2308079632
Short name T21
Test name
Test status
Simulation time 1719651451 ps
CPU time 31.3 seconds
Started Oct 09 02:07:57 AM UTC 24
Finished Oct 09 02:08:38 AM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2308079632 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 20.prim_prince_test.2308079632
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/20.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/200.prim_prince_test.3115368893
Short name T222
Test name
Test status
Simulation time 2881127474 ps
CPU time 53.1 seconds
Started Oct 09 02:10:54 AM UTC 24
Finished Oct 09 02:12:02 AM UTC 24
Peak memory 155000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3115368893 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 200.prim_prince_test.3115368893
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/200.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/201.prim_prince_test.820957387
Short name T211
Test name
Test status
Simulation time 2511609453 ps
CPU time 46.97 seconds
Started Oct 09 02:10:54 AM UTC 24
Finished Oct 09 02:11:54 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=820957387 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 201.prim_prince_test.820957387
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/201.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/202.prim_prince_test.55951132
Short name T217
Test name
Test status
Simulation time 2557493429 ps
CPU time 50.55 seconds
Started Oct 09 02:10:54 AM UTC 24
Finished Oct 09 02:11:58 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=55951132 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 202.prim_prince_test.55951132
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/202.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/203.prim_prince_test.3943614683
Short name T221
Test name
Test status
Simulation time 2728675220 ps
CPU time 50.4 seconds
Started Oct 09 02:10:56 AM UTC 24
Finished Oct 09 02:12:01 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3943614683 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 203.prim_prince_test.3943614683
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/203.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/204.prim_prince_test.1141923958
Short name T208
Test name
Test status
Simulation time 2273402468 ps
CPU time 42.44 seconds
Started Oct 09 02:10:58 AM UTC 24
Finished Oct 09 02:11:53 AM UTC 24
Peak memory 155032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1141923958 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 204.prim_prince_test.1141923958
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/204.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/205.prim_prince_test.3318685658
Short name T174
Test name
Test status
Simulation time 892346203 ps
CPU time 17.07 seconds
Started Oct 09 02:10:59 AM UTC 24
Finished Oct 09 02:11:22 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3318685658 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 205.prim_prince_test.3318685658
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/205.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/206.prim_prince_test.2384619672
Short name T209
Test name
Test status
Simulation time 2158570147 ps
CPU time 42.15 seconds
Started Oct 09 02:10:59 AM UTC 24
Finished Oct 09 02:11:53 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2384619672 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 206.prim_prince_test.2384619672
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/206.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/207.prim_prince_test.3631399487
Short name T194
Test name
Test status
Simulation time 1897459151 ps
CPU time 35.03 seconds
Started Oct 09 02:10:59 AM UTC 24
Finished Oct 09 02:11:45 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3631399487 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 207.prim_prince_test.3631399487
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/207.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/208.prim_prince_test.421242998
Short name T230
Test name
Test status
Simulation time 3071406349 ps
CPU time 61.6 seconds
Started Oct 09 02:11:00 AM UTC 24
Finished Oct 09 02:12:18 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=421242998 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 208.prim_prince_test.421242998
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/208.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/209.prim_prince_test.1899394414
Short name T232
Test name
Test status
Simulation time 3179557301 ps
CPU time 63.57 seconds
Started Oct 09 02:11:02 AM UTC 24
Finished Oct 09 02:12:22 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1899394414 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 209.prim_prince_test.1899394414
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/209.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/21.prim_prince_test.3964986520
Short name T57
Test name
Test status
Simulation time 3362311071 ps
CPU time 63.77 seconds
Started Oct 09 02:07:57 AM UTC 24
Finished Oct 09 02:09:19 AM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3964986520 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 21.prim_prince_test.3964986520
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/21.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/210.prim_prince_test.923008950
Short name T204
Test name
Test status
Simulation time 1923258404 ps
CPU time 37.9 seconds
Started Oct 09 02:11:03 AM UTC 24
Finished Oct 09 02:11:51 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=923008950 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 210.prim_prince_test.923008950
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/210.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/211.prim_prince_test.1463063190
Short name T238
Test name
Test status
Simulation time 3397085184 ps
CPU time 68.23 seconds
Started Oct 09 02:11:03 AM UTC 24
Finished Oct 09 02:12:29 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1463063190 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 211.prim_prince_test.1463063190
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/211.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/212.prim_prince_test.1794863027
Short name T215
Test name
Test status
Simulation time 2206135947 ps
CPU time 42.88 seconds
Started Oct 09 02:11:03 AM UTC 24
Finished Oct 09 02:11:58 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1794863027 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 212.prim_prince_test.1794863027
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/212.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/213.prim_prince_test.1363304966
Short name T237
Test name
Test status
Simulation time 3521228672 ps
CPU time 65.11 seconds
Started Oct 09 02:11:05 AM UTC 24
Finished Oct 09 02:12:29 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1363304966 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 213.prim_prince_test.1363304966
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/213.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/214.prim_prince_test.1536762212
Short name T240
Test name
Test status
Simulation time 3587582554 ps
CPU time 66.92 seconds
Started Oct 09 02:11:05 AM UTC 24
Finished Oct 09 02:12:31 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1536762212 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 214.prim_prince_test.1536762212
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/214.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/215.prim_prince_test.4289520942
Short name T182
Test name
Test status
Simulation time 854374488 ps
CPU time 16.31 seconds
Started Oct 09 02:11:07 AM UTC 24
Finished Oct 09 02:11:29 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4289520942 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 215.prim_prince_test.4289520942
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/215.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/216.prim_prince_test.2794729435
Short name T187
Test name
Test status
Simulation time 1368714405 ps
CPU time 27.6 seconds
Started Oct 09 02:11:07 AM UTC 24
Finished Oct 09 02:11:42 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2794729435 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 216.prim_prince_test.2794729435
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/216.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/217.prim_prince_test.4282723436
Short name T219
Test name
Test status
Simulation time 2091746288 ps
CPU time 41.88 seconds
Started Oct 09 02:11:07 AM UTC 24
Finished Oct 09 02:12:00 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4282723436 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 217.prim_prince_test.4282723436
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/217.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/218.prim_prince_test.1717091477
Short name T239
Test name
Test status
Simulation time 3263079057 ps
CPU time 65.05 seconds
Started Oct 09 02:11:08 AM UTC 24
Finished Oct 09 02:12:31 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1717091477 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 218.prim_prince_test.1717091477
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/218.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/219.prim_prince_test.907090628
Short name T203
Test name
Test status
Simulation time 1719838858 ps
CPU time 32.91 seconds
Started Oct 09 02:11:09 AM UTC 24
Finished Oct 09 02:11:51 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=907090628 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 219.prim_prince_test.907090628
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/219.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/22.prim_prince_test.913379548
Short name T7
Test name
Test status
Simulation time 879115383 ps
CPU time 15.99 seconds
Started Oct 09 02:07:57 AM UTC 24
Finished Oct 09 02:08:19 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=913379548 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 22.prim_prince_test.913379548
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/22.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/220.prim_prince_test.3192086734
Short name T235
Test name
Test status
Simulation time 3013830290 ps
CPU time 60.66 seconds
Started Oct 09 02:11:11 AM UTC 24
Finished Oct 09 02:12:27 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3192086734 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 220.prim_prince_test.3192086734
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/220.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/221.prim_prince_test.2461049258
Short name T224
Test name
Test status
Simulation time 2403028166 ps
CPU time 44.25 seconds
Started Oct 09 02:11:12 AM UTC 24
Finished Oct 09 02:12:09 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2461049258 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 221.prim_prince_test.2461049258
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/221.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/222.prim_prince_test.1023414996
Short name T218
Test name
Test status
Simulation time 1854763478 ps
CPU time 37.05 seconds
Started Oct 09 02:11:12 AM UTC 24
Finished Oct 09 02:11:59 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1023414996 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 222.prim_prince_test.1023414996
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/222.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/223.prim_prince_test.206901494
Short name T202
Test name
Test status
Simulation time 1456351931 ps
CPU time 28.88 seconds
Started Oct 09 02:11:13 AM UTC 24
Finished Oct 09 02:11:50 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=206901494 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 223.prim_prince_test.206901494
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/223.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/224.prim_prince_test.1891446262
Short name T200
Test name
Test status
Simulation time 1457150583 ps
CPU time 27.22 seconds
Started Oct 09 02:11:13 AM UTC 24
Finished Oct 09 02:11:48 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1891446262 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 224.prim_prince_test.1891446262
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/224.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/225.prim_prince_test.1590464416
Short name T227
Test name
Test status
Simulation time 2284710801 ps
CPU time 42.37 seconds
Started Oct 09 02:11:16 AM UTC 24
Finished Oct 09 02:12:11 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1590464416 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 225.prim_prince_test.1590464416
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/225.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/226.prim_prince_test.3686318880
Short name T220
Test name
Test status
Simulation time 1762357321 ps
CPU time 34.78 seconds
Started Oct 09 02:11:16 AM UTC 24
Finished Oct 09 02:12:01 AM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3686318880 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 226.prim_prince_test.3686318880
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/226.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/227.prim_prince_test.3613717198
Short name T245
Test name
Test status
Simulation time 3108777393 ps
CPU time 62.83 seconds
Started Oct 09 02:11:16 AM UTC 24
Finished Oct 09 02:12:36 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3613717198 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 227.prim_prince_test.3613717198
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/227.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/228.prim_prince_test.2839039920
Short name T252
Test name
Test status
Simulation time 3431585436 ps
CPU time 68.75 seconds
Started Oct 09 02:11:16 AM UTC 24
Finished Oct 09 02:12:43 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2839039920 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 228.prim_prince_test.2839039920
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/228.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/229.prim_prince_test.2560186073
Short name T257
Test name
Test status
Simulation time 3554131714 ps
CPU time 71.75 seconds
Started Oct 09 02:11:21 AM UTC 24
Finished Oct 09 02:12:51 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2560186073 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 229.prim_prince_test.2560186073
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/229.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/23.prim_prince_test.488561285
Short name T50
Test name
Test status
Simulation time 3155978996 ps
CPU time 58.5 seconds
Started Oct 09 02:07:57 AM UTC 24
Finished Oct 09 02:09:13 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=488561285 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 23.prim_prince_test.488561285
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/23.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/230.prim_prince_test.3108305422
Short name T192
Test name
Test status
Simulation time 811655163 ps
CPU time 16.41 seconds
Started Oct 09 02:11:23 AM UTC 24
Finished Oct 09 02:11:44 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3108305422 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 230.prim_prince_test.3108305422
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/230.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/231.prim_prince_test.1945571201
Short name T236
Test name
Test status
Simulation time 2704098234 ps
CPU time 50.57 seconds
Started Oct 09 02:11:23 AM UTC 24
Finished Oct 09 02:12:28 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1945571201 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 231.prim_prince_test.1945571201
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/231.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/232.prim_prince_test.2752705460
Short name T207
Test name
Test status
Simulation time 1092171163 ps
CPU time 22.1 seconds
Started Oct 09 02:11:24 AM UTC 24
Finished Oct 09 02:11:52 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2752705460 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 232.prim_prince_test.2752705460
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/232.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/233.prim_prince_test.2412753997
Short name T229
Test name
Test status
Simulation time 2020887941 ps
CPU time 40.47 seconds
Started Oct 09 02:11:24 AM UTC 24
Finished Oct 09 02:12:15 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2412753997 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 233.prim_prince_test.2412753997
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/233.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/234.prim_prince_test.2970509839
Short name T223
Test name
Test status
Simulation time 1617904473 ps
CPU time 32.19 seconds
Started Oct 09 02:11:24 AM UTC 24
Finished Oct 09 02:12:05 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2970509839 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 234.prim_prince_test.2970509839
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/234.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/235.prim_prince_test.259188428
Short name T198
Test name
Test status
Simulation time 832906488 ps
CPU time 16.9 seconds
Started Oct 09 02:11:24 AM UTC 24
Finished Oct 09 02:11:46 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=259188428 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 235.prim_prince_test.259188428
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/235.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/236.prim_prince_test.1938045734
Short name T231
Test name
Test status
Simulation time 2227758296 ps
CPU time 41.27 seconds
Started Oct 09 02:11:26 AM UTC 24
Finished Oct 09 02:12:20 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1938045734 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 236.prim_prince_test.1938045734
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/236.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/237.prim_prince_test.3627357610
Short name T265
Test name
Test status
Simulation time 3758240228 ps
CPU time 76 seconds
Started Oct 09 02:11:28 AM UTC 24
Finished Oct 09 02:13:04 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3627357610 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 237.prim_prince_test.3627357610
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/237.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/238.prim_prince_test.451987480
Short name T226
Test name
Test status
Simulation time 1673233675 ps
CPU time 31.5 seconds
Started Oct 09 02:11:30 AM UTC 24
Finished Oct 09 02:12:11 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=451987480 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 238.prim_prince_test.451987480
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/238.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/239.prim_prince_test.4124067487
Short name T244
Test name
Test status
Simulation time 2573523386 ps
CPU time 48.5 seconds
Started Oct 09 02:11:33 AM UTC 24
Finished Oct 09 02:12:35 AM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4124067487 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 239.prim_prince_test.4124067487
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/239.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/24.prim_prince_test.144007397
Short name T40
Test name
Test status
Simulation time 2470839392 ps
CPU time 47.36 seconds
Started Oct 09 02:07:57 AM UTC 24
Finished Oct 09 02:08:58 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=144007397 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 24.prim_prince_test.144007397
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/24.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/240.prim_prince_test.917851188
Short name T216
Test name
Test status
Simulation time 996320588 ps
CPU time 19.09 seconds
Started Oct 09 02:11:33 AM UTC 24
Finished Oct 09 02:11:58 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=917851188 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 240.prim_prince_test.917851188
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/240.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/241.prim_prince_test.1481637405
Short name T249
Test name
Test status
Simulation time 2481919148 ps
CPU time 50.3 seconds
Started Oct 09 02:11:35 AM UTC 24
Finished Oct 09 02:12:39 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1481637405 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 241.prim_prince_test.1481637405
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/241.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/242.prim_prince_test.4261976809
Short name T241
Test name
Test status
Simulation time 2166761257 ps
CPU time 40.53 seconds
Started Oct 09 02:11:39 AM UTC 24
Finished Oct 09 02:12:31 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4261976809 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 242.prim_prince_test.4261976809
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/242.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/243.prim_prince_test.8392015
Short name T247
Test name
Test status
Simulation time 2131912209 ps
CPU time 41.42 seconds
Started Oct 09 02:11:43 AM UTC 24
Finished Oct 09 02:12:36 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8392015 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 243.prim_prince_test.8392015
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/243.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/244.prim_prince_test.3543040363
Short name T278
Test name
Test status
Simulation time 3628409239 ps
CPU time 67.77 seconds
Started Oct 09 02:11:43 AM UTC 24
Finished Oct 09 02:13:10 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3543040363 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 244.prim_prince_test.3543040363
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/244.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/245.prim_prince_test.2367071943
Short name T243
Test name
Test status
Simulation time 1939393089 ps
CPU time 39.72 seconds
Started Oct 09 02:11:44 AM UTC 24
Finished Oct 09 02:12:35 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2367071943 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 245.prim_prince_test.2367071943
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/245.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/246.prim_prince_test.4103271261
Short name T275
Test name
Test status
Simulation time 3553852365 ps
CPU time 65.55 seconds
Started Oct 09 02:11:44 AM UTC 24
Finished Oct 09 02:13:09 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4103271261 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 246.prim_prince_test.4103271261
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/246.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/247.prim_prince_test.3598889034
Short name T225
Test name
Test status
Simulation time 959562936 ps
CPU time 19.36 seconds
Started Oct 09 02:11:45 AM UTC 24
Finished Oct 09 02:12:10 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3598889034 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 247.prim_prince_test.3598889034
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/247.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/248.prim_prince_test.128850877
Short name T274
Test name
Test status
Simulation time 3542601642 ps
CPU time 64.8 seconds
Started Oct 09 02:11:45 AM UTC 24
Finished Oct 09 02:13:08 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=128850877 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 248.prim_prince_test.128850877
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/248.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/249.prim_prince_test.4102486486
Short name T195
Test name
Test status
Simulation time 2229107276 ps
CPU time 45.72 seconds
Started Oct 09 02:11:46 AM UTC 24
Finished Oct 09 02:12:44 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4102486486 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 249.prim_prince_test.4102486486
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/249.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/25.prim_prince_test.1446271501
Short name T43
Test name
Test status
Simulation time 2533759399 ps
CPU time 48.61 seconds
Started Oct 09 02:07:59 AM UTC 24
Finished Oct 09 02:09:01 AM UTC 24
Peak memory 154592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1446271501 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 25.prim_prince_test.1446271501
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/25.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/250.prim_prince_test.2415013973
Short name T264
Test name
Test status
Simulation time 2844153743 ps
CPU time 58.03 seconds
Started Oct 09 02:11:46 AM UTC 24
Finished Oct 09 02:12:59 AM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2415013973 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 250.prim_prince_test.2415013973
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/250.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/251.prim_prince_test.227732891
Short name T233
Test name
Test status
Simulation time 1656514479 ps
CPU time 30.63 seconds
Started Oct 09 02:11:46 AM UTC 24
Finished Oct 09 02:12:26 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=227732891 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 251.prim_prince_test.227732891
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/251.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/252.prim_prince_test.1434868645
Short name T276
Test name
Test status
Simulation time 3254817891 ps
CPU time 64.61 seconds
Started Oct 09 02:11:47 AM UTC 24
Finished Oct 09 02:13:09 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1434868645 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 252.prim_prince_test.1434868645
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/252.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/253.prim_prince_test.4071989351
Short name T282
Test name
Test status
Simulation time 3345436313 ps
CPU time 68.07 seconds
Started Oct 09 02:11:47 AM UTC 24
Finished Oct 09 02:13:13 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4071989351 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 253.prim_prince_test.4071989351
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/253.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/254.prim_prince_test.2725195502
Short name T279
Test name
Test status
Simulation time 3295575699 ps
CPU time 64.49 seconds
Started Oct 09 02:11:48 AM UTC 24
Finished Oct 09 02:13:10 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2725195502 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 254.prim_prince_test.2725195502
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/254.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/255.prim_prince_test.3654332950
Short name T288
Test name
Test status
Simulation time 3535802782 ps
CPU time 67.5 seconds
Started Oct 09 02:11:49 AM UTC 24
Finished Oct 09 02:13:16 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3654332950 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 255.prim_prince_test.3654332950
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/255.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/256.prim_prince_test.2937146082
Short name T248
Test name
Test status
Simulation time 2001664837 ps
CPU time 36.9 seconds
Started Oct 09 02:11:51 AM UTC 24
Finished Oct 09 02:12:39 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2937146082 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 256.prim_prince_test.2937146082
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/256.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/257.prim_prince_test.2758329603
Short name T285
Test name
Test status
Simulation time 3505705890 ps
CPU time 65.83 seconds
Started Oct 09 02:11:51 AM UTC 24
Finished Oct 09 02:13:15 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2758329603 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 257.prim_prince_test.2758329603
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/257.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/258.prim_prince_test.1669072065
Short name T268
Test name
Test status
Simulation time 3042216541 ps
CPU time 55.88 seconds
Started Oct 09 02:11:52 AM UTC 24
Finished Oct 09 02:13:04 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1669072065 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 258.prim_prince_test.1669072065
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/258.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/259.prim_prince_test.2682245631
Short name T251
Test name
Test status
Simulation time 2031644067 ps
CPU time 39.91 seconds
Started Oct 09 02:11:52 AM UTC 24
Finished Oct 09 02:12:43 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2682245631 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 259.prim_prince_test.2682245631
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/259.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/26.prim_prince_test.2584770527
Short name T51
Test name
Test status
Simulation time 3104168761 ps
CPU time 57.51 seconds
Started Oct 09 02:07:59 AM UTC 24
Finished Oct 09 02:09:13 AM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2584770527 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 26.prim_prince_test.2584770527
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/26.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/260.prim_prince_test.2307814156
Short name T270
Test name
Test status
Simulation time 2975572056 ps
CPU time 56.02 seconds
Started Oct 09 02:11:53 AM UTC 24
Finished Oct 09 02:13:05 AM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2307814156 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 260.prim_prince_test.2307814156
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/260.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/261.prim_prince_test.1401936588
Short name T246
Test name
Test status
Simulation time 1640080590 ps
CPU time 33.51 seconds
Started Oct 09 02:11:53 AM UTC 24
Finished Oct 09 02:12:36 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1401936588 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 261.prim_prince_test.1401936588
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/261.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/262.prim_prince_test.2101819953
Short name T271
Test name
Test status
Simulation time 3020602846 ps
CPU time 56.49 seconds
Started Oct 09 02:11:53 AM UTC 24
Finished Oct 09 02:13:06 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2101819953 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 262.prim_prince_test.2101819953
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/262.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/263.prim_prince_test.2393569725
Short name T258
Test name
Test status
Simulation time 2177222518 ps
CPU time 44.71 seconds
Started Oct 09 02:11:54 AM UTC 24
Finished Oct 09 02:12:51 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2393569725 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 263.prim_prince_test.2393569725
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/263.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/264.prim_prince_test.1414882779
Short name T281
Test name
Test status
Simulation time 3111354199 ps
CPU time 60.49 seconds
Started Oct 09 02:11:54 AM UTC 24
Finished Oct 09 02:13:12 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1414882779 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 264.prim_prince_test.1414882779
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/264.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/265.prim_prince_test.2737583342
Short name T269
Test name
Test status
Simulation time 2948778260 ps
CPU time 53.77 seconds
Started Oct 09 02:11:55 AM UTC 24
Finished Oct 09 02:13:04 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2737583342 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 265.prim_prince_test.2737583342
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/265.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/266.prim_prince_test.3440315036
Short name T280
Test name
Test status
Simulation time 3132630691 ps
CPU time 58.14 seconds
Started Oct 09 02:11:56 AM UTC 24
Finished Oct 09 02:13:11 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3440315036 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 266.prim_prince_test.3440315036
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/266.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/267.prim_prince_test.534908173
Short name T234
Test name
Test status
Simulation time 1268244334 ps
CPU time 23.68 seconds
Started Oct 09 02:11:56 AM UTC 24
Finished Oct 09 02:12:27 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=534908173 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 267.prim_prince_test.534908173
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/267.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/268.prim_prince_test.2717677517
Short name T277
Test name
Test status
Simulation time 2947886358 ps
CPU time 57.29 seconds
Started Oct 09 02:11:57 AM UTC 24
Finished Oct 09 02:13:10 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2717677517 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 268.prim_prince_test.2717677517
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/268.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/269.prim_prince_test.4266026069
Short name T295
Test name
Test status
Simulation time 3270068070 ps
CPU time 67.42 seconds
Started Oct 09 02:11:58 AM UTC 24
Finished Oct 09 02:13:23 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4266026069 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 269.prim_prince_test.4266026069
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/269.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/27.prim_prince_test.3263907941
Short name T28
Test name
Test status
Simulation time 1877586132 ps
CPU time 35.02 seconds
Started Oct 09 02:07:59 AM UTC 24
Finished Oct 09 02:08:45 AM UTC 24
Peak memory 154536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3263907941 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 27.prim_prince_test.3263907941
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/27.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/270.prim_prince_test.2698144660
Short name T283
Test name
Test status
Simulation time 2913473283 ps
CPU time 59.2 seconds
Started Oct 09 02:11:58 AM UTC 24
Finished Oct 09 02:13:13 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2698144660 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 270.prim_prince_test.2698144660
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/270.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/271.prim_prince_test.956983614
Short name T255
Test name
Test status
Simulation time 1992981072 ps
CPU time 40.63 seconds
Started Oct 09 02:11:58 AM UTC 24
Finished Oct 09 02:12:50 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=956983614 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 271.prim_prince_test.956983614
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/271.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/272.prim_prince_test.3809886797
Short name T261
Test name
Test status
Simulation time 2189892779 ps
CPU time 45.24 seconds
Started Oct 09 02:11:59 AM UTC 24
Finished Oct 09 02:12:57 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3809886797 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 272.prim_prince_test.3809886797
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/272.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/273.prim_prince_test.3080973651
Short name T291
Test name
Test status
Simulation time 3023901824 ps
CPU time 61.6 seconds
Started Oct 09 02:11:59 AM UTC 24
Finished Oct 09 02:13:17 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3080973651 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 273.prim_prince_test.3080973651
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/273.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/274.prim_prince_test.2064230588
Short name T254
Test name
Test status
Simulation time 1876995435 ps
CPU time 34.87 seconds
Started Oct 09 02:12:02 AM UTC 24
Finished Oct 09 02:12:47 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2064230588 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 274.prim_prince_test.2064230588
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/274.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/275.prim_prince_test.201520516
Short name T250
Test name
Test status
Simulation time 1683047009 ps
CPU time 31.37 seconds
Started Oct 09 02:12:02 AM UTC 24
Finished Oct 09 02:12:43 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=201520516 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 275.prim_prince_test.201520516
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/275.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/276.prim_prince_test.3502133611
Short name T272
Test name
Test status
Simulation time 2521085061 ps
CPU time 51.91 seconds
Started Oct 09 02:12:02 AM UTC 24
Finished Oct 09 02:13:07 AM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3502133611 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 276.prim_prince_test.3502133611
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/276.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/277.prim_prince_test.1821863605
Short name T292
Test name
Test status
Simulation time 3048269574 ps
CPU time 59.92 seconds
Started Oct 09 02:12:03 AM UTC 24
Finished Oct 09 02:13:19 AM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1821863605 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 277.prim_prince_test.1821863605
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/277.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/278.prim_prince_test.3410000925
Short name T305
Test name
Test status
Simulation time 3514195828 ps
CPU time 70.64 seconds
Started Oct 09 02:12:06 AM UTC 24
Finished Oct 09 02:13:35 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3410000925 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 278.prim_prince_test.3410000925
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/278.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/279.prim_prince_test.1367145851
Short name T242
Test name
Test status
Simulation time 861615653 ps
CPU time 17.09 seconds
Started Oct 09 02:12:10 AM UTC 24
Finished Oct 09 02:12:33 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1367145851 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 279.prim_prince_test.1367145851
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/279.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/28.prim_prince_test.533975435
Short name T32
Test name
Test status
Simulation time 2014040019 ps
CPU time 38.39 seconds
Started Oct 09 02:07:59 AM UTC 24
Finished Oct 09 02:08:48 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=533975435 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 28.prim_prince_test.533975435
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/28.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/280.prim_prince_test.2880507787
Short name T311
Test name
Test status
Simulation time 3691252812 ps
CPU time 74.61 seconds
Started Oct 09 02:12:10 AM UTC 24
Finished Oct 09 02:13:44 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2880507787 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 280.prim_prince_test.2880507787
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/280.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/281.prim_prince_test.1233687831
Short name T260
Test name
Test status
Simulation time 1660089876 ps
CPU time 34.03 seconds
Started Oct 09 02:12:11 AM UTC 24
Finished Oct 09 02:12:55 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1233687831 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 281.prim_prince_test.1233687831
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/281.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/282.prim_prince_test.597188349
Short name T304
Test name
Test status
Simulation time 3491807158 ps
CPU time 63.88 seconds
Started Oct 09 02:12:13 AM UTC 24
Finished Oct 09 02:13:35 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=597188349 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 282.prim_prince_test.597188349
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/282.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/283.prim_prince_test.1496263753
Short name T294
Test name
Test status
Simulation time 2661876142 ps
CPU time 54.13 seconds
Started Oct 09 02:12:14 AM UTC 24
Finished Oct 09 02:13:22 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1496263753 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 283.prim_prince_test.1496263753
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/283.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/284.prim_prince_test.406670405
Short name T253
Test name
Test status
Simulation time 1205189491 ps
CPU time 23.16 seconds
Started Oct 09 02:12:16 AM UTC 24
Finished Oct 09 02:12:46 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=406670405 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 284.prim_prince_test.406670405
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/284.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/285.prim_prince_test.3962121870
Short name T259
Test name
Test status
Simulation time 1340165226 ps
CPU time 25.35 seconds
Started Oct 09 02:12:19 AM UTC 24
Finished Oct 09 02:12:52 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3962121870 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 285.prim_prince_test.3962121870
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/285.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/286.prim_prince_test.2948611129
Short name T313
Test name
Test status
Simulation time 3516001355 ps
CPU time 65.13 seconds
Started Oct 09 02:12:21 AM UTC 24
Finished Oct 09 02:13:45 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2948611129 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 286.prim_prince_test.2948611129
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/286.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/287.prim_prince_test.2703248664
Short name T262
Test name
Test status
Simulation time 1330412871 ps
CPU time 27.31 seconds
Started Oct 09 02:12:22 AM UTC 24
Finished Oct 09 02:12:57 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2703248664 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 287.prim_prince_test.2703248664
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/287.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/288.prim_prince_test.96725948
Short name T303
Test name
Test status
Simulation time 2837822086 ps
CPU time 51.93 seconds
Started Oct 09 02:12:26 AM UTC 24
Finished Oct 09 02:13:34 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=96725948 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 288.prim_prince_test.96725948
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/288.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/289.prim_prince_test.1708657773
Short name T256
Test name
Test status
Simulation time 837271457 ps
CPU time 17.41 seconds
Started Oct 09 02:12:27 AM UTC 24
Finished Oct 09 02:12:50 AM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1708657773 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 289.prim_prince_test.1708657773
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/289.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/29.prim_prince_test.613333492
Short name T27
Test name
Test status
Simulation time 1873976791 ps
CPU time 34.57 seconds
Started Oct 09 02:07:59 AM UTC 24
Finished Oct 09 02:08:44 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=613333492 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 29.prim_prince_test.613333492
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/29.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/290.prim_prince_test.733343047
Short name T296
Test name
Test status
Simulation time 2103907791 ps
CPU time 42.73 seconds
Started Oct 09 02:12:29 AM UTC 24
Finished Oct 09 02:13:23 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=733343047 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 290.prim_prince_test.733343047
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/290.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/291.prim_prince_test.1207762597
Short name T321
Test name
Test status
Simulation time 3385113473 ps
CPU time 65.68 seconds
Started Oct 09 02:12:29 AM UTC 24
Finished Oct 09 02:13:53 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1207762597 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 291.prim_prince_test.1207762597
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/291.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/292.prim_prince_test.1133745321
Short name T293
Test name
Test status
Simulation time 1928587303 ps
CPU time 39.51 seconds
Started Oct 09 02:12:30 AM UTC 24
Finished Oct 09 02:13:21 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1133745321 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 292.prim_prince_test.1133745321
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/292.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/293.prim_prince_test.163855975
Short name T287
Test name
Test status
Simulation time 1730604430 ps
CPU time 35.14 seconds
Started Oct 09 02:12:30 AM UTC 24
Finished Oct 09 02:13:15 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=163855975 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 293.prim_prince_test.163855975
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/293.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/294.prim_prince_test.814534000
Short name T300
Test name
Test status
Simulation time 2447392957 ps
CPU time 45.9 seconds
Started Oct 09 02:12:31 AM UTC 24
Finished Oct 09 02:13:31 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=814534000 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 294.prim_prince_test.814534000
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/294.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/295.prim_prince_test.3957043114
Short name T263
Test name
Test status
Simulation time 987038067 ps
CPU time 19.15 seconds
Started Oct 09 02:12:32 AM UTC 24
Finished Oct 09 02:12:58 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3957043114 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 295.prim_prince_test.3957043114
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/295.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/296.prim_prince_test.2644607930
Short name T320
Test name
Test status
Simulation time 3156278336 ps
CPU time 61.45 seconds
Started Oct 09 02:12:32 AM UTC 24
Finished Oct 09 02:13:51 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2644607930 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 296.prim_prince_test.2644607930
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/296.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/297.prim_prince_test.1029884146
Short name T310
Test name
Test status
Simulation time 2837473976 ps
CPU time 52.6 seconds
Started Oct 09 02:12:34 AM UTC 24
Finished Oct 09 02:13:41 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1029884146 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 297.prim_prince_test.1029884146
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/297.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/298.prim_prince_test.3468059673
Short name T319
Test name
Test status
Simulation time 2921160719 ps
CPU time 58.41 seconds
Started Oct 09 02:12:36 AM UTC 24
Finished Oct 09 02:13:50 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3468059673 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 298.prim_prince_test.3468059673
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/298.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/299.prim_prince_test.878005436
Short name T273
Test name
Test status
Simulation time 1274809044 ps
CPU time 24.09 seconds
Started Oct 09 02:12:36 AM UTC 24
Finished Oct 09 02:13:08 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=878005436 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 299.prim_prince_test.878005436
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/299.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/3.prim_prince_test.2665165875
Short name T6
Test name
Test status
Simulation time 2341597917 ps
CPU time 38.74 seconds
Started Oct 09 02:07:24 AM UTC 24
Finished Oct 09 02:08:16 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2665165875 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 3.prim_prince_test.2665165875
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/3.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/30.prim_prince_test.2320018016
Short name T10
Test name
Test status
Simulation time 1061168944 ps
CPU time 20.59 seconds
Started Oct 09 02:07:59 AM UTC 24
Finished Oct 09 02:08:26 AM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2320018016 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 30.prim_prince_test.2320018016
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/30.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/300.prim_prince_test.1492228464
Short name T331
Test name
Test status
Simulation time 3594943800 ps
CPU time 66.75 seconds
Started Oct 09 02:12:37 AM UTC 24
Finished Oct 09 02:14:03 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1492228464 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 300.prim_prince_test.1492228464
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/300.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/301.prim_prince_test.1585718601
Short name T299
Test name
Test status
Simulation time 1991225769 ps
CPU time 40.65 seconds
Started Oct 09 02:12:37 AM UTC 24
Finished Oct 09 02:13:29 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1585718601 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 301.prim_prince_test.1585718601
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/301.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/302.prim_prince_test.2059340148
Short name T284
Test name
Test status
Simulation time 1462816759 ps
CPU time 28.88 seconds
Started Oct 09 02:12:37 AM UTC 24
Finished Oct 09 02:13:15 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2059340148 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 302.prim_prince_test.2059340148
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/302.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/303.prim_prince_test.437405734
Short name T267
Test name
Test status
Simulation time 907270166 ps
CPU time 19.12 seconds
Started Oct 09 02:12:39 AM UTC 24
Finished Oct 09 02:13:04 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=437405734 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 303.prim_prince_test.437405734
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/303.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/304.prim_prince_test.3365073749
Short name T266
Test name
Test status
Simulation time 908921705 ps
CPU time 18.9 seconds
Started Oct 09 02:12:39 AM UTC 24
Finished Oct 09 02:13:04 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3365073749 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 304.prim_prince_test.3365073749
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/304.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/305.prim_prince_test.804898684
Short name T335
Test name
Test status
Simulation time 3296771856 ps
CPU time 66.39 seconds
Started Oct 09 02:12:44 AM UTC 24
Finished Oct 09 02:14:07 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=804898684 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 305.prim_prince_test.804898684
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/305.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/306.prim_prince_test.241981267
Short name T346
Test name
Test status
Simulation time 3669734658 ps
CPU time 71.36 seconds
Started Oct 09 02:12:44 AM UTC 24
Finished Oct 09 02:14:14 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=241981267 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 306.prim_prince_test.241981267
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/306.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/307.prim_prince_test.4095998413
Short name T298
Test name
Test status
Simulation time 1828664278 ps
CPU time 33.56 seconds
Started Oct 09 02:12:44 AM UTC 24
Finished Oct 09 02:13:28 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4095998413 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 307.prim_prince_test.4095998413
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/307.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/308.prim_prince_test.3272702588
Short name T306
Test name
Test status
Simulation time 1942333972 ps
CPU time 39.61 seconds
Started Oct 09 02:12:45 AM UTC 24
Finished Oct 09 02:13:35 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3272702588 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 308.prim_prince_test.3272702588
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/308.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/309.prim_prince_test.1998683797
Short name T289
Test name
Test status
Simulation time 1083626720 ps
CPU time 22.29 seconds
Started Oct 09 02:12:47 AM UTC 24
Finished Oct 09 02:13:16 AM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1998683797 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 309.prim_prince_test.1998683797
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/309.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/31.prim_prince_test.750630335
Short name T62
Test name
Test status
Simulation time 3340268792 ps
CPU time 62.25 seconds
Started Oct 09 02:08:03 AM UTC 24
Finished Oct 09 02:09:23 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=750630335 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 31.prim_prince_test.750630335
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/31.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/310.prim_prince_test.4254808408
Short name T345
Test name
Test status
Simulation time 3389524120 ps
CPU time 67.9 seconds
Started Oct 09 02:12:48 AM UTC 24
Finished Oct 09 02:14:14 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4254808408 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 310.prim_prince_test.4254808408
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/310.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/311.prim_prince_test.986332391
Short name T348
Test name
Test status
Simulation time 3564553943 ps
CPU time 67.56 seconds
Started Oct 09 02:12:50 AM UTC 24
Finished Oct 09 02:14:17 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=986332391 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 311.prim_prince_test.986332391
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/311.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/312.prim_prince_test.3496469349
Short name T297
Test name
Test status
Simulation time 1384190204 ps
CPU time 26.04 seconds
Started Oct 09 02:12:52 AM UTC 24
Finished Oct 09 02:13:26 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3496469349 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 312.prim_prince_test.3496469349
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/312.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/313.prim_prince_test.2533577208
Short name T315
Test name
Test status
Simulation time 2184757420 ps
CPU time 43.75 seconds
Started Oct 09 02:12:52 AM UTC 24
Finished Oct 09 02:13:48 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2533577208 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 313.prim_prince_test.2533577208
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/313.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/314.prim_prince_test.2984893070
Short name T286
Test name
Test status
Simulation time 865547990 ps
CPU time 16.71 seconds
Started Oct 09 02:12:53 AM UTC 24
Finished Oct 09 02:13:15 AM UTC 24
Peak memory 154872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2984893070 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 314.prim_prince_test.2984893070
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/314.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/315.prim_prince_test.996016150
Short name T333
Test name
Test status
Simulation time 2894168565 ps
CPU time 54.23 seconds
Started Oct 09 02:12:53 AM UTC 24
Finished Oct 09 02:14:03 AM UTC 24
Peak memory 154952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=996016150 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 315.prim_prince_test.996016150
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/315.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/316.prim_prince_test.3073401293
Short name T290
Test name
Test status
Simulation time 790807314 ps
CPU time 14.97 seconds
Started Oct 09 02:12:56 AM UTC 24
Finished Oct 09 02:13:16 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3073401293 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 316.prim_prince_test.3073401293
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/316.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/317.prim_prince_test.866287093
Short name T328
Test name
Test status
Simulation time 2664955046 ps
CPU time 50.75 seconds
Started Oct 09 02:12:57 AM UTC 24
Finished Oct 09 02:14:02 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=866287093 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 317.prim_prince_test.866287093
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/317.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/318.prim_prince_test.1071041591
Short name T318
Test name
Test status
Simulation time 2117994237 ps
CPU time 39 seconds
Started Oct 09 02:12:58 AM UTC 24
Finished Oct 09 02:13:49 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1071041591 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 318.prim_prince_test.1071041591
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/318.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/319.prim_prince_test.2906549752
Short name T317
Test name
Test status
Simulation time 1973617889 ps
CPU time 39.47 seconds
Started Oct 09 02:12:58 AM UTC 24
Finished Oct 09 02:13:49 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2906549752 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 319.prim_prince_test.2906549752
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/319.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/32.prim_prince_test.612820262
Short name T70
Test name
Test status
Simulation time 3473086576 ps
CPU time 67.29 seconds
Started Oct 09 02:08:03 AM UTC 24
Finished Oct 09 02:09:28 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=612820262 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 32.prim_prince_test.612820262
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/32.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/320.prim_prince_test.3838616841
Short name T316
Test name
Test status
Simulation time 1907021603 ps
CPU time 37.85 seconds
Started Oct 09 02:13:00 AM UTC 24
Finished Oct 09 02:13:48 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3838616841 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 320.prim_prince_test.3838616841
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/320.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/321.prim_prince_test.2595779440
Short name T324
Test name
Test status
Simulation time 1982300333 ps
CPU time 39.17 seconds
Started Oct 09 02:13:05 AM UTC 24
Finished Oct 09 02:13:55 AM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2595779440 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 321.prim_prince_test.2595779440
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/321.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/322.prim_prince_test.3301343326
Short name T326
Test name
Test status
Simulation time 2099627616 ps
CPU time 41.24 seconds
Started Oct 09 02:13:05 AM UTC 24
Finished Oct 09 02:13:58 AM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3301343326 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 322.prim_prince_test.3301343326
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/322.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/323.prim_prince_test.2702677814
Short name T322
Test name
Test status
Simulation time 1959892475 ps
CPU time 38.81 seconds
Started Oct 09 02:13:05 AM UTC 24
Finished Oct 09 02:13:54 AM UTC 24
Peak memory 156336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2702677814 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 323.prim_prince_test.2702677814
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/323.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/324.prim_prince_test.2933936610
Short name T337
Test name
Test status
Simulation time 2638202593 ps
CPU time 49.49 seconds
Started Oct 09 02:13:05 AM UTC 24
Finished Oct 09 02:14:09 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2933936610 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 324.prim_prince_test.2933936610
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/324.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/325.prim_prince_test.4127550409
Short name T363
Test name
Test status
Simulation time 3574309658 ps
CPU time 68.48 seconds
Started Oct 09 02:13:05 AM UTC 24
Finished Oct 09 02:14:33 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4127550409 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 325.prim_prince_test.4127550409
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/325.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/326.prim_prince_test.1547800547
Short name T301
Test name
Test status
Simulation time 924413084 ps
CPU time 19.21 seconds
Started Oct 09 02:13:07 AM UTC 24
Finished Oct 09 02:13:31 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1547800547 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 326.prim_prince_test.1547800547
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/326.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/327.prim_prince_test.4240005332
Short name T329
Test name
Test status
Simulation time 2223301127 ps
CPU time 43.81 seconds
Started Oct 09 02:13:07 AM UTC 24
Finished Oct 09 02:14:02 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4240005332 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 327.prim_prince_test.4240005332
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/327.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/328.prim_prince_test.3986851314
Short name T330
Test name
Test status
Simulation time 2230587660 ps
CPU time 42.65 seconds
Started Oct 09 02:13:08 AM UTC 24
Finished Oct 09 02:14:03 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3986851314 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 328.prim_prince_test.3986851314
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/328.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/329.prim_prince_test.1435681830
Short name T342
Test name
Test status
Simulation time 2561358588 ps
CPU time 48.86 seconds
Started Oct 09 02:13:09 AM UTC 24
Finished Oct 09 02:14:12 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1435681830 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 329.prim_prince_test.1435681830
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/329.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/33.prim_prince_test.4285191580
Short name T25
Test name
Test status
Simulation time 1554207993 ps
CPU time 30.31 seconds
Started Oct 09 02:08:03 AM UTC 24
Finished Oct 09 02:08:42 AM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4285191580 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 33.prim_prince_test.4285191580
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/33.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/330.prim_prince_test.32233873
Short name T312
Test name
Test status
Simulation time 1373999148 ps
CPU time 27.5 seconds
Started Oct 09 02:13:09 AM UTC 24
Finished Oct 09 02:13:44 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32233873 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 330.prim_prince_test.32233873
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/330.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/331.prim_prince_test.34875594
Short name T302
Test name
Test status
Simulation time 858064723 ps
CPU time 17.85 seconds
Started Oct 09 02:13:10 AM UTC 24
Finished Oct 09 02:13:33 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34875594 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 331.prim_prince_test.34875594
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/331.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/332.prim_prince_test.390123098
Short name T343
Test name
Test status
Simulation time 2614510811 ps
CPU time 48.87 seconds
Started Oct 09 02:13:10 AM UTC 24
Finished Oct 09 02:14:13 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=390123098 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 332.prim_prince_test.390123098
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/332.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/333.prim_prince_test.2023874143
Short name T336
Test name
Test status
Simulation time 2275659682 ps
CPU time 44.85 seconds
Started Oct 09 02:13:12 AM UTC 24
Finished Oct 09 02:14:09 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2023874143 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 333.prim_prince_test.2023874143
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/333.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/334.prim_prince_test.3362258321
Short name T347
Test name
Test status
Simulation time 2654362664 ps
CPU time 49.95 seconds
Started Oct 09 02:13:12 AM UTC 24
Finished Oct 09 02:14:16 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3362258321 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 334.prim_prince_test.3362258321
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/334.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/335.prim_prince_test.2125434257
Short name T356
Test name
Test status
Simulation time 3226498021 ps
CPU time 61.04 seconds
Started Oct 09 02:13:12 AM UTC 24
Finished Oct 09 02:14:30 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2125434257 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 335.prim_prince_test.2125434257
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/335.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/336.prim_prince_test.216236208
Short name T340
Test name
Test status
Simulation time 2291356975 ps
CPU time 45.97 seconds
Started Oct 09 02:13:12 AM UTC 24
Finished Oct 09 02:14:10 AM UTC 24
Peak memory 156468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=216236208 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 336.prim_prince_test.216236208
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/336.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/337.prim_prince_test.1437811635
Short name T327
Test name
Test status
Simulation time 1878641998 ps
CPU time 35.79 seconds
Started Oct 09 02:13:13 AM UTC 24
Finished Oct 09 02:13:59 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1437811635 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 337.prim_prince_test.1437811635
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/337.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/338.prim_prince_test.975311203
Short name T307
Test name
Test status
Simulation time 834754167 ps
CPU time 17.14 seconds
Started Oct 09 02:13:14 AM UTC 24
Finished Oct 09 02:13:36 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=975311203 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 338.prim_prince_test.975311203
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/338.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/339.prim_prince_test.2820779241
Short name T308
Test name
Test status
Simulation time 937183662 ps
CPU time 19.06 seconds
Started Oct 09 02:13:14 AM UTC 24
Finished Oct 09 02:13:39 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2820779241 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 339.prim_prince_test.2820779241
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/339.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/34.prim_prince_test.4142108530
Short name T48
Test name
Test status
Simulation time 2845165350 ps
CPU time 53.58 seconds
Started Oct 09 02:08:03 AM UTC 24
Finished Oct 09 02:09:12 AM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4142108530 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 34.prim_prince_test.4142108530
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/34.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/340.prim_prince_test.3834667455
Short name T309
Test name
Test status
Simulation time 1044142192 ps
CPU time 19.38 seconds
Started Oct 09 02:13:15 AM UTC 24
Finished Oct 09 02:13:41 AM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3834667455 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 340.prim_prince_test.3834667455
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/340.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/341.prim_prince_test.1954320413
Short name T351
Test name
Test status
Simulation time 2763339160 ps
CPU time 51.95 seconds
Started Oct 09 02:13:17 AM UTC 24
Finished Oct 09 02:14:24 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1954320413 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 341.prim_prince_test.1954320413
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/341.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/342.prim_prince_test.3233578152
Short name T323
Test name
Test status
Simulation time 1495453504 ps
CPU time 29.59 seconds
Started Oct 09 02:13:17 AM UTC 24
Finished Oct 09 02:13:55 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3233578152 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 342.prim_prince_test.3233578152
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/342.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/343.prim_prince_test.3325654271
Short name T371
Test name
Test status
Simulation time 3598495885 ps
CPU time 70.59 seconds
Started Oct 09 02:13:17 AM UTC 24
Finished Oct 09 02:14:47 AM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3325654271 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 343.prim_prince_test.3325654271
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/343.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/344.prim_prince_test.1186937225
Short name T314
Test name
Test status
Simulation time 1179075241 ps
CPU time 23.52 seconds
Started Oct 09 02:13:17 AM UTC 24
Finished Oct 09 02:13:47 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1186937225 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 344.prim_prince_test.1186937225
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/344.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/345.prim_prince_test.2495920453
Short name T362
Test name
Test status
Simulation time 2960807433 ps
CPU time 59.38 seconds
Started Oct 09 02:13:17 AM UTC 24
Finished Oct 09 02:14:32 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2495920453 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 345.prim_prince_test.2495920453
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/345.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/346.prim_prince_test.311834128
Short name T366
Test name
Test status
Simulation time 3089592608 ps
CPU time 61.61 seconds
Started Oct 09 02:13:17 AM UTC 24
Finished Oct 09 02:14:35 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=311834128 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 346.prim_prince_test.311834128
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/346.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/347.prim_prince_test.2143542984
Short name T377
Test name
Test status
Simulation time 3735499282 ps
CPU time 74.55 seconds
Started Oct 09 02:13:18 AM UTC 24
Finished Oct 09 02:14:52 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2143542984 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 347.prim_prince_test.2143542984
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/347.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/348.prim_prince_test.1883017966
Short name T334
Test name
Test status
Simulation time 1812525130 ps
CPU time 35.22 seconds
Started Oct 09 02:13:20 AM UTC 24
Finished Oct 09 02:14:06 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1883017966 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 348.prim_prince_test.1883017966
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/348.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/349.prim_prince_test.2993873060
Short name T341
Test name
Test status
Simulation time 1976108821 ps
CPU time 39.12 seconds
Started Oct 09 02:13:21 AM UTC 24
Finished Oct 09 02:14:11 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2993873060 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 349.prim_prince_test.2993873060
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/349.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/35.prim_prince_test.2776092725
Short name T64
Test name
Test status
Simulation time 3338966334 ps
CPU time 63.65 seconds
Started Oct 09 02:08:04 AM UTC 24
Finished Oct 09 02:09:25 AM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2776092725 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 35.prim_prince_test.2776092725
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/35.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/350.prim_prince_test.2198598733
Short name T344
Test name
Test status
Simulation time 2001788889 ps
CPU time 39.77 seconds
Started Oct 09 02:13:23 AM UTC 24
Finished Oct 09 02:14:13 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2198598733 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 350.prim_prince_test.2198598733
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/350.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/351.prim_prince_test.3768820221
Short name T349
Test name
Test status
Simulation time 2243865511 ps
CPU time 44.2 seconds
Started Oct 09 02:13:24 AM UTC 24
Finished Oct 09 02:14:20 AM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3768820221 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 351.prim_prince_test.3768820221
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/351.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/352.prim_prince_test.2961386420
Short name T379
Test name
Test status
Simulation time 3668481004 ps
CPU time 69.1 seconds
Started Oct 09 02:13:24 AM UTC 24
Finished Oct 09 02:14:53 AM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2961386420 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 352.prim_prince_test.2961386420
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/352.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/353.prim_prince_test.1076324695
Short name T359
Test name
Test status
Simulation time 2530731945 ps
CPU time 50.42 seconds
Started Oct 09 02:13:27 AM UTC 24
Finished Oct 09 02:14:31 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1076324695 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 353.prim_prince_test.1076324695
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/353.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/354.prim_prince_test.1086974425
Short name T386
Test name
Test status
Simulation time 3665966051 ps
CPU time 69.34 seconds
Started Oct 09 02:13:28 AM UTC 24
Finished Oct 09 02:14:57 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1086974425 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 354.prim_prince_test.1086974425
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/354.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/355.prim_prince_test.1579602538
Short name T325
Test name
Test status
Simulation time 1038902601 ps
CPU time 19.88 seconds
Started Oct 09 02:13:29 AM UTC 24
Finished Oct 09 02:13:55 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1579602538 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 355.prim_prince_test.1579602538
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/355.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/356.prim_prince_test.1845075071
Short name T338
Test name
Test status
Simulation time 1485030976 ps
CPU time 29.56 seconds
Started Oct 09 02:13:32 AM UTC 24
Finished Oct 09 02:14:09 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1845075071 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 356.prim_prince_test.1845075071
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/356.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/357.prim_prince_test.1407617613
Short name T357
Test name
Test status
Simulation time 2357047760 ps
CPU time 44.61 seconds
Started Oct 09 02:13:33 AM UTC 24
Finished Oct 09 02:14:30 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1407617613 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 357.prim_prince_test.1407617613
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/357.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/358.prim_prince_test.4118472330
Short name T354
Test name
Test status
Simulation time 2195261258 ps
CPU time 41.49 seconds
Started Oct 09 02:13:34 AM UTC 24
Finished Oct 09 02:14:27 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4118472330 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 358.prim_prince_test.4118472330
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/358.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/359.prim_prince_test.1803815489
Short name T393
Test name
Test status
Simulation time 3710904010 ps
CPU time 70.51 seconds
Started Oct 09 02:13:35 AM UTC 24
Finished Oct 09 02:15:05 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1803815489 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 359.prim_prince_test.1803815489
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/359.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/36.prim_prince_test.2389142357
Short name T42
Test name
Test status
Simulation time 2248339165 ps
CPU time 44.04 seconds
Started Oct 09 02:08:04 AM UTC 24
Finished Oct 09 02:09:00 AM UTC 24
Peak memory 155028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2389142357 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 36.prim_prince_test.2389142357
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/36.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/360.prim_prince_test.1169906613
Short name T376
Test name
Test status
Simulation time 3035936830 ps
CPU time 59.34 seconds
Started Oct 09 02:13:36 AM UTC 24
Finished Oct 09 02:14:52 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1169906613 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 360.prim_prince_test.1169906613
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/360.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/361.prim_prince_test.844103409
Short name T382
Test name
Test status
Simulation time 3050479403 ps
CPU time 61.19 seconds
Started Oct 09 02:13:36 AM UTC 24
Finished Oct 09 02:14:54 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=844103409 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 361.prim_prince_test.844103409
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/361.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/362.prim_prince_test.1672956294
Short name T332
Test name
Test status
Simulation time 1024940670 ps
CPU time 20.51 seconds
Started Oct 09 02:13:36 AM UTC 24
Finished Oct 09 02:14:03 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1672956294 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 362.prim_prince_test.1672956294
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/362.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/363.prim_prince_test.1402088167
Short name T350
Test name
Test status
Simulation time 1666859116 ps
CPU time 33.43 seconds
Started Oct 09 02:13:38 AM UTC 24
Finished Oct 09 02:14:20 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1402088167 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 363.prim_prince_test.1402088167
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/363.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/364.prim_prince_test.866928847
Short name T368
Test name
Test status
Simulation time 2310081602 ps
CPU time 45.1 seconds
Started Oct 09 02:13:40 AM UTC 24
Finished Oct 09 02:14:37 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=866928847 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 364.prim_prince_test.866928847
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/364.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/365.prim_prince_test.3422396501
Short name T365
Test name
Test status
Simulation time 2109787399 ps
CPU time 40.2 seconds
Started Oct 09 02:13:42 AM UTC 24
Finished Oct 09 02:14:34 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3422396501 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 365.prim_prince_test.3422396501
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/365.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/366.prim_prince_test.1439551253
Short name T355
Test name
Test status
Simulation time 1922297692 ps
CPU time 36.46 seconds
Started Oct 09 02:13:42 AM UTC 24
Finished Oct 09 02:14:29 AM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1439551253 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 366.prim_prince_test.1439551253
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/366.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/367.prim_prince_test.2607371339
Short name T339
Test name
Test status
Simulation time 955225690 ps
CPU time 18.49 seconds
Started Oct 09 02:13:45 AM UTC 24
Finished Oct 09 02:14:10 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2607371339 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 367.prim_prince_test.2607371339
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/367.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/368.prim_prince_test.3535659123
Short name T364
Test name
Test status
Simulation time 1912428539 ps
CPU time 37.14 seconds
Started Oct 09 02:13:45 AM UTC 24
Finished Oct 09 02:14:33 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3535659123 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 368.prim_prince_test.3535659123
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/368.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/369.prim_prince_test.2459258458
Short name T353
Test name
Test status
Simulation time 1572684789 ps
CPU time 31.95 seconds
Started Oct 09 02:13:45 AM UTC 24
Finished Oct 09 02:14:26 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2459258458 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 369.prim_prince_test.2459258458
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/369.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/37.prim_prince_test.747050897
Short name T12
Test name
Test status
Simulation time 923560387 ps
CPU time 18.52 seconds
Started Oct 09 02:08:04 AM UTC 24
Finished Oct 09 02:08:28 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=747050897 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 37.prim_prince_test.747050897
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/37.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/370.prim_prince_test.106891466
Short name T374
Test name
Test status
Simulation time 2439497623 ps
CPU time 49.1 seconds
Started Oct 09 02:13:49 AM UTC 24
Finished Oct 09 02:14:51 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=106891466 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 370.prim_prince_test.106891466
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/370.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/371.prim_prince_test.1006453603
Short name T392
Test name
Test status
Simulation time 3012331636 ps
CPU time 57.67 seconds
Started Oct 09 02:13:49 AM UTC 24
Finished Oct 09 02:15:03 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1006453603 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 371.prim_prince_test.1006453603
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/371.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/372.prim_prince_test.216702145
Short name T370
Test name
Test status
Simulation time 2321561907 ps
CPU time 44.34 seconds
Started Oct 09 02:13:49 AM UTC 24
Finished Oct 09 02:14:46 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=216702145 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 372.prim_prince_test.216702145
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/372.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/373.prim_prince_test.3519115630
Short name T395
Test name
Test status
Simulation time 3013407164 ps
CPU time 59.82 seconds
Started Oct 09 02:13:50 AM UTC 24
Finished Oct 09 02:15:06 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3519115630 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 373.prim_prince_test.3519115630
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/373.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/374.prim_prince_test.93677575
Short name T400
Test name
Test status
Simulation time 3534923961 ps
CPU time 66.64 seconds
Started Oct 09 02:13:50 AM UTC 24
Finished Oct 09 02:15:16 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=93677575 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 374.prim_prince_test.93677575
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/374.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/375.prim_prince_test.2380793406
Short name T352
Test name
Test status
Simulation time 1300583496 ps
CPU time 26.78 seconds
Started Oct 09 02:13:51 AM UTC 24
Finished Oct 09 02:14:26 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2380793406 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 375.prim_prince_test.2380793406
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/375.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/376.prim_prince_test.1889978500
Short name T390
Test name
Test status
Simulation time 2808093903 ps
CPU time 54.31 seconds
Started Oct 09 02:13:51 AM UTC 24
Finished Oct 09 02:15:01 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1889978500 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 376.prim_prince_test.1889978500
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/376.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/377.prim_prince_test.2189013966
Short name T396
Test name
Test status
Simulation time 2948893817 ps
CPU time 56.9 seconds
Started Oct 09 02:13:54 AM UTC 24
Finished Oct 09 02:15:06 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2189013966 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 377.prim_prince_test.2189013966
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/377.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/378.prim_prince_test.1988152425
Short name T375
Test name
Test status
Simulation time 2138772529 ps
CPU time 43.61 seconds
Started Oct 09 02:13:56 AM UTC 24
Finished Oct 09 02:14:51 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1988152425 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 378.prim_prince_test.1988152425
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/378.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/379.prim_prince_test.4007879339
Short name T404
Test name
Test status
Simulation time 3278794085 ps
CPU time 64.06 seconds
Started Oct 09 02:13:56 AM UTC 24
Finished Oct 09 02:15:18 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4007879339 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 379.prim_prince_test.4007879339
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/379.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/38.prim_prince_test.3878937808
Short name T46
Test name
Test status
Simulation time 2546534538 ps
CPU time 47.37 seconds
Started Oct 09 02:08:04 AM UTC 24
Finished Oct 09 02:09:06 AM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3878937808 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 38.prim_prince_test.3878937808
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/38.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/380.prim_prince_test.48773613
Short name T406
Test name
Test status
Simulation time 3373133029 ps
CPU time 64.33 seconds
Started Oct 09 02:13:56 AM UTC 24
Finished Oct 09 02:15:19 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=48773613 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 380.prim_prince_test.48773613
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/380.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/381.prim_prince_test.1950354529
Short name T358
Test name
Test status
Simulation time 1300720658 ps
CPU time 27.1 seconds
Started Oct 09 02:13:56 AM UTC 24
Finished Oct 09 02:14:31 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1950354529 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 381.prim_prince_test.1950354529
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/381.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/382.prim_prince_test.687357499
Short name T397
Test name
Test status
Simulation time 2825787713 ps
CPU time 55.28 seconds
Started Oct 09 02:13:58 AM UTC 24
Finished Oct 09 02:15:09 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=687357499 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 382.prim_prince_test.687357499
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/382.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/383.prim_prince_test.2014497083
Short name T416
Test name
Test status
Simulation time 3534168993 ps
CPU time 69.36 seconds
Started Oct 09 02:14:00 AM UTC 24
Finished Oct 09 02:15:27 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2014497083 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 383.prim_prince_test.2014497083
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/383.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/384.prim_prince_test.3105650428
Short name T412
Test name
Test status
Simulation time 3331975760 ps
CPU time 65.22 seconds
Started Oct 09 02:14:03 AM UTC 24
Finished Oct 09 02:15:25 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3105650428 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 384.prim_prince_test.3105650428
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/384.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/385.prim_prince_test.2121819631
Short name T380
Test name
Test status
Simulation time 1894165179 ps
CPU time 37.84 seconds
Started Oct 09 02:14:04 AM UTC 24
Finished Oct 09 02:14:53 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2121819631 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 385.prim_prince_test.2121819631
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/385.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/386.prim_prince_test.680764394
Short name T360
Test name
Test status
Simulation time 994113538 ps
CPU time 20.87 seconds
Started Oct 09 02:14:04 AM UTC 24
Finished Oct 09 02:14:31 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=680764394 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 386.prim_prince_test.680764394
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/386.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/387.prim_prince_test.2547344560
Short name T361
Test name
Test status
Simulation time 1008763791 ps
CPU time 20.9 seconds
Started Oct 09 02:14:04 AM UTC 24
Finished Oct 09 02:14:31 AM UTC 24
Peak memory 154916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2547344560 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 387.prim_prince_test.2547344560
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/387.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/388.prim_prince_test.276349387
Short name T427
Test name
Test status
Simulation time 3732050312 ps
CPU time 72.51 seconds
Started Oct 09 02:14:04 AM UTC 24
Finished Oct 09 02:15:36 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=276349387 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 388.prim_prince_test.276349387
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/388.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/389.prim_prince_test.2652020521
Short name T384
Test name
Test status
Simulation time 2062021706 ps
CPU time 39.19 seconds
Started Oct 09 02:14:04 AM UTC 24
Finished Oct 09 02:14:55 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2652020521 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 389.prim_prince_test.2652020521
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/389.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/39.prim_prince_test.4239467597
Short name T54
Test name
Test status
Simulation time 3008952330 ps
CPU time 57.14 seconds
Started Oct 09 02:08:04 AM UTC 24
Finished Oct 09 02:09:17 AM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4239467597 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 39.prim_prince_test.4239467597
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/39.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/390.prim_prince_test.233988482
Short name T388
Test name
Test status
Simulation time 2085385651 ps
CPU time 41.72 seconds
Started Oct 09 02:14:07 AM UTC 24
Finished Oct 09 02:15:00 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=233988482 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 390.prim_prince_test.233988482
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/390.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/391.prim_prince_test.1250758989
Short name T372
Test name
Test status
Simulation time 1545342142 ps
CPU time 30.43 seconds
Started Oct 09 02:14:09 AM UTC 24
Finished Oct 09 02:14:48 AM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1250758989 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 391.prim_prince_test.1250758989
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/391.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/392.prim_prince_test.2740456578
Short name T409
Test name
Test status
Simulation time 2816630601 ps
CPU time 55.04 seconds
Started Oct 09 02:14:10 AM UTC 24
Finished Oct 09 02:15:20 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2740456578 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 392.prim_prince_test.2740456578
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/392.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/393.prim_prince_test.318745176
Short name T425
Test name
Test status
Simulation time 3413864566 ps
CPU time 65.86 seconds
Started Oct 09 02:14:10 AM UTC 24
Finished Oct 09 02:15:34 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=318745176 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 393.prim_prince_test.318745176
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/393.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/394.prim_prince_test.1468693723
Short name T419
Test name
Test status
Simulation time 3216314597 ps
CPU time 61.19 seconds
Started Oct 09 02:14:10 AM UTC 24
Finished Oct 09 02:15:29 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1468693723 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 394.prim_prince_test.1468693723
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/394.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/395.prim_prince_test.4007142949
Short name T387
Test name
Test status
Simulation time 1932895324 ps
CPU time 38.65 seconds
Started Oct 09 02:14:10 AM UTC 24
Finished Oct 09 02:15:00 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4007142949 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 395.prim_prince_test.4007142949
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/395.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/396.prim_prince_test.1499776796
Short name T413
Test name
Test status
Simulation time 3047772439 ps
CPU time 59.25 seconds
Started Oct 09 02:14:12 AM UTC 24
Finished Oct 09 02:15:27 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1499776796 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 396.prim_prince_test.1499776796
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/396.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/397.prim_prince_test.2894272167
Short name T383
Test name
Test status
Simulation time 1671640533 ps
CPU time 32.65 seconds
Started Oct 09 02:14:13 AM UTC 24
Finished Oct 09 02:14:55 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2894272167 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 397.prim_prince_test.2894272167
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/397.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/398.prim_prince_test.881002982
Short name T367
Test name
Test status
Simulation time 864192691 ps
CPU time 17.17 seconds
Started Oct 09 02:14:13 AM UTC 24
Finished Oct 09 02:14:36 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=881002982 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 398.prim_prince_test.881002982
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/398.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/399.prim_prince_test.2394155795
Short name T398
Test name
Test status
Simulation time 2288349903 ps
CPU time 43.09 seconds
Started Oct 09 02:14:14 AM UTC 24
Finished Oct 09 02:15:10 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2394155795 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 399.prim_prince_test.2394155795
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/399.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/4.prim_prince_test.80429850
Short name T14
Test name
Test status
Simulation time 2917043590 ps
CPU time 48.61 seconds
Started Oct 09 02:07:26 AM UTC 24
Finished Oct 09 02:08:30 AM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=80429850 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 4.prim_prince_test.80429850
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/4.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/40.prim_prince_test.1119348555
Short name T45
Test name
Test status
Simulation time 2451338359 ps
CPU time 46.84 seconds
Started Oct 09 02:08:04 AM UTC 24
Finished Oct 09 02:09:05 AM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1119348555 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 40.prim_prince_test.1119348555
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/40.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/400.prim_prince_test.4216226176
Short name T422
Test name
Test status
Simulation time 3104829144 ps
CPU time 60.44 seconds
Started Oct 09 02:14:14 AM UTC 24
Finished Oct 09 02:15:31 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4216226176 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 400.prim_prince_test.4216226176
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/400.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/401.prim_prince_test.2472900645
Short name T385
Test name
Test status
Simulation time 1607328537 ps
CPU time 32.19 seconds
Started Oct 09 02:14:16 AM UTC 24
Finished Oct 09 02:14:57 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2472900645 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 401.prim_prince_test.2472900645
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/401.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/402.prim_prince_test.3892499526
Short name T369
Test name
Test status
Simulation time 1126895799 ps
CPU time 23.17 seconds
Started Oct 09 02:14:16 AM UTC 24
Finished Oct 09 02:14:45 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3892499526 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 402.prim_prince_test.3892499526
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/402.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/403.prim_prince_test.792057272
Short name T411
Test name
Test status
Simulation time 2594638919 ps
CPU time 50.46 seconds
Started Oct 09 02:14:17 AM UTC 24
Finished Oct 09 02:15:21 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=792057272 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 403.prim_prince_test.792057272
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/403.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/404.prim_prince_test.3336644657
Short name T407
Test name
Test status
Simulation time 2438793481 ps
CPU time 47.74 seconds
Started Oct 09 02:14:18 AM UTC 24
Finished Oct 09 02:15:19 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3336644657 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 404.prim_prince_test.3336644657
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/404.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/405.prim_prince_test.1691099164
Short name T410
Test name
Test status
Simulation time 2430377337 ps
CPU time 46.04 seconds
Started Oct 09 02:14:21 AM UTC 24
Finished Oct 09 02:15:20 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1691099164 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 405.prim_prince_test.1691099164
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/405.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/406.prim_prince_test.3163845359
Short name T402
Test name
Test status
Simulation time 2239658271 ps
CPU time 42.81 seconds
Started Oct 09 02:14:21 AM UTC 24
Finished Oct 09 02:15:16 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3163845359 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 406.prim_prince_test.3163845359
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/406.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/407.prim_prince_test.822684770
Short name T399
Test name
Test status
Simulation time 1907187271 ps
CPU time 37.3 seconds
Started Oct 09 02:14:24 AM UTC 24
Finished Oct 09 02:15:12 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=822684770 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 407.prim_prince_test.822684770
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/407.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/408.prim_prince_test.2561091110
Short name T373
Test name
Test status
Simulation time 819143852 ps
CPU time 16.16 seconds
Started Oct 09 02:14:27 AM UTC 24
Finished Oct 09 02:14:49 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2561091110 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 408.prim_prince_test.2561091110
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/408.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/409.prim_prince_test.2920407418
Short name T389
Test name
Test status
Simulation time 1315942151 ps
CPU time 25.92 seconds
Started Oct 09 02:14:27 AM UTC 24
Finished Oct 09 02:15:01 AM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2920407418 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 409.prim_prince_test.2920407418
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/409.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/41.prim_prince_test.4162131472
Short name T11
Test name
Test status
Simulation time 901803888 ps
CPU time 17.1 seconds
Started Oct 09 02:08:04 AM UTC 24
Finished Oct 09 02:08:27 AM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4162131472 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 41.prim_prince_test.4162131472
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/41.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/410.prim_prince_test.1962314782
Short name T418
Test name
Test status
Simulation time 2420922845 ps
CPU time 46.94 seconds
Started Oct 09 02:14:28 AM UTC 24
Finished Oct 09 02:15:28 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1962314782 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 410.prim_prince_test.1962314782
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/410.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/411.prim_prince_test.1665366436
Short name T394
Test name
Test status
Simulation time 1409218961 ps
CPU time 26.81 seconds
Started Oct 09 02:14:30 AM UTC 24
Finished Oct 09 02:15:05 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1665366436 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 411.prim_prince_test.1665366436
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/411.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/412.prim_prince_test.711062719
Short name T378
Test name
Test status
Simulation time 785870722 ps
CPU time 15.49 seconds
Started Oct 09 02:14:32 AM UTC 24
Finished Oct 09 02:14:52 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=711062719 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 412.prim_prince_test.711062719
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/412.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/413.prim_prince_test.153096714
Short name T439
Test name
Test status
Simulation time 2994814706 ps
CPU time 56.38 seconds
Started Oct 09 02:14:32 AM UTC 24
Finished Oct 09 02:15:44 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=153096714 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 413.prim_prince_test.153096714
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/413.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/414.prim_prince_test.2636932554
Short name T432
Test name
Test status
Simulation time 2824503145 ps
CPU time 53.41 seconds
Started Oct 09 02:14:32 AM UTC 24
Finished Oct 09 02:15:40 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2636932554 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 414.prim_prince_test.2636932554
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/414.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/415.prim_prince_test.3114111625
Short name T381
Test name
Test status
Simulation time 795216267 ps
CPU time 16.26 seconds
Started Oct 09 02:14:32 AM UTC 24
Finished Oct 09 02:14:53 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3114111625 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 415.prim_prince_test.3114111625
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/415.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/416.prim_prince_test.3397718369
Short name T391
Test name
Test status
Simulation time 1107173665 ps
CPU time 21.65 seconds
Started Oct 09 02:14:33 AM UTC 24
Finished Oct 09 02:15:01 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3397718369 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 416.prim_prince_test.3397718369
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/416.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/417.prim_prince_test.544019045
Short name T434
Test name
Test status
Simulation time 2808175667 ps
CPU time 53.3 seconds
Started Oct 09 02:14:33 AM UTC 24
Finished Oct 09 02:15:41 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=544019045 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 417.prim_prince_test.544019045
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/417.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/418.prim_prince_test.2083638926
Short name T437
Test name
Test status
Simulation time 2906500477 ps
CPU time 55.17 seconds
Started Oct 09 02:14:33 AM UTC 24
Finished Oct 09 02:15:43 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2083638926 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 418.prim_prince_test.2083638926
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/418.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/419.prim_prince_test.1934535924
Short name T408
Test name
Test status
Simulation time 1780383923 ps
CPU time 34.26 seconds
Started Oct 09 02:14:35 AM UTC 24
Finished Oct 09 02:15:19 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1934535924 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 419.prim_prince_test.1934535924
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/419.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/42.prim_prince_test.2670809517
Short name T49
Test name
Test status
Simulation time 2817677054 ps
CPU time 52.96 seconds
Started Oct 09 02:08:05 AM UTC 24
Finished Oct 09 02:09:13 AM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2670809517 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 42.prim_prince_test.2670809517
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/42.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/420.prim_prince_test.4037565055
Short name T424
Test name
Test status
Simulation time 2443633643 ps
CPU time 46.21 seconds
Started Oct 09 02:14:35 AM UTC 24
Finished Oct 09 02:15:34 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4037565055 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 420.prim_prince_test.4037565055
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/420.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/421.prim_prince_test.345321309
Short name T454
Test name
Test status
Simulation time 3601907862 ps
CPU time 68.41 seconds
Started Oct 09 02:14:35 AM UTC 24
Finished Oct 09 02:16:02 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=345321309 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 421.prim_prince_test.345321309
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/421.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/422.prim_prince_test.4088301472
Short name T420
Test name
Test status
Simulation time 2174252479 ps
CPU time 41.68 seconds
Started Oct 09 02:14:36 AM UTC 24
Finished Oct 09 02:15:29 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4088301472 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 422.prim_prince_test.4088301472
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/422.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/423.prim_prince_test.3428891809
Short name T442
Test name
Test status
Simulation time 2883954465 ps
CPU time 55.01 seconds
Started Oct 09 02:14:36 AM UTC 24
Finished Oct 09 02:15:46 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3428891809 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 423.prim_prince_test.3428891809
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/423.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/424.prim_prince_test.2211778490
Short name T449
Test name
Test status
Simulation time 3258513344 ps
CPU time 61.53 seconds
Started Oct 09 02:14:38 AM UTC 24
Finished Oct 09 02:15:57 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2211778490 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 424.prim_prince_test.2211778490
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/424.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/425.prim_prince_test.3706074181
Short name T436
Test name
Test status
Simulation time 2300460259 ps
CPU time 43.38 seconds
Started Oct 09 02:14:47 AM UTC 24
Finished Oct 09 02:15:42 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3706074181 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 425.prim_prince_test.3706074181
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/425.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/426.prim_prince_test.2201005397
Short name T457
Test name
Test status
Simulation time 3278829923 ps
CPU time 61.65 seconds
Started Oct 09 02:14:47 AM UTC 24
Finished Oct 09 02:16:05 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2201005397 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 426.prim_prince_test.2201005397
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/426.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/427.prim_prince_test.3706427604
Short name T444
Test name
Test status
Simulation time 2546703895 ps
CPU time 47.89 seconds
Started Oct 09 02:14:48 AM UTC 24
Finished Oct 09 02:15:49 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3706427604 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 427.prim_prince_test.3706427604
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/427.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/428.prim_prince_test.3131716481
Short name T429
Test name
Test status
Simulation time 1998742179 ps
CPU time 37.9 seconds
Started Oct 09 02:14:49 AM UTC 24
Finished Oct 09 02:15:37 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3131716481 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 428.prim_prince_test.3131716481
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/428.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/429.prim_prince_test.2976991354
Short name T405
Test name
Test status
Simulation time 1153478627 ps
CPU time 21.96 seconds
Started Oct 09 02:14:49 AM UTC 24
Finished Oct 09 02:15:18 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2976991354 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 429.prim_prince_test.2976991354
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/429.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/43.prim_prince_test.3062242410
Short name T19
Test name
Test status
Simulation time 1272555169 ps
CPU time 24.91 seconds
Started Oct 09 02:08:05 AM UTC 24
Finished Oct 09 02:08:37 AM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3062242410 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 43.prim_prince_test.3062242410
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/43.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/430.prim_prince_test.4259492750
Short name T451
Test name
Test status
Simulation time 2714875038 ps
CPU time 51.27 seconds
Started Oct 09 02:14:52 AM UTC 24
Finished Oct 09 02:15:58 AM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4259492750 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 430.prim_prince_test.4259492750
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/430.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/431.prim_prince_test.1567180319
Short name T403
Test name
Test status
Simulation time 1002592894 ps
CPU time 19.06 seconds
Started Oct 09 02:14:52 AM UTC 24
Finished Oct 09 02:15:17 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1567180319 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 431.prim_prince_test.1567180319
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/431.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/432.prim_prince_test.3371172002
Short name T458
Test name
Test status
Simulation time 2979368384 ps
CPU time 55.86 seconds
Started Oct 09 02:14:54 AM UTC 24
Finished Oct 09 02:16:05 AM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3371172002 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 432.prim_prince_test.3371172002
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/432.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/433.prim_prince_test.2236145733
Short name T446
Test name
Test status
Simulation time 2271839079 ps
CPU time 42.95 seconds
Started Oct 09 02:14:54 AM UTC 24
Finished Oct 09 02:15:49 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2236145733 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 433.prim_prince_test.2236145733
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/433.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/434.prim_prince_test.2963449932
Short name T438
Test name
Test status
Simulation time 2037432482 ps
CPU time 38.22 seconds
Started Oct 09 02:14:54 AM UTC 24
Finished Oct 09 02:15:44 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2963449932 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 434.prim_prince_test.2963449932
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/434.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/435.prim_prince_test.189048076
Short name T421
Test name
Test status
Simulation time 1427034800 ps
CPU time 27.21 seconds
Started Oct 09 02:14:54 AM UTC 24
Finished Oct 09 02:15:30 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=189048076 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 435.prim_prince_test.189048076
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/435.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/436.prim_prince_test.2118251800
Short name T428
Test name
Test status
Simulation time 1706919195 ps
CPU time 32.69 seconds
Started Oct 09 02:14:54 AM UTC 24
Finished Oct 09 02:15:36 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2118251800 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 436.prim_prince_test.2118251800
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/436.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/437.prim_prince_test.3243791872
Short name T462
Test name
Test status
Simulation time 3070828484 ps
CPU time 57.67 seconds
Started Oct 09 02:14:54 AM UTC 24
Finished Oct 09 02:16:08 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3243791872 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 437.prim_prince_test.3243791872
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/437.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/438.prim_prince_test.3648129241
Short name T460
Test name
Test status
Simulation time 2946157003 ps
CPU time 55.28 seconds
Started Oct 09 02:14:56 AM UTC 24
Finished Oct 09 02:16:06 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3648129241 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 438.prim_prince_test.3648129241
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/438.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/439.prim_prince_test.1929200822
Short name T448
Test name
Test status
Simulation time 2499012538 ps
CPU time 47.11 seconds
Started Oct 09 02:14:56 AM UTC 24
Finished Oct 09 02:15:56 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1929200822 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 439.prim_prince_test.1929200822
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/439.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/44.prim_prince_test.4196247065
Short name T20
Test name
Test status
Simulation time 1353835845 ps
CPU time 25.7 seconds
Started Oct 09 02:08:05 AM UTC 24
Finished Oct 09 02:08:38 AM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4196247065 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 44.prim_prince_test.4196247065
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/44.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/440.prim_prince_test.4189217962
Short name T401
Test name
Test status
Simulation time 796166213 ps
CPU time 15.4 seconds
Started Oct 09 02:14:56 AM UTC 24
Finished Oct 09 02:15:16 AM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4189217962 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 440.prim_prince_test.4189217962
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/440.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/441.prim_prince_test.2746753862
Short name T440
Test name
Test status
Simulation time 1932814152 ps
CPU time 36.39 seconds
Started Oct 09 02:14:58 AM UTC 24
Finished Oct 09 02:15:45 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2746753862 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 441.prim_prince_test.2746753862
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/441.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/442.prim_prince_test.745998016
Short name T415
Test name
Test status
Simulation time 1174083195 ps
CPU time 22.43 seconds
Started Oct 09 02:14:58 AM UTC 24
Finished Oct 09 02:15:27 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=745998016 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 442.prim_prince_test.745998016
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/442.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/443.prim_prince_test.3763524765
Short name T473
Test name
Test status
Simulation time 3485230067 ps
CPU time 64.83 seconds
Started Oct 09 02:15:00 AM UTC 24
Finished Oct 09 02:16:23 AM UTC 24
Peak memory 155032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3763524765 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 443.prim_prince_test.3763524765
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/443.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/444.prim_prince_test.4114469623
Short name T417
Test name
Test status
Simulation time 1084070595 ps
CPU time 20.66 seconds
Started Oct 09 02:15:00 AM UTC 24
Finished Oct 09 02:15:27 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4114469623 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 444.prim_prince_test.4114469623
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/444.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/445.prim_prince_test.2187824010
Short name T414
Test name
Test status
Simulation time 997080717 ps
CPU time 19.2 seconds
Started Oct 09 02:15:02 AM UTC 24
Finished Oct 09 02:15:27 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2187824010 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 445.prim_prince_test.2187824010
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/445.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/446.prim_prince_test.1772540644
Short name T470
Test name
Test status
Simulation time 3305560342 ps
CPU time 62.43 seconds
Started Oct 09 02:15:02 AM UTC 24
Finished Oct 09 02:16:21 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1772540644 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 446.prim_prince_test.1772540644
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/446.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/447.prim_prince_test.3421139935
Short name T435
Test name
Test status
Simulation time 1626215458 ps
CPU time 30.88 seconds
Started Oct 09 02:15:02 AM UTC 24
Finished Oct 09 02:15:41 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3421139935 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 447.prim_prince_test.3421139935
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/447.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/448.prim_prince_test.4217765839
Short name T445
Test name
Test status
Simulation time 1873591903 ps
CPU time 35.16 seconds
Started Oct 09 02:15:04 AM UTC 24
Finished Oct 09 02:15:49 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4217765839 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 448.prim_prince_test.4217765839
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/448.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/449.prim_prince_test.2798299988
Short name T423
Test name
Test status
Simulation time 1031406407 ps
CPU time 19.89 seconds
Started Oct 09 02:15:05 AM UTC 24
Finished Oct 09 02:15:31 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2798299988 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 449.prim_prince_test.2798299988
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/449.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/45.prim_prince_test.2078487742
Short name T53
Test name
Test status
Simulation time 2953970978 ps
CPU time 57.1 seconds
Started Oct 09 02:08:05 AM UTC 24
Finished Oct 09 02:09:17 AM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2078487742 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 45.prim_prince_test.2078487742
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/45.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/450.prim_prince_test.3672409277
Short name T472
Test name
Test status
Simulation time 3223124355 ps
CPU time 59.78 seconds
Started Oct 09 02:15:07 AM UTC 24
Finished Oct 09 02:16:23 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3672409277 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 450.prim_prince_test.3672409277
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/450.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/451.prim_prince_test.383954247
Short name T468
Test name
Test status
Simulation time 3069523604 ps
CPU time 57.4 seconds
Started Oct 09 02:15:07 AM UTC 24
Finished Oct 09 02:16:20 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=383954247 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 451.prim_prince_test.383954247
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/451.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/452.prim_prince_test.151038772
Short name T456
Test name
Test status
Simulation time 2334428318 ps
CPU time 44.12 seconds
Started Oct 09 02:15:08 AM UTC 24
Finished Oct 09 02:16:04 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=151038772 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 452.prim_prince_test.151038772
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/452.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/453.prim_prince_test.1666849722
Short name T485
Test name
Test status
Simulation time 3706305201 ps
CPU time 70.13 seconds
Started Oct 09 02:15:10 AM UTC 24
Finished Oct 09 02:16:39 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1666849722 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 453.prim_prince_test.1666849722
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/453.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/454.prim_prince_test.873375709
Short name T426
Test name
Test status
Simulation time 982540910 ps
CPU time 18.74 seconds
Started Oct 09 02:15:11 AM UTC 24
Finished Oct 09 02:15:35 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=873375709 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 454.prim_prince_test.873375709
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/454.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/455.prim_prince_test.4064363524
Short name T474
Test name
Test status
Simulation time 3030973164 ps
CPU time 56.04 seconds
Started Oct 09 02:15:13 AM UTC 24
Finished Oct 09 02:16:25 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4064363524 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 455.prim_prince_test.4064363524
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/455.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/456.prim_prince_test.2854312739
Short name T431
Test name
Test status
Simulation time 955120947 ps
CPU time 18.3 seconds
Started Oct 09 02:15:14 AM UTC 24
Finished Oct 09 02:15:38 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2854312739 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 456.prim_prince_test.2854312739
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/456.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/457.prim_prince_test.3187899455
Short name T441
Test name
Test status
Simulation time 1155210783 ps
CPU time 22.39 seconds
Started Oct 09 02:15:17 AM UTC 24
Finished Oct 09 02:15:46 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3187899455 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 457.prim_prince_test.3187899455
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/457.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/458.prim_prince_test.3531612705
Short name T455
Test name
Test status
Simulation time 1890799261 ps
CPU time 35.77 seconds
Started Oct 09 02:15:17 AM UTC 24
Finished Oct 09 02:16:03 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3531612705 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 458.prim_prince_test.3531612705
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/458.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/459.prim_prince_test.1558858678
Short name T481
Test name
Test status
Simulation time 3208885496 ps
CPU time 60.71 seconds
Started Oct 09 02:15:18 AM UTC 24
Finished Oct 09 02:16:35 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1558858678 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 459.prim_prince_test.1558858678
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/459.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/46.prim_prince_test.2666085972
Short name T79
Test name
Test status
Simulation time 3735506634 ps
CPU time 72.02 seconds
Started Oct 09 02:08:05 AM UTC 24
Finished Oct 09 02:09:36 AM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2666085972 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 46.prim_prince_test.2666085972
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/46.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/460.prim_prince_test.4095084114
Short name T430
Test name
Test status
Simulation time 770950582 ps
CPU time 14.75 seconds
Started Oct 09 02:15:18 AM UTC 24
Finished Oct 09 02:15:38 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4095084114 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 460.prim_prince_test.4095084114
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/460.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/461.prim_prince_test.2008919435
Short name T491
Test name
Test status
Simulation time 3732420715 ps
CPU time 67.58 seconds
Started Oct 09 02:15:20 AM UTC 24
Finished Oct 09 02:16:47 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2008919435 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 461.prim_prince_test.2008919435
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/461.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/462.prim_prince_test.469803105
Short name T465
Test name
Test status
Simulation time 2290127639 ps
CPU time 43.42 seconds
Started Oct 09 02:15:20 AM UTC 24
Finished Oct 09 02:16:15 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=469803105 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 462.prim_prince_test.469803105
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/462.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/463.prim_prince_test.1604717181
Short name T443
Test name
Test status
Simulation time 1149107761 ps
CPU time 21.92 seconds
Started Oct 09 02:15:20 AM UTC 24
Finished Oct 09 02:15:48 AM UTC 24
Peak memory 154968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1604717181 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 463.prim_prince_test.1604717181
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/463.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/464.prim_prince_test.2757739206
Short name T479
Test name
Test status
Simulation time 2963058451 ps
CPU time 55.36 seconds
Started Oct 09 02:15:20 AM UTC 24
Finished Oct 09 02:16:30 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2757739206 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 464.prim_prince_test.2757739206
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/464.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/465.prim_prince_test.2372171898
Short name T477
Test name
Test status
Simulation time 2852509072 ps
CPU time 53.04 seconds
Started Oct 09 02:15:20 AM UTC 24
Finished Oct 09 02:16:28 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2372171898 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 465.prim_prince_test.2372171898
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/465.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/466.prim_prince_test.3860257518
Short name T433
Test name
Test status
Simulation time 762745332 ps
CPU time 14.68 seconds
Started Oct 09 02:15:21 AM UTC 24
Finished Oct 09 02:15:41 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3860257518 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 466.prim_prince_test.3860257518
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/466.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/467.prim_prince_test.3076663602
Short name T492
Test name
Test status
Simulation time 3588948853 ps
CPU time 67.34 seconds
Started Oct 09 02:15:21 AM UTC 24
Finished Oct 09 02:16:47 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3076663602 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 467.prim_prince_test.3076663602
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/467.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/468.prim_prince_test.803235897
Short name T476
Test name
Test status
Simulation time 2788203234 ps
CPU time 51.77 seconds
Started Oct 09 02:15:21 AM UTC 24
Finished Oct 09 02:16:28 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=803235897 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 468.prim_prince_test.803235897
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/468.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/469.prim_prince_test.2317633629
Short name T478
Test name
Test status
Simulation time 2722766449 ps
CPU time 50.32 seconds
Started Oct 09 02:15:26 AM UTC 24
Finished Oct 09 02:16:30 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2317633629 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 469.prim_prince_test.2317633629
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/469.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/47.prim_prince_test.4159147346
Short name T33
Test name
Test status
Simulation time 1747512075 ps
CPU time 34.15 seconds
Started Oct 09 02:08:05 AM UTC 24
Finished Oct 09 02:08:48 AM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4159147346 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 47.prim_prince_test.4159147346
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/47.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/470.prim_prince_test.1805624465
Short name T489
Test name
Test status
Simulation time 3135327179 ps
CPU time 59.2 seconds
Started Oct 09 02:15:28 AM UTC 24
Finished Oct 09 02:16:44 AM UTC 24
Peak memory 154992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1805624465 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 470.prim_prince_test.1805624465
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/470.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/471.prim_prince_test.3827280648
Short name T452
Test name
Test status
Simulation time 1207343773 ps
CPU time 23.07 seconds
Started Oct 09 02:15:28 AM UTC 24
Finished Oct 09 02:15:58 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3827280648 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 471.prim_prince_test.3827280648
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/471.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/472.prim_prince_test.3310452081
Short name T450
Test name
Test status
Simulation time 1159171567 ps
CPU time 22.21 seconds
Started Oct 09 02:15:29 AM UTC 24
Finished Oct 09 02:15:57 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3310452081 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 472.prim_prince_test.3310452081
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/472.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/473.prim_prince_test.2494484775
Short name T447
Test name
Test status
Simulation time 860039328 ps
CPU time 16.66 seconds
Started Oct 09 02:15:29 AM UTC 24
Finished Oct 09 02:15:50 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2494484775 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 473.prim_prince_test.2494484775
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/473.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/474.prim_prince_test.2490502301
Short name T461
Test name
Test status
Simulation time 1577171791 ps
CPU time 29.89 seconds
Started Oct 09 02:15:29 AM UTC 24
Finished Oct 09 02:16:07 AM UTC 24
Peak memory 154904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2490502301 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 474.prim_prince_test.2490502301
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/474.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/475.prim_prince_test.3635751909
Short name T484
Test name
Test status
Simulation time 2928823859 ps
CPU time 55.21 seconds
Started Oct 09 02:15:29 AM UTC 24
Finished Oct 09 02:16:39 AM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3635751909 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 475.prim_prince_test.3635751909
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/475.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/476.prim_prince_test.2912454344
Short name T469
Test name
Test status
Simulation time 2063342238 ps
CPU time 38.54 seconds
Started Oct 09 02:15:30 AM UTC 24
Finished Oct 09 02:16:20 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2912454344 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 476.prim_prince_test.2912454344
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/476.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/477.prim_prince_test.3422437761
Short name T453
Test name
Test status
Simulation time 1150530786 ps
CPU time 21.95 seconds
Started Oct 09 02:15:30 AM UTC 24
Finished Oct 09 02:15:59 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3422437761 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 477.prim_prince_test.3422437761
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/477.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/478.prim_prince_test.4169663768
Short name T466
Test name
Test status
Simulation time 1989261578 ps
CPU time 36.92 seconds
Started Oct 09 02:15:30 AM UTC 24
Finished Oct 09 02:16:18 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4169663768 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 478.prim_prince_test.4169663768
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/478.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/479.prim_prince_test.1598680037
Short name T475
Test name
Test status
Simulation time 2288877303 ps
CPU time 42.38 seconds
Started Oct 09 02:15:31 AM UTC 24
Finished Oct 09 02:16:26 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1598680037 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 479.prim_prince_test.1598680037
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/479.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/48.prim_prince_test.638356304
Short name T73
Test name
Test status
Simulation time 3410783541 ps
CPU time 65.91 seconds
Started Oct 09 02:08:08 AM UTC 24
Finished Oct 09 02:09:32 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=638356304 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 48.prim_prince_test.638356304
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/48.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/480.prim_prince_test.460145569
Short name T496
Test name
Test status
Simulation time 3442984896 ps
CPU time 61.8 seconds
Started Oct 09 02:15:32 AM UTC 24
Finished Oct 09 02:16:52 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=460145569 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 480.prim_prince_test.460145569
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/480.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/481.prim_prince_test.2583024139
Short name T497
Test name
Test status
Simulation time 3250853552 ps
CPU time 61.9 seconds
Started Oct 09 02:15:35 AM UTC 24
Finished Oct 09 02:16:54 AM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2583024139 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 481.prim_prince_test.2583024139
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/481.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/482.prim_prince_test.2330547772
Short name T488
Test name
Test status
Simulation time 2913619266 ps
CPU time 52.4 seconds
Started Oct 09 02:15:35 AM UTC 24
Finished Oct 09 02:16:43 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2330547772 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 482.prim_prince_test.2330547772
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/482.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/483.prim_prince_test.893070256
Short name T464
Test name
Test status
Simulation time 1460112928 ps
CPU time 27.67 seconds
Started Oct 09 02:15:36 AM UTC 24
Finished Oct 09 02:16:12 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=893070256 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 483.prim_prince_test.893070256
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/483.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/484.prim_prince_test.1099956713
Short name T486
Test name
Test status
Simulation time 2613131880 ps
CPU time 48.79 seconds
Started Oct 09 02:15:37 AM UTC 24
Finished Oct 09 02:16:40 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1099956713 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 484.prim_prince_test.1099956713
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/484.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/485.prim_prince_test.3836807419
Short name T459
Test name
Test status
Simulation time 1126721007 ps
CPU time 21.63 seconds
Started Oct 09 02:15:37 AM UTC 24
Finished Oct 09 02:16:05 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3836807419 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 485.prim_prince_test.3836807419
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/485.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/486.prim_prince_test.2988844884
Short name T463
Test name
Test status
Simulation time 1329311306 ps
CPU time 24.85 seconds
Started Oct 09 02:15:39 AM UTC 24
Finished Oct 09 02:16:11 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2988844884 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 486.prim_prince_test.2988844884
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/486.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/487.prim_prince_test.4201094110
Short name T467
Test name
Test status
Simulation time 1621738817 ps
CPU time 30.53 seconds
Started Oct 09 02:15:39 AM UTC 24
Finished Oct 09 02:16:18 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4201094110 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 487.prim_prince_test.4201094110
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/487.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/488.prim_prince_test.1243654334
Short name T494
Test name
Test status
Simulation time 3105497609 ps
CPU time 55.76 seconds
Started Oct 09 02:15:39 AM UTC 24
Finished Oct 09 02:16:51 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1243654334 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 488.prim_prince_test.1243654334
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/488.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/489.prim_prince_test.196499783
Short name T480
Test name
Test status
Simulation time 2151066548 ps
CPU time 40.72 seconds
Started Oct 09 02:15:41 AM UTC 24
Finished Oct 09 02:16:33 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=196499783 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 489.prim_prince_test.196499783
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/489.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/49.prim_prince_test.1005374856
Short name T18
Test name
Test status
Simulation time 1103146840 ps
CPU time 21.64 seconds
Started Oct 09 02:08:08 AM UTC 24
Finished Oct 09 02:08:37 AM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1005374856 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 49.prim_prince_test.1005374856
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/49.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/490.prim_prince_test.622475278
Short name T471
Test name
Test status
Simulation time 1666714434 ps
CPU time 31.5 seconds
Started Oct 09 02:15:41 AM UTC 24
Finished Oct 09 02:16:22 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=622475278 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 490.prim_prince_test.622475278
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/490.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/491.prim_prince_test.1029554669
Short name T490
Test name
Test status
Simulation time 2665583575 ps
CPU time 48.03 seconds
Started Oct 09 02:15:43 AM UTC 24
Finished Oct 09 02:16:45 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1029554669 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 491.prim_prince_test.1029554669
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/491.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/492.prim_prince_test.3208845545
Short name T499
Test name
Test status
Simulation time 3398370710 ps
CPU time 60.41 seconds
Started Oct 09 02:15:43 AM UTC 24
Finished Oct 09 02:17:01 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3208845545 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 492.prim_prince_test.3208845545
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/492.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/493.prim_prince_test.3155628071
Short name T498
Test name
Test status
Simulation time 3170215951 ps
CPU time 56.68 seconds
Started Oct 09 02:15:44 AM UTC 24
Finished Oct 09 02:16:58 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3155628071 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 493.prim_prince_test.3155628071
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/493.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/494.prim_prince_test.1295632701
Short name T495
Test name
Test status
Simulation time 2870432358 ps
CPU time 52.86 seconds
Started Oct 09 02:15:44 AM UTC 24
Finished Oct 09 02:16:52 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1295632701 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 494.prim_prince_test.1295632701
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/494.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/495.prim_prince_test.1491023554
Short name T483
Test name
Test status
Simulation time 2213430663 ps
CPU time 41.6 seconds
Started Oct 09 02:15:44 AM UTC 24
Finished Oct 09 02:16:38 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1491023554 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 495.prim_prince_test.1491023554
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/495.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/496.prim_prince_test.1049178098
Short name T482
Test name
Test status
Simulation time 2073648546 ps
CPU time 39 seconds
Started Oct 09 02:15:46 AM UTC 24
Finished Oct 09 02:16:35 AM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1049178098 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 496.prim_prince_test.1049178098
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/496.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/497.prim_prince_test.525774283
Short name T500
Test name
Test status
Simulation time 3489153274 ps
CPU time 62.47 seconds
Started Oct 09 02:15:46 AM UTC 24
Finished Oct 09 02:17:07 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=525774283 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 497.prim_prince_test.525774283
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/497.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/498.prim_prince_test.3942016602
Short name T487
Test name
Test status
Simulation time 2240559123 ps
CPU time 42.92 seconds
Started Oct 09 02:15:47 AM UTC 24
Finished Oct 09 02:16:42 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3942016602 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 498.prim_prince_test.3942016602
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/498.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/499.prim_prince_test.2966232036
Short name T493
Test name
Test status
Simulation time 2638393294 ps
CPU time 50.26 seconds
Started Oct 09 02:15:47 AM UTC 24
Finished Oct 09 02:16:51 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2966232036 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 499.prim_prince_test.2966232036
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/499.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/5.prim_prince_test.1502689157
Short name T23
Test name
Test status
Simulation time 3336144230 ps
CPU time 55.39 seconds
Started Oct 09 02:07:28 AM UTC 24
Finished Oct 09 02:08:41 AM UTC 24
Peak memory 154920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1502689157 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 5.prim_prince_test.1502689157
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/5.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/50.prim_prince_test.293051979
Short name T35
Test name
Test status
Simulation time 1739313933 ps
CPU time 33.88 seconds
Started Oct 09 02:08:08 AM UTC 24
Finished Oct 09 02:08:52 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=293051979 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 50.prim_prince_test.293051979
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/50.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/51.prim_prince_test.3443103010
Short name T74
Test name
Test status
Simulation time 3442813446 ps
CPU time 65.26 seconds
Started Oct 09 02:08:09 AM UTC 24
Finished Oct 09 02:09:32 AM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3443103010 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 51.prim_prince_test.3443103010
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/51.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/52.prim_prince_test.2278931916
Short name T58
Test name
Test status
Simulation time 2869948894 ps
CPU time 55.17 seconds
Started Oct 09 02:08:10 AM UTC 24
Finished Oct 09 02:09:20 AM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2278931916 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 52.prim_prince_test.2278931916
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/52.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/53.prim_prince_test.782574697
Short name T34
Test name
Test status
Simulation time 1601087896 ps
CPU time 30.3 seconds
Started Oct 09 02:08:10 AM UTC 24
Finished Oct 09 02:08:49 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=782574697 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 53.prim_prince_test.782574697
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/53.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/54.prim_prince_test.3973786555
Short name T56
Test name
Test status
Simulation time 2789362531 ps
CPU time 53.99 seconds
Started Oct 09 02:08:10 AM UTC 24
Finished Oct 09 02:09:18 AM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3973786555 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 54.prim_prince_test.3973786555
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/54.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/55.prim_prince_test.3207899458
Short name T76
Test name
Test status
Simulation time 3359118875 ps
CPU time 64.97 seconds
Started Oct 09 02:08:10 AM UTC 24
Finished Oct 09 02:09:32 AM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3207899458 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 55.prim_prince_test.3207899458
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/55.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/56.prim_prince_test.3918604711
Short name T63
Test name
Test status
Simulation time 2975741243 ps
CPU time 56 seconds
Started Oct 09 02:08:11 AM UTC 24
Finished Oct 09 02:09:23 AM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3918604711 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 56.prim_prince_test.3918604711
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/56.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/57.prim_prince_test.3516036570
Short name T22
Test name
Test status
Simulation time 1165040727 ps
CPU time 22.5 seconds
Started Oct 09 02:08:11 AM UTC 24
Finished Oct 09 02:08:40 AM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3516036570 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 57.prim_prince_test.3516036570
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/57.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/58.prim_prince_test.1488549333
Short name T78
Test name
Test status
Simulation time 3475222542 ps
CPU time 65.58 seconds
Started Oct 09 02:08:11 AM UTC 24
Finished Oct 09 02:09:35 AM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1488549333 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 58.prim_prince_test.1488549333
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/58.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/59.prim_prince_test.3531064720
Short name T29
Test name
Test status
Simulation time 1103900330 ps
CPU time 21.62 seconds
Started Oct 09 02:08:17 AM UTC 24
Finished Oct 09 02:08:45 AM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3531064720 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 59.prim_prince_test.3531064720
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/59.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/6.prim_prince_test.642947474
Short name T15
Test name
Test status
Simulation time 2788423692 ps
CPU time 47.57 seconds
Started Oct 09 02:07:28 AM UTC 24
Finished Oct 09 02:08:30 AM UTC 24
Peak memory 155048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=642947474 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 6.prim_prince_test.642947474
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/6.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/60.prim_prince_test.3979264453
Short name T77
Test name
Test status
Simulation time 2981332626 ps
CPU time 55.78 seconds
Started Oct 09 02:08:21 AM UTC 24
Finished Oct 09 02:09:32 AM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3979264453 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 60.prim_prince_test.3979264453
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/60.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/61.prim_prince_test.1478035068
Short name T31
Test name
Test status
Simulation time 897342033 ps
CPU time 17.22 seconds
Started Oct 09 02:08:23 AM UTC 24
Finished Oct 09 02:08:46 AM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1478035068 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 61.prim_prince_test.1478035068
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/61.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/62.prim_prince_test.504340412
Short name T38
Test name
Test status
Simulation time 1290426320 ps
CPU time 24.82 seconds
Started Oct 09 02:08:25 AM UTC 24
Finished Oct 09 02:08:57 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=504340412 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 62.prim_prince_test.504340412
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/62.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/63.prim_prince_test.2247162394
Short name T55
Test name
Test status
Simulation time 2097012679 ps
CPU time 39.76 seconds
Started Oct 09 02:08:27 AM UTC 24
Finished Oct 09 02:09:18 AM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2247162394 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 63.prim_prince_test.2247162394
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/63.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/64.prim_prince_test.2018789272
Short name T65
Test name
Test status
Simulation time 2345531182 ps
CPU time 43.63 seconds
Started Oct 09 02:08:29 AM UTC 24
Finished Oct 09 02:09:25 AM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2018789272 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 64.prim_prince_test.2018789272
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/64.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/65.prim_prince_test.1340143988
Short name T41
Test name
Test status
Simulation time 1173731925 ps
CPU time 22.84 seconds
Started Oct 09 02:08:29 AM UTC 24
Finished Oct 09 02:08:59 AM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1340143988 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 65.prim_prince_test.1340143988
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/65.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/66.prim_prince_test.2810054778
Short name T61
Test name
Test status
Simulation time 2052022393 ps
CPU time 38.73 seconds
Started Oct 09 02:08:31 AM UTC 24
Finished Oct 09 02:09:21 AM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2810054778 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 66.prim_prince_test.2810054778
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/66.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/67.prim_prince_test.1719954254
Short name T36
Test name
Test status
Simulation time 886037989 ps
CPU time 17.29 seconds
Started Oct 09 02:08:31 AM UTC 24
Finished Oct 09 02:08:54 AM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1719954254 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 67.prim_prince_test.1719954254
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/67.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/68.prim_prince_test.1804998826
Short name T37
Test name
Test status
Simulation time 896321759 ps
CPU time 17.46 seconds
Started Oct 09 02:08:31 AM UTC 24
Finished Oct 09 02:08:54 AM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1804998826 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 68.prim_prince_test.1804998826
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/68.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/69.prim_prince_test.2212400974
Short name T83
Test name
Test status
Simulation time 2656742253 ps
CPU time 50.11 seconds
Started Oct 09 02:08:36 AM UTC 24
Finished Oct 09 02:09:41 AM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2212400974 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 69.prim_prince_test.2212400974
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/69.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/7.prim_prince_test.828948000
Short name T2
Test name
Test status
Simulation time 1177638391 ps
CPU time 17.49 seconds
Started Oct 09 02:07:28 AM UTC 24
Finished Oct 09 02:07:52 AM UTC 24
Peak memory 154984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=828948000 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 7.prim_prince_test.828948000
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/7.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/70.prim_prince_test.641322246
Short name T98
Test name
Test status
Simulation time 3490897866 ps
CPU time 64.62 seconds
Started Oct 09 02:08:39 AM UTC 24
Finished Oct 09 02:10:02 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=641322246 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 70.prim_prince_test.641322246
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/70.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/71.prim_prince_test.1298558697
Short name T68
Test name
Test status
Simulation time 1935813074 ps
CPU time 37 seconds
Started Oct 09 02:08:39 AM UTC 24
Finished Oct 09 02:09:26 AM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1298558697 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 71.prim_prince_test.1298558697
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/71.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/72.prim_prince_test.1882758743
Short name T94
Test name
Test status
Simulation time 3164461661 ps
CPU time 62.25 seconds
Started Oct 09 02:08:39 AM UTC 24
Finished Oct 09 02:09:57 AM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1882758743 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 72.prim_prince_test.1882758743
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/72.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/73.prim_prince_test.3026207504
Short name T60
Test name
Test status
Simulation time 1699071538 ps
CPU time 31.75 seconds
Started Oct 09 02:08:39 AM UTC 24
Finished Oct 09 02:09:20 AM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3026207504 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 73.prim_prince_test.3026207504
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/73.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/74.prim_prince_test.3406904846
Short name T47
Test name
Test status
Simulation time 1165585402 ps
CPU time 22.94 seconds
Started Oct 09 02:08:41 AM UTC 24
Finished Oct 09 02:09:11 AM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3406904846 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 74.prim_prince_test.3406904846
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/74.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/75.prim_prince_test.1617863107
Short name T104
Test name
Test status
Simulation time 3446736337 ps
CPU time 64.98 seconds
Started Oct 09 02:08:41 AM UTC 24
Finished Oct 09 02:10:04 AM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1617863107 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 75.prim_prince_test.1617863107
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/75.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/76.prim_prince_test.2353672224
Short name T85
Test name
Test status
Simulation time 2475936468 ps
CPU time 48.51 seconds
Started Oct 09 02:08:43 AM UTC 24
Finished Oct 09 02:09:45 AM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2353672224 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 76.prim_prince_test.2353672224
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/76.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/77.prim_prince_test.923935974
Short name T59
Test name
Test status
Simulation time 1503900458 ps
CPU time 28.13 seconds
Started Oct 09 02:08:43 AM UTC 24
Finished Oct 09 02:09:20 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=923935974 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 77.prim_prince_test.923935974
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/77.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/78.prim_prince_test.228917718
Short name T71
Test name
Test status
Simulation time 1891732976 ps
CPU time 36.49 seconds
Started Oct 09 02:08:43 AM UTC 24
Finished Oct 09 02:09:30 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=228917718 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 78.prim_prince_test.228917718
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/78.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/79.prim_prince_test.1170485966
Short name T95
Test name
Test status
Simulation time 2916985036 ps
CPU time 58.15 seconds
Started Oct 09 02:08:45 AM UTC 24
Finished Oct 09 02:09:59 AM UTC 24
Peak memory 155032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1170485966 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 79.prim_prince_test.1170485966
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/79.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/8.prim_prince_test.192531088
Short name T4
Test name
Test status
Simulation time 1355937156 ps
CPU time 20.72 seconds
Started Oct 09 02:07:28 AM UTC 24
Finished Oct 09 02:07:57 AM UTC 24
Peak memory 154984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=192531088 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 8.prim_prince_test.192531088
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/8.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/80.prim_prince_test.1722643351
Short name T66
Test name
Test status
Simulation time 1637925470 ps
CPU time 31.91 seconds
Started Oct 09 02:08:45 AM UTC 24
Finished Oct 09 02:09:26 AM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1722643351 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 80.prim_prince_test.1722643351
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/80.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/81.prim_prince_test.2480849082
Short name T109
Test name
Test status
Simulation time 3597171732 ps
CPU time 68.17 seconds
Started Oct 09 02:08:45 AM UTC 24
Finished Oct 09 02:10:13 AM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2480849082 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 81.prim_prince_test.2480849082
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/81.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/82.prim_prince_test.390332700
Short name T92
Test name
Test status
Simulation time 2593955688 ps
CPU time 50.45 seconds
Started Oct 09 02:08:47 AM UTC 24
Finished Oct 09 02:09:51 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=390332700 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 82.prim_prince_test.390332700
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/82.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/83.prim_prince_test.779049803
Short name T69
Test name
Test status
Simulation time 1619094301 ps
CPU time 31.49 seconds
Started Oct 09 02:08:47 AM UTC 24
Finished Oct 09 02:09:28 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=779049803 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 83.prim_prince_test.779049803
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/83.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/84.prim_prince_test.297158249
Short name T52
Test name
Test status
Simulation time 1120987739 ps
CPU time 22.23 seconds
Started Oct 09 02:08:47 AM UTC 24
Finished Oct 09 02:09:16 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=297158249 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 84.prim_prince_test.297158249
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/84.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/85.prim_prince_test.1667489318
Short name T93
Test name
Test status
Simulation time 2772230666 ps
CPU time 52.37 seconds
Started Oct 09 02:08:49 AM UTC 24
Finished Oct 09 02:09:57 AM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1667489318 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 85.prim_prince_test.1667489318
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/85.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/86.prim_prince_test.3978947890
Short name T86
Test name
Test status
Simulation time 2222085966 ps
CPU time 43.29 seconds
Started Oct 09 02:08:49 AM UTC 24
Finished Oct 09 02:09:45 AM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3978947890 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 86.prim_prince_test.3978947890
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/86.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/87.prim_prince_test.919404938
Short name T97
Test name
Test status
Simulation time 2841375370 ps
CPU time 57 seconds
Started Oct 09 02:08:49 AM UTC 24
Finished Oct 09 02:10:02 AM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=919404938 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 87.prim_prince_test.919404938
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/87.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/88.prim_prince_test.99247290
Short name T72
Test name
Test status
Simulation time 1661270295 ps
CPU time 31.46 seconds
Started Oct 09 02:08:51 AM UTC 24
Finished Oct 09 02:09:31 AM UTC 24
Peak memory 154984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=99247290 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 88.prim_prince_test.99247290
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/88.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/89.prim_prince_test.3402555455
Short name T118
Test name
Test status
Simulation time 3656624972 ps
CPU time 73.29 seconds
Started Oct 09 02:08:53 AM UTC 24
Finished Oct 09 02:10:25 AM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3402555455 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 89.prim_prince_test.3402555455
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/89.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/9.prim_prince_test.2362239934
Short name T13
Test name
Test status
Simulation time 2523216789 ps
CPU time 43.2 seconds
Started Oct 09 02:07:33 AM UTC 24
Finished Oct 09 02:08:30 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2362239934 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 9.prim_prince_test.2362239934
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/9.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/90.prim_prince_test.3021536537
Short name T116
Test name
Test status
Simulation time 3503440536 ps
CPU time 70.22 seconds
Started Oct 09 02:08:55 AM UTC 24
Finished Oct 09 02:10:24 AM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3021536537 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 90.prim_prince_test.3021536537
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/90.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/91.prim_prince_test.4025397729
Short name T89
Test name
Test status
Simulation time 2131913277 ps
CPU time 40.62 seconds
Started Oct 09 02:08:55 AM UTC 24
Finished Oct 09 02:09:47 AM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4025397729 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 91.prim_prince_test.4025397729
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/91.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/92.prim_prince_test.2379095099
Short name T75
Test name
Test status
Simulation time 1335597630 ps
CPU time 26.34 seconds
Started Oct 09 02:08:58 AM UTC 24
Finished Oct 09 02:09:32 AM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2379095099 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 92.prim_prince_test.2379095099
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/92.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/93.prim_prince_test.1756834704
Short name T115
Test name
Test status
Simulation time 3460300999 ps
CPU time 65.08 seconds
Started Oct 09 02:08:59 AM UTC 24
Finished Oct 09 02:10:22 AM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1756834704 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 93.prim_prince_test.1756834704
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/93.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/94.prim_prince_test.409697648
Short name T80
Test name
Test status
Simulation time 1562937416 ps
CPU time 30.26 seconds
Started Oct 09 02:08:59 AM UTC 24
Finished Oct 09 02:09:38 AM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=409697648 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 94.prim_prince_test.409697648
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/94.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/95.prim_prince_test.3535993899
Short name T101
Test name
Test status
Simulation time 2444781208 ps
CPU time 49.23 seconds
Started Oct 09 02:09:00 AM UTC 24
Finished Oct 09 02:10:03 AM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3535993899 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 95.prim_prince_test.3535993899
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/95.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/96.prim_prince_test.858817181
Short name T112
Test name
Test status
Simulation time 3046771844 ps
CPU time 58.81 seconds
Started Oct 09 02:09:01 AM UTC 24
Finished Oct 09 02:10:16 AM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=858817181 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 96.prim_prince_test.858817181
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/96.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/97.prim_prince_test.2488508015
Short name T117
Test name
Test status
Simulation time 3400657120 ps
CPU time 64.5 seconds
Started Oct 09 02:09:02 AM UTC 24
Finished Oct 09 02:10:25 AM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2488508015 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 97.prim_prince_test.2488508015
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/97.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/98.prim_prince_test.2792749261
Short name T102
Test name
Test status
Simulation time 2420431184 ps
CPU time 45.4 seconds
Started Oct 09 02:09:04 AM UTC 24
Finished Oct 09 02:10:03 AM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2792749261 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 98.prim_prince_test.2792749261
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/98.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default/99.prim_prince_test.3824621340
Short name T84
Test name
Test status
Simulation time 1434738257 ps
CPU time 28.55 seconds
Started Oct 09 02:09:05 AM UTC 24
Finished Oct 09 02:09:42 AM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3824621340 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 99.prim_prince_test.3824621340
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_prince-sim-vcs/99.prim_prince_test/latest
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