Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00 100.00


Total test records in report: 500
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html
T251 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/247.prim_prince_test.2366229047 Oct 11 11:40:13 PM UTC 24 Oct 11 11:41:10 PM UTC 24 2383741310 ps
T252 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/233.prim_prince_test.2067321460 Oct 11 11:39:58 PM UTC 24 Oct 11 11:41:10 PM UTC 24 2990167291 ps
T253 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/255.prim_prince_test.1989630341 Oct 11 11:40:22 PM UTC 24 Oct 11 11:41:11 PM UTC 24 2050108735 ps
T254 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/237.prim_prince_test.2378330206 Oct 11 11:40:08 PM UTC 24 Oct 11 11:41:12 PM UTC 24 2685693707 ps
T255 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/216.prim_prince_test.3300508093 Oct 11 11:39:46 PM UTC 24 Oct 11 11:41:12 PM UTC 24 3658535768 ps
T256 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/248.prim_prince_test.2327173254 Oct 11 11:40:17 PM UTC 24 Oct 11 11:41:12 PM UTC 24 2299167128 ps
T257 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/238.prim_prince_test.3837476484 Oct 11 11:40:09 PM UTC 24 Oct 11 11:41:14 PM UTC 24 2706128268 ps
T258 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/249.prim_prince_test.4172272145 Oct 11 11:40:18 PM UTC 24 Oct 11 11:41:15 PM UTC 24 2382320621 ps
T259 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/279.prim_prince_test.3045468074 Oct 11 11:40:47 PM UTC 24 Oct 11 11:41:15 PM UTC 24 1125999931 ps
T260 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/273.prim_prince_test.94209026 Oct 11 11:40:41 PM UTC 24 Oct 11 11:41:17 PM UTC 24 1510949347 ps
T261 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/231.prim_prince_test.1047817075 Oct 11 11:39:56 PM UTC 24 Oct 11 11:41:18 PM UTC 24 3432609001 ps
T262 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/245.prim_prince_test.1623753215 Oct 11 11:40:12 PM UTC 24 Oct 11 11:41:22 PM UTC 24 2968970540 ps
T263 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/259.prim_prince_test.264690745 Oct 11 11:40:24 PM UTC 24 Oct 11 11:41:22 PM UTC 24 2434133426 ps
T264 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/285.prim_prince_test.1487343559 Oct 11 11:40:55 PM UTC 24 Oct 11 11:41:22 PM UTC 24 1110063652 ps
T265 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/271.prim_prince_test.3726036713 Oct 11 11:40:40 PM UTC 24 Oct 11 11:41:23 PM UTC 24 1798999344 ps
T266 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/284.prim_prince_test.212478374 Oct 11 11:40:54 PM UTC 24 Oct 11 11:41:27 PM UTC 24 1386262058 ps
T267 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/289.prim_prince_test.308493618 Oct 11 11:40:57 PM UTC 24 Oct 11 11:41:28 PM UTC 24 1277272960 ps
T268 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/250.prim_prince_test.3145178167 Oct 11 11:40:19 PM UTC 24 Oct 11 11:41:29 PM UTC 24 2959454310 ps
T269 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/288.prim_prince_test.1365698829 Oct 11 11:40:56 PM UTC 24 Oct 11 11:41:30 PM UTC 24 1395519121 ps
T270 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/300.prim_prince_test.3559462341 Oct 11 11:41:07 PM UTC 24 Oct 11 11:41:32 PM UTC 24 1000900753 ps
T271 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/294.prim_prince_test.1311425001 Oct 11 11:40:59 PM UTC 24 Oct 11 11:41:32 PM UTC 24 1360938947 ps
T272 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/307.prim_prince_test.897656725 Oct 11 11:41:12 PM UTC 24 Oct 11 11:41:32 PM UTC 24 830391886 ps
T273 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/257.prim_prince_test.2120014424 Oct 11 11:40:23 PM UTC 24 Oct 11 11:41:32 PM UTC 24 2941227057 ps
T274 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/240.prim_prince_test.86200047 Oct 11 11:40:10 PM UTC 24 Oct 11 11:41:34 PM UTC 24 3566588939 ps
T275 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/315.prim_prince_test.3476542318 Oct 11 11:41:16 PM UTC 24 Oct 11 11:41:35 PM UTC 24 757341597 ps
T276 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/308.prim_prince_test.1931606165 Oct 11 11:41:12 PM UTC 24 Oct 11 11:41:35 PM UTC 24 932037834 ps
T277 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/295.prim_prince_test.2185050936 Oct 11 11:41:02 PM UTC 24 Oct 11 11:41:37 PM UTC 24 1431969913 ps
T278 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/244.prim_prince_test.1757775506 Oct 11 11:40:12 PM UTC 24 Oct 11 11:41:37 PM UTC 24 3680154112 ps
T279 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/291.prim_prince_test.3860078541 Oct 11 11:40:58 PM UTC 24 Oct 11 11:41:39 PM UTC 24 1698981922 ps
T280 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/261.prim_prince_test.1641804397 Oct 11 11:40:26 PM UTC 24 Oct 11 11:41:41 PM UTC 24 3128380909 ps
T281 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/252.prim_prince_test.1875614887 Oct 11 11:40:21 PM UTC 24 Oct 11 11:41:41 PM UTC 24 3389160649 ps
T282 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/264.prim_prince_test.1583460424 Oct 11 11:40:30 PM UTC 24 Oct 11 11:41:41 PM UTC 24 2993746098 ps
T283 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/292.prim_prince_test.4228918931 Oct 11 11:40:58 PM UTC 24 Oct 11 11:41:43 PM UTC 24 1914732873 ps
T284 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/272.prim_prince_test.2180514025 Oct 11 11:40:41 PM UTC 24 Oct 11 11:41:44 PM UTC 24 2697737258 ps
T285 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/313.prim_prince_test.2745520703 Oct 11 11:41:14 PM UTC 24 Oct 11 11:41:44 PM UTC 24 1235180128 ps
T286 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/299.prim_prince_test.120105890 Oct 11 11:41:06 PM UTC 24 Oct 11 11:41:46 PM UTC 24 1651607202 ps
T287 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/268.prim_prince_test.2529515778 Oct 11 11:40:38 PM UTC 24 Oct 11 11:41:46 PM UTC 24 2879037316 ps
T288 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/283.prim_prince_test.2315418031 Oct 11 11:40:54 PM UTC 24 Oct 11 11:41:47 PM UTC 24 2242585044 ps
T289 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/276.prim_prince_test.179946587 Oct 11 11:40:44 PM UTC 24 Oct 11 11:41:47 PM UTC 24 2672088508 ps
T290 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/293.prim_prince_test.3781836693 Oct 11 11:40:58 PM UTC 24 Oct 11 11:41:48 PM UTC 24 2064366039 ps
T291 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/275.prim_prince_test.3856602522 Oct 11 11:40:44 PM UTC 24 Oct 11 11:41:49 PM UTC 24 2793176196 ps
T292 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/322.prim_prince_test.675891346 Oct 11 11:41:29 PM UTC 24 Oct 11 11:41:50 PM UTC 24 873469141 ps
T293 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/309.prim_prince_test.2406871144 Oct 11 11:41:12 PM UTC 24 Oct 11 11:41:50 PM UTC 24 1601425107 ps
T294 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/321.prim_prince_test.1560390913 Oct 11 11:41:24 PM UTC 24 Oct 11 11:41:51 PM UTC 24 1061149067 ps
T295 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/282.prim_prince_test.2791939373 Oct 11 11:40:54 PM UTC 24 Oct 11 11:41:51 PM UTC 24 2425789190 ps
T296 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/280.prim_prince_test.3472155917 Oct 11 11:40:52 PM UTC 24 Oct 11 11:41:51 PM UTC 24 2501956702 ps
T297 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/317.prim_prince_test.59090249 Oct 11 11:41:19 PM UTC 24 Oct 11 11:41:53 PM UTC 24 1400105689 ps
T298 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/267.prim_prince_test.3249226695 Oct 11 11:40:37 PM UTC 24 Oct 11 11:41:53 PM UTC 24 3295855846 ps
T299 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/287.prim_prince_test.2513695679 Oct 11 11:40:56 PM UTC 24 Oct 11 11:41:54 PM UTC 24 2437178921 ps
T300 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/281.prim_prince_test.156948566 Oct 11 11:40:52 PM UTC 24 Oct 11 11:41:54 PM UTC 24 2604043725 ps
T301 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/269.prim_prince_test.307344136 Oct 11 11:40:39 PM UTC 24 Oct 11 11:41:54 PM UTC 24 3270854335 ps
T302 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/277.prim_prince_test.662974444 Oct 11 11:40:45 PM UTC 24 Oct 11 11:41:56 PM UTC 24 3037515287 ps
T303 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/302.prim_prince_test.582523721 Oct 11 11:41:08 PM UTC 24 Oct 11 11:41:56 PM UTC 24 1998450310 ps
T304 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/326.prim_prince_test.4139812543 Oct 11 11:41:32 PM UTC 24 Oct 11 11:41:57 PM UTC 24 1012790284 ps
T305 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/290.prim_prince_test.792898588 Oct 11 11:40:57 PM UTC 24 Oct 11 11:42:04 PM UTC 24 2849314058 ps
T306 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/278.prim_prince_test.2783599048 Oct 11 11:40:46 PM UTC 24 Oct 11 11:42:04 PM UTC 24 3369669896 ps
T307 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/325.prim_prince_test.580780261 Oct 11 11:41:31 PM UTC 24 Oct 11 11:42:04 PM UTC 24 1396939903 ps
T308 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/297.prim_prince_test.2068189659 Oct 11 11:41:06 PM UTC 24 Oct 11 11:42:05 PM UTC 24 2507307602 ps
T309 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/338.prim_prince_test.1418757159 Oct 11 11:41:42 PM UTC 24 Oct 11 11:42:08 PM UTC 24 1051289118 ps
T310 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/286.prim_prince_test.3510396221 Oct 11 11:40:55 PM UTC 24 Oct 11 11:42:08 PM UTC 24 3084020939 ps
T311 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/274.prim_prince_test.938580962 Oct 11 11:40:42 PM UTC 24 Oct 11 11:42:08 PM UTC 24 3698951784 ps
T312 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/323.prim_prince_test.3893313567 Oct 11 11:41:29 PM UTC 24 Oct 11 11:42:10 PM UTC 24 1725155771 ps
T313 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/306.prim_prince_test.333733740 Oct 11 11:41:12 PM UTC 24 Oct 11 11:42:10 PM UTC 24 2509150755 ps
T314 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/296.prim_prince_test.2088950698 Oct 11 11:41:03 PM UTC 24 Oct 11 11:42:10 PM UTC 24 2832326639 ps
T315 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/298.prim_prince_test.2151312946 Oct 11 11:41:06 PM UTC 24 Oct 11 11:42:12 PM UTC 24 2826937467 ps
T316 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/343.prim_prince_test.748727759 Oct 11 11:41:46 PM UTC 24 Oct 11 11:42:14 PM UTC 24 1142741351 ps
T317 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/303.prim_prince_test.820121590 Oct 11 11:41:08 PM UTC 24 Oct 11 11:42:15 PM UTC 24 2833721688 ps
T318 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/352.prim_prince_test.3973656731 Oct 11 11:41:53 PM UTC 24 Oct 11 11:42:15 PM UTC 24 919641852 ps
T319 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/311.prim_prince_test.3258156994 Oct 11 11:41:13 PM UTC 24 Oct 11 11:42:19 PM UTC 24 2832793529 ps
T320 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/312.prim_prince_test.1367746358 Oct 11 11:41:13 PM UTC 24 Oct 11 11:42:21 PM UTC 24 2867626839 ps
T321 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/314.prim_prince_test.4134053370 Oct 11 11:41:15 PM UTC 24 Oct 11 11:42:21 PM UTC 24 2800091614 ps
T322 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/310.prim_prince_test.1503931807 Oct 11 11:41:13 PM UTC 24 Oct 11 11:42:21 PM UTC 24 2904947093 ps
T323 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/350.prim_prince_test.3561946355 Oct 11 11:41:51 PM UTC 24 Oct 11 11:42:22 PM UTC 24 1257168692 ps
T324 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/301.prim_prince_test.1249567088 Oct 11 11:41:07 PM UTC 24 Oct 11 11:42:22 PM UTC 24 3223700814 ps
T325 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/304.prim_prince_test.3533113421 Oct 11 11:41:08 PM UTC 24 Oct 11 11:42:23 PM UTC 24 3171198840 ps
T326 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/340.prim_prince_test.3781073461 Oct 11 11:41:44 PM UTC 24 Oct 11 11:42:23 PM UTC 24 1630717435 ps
T327 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/324.prim_prince_test.2791977912 Oct 11 11:41:30 PM UTC 24 Oct 11 11:42:24 PM UTC 24 2276138976 ps
T328 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/320.prim_prince_test.4045064483 Oct 11 11:41:23 PM UTC 24 Oct 11 11:42:25 PM UTC 24 2633525497 ps
T329 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/349.prim_prince_test.3811472134 Oct 11 11:41:51 PM UTC 24 Oct 11 11:42:26 PM UTC 24 1443827442 ps
T330 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/332.prim_prince_test.2888021695 Oct 11 11:41:36 PM UTC 24 Oct 11 11:42:26 PM UTC 24 2151605961 ps
T331 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/345.prim_prince_test.70355889 Oct 11 11:41:48 PM UTC 24 Oct 11 11:42:27 PM UTC 24 1617417369 ps
T332 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/351.prim_prince_test.1395129025 Oct 11 11:41:52 PM UTC 24 Oct 11 11:42:28 PM UTC 24 1541624041 ps
T333 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/354.prim_prince_test.2548806073 Oct 11 11:41:54 PM UTC 24 Oct 11 11:42:29 PM UTC 24 1412870913 ps
T334 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/305.prim_prince_test.781253042 Oct 11 11:41:10 PM UTC 24 Oct 11 11:42:29 PM UTC 24 3364537951 ps
T335 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/335.prim_prince_test.2011101013 Oct 11 11:41:40 PM UTC 24 Oct 11 11:42:30 PM UTC 24 2065561135 ps
T336 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/336.prim_prince_test.1574064392 Oct 11 11:41:40 PM UTC 24 Oct 11 11:42:30 PM UTC 24 2058922958 ps
T337 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/318.prim_prince_test.2654349397 Oct 11 11:41:23 PM UTC 24 Oct 11 11:42:30 PM UTC 24 2790953167 ps
T338 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/355.prim_prince_test.480131748 Oct 11 11:41:54 PM UTC 24 Oct 11 11:42:30 PM UTC 24 1498170024 ps
T339 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/348.prim_prince_test.2143059458 Oct 11 11:41:50 PM UTC 24 Oct 11 11:42:30 PM UTC 24 1671425362 ps
T340 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/361.prim_prince_test.993851244 Oct 11 11:41:58 PM UTC 24 Oct 11 11:42:33 PM UTC 24 1489789062 ps
T341 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/346.prim_prince_test.4198085534 Oct 11 11:41:49 PM UTC 24 Oct 11 11:42:35 PM UTC 24 1970523301 ps
T342 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/353.prim_prince_test.143012394 Oct 11 11:41:53 PM UTC 24 Oct 11 11:42:36 PM UTC 24 1823154595 ps
T343 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/342.prim_prince_test.2582742752 Oct 11 11:41:45 PM UTC 24 Oct 11 11:42:37 PM UTC 24 2165475004 ps
T344 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/316.prim_prince_test.2303002547 Oct 11 11:41:18 PM UTC 24 Oct 11 11:42:37 PM UTC 24 3417247592 ps
T345 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/327.prim_prince_test.4278056331 Oct 11 11:41:33 PM UTC 24 Oct 11 11:42:39 PM UTC 24 2788753170 ps
T346 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/328.prim_prince_test.328618093 Oct 11 11:41:33 PM UTC 24 Oct 11 11:42:40 PM UTC 24 2833640408 ps
T347 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/319.prim_prince_test.1780802308 Oct 11 11:41:23 PM UTC 24 Oct 11 11:42:40 PM UTC 24 3253569591 ps
T348 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/374.prim_prince_test.1875557237 Oct 11 11:42:15 PM UTC 24 Oct 11 11:42:42 PM UTC 24 1117602860 ps
T349 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/375.prim_prince_test.3760911610 Oct 11 11:42:16 PM UTC 24 Oct 11 11:42:43 PM UTC 24 1130923015 ps
T350 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/357.prim_prince_test.972808585 Oct 11 11:41:55 PM UTC 24 Oct 11 11:42:43 PM UTC 24 2010365266 ps
T351 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/370.prim_prince_test.2412933957 Oct 11 11:42:11 PM UTC 24 Oct 11 11:42:44 PM UTC 24 1334268992 ps
T352 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/364.prim_prince_test.2995388707 Oct 11 11:42:05 PM UTC 24 Oct 11 11:42:44 PM UTC 24 1624632036 ps
T353 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/378.prim_prince_test.2020633801 Oct 11 11:42:22 PM UTC 24 Oct 11 11:42:46 PM UTC 24 974223322 ps
T354 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/329.prim_prince_test.2095511009 Oct 11 11:41:33 PM UTC 24 Oct 11 11:42:48 PM UTC 24 3221092631 ps
T355 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/365.prim_prince_test.4178086106 Oct 11 11:42:06 PM UTC 24 Oct 11 11:42:48 PM UTC 24 1749573414 ps
T356 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/358.prim_prince_test.1020212211 Oct 11 11:41:55 PM UTC 24 Oct 11 11:42:49 PM UTC 24 2274299114 ps
T357 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/347.prim_prince_test.764333454 Oct 11 11:41:49 PM UTC 24 Oct 11 11:42:50 PM UTC 24 2560239460 ps
T358 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/379.prim_prince_test.142094789 Oct 11 11:42:22 PM UTC 24 Oct 11 11:42:50 PM UTC 24 1178807624 ps
T359 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/369.prim_prince_test.2322955878 Oct 11 11:42:11 PM UTC 24 Oct 11 11:42:51 PM UTC 24 1642328240 ps
T360 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/386.prim_prince_test.2488215110 Oct 11 11:42:27 PM UTC 24 Oct 11 11:42:52 PM UTC 24 1022386171 ps
T361 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/363.prim_prince_test.305451460 Oct 11 11:42:05 PM UTC 24 Oct 11 11:42:52 PM UTC 24 1950402300 ps
T362 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/394.prim_prince_test.1046813185 Oct 11 11:42:31 PM UTC 24 Oct 11 11:42:53 PM UTC 24 880109162 ps
T363 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/333.prim_prince_test.2213228618 Oct 11 11:41:38 PM UTC 24 Oct 11 11:42:53 PM UTC 24 3203137529 ps
T364 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/381.prim_prince_test.1476009038 Oct 11 11:42:23 PM UTC 24 Oct 11 11:42:55 PM UTC 24 1305277356 ps
T365 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/397.prim_prince_test.4211152194 Oct 11 11:42:31 PM UTC 24 Oct 11 11:42:55 PM UTC 24 946425375 ps
T366 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/330.prim_prince_test.3958104727 Oct 11 11:41:34 PM UTC 24 Oct 11 11:42:56 PM UTC 24 3469822604 ps
T367 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/385.prim_prince_test.2285088871 Oct 11 11:42:24 PM UTC 24 Oct 11 11:42:57 PM UTC 24 1369685451 ps
T368 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/384.prim_prince_test.1929170282 Oct 11 11:42:24 PM UTC 24 Oct 11 11:42:58 PM UTC 24 1405163974 ps
T369 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/339.prim_prince_test.2290140869 Oct 11 11:41:42 PM UTC 24 Oct 11 11:42:58 PM UTC 24 3209840027 ps
T370 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/371.prim_prince_test.1456895015 Oct 11 11:42:11 PM UTC 24 Oct 11 11:42:58 PM UTC 24 1991337990 ps
T371 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/337.prim_prince_test.4185149174 Oct 11 11:41:42 PM UTC 24 Oct 11 11:42:59 PM UTC 24 3288059816 ps
T372 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/331.prim_prince_test.1643897603 Oct 11 11:41:36 PM UTC 24 Oct 11 11:43:00 PM UTC 24 3626722283 ps
T373 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/359.prim_prince_test.169652886 Oct 11 11:41:57 PM UTC 24 Oct 11 11:43:01 PM UTC 24 2706451505 ps
T374 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/334.prim_prince_test.108383387 Oct 11 11:41:38 PM UTC 24 Oct 11 11:43:05 PM UTC 24 3688818744 ps
T375 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/344.prim_prince_test.129691037 Oct 11 11:41:48 PM UTC 24 Oct 11 11:43:06 PM UTC 24 3398354082 ps
T376 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/392.prim_prince_test.440640335 Oct 11 11:42:31 PM UTC 24 Oct 11 11:43:07 PM UTC 24 1475498878 ps
T377 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/356.prim_prince_test.2342887568 Oct 11 11:41:54 PM UTC 24 Oct 11 11:43:09 PM UTC 24 3188106890 ps
T378 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/341.prim_prince_test.1925547751 Oct 11 11:41:45 PM UTC 24 Oct 11 11:43:09 PM UTC 24 3563660116 ps
T379 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/376.prim_prince_test.3520235702 Oct 11 11:42:16 PM UTC 24 Oct 11 11:43:11 PM UTC 24 2282012827 ps
T380 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/406.prim_prince_test.3071467668 Oct 11 11:42:44 PM UTC 24 Oct 11 11:43:11 PM UTC 24 1111434577 ps
T381 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/362.prim_prince_test.3399020508 Oct 11 11:42:05 PM UTC 24 Oct 11 11:43:11 PM UTC 24 2829588211 ps
T382 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/412.prim_prince_test.2363312122 Oct 11 11:42:47 PM UTC 24 Oct 11 11:43:12 PM UTC 24 1041160730 ps
T383 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/416.prim_prince_test.963998635 Oct 11 11:42:50 PM UTC 24 Oct 11 11:43:12 PM UTC 24 889511076 ps
T384 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/389.prim_prince_test.3822906218 Oct 11 11:42:28 PM UTC 24 Oct 11 11:43:15 PM UTC 24 1947335066 ps
T385 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/360.prim_prince_test.2837208498 Oct 11 11:41:57 PM UTC 24 Oct 11 11:43:15 PM UTC 24 3356471096 ps
T386 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/420.prim_prince_test.377982694 Oct 11 11:42:52 PM UTC 24 Oct 11 11:43:17 PM UTC 24 1023756339 ps
T387 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/390.prim_prince_test.1900442361 Oct 11 11:42:29 PM UTC 24 Oct 11 11:43:17 PM UTC 24 2033871781 ps
T388 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/382.prim_prince_test.465569796 Oct 11 11:42:23 PM UTC 24 Oct 11 11:43:17 PM UTC 24 2289251877 ps
T389 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/368.prim_prince_test.1764746775 Oct 11 11:42:10 PM UTC 24 Oct 11 11:43:18 PM UTC 24 2912149548 ps
T390 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/383.prim_prince_test.3635550576 Oct 11 11:42:24 PM UTC 24 Oct 11 11:43:18 PM UTC 24 2287042661 ps
T391 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/373.prim_prince_test.4052741013 Oct 11 11:42:13 PM UTC 24 Oct 11 11:43:19 PM UTC 24 2831798209 ps
T392 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/391.prim_prince_test.3123756233 Oct 11 11:42:29 PM UTC 24 Oct 11 11:43:21 PM UTC 24 2193562467 ps
T393 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/402.prim_prince_test.3785735053 Oct 11 11:42:39 PM UTC 24 Oct 11 11:43:21 PM UTC 24 1745827127 ps
T394 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/398.prim_prince_test.3820133275 Oct 11 11:42:34 PM UTC 24 Oct 11 11:43:25 PM UTC 24 2138403780 ps
T395 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/418.prim_prince_test.1800697219 Oct 11 11:42:52 PM UTC 24 Oct 11 11:43:25 PM UTC 24 1386903941 ps
T396 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/421.prim_prince_test.1450862836 Oct 11 11:42:53 PM UTC 24 Oct 11 11:43:28 PM UTC 24 1417739030 ps
T397 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/427.prim_prince_test.3473320155 Oct 11 11:42:57 PM UTC 24 Oct 11 11:43:28 PM UTC 24 1266011086 ps
T398 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/409.prim_prince_test.1752571773 Oct 11 11:42:45 PM UTC 24 Oct 11 11:43:30 PM UTC 24 1876179318 ps
T399 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/411.prim_prince_test.2781001573 Oct 11 11:42:47 PM UTC 24 Oct 11 11:43:30 PM UTC 24 1856977760 ps
T400 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/415.prim_prince_test.2220742882 Oct 11 11:42:50 PM UTC 24 Oct 11 11:43:31 PM UTC 24 1677002741 ps
T401 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/429.prim_prince_test.1249343199 Oct 11 11:42:59 PM UTC 24 Oct 11 11:43:31 PM UTC 24 1318355579 ps
T402 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/407.prim_prince_test.2055596192 Oct 11 11:42:45 PM UTC 24 Oct 11 11:43:32 PM UTC 24 1960419647 ps
T403 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/399.prim_prince_test.2856118303 Oct 11 11:42:37 PM UTC 24 Oct 11 11:43:32 PM UTC 24 2386275506 ps
T404 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/438.prim_prince_test.503261860 Oct 11 11:43:10 PM UTC 24 Oct 11 11:43:34 PM UTC 24 961560815 ps
T405 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/372.prim_prince_test.1897707501 Oct 11 11:42:13 PM UTC 24 Oct 11 11:43:35 PM UTC 24 3528679540 ps
T406 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/366.prim_prince_test.2152782974 Oct 11 11:42:09 PM UTC 24 Oct 11 11:43:35 PM UTC 24 3731329014 ps
T407 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/367.prim_prince_test.3827618260 Oct 11 11:42:09 PM UTC 24 Oct 11 11:43:36 PM UTC 24 3707221087 ps
T408 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/380.prim_prince_test.2872373423 Oct 11 11:42:23 PM UTC 24 Oct 11 11:43:36 PM UTC 24 3144860403 ps
T409 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/450.prim_prince_test.2750604771 Oct 11 11:43:19 PM UTC 24 Oct 11 11:43:37 PM UTC 24 757352989 ps
T410 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/377.prim_prince_test.1189656901 Oct 11 11:42:20 PM UTC 24 Oct 11 11:43:38 PM UTC 24 3343012457 ps
T411 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/396.prim_prince_test.3460979363 Oct 11 11:42:31 PM UTC 24 Oct 11 11:43:40 PM UTC 24 2924109199 ps
T412 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/393.prim_prince_test.2600725002 Oct 11 11:42:31 PM UTC 24 Oct 11 11:43:40 PM UTC 24 3019468968 ps
T413 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/432.prim_prince_test.3506550389 Oct 11 11:43:00 PM UTC 24 Oct 11 11:43:40 PM UTC 24 1704424192 ps
T414 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/404.prim_prince_test.1885760713 Oct 11 11:42:40 PM UTC 24 Oct 11 11:43:41 PM UTC 24 2624408710 ps
T415 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/388.prim_prince_test.3679838143 Oct 11 11:42:27 PM UTC 24 Oct 11 11:43:42 PM UTC 24 3183335366 ps
T416 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/454.prim_prince_test.3574328305 Oct 11 11:43:22 PM UTC 24 Oct 11 11:43:42 PM UTC 24 828260503 ps
T417 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/444.prim_prince_test.1324281276 Oct 11 11:43:14 PM UTC 24 Oct 11 11:43:43 PM UTC 24 1191214266 ps
T418 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/408.prim_prince_test.1450003606 Oct 11 11:42:45 PM UTC 24 Oct 11 11:43:45 PM UTC 24 2573858009 ps
T419 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/431.prim_prince_test.1222766991 Oct 11 11:42:59 PM UTC 24 Oct 11 11:43:45 PM UTC 24 1996845154 ps
T420 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/442.prim_prince_test.2466194372 Oct 11 11:43:13 PM UTC 24 Oct 11 11:43:46 PM UTC 24 1407050258 ps
T421 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/437.prim_prince_test.1428053349 Oct 11 11:43:08 PM UTC 24 Oct 11 11:43:46 PM UTC 24 1586967375 ps
T422 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/433.prim_prince_test.1272916863 Oct 11 11:43:01 PM UTC 24 Oct 11 11:43:46 PM UTC 24 1877383829 ps
T423 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/387.prim_prince_test.2308688235 Oct 11 11:42:27 PM UTC 24 Oct 11 11:43:47 PM UTC 24 3400134001 ps
T424 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/403.prim_prince_test.3802163271 Oct 11 11:42:40 PM UTC 24 Oct 11 11:43:48 PM UTC 24 2917294860 ps
T425 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/425.prim_prince_test.100472758 Oct 11 11:42:56 PM UTC 24 Oct 11 11:43:48 PM UTC 24 2250493531 ps
T426 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/400.prim_prince_test.2708445139 Oct 11 11:42:37 PM UTC 24 Oct 11 11:43:49 PM UTC 24 3071381695 ps
T427 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/434.prim_prince_test.2444677775 Oct 11 11:43:02 PM UTC 24 Oct 11 11:43:51 PM UTC 24 2074292843 ps
T428 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/395.prim_prince_test.532459442 Oct 11 11:42:31 PM UTC 24 Oct 11 11:43:52 PM UTC 24 3437962936 ps
T429 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/452.prim_prince_test.4244298915 Oct 11 11:43:20 PM UTC 24 Oct 11 11:43:53 PM UTC 24 1371623108 ps
T430 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/464.prim_prince_test.1659938056 Oct 11 11:43:33 PM UTC 24 Oct 11 11:43:54 PM UTC 24 814070744 ps
T431 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/443.prim_prince_test.2182696599 Oct 11 11:43:13 PM UTC 24 Oct 11 11:44:00 PM UTC 24 1967605502 ps
T432 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/422.prim_prince_test.381273701 Oct 11 11:42:53 PM UTC 24 Oct 11 11:44:00 PM UTC 24 2834537391 ps
T433 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/462.prim_prince_test.1705094450 Oct 11 11:43:32 PM UTC 24 Oct 11 11:44:03 PM UTC 24 1251927903 ps
T434 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/446.prim_prince_test.2934479440 Oct 11 11:43:16 PM UTC 24 Oct 11 11:44:04 PM UTC 24 2006177429 ps
T435 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/401.prim_prince_test.910738346 Oct 11 11:42:38 PM UTC 24 Oct 11 11:44:04 PM UTC 24 3696542403 ps
T436 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/405.prim_prince_test.3785676696 Oct 11 11:42:41 PM UTC 24 Oct 11 11:44:04 PM UTC 24 3558196079 ps
T437 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/469.prim_prince_test.2423199011 Oct 11 11:43:37 PM UTC 24 Oct 11 11:44:05 PM UTC 24 1132470167 ps
T438 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/410.prim_prince_test.4154309659 Oct 11 11:42:45 PM UTC 24 Oct 11 11:44:05 PM UTC 24 3397502246 ps
T439 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/470.prim_prince_test.320040003 Oct 11 11:43:38 PM UTC 24 Oct 11 11:44:05 PM UTC 24 1109770816 ps
T440 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/419.prim_prince_test.1451719182 Oct 11 11:42:52 PM UTC 24 Oct 11 11:44:05 PM UTC 24 3163313176 ps
T441 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/430.prim_prince_test.2110273205 Oct 11 11:42:59 PM UTC 24 Oct 11 11:44:05 PM UTC 24 2881745210 ps
T442 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/453.prim_prince_test.1602651359 Oct 11 11:43:22 PM UTC 24 Oct 11 11:44:07 PM UTC 24 1908422354 ps
T443 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/449.prim_prince_test.2171785053 Oct 11 11:43:19 PM UTC 24 Oct 11 11:44:07 PM UTC 24 2034964347 ps
T444 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/423.prim_prince_test.3859268980 Oct 11 11:42:54 PM UTC 24 Oct 11 11:44:07 PM UTC 24 3133229973 ps
T445 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/413.prim_prince_test.815236755 Oct 11 11:42:49 PM UTC 24 Oct 11 11:44:08 PM UTC 24 3410903725 ps
T446 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/424.prim_prince_test.2432778926 Oct 11 11:42:55 PM UTC 24 Oct 11 11:44:10 PM UTC 24 3240005688 ps
T447 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/426.prim_prince_test.58397201 Oct 11 11:42:56 PM UTC 24 Oct 11 11:44:10 PM UTC 24 3161118211 ps
T448 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/474.prim_prince_test.4266802070 Oct 11 11:43:42 PM UTC 24 Oct 11 11:44:12 PM UTC 24 1223594335 ps
T449 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/414.prim_prince_test.2934299248 Oct 11 11:42:49 PM UTC 24 Oct 11 11:44:12 PM UTC 24 3538862245 ps
T450 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/476.prim_prince_test.2601398402 Oct 11 11:43:44 PM UTC 24 Oct 11 11:44:12 PM UTC 24 1192990250 ps
T451 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/428.prim_prince_test.2368170931 Oct 11 11:42:59 PM UTC 24 Oct 11 11:44:13 PM UTC 24 3158018096 ps
T452 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/458.prim_prince_test.84982546 Oct 11 11:43:29 PM UTC 24 Oct 11 11:44:14 PM UTC 24 1883096624 ps
T453 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/486.prim_prince_test.228082978 Oct 11 11:43:49 PM UTC 24 Oct 11 11:44:14 PM UTC 24 1039035471 ps
T454 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/435.prim_prince_test.2702633616 Oct 11 11:43:06 PM UTC 24 Oct 11 11:44:14 PM UTC 24 2890338622 ps
T455 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/485.prim_prince_test.2689076375 Oct 11 11:43:49 PM UTC 24 Oct 11 11:44:17 PM UTC 24 1153372562 ps
T456 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/417.prim_prince_test.1975914363 Oct 11 11:42:50 PM UTC 24 Oct 11 11:44:17 PM UTC 24 3699192383 ps
T457 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/478.prim_prince_test.1618598459 Oct 11 11:43:44 PM UTC 24 Oct 11 11:44:17 PM UTC 24 1409151807 ps
T458 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/448.prim_prince_test.1691145831 Oct 11 11:43:18 PM UTC 24 Oct 11 11:44:18 PM UTC 24 2555064717 ps
T459 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/436.prim_prince_test.1437696353 Oct 11 11:43:07 PM UTC 24 Oct 11 11:44:18 PM UTC 24 3070164098 ps
T460 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/487.prim_prince_test.1553234710 Oct 11 11:43:50 PM UTC 24 Oct 11 11:44:19 PM UTC 24 1229855136 ps
T461 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/456.prim_prince_test.110439783 Oct 11 11:43:27 PM UTC 24 Oct 11 11:44:19 PM UTC 24 2205989059 ps
T462 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/440.prim_prince_test.3830621703 Oct 11 11:43:11 PM UTC 24 Oct 11 11:44:19 PM UTC 24 2935220587 ps
T463 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/467.prim_prince_test.1905693623 Oct 11 11:43:37 PM UTC 24 Oct 11 11:44:20 PM UTC 24 1825920530 ps
T464 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/466.prim_prince_test.41725363 Oct 11 11:43:37 PM UTC 24 Oct 11 11:44:20 PM UTC 24 1826595414 ps
T465 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/439.prim_prince_test.1120813984 Oct 11 11:43:10 PM UTC 24 Oct 11 11:44:20 PM UTC 24 3001501582 ps
T466 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/441.prim_prince_test.2933565060 Oct 11 11:43:11 PM UTC 24 Oct 11 11:44:20 PM UTC 24 2969336343 ps
T467 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/471.prim_prince_test.852516752 Oct 11 11:43:38 PM UTC 24 Oct 11 11:44:20 PM UTC 24 1787934515 ps
T468 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/483.prim_prince_test.1759614549 Oct 11 11:43:47 PM UTC 24 Oct 11 11:44:20 PM UTC 24 1388249564 ps
T469 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/447.prim_prince_test.2283466808 Oct 11 11:43:17 PM UTC 24 Oct 11 11:44:25 PM UTC 24 2894692862 ps
T470 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/465.prim_prince_test.4221310045 Oct 11 11:43:35 PM UTC 24 Oct 11 11:44:27 PM UTC 24 2250156496 ps
T471 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/451.prim_prince_test.2783753541 Oct 11 11:43:19 PM UTC 24 Oct 11 11:44:28 PM UTC 24 2967063797 ps
T472 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/499.prim_prince_test.4202581417 Oct 11 11:44:05 PM UTC 24 Oct 11 11:44:28 PM UTC 24 970420053 ps
T473 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/460.prim_prince_test.911417735 Oct 11 11:43:32 PM UTC 24 Oct 11 11:44:28 PM UTC 24 2420101528 ps
T474 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/457.prim_prince_test.908167399 Oct 11 11:43:28 PM UTC 24 Oct 11 11:44:29 PM UTC 24 2673799488 ps
T475 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/488.prim_prince_test.2213195142 Oct 11 11:43:51 PM UTC 24 Oct 11 11:44:30 PM UTC 24 1679788024 ps
T476 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/445.prim_prince_test.2207454687 Oct 11 11:43:15 PM UTC 24 Oct 11 11:44:31 PM UTC 24 3314307181 ps
T477 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/468.prim_prince_test.2743907134 Oct 11 11:43:37 PM UTC 24 Oct 11 11:44:32 PM UTC 24 2409742429 ps
T478 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/473.prim_prince_test.1349731807 Oct 11 11:43:42 PM UTC 24 Oct 11 11:44:35 PM UTC 24 2301283478 ps
T479 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/480.prim_prince_test.1286947836 Oct 11 11:43:46 PM UTC 24 Oct 11 11:44:37 PM UTC 24 2272270282 ps
T480 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/455.prim_prince_test.3147239823 Oct 11 11:43:27 PM UTC 24 Oct 11 11:44:38 PM UTC 24 3114991551 ps
T481 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/475.prim_prince_test.2514161210 Oct 11 11:43:42 PM UTC 24 Oct 11 11:44:40 PM UTC 24 2537477192 ps
T482 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/459.prim_prince_test.1460136799 Oct 11 11:43:32 PM UTC 24 Oct 11 11:44:42 PM UTC 24 3107302159 ps
T483 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/481.prim_prince_test.2977324714 Oct 11 11:43:47 PM UTC 24 Oct 11 11:44:43 PM UTC 24 2462620606 ps
T484 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/496.prim_prince_test.2157536549 Oct 11 11:44:05 PM UTC 24 Oct 11 11:44:46 PM UTC 24 1860046887 ps
T485 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/461.prim_prince_test.319589382 Oct 11 11:43:32 PM UTC 24 Oct 11 11:44:50 PM UTC 24 3443991146 ps
T486 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/477.prim_prince_test.2068032377 Oct 11 11:43:44 PM UTC 24 Oct 11 11:44:52 PM UTC 24 3106459832 ps
T487 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/497.prim_prince_test.2354885875 Oct 11 11:44:05 PM UTC 24 Oct 11 11:44:53 PM UTC 24 2158267852 ps
T488 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/463.prim_prince_test.3889906104 Oct 11 11:43:33 PM UTC 24 Oct 11 11:44:53 PM UTC 24 3542979753 ps
T489 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/482.prim_prince_test.1253348249 Oct 11 11:43:47 PM UTC 24 Oct 11 11:44:54 PM UTC 24 3027361328 ps
T490 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/479.prim_prince_test.3324001966 Oct 11 11:43:46 PM UTC 24 Oct 11 11:44:55 PM UTC 24 3076915372 ps
T491 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/472.prim_prince_test.118549832 Oct 11 11:43:41 PM UTC 24 Oct 11 11:44:57 PM UTC 24 3373590518 ps
T492 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/484.prim_prince_test.1190767695 Oct 11 11:43:49 PM UTC 24 Oct 11 11:44:58 PM UTC 24 3071350455 ps
T493 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/489.prim_prince_test.90821460 Oct 11 11:43:53 PM UTC 24 Oct 11 11:45:01 PM UTC 24 3064646100 ps
T494 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/491.prim_prince_test.1497294613 Oct 11 11:43:54 PM UTC 24 Oct 11 11:45:02 PM UTC 24 3039394019 ps
T495 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/493.prim_prince_test.2264267592 Oct 11 11:44:00 PM UTC 24 Oct 11 11:45:04 PM UTC 24 2798253914 ps
T496 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/492.prim_prince_test.786098291 Oct 11 11:43:54 PM UTC 24 Oct 11 11:45:11 PM UTC 24 3457781036 ps
T497 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/490.prim_prince_test.2305057277 Oct 11 11:43:53 PM UTC 24 Oct 11 11:45:12 PM UTC 24 3526856072 ps
T498 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/495.prim_prince_test.3082307370 Oct 11 11:44:04 PM UTC 24 Oct 11 11:45:12 PM UTC 24 3053324427 ps
T499 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/494.prim_prince_test.391647123 Oct 11 11:44:01 PM UTC 24 Oct 11 11:45:23 PM UTC 24 3415656961 ps
T500 /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/498.prim_prince_test.3395404604 Oct 11 11:44:05 PM UTC 24 Oct 11 11:45:32 PM UTC 24 3626460362 ps

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/11.prim_prince_test.3409996174
Short name T4
Test name
Test status
Simulation time 919882879 ps
CPU time 17.98 seconds
Started Oct 11 11:35:49 PM UTC 24
Finished Oct 11 11:36:12 PM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3409996174 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 11.prim_prince_test.3409996174
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/11.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/0.prim_prince_test.2747873455
Short name T39
Test name
Test status
Simulation time 3366690826 ps
CPU time 64.66 seconds
Started Oct 11 11:35:47 PM UTC 24
Finished Oct 11 11:37:10 PM UTC 24
Peak memory 153116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2747873455 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 0.prim_prince_test.2747873455
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/0.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/1.prim_prince_test.4119242476
Short name T37
Test name
Test status
Simulation time 3345548100 ps
CPU time 62.47 seconds
Started Oct 11 11:35:47 PM UTC 24
Finished Oct 11 11:37:08 PM UTC 24
Peak memory 153016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4119242476 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 1.prim_prince_test.4119242476
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/1.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/10.prim_prince_test.1799145025
Short name T16
Test name
Test status
Simulation time 1690363349 ps
CPU time 32.98 seconds
Started Oct 11 11:35:49 PM UTC 24
Finished Oct 11 11:36:31 PM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1799145025 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 10.prim_prince_test.1799145025
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/10.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/100.prim_prince_test.1552578962
Short name T117
Test name
Test status
Simulation time 3219009763 ps
CPU time 59.47 seconds
Started Oct 11 11:37:35 PM UTC 24
Finished Oct 11 11:38:52 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1552578962 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 100.prim_prince_test.1552578962
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/100.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/101.prim_prince_test.2471080020
Short name T108
Test name
Test status
Simulation time 2846786912 ps
CPU time 54.87 seconds
Started Oct 11 11:37:35 PM UTC 24
Finished Oct 11 11:38:45 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2471080020 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 101.prim_prince_test.2471080020
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/101.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/102.prim_prince_test.2646081312
Short name T87
Test name
Test status
Simulation time 1771463762 ps
CPU time 33.21 seconds
Started Oct 11 11:37:39 PM UTC 24
Finished Oct 11 11:38:22 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2646081312 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 102.prim_prince_test.2646081312
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/102.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/103.prim_prince_test.3691219813
Short name T79
Test name
Test status
Simulation time 1101555824 ps
CPU time 21.52 seconds
Started Oct 11 11:37:39 PM UTC 24
Finished Oct 11 11:38:07 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3691219813 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 103.prim_prince_test.3691219813
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/103.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/104.prim_prince_test.474084127
Short name T103
Test name
Test status
Simulation time 2394623955 ps
CPU time 45.83 seconds
Started Oct 11 11:37:39 PM UTC 24
Finished Oct 11 11:38:37 PM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=474084127 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 104.prim_prince_test.474084127
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/104.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/105.prim_prince_test.3252264524
Short name T91
Test name
Test status
Simulation time 1933933956 ps
CPU time 37.19 seconds
Started Oct 11 11:37:39 PM UTC 24
Finished Oct 11 11:38:26 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3252264524 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 105.prim_prince_test.3252264524
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/105.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/106.prim_prince_test.2114984031
Short name T99
Test name
Test status
Simulation time 1977360520 ps
CPU time 37.84 seconds
Started Oct 11 11:37:44 PM UTC 24
Finished Oct 11 11:38:33 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2114984031 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 106.prim_prince_test.2114984031
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/106.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/107.prim_prince_test.3963434017
Short name T124
Test name
Test status
Simulation time 3042915466 ps
CPU time 56.85 seconds
Started Oct 11 11:37:45 PM UTC 24
Finished Oct 11 11:38:58 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3963434017 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 107.prim_prince_test.3963434017
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/107.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/108.prim_prince_test.24499263
Short name T114
Test name
Test status
Simulation time 2579887685 ps
CPU time 47.8 seconds
Started Oct 11 11:37:47 PM UTC 24
Finished Oct 11 11:38:49 PM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=24499263 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 108.prim_prince_test.24499263
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/108.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/109.prim_prince_test.3391513910
Short name T110
Test name
Test status
Simulation time 2380210038 ps
CPU time 45.84 seconds
Started Oct 11 11:37:48 PM UTC 24
Finished Oct 11 11:38:47 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3391513910 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 109.prim_prince_test.3391513910
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/109.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/110.prim_prince_test.875748011
Short name T129
Test name
Test status
Simulation time 3194151676 ps
CPU time 58.57 seconds
Started Oct 11 11:37:50 PM UTC 24
Finished Oct 11 11:39:05 PM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=875748011 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 110.prim_prince_test.875748011
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/110.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/111.prim_prince_test.646369180
Short name T107
Test name
Test status
Simulation time 2285670330 ps
CPU time 42.54 seconds
Started Oct 11 11:37:50 PM UTC 24
Finished Oct 11 11:38:44 PM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=646369180 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 111.prim_prince_test.646369180
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/111.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/112.prim_prince_test.2068299105
Short name T89
Test name
Test status
Simulation time 1326094803 ps
CPU time 25.67 seconds
Started Oct 11 11:37:51 PM UTC 24
Finished Oct 11 11:38:24 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2068299105 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 112.prim_prince_test.2068299105
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/112.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/113.prim_prince_test.3350301840
Short name T84
Test name
Test status
Simulation time 824076480 ps
CPU time 16.06 seconds
Started Oct 11 11:37:53 PM UTC 24
Finished Oct 11 11:38:14 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3350301840 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 113.prim_prince_test.3350301840
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/113.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/114.prim_prince_test.3357606277
Short name T139
Test name
Test status
Simulation time 3677509761 ps
CPU time 67.51 seconds
Started Oct 11 11:37:55 PM UTC 24
Finished Oct 11 11:39:21 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3357606277 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 114.prim_prince_test.3357606277
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/114.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/115.prim_prince_test.1437541016
Short name T113
Test name
Test status
Simulation time 2101375940 ps
CPU time 40 seconds
Started Oct 11 11:37:57 PM UTC 24
Finished Oct 11 11:38:49 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1437541016 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 115.prim_prince_test.1437541016
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/115.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/116.prim_prince_test.54340314
Short name T109
Test name
Test status
Simulation time 1912376245 ps
CPU time 35.9 seconds
Started Oct 11 11:37:59 PM UTC 24
Finished Oct 11 11:38:46 PM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=54340314 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 116.prim_prince_test.54340314
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/116.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/117.prim_prince_test.2227911376
Short name T130
Test name
Test status
Simulation time 2707806339 ps
CPU time 51.84 seconds
Started Oct 11 11:38:01 PM UTC 24
Finished Oct 11 11:39:07 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2227911376 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 117.prim_prince_test.2227911376
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/117.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/118.prim_prince_test.1442415035
Short name T119
Test name
Test status
Simulation time 2176743501 ps
CPU time 40.27 seconds
Started Oct 11 11:38:01 PM UTC 24
Finished Oct 11 11:38:53 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1442415035 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 118.prim_prince_test.1442415035
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/118.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/119.prim_prince_test.936309594
Short name T136
Test name
Test status
Simulation time 3041246882 ps
CPU time 57.82 seconds
Started Oct 11 11:38:02 PM UTC 24
Finished Oct 11 11:39:16 PM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=936309594 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 119.prim_prince_test.936309594
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/119.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/12.prim_prince_test.2418291015
Short name T26
Test name
Test status
Simulation time 2313070979 ps
CPU time 44.87 seconds
Started Oct 11 11:35:49 PM UTC 24
Finished Oct 11 11:36:46 PM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2418291015 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 12.prim_prince_test.2418291015
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/12.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/120.prim_prince_test.4245058165
Short name T121
Test name
Test status
Simulation time 2000147314 ps
CPU time 38.5 seconds
Started Oct 11 11:38:05 PM UTC 24
Finished Oct 11 11:38:54 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4245058165 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 120.prim_prince_test.4245058165
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/120.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/121.prim_prince_test.2302687089
Short name T102
Test name
Test status
Simulation time 1203771547 ps
CPU time 23.35 seconds
Started Oct 11 11:38:06 PM UTC 24
Finished Oct 11 11:38:37 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2302687089 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 121.prim_prince_test.2302687089
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/121.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/122.prim_prince_test.2723645161
Short name T128
Test name
Test status
Simulation time 2346760506 ps
CPU time 44.78 seconds
Started Oct 11 11:38:08 PM UTC 24
Finished Oct 11 11:39:04 PM UTC 24
Peak memory 156464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2723645161 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 122.prim_prince_test.2723645161
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/122.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/123.prim_prince_test.270620048
Short name T115
Test name
Test status
Simulation time 1648868740 ps
CPU time 31.8 seconds
Started Oct 11 11:38:09 PM UTC 24
Finished Oct 11 11:38:49 PM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=270620048 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 123.prim_prince_test.270620048
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/123.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/124.prim_prince_test.2443575978
Short name T163
Test name
Test status
Simulation time 3749652473 ps
CPU time 70.88 seconds
Started Oct 11 11:38:12 PM UTC 24
Finished Oct 11 11:39:41 PM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2443575978 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 124.prim_prince_test.2443575978
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/124.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/125.prim_prince_test.989193876
Short name T104
Test name
Test status
Simulation time 1140956304 ps
CPU time 21.07 seconds
Started Oct 11 11:38:13 PM UTC 24
Finished Oct 11 11:38:40 PM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=989193876 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 125.prim_prince_test.989193876
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/125.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/126.prim_prince_test.3747064560
Short name T118
Test name
Test status
Simulation time 1509382472 ps
CPU time 28.95 seconds
Started Oct 11 11:38:15 PM UTC 24
Finished Oct 11 11:38:52 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3747064560 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 126.prim_prince_test.3747064560
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/126.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/127.prim_prince_test.60935130
Short name T123
Test name
Test status
Simulation time 1718271591 ps
CPU time 31.96 seconds
Started Oct 11 11:38:15 PM UTC 24
Finished Oct 11 11:38:56 PM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=60935130 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 127.prim_prince_test.60935130
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/127.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/128.prim_prince_test.997537160
Short name T161
Test name
Test status
Simulation time 3481451092 ps
CPU time 66.04 seconds
Started Oct 11 11:38:17 PM UTC 24
Finished Oct 11 11:39:41 PM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=997537160 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 128.prim_prince_test.997537160
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/128.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/129.prim_prince_test.4160768326
Short name T120
Test name
Test status
Simulation time 1456479414 ps
CPU time 27.05 seconds
Started Oct 11 11:38:18 PM UTC 24
Finished Oct 11 11:38:54 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4160768326 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 129.prim_prince_test.4160768326
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/129.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/13.prim_prince_test.3839468032
Short name T18
Test name
Test status
Simulation time 1850866083 ps
CPU time 35.96 seconds
Started Oct 11 11:35:50 PM UTC 24
Finished Oct 11 11:36:36 PM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3839468032 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 13.prim_prince_test.3839468032
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/13.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/130.prim_prince_test.2346255832
Short name T112
Test name
Test status
Simulation time 1136075633 ps
CPU time 21.97 seconds
Started Oct 11 11:38:20 PM UTC 24
Finished Oct 11 11:38:48 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2346255832 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 130.prim_prince_test.2346255832
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/130.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/131.prim_prince_test.4201690190
Short name T131
Test name
Test status
Simulation time 2010054997 ps
CPU time 36.87 seconds
Started Oct 11 11:38:20 PM UTC 24
Finished Oct 11 11:39:07 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4201690190 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 131.prim_prince_test.4201690190
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/131.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/132.prim_prince_test.2426509413
Short name T138
Test name
Test status
Simulation time 2441862837 ps
CPU time 44.76 seconds
Started Oct 11 11:38:23 PM UTC 24
Finished Oct 11 11:39:21 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2426509413 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 132.prim_prince_test.2426509413
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/132.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/133.prim_prince_test.641189749
Short name T152
Test name
Test status
Simulation time 2877925590 ps
CPU time 54.72 seconds
Started Oct 11 11:38:23 PM UTC 24
Finished Oct 11 11:39:32 PM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=641189749 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 133.prim_prince_test.641189749
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/133.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/134.prim_prince_test.3663905181
Short name T137
Test name
Test status
Simulation time 2194555140 ps
CPU time 41.73 seconds
Started Oct 11 11:38:23 PM UTC 24
Finished Oct 11 11:39:16 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3663905181 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 134.prim_prince_test.3663905181
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/134.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/135.prim_prince_test.947030357
Short name T134
Test name
Test status
Simulation time 2031642147 ps
CPU time 38.21 seconds
Started Oct 11 11:38:24 PM UTC 24
Finished Oct 11 11:39:13 PM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=947030357 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 135.prim_prince_test.947030357
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/135.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/136.prim_prince_test.2947441610
Short name T135
Test name
Test status
Simulation time 2017249837 ps
CPU time 38.11 seconds
Started Oct 11 11:38:25 PM UTC 24
Finished Oct 11 11:39:14 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2947441610 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 136.prim_prince_test.2947441610
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/136.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/137.prim_prince_test.78280846
Short name T160
Test name
Test status
Simulation time 2991998832 ps
CPU time 56.39 seconds
Started Oct 11 11:38:27 PM UTC 24
Finished Oct 11 11:39:39 PM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=78280846 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 137.prim_prince_test.78280846
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/137.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/138.prim_prince_test.3616300448
Short name T143
Test name
Test status
Simulation time 2454114202 ps
CPU time 46.69 seconds
Started Oct 11 11:38:28 PM UTC 24
Finished Oct 11 11:39:27 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3616300448 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 138.prim_prince_test.3616300448
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/138.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/139.prim_prince_test.1743018102
Short name T133
Test name
Test status
Simulation time 1803987807 ps
CPU time 34.18 seconds
Started Oct 11 11:38:29 PM UTC 24
Finished Oct 11 11:39:13 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1743018102 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 139.prim_prince_test.1743018102
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/139.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/14.prim_prince_test.2246274252
Short name T23
Test name
Test status
Simulation time 1978198177 ps
CPU time 38.36 seconds
Started Oct 11 11:35:50 PM UTC 24
Finished Oct 11 11:36:40 PM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2246274252 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 14.prim_prince_test.2246274252
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/14.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/140.prim_prince_test.2849211220
Short name T132
Test name
Test status
Simulation time 1759866516 ps
CPU time 33.37 seconds
Started Oct 11 11:38:29 PM UTC 24
Finished Oct 11 11:39:12 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2849211220 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 140.prim_prince_test.2849211220
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/140.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/141.prim_prince_test.3858582764
Short name T164
Test name
Test status
Simulation time 3001856599 ps
CPU time 57.33 seconds
Started Oct 11 11:38:30 PM UTC 24
Finished Oct 11 11:39:42 PM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3858582764 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 141.prim_prince_test.3858582764
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/141.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/142.prim_prince_test.3351504488
Short name T169
Test name
Test status
Simulation time 3234895847 ps
CPU time 60.69 seconds
Started Oct 11 11:38:30 PM UTC 24
Finished Oct 11 11:39:47 PM UTC 24
Peak memory 155032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3351504488 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 142.prim_prince_test.3351504488
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/142.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/143.prim_prince_test.1702059420
Short name T155
Test name
Test status
Simulation time 2799604536 ps
CPU time 52.28 seconds
Started Oct 11 11:38:30 PM UTC 24
Finished Oct 11 11:39:37 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1702059420 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 143.prim_prince_test.1702059420
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/143.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/144.prim_prince_test.3421268261
Short name T157
Test name
Test status
Simulation time 2758456589 ps
CPU time 52.64 seconds
Started Oct 11 11:38:31 PM UTC 24
Finished Oct 11 11:39:38 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3421268261 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 144.prim_prince_test.3421268261
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/144.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/145.prim_prince_test.931203256
Short name T145
Test name
Test status
Simulation time 2346432589 ps
CPU time 44.78 seconds
Started Oct 11 11:38:31 PM UTC 24
Finished Oct 11 11:39:28 PM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=931203256 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 145.prim_prince_test.931203256
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/145.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/146.prim_prince_test.3284893092
Short name T126
Test name
Test status
Simulation time 1191124732 ps
CPU time 21.97 seconds
Started Oct 11 11:38:32 PM UTC 24
Finished Oct 11 11:39:01 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3284893092 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 146.prim_prince_test.3284893092
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/146.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/147.prim_prince_test.3002292243
Short name T142
Test name
Test status
Simulation time 2199215897 ps
CPU time 40.64 seconds
Started Oct 11 11:38:34 PM UTC 24
Finished Oct 11 11:39:26 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3002292243 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 147.prim_prince_test.3002292243
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/147.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/148.prim_prince_test.4016427215
Short name T141
Test name
Test status
Simulation time 2140964275 ps
CPU time 40.71 seconds
Started Oct 11 11:38:34 PM UTC 24
Finished Oct 11 11:39:25 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4016427215 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 148.prim_prince_test.4016427215
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/148.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/149.prim_prince_test.1957618309
Short name T127
Test name
Test status
Simulation time 1144351818 ps
CPU time 21.37 seconds
Started Oct 11 11:38:35 PM UTC 24
Finished Oct 11 11:39:03 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1957618309 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 149.prim_prince_test.1957618309
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/149.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/15.prim_prince_test.166324051
Short name T6
Test name
Test status
Simulation time 1068786787 ps
CPU time 20.64 seconds
Started Oct 11 11:35:52 PM UTC 24
Finished Oct 11 11:36:19 PM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=166324051 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 15.prim_prince_test.166324051
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/15.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/150.prim_prince_test.2539475366
Short name T179
Test name
Test status
Simulation time 3295769349 ps
CPU time 60.76 seconds
Started Oct 11 11:38:38 PM UTC 24
Finished Oct 11 11:39:56 PM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2539475366 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 150.prim_prince_test.2539475366
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/150.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/151.prim_prince_test.1847540894
Short name T182
Test name
Test status
Simulation time 3396459302 ps
CPU time 63.21 seconds
Started Oct 11 11:38:38 PM UTC 24
Finished Oct 11 11:39:58 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1847540894 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 151.prim_prince_test.1847540894
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/151.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/152.prim_prince_test.384631194
Short name T185
Test name
Test status
Simulation time 3685655652 ps
CPU time 68.46 seconds
Started Oct 11 11:38:40 PM UTC 24
Finished Oct 11 11:40:07 PM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=384631194 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 152.prim_prince_test.384631194
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/152.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/153.prim_prince_test.3841300872
Short name T168
Test name
Test status
Simulation time 2799790968 ps
CPU time 51.09 seconds
Started Oct 11 11:38:41 PM UTC 24
Finished Oct 11 11:39:47 PM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3841300872 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 153.prim_prince_test.3841300872
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/153.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/154.prim_prince_test.1682935838
Short name T167
Test name
Test status
Simulation time 2678125727 ps
CPU time 49.14 seconds
Started Oct 11 11:38:42 PM UTC 24
Finished Oct 11 11:39:45 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1682935838 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 154.prim_prince_test.1682935838
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/154.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/155.prim_prince_test.4210621100
Short name T140
Test name
Test status
Simulation time 1728582429 ps
CPU time 32.33 seconds
Started Oct 11 11:38:42 PM UTC 24
Finished Oct 11 11:39:24 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4210621100 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 155.prim_prince_test.4210621100
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/155.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/156.prim_prince_test.449245487
Short name T147
Test name
Test status
Simulation time 1811980941 ps
CPU time 34.19 seconds
Started Oct 11 11:38:46 PM UTC 24
Finished Oct 11 11:39:29 PM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=449245487 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 156.prim_prince_test.449245487
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/156.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/157.prim_prince_test.585059534
Short name T173
Test name
Test status
Simulation time 2663211616 ps
CPU time 50.38 seconds
Started Oct 11 11:38:46 PM UTC 24
Finished Oct 11 11:39:49 PM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=585059534 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 157.prim_prince_test.585059534
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/157.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/158.prim_prince_test.3012853254
Short name T175
Test name
Test status
Simulation time 2751337006 ps
CPU time 50.54 seconds
Started Oct 11 11:38:47 PM UTC 24
Finished Oct 11 11:39:51 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3012853254 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 158.prim_prince_test.3012853254
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/158.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/159.prim_prince_test.3925735124
Short name T177
Test name
Test status
Simulation time 2766800876 ps
CPU time 52.72 seconds
Started Oct 11 11:38:48 PM UTC 24
Finished Oct 11 11:39:55 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3925735124 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 159.prim_prince_test.3925735124
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/159.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/16.prim_prince_test.2230773143
Short name T21
Test name
Test status
Simulation time 1820833315 ps
CPU time 35.79 seconds
Started Oct 11 11:35:52 PM UTC 24
Finished Oct 11 11:36:38 PM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2230773143 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 16.prim_prince_test.2230773143
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/16.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/160.prim_prince_test.560249321
Short name T172
Test name
Test status
Simulation time 2497031212 ps
CPU time 47.29 seconds
Started Oct 11 11:38:49 PM UTC 24
Finished Oct 11 11:39:49 PM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=560249321 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 160.prim_prince_test.560249321
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/160.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/161.prim_prince_test.3965691364
Short name T146
Test name
Test status
Simulation time 1657874978 ps
CPU time 31.14 seconds
Started Oct 11 11:38:49 PM UTC 24
Finished Oct 11 11:39:29 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3965691364 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 161.prim_prince_test.3965691364
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/161.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/162.prim_prince_test.3979505783
Short name T181
Test name
Test status
Simulation time 2831582028 ps
CPU time 52.43 seconds
Started Oct 11 11:38:50 PM UTC 24
Finished Oct 11 11:39:57 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3979505783 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 162.prim_prince_test.3979505783
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/162.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/163.prim_prince_test.3868104999
Short name T184
Test name
Test status
Simulation time 3242649435 ps
CPU time 59.33 seconds
Started Oct 11 11:38:50 PM UTC 24
Finished Oct 11 11:40:06 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3868104999 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 163.prim_prince_test.3868104999
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/163.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/164.prim_prince_test.2673611907
Short name T153
Test name
Test status
Simulation time 1866781185 ps
CPU time 35.77 seconds
Started Oct 11 11:38:50 PM UTC 24
Finished Oct 11 11:39:36 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2673611907 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 164.prim_prince_test.2673611907
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/164.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/165.prim_prince_test.366287804
Short name T165
Test name
Test status
Simulation time 2237112303 ps
CPU time 41.54 seconds
Started Oct 11 11:38:51 PM UTC 24
Finished Oct 11 11:39:44 PM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=366287804 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 165.prim_prince_test.366287804
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/165.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/166.prim_prince_test.2016052268
Short name T195
Test name
Test status
Simulation time 3350466549 ps
CPU time 63.53 seconds
Started Oct 11 11:38:52 PM UTC 24
Finished Oct 11 11:40:12 PM UTC 24
Peak memory 156400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2016052268 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 166.prim_prince_test.2016052268
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/166.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/167.prim_prince_test.2303867514
Short name T144
Test name
Test status
Simulation time 1402250622 ps
CPU time 26.91 seconds
Started Oct 11 11:38:53 PM UTC 24
Finished Oct 11 11:39:27 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2303867514 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 167.prim_prince_test.2303867514
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/167.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/168.prim_prince_test.1026258513
Short name T150
Test name
Test status
Simulation time 1536890973 ps
CPU time 29.57 seconds
Started Oct 11 11:38:53 PM UTC 24
Finished Oct 11 11:39:31 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1026258513 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 168.prim_prince_test.1026258513
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/168.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/169.prim_prince_test.3563838105
Short name T170
Test name
Test status
Simulation time 2272732756 ps
CPU time 42.04 seconds
Started Oct 11 11:38:54 PM UTC 24
Finished Oct 11 11:39:48 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3563838105 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 169.prim_prince_test.3563838105
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/169.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/17.prim_prince_test.31515397
Short name T9
Test name
Test status
Simulation time 1285634163 ps
CPU time 25.01 seconds
Started Oct 11 11:35:53 PM UTC 24
Finished Oct 11 11:36:26 PM UTC 24
Peak memory 154984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31515397 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 17.prim_prince_test.31515397
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/17.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/170.prim_prince_test.2985779208
Short name T174
Test name
Test status
Simulation time 2268764827 ps
CPU time 43.03 seconds
Started Oct 11 11:38:55 PM UTC 24
Finished Oct 11 11:39:50 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2985779208 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 170.prim_prince_test.2985779208
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/170.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/171.prim_prince_test.3722386532
Short name T197
Test name
Test status
Simulation time 3409224907 ps
CPU time 63.83 seconds
Started Oct 11 11:38:55 PM UTC 24
Finished Oct 11 11:40:16 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3722386532 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 171.prim_prince_test.3722386532
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/171.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/172.prim_prince_test.3941313136
Short name T154
Test name
Test status
Simulation time 1732462611 ps
CPU time 31.97 seconds
Started Oct 11 11:38:55 PM UTC 24
Finished Oct 11 11:39:36 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3941313136 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 172.prim_prince_test.3941313136
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/172.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/173.prim_prince_test.4093780617
Short name T151
Test name
Test status
Simulation time 1365197078 ps
CPU time 26.14 seconds
Started Oct 11 11:38:57 PM UTC 24
Finished Oct 11 11:39:31 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4093780617 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 173.prim_prince_test.4093780617
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/173.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/174.prim_prince_test.3606838363
Short name T159
Test name
Test status
Simulation time 1648673549 ps
CPU time 31.06 seconds
Started Oct 11 11:38:58 PM UTC 24
Finished Oct 11 11:39:38 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3606838363 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 174.prim_prince_test.3606838363
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/174.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/175.prim_prince_test.3992961748
Short name T149
Test name
Test status
Simulation time 1225696567 ps
CPU time 23.73 seconds
Started Oct 11 11:39:00 PM UTC 24
Finished Oct 11 11:39:30 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3992961748 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 175.prim_prince_test.3992961748
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/175.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/176.prim_prince_test.2569056753
Short name T162
Test name
Test status
Simulation time 1617408250 ps
CPU time 30.57 seconds
Started Oct 11 11:39:02 PM UTC 24
Finished Oct 11 11:39:41 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2569056753 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 176.prim_prince_test.2569056753
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/176.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/177.prim_prince_test.544528691
Short name T183
Test name
Test status
Simulation time 2425110686 ps
CPU time 45.18 seconds
Started Oct 11 11:39:04 PM UTC 24
Finished Oct 11 11:40:02 PM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=544528691 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 177.prim_prince_test.544528691
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/177.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/178.prim_prince_test.1845861441
Short name T148
Test name
Test status
Simulation time 982828275 ps
CPU time 19.02 seconds
Started Oct 11 11:39:05 PM UTC 24
Finished Oct 11 11:39:30 PM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1845861441 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 178.prim_prince_test.1845861441
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/178.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/179.prim_prince_test.2893618409
Short name T158
Test name
Test status
Simulation time 1335995860 ps
CPU time 25.78 seconds
Started Oct 11 11:39:05 PM UTC 24
Finished Oct 11 11:39:38 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2893618409 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 179.prim_prince_test.2893618409
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/179.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/18.prim_prince_test.3171101101
Short name T15
Test name
Test status
Simulation time 1423698467 ps
CPU time 27.22 seconds
Started Oct 11 11:35:54 PM UTC 24
Finished Oct 11 11:36:30 PM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3171101101 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 18.prim_prince_test.3171101101
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/18.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/180.prim_prince_test.182725257
Short name T156
Test name
Test status
Simulation time 1198792107 ps
CPU time 23.03 seconds
Started Oct 11 11:39:08 PM UTC 24
Finished Oct 11 11:39:38 PM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=182725257 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 180.prim_prince_test.182725257
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/180.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/181.prim_prince_test.1015739435
Short name T200
Test name
Test status
Simulation time 3013291075 ps
CPU time 56.35 seconds
Started Oct 11 11:39:08 PM UTC 24
Finished Oct 11 11:40:20 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1015739435 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 181.prim_prince_test.1015739435
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/181.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/182.prim_prince_test.3346410688
Short name T176
Test name
Test status
Simulation time 1620995288 ps
CPU time 30.66 seconds
Started Oct 11 11:39:12 PM UTC 24
Finished Oct 11 11:39:52 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3346410688 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 182.prim_prince_test.3346410688
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/182.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/183.prim_prince_test.960607909
Short name T125
Test name
Test status
Simulation time 1299861725 ps
CPU time 25.05 seconds
Started Oct 11 11:39:13 PM UTC 24
Finished Oct 11 11:39:46 PM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=960607909 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 183.prim_prince_test.960607909
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/183.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/184.prim_prince_test.1368471181
Short name T222
Test name
Test status
Simulation time 3748568477 ps
CPU time 69.84 seconds
Started Oct 11 11:39:14 PM UTC 24
Finished Oct 11 11:40:43 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1368471181 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 184.prim_prince_test.1368471181
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/184.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/185.prim_prince_test.3276487501
Short name T166
Test name
Test status
Simulation time 1233449016 ps
CPU time 23.42 seconds
Started Oct 11 11:39:15 PM UTC 24
Finished Oct 11 11:39:45 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3276487501 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 185.prim_prince_test.3276487501
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/185.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/186.prim_prince_test.3736309880
Short name T180
Test name
Test status
Simulation time 1645729346 ps
CPU time 31.44 seconds
Started Oct 11 11:39:17 PM UTC 24
Finished Oct 11 11:39:57 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3736309880 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 186.prim_prince_test.3736309880
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/186.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/187.prim_prince_test.2599673048
Short name T212
Test name
Test status
Simulation time 3145414551 ps
CPU time 57.67 seconds
Started Oct 11 11:39:17 PM UTC 24
Finished Oct 11 11:40:30 PM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2599673048 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 187.prim_prince_test.2599673048
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/187.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/188.prim_prince_test.995455800
Short name T171
Test name
Test status
Simulation time 1057207072 ps
CPU time 20.31 seconds
Started Oct 11 11:39:22 PM UTC 24
Finished Oct 11 11:39:48 PM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=995455800 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 188.prim_prince_test.995455800
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/188.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/189.prim_prince_test.222745695
Short name T209
Test name
Test status
Simulation time 2756115048 ps
CPU time 50.27 seconds
Started Oct 11 11:39:22 PM UTC 24
Finished Oct 11 11:40:26 PM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=222745695 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 189.prim_prince_test.222745695
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/189.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/19.prim_prince_test.1260808392
Short name T20
Test name
Test status
Simulation time 1717788794 ps
CPU time 33.62 seconds
Started Oct 11 11:35:54 PM UTC 24
Finished Oct 11 11:36:38 PM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1260808392 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 19.prim_prince_test.1260808392
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/19.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/190.prim_prince_test.203274586
Short name T225
Test name
Test status
Simulation time 3464152347 ps
CPU time 64.32 seconds
Started Oct 11 11:39:25 PM UTC 24
Finished Oct 11 11:40:47 PM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=203274586 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 190.prim_prince_test.203274586
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/190.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/191.prim_prince_test.1024667655
Short name T202
Test name
Test status
Simulation time 2263320814 ps
CPU time 43.09 seconds
Started Oct 11 11:39:26 PM UTC 24
Finished Oct 11 11:40:21 PM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1024667655 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 191.prim_prince_test.1024667655
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/191.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/192.prim_prince_test.3546114938
Short name T220
Test name
Test status
Simulation time 3131376802 ps
CPU time 58.57 seconds
Started Oct 11 11:39:26 PM UTC 24
Finished Oct 11 11:40:40 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3546114938 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 192.prim_prince_test.3546114938
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/192.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/193.prim_prince_test.1672699012
Short name T196
Test name
Test status
Simulation time 1859531016 ps
CPU time 34.94 seconds
Started Oct 11 11:39:27 PM UTC 24
Finished Oct 11 11:40:12 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1672699012 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 193.prim_prince_test.1672699012
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/193.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/194.prim_prince_test.1694968157
Short name T226
Test name
Test status
Simulation time 3536568147 ps
CPU time 65.4 seconds
Started Oct 11 11:39:28 PM UTC 24
Finished Oct 11 11:40:52 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1694968157 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 194.prim_prince_test.1694968157
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/194.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/195.prim_prince_test.1804651961
Short name T189
Test name
Test status
Simulation time 1616944031 ps
CPU time 31.05 seconds
Started Oct 11 11:39:30 PM UTC 24
Finished Oct 11 11:40:09 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1804651961 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 195.prim_prince_test.1804651961
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/195.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/196.prim_prince_test.893369294
Short name T230
Test name
Test status
Simulation time 3464699779 ps
CPU time 65.46 seconds
Started Oct 11 11:39:30 PM UTC 24
Finished Oct 11 11:40:53 PM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=893369294 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 196.prim_prince_test.893369294
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/196.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/197.prim_prince_test.1643690512
Short name T205
Test name
Test status
Simulation time 2128072836 ps
CPU time 40.53 seconds
Started Oct 11 11:39:31 PM UTC 24
Finished Oct 11 11:40:23 PM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1643690512 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 197.prim_prince_test.1643690512
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/197.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/198.prim_prince_test.971354667
Short name T193
Test name
Test status
Simulation time 1622203464 ps
CPU time 31.19 seconds
Started Oct 11 11:39:31 PM UTC 24
Finished Oct 11 11:40:11 PM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=971354667 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 198.prim_prince_test.971354667
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/198.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/199.prim_prince_test.779803700
Short name T221
Test name
Test status
Simulation time 2937400630 ps
CPU time 54.83 seconds
Started Oct 11 11:39:31 PM UTC 24
Finished Oct 11 11:40:41 PM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=779803700 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 199.prim_prince_test.779803700
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/199.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/2.prim_prince_test.2416801823
Short name T1
Test name
Test status
Simulation time 815032866 ps
CPU time 15.07 seconds
Started Oct 11 11:35:47 PM UTC 24
Finished Oct 11 11:36:08 PM UTC 24
Peak memory 153104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2416801823 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 2.prim_prince_test.2416801823
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/2.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/20.prim_prince_test.1613964614
Short name T25
Test name
Test status
Simulation time 1867925845 ps
CPU time 35.29 seconds
Started Oct 11 11:35:54 PM UTC 24
Finished Oct 11 11:36:41 PM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1613964614 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 20.prim_prince_test.1613964614
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/20.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/200.prim_prince_test.811340865
Short name T206
Test name
Test status
Simulation time 2137661315 ps
CPU time 39.44 seconds
Started Oct 11 11:39:32 PM UTC 24
Finished Oct 11 11:40:23 PM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=811340865 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 200.prim_prince_test.811340865
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/200.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/201.prim_prince_test.1935861519
Short name T186
Test name
Test status
Simulation time 1441708440 ps
CPU time 27.72 seconds
Started Oct 11 11:39:32 PM UTC 24
Finished Oct 11 11:40:08 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1935861519 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 201.prim_prince_test.1935861519
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/201.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/202.prim_prince_test.621671670
Short name T178
Test name
Test status
Simulation time 888148304 ps
CPU time 16.71 seconds
Started Oct 11 11:39:33 PM UTC 24
Finished Oct 11 11:39:55 PM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=621671670 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 202.prim_prince_test.621671670
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/202.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/203.prim_prince_test.1911165467
Short name T235
Test name
Test status
Simulation time 3360249361 ps
CPU time 62.49 seconds
Started Oct 11 11:39:36 PM UTC 24
Finished Oct 11 11:40:56 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1911165467 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 203.prim_prince_test.1911165467
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/203.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/204.prim_prince_test.434429962
Short name T198
Test name
Test status
Simulation time 1660304841 ps
CPU time 31.44 seconds
Started Oct 11 11:39:37 PM UTC 24
Finished Oct 11 11:40:18 PM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=434429962 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 204.prim_prince_test.434429962
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/204.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/205.prim_prince_test.3637104942
Short name T207
Test name
Test status
Simulation time 1962062187 ps
CPU time 37.2 seconds
Started Oct 11 11:39:37 PM UTC 24
Finished Oct 11 11:40:25 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3637104942 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 205.prim_prince_test.3637104942
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/205.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/206.prim_prince_test.1708759890
Short name T219
Test name
Test status
Simulation time 2620421260 ps
CPU time 48.14 seconds
Started Oct 11 11:39:39 PM UTC 24
Finished Oct 11 11:40:40 PM UTC 24
Peak memory 154804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1708759890 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 206.prim_prince_test.1708759890
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/206.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/207.prim_prince_test.931646980
Short name T188
Test name
Test status
Simulation time 1234276136 ps
CPU time 23.7 seconds
Started Oct 11 11:39:39 PM UTC 24
Finished Oct 11 11:40:09 PM UTC 24
Peak memory 154700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=931646980 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 207.prim_prince_test.931646980
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/207.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/208.prim_prince_test.3484133232
Short name T201
Test name
Test status
Simulation time 1706585420 ps
CPU time 32.13 seconds
Started Oct 11 11:39:39 PM UTC 24
Finished Oct 11 11:40:20 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3484133232 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 208.prim_prince_test.3484133232
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/208.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/209.prim_prince_test.2566921345
Short name T192
Test name
Test status
Simulation time 1224693437 ps
CPU time 23.79 seconds
Started Oct 11 11:39:40 PM UTC 24
Finished Oct 11 11:40:11 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2566921345 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 209.prim_prince_test.2566921345
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/209.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/21.prim_prince_test.3789779942
Short name T13
Test name
Test status
Simulation time 1307523007 ps
CPU time 25.68 seconds
Started Oct 11 11:35:54 PM UTC 24
Finished Oct 11 11:36:28 PM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3789779942 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 21.prim_prince_test.3789779942
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/21.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/210.prim_prince_test.3615755663
Short name T211
Test name
Test status
Simulation time 2040400389 ps
CPU time 38.48 seconds
Started Oct 11 11:39:40 PM UTC 24
Finished Oct 11 11:40:29 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3615755663 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 210.prim_prince_test.3615755663
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/210.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/211.prim_prince_test.3861507941
Short name T203
Test name
Test status
Simulation time 1619637089 ps
CPU time 30.89 seconds
Started Oct 11 11:39:42 PM UTC 24
Finished Oct 11 11:40:22 PM UTC 24
Peak memory 154944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3861507941 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 211.prim_prince_test.3861507941
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/211.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/212.prim_prince_test.569627684
Short name T250
Test name
Test status
Simulation time 3625123355 ps
CPU time 67.07 seconds
Started Oct 11 11:39:42 PM UTC 24
Finished Oct 11 11:41:07 PM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=569627684 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 212.prim_prince_test.569627684
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/212.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/213.prim_prince_test.674665037
Short name T227
Test name
Test status
Simulation time 2903773691 ps
CPU time 55 seconds
Started Oct 11 11:39:42 PM UTC 24
Finished Oct 11 11:40:52 PM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=674665037 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 213.prim_prince_test.674665037
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/213.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/214.prim_prince_test.3016861038
Short name T248
Test name
Test status
Simulation time 3508080856 ps
CPU time 66.43 seconds
Started Oct 11 11:39:43 PM UTC 24
Finished Oct 11 11:41:07 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3016861038 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 214.prim_prince_test.3016861038
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/214.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/215.prim_prince_test.1210432492
Short name T239
Test name
Test status
Simulation time 3096156440 ps
CPU time 57.13 seconds
Started Oct 11 11:39:44 PM UTC 24
Finished Oct 11 11:40:58 PM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1210432492 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 215.prim_prince_test.1210432492
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/215.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/216.prim_prince_test.3300508093
Short name T255
Test name
Test status
Simulation time 3658535768 ps
CPU time 67.32 seconds
Started Oct 11 11:39:46 PM UTC 24
Finished Oct 11 11:41:12 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3300508093 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 216.prim_prince_test.3300508093
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/216.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/217.prim_prince_test.2132495044
Short name T187
Test name
Test status
Simulation time 805823988 ps
CPU time 15.52 seconds
Started Oct 11 11:39:47 PM UTC 24
Finished Oct 11 11:40:08 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2132495044 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 217.prim_prince_test.2132495044
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/217.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/218.prim_prince_test.2617841083
Short name T199
Test name
Test status
Simulation time 1299149578 ps
CPU time 24.1 seconds
Started Oct 11 11:39:47 PM UTC 24
Finished Oct 11 11:40:19 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2617841083 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 218.prim_prince_test.2617841083
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/218.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/219.prim_prince_test.2005110182
Short name T190
Test name
Test status
Simulation time 826479090 ps
CPU time 15.92 seconds
Started Oct 11 11:39:48 PM UTC 24
Finished Oct 11 11:40:10 PM UTC 24
Peak memory 154768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2005110182 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 219.prim_prince_test.2005110182
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/219.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/22.prim_prince_test.941012248
Short name T30
Test name
Test status
Simulation time 2389097082 ps
CPU time 46.1 seconds
Started Oct 11 11:35:54 PM UTC 24
Finished Oct 11 11:36:54 PM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=941012248 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 22.prim_prince_test.941012248
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/22.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/220.prim_prince_test.3235837413
Short name T210
Test name
Test status
Simulation time 1656567304 ps
CPU time 30.82 seconds
Started Oct 11 11:39:48 PM UTC 24
Finished Oct 11 11:40:28 PM UTC 24
Peak memory 154828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3235837413 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 220.prim_prince_test.3235837413
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/220.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/221.prim_prince_test.4190881648
Short name T191
Test name
Test status
Simulation time 801373510 ps
CPU time 15.32 seconds
Started Oct 11 11:39:49 PM UTC 24
Finished Oct 11 11:40:10 PM UTC 24
Peak memory 154804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4190881648 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 221.prim_prince_test.4190881648
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/221.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/222.prim_prince_test.3938583380
Short name T246
Test name
Test status
Simulation time 3206459335 ps
CPU time 60.05 seconds
Started Oct 11 11:39:49 PM UTC 24
Finished Oct 11 11:41:06 PM UTC 24
Peak memory 154888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3938583380 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 222.prim_prince_test.3938583380
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/222.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/223.prim_prince_test.2391430394
Short name T223
Test name
Test status
Simulation time 2302409765 ps
CPU time 42.59 seconds
Started Oct 11 11:39:49 PM UTC 24
Finished Oct 11 11:40:44 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2391430394 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 223.prim_prince_test.2391430394
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/223.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/224.prim_prince_test.1736495387
Short name T242
Test name
Test status
Simulation time 3061522157 ps
CPU time 57.98 seconds
Started Oct 11 11:39:51 PM UTC 24
Finished Oct 11 11:41:04 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1736495387 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 224.prim_prince_test.1736495387
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/224.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/225.prim_prince_test.2835362013
Short name T216
Test name
Test status
Simulation time 1989751535 ps
CPU time 36.9 seconds
Started Oct 11 11:39:51 PM UTC 24
Finished Oct 11 11:40:38 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2835362013 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 225.prim_prince_test.2835362013
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/225.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/226.prim_prince_test.2250553806
Short name T204
Test name
Test status
Simulation time 1275298054 ps
CPU time 24.3 seconds
Started Oct 11 11:39:51 PM UTC 24
Finished Oct 11 11:40:22 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2250553806 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 226.prim_prince_test.2250553806
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/226.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/227.prim_prince_test.2408082462
Short name T228
Test name
Test status
Simulation time 2506623751 ps
CPU time 46.56 seconds
Started Oct 11 11:39:53 PM UTC 24
Finished Oct 11 11:40:52 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2408082462 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 227.prim_prince_test.2408082462
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/227.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/228.prim_prince_test.1925773174
Short name T233
Test name
Test status
Simulation time 2634388227 ps
CPU time 48.33 seconds
Started Oct 11 11:39:53 PM UTC 24
Finished Oct 11 11:40:55 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1925773174 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 228.prim_prince_test.1925773174
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/228.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/229.prim_prince_test.1891576293
Short name T234
Test name
Test status
Simulation time 2505806406 ps
CPU time 47.33 seconds
Started Oct 11 11:39:55 PM UTC 24
Finished Oct 11 11:40:55 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1891576293 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 229.prim_prince_test.1891576293
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/229.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/23.prim_prince_test.981114335
Short name T22
Test name
Test status
Simulation time 1704940342 ps
CPU time 33.59 seconds
Started Oct 11 11:35:56 PM UTC 24
Finished Oct 11 11:36:39 PM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=981114335 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 23.prim_prince_test.981114335
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/23.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/230.prim_prince_test.2770058764
Short name T214
Test name
Test status
Simulation time 1619845783 ps
CPU time 31.09 seconds
Started Oct 11 11:39:56 PM UTC 24
Finished Oct 11 11:40:36 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2770058764 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 230.prim_prince_test.2770058764
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/230.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/231.prim_prince_test.1047817075
Short name T261
Test name
Test status
Simulation time 3432609001 ps
CPU time 64.41 seconds
Started Oct 11 11:39:56 PM UTC 24
Finished Oct 11 11:41:18 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1047817075 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 231.prim_prince_test.1047817075
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/231.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/232.prim_prince_test.1236453114
Short name T208
Test name
Test status
Simulation time 1132033913 ps
CPU time 21.38 seconds
Started Oct 11 11:39:57 PM UTC 24
Finished Oct 11 11:40:25 PM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1236453114 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 232.prim_prince_test.1236453114
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/232.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/233.prim_prince_test.2067321460
Short name T252
Test name
Test status
Simulation time 2990167291 ps
CPU time 56.6 seconds
Started Oct 11 11:39:58 PM UTC 24
Finished Oct 11 11:41:10 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2067321460 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 233.prim_prince_test.2067321460
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/233.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/234.prim_prince_test.4087318384
Short name T218
Test name
Test status
Simulation time 1650940553 ps
CPU time 30.91 seconds
Started Oct 11 11:40:00 PM UTC 24
Finished Oct 11 11:40:40 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4087318384 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 234.prim_prince_test.4087318384
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/234.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/235.prim_prince_test.1129372676
Short name T215
Test name
Test status
Simulation time 1374663650 ps
CPU time 26.1 seconds
Started Oct 11 11:40:03 PM UTC 24
Finished Oct 11 11:40:36 PM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1129372676 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 235.prim_prince_test.1129372676
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/235.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/236.prim_prince_test.612365104
Short name T244
Test name
Test status
Simulation time 2426233971 ps
CPU time 46 seconds
Started Oct 11 11:40:07 PM UTC 24
Finished Oct 11 11:41:05 PM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=612365104 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 236.prim_prince_test.612365104
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/236.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/237.prim_prince_test.2378330206
Short name T254
Test name
Test status
Simulation time 2685693707 ps
CPU time 50.59 seconds
Started Oct 11 11:40:08 PM UTC 24
Finished Oct 11 11:41:12 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2378330206 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 237.prim_prince_test.2378330206
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/237.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/238.prim_prince_test.3837476484
Short name T257
Test name
Test status
Simulation time 2706128268 ps
CPU time 51.05 seconds
Started Oct 11 11:40:09 PM UTC 24
Finished Oct 11 11:41:14 PM UTC 24
Peak memory 154920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3837476484 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 238.prim_prince_test.3837476484
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/238.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/239.prim_prince_test.1007768162
Short name T229
Test name
Test status
Simulation time 1794416329 ps
CPU time 33.98 seconds
Started Oct 11 11:40:09 PM UTC 24
Finished Oct 11 11:40:52 PM UTC 24
Peak memory 154868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1007768162 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 239.prim_prince_test.1007768162
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/239.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/24.prim_prince_test.2699595199
Short name T8
Test name
Test status
Simulation time 1107787590 ps
CPU time 21.89 seconds
Started Oct 11 11:35:56 PM UTC 24
Finished Oct 11 11:36:25 PM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2699595199 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 24.prim_prince_test.2699595199
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/24.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/240.prim_prince_test.86200047
Short name T274
Test name
Test status
Simulation time 3566588939 ps
CPU time 65.61 seconds
Started Oct 11 11:40:10 PM UTC 24
Finished Oct 11 11:41:34 PM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=86200047 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 240.prim_prince_test.86200047
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/240.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/241.prim_prince_test.775854502
Short name T249
Test name
Test status
Simulation time 2373940527 ps
CPU time 44.87 seconds
Started Oct 11 11:40:10 PM UTC 24
Finished Oct 11 11:41:07 PM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=775854502 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 241.prim_prince_test.775854502
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/241.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/242.prim_prince_test.1617947794
Short name T213
Test name
Test status
Simulation time 836080065 ps
CPU time 16.1 seconds
Started Oct 11 11:40:10 PM UTC 24
Finished Oct 11 11:40:31 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1617947794 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 242.prim_prince_test.1617947794
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/242.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/243.prim_prince_test.2034873739
Short name T217
Test name
Test status
Simulation time 1179552598 ps
CPU time 21.96 seconds
Started Oct 11 11:40:10 PM UTC 24
Finished Oct 11 11:40:39 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2034873739 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 243.prim_prince_test.2034873739
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/243.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/244.prim_prince_test.1757775506
Short name T278
Test name
Test status
Simulation time 3680154112 ps
CPU time 67.35 seconds
Started Oct 11 11:40:12 PM UTC 24
Finished Oct 11 11:41:37 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1757775506 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 244.prim_prince_test.1757775506
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/244.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/245.prim_prince_test.1623753215
Short name T262
Test name
Test status
Simulation time 2968970540 ps
CPU time 55.32 seconds
Started Oct 11 11:40:12 PM UTC 24
Finished Oct 11 11:41:22 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1623753215 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 245.prim_prince_test.1623753215
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/245.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/246.prim_prince_test.631938020
Short name T224
Test name
Test status
Simulation time 1309964363 ps
CPU time 25.2 seconds
Started Oct 11 11:40:13 PM UTC 24
Finished Oct 11 11:40:45 PM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=631938020 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 246.prim_prince_test.631938020
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/246.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/247.prim_prince_test.2366229047
Short name T251
Test name
Test status
Simulation time 2383741310 ps
CPU time 45.12 seconds
Started Oct 11 11:40:13 PM UTC 24
Finished Oct 11 11:41:10 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2366229047 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 247.prim_prince_test.2366229047
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/247.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/248.prim_prince_test.2327173254
Short name T256
Test name
Test status
Simulation time 2299167128 ps
CPU time 43.75 seconds
Started Oct 11 11:40:17 PM UTC 24
Finished Oct 11 11:41:12 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2327173254 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 248.prim_prince_test.2327173254
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/248.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/249.prim_prince_test.4172272145
Short name T258
Test name
Test status
Simulation time 2382320621 ps
CPU time 44.72 seconds
Started Oct 11 11:40:18 PM UTC 24
Finished Oct 11 11:41:15 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4172272145 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 249.prim_prince_test.4172272145
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/249.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/25.prim_prince_test.1585260101
Short name T14
Test name
Test status
Simulation time 1288744158 ps
CPU time 25.08 seconds
Started Oct 11 11:35:56 PM UTC 24
Finished Oct 11 11:36:29 PM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1585260101 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 25.prim_prince_test.1585260101
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/25.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/250.prim_prince_test.3145178167
Short name T268
Test name
Test status
Simulation time 2959454310 ps
CPU time 54.47 seconds
Started Oct 11 11:40:19 PM UTC 24
Finished Oct 11 11:41:29 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3145178167 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 250.prim_prince_test.3145178167
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/250.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/251.prim_prince_test.2913130496
Short name T245
Test name
Test status
Simulation time 1906374725 ps
CPU time 35.98 seconds
Started Oct 11 11:40:20 PM UTC 24
Finished Oct 11 11:41:05 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2913130496 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 251.prim_prince_test.2913130496
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/251.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/252.prim_prince_test.1875614887
Short name T281
Test name
Test status
Simulation time 3389160649 ps
CPU time 63.02 seconds
Started Oct 11 11:40:21 PM UTC 24
Finished Oct 11 11:41:41 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1875614887 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 252.prim_prince_test.1875614887
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/252.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/253.prim_prince_test.199199767
Short name T231
Test name
Test status
Simulation time 1372805671 ps
CPU time 25.68 seconds
Started Oct 11 11:40:21 PM UTC 24
Finished Oct 11 11:40:54 PM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=199199767 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 253.prim_prince_test.199199767
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/253.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/254.prim_prince_test.2708815845
Short name T247
Test name
Test status
Simulation time 2024939782 ps
CPU time 37.24 seconds
Started Oct 11 11:40:22 PM UTC 24
Finished Oct 11 11:41:10 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2708815845 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 254.prim_prince_test.2708815845
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/254.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/255.prim_prince_test.1989630341
Short name T253
Test name
Test status
Simulation time 2050108735 ps
CPU time 38.3 seconds
Started Oct 11 11:40:22 PM UTC 24
Finished Oct 11 11:41:11 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1989630341 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 255.prim_prince_test.1989630341
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/255.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/256.prim_prince_test.757368429
Short name T232
Test name
Test status
Simulation time 1236076542 ps
CPU time 23.65 seconds
Started Oct 11 11:40:23 PM UTC 24
Finished Oct 11 11:40:54 PM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=757368429 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 256.prim_prince_test.757368429
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/256.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/257.prim_prince_test.2120014424
Short name T273
Test name
Test status
Simulation time 2941227057 ps
CPU time 54.07 seconds
Started Oct 11 11:40:23 PM UTC 24
Finished Oct 11 11:41:32 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2120014424 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 257.prim_prince_test.2120014424
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/257.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/258.prim_prince_test.1844761474
Short name T240
Test name
Test status
Simulation time 1525198497 ps
CPU time 29.26 seconds
Started Oct 11 11:40:24 PM UTC 24
Finished Oct 11 11:41:01 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1844761474 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 258.prim_prince_test.1844761474
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/258.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/259.prim_prince_test.264690745
Short name T263
Test name
Test status
Simulation time 2434133426 ps
CPU time 46.03 seconds
Started Oct 11 11:40:24 PM UTC 24
Finished Oct 11 11:41:22 PM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=264690745 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 259.prim_prince_test.264690745
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/259.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/26.prim_prince_test.3837173870
Short name T10
Test name
Test status
Simulation time 1166546754 ps
CPU time 23.12 seconds
Started Oct 11 11:35:56 PM UTC 24
Finished Oct 11 11:36:26 PM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3837173870 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 26.prim_prince_test.3837173870
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/26.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/260.prim_prince_test.2958493154
Short name T194
Test name
Test status
Simulation time 1834764143 ps
CPU time 34.16 seconds
Started Oct 11 11:40:26 PM UTC 24
Finished Oct 11 11:41:10 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2958493154 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 260.prim_prince_test.2958493154
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/260.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/261.prim_prince_test.1641804397
Short name T280
Test name
Test status
Simulation time 3128380909 ps
CPU time 59.2 seconds
Started Oct 11 11:40:26 PM UTC 24
Finished Oct 11 11:41:41 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1641804397 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 261.prim_prince_test.1641804397
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/261.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/262.prim_prince_test.3227034966
Short name T243
Test name
Test status
Simulation time 1562559817 ps
CPU time 29.23 seconds
Started Oct 11 11:40:27 PM UTC 24
Finished Oct 11 11:41:05 PM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3227034966 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 262.prim_prince_test.3227034966
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/262.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/263.prim_prince_test.53312773
Short name T236
Test name
Test status
Simulation time 1087909657 ps
CPU time 20.56 seconds
Started Oct 11 11:40:29 PM UTC 24
Finished Oct 11 11:40:56 PM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=53312773 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 263.prim_prince_test.53312773
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/263.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/264.prim_prince_test.1583460424
Short name T282
Test name
Test status
Simulation time 2993746098 ps
CPU time 56.21 seconds
Started Oct 11 11:40:30 PM UTC 24
Finished Oct 11 11:41:41 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1583460424 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 264.prim_prince_test.1583460424
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/264.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/265.prim_prince_test.1016893994
Short name T238
Test name
Test status
Simulation time 1000507355 ps
CPU time 19.07 seconds
Started Oct 11 11:40:31 PM UTC 24
Finished Oct 11 11:40:56 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1016893994 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 265.prim_prince_test.1016893994
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/265.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/266.prim_prince_test.1115754008
Short name T237
Test name
Test status
Simulation time 945457858 ps
CPU time 18.14 seconds
Started Oct 11 11:40:32 PM UTC 24
Finished Oct 11 11:40:56 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1115754008 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 266.prim_prince_test.1115754008
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/266.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/267.prim_prince_test.3249226695
Short name T298
Test name
Test status
Simulation time 3295855846 ps
CPU time 60.16 seconds
Started Oct 11 11:40:37 PM UTC 24
Finished Oct 11 11:41:53 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3249226695 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 267.prim_prince_test.3249226695
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/267.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/268.prim_prince_test.2529515778
Short name T287
Test name
Test status
Simulation time 2879037316 ps
CPU time 54.36 seconds
Started Oct 11 11:40:38 PM UTC 24
Finished Oct 11 11:41:46 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2529515778 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 268.prim_prince_test.2529515778
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/268.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/269.prim_prince_test.307344136
Short name T301
Test name
Test status
Simulation time 3270854335 ps
CPU time 59.33 seconds
Started Oct 11 11:40:39 PM UTC 24
Finished Oct 11 11:41:54 PM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=307344136 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 269.prim_prince_test.307344136
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/269.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/27.prim_prince_test.350539794
Short name T24
Test name
Test status
Simulation time 1781426442 ps
CPU time 33.7 seconds
Started Oct 11 11:35:56 PM UTC 24
Finished Oct 11 11:36:40 PM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=350539794 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 27.prim_prince_test.350539794
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/27.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/270.prim_prince_test.4005344592
Short name T241
Test name
Test status
Simulation time 876684931 ps
CPU time 16.92 seconds
Started Oct 11 11:40:40 PM UTC 24
Finished Oct 11 11:41:02 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4005344592 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 270.prim_prince_test.4005344592
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/270.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/271.prim_prince_test.3726036713
Short name T265
Test name
Test status
Simulation time 1798999344 ps
CPU time 34.07 seconds
Started Oct 11 11:40:40 PM UTC 24
Finished Oct 11 11:41:23 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3726036713 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 271.prim_prince_test.3726036713
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/271.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/272.prim_prince_test.2180514025
Short name T284
Test name
Test status
Simulation time 2697737258 ps
CPU time 49.48 seconds
Started Oct 11 11:40:41 PM UTC 24
Finished Oct 11 11:41:44 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2180514025 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 272.prim_prince_test.2180514025
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/272.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/273.prim_prince_test.94209026
Short name T260
Test name
Test status
Simulation time 1510949347 ps
CPU time 27.96 seconds
Started Oct 11 11:40:41 PM UTC 24
Finished Oct 11 11:41:17 PM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=94209026 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 273.prim_prince_test.94209026
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/273.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/274.prim_prince_test.938580962
Short name T311
Test name
Test status
Simulation time 3698951784 ps
CPU time 67.56 seconds
Started Oct 11 11:40:42 PM UTC 24
Finished Oct 11 11:42:08 PM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=938580962 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 274.prim_prince_test.938580962
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/274.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/275.prim_prince_test.3856602522
Short name T291
Test name
Test status
Simulation time 2793176196 ps
CPU time 51.5 seconds
Started Oct 11 11:40:44 PM UTC 24
Finished Oct 11 11:41:49 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3856602522 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 275.prim_prince_test.3856602522
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/275.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/276.prim_prince_test.179946587
Short name T289
Test name
Test status
Simulation time 2672088508 ps
CPU time 50.37 seconds
Started Oct 11 11:40:44 PM UTC 24
Finished Oct 11 11:41:47 PM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=179946587 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 276.prim_prince_test.179946587
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/276.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/277.prim_prince_test.662974444
Short name T302
Test name
Test status
Simulation time 3037515287 ps
CPU time 55.58 seconds
Started Oct 11 11:40:45 PM UTC 24
Finished Oct 11 11:41:56 PM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=662974444 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 277.prim_prince_test.662974444
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/277.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/278.prim_prince_test.2783599048
Short name T306
Test name
Test status
Simulation time 3369669896 ps
CPU time 61.07 seconds
Started Oct 11 11:40:46 PM UTC 24
Finished Oct 11 11:42:04 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2783599048 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 278.prim_prince_test.2783599048
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/278.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/279.prim_prince_test.3045468074
Short name T259
Test name
Test status
Simulation time 1125999931 ps
CPU time 21.63 seconds
Started Oct 11 11:40:47 PM UTC 24
Finished Oct 11 11:41:15 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3045468074 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 279.prim_prince_test.3045468074
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/279.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/28.prim_prince_test.4032690807
Short name T41
Test name
Test status
Simulation time 3075603375 ps
CPU time 58.52 seconds
Started Oct 11 11:35:56 PM UTC 24
Finished Oct 11 11:37:11 PM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4032690807 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 28.prim_prince_test.4032690807
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/28.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/280.prim_prince_test.3472155917
Short name T296
Test name
Test status
Simulation time 2501956702 ps
CPU time 46.64 seconds
Started Oct 11 11:40:52 PM UTC 24
Finished Oct 11 11:41:51 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3472155917 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 280.prim_prince_test.3472155917
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/280.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/281.prim_prince_test.156948566
Short name T300
Test name
Test status
Simulation time 2604043725 ps
CPU time 48.06 seconds
Started Oct 11 11:40:52 PM UTC 24
Finished Oct 11 11:41:54 PM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=156948566 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 281.prim_prince_test.156948566
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/281.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/282.prim_prince_test.2791939373
Short name T295
Test name
Test status
Simulation time 2425789190 ps
CPU time 45.58 seconds
Started Oct 11 11:40:54 PM UTC 24
Finished Oct 11 11:41:51 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2791939373 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 282.prim_prince_test.2791939373
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/282.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/283.prim_prince_test.2315418031
Short name T288
Test name
Test status
Simulation time 2242585044 ps
CPU time 42 seconds
Started Oct 11 11:40:54 PM UTC 24
Finished Oct 11 11:41:47 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2315418031 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 283.prim_prince_test.2315418031
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/283.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/284.prim_prince_test.212478374
Short name T266
Test name
Test status
Simulation time 1386262058 ps
CPU time 26.21 seconds
Started Oct 11 11:40:54 PM UTC 24
Finished Oct 11 11:41:27 PM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=212478374 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 284.prim_prince_test.212478374
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/284.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/285.prim_prince_test.1487343559
Short name T264
Test name
Test status
Simulation time 1110063652 ps
CPU time 21.1 seconds
Started Oct 11 11:40:55 PM UTC 24
Finished Oct 11 11:41:22 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1487343559 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 285.prim_prince_test.1487343559
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/285.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/286.prim_prince_test.3510396221
Short name T310
Test name
Test status
Simulation time 3084020939 ps
CPU time 57.98 seconds
Started Oct 11 11:40:55 PM UTC 24
Finished Oct 11 11:42:08 PM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3510396221 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 286.prim_prince_test.3510396221
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/286.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/287.prim_prince_test.2513695679
Short name T299
Test name
Test status
Simulation time 2437178921 ps
CPU time 44.6 seconds
Started Oct 11 11:40:56 PM UTC 24
Finished Oct 11 11:41:54 PM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2513695679 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 287.prim_prince_test.2513695679
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/287.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/288.prim_prince_test.1365698829
Short name T269
Test name
Test status
Simulation time 1395519121 ps
CPU time 26.06 seconds
Started Oct 11 11:40:56 PM UTC 24
Finished Oct 11 11:41:30 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1365698829 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 288.prim_prince_test.1365698829
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/288.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/289.prim_prince_test.308493618
Short name T267
Test name
Test status
Simulation time 1277272960 ps
CPU time 24.32 seconds
Started Oct 11 11:40:57 PM UTC 24
Finished Oct 11 11:41:28 PM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=308493618 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 289.prim_prince_test.308493618
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/289.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/29.prim_prince_test.2436858334
Short name T42
Test name
Test status
Simulation time 3065436638 ps
CPU time 59.4 seconds
Started Oct 11 11:35:56 PM UTC 24
Finished Oct 11 11:37:12 PM UTC 24
Peak memory 155008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2436858334 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 29.prim_prince_test.2436858334
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/29.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/290.prim_prince_test.792898588
Short name T305
Test name
Test status
Simulation time 2849314058 ps
CPU time 53.34 seconds
Started Oct 11 11:40:57 PM UTC 24
Finished Oct 11 11:42:04 PM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=792898588 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 290.prim_prince_test.792898588
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/290.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/291.prim_prince_test.3860078541
Short name T279
Test name
Test status
Simulation time 1698981922 ps
CPU time 32.16 seconds
Started Oct 11 11:40:58 PM UTC 24
Finished Oct 11 11:41:39 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3860078541 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 291.prim_prince_test.3860078541
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/291.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/292.prim_prince_test.4228918931
Short name T283
Test name
Test status
Simulation time 1914732873 ps
CPU time 35.18 seconds
Started Oct 11 11:40:58 PM UTC 24
Finished Oct 11 11:41:43 PM UTC 24
Peak memory 154952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4228918931 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 292.prim_prince_test.4228918931
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/292.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/293.prim_prince_test.3781836693
Short name T290
Test name
Test status
Simulation time 2064366039 ps
CPU time 38.95 seconds
Started Oct 11 11:40:58 PM UTC 24
Finished Oct 11 11:41:48 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3781836693 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 293.prim_prince_test.3781836693
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/293.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/294.prim_prince_test.1311425001
Short name T271
Test name
Test status
Simulation time 1360938947 ps
CPU time 25.99 seconds
Started Oct 11 11:40:59 PM UTC 24
Finished Oct 11 11:41:32 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1311425001 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 294.prim_prince_test.1311425001
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/294.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/295.prim_prince_test.2185050936
Short name T277
Test name
Test status
Simulation time 1431969913 ps
CPU time 26.94 seconds
Started Oct 11 11:41:02 PM UTC 24
Finished Oct 11 11:41:37 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2185050936 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 295.prim_prince_test.2185050936
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/295.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/296.prim_prince_test.2088950698
Short name T314
Test name
Test status
Simulation time 2832326639 ps
CPU time 52.93 seconds
Started Oct 11 11:41:03 PM UTC 24
Finished Oct 11 11:42:10 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2088950698 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 296.prim_prince_test.2088950698
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/296.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/297.prim_prince_test.2068189659
Short name T308
Test name
Test status
Simulation time 2507307602 ps
CPU time 46.96 seconds
Started Oct 11 11:41:06 PM UTC 24
Finished Oct 11 11:42:05 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2068189659 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 297.prim_prince_test.2068189659
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/297.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/298.prim_prince_test.2151312946
Short name T315
Test name
Test status
Simulation time 2826937467 ps
CPU time 51.91 seconds
Started Oct 11 11:41:06 PM UTC 24
Finished Oct 11 11:42:12 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2151312946 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 298.prim_prince_test.2151312946
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/298.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/299.prim_prince_test.120105890
Short name T286
Test name
Test status
Simulation time 1651607202 ps
CPU time 31.54 seconds
Started Oct 11 11:41:06 PM UTC 24
Finished Oct 11 11:41:46 PM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=120105890 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 299.prim_prince_test.120105890
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/299.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/3.prim_prince_test.426348831
Short name T7
Test name
Test status
Simulation time 1332880695 ps
CPU time 25.69 seconds
Started Oct 11 11:35:47 PM UTC 24
Finished Oct 11 11:36:21 PM UTC 24
Peak memory 154984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=426348831 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 3.prim_prince_test.426348831
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/3.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/30.prim_prince_test.415237299
Short name T31
Test name
Test status
Simulation time 2473015124 ps
CPU time 48.43 seconds
Started Oct 11 11:35:56 PM UTC 24
Finished Oct 11 11:36:58 PM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=415237299 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 30.prim_prince_test.415237299
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/30.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/300.prim_prince_test.3559462341
Short name T270
Test name
Test status
Simulation time 1000900753 ps
CPU time 19.13 seconds
Started Oct 11 11:41:07 PM UTC 24
Finished Oct 11 11:41:32 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3559462341 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 300.prim_prince_test.3559462341
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/300.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/301.prim_prince_test.1249567088
Short name T324
Test name
Test status
Simulation time 3223700814 ps
CPU time 58.99 seconds
Started Oct 11 11:41:07 PM UTC 24
Finished Oct 11 11:42:22 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1249567088 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 301.prim_prince_test.1249567088
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/301.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/302.prim_prince_test.582523721
Short name T303
Test name
Test status
Simulation time 1998450310 ps
CPU time 37.58 seconds
Started Oct 11 11:41:08 PM UTC 24
Finished Oct 11 11:41:56 PM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=582523721 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 302.prim_prince_test.582523721
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/302.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/303.prim_prince_test.820121590
Short name T317
Test name
Test status
Simulation time 2833721688 ps
CPU time 53.12 seconds
Started Oct 11 11:41:08 PM UTC 24
Finished Oct 11 11:42:15 PM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=820121590 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 303.prim_prince_test.820121590
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/303.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/304.prim_prince_test.3533113421
Short name T325
Test name
Test status
Simulation time 3171198840 ps
CPU time 59.08 seconds
Started Oct 11 11:41:08 PM UTC 24
Finished Oct 11 11:42:23 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3533113421 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 304.prim_prince_test.3533113421
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/304.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/305.prim_prince_test.781253042
Short name T334
Test name
Test status
Simulation time 3364537951 ps
CPU time 62.8 seconds
Started Oct 11 11:41:10 PM UTC 24
Finished Oct 11 11:42:29 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=781253042 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 305.prim_prince_test.781253042
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/305.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/306.prim_prince_test.333733740
Short name T313
Test name
Test status
Simulation time 2509150755 ps
CPU time 45.71 seconds
Started Oct 11 11:41:12 PM UTC 24
Finished Oct 11 11:42:10 PM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=333733740 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 306.prim_prince_test.333733740
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/306.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/307.prim_prince_test.897656725
Short name T272
Test name
Test status
Simulation time 830391886 ps
CPU time 16.02 seconds
Started Oct 11 11:41:12 PM UTC 24
Finished Oct 11 11:41:32 PM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=897656725 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 307.prim_prince_test.897656725
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/307.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/308.prim_prince_test.1931606165
Short name T276
Test name
Test status
Simulation time 932037834 ps
CPU time 18.01 seconds
Started Oct 11 11:41:12 PM UTC 24
Finished Oct 11 11:41:35 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1931606165 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 308.prim_prince_test.1931606165
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/308.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/309.prim_prince_test.2406871144
Short name T293
Test name
Test status
Simulation time 1601425107 ps
CPU time 29.97 seconds
Started Oct 11 11:41:12 PM UTC 24
Finished Oct 11 11:41:50 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2406871144 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 309.prim_prince_test.2406871144
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/309.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/31.prim_prince_test.1095261033
Short name T19
Test name
Test status
Simulation time 1629689629 ps
CPU time 30.86 seconds
Started Oct 11 11:35:56 PM UTC 24
Finished Oct 11 11:36:37 PM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1095261033 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 31.prim_prince_test.1095261033
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/31.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/310.prim_prince_test.1503931807
Short name T322
Test name
Test status
Simulation time 2904947093 ps
CPU time 53.65 seconds
Started Oct 11 11:41:13 PM UTC 24
Finished Oct 11 11:42:21 PM UTC 24
Peak memory 155008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1503931807 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 310.prim_prince_test.1503931807
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/310.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/311.prim_prince_test.3258156994
Short name T319
Test name
Test status
Simulation time 2832793529 ps
CPU time 51.78 seconds
Started Oct 11 11:41:13 PM UTC 24
Finished Oct 11 11:42:19 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3258156994 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 311.prim_prince_test.3258156994
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/311.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/312.prim_prince_test.1367746358
Short name T320
Test name
Test status
Simulation time 2867626839 ps
CPU time 53.71 seconds
Started Oct 11 11:41:13 PM UTC 24
Finished Oct 11 11:42:21 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1367746358 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 312.prim_prince_test.1367746358
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/312.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/313.prim_prince_test.2745520703
Short name T285
Test name
Test status
Simulation time 1235180128 ps
CPU time 23.29 seconds
Started Oct 11 11:41:14 PM UTC 24
Finished Oct 11 11:41:44 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2745520703 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 313.prim_prince_test.2745520703
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/313.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/314.prim_prince_test.4134053370
Short name T321
Test name
Test status
Simulation time 2800091614 ps
CPU time 51.55 seconds
Started Oct 11 11:41:15 PM UTC 24
Finished Oct 11 11:42:21 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4134053370 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 314.prim_prince_test.4134053370
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/314.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/315.prim_prince_test.3476542318
Short name T275
Test name
Test status
Simulation time 757341597 ps
CPU time 14.62 seconds
Started Oct 11 11:41:16 PM UTC 24
Finished Oct 11 11:41:35 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3476542318 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 315.prim_prince_test.3476542318
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/315.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/316.prim_prince_test.2303002547
Short name T344
Test name
Test status
Simulation time 3417247592 ps
CPU time 62.77 seconds
Started Oct 11 11:41:18 PM UTC 24
Finished Oct 11 11:42:37 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2303002547 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 316.prim_prince_test.2303002547
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/316.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/317.prim_prince_test.59090249
Short name T297
Test name
Test status
Simulation time 1400105689 ps
CPU time 26.44 seconds
Started Oct 11 11:41:19 PM UTC 24
Finished Oct 11 11:41:53 PM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=59090249 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 317.prim_prince_test.59090249
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/317.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/318.prim_prince_test.2654349397
Short name T337
Test name
Test status
Simulation time 2790953167 ps
CPU time 52.05 seconds
Started Oct 11 11:41:23 PM UTC 24
Finished Oct 11 11:42:30 PM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2654349397 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 318.prim_prince_test.2654349397
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/318.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/319.prim_prince_test.1780802308
Short name T347
Test name
Test status
Simulation time 3253569591 ps
CPU time 60.17 seconds
Started Oct 11 11:41:23 PM UTC 24
Finished Oct 11 11:42:40 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1780802308 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 319.prim_prince_test.1780802308
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/319.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/32.prim_prince_test.3615984656
Short name T11
Test name
Test status
Simulation time 1147752921 ps
CPU time 22.48 seconds
Started Oct 11 11:35:57 PM UTC 24
Finished Oct 11 11:36:27 PM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3615984656 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 32.prim_prince_test.3615984656
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/32.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/320.prim_prince_test.4045064483
Short name T328
Test name
Test status
Simulation time 2633525497 ps
CPU time 48.36 seconds
Started Oct 11 11:41:23 PM UTC 24
Finished Oct 11 11:42:25 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4045064483 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 320.prim_prince_test.4045064483
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/320.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/321.prim_prince_test.1560390913
Short name T294
Test name
Test status
Simulation time 1061149067 ps
CPU time 19.76 seconds
Started Oct 11 11:41:24 PM UTC 24
Finished Oct 11 11:41:51 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1560390913 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 321.prim_prince_test.1560390913
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/321.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/322.prim_prince_test.675891346
Short name T292
Test name
Test status
Simulation time 873469141 ps
CPU time 16.59 seconds
Started Oct 11 11:41:29 PM UTC 24
Finished Oct 11 11:41:50 PM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=675891346 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 322.prim_prince_test.675891346
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/322.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/323.prim_prince_test.3893313567
Short name T312
Test name
Test status
Simulation time 1725155771 ps
CPU time 32.41 seconds
Started Oct 11 11:41:29 PM UTC 24
Finished Oct 11 11:42:10 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3893313567 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 323.prim_prince_test.3893313567
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/323.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/324.prim_prince_test.2791977912
Short name T327
Test name
Test status
Simulation time 2276138976 ps
CPU time 42.83 seconds
Started Oct 11 11:41:30 PM UTC 24
Finished Oct 11 11:42:24 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2791977912 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 324.prim_prince_test.2791977912
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/324.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/325.prim_prince_test.580780261
Short name T307
Test name
Test status
Simulation time 1396939903 ps
CPU time 25.8 seconds
Started Oct 11 11:41:31 PM UTC 24
Finished Oct 11 11:42:04 PM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=580780261 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 325.prim_prince_test.580780261
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/325.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/326.prim_prince_test.4139812543
Short name T304
Test name
Test status
Simulation time 1012790284 ps
CPU time 19.24 seconds
Started Oct 11 11:41:32 PM UTC 24
Finished Oct 11 11:41:57 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4139812543 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 326.prim_prince_test.4139812543
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/326.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/327.prim_prince_test.4278056331
Short name T345
Test name
Test status
Simulation time 2788753170 ps
CPU time 51.52 seconds
Started Oct 11 11:41:33 PM UTC 24
Finished Oct 11 11:42:39 PM UTC 24
Peak memory 155032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4278056331 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 327.prim_prince_test.4278056331
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/327.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/328.prim_prince_test.328618093
Short name T346
Test name
Test status
Simulation time 2833640408 ps
CPU time 51.91 seconds
Started Oct 11 11:41:33 PM UTC 24
Finished Oct 11 11:42:40 PM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=328618093 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 328.prim_prince_test.328618093
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/328.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/329.prim_prince_test.2095511009
Short name T354
Test name
Test status
Simulation time 3221092631 ps
CPU time 58.48 seconds
Started Oct 11 11:41:33 PM UTC 24
Finished Oct 11 11:42:48 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2095511009 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 329.prim_prince_test.2095511009
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/329.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/33.prim_prince_test.1430070210
Short name T12
Test name
Test status
Simulation time 1129052047 ps
CPU time 22.31 seconds
Started Oct 11 11:35:59 PM UTC 24
Finished Oct 11 11:36:28 PM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1430070210 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 33.prim_prince_test.1430070210
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/33.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/330.prim_prince_test.3958104727
Short name T366
Test name
Test status
Simulation time 3469822604 ps
CPU time 64.93 seconds
Started Oct 11 11:41:34 PM UTC 24
Finished Oct 11 11:42:56 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3958104727 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 330.prim_prince_test.3958104727
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/330.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/331.prim_prince_test.1643897603
Short name T372
Test name
Test status
Simulation time 3626722283 ps
CPU time 65.85 seconds
Started Oct 11 11:41:36 PM UTC 24
Finished Oct 11 11:43:00 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1643897603 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 331.prim_prince_test.1643897603
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/331.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/332.prim_prince_test.2888021695
Short name T330
Test name
Test status
Simulation time 2151605961 ps
CPU time 39.44 seconds
Started Oct 11 11:41:36 PM UTC 24
Finished Oct 11 11:42:26 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2888021695 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 332.prim_prince_test.2888021695
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/332.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/333.prim_prince_test.2213228618
Short name T363
Test name
Test status
Simulation time 3203137529 ps
CPU time 59.27 seconds
Started Oct 11 11:41:38 PM UTC 24
Finished Oct 11 11:42:53 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2213228618 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 333.prim_prince_test.2213228618
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/333.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/334.prim_prince_test.108383387
Short name T374
Test name
Test status
Simulation time 3688818744 ps
CPU time 68.94 seconds
Started Oct 11 11:41:38 PM UTC 24
Finished Oct 11 11:43:05 PM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=108383387 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 334.prim_prince_test.108383387
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/334.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/335.prim_prince_test.2011101013
Short name T335
Test name
Test status
Simulation time 2065561135 ps
CPU time 38.01 seconds
Started Oct 11 11:41:40 PM UTC 24
Finished Oct 11 11:42:30 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2011101013 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 335.prim_prince_test.2011101013
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/335.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/336.prim_prince_test.1574064392
Short name T336
Test name
Test status
Simulation time 2058922958 ps
CPU time 38.28 seconds
Started Oct 11 11:41:40 PM UTC 24
Finished Oct 11 11:42:30 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1574064392 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 336.prim_prince_test.1574064392
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/336.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/337.prim_prince_test.4185149174
Short name T371
Test name
Test status
Simulation time 3288059816 ps
CPU time 61.25 seconds
Started Oct 11 11:41:42 PM UTC 24
Finished Oct 11 11:42:59 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4185149174 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 337.prim_prince_test.4185149174
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/337.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/338.prim_prince_test.1418757159
Short name T309
Test name
Test status
Simulation time 1051289118 ps
CPU time 19.99 seconds
Started Oct 11 11:41:42 PM UTC 24
Finished Oct 11 11:42:08 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1418757159 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 338.prim_prince_test.1418757159
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/338.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/339.prim_prince_test.2290140869
Short name T369
Test name
Test status
Simulation time 3209840027 ps
CPU time 59.87 seconds
Started Oct 11 11:41:42 PM UTC 24
Finished Oct 11 11:42:58 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2290140869 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 339.prim_prince_test.2290140869
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/339.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/34.prim_prince_test.1264298151
Short name T46
Test name
Test status
Simulation time 3050383245 ps
CPU time 58.2 seconds
Started Oct 11 11:36:01 PM UTC 24
Finished Oct 11 11:37:16 PM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1264298151 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 34.prim_prince_test.1264298151
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/34.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/340.prim_prince_test.3781073461
Short name T326
Test name
Test status
Simulation time 1630717435 ps
CPU time 30.36 seconds
Started Oct 11 11:41:44 PM UTC 24
Finished Oct 11 11:42:23 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3781073461 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 340.prim_prince_test.3781073461
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/340.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/341.prim_prince_test.1925547751
Short name T378
Test name
Test status
Simulation time 3563660116 ps
CPU time 66.68 seconds
Started Oct 11 11:41:45 PM UTC 24
Finished Oct 11 11:43:09 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1925547751 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 341.prim_prince_test.1925547751
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/341.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/342.prim_prince_test.2582742752
Short name T343
Test name
Test status
Simulation time 2165475004 ps
CPU time 40.06 seconds
Started Oct 11 11:41:45 PM UTC 24
Finished Oct 11 11:42:37 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2582742752 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 342.prim_prince_test.2582742752
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/342.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/343.prim_prince_test.748727759
Short name T316
Test name
Test status
Simulation time 1142741351 ps
CPU time 21.55 seconds
Started Oct 11 11:41:46 PM UTC 24
Finished Oct 11 11:42:14 PM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=748727759 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 343.prim_prince_test.748727759
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/343.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/344.prim_prince_test.129691037
Short name T375
Test name
Test status
Simulation time 3398354082 ps
CPU time 61.23 seconds
Started Oct 11 11:41:48 PM UTC 24
Finished Oct 11 11:43:06 PM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=129691037 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 344.prim_prince_test.129691037
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/344.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/345.prim_prince_test.70355889
Short name T331
Test name
Test status
Simulation time 1617417369 ps
CPU time 30.51 seconds
Started Oct 11 11:41:48 PM UTC 24
Finished Oct 11 11:42:27 PM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=70355889 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 345.prim_prince_test.70355889
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/345.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/346.prim_prince_test.4198085534
Short name T341
Test name
Test status
Simulation time 1970523301 ps
CPU time 36.2 seconds
Started Oct 11 11:41:49 PM UTC 24
Finished Oct 11 11:42:35 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4198085534 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 346.prim_prince_test.4198085534
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/346.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/347.prim_prince_test.764333454
Short name T357
Test name
Test status
Simulation time 2560239460 ps
CPU time 48.05 seconds
Started Oct 11 11:41:49 PM UTC 24
Finished Oct 11 11:42:50 PM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=764333454 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 347.prim_prince_test.764333454
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/347.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/348.prim_prince_test.2143059458
Short name T339
Test name
Test status
Simulation time 1671425362 ps
CPU time 31.67 seconds
Started Oct 11 11:41:50 PM UTC 24
Finished Oct 11 11:42:30 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2143059458 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 348.prim_prince_test.2143059458
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/348.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/349.prim_prince_test.3811472134
Short name T329
Test name
Test status
Simulation time 1443827442 ps
CPU time 27.01 seconds
Started Oct 11 11:41:51 PM UTC 24
Finished Oct 11 11:42:26 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3811472134 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 349.prim_prince_test.3811472134
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/349.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/35.prim_prince_test.2966188207
Short name T36
Test name
Test status
Simulation time 2197134246 ps
CPU time 43.24 seconds
Started Oct 11 11:36:09 PM UTC 24
Finished Oct 11 11:37:05 PM UTC 24
Peak memory 156396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2966188207 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 35.prim_prince_test.2966188207
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/35.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/350.prim_prince_test.3561946355
Short name T323
Test name
Test status
Simulation time 1257168692 ps
CPU time 23.33 seconds
Started Oct 11 11:41:51 PM UTC 24
Finished Oct 11 11:42:22 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3561946355 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 350.prim_prince_test.3561946355
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/350.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/351.prim_prince_test.1395129025
Short name T332
Test name
Test status
Simulation time 1541624041 ps
CPU time 28.36 seconds
Started Oct 11 11:41:52 PM UTC 24
Finished Oct 11 11:42:28 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1395129025 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 351.prim_prince_test.1395129025
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/351.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/352.prim_prince_test.3973656731
Short name T318
Test name
Test status
Simulation time 919641852 ps
CPU time 17.16 seconds
Started Oct 11 11:41:53 PM UTC 24
Finished Oct 11 11:42:15 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3973656731 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 352.prim_prince_test.3973656731
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/352.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/353.prim_prince_test.143012394
Short name T342
Test name
Test status
Simulation time 1823154595 ps
CPU time 33.4 seconds
Started Oct 11 11:41:53 PM UTC 24
Finished Oct 11 11:42:36 PM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=143012394 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 353.prim_prince_test.143012394
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/353.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/354.prim_prince_test.2548806073
Short name T333
Test name
Test status
Simulation time 1412870913 ps
CPU time 26.82 seconds
Started Oct 11 11:41:54 PM UTC 24
Finished Oct 11 11:42:29 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2548806073 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 354.prim_prince_test.2548806073
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/354.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/355.prim_prince_test.480131748
Short name T338
Test name
Test status
Simulation time 1498170024 ps
CPU time 28.08 seconds
Started Oct 11 11:41:54 PM UTC 24
Finished Oct 11 11:42:30 PM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=480131748 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 355.prim_prince_test.480131748
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/355.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/356.prim_prince_test.2342887568
Short name T377
Test name
Test status
Simulation time 3188106890 ps
CPU time 59.03 seconds
Started Oct 11 11:41:54 PM UTC 24
Finished Oct 11 11:43:09 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2342887568 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 356.prim_prince_test.2342887568
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/356.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/357.prim_prince_test.972808585
Short name T350
Test name
Test status
Simulation time 2010365266 ps
CPU time 37.66 seconds
Started Oct 11 11:41:55 PM UTC 24
Finished Oct 11 11:42:43 PM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=972808585 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 357.prim_prince_test.972808585
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/357.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/358.prim_prince_test.1020212211
Short name T356
Test name
Test status
Simulation time 2274299114 ps
CPU time 41.81 seconds
Started Oct 11 11:41:55 PM UTC 24
Finished Oct 11 11:42:49 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1020212211 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 358.prim_prince_test.1020212211
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/358.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/359.prim_prince_test.169652886
Short name T373
Test name
Test status
Simulation time 2706451505 ps
CPU time 50.71 seconds
Started Oct 11 11:41:57 PM UTC 24
Finished Oct 11 11:43:01 PM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=169652886 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 359.prim_prince_test.169652886
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/359.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/36.prim_prince_test.1154606678
Short name T63
Test name
Test status
Simulation time 3636167521 ps
CPU time 67.48 seconds
Started Oct 11 11:36:10 PM UTC 24
Finished Oct 11 11:37:38 PM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1154606678 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 36.prim_prince_test.1154606678
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/36.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/360.prim_prince_test.2837208498
Short name T385
Test name
Test status
Simulation time 3356471096 ps
CPU time 62.15 seconds
Started Oct 11 11:41:57 PM UTC 24
Finished Oct 11 11:43:15 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2837208498 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 360.prim_prince_test.2837208498
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/360.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/361.prim_prince_test.993851244
Short name T340
Test name
Test status
Simulation time 1489789062 ps
CPU time 27.2 seconds
Started Oct 11 11:41:58 PM UTC 24
Finished Oct 11 11:42:33 PM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=993851244 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 361.prim_prince_test.993851244
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/361.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/362.prim_prince_test.3399020508
Short name T381
Test name
Test status
Simulation time 2829588211 ps
CPU time 51.81 seconds
Started Oct 11 11:42:05 PM UTC 24
Finished Oct 11 11:43:11 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3399020508 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 362.prim_prince_test.3399020508
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/362.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/363.prim_prince_test.305451460
Short name T361
Test name
Test status
Simulation time 1950402300 ps
CPU time 36.89 seconds
Started Oct 11 11:42:05 PM UTC 24
Finished Oct 11 11:42:52 PM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=305451460 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 363.prim_prince_test.305451460
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/363.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/364.prim_prince_test.2995388707
Short name T352
Test name
Test status
Simulation time 1624632036 ps
CPU time 30.58 seconds
Started Oct 11 11:42:05 PM UTC 24
Finished Oct 11 11:42:44 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2995388707 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 364.prim_prince_test.2995388707
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/364.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/365.prim_prince_test.4178086106
Short name T355
Test name
Test status
Simulation time 1749573414 ps
CPU time 32.88 seconds
Started Oct 11 11:42:06 PM UTC 24
Finished Oct 11 11:42:48 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4178086106 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 365.prim_prince_test.4178086106
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/365.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/366.prim_prince_test.2152782974
Short name T406
Test name
Test status
Simulation time 3731329014 ps
CPU time 68.71 seconds
Started Oct 11 11:42:09 PM UTC 24
Finished Oct 11 11:43:35 PM UTC 24
Peak memory 154876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2152782974 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 366.prim_prince_test.2152782974
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/366.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/367.prim_prince_test.3827618260
Short name T407
Test name
Test status
Simulation time 3707221087 ps
CPU time 69.54 seconds
Started Oct 11 11:42:09 PM UTC 24
Finished Oct 11 11:43:36 PM UTC 24
Peak memory 154820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3827618260 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 367.prim_prince_test.3827618260
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/367.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/368.prim_prince_test.1764746775
Short name T389
Test name
Test status
Simulation time 2912149548 ps
CPU time 53.89 seconds
Started Oct 11 11:42:10 PM UTC 24
Finished Oct 11 11:43:18 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1764746775 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 368.prim_prince_test.1764746775
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/368.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/369.prim_prince_test.2322955878
Short name T359
Test name
Test status
Simulation time 1642328240 ps
CPU time 31.12 seconds
Started Oct 11 11:42:11 PM UTC 24
Finished Oct 11 11:42:51 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2322955878 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 369.prim_prince_test.2322955878
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/369.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/37.prim_prince_test.1476236755
Short name T55
Test name
Test status
Simulation time 3043643756 ps
CPU time 57.24 seconds
Started Oct 11 11:36:12 PM UTC 24
Finished Oct 11 11:37:26 PM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1476236755 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 37.prim_prince_test.1476236755
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/37.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/370.prim_prince_test.2412933957
Short name T351
Test name
Test status
Simulation time 1334268992 ps
CPU time 25.26 seconds
Started Oct 11 11:42:11 PM UTC 24
Finished Oct 11 11:42:44 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2412933957 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 370.prim_prince_test.2412933957
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/370.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/371.prim_prince_test.1456895015
Short name T370
Test name
Test status
Simulation time 1991337990 ps
CPU time 36.38 seconds
Started Oct 11 11:42:11 PM UTC 24
Finished Oct 11 11:42:58 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1456895015 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 371.prim_prince_test.1456895015
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/371.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/372.prim_prince_test.1897707501
Short name T405
Test name
Test status
Simulation time 3528679540 ps
CPU time 65.37 seconds
Started Oct 11 11:42:13 PM UTC 24
Finished Oct 11 11:43:35 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1897707501 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 372.prim_prince_test.1897707501
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/372.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/373.prim_prince_test.4052741013
Short name T391
Test name
Test status
Simulation time 2831798209 ps
CPU time 51.46 seconds
Started Oct 11 11:42:13 PM UTC 24
Finished Oct 11 11:43:19 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4052741013 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 373.prim_prince_test.4052741013
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/373.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/374.prim_prince_test.1875557237
Short name T348
Test name
Test status
Simulation time 1117602860 ps
CPU time 21.45 seconds
Started Oct 11 11:42:15 PM UTC 24
Finished Oct 11 11:42:42 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1875557237 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 374.prim_prince_test.1875557237
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/374.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/375.prim_prince_test.3760911610
Short name T349
Test name
Test status
Simulation time 1130923015 ps
CPU time 21 seconds
Started Oct 11 11:42:16 PM UTC 24
Finished Oct 11 11:42:43 PM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3760911610 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 375.prim_prince_test.3760911610
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/375.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/376.prim_prince_test.3520235702
Short name T379
Test name
Test status
Simulation time 2282012827 ps
CPU time 42.98 seconds
Started Oct 11 11:42:16 PM UTC 24
Finished Oct 11 11:43:11 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3520235702 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 376.prim_prince_test.3520235702
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/376.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/377.prim_prince_test.1189656901
Short name T410
Test name
Test status
Simulation time 3343012457 ps
CPU time 60.9 seconds
Started Oct 11 11:42:20 PM UTC 24
Finished Oct 11 11:43:38 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1189656901 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 377.prim_prince_test.1189656901
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/377.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/378.prim_prince_test.2020633801
Short name T353
Test name
Test status
Simulation time 974223322 ps
CPU time 18.52 seconds
Started Oct 11 11:42:22 PM UTC 24
Finished Oct 11 11:42:46 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2020633801 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 378.prim_prince_test.2020633801
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/378.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/379.prim_prince_test.142094789
Short name T358
Test name
Test status
Simulation time 1178807624 ps
CPU time 22.24 seconds
Started Oct 11 11:42:22 PM UTC 24
Finished Oct 11 11:42:50 PM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=142094789 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 379.prim_prince_test.142094789
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/379.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/38.prim_prince_test.1125564692
Short name T52
Test name
Test status
Simulation time 2846842039 ps
CPU time 55.14 seconds
Started Oct 11 11:36:13 PM UTC 24
Finished Oct 11 11:37:24 PM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1125564692 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 38.prim_prince_test.1125564692
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/38.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/380.prim_prince_test.2872373423
Short name T408
Test name
Test status
Simulation time 3144860403 ps
CPU time 58.01 seconds
Started Oct 11 11:42:23 PM UTC 24
Finished Oct 11 11:43:36 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2872373423 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 380.prim_prince_test.2872373423
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/380.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/381.prim_prince_test.1476009038
Short name T364
Test name
Test status
Simulation time 1305277356 ps
CPU time 24.72 seconds
Started Oct 11 11:42:23 PM UTC 24
Finished Oct 11 11:42:55 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1476009038 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 381.prim_prince_test.1476009038
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/381.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/382.prim_prince_test.465569796
Short name T388
Test name
Test status
Simulation time 2289251877 ps
CPU time 42.79 seconds
Started Oct 11 11:42:23 PM UTC 24
Finished Oct 11 11:43:17 PM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=465569796 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 382.prim_prince_test.465569796
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/382.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/383.prim_prince_test.3635550576
Short name T390
Test name
Test status
Simulation time 2287042661 ps
CPU time 42.48 seconds
Started Oct 11 11:42:24 PM UTC 24
Finished Oct 11 11:43:18 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3635550576 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 383.prim_prince_test.3635550576
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/383.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/384.prim_prince_test.1929170282
Short name T368
Test name
Test status
Simulation time 1405163974 ps
CPU time 25.64 seconds
Started Oct 11 11:42:24 PM UTC 24
Finished Oct 11 11:42:58 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1929170282 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 384.prim_prince_test.1929170282
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/384.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/385.prim_prince_test.2285088871
Short name T367
Test name
Test status
Simulation time 1369685451 ps
CPU time 25.53 seconds
Started Oct 11 11:42:24 PM UTC 24
Finished Oct 11 11:42:57 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2285088871 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 385.prim_prince_test.2285088871
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/385.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/386.prim_prince_test.2488215110
Short name T360
Test name
Test status
Simulation time 1022386171 ps
CPU time 19.28 seconds
Started Oct 11 11:42:27 PM UTC 24
Finished Oct 11 11:42:52 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2488215110 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 386.prim_prince_test.2488215110
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/386.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/387.prim_prince_test.2308688235
Short name T423
Test name
Test status
Simulation time 3400134001 ps
CPU time 63.56 seconds
Started Oct 11 11:42:27 PM UTC 24
Finished Oct 11 11:43:47 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2308688235 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 387.prim_prince_test.2308688235
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/387.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/388.prim_prince_test.3679838143
Short name T415
Test name
Test status
Simulation time 3183335366 ps
CPU time 59.62 seconds
Started Oct 11 11:42:27 PM UTC 24
Finished Oct 11 11:43:42 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3679838143 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 388.prim_prince_test.3679838143
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/388.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/389.prim_prince_test.3822906218
Short name T384
Test name
Test status
Simulation time 1947335066 ps
CPU time 36.57 seconds
Started Oct 11 11:42:28 PM UTC 24
Finished Oct 11 11:43:15 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3822906218 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 389.prim_prince_test.3822906218
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/389.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/39.prim_prince_test.1511067482
Short name T35
Test name
Test status
Simulation time 1938489549 ps
CPU time 37.84 seconds
Started Oct 11 11:36:15 PM UTC 24
Finished Oct 11 11:37:04 PM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1511067482 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 39.prim_prince_test.1511067482
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/39.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/390.prim_prince_test.1900442361
Short name T387
Test name
Test status
Simulation time 2033871781 ps
CPU time 37.1 seconds
Started Oct 11 11:42:29 PM UTC 24
Finished Oct 11 11:43:17 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1900442361 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 390.prim_prince_test.1900442361
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/390.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/391.prim_prince_test.3123756233
Short name T392
Test name
Test status
Simulation time 2193562467 ps
CPU time 39.9 seconds
Started Oct 11 11:42:29 PM UTC 24
Finished Oct 11 11:43:21 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3123756233 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 391.prim_prince_test.3123756233
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/391.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/392.prim_prince_test.440640335
Short name T376
Test name
Test status
Simulation time 1475498878 ps
CPU time 27.87 seconds
Started Oct 11 11:42:31 PM UTC 24
Finished Oct 11 11:43:07 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=440640335 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 392.prim_prince_test.440640335
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/392.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/393.prim_prince_test.2600725002
Short name T412
Test name
Test status
Simulation time 3019468968 ps
CPU time 54.35 seconds
Started Oct 11 11:42:31 PM UTC 24
Finished Oct 11 11:43:40 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2600725002 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 393.prim_prince_test.2600725002
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/393.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/394.prim_prince_test.1046813185
Short name T362
Test name
Test status
Simulation time 880109162 ps
CPU time 16.78 seconds
Started Oct 11 11:42:31 PM UTC 24
Finished Oct 11 11:42:53 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1046813185 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 394.prim_prince_test.1046813185
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/394.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/395.prim_prince_test.532459442
Short name T428
Test name
Test status
Simulation time 3437962936 ps
CPU time 64.26 seconds
Started Oct 11 11:42:31 PM UTC 24
Finished Oct 11 11:43:52 PM UTC 24
Peak memory 154852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=532459442 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 395.prim_prince_test.532459442
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/395.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/396.prim_prince_test.3460979363
Short name T411
Test name
Test status
Simulation time 2924109199 ps
CPU time 54.56 seconds
Started Oct 11 11:42:31 PM UTC 24
Finished Oct 11 11:43:40 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3460979363 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 396.prim_prince_test.3460979363
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/396.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/397.prim_prince_test.4211152194
Short name T365
Test name
Test status
Simulation time 946425375 ps
CPU time 18.09 seconds
Started Oct 11 11:42:31 PM UTC 24
Finished Oct 11 11:42:55 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4211152194 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 397.prim_prince_test.4211152194
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/397.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/398.prim_prince_test.3820133275
Short name T394
Test name
Test status
Simulation time 2138403780 ps
CPU time 40.1 seconds
Started Oct 11 11:42:34 PM UTC 24
Finished Oct 11 11:43:25 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3820133275 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 398.prim_prince_test.3820133275
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/398.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/399.prim_prince_test.2856118303
Short name T403
Test name
Test status
Simulation time 2386275506 ps
CPU time 43.61 seconds
Started Oct 11 11:42:37 PM UTC 24
Finished Oct 11 11:43:32 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2856118303 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 399.prim_prince_test.2856118303
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/399.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/4.prim_prince_test.3526192074
Short name T17
Test name
Test status
Simulation time 1756517472 ps
CPU time 33.8 seconds
Started Oct 11 11:35:48 PM UTC 24
Finished Oct 11 11:36:33 PM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3526192074 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 4.prim_prince_test.3526192074
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/4.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/40.prim_prince_test.4281777832
Short name T34
Test name
Test status
Simulation time 1903674688 ps
CPU time 36.39 seconds
Started Oct 11 11:36:16 PM UTC 24
Finished Oct 11 11:37:04 PM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4281777832 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 40.prim_prince_test.4281777832
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/40.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/400.prim_prince_test.2708445139
Short name T426
Test name
Test status
Simulation time 3071381695 ps
CPU time 57.47 seconds
Started Oct 11 11:42:37 PM UTC 24
Finished Oct 11 11:43:49 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2708445139 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 400.prim_prince_test.2708445139
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/400.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/401.prim_prince_test.910738346
Short name T435
Test name
Test status
Simulation time 3696542403 ps
CPU time 68.23 seconds
Started Oct 11 11:42:38 PM UTC 24
Finished Oct 11 11:44:04 PM UTC 24
Peak memory 155048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=910738346 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 401.prim_prince_test.910738346
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/401.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/402.prim_prince_test.3785735053
Short name T393
Test name
Test status
Simulation time 1745827127 ps
CPU time 32.93 seconds
Started Oct 11 11:42:39 PM UTC 24
Finished Oct 11 11:43:21 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3785735053 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 402.prim_prince_test.3785735053
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/402.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/403.prim_prince_test.3802163271
Short name T424
Test name
Test status
Simulation time 2917294860 ps
CPU time 53.11 seconds
Started Oct 11 11:42:40 PM UTC 24
Finished Oct 11 11:43:48 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3802163271 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 403.prim_prince_test.3802163271
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/403.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/404.prim_prince_test.1885760713
Short name T414
Test name
Test status
Simulation time 2624408710 ps
CPU time 47.86 seconds
Started Oct 11 11:42:40 PM UTC 24
Finished Oct 11 11:43:41 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1885760713 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 404.prim_prince_test.1885760713
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/404.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/405.prim_prince_test.3785676696
Short name T436
Test name
Test status
Simulation time 3558196079 ps
CPU time 65.22 seconds
Started Oct 11 11:42:41 PM UTC 24
Finished Oct 11 11:44:04 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3785676696 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 405.prim_prince_test.3785676696
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/405.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/406.prim_prince_test.3071467668
Short name T380
Test name
Test status
Simulation time 1111434577 ps
CPU time 21.02 seconds
Started Oct 11 11:42:44 PM UTC 24
Finished Oct 11 11:43:11 PM UTC 24
Peak memory 156328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3071467668 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 406.prim_prince_test.3071467668
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/406.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/407.prim_prince_test.2055596192
Short name T402
Test name
Test status
Simulation time 1960419647 ps
CPU time 36.91 seconds
Started Oct 11 11:42:45 PM UTC 24
Finished Oct 11 11:43:32 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2055596192 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 407.prim_prince_test.2055596192
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/407.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/408.prim_prince_test.1450003606
Short name T418
Test name
Test status
Simulation time 2573858009 ps
CPU time 46.84 seconds
Started Oct 11 11:42:45 PM UTC 24
Finished Oct 11 11:43:45 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1450003606 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 408.prim_prince_test.1450003606
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/408.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/409.prim_prince_test.1752571773
Short name T398
Test name
Test status
Simulation time 1876179318 ps
CPU time 35.35 seconds
Started Oct 11 11:42:45 PM UTC 24
Finished Oct 11 11:43:30 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1752571773 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 409.prim_prince_test.1752571773
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/409.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/41.prim_prince_test.2755201054
Short name T27
Test name
Test status
Simulation time 1186006808 ps
CPU time 23.29 seconds
Started Oct 11 11:36:18 PM UTC 24
Finished Oct 11 11:36:48 PM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2755201054 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 41.prim_prince_test.2755201054
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/41.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/410.prim_prince_test.4154309659
Short name T438
Test name
Test status
Simulation time 3397502246 ps
CPU time 63.56 seconds
Started Oct 11 11:42:45 PM UTC 24
Finished Oct 11 11:44:05 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4154309659 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 410.prim_prince_test.4154309659
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/410.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/411.prim_prince_test.2781001573
Short name T399
Test name
Test status
Simulation time 1856977760 ps
CPU time 34.29 seconds
Started Oct 11 11:42:47 PM UTC 24
Finished Oct 11 11:43:30 PM UTC 24
Peak memory 154608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2781001573 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 411.prim_prince_test.2781001573
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/411.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/412.prim_prince_test.2363312122
Short name T382
Test name
Test status
Simulation time 1041160730 ps
CPU time 19.2 seconds
Started Oct 11 11:42:47 PM UTC 24
Finished Oct 11 11:43:12 PM UTC 24
Peak memory 154540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2363312122 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 412.prim_prince_test.2363312122
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/412.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/413.prim_prince_test.815236755
Short name T445
Test name
Test status
Simulation time 3410903725 ps
CPU time 61.93 seconds
Started Oct 11 11:42:49 PM UTC 24
Finished Oct 11 11:44:08 PM UTC 24
Peak memory 155048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=815236755 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 413.prim_prince_test.815236755
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/413.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/414.prim_prince_test.2934299248
Short name T449
Test name
Test status
Simulation time 3538862245 ps
CPU time 65.87 seconds
Started Oct 11 11:42:49 PM UTC 24
Finished Oct 11 11:44:12 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2934299248 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 414.prim_prince_test.2934299248
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/414.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/415.prim_prince_test.2220742882
Short name T400
Test name
Test status
Simulation time 1677002741 ps
CPU time 31.65 seconds
Started Oct 11 11:42:50 PM UTC 24
Finished Oct 11 11:43:31 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2220742882 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 415.prim_prince_test.2220742882
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/415.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/416.prim_prince_test.963998635
Short name T383
Test name
Test status
Simulation time 889511076 ps
CPU time 16.7 seconds
Started Oct 11 11:42:50 PM UTC 24
Finished Oct 11 11:43:12 PM UTC 24
Peak memory 154984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=963998635 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 416.prim_prince_test.963998635
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/416.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/417.prim_prince_test.1975914363
Short name T456
Test name
Test status
Simulation time 3699192383 ps
CPU time 68.76 seconds
Started Oct 11 11:42:50 PM UTC 24
Finished Oct 11 11:44:17 PM UTC 24
Peak memory 156400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1975914363 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 417.prim_prince_test.1975914363
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/417.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/418.prim_prince_test.1800697219
Short name T395
Test name
Test status
Simulation time 1386903941 ps
CPU time 26 seconds
Started Oct 11 11:42:52 PM UTC 24
Finished Oct 11 11:43:25 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1800697219 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 418.prim_prince_test.1800697219
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/418.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/419.prim_prince_test.1451719182
Short name T440
Test name
Test status
Simulation time 3163313176 ps
CPU time 57.58 seconds
Started Oct 11 11:42:52 PM UTC 24
Finished Oct 11 11:44:05 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1451719182 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 419.prim_prince_test.1451719182
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/419.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/42.prim_prince_test.2678186481
Short name T40
Test name
Test status
Simulation time 1999800759 ps
CPU time 39.13 seconds
Started Oct 11 11:36:20 PM UTC 24
Finished Oct 11 11:37:10 PM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2678186481 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 42.prim_prince_test.2678186481
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/42.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/420.prim_prince_test.377982694
Short name T386
Test name
Test status
Simulation time 1023756339 ps
CPU time 19.14 seconds
Started Oct 11 11:42:52 PM UTC 24
Finished Oct 11 11:43:17 PM UTC 24
Peak memory 154984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=377982694 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 420.prim_prince_test.377982694
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/420.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/421.prim_prince_test.1450862836
Short name T396
Test name
Test status
Simulation time 1417739030 ps
CPU time 26.72 seconds
Started Oct 11 11:42:53 PM UTC 24
Finished Oct 11 11:43:28 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1450862836 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 421.prim_prince_test.1450862836
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/421.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/422.prim_prince_test.381273701
Short name T432
Test name
Test status
Simulation time 2834537391 ps
CPU time 52.35 seconds
Started Oct 11 11:42:53 PM UTC 24
Finished Oct 11 11:44:00 PM UTC 24
Peak memory 155048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=381273701 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 422.prim_prince_test.381273701
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/422.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/423.prim_prince_test.3859268980
Short name T444
Test name
Test status
Simulation time 3133229973 ps
CPU time 58.85 seconds
Started Oct 11 11:42:54 PM UTC 24
Finished Oct 11 11:44:07 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3859268980 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 423.prim_prince_test.3859268980
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/423.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/424.prim_prince_test.2432778926
Short name T446
Test name
Test status
Simulation time 3240005688 ps
CPU time 59.42 seconds
Started Oct 11 11:42:55 PM UTC 24
Finished Oct 11 11:44:10 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2432778926 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 424.prim_prince_test.2432778926
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/424.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/425.prim_prince_test.100472758
Short name T425
Test name
Test status
Simulation time 2250493531 ps
CPU time 41.05 seconds
Started Oct 11 11:42:56 PM UTC 24
Finished Oct 11 11:43:48 PM UTC 24
Peak memory 155048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=100472758 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 425.prim_prince_test.100472758
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/425.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/426.prim_prince_test.58397201
Short name T447
Test name
Test status
Simulation time 3161118211 ps
CPU time 59.14 seconds
Started Oct 11 11:42:56 PM UTC 24
Finished Oct 11 11:44:10 PM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=58397201 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 426.prim_prince_test.58397201
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/426.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/427.prim_prince_test.3473320155
Short name T397
Test name
Test status
Simulation time 1266011086 ps
CPU time 24.16 seconds
Started Oct 11 11:42:57 PM UTC 24
Finished Oct 11 11:43:28 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3473320155 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 427.prim_prince_test.3473320155
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/427.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/428.prim_prince_test.2368170931
Short name T451
Test name
Test status
Simulation time 3158018096 ps
CPU time 58.92 seconds
Started Oct 11 11:42:59 PM UTC 24
Finished Oct 11 11:44:13 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2368170931 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 428.prim_prince_test.2368170931
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/428.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/429.prim_prince_test.1249343199
Short name T401
Test name
Test status
Simulation time 1318355579 ps
CPU time 25.02 seconds
Started Oct 11 11:42:59 PM UTC 24
Finished Oct 11 11:43:31 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1249343199 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 429.prim_prince_test.1249343199
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/429.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/43.prim_prince_test.371476120
Short name T54
Test name
Test status
Simulation time 2510173500 ps
CPU time 48.91 seconds
Started Oct 11 11:36:22 PM UTC 24
Finished Oct 11 11:37:25 PM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=371476120 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 43.prim_prince_test.371476120
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/43.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/430.prim_prince_test.2110273205
Short name T441
Test name
Test status
Simulation time 2881745210 ps
CPU time 52.44 seconds
Started Oct 11 11:42:59 PM UTC 24
Finished Oct 11 11:44:05 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2110273205 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 430.prim_prince_test.2110273205
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/430.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/431.prim_prince_test.1222766991
Short name T419
Test name
Test status
Simulation time 1996845154 ps
CPU time 36.12 seconds
Started Oct 11 11:42:59 PM UTC 24
Finished Oct 11 11:43:45 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1222766991 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 431.prim_prince_test.1222766991
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/431.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/432.prim_prince_test.3506550389
Short name T413
Test name
Test status
Simulation time 1704424192 ps
CPU time 31.61 seconds
Started Oct 11 11:43:00 PM UTC 24
Finished Oct 11 11:43:40 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3506550389 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 432.prim_prince_test.3506550389
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/432.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/433.prim_prince_test.1272916863
Short name T422
Test name
Test status
Simulation time 1877383829 ps
CPU time 35.52 seconds
Started Oct 11 11:43:01 PM UTC 24
Finished Oct 11 11:43:46 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1272916863 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 433.prim_prince_test.1272916863
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/433.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/434.prim_prince_test.2444677775
Short name T427
Test name
Test status
Simulation time 2074292843 ps
CPU time 37.96 seconds
Started Oct 11 11:43:02 PM UTC 24
Finished Oct 11 11:43:51 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2444677775 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 434.prim_prince_test.2444677775
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/434.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/435.prim_prince_test.2702633616
Short name T454
Test name
Test status
Simulation time 2890338622 ps
CPU time 53.26 seconds
Started Oct 11 11:43:06 PM UTC 24
Finished Oct 11 11:44:14 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2702633616 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 435.prim_prince_test.2702633616
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/435.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/436.prim_prince_test.1437696353
Short name T459
Test name
Test status
Simulation time 3070164098 ps
CPU time 56.97 seconds
Started Oct 11 11:43:07 PM UTC 24
Finished Oct 11 11:44:18 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1437696353 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 436.prim_prince_test.1437696353
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/436.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/437.prim_prince_test.1428053349
Short name T421
Test name
Test status
Simulation time 1586967375 ps
CPU time 29.9 seconds
Started Oct 11 11:43:08 PM UTC 24
Finished Oct 11 11:43:46 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1428053349 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 437.prim_prince_test.1428053349
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/437.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/438.prim_prince_test.503261860
Short name T404
Test name
Test status
Simulation time 961560815 ps
CPU time 18.45 seconds
Started Oct 11 11:43:10 PM UTC 24
Finished Oct 11 11:43:34 PM UTC 24
Peak memory 154940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=503261860 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 438.prim_prince_test.503261860
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/438.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/439.prim_prince_test.1120813984
Short name T465
Test name
Test status
Simulation time 3001501582 ps
CPU time 54.73 seconds
Started Oct 11 11:43:10 PM UTC 24
Finished Oct 11 11:44:20 PM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1120813984 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 439.prim_prince_test.1120813984
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/439.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/44.prim_prince_test.1116922493
Short name T28
Test name
Test status
Simulation time 995059000 ps
CPU time 19.91 seconds
Started Oct 11 11:36:26 PM UTC 24
Finished Oct 11 11:36:52 PM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1116922493 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 44.prim_prince_test.1116922493
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/44.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/440.prim_prince_test.3830621703
Short name T462
Test name
Test status
Simulation time 2935220587 ps
CPU time 53.44 seconds
Started Oct 11 11:43:11 PM UTC 24
Finished Oct 11 11:44:19 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3830621703 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 440.prim_prince_test.3830621703
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/440.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/441.prim_prince_test.2933565060
Short name T466
Test name
Test status
Simulation time 2969336343 ps
CPU time 53.58 seconds
Started Oct 11 11:43:11 PM UTC 24
Finished Oct 11 11:44:20 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2933565060 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 441.prim_prince_test.2933565060
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/441.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/442.prim_prince_test.2466194372
Short name T420
Test name
Test status
Simulation time 1407050258 ps
CPU time 25.82 seconds
Started Oct 11 11:43:13 PM UTC 24
Finished Oct 11 11:43:46 PM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2466194372 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 442.prim_prince_test.2466194372
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/442.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/443.prim_prince_test.2182696599
Short name T431
Test name
Test status
Simulation time 1967605502 ps
CPU time 37.14 seconds
Started Oct 11 11:43:13 PM UTC 24
Finished Oct 11 11:44:00 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2182696599 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 443.prim_prince_test.2182696599
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/443.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/444.prim_prince_test.1324281276
Short name T417
Test name
Test status
Simulation time 1191214266 ps
CPU time 22.55 seconds
Started Oct 11 11:43:14 PM UTC 24
Finished Oct 11 11:43:43 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1324281276 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 444.prim_prince_test.1324281276
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/444.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/445.prim_prince_test.2207454687
Short name T476
Test name
Test status
Simulation time 3314307181 ps
CPU time 59.39 seconds
Started Oct 11 11:43:15 PM UTC 24
Finished Oct 11 11:44:31 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2207454687 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 445.prim_prince_test.2207454687
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/445.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/446.prim_prince_test.2934479440
Short name T434
Test name
Test status
Simulation time 2006177429 ps
CPU time 37.55 seconds
Started Oct 11 11:43:16 PM UTC 24
Finished Oct 11 11:44:04 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2934479440 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 446.prim_prince_test.2934479440
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/446.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/447.prim_prince_test.2283466808
Short name T469
Test name
Test status
Simulation time 2894692862 ps
CPU time 53.46 seconds
Started Oct 11 11:43:17 PM UTC 24
Finished Oct 11 11:44:25 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2283466808 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 447.prim_prince_test.2283466808
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/447.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/448.prim_prince_test.1691145831
Short name T458
Test name
Test status
Simulation time 2555064717 ps
CPU time 47.39 seconds
Started Oct 11 11:43:18 PM UTC 24
Finished Oct 11 11:44:18 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1691145831 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 448.prim_prince_test.1691145831
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/448.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/449.prim_prince_test.2171785053
Short name T443
Test name
Test status
Simulation time 2034964347 ps
CPU time 38 seconds
Started Oct 11 11:43:19 PM UTC 24
Finished Oct 11 11:44:07 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2171785053 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 449.prim_prince_test.2171785053
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/449.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/45.prim_prince_test.2643650317
Short name T60
Test name
Test status
Simulation time 3541215160 ps
CPU time 67.78 seconds
Started Oct 11 11:36:27 PM UTC 24
Finished Oct 11 11:37:54 PM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2643650317 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 45.prim_prince_test.2643650317
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/45.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/450.prim_prince_test.2750604771
Short name T409
Test name
Test status
Simulation time 757352989 ps
CPU time 13.96 seconds
Started Oct 11 11:43:19 PM UTC 24
Finished Oct 11 11:43:37 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2750604771 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 450.prim_prince_test.2750604771
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/450.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/451.prim_prince_test.2783753541
Short name T471
Test name
Test status
Simulation time 2967063797 ps
CPU time 54.13 seconds
Started Oct 11 11:43:19 PM UTC 24
Finished Oct 11 11:44:28 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2783753541 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 451.prim_prince_test.2783753541
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/451.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/452.prim_prince_test.4244298915
Short name T429
Test name
Test status
Simulation time 1371623108 ps
CPU time 25.88 seconds
Started Oct 11 11:43:20 PM UTC 24
Finished Oct 11 11:43:53 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4244298915 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 452.prim_prince_test.4244298915
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/452.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/453.prim_prince_test.1602651359
Short name T442
Test name
Test status
Simulation time 1908422354 ps
CPU time 35.78 seconds
Started Oct 11 11:43:22 PM UTC 24
Finished Oct 11 11:44:07 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1602651359 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 453.prim_prince_test.1602651359
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/453.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/454.prim_prince_test.3574328305
Short name T416
Test name
Test status
Simulation time 828260503 ps
CPU time 15.77 seconds
Started Oct 11 11:43:22 PM UTC 24
Finished Oct 11 11:43:42 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3574328305 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 454.prim_prince_test.3574328305
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/454.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/455.prim_prince_test.3147239823
Short name T480
Test name
Test status
Simulation time 3114991551 ps
CPU time 55.48 seconds
Started Oct 11 11:43:27 PM UTC 24
Finished Oct 11 11:44:38 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3147239823 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 455.prim_prince_test.3147239823
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/455.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/456.prim_prince_test.110439783
Short name T461
Test name
Test status
Simulation time 2205989059 ps
CPU time 41.19 seconds
Started Oct 11 11:43:27 PM UTC 24
Finished Oct 11 11:44:19 PM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=110439783 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 456.prim_prince_test.110439783
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/456.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/457.prim_prince_test.908167399
Short name T474
Test name
Test status
Simulation time 2673799488 ps
CPU time 47.75 seconds
Started Oct 11 11:43:28 PM UTC 24
Finished Oct 11 11:44:29 PM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=908167399 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 457.prim_prince_test.908167399
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/457.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/458.prim_prince_test.84982546
Short name T452
Test name
Test status
Simulation time 1883096624 ps
CPU time 34.3 seconds
Started Oct 11 11:43:29 PM UTC 24
Finished Oct 11 11:44:14 PM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=84982546 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 458.prim_prince_test.84982546
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/458.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/459.prim_prince_test.1460136799
Short name T482
Test name
Test status
Simulation time 3107302159 ps
CPU time 54.62 seconds
Started Oct 11 11:43:32 PM UTC 24
Finished Oct 11 11:44:42 PM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1460136799 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 459.prim_prince_test.1460136799
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/459.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/46.prim_prince_test.3043194517
Short name T48
Test name
Test status
Simulation time 2001000849 ps
CPU time 38.07 seconds
Started Oct 11 11:36:27 PM UTC 24
Finished Oct 11 11:37:17 PM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3043194517 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 46.prim_prince_test.3043194517
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/46.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/460.prim_prince_test.911417735
Short name T473
Test name
Test status
Simulation time 2420101528 ps
CPU time 44.36 seconds
Started Oct 11 11:43:32 PM UTC 24
Finished Oct 11 11:44:28 PM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=911417735 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 460.prim_prince_test.911417735
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/460.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/461.prim_prince_test.319589382
Short name T485
Test name
Test status
Simulation time 3443991146 ps
CPU time 61.86 seconds
Started Oct 11 11:43:32 PM UTC 24
Finished Oct 11 11:44:50 PM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=319589382 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 461.prim_prince_test.319589382
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/461.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/462.prim_prince_test.1705094450
Short name T433
Test name
Test status
Simulation time 1251927903 ps
CPU time 23.81 seconds
Started Oct 11 11:43:32 PM UTC 24
Finished Oct 11 11:44:03 PM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1705094450 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 462.prim_prince_test.1705094450
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/462.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/463.prim_prince_test.3889906104
Short name T488
Test name
Test status
Simulation time 3542979753 ps
CPU time 62.84 seconds
Started Oct 11 11:43:33 PM UTC 24
Finished Oct 11 11:44:53 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3889906104 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 463.prim_prince_test.3889906104
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/463.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/464.prim_prince_test.1659938056
Short name T430
Test name
Test status
Simulation time 814070744 ps
CPU time 15.58 seconds
Started Oct 11 11:43:33 PM UTC 24
Finished Oct 11 11:43:54 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1659938056 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 464.prim_prince_test.1659938056
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/464.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/465.prim_prince_test.4221310045
Short name T470
Test name
Test status
Simulation time 2250156496 ps
CPU time 40.74 seconds
Started Oct 11 11:43:35 PM UTC 24
Finished Oct 11 11:44:27 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4221310045 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 465.prim_prince_test.4221310045
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/465.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/466.prim_prince_test.41725363
Short name T464
Test name
Test status
Simulation time 1826595414 ps
CPU time 33.64 seconds
Started Oct 11 11:43:37 PM UTC 24
Finished Oct 11 11:44:20 PM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41725363 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 466.prim_prince_test.41725363
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/466.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/467.prim_prince_test.1905693623
Short name T463
Test name
Test status
Simulation time 1825920530 ps
CPU time 33.63 seconds
Started Oct 11 11:43:37 PM UTC 24
Finished Oct 11 11:44:20 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1905693623 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 467.prim_prince_test.1905693623
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/467.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/468.prim_prince_test.2743907134
Short name T477
Test name
Test status
Simulation time 2409742429 ps
CPU time 43.41 seconds
Started Oct 11 11:43:37 PM UTC 24
Finished Oct 11 11:44:32 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2743907134 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 468.prim_prince_test.2743907134
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/468.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/469.prim_prince_test.2423199011
Short name T437
Test name
Test status
Simulation time 1132470167 ps
CPU time 21.6 seconds
Started Oct 11 11:43:37 PM UTC 24
Finished Oct 11 11:44:05 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2423199011 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 469.prim_prince_test.2423199011
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/469.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/47.prim_prince_test.1735677965
Short name T71
Test name
Test status
Simulation time 3476658247 ps
CPU time 64.72 seconds
Started Oct 11 11:36:28 PM UTC 24
Finished Oct 11 11:37:52 PM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1735677965 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 47.prim_prince_test.1735677965
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/47.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/470.prim_prince_test.320040003
Short name T439
Test name
Test status
Simulation time 1109770816 ps
CPU time 20.79 seconds
Started Oct 11 11:43:38 PM UTC 24
Finished Oct 11 11:44:05 PM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=320040003 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 470.prim_prince_test.320040003
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/470.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/471.prim_prince_test.852516752
Short name T467
Test name
Test status
Simulation time 1787934515 ps
CPU time 32.65 seconds
Started Oct 11 11:43:38 PM UTC 24
Finished Oct 11 11:44:20 PM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=852516752 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 471.prim_prince_test.852516752
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/471.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/472.prim_prince_test.118549832
Short name T491
Test name
Test status
Simulation time 3373590518 ps
CPU time 60.06 seconds
Started Oct 11 11:43:41 PM UTC 24
Finished Oct 11 11:44:57 PM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=118549832 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 472.prim_prince_test.118549832
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/472.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/473.prim_prince_test.1349731807
Short name T478
Test name
Test status
Simulation time 2301283478 ps
CPU time 41.93 seconds
Started Oct 11 11:43:42 PM UTC 24
Finished Oct 11 11:44:35 PM UTC 24
Peak memory 154648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1349731807 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 473.prim_prince_test.1349731807
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/473.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/474.prim_prince_test.4266802070
Short name T448
Test name
Test status
Simulation time 1223594335 ps
CPU time 23.22 seconds
Started Oct 11 11:43:42 PM UTC 24
Finished Oct 11 11:44:12 PM UTC 24
Peak memory 154660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4266802070 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 474.prim_prince_test.4266802070
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/474.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/475.prim_prince_test.2514161210
Short name T481
Test name
Test status
Simulation time 2537477192 ps
CPU time 45.01 seconds
Started Oct 11 11:43:42 PM UTC 24
Finished Oct 11 11:44:40 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2514161210 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 475.prim_prince_test.2514161210
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/475.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/476.prim_prince_test.2601398402
Short name T450
Test name
Test status
Simulation time 1192990250 ps
CPU time 22.41 seconds
Started Oct 11 11:43:44 PM UTC 24
Finished Oct 11 11:44:12 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2601398402 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 476.prim_prince_test.2601398402
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/476.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/477.prim_prince_test.2068032377
Short name T486
Test name
Test status
Simulation time 3106459832 ps
CPU time 53.6 seconds
Started Oct 11 11:43:44 PM UTC 24
Finished Oct 11 11:44:52 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2068032377 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 477.prim_prince_test.2068032377
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/477.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/478.prim_prince_test.1618598459
Short name T457
Test name
Test status
Simulation time 1409151807 ps
CPU time 25.97 seconds
Started Oct 11 11:43:44 PM UTC 24
Finished Oct 11 11:44:17 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1618598459 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 478.prim_prince_test.1618598459
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/478.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/479.prim_prince_test.3324001966
Short name T490
Test name
Test status
Simulation time 3076915372 ps
CPU time 54.2 seconds
Started Oct 11 11:43:46 PM UTC 24
Finished Oct 11 11:44:55 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3324001966 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 479.prim_prince_test.3324001966
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/479.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/48.prim_prince_test.2733192917
Short name T61
Test name
Test status
Simulation time 2671438711 ps
CPU time 51.9 seconds
Started Oct 11 11:36:28 PM UTC 24
Finished Oct 11 11:37:35 PM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2733192917 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 48.prim_prince_test.2733192917
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/48.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/480.prim_prince_test.1286947836
Short name T479
Test name
Test status
Simulation time 2272270282 ps
CPU time 40.32 seconds
Started Oct 11 11:43:46 PM UTC 24
Finished Oct 11 11:44:37 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1286947836 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 480.prim_prince_test.1286947836
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/480.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/481.prim_prince_test.2977324714
Short name T483
Test name
Test status
Simulation time 2462620606 ps
CPU time 43.17 seconds
Started Oct 11 11:43:47 PM UTC 24
Finished Oct 11 11:44:43 PM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2977324714 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 481.prim_prince_test.2977324714
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/481.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/482.prim_prince_test.1253348249
Short name T489
Test name
Test status
Simulation time 3027361328 ps
CPU time 52.09 seconds
Started Oct 11 11:43:47 PM UTC 24
Finished Oct 11 11:44:54 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1253348249 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 482.prim_prince_test.1253348249
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/482.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/483.prim_prince_test.1759614549
Short name T468
Test name
Test status
Simulation time 1388249564 ps
CPU time 25.39 seconds
Started Oct 11 11:43:47 PM UTC 24
Finished Oct 11 11:44:20 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1759614549 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 483.prim_prince_test.1759614549
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/483.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/484.prim_prince_test.1190767695
Short name T492
Test name
Test status
Simulation time 3071350455 ps
CPU time 54.9 seconds
Started Oct 11 11:43:49 PM UTC 24
Finished Oct 11 11:44:58 PM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1190767695 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 484.prim_prince_test.1190767695
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/484.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/485.prim_prince_test.2689076375
Short name T455
Test name
Test status
Simulation time 1153372562 ps
CPU time 21.43 seconds
Started Oct 11 11:43:49 PM UTC 24
Finished Oct 11 11:44:17 PM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2689076375 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 485.prim_prince_test.2689076375
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/485.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/486.prim_prince_test.228082978
Short name T453
Test name
Test status
Simulation time 1039035471 ps
CPU time 19.4 seconds
Started Oct 11 11:43:49 PM UTC 24
Finished Oct 11 11:44:14 PM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=228082978 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 486.prim_prince_test.228082978
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/486.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/487.prim_prince_test.1553234710
Short name T460
Test name
Test status
Simulation time 1229855136 ps
CPU time 22.73 seconds
Started Oct 11 11:43:50 PM UTC 24
Finished Oct 11 11:44:19 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1553234710 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 487.prim_prince_test.1553234710
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/487.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/488.prim_prince_test.2213195142
Short name T475
Test name
Test status
Simulation time 1679788024 ps
CPU time 30.18 seconds
Started Oct 11 11:43:51 PM UTC 24
Finished Oct 11 11:44:30 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2213195142 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 488.prim_prince_test.2213195142
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/488.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/489.prim_prince_test.90821460
Short name T493
Test name
Test status
Simulation time 3064646100 ps
CPU time 53.29 seconds
Started Oct 11 11:43:53 PM UTC 24
Finished Oct 11 11:45:01 PM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=90821460 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 489.prim_prince_test.90821460
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/489.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/49.prim_prince_test.1361163286
Short name T70
Test name
Test status
Simulation time 3254489672 ps
CPU time 62.77 seconds
Started Oct 11 11:36:29 PM UTC 24
Finished Oct 11 11:37:49 PM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1361163286 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 49.prim_prince_test.1361163286
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/49.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/490.prim_prince_test.2305057277
Short name T497
Test name
Test status
Simulation time 3526856072 ps
CPU time 61.65 seconds
Started Oct 11 11:43:53 PM UTC 24
Finished Oct 11 11:45:12 PM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2305057277 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 490.prim_prince_test.2305057277
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/490.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/491.prim_prince_test.1497294613
Short name T494
Test name
Test status
Simulation time 3039394019 ps
CPU time 53.39 seconds
Started Oct 11 11:43:54 PM UTC 24
Finished Oct 11 11:45:02 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1497294613 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 491.prim_prince_test.1497294613
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/491.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/492.prim_prince_test.786098291
Short name T496
Test name
Test status
Simulation time 3457781036 ps
CPU time 59.85 seconds
Started Oct 11 11:43:54 PM UTC 24
Finished Oct 11 11:45:11 PM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=786098291 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 492.prim_prince_test.786098291
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/492.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/493.prim_prince_test.2264267592
Short name T495
Test name
Test status
Simulation time 2798253914 ps
CPU time 50.32 seconds
Started Oct 11 11:44:00 PM UTC 24
Finished Oct 11 11:45:04 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2264267592 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 493.prim_prince_test.2264267592
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/493.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/494.prim_prince_test.391647123
Short name T499
Test name
Test status
Simulation time 3415656961 ps
CPU time 64.03 seconds
Started Oct 11 11:44:01 PM UTC 24
Finished Oct 11 11:45:23 PM UTC 24
Peak memory 156920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=391647123 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 494.prim_prince_test.391647123
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/494.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/495.prim_prince_test.3082307370
Short name T498
Test name
Test status
Simulation time 3053324427 ps
CPU time 52.95 seconds
Started Oct 11 11:44:04 PM UTC 24
Finished Oct 11 11:45:12 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3082307370 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 495.prim_prince_test.3082307370
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/495.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/496.prim_prince_test.2157536549
Short name T484
Test name
Test status
Simulation time 1860046887 ps
CPU time 32.13 seconds
Started Oct 11 11:44:05 PM UTC 24
Finished Oct 11 11:44:46 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2157536549 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 496.prim_prince_test.2157536549
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/496.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/497.prim_prince_test.2354885875
Short name T487
Test name
Test status
Simulation time 2158267852 ps
CPU time 36.81 seconds
Started Oct 11 11:44:05 PM UTC 24
Finished Oct 11 11:44:53 PM UTC 24
Peak memory 155040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2354885875 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 497.prim_prince_test.2354885875
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/497.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/498.prim_prince_test.3395404604
Short name T500
Test name
Test status
Simulation time 3626460362 ps
CPU time 66.56 seconds
Started Oct 11 11:44:05 PM UTC 24
Finished Oct 11 11:45:32 PM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3395404604 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 498.prim_prince_test.3395404604
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/498.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/499.prim_prince_test.4202581417
Short name T472
Test name
Test status
Simulation time 970420053 ps
CPU time 17.54 seconds
Started Oct 11 11:44:05 PM UTC 24
Finished Oct 11 11:44:28 PM UTC 24
Peak memory 154976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4202581417 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 499.prim_prince_test.4202581417
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/499.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/5.prim_prince_test.1877111272
Short name T43
Test name
Test status
Simulation time 3494918313 ps
CPU time 64.89 seconds
Started Oct 11 11:35:48 PM UTC 24
Finished Oct 11 11:37:13 PM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1877111272 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 5.prim_prince_test.1877111272
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/5.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/50.prim_prince_test.2375729327
Short name T47
Test name
Test status
Simulation time 1854195998 ps
CPU time 36.1 seconds
Started Oct 11 11:36:29 PM UTC 24
Finished Oct 11 11:37:16 PM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2375729327 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 50.prim_prince_test.2375729327
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/50.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/51.prim_prince_test.2016204203
Short name T29
Test name
Test status
Simulation time 811047137 ps
CPU time 15.88 seconds
Started Oct 11 11:36:31 PM UTC 24
Finished Oct 11 11:36:52 PM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2016204203 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 51.prim_prince_test.2016204203
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/51.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/52.prim_prince_test.2851958123
Short name T64
Test name
Test status
Simulation time 2726927996 ps
CPU time 50.7 seconds
Started Oct 11 11:36:32 PM UTC 24
Finished Oct 11 11:37:38 PM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2851958123 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 52.prim_prince_test.2851958123
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/52.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/53.prim_prince_test.1075967715
Short name T67
Test name
Test status
Simulation time 3010011867 ps
CPU time 57.66 seconds
Started Oct 11 11:36:33 PM UTC 24
Finished Oct 11 11:37:47 PM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1075967715 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 53.prim_prince_test.1075967715
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/53.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/54.prim_prince_test.3912968820
Short name T74
Test name
Test status
Simulation time 3440419597 ps
CPU time 63.78 seconds
Started Oct 11 11:36:38 PM UTC 24
Finished Oct 11 11:38:00 PM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3912968820 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 54.prim_prince_test.3912968820
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/54.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/55.prim_prince_test.2664035135
Short name T73
Test name
Test status
Simulation time 3379492216 ps
CPU time 62.03 seconds
Started Oct 11 11:36:38 PM UTC 24
Finished Oct 11 11:37:58 PM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2664035135 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 55.prim_prince_test.2664035135
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/55.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/56.prim_prince_test.1251479318
Short name T32
Test name
Test status
Simulation time 777087854 ps
CPU time 15.46 seconds
Started Oct 11 11:36:39 PM UTC 24
Finished Oct 11 11:36:59 PM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1251479318 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 56.prim_prince_test.1251479318
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/56.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/57.prim_prince_test.3580191371
Short name T38
Test name
Test status
Simulation time 1162536047 ps
CPU time 22.73 seconds
Started Oct 11 11:36:39 PM UTC 24
Finished Oct 11 11:37:08 PM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3580191371 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 57.prim_prince_test.3580191371
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/57.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/58.prim_prince_test.3043355631
Short name T72
Test name
Test status
Simulation time 3125629776 ps
CPU time 60.18 seconds
Started Oct 11 11:36:40 PM UTC 24
Finished Oct 11 11:37:56 PM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3043355631 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 58.prim_prince_test.3043355631
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/58.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/59.prim_prince_test.3583419132
Short name T44
Test name
Test status
Simulation time 1301463561 ps
CPU time 25.22 seconds
Started Oct 11 11:36:41 PM UTC 24
Finished Oct 11 11:37:14 PM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3583419132 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 59.prim_prince_test.3583419132
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/59.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/6.prim_prince_test.2875418914
Short name T3
Test name
Test status
Simulation time 893447066 ps
CPU time 17.26 seconds
Started Oct 11 11:35:48 PM UTC 24
Finished Oct 11 11:36:11 PM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2875418914 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 6.prim_prince_test.2875418914
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/6.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/60.prim_prince_test.2967144209
Short name T65
Test name
Test status
Simulation time 2577966795 ps
CPU time 49.82 seconds
Started Oct 11 11:36:41 PM UTC 24
Finished Oct 11 11:37:45 PM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2967144209 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 60.prim_prince_test.2967144209
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/60.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/61.prim_prince_test.3935138551
Short name T76
Test name
Test status
Simulation time 3260539541 ps
CPU time 63.13 seconds
Started Oct 11 11:36:41 PM UTC 24
Finished Oct 11 11:38:01 PM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3935138551 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 61.prim_prince_test.3935138551
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/61.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/62.prim_prince_test.2505190970
Short name T62
Test name
Test status
Simulation time 2309035532 ps
CPU time 42.59 seconds
Started Oct 11 11:36:42 PM UTC 24
Finished Oct 11 11:37:37 PM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2505190970 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 62.prim_prince_test.2505190970
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/62.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/63.prim_prince_test.657760585
Short name T75
Test name
Test status
Simulation time 3163367115 ps
CPU time 60.27 seconds
Started Oct 11 11:36:43 PM UTC 24
Finished Oct 11 11:38:00 PM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=657760585 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 63.prim_prince_test.657760585
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/63.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/64.prim_prince_test.1218067422
Short name T68
Test name
Test status
Simulation time 2523790704 ps
CPU time 47.01 seconds
Started Oct 11 11:36:47 PM UTC 24
Finished Oct 11 11:37:48 PM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1218067422 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 64.prim_prince_test.1218067422
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/64.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/65.prim_prince_test.1332295283
Short name T51
Test name
Test status
Simulation time 1376227569 ps
CPU time 27.05 seconds
Started Oct 11 11:36:48 PM UTC 24
Finished Oct 11 11:37:24 PM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1332295283 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 65.prim_prince_test.1332295283
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/65.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/66.prim_prince_test.576534363
Short name T49
Test name
Test status
Simulation time 1128917586 ps
CPU time 22.03 seconds
Started Oct 11 11:36:52 PM UTC 24
Finished Oct 11 11:37:20 PM UTC 24
Peak memory 156340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=576534363 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 66.prim_prince_test.576534363
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/66.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/67.prim_prince_test.2674439496
Short name T45
Test name
Test status
Simulation time 858035851 ps
CPU time 16.17 seconds
Started Oct 11 11:36:53 PM UTC 24
Finished Oct 11 11:37:14 PM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2674439496 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 67.prim_prince_test.2674439496
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/67.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/68.prim_prince_test.3771871053
Short name T58
Test name
Test status
Simulation time 1555771452 ps
CPU time 30.34 seconds
Started Oct 11 11:36:53 PM UTC 24
Finished Oct 11 11:37:32 PM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3771871053 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 68.prim_prince_test.3771871053
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/68.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/69.prim_prince_test.4030012203
Short name T83
Test name
Test status
Simulation time 3231360667 ps
CPU time 61.85 seconds
Started Oct 11 11:36:55 PM UTC 24
Finished Oct 11 11:38:14 PM UTC 24
Peak memory 155032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4030012203 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 69.prim_prince_test.4030012203
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/69.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/7.prim_prince_test.4238419100
Short name T5
Test name
Test status
Simulation time 1073789158 ps
CPU time 20.72 seconds
Started Oct 11 11:35:48 PM UTC 24
Finished Oct 11 11:36:16 PM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4238419100 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 7.prim_prince_test.4238419100
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/7.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/70.prim_prince_test.2025957362
Short name T81
Test name
Test status
Simulation time 2971752686 ps
CPU time 55.48 seconds
Started Oct 11 11:36:59 PM UTC 24
Finished Oct 11 11:38:11 PM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2025957362 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 70.prim_prince_test.2025957362
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/70.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/71.prim_prince_test.2182507090
Short name T53
Test name
Test status
Simulation time 1006923875 ps
CPU time 18.78 seconds
Started Oct 11 11:36:59 PM UTC 24
Finished Oct 11 11:37:24 PM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2182507090 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 71.prim_prince_test.2182507090
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/71.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/72.prim_prince_test.178411180
Short name T50
Test name
Test status
Simulation time 906141058 ps
CPU time 17.62 seconds
Started Oct 11 11:37:00 PM UTC 24
Finished Oct 11 11:37:23 PM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=178411180 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 72.prim_prince_test.178411180
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/72.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/73.prim_prince_test.1958298189
Short name T59
Test name
Test status
Simulation time 1215209670 ps
CPU time 23.64 seconds
Started Oct 11 11:37:03 PM UTC 24
Finished Oct 11 11:37:34 PM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1958298189 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 73.prim_prince_test.1958298189
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/73.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/74.prim_prince_test.928552317
Short name T88
Test name
Test status
Simulation time 3249571901 ps
CPU time 60.46 seconds
Started Oct 11 11:37:05 PM UTC 24
Finished Oct 11 11:38:22 PM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=928552317 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 74.prim_prince_test.928552317
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/74.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/75.prim_prince_test.3639879395
Short name T82
Test name
Test status
Simulation time 2746292600 ps
CPU time 52.43 seconds
Started Oct 11 11:37:06 PM UTC 24
Finished Oct 11 11:38:12 PM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3639879395 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 75.prim_prince_test.3639879395
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/75.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/76.prim_prince_test.24161792
Short name T57
Test name
Test status
Simulation time 1024682711 ps
CPU time 20.2 seconds
Started Oct 11 11:37:06 PM UTC 24
Finished Oct 11 11:37:32 PM UTC 24
Peak memory 154984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=24161792 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 76.prim_prince_test.24161792
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/76.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/77.prim_prince_test.3317234548
Short name T97
Test name
Test status
Simulation time 3321844961 ps
CPU time 64.01 seconds
Started Oct 11 11:37:09 PM UTC 24
Finished Oct 11 11:38:30 PM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3317234548 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 77.prim_prince_test.3317234548
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/77.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/78.prim_prince_test.3788759930
Short name T100
Test name
Test status
Simulation time 3518438149 ps
CPU time 66.5 seconds
Started Oct 11 11:37:09 PM UTC 24
Finished Oct 11 11:38:33 PM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3788759930 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 78.prim_prince_test.3788759930
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/78.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/79.prim_prince_test.3749132361
Short name T106
Test name
Test status
Simulation time 3740174896 ps
CPU time 71.76 seconds
Started Oct 11 11:37:11 PM UTC 24
Finished Oct 11 11:38:42 PM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3749132361 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 79.prim_prince_test.3749132361
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/79.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/8.prim_prince_test.2108076570
Short name T2
Test name
Test status
Simulation time 775018238 ps
CPU time 15.86 seconds
Started Oct 11 11:35:49 PM UTC 24
Finished Oct 11 11:36:09 PM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2108076570 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 8.prim_prince_test.2108076570
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/8.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/80.prim_prince_test.339252336
Short name T56
Test name
Test status
Simulation time 762721515 ps
CPU time 15.26 seconds
Started Oct 11 11:37:11 PM UTC 24
Finished Oct 11 11:37:31 PM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=339252336 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 80.prim_prince_test.339252336
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/80.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/81.prim_prince_test.1751689049
Short name T69
Test name
Test status
Simulation time 1514888064 ps
CPU time 28.57 seconds
Started Oct 11 11:37:12 PM UTC 24
Finished Oct 11 11:37:49 PM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1751689049 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 81.prim_prince_test.1751689049
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/81.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/82.prim_prince_test.3060468369
Short name T98
Test name
Test status
Simulation time 3278524953 ps
CPU time 62.01 seconds
Started Oct 11 11:37:13 PM UTC 24
Finished Oct 11 11:38:32 PM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3060468369 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 82.prim_prince_test.3060468369
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/82.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/83.prim_prince_test.3845168437
Short name T105
Test name
Test status
Simulation time 3636831092 ps
CPU time 68.57 seconds
Started Oct 11 11:37:14 PM UTC 24
Finished Oct 11 11:38:41 PM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3845168437 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 83.prim_prince_test.3845168437
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/83.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/84.prim_prince_test.3173394944
Short name T92
Test name
Test status
Simulation time 2997868214 ps
CPU time 57.29 seconds
Started Oct 11 11:37:14 PM UTC 24
Finished Oct 11 11:38:27 PM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3173394944 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 84.prim_prince_test.3173394944
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/84.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/85.prim_prince_test.1386674998
Short name T96
Test name
Test status
Simulation time 3117220743 ps
CPU time 57.15 seconds
Started Oct 11 11:37:15 PM UTC 24
Finished Oct 11 11:38:29 PM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1386674998 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 85.prim_prince_test.1386674998
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/85.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/86.prim_prince_test.994794793
Short name T86
Test name
Test status
Simulation time 2520475314 ps
CPU time 49.1 seconds
Started Oct 11 11:37:16 PM UTC 24
Finished Oct 11 11:38:19 PM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=994794793 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 86.prim_prince_test.994794793
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/86.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/87.prim_prince_test.2095223028
Short name T80
Test name
Test status
Simulation time 2090882285 ps
CPU time 40.28 seconds
Started Oct 11 11:37:16 PM UTC 24
Finished Oct 11 11:38:08 PM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2095223028 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 87.prim_prince_test.2095223028
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/87.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/88.prim_prince_test.1192396597
Short name T90
Test name
Test status
Simulation time 2749529409 ps
CPU time 52.1 seconds
Started Oct 11 11:37:17 PM UTC 24
Finished Oct 11 11:38:24 PM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1192396597 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 88.prim_prince_test.1192396597
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/88.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/89.prim_prince_test.475813872
Short name T66
Test name
Test status
Simulation time 994996101 ps
CPU time 19.13 seconds
Started Oct 11 11:37:21 PM UTC 24
Finished Oct 11 11:37:46 PM UTC 24
Peak memory 154980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=475813872 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 89.prim_prince_test.475813872
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/89.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/9.prim_prince_test.1511318345
Short name T33
Test name
Test status
Simulation time 3019934626 ps
CPU time 57.87 seconds
Started Oct 11 11:35:49 PM UTC 24
Finished Oct 11 11:37:03 PM UTC 24
Peak memory 155044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1511318345 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 9.prim_prince_test.1511318345
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/9.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/90.prim_prince_test.4128143234
Short name T111
Test name
Test status
Simulation time 3404287655 ps
CPU time 65.6 seconds
Started Oct 11 11:37:25 PM UTC 24
Finished Oct 11 11:38:48 PM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4128143234 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 90.prim_prince_test.4128143234
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/90.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/91.prim_prince_test.1542827433
Short name T93
Test name
Test status
Simulation time 2553737485 ps
CPU time 49.43 seconds
Started Oct 11 11:37:25 PM UTC 24
Finished Oct 11 11:38:27 PM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1542827433 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 91.prim_prince_test.1542827433
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/91.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/92.prim_prince_test.1503458305
Short name T78
Test name
Test status
Simulation time 1676275499 ps
CPU time 32.33 seconds
Started Oct 11 11:37:25 PM UTC 24
Finished Oct 11 11:38:06 PM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1503458305 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 92.prim_prince_test.1503458305
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/92.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/93.prim_prince_test.3393287427
Short name T95
Test name
Test status
Simulation time 2650275065 ps
CPU time 48.74 seconds
Started Oct 11 11:37:26 PM UTC 24
Finished Oct 11 11:38:29 PM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3393287427 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 93.prim_prince_test.3393287427
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/93.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/94.prim_prince_test.3740917864
Short name T101
Test name
Test status
Simulation time 2762015193 ps
CPU time 53.22 seconds
Started Oct 11 11:37:26 PM UTC 24
Finished Oct 11 11:38:33 PM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3740917864 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 94.prim_prince_test.3740917864
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/94.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/95.prim_prince_test.1515063906
Short name T116
Test name
Test status
Simulation time 3421509805 ps
CPU time 65.51 seconds
Started Oct 11 11:37:27 PM UTC 24
Finished Oct 11 11:38:50 PM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1515063906 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 95.prim_prince_test.1515063906
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/95.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/96.prim_prince_test.2822797463
Short name T77
Test name
Test status
Simulation time 1321440333 ps
CPU time 24.82 seconds
Started Oct 11 11:37:32 PM UTC 24
Finished Oct 11 11:38:05 PM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2822797463 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 96.prim_prince_test.2822797463
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/96.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/97.prim_prince_test.4176802054
Short name T122
Test name
Test status
Simulation time 3357142095 ps
CPU time 64.3 seconds
Started Oct 11 11:37:33 PM UTC 24
Finished Oct 11 11:38:54 PM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4176802054 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 97.prim_prince_test.4176802054
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/97.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/98.prim_prince_test.2376637657
Short name T85
Test name
Test status
Simulation time 1837058950 ps
CPU time 34.64 seconds
Started Oct 11 11:37:33 PM UTC 24
Finished Oct 11 11:38:18 PM UTC 24
Peak memory 154972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2376637657 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 98.prim_prince_test.2376637657
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/98.prim_prince_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default/99.prim_prince_test.1715424335
Short name T94
Test name
Test status
Simulation time 2210519463 ps
CPU time 41.16 seconds
Started Oct 11 11:37:35 PM UTC 24
Finished Oct 11 11:38:29 PM UTC 24
Peak memory 155036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1715424335 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 99.prim_prince_test.1715424335
Directory /workspaces/repo/scratch/os_regression_2024_10_11/prim_prince-sim-vcs/99.prim_prince_test/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%